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mcm64e918 ? mcm64e836 1 motorola fast sram product preview 8mb double data rate hstl i/o fast sram the mcm64e918 / mcm64e836 are 8mbit pipelined burst synchronous late write fast static rams designed to provide very high data bandwidth in secondary cache applications. the mcm64e918 (organized as 512k words by 18 bits wide) and the mcm64e836 (organized as 256k words by 36 bits wide) are fabricated in motorola's high performance silicon gate mos technology. the differential clock (ck) inputs control the timing of read/write operations of the ram. at the rising edge of ck, all addresses and burst control inputs are registered. an internal buffer and special logic enables the memory to accept write data on the rising or rising and falling edges of the clock, a cycle following address and control signals. read data is driven on the rising or rising and falling edges of the ck clock and is referenced to echo clock (cq and cq ) outputs. the mcm64e918 / mcm64e836 have hstl inputs and outputs. the adjust- able input trippoint (v ref ) and output power supply voltage (v ddq ) gives the system designer greater flexibility in optimizing system performance. the impedance of the output buffers is programmable, allowing the outputs to match the impedance of the circuit traces, which reduces signal reflections. ? single 2.5 v 5% power supply ? single data rate (sdr) and double data rate (ddr) burst read and write ? pin selectable linear or interleaved burst order ? four tick burst with automatic wraparound ? differential clock inputs ? active high and active low echo clock outputs ? 1.8 v expanded hstl e i/o (jedec standard jesd86 class i compatible) ? 1.8 v expanded hstl e compatible programmable impedance output drivers ? pipelined (register to register) synchronous operation ? boundary scan (jtag) ieee 1149.1 compatible ? stop clock functionality supported ? optional x18 or x36 organization ? mcm64e918 / mcm64e8363.0 = 3.0 ns clock cycle time mcm64e918 / mcm64e8363.3 = 3.3 ns clock cycle time mcm64e918 / mcm64e8364.0 = 4.0 ns clock cycle time mcm64e918 / mcm64e8364.4 = 4.4 ns clock cycle time mcm64e918 / mcm64e8365.0 = 5.0 ns clock cycle time ? 9 x 17 (153) bump, 50 mil (1.27 mm) pitch, 14 mm x 22 mm flipped chip plastic ball grid array (pbga) or flipped chip ceramic ball grid array (cbga) packages this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. order this document by mc64e918/d semiconductor technical data mcm64e918 mcm64e836 fc package flipped chip pbga case 1107a01 rs package flipped chip cbga case 1107b01 8/25/99 ? motorola, inc. 1999
mcm64e918 ? mcm64e836 motorola fast sram 2 mcm64e918 top view 153bump 6 5 4 3 2 17 b c v dd g a d e f h j v ref v dd v ss ck b1 v dd v ref v dd v ddq sa zq sa sa g sa nc sa sa0 v ss sa sa sa v ddq sa sa v dd v ss v ss nc v ss nc dq v ss dq sa sa1 sa tck* v ss tms v ddq dq nc dq sa v ss lbo v dd v ss v dd v dd v ss v ddq v ss dq nc dq v ss v dd nc b3 v ss v ddq v ss nc dq nc v ss b2 dq v ss v dd v dd v dd v ss v ddq v ss nc dq v dd v dd v dd cq nc v dd v dd v dd v ss v ddq v ss dq nc v ss nc v ss sa v ss nc dq sa v ss sa k l m n p r t u v ss sa v ss v ss v ddq v dd pin assignments 89 dq dq v ss nc v ddq nc nc v ss v ss nc v ss nc dq v ss dq dq nc v ddq cq nc v ddq dq nc dq v ss nc v ss v ss v ddq v ddq v ddq v ddq nc v ss v ddq v ss ck v ss v ss v ddq v ss v ddq tdi tdo mcm64e836 top view 153bump 6 5 4 3 2 17 b c v dd g a d e f h j v ref v dd v ss ck b1 v dd v ref v dd v ddq sa zq sa sa g sa dq sa sa0 v ss sa sa sa v ddq sa sa v dd v ss v ss dq v ss dq dq v ss dq sa sa1 sa tck* v ss tms v ddq dq dq dq nc v ss lbo v dd v ss v dd v dd v ss v ddq v ss dq cq dq v ss v dd nc b3 v ss v ddq v ss dq dq dq v ss b2 dq v ss v dd v dd v dd v ss v ddq v ss dq dq v dd v dd v dd cq dq v dd v dd v dd v ss v ddq v ss dq dq v ss nc v ss sa v ss dq dq sa v ss sa k l m n p r t u v ss sa v ss v ss v ddq v dd 89 dq dq v ss dq v ddq nc dq v ss v ss dq v ss dq dq v ss dq dq dq v ddq cq dq v ddq dq cq dq v ss dq v ss v ss v ddq v ddq v ddq v ddq dq v ss v ddq v ss ck v ss v ss v ddq v ss v ddq tdi tdo * if jtag is not used, tck pin must be tied to v dd or v ss .
mcm64e918 ? mcm64e836 3 motorola fast sram mcm64e918 x18 pin descriptions pin locations symbol type description 5b b1 input synchronous function control input: b1 = 0 initiates a load new address. 5k b2 input synchronous function control input: b2 = 0 initiates a write, b2 = 1 initiates a read. 5l b3 input synchronous function control input: b3 = 0 initiates a double (or burst) operation, b3 = 1 initiates a single operation. 5g ck input address, data in, and control input register clock. active high. 5h ck input address, data in, and control input register clock. active low. 2f cq output echo clock output: active high. 8m cq output echo clock output: active low. 2b, 9b, 1d, 8d, 7f, 9f, 1h, 3h, 8h, 2k, 7k, 9k, 1m, 3m, 2p, 9p, 1t, 8t dq i/o synchronous data i/o. 5c g input output enable functionality not supported. must be tied to v ss or driven to v il max. 4l lbo input linear burst order: this is a mode pin. it must be tied to v dd or v ss before power up. lbo = 1 selects interleaved mode. lbo = 0 selects linear mode. 3a, 4a, 6a, 7a, 3b, 7b, 3c, 4c, 6c, 7c, 7d, 3p, 7p, 4r, 6r, 3t, 7t sa input synchronous address inputs: registered on the rising clock edge. 5r, 5t sa1, sa0 input synchronous burst counter preload address inputs: sa0 = lsb. 5u tck input jtag pin, test clock. if jtag is not used, tck must be tied to v ss or v dd . 4u tdi input jtag pin, test data in. 6u tdo output jtag, test data out. 3u tms jtag pin. 5a zq input output impedance programming input. 5e, 5n v ref supply input reference: provides reference voltage for input buffers. 5d, 4e, 6e, 4f, 5f, 6f, 4h, 6h, 4j, 5j, 6j, 4m, 5m, 6m, 4n, 6n, 5p, 3r, 7r v dd supply core power supply: these pins act as thermal vias to pcb power plane. 2a, 8a, 2c, 8c, 2e, 8e, 2g, 8g, 2j, 8j, 2l, 8l, 2n, 8n, 2r, 8r, 2u, 8u v ddq supply output power supply: provides operating power for output buffers. 1a, 9a, 4b, 6b, 1c, 9c, 4d, 6d, 1e, 3e, 7e, 9e, 1g, 3g, 4g, 6g, 7g, 9g, 1j, 3j, 7j, 9j, 4k, 6k, 1l, 3l, 7l, 9l, 1n, 3n, 7n, 9n, 4p, 6p, 1r, 9r, 4t, 6t, 1u, 9u v ss supply ground: these pins act as thermal vias to pcb ground plane. 1b, 8b, 2d, 3d, 9d, 1f, 3f, 8f, 2h, 7h, 9h, 1k, 3k, 8k, 6l, 2m, 7m, 9m, 1p, 8p, 2t, 9t, 7u nc e no connection: this means there is no connection to the chip.
mcm64e918 ? mcm64e836 motorola fast sram 4 mcm64e836 x36 pin descriptions pin locations symbol type description 5b b1 input synchronous function control input: b1 = 0 initiates a load new address. 5k b2 input synchronous function control input: b2 = 0 initiates a write, b2 = 1 initiates a read. 5l b3 input synchronous function control input: b3 = 0 initiates a double (or burst) operation, b3 = 1 initiates a single operation. 5g ck input address, data in, and control input register clock. active high. 5h ck input address, data in, and control input register clock. active low. 2f, 8f cq output echo clock output: active high. 2m, 8m cq output echo clock output: active low. 1b, 2b, 8b, 9b, 1d, 2d, 8d, 9d, 1f, 3f, 7f, 9f, 1h, 2h, 3h, 7h, 8h, 9h, 1k, 2k, 3k, 7k, 8k, 9k, 1m, 3m, 7m, 9m, 1p, 2p, 8p, 9p, 1t, 2t, 8t, 9t dq i/o synchronous data i/o. 5c g input output enable functionality not supported. must be tied to v ss or driven to v il max. 4l lbo input linear burst order: this is a mode pin. it must be tied to v dd or v ss before power up. lbo = 1 selects interleaved mode. lbo = 0 selects linear mode. 3a, 4a, 6a, 7a, 3b, 7b, 3c, 4c, 6c, 7c, 7d, 7p, 4r, 6r, 3t, 7t sa input synchronous address inputs: registered on the rising clock edge. 5r, 5t sa1, sa0 input synchronous burst counter preload address inputs: sa0 = lsb. 5u tck input jtag pin, test clock. if jtag is not used, tck must be tied to v ss or v dd . 4u tdi input jtag pin, test data in. 6u tdo output jtag, test data out. 3u tms jtag pin. 5a zq input output impedance programming input. 5e, 5n v ref supply input reference: provides reference voltage for input buffers. 5d, 4e, 6e, 4f, 5f, 6f, 4h, 6h, 4j, 5j, 6j, 4m, 5m, 6m, 4n, 6n, 5p, 3r, 7r v dd supply core power supply: these pins act as thermal vias to pcb power plane. 2a, 8a, 2c, 8c, 2e, 8e, 2g, 8g, 2j, 8j, 2l, 8l, 2n, 8n, 2r, 8r, 2u, 8u v ddq supply output power supply: provides operating power for output buffers. 1a, 9a, 4b, 6b, 1c, 9c, 4d, 6d, 1e, 3e, 7e, 9e, 1g, 3g, 4g, 6g, 7g, 9g, 1j, 3j, 7j, 9j, 4k, 6k, 1l, 3l, 7l, 9l, 1n, 3n, 7n, 9n, 4p, 6p, 1r, 9r, 4t, 6t, 1u, 9u v ss supply ground: these pins act as thermal vias to pcb ground plane. 3d, 6l, 3p, 7u nc e no connection: this means there is no connection to the chip.
mcm64e918 ? mcm64e836 5 motorola fast sram bus cycle state diagram read single write single read double write double advance address by one (see note 1) load new address deselect supply voltage provided b1 note: 1. advance internal address in accordance with burst order with wraparound. burstlength of four. advance address by one (see note 1) advance address by two (see note 1) advance address by two (see note 1) power up b1 b2, b3 b1 b2 , b3 b2, b3 b1 b2 , b3 b1 b1, b2 b1, b2 b1, b2 b1, b2 b1, b2 b1, b2 b1, b2 b1, b2 b1 threewire synchronous function controls (see notes 1 through 4) b1 b2 b3 function launched at next clock d q (n) q (n + 1) 0 0 1 write single, load new address next edge highz highz 0 0 0 write double, load new address both edges highz highz 0 1 1 read single, load new address highz next cq + edge next cq + edge 0 1 0 read double, load new address highz both cq edges both cq edges 1 1 x increment address, continue previous function x x x 1 0 x deselect, pipeline highz x x highz notes: 1. x = don't care. 2. deselect usage is discussed in the functional description section. 3. outputs will be in highz during power up, except cq and cq . 4. double reads and writes occur per burst sequence.
mcm64e918 ? mcm64e836 motorola fast sram 6 burst sequences interleaved burst add h binary address hex sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 start e base address 0 1 2 3 0 0 0 1 1 0 1 1 2nd address 1 0 3 2 0 1 0 0 1 1 1 0 3rd address 2 3 0 1 1 0 1 1 0 0 0 1 4th address 3 2 1 0 1 1 1 0 0 1 0 0 linear burst add h binary address hex sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 start e base address 0 1 2 3 0 0 0 1 1 0 1 1 2nd address 1 2 3 0 0 1 1 0 1 1 0 0 3rd address 2 3 0 1 1 0 1 1 0 0 0 1 4th address 3 0 1 2 1 1 0 0 0 1 1 0 absolute maximum ratings (see note) rating symbol value unit power supply voltage relative to v ss v dd 0.5 to 3.6 v output supply voltage v ddq 0.5 to 2.5 v voltage on any pin other than jtag v in 0.5 to 2.5 v voltage on any jtag pin v jtag 0.5 to 3.0 v input current (per i/o) i in 50 ma output current (per i/o) i out 25 ma operating temperature t a 0 to 70 c storage temperature t stg 55 to 125 c note: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. pbga package thermal characteristics rating symbol max unit notes junction to ambient (still air) r q ja 50 c/w 1, 2 junction to ambient (@200 ft/min) singlelayer board r q ja 39 c/w 1, 2 junction to ambient (@200 ft/min) fourlayer board r q ja 27 c/w 3 junction to board (bottom) r q jb 23 c/w 4 junction to case (top) r q jc 1 c/w 5 notes: 1. junction temperature is a function of onchip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per semi g3887. 3. measured using a fourlayer test board with two internal planes. 4. indicates the average thermal resistance between the die and the printed circuit board as measured by the ring cold plate method. 5. indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec883 method 1012.1). this device contains circuitry to protect the in- puts against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applica- tion of any voltage higher than maximum rated voltages to this highimpedance circuit. this cmos memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
mcm64e918 ? mcm64e836 7 motorola fast sram dc operating conditions and characteristics (2.375 v v dd 2.625 v, 0 c t a 70 c, unless otherwise noted) recommended operating conditions (see notes 1 through 4) parameter symbol min max 3.0 max 3.3 max 4.0 max 4.4 max 5.0 max unit notes core power supply voltage v dd 2.375 e e e e e 2.625 v output driver supply voltage v ddq 1.4 e e e e e 1.9 v ac supply current (device selected, all outputs open, freq = max, v dd = max, v ddq = max). includes supply currents for v dd . i dd1 e e 720 700 680 660 640 e ma 5 quiescent active power supply current (device selected, all outputs open, freq = 0, v dd = max, v ddq = max). includes supply currents for v dd . i dd2 e 200 200 200 200 200 e ma 6 active standby power supply current (device deselected, freq = max, v dd = max, v ddq = max) i sb1 e 225 220 210 205 200 e ma 7 stop clock current (device deselected, freq = 0, v dd = max, v ddq = max, all inputs static at cmos levels) i sb2 e 200 200 200 200 200 e ma 6, 7 input reference dc voltage v ref (dc) 0.6 e e e e e 1.3 v 8 notes: 1. all data sheet parameters specified to full range of v dd unless otherwise noted. all voltages are referenced to voltage applied to v ss bumps. 2. supply voltage applied to v dd connections. 3. supply voltage applied to v ddq connections. 4. all power supply currents measured with outputs open or deselected. 5. all inputs are toggling per cmos i/o levels (see note 6). 6. input levels for i/os are v ss v in 0.2 v or v ddq 0.2 v v in v ddq . 7. device deselected as defined by the truth table. 8. although considerable latitude in the selection of the nominal dc value (i.e., rms value) of v ref is supported, the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref .
mcm64e918 ? mcm64e836 motorola fast sram 8 dc characteristics and power supply currents (see notes 1 and 2) parameter symbol min typ max unit dc input logic high v ih (dc) v ref + 0.1 e v ddq + 0.3 v dc input logic low v il (dc) 0.5 e v ref 0.1 v input leakage current (all inputs, v in = 0 to v ddq ) i lkg(i) e e 5 m a output low current (v ol = v ddq /2) i ol (v ddq /2) / [(rq/5) + 10%] e (v ddq /2) / [(rq/5) 10%] v output high current (v oh = v ddq /2) i oh (v ddq /2) / [(rq/5) + 10%] e (v ddq /2) / [(rq/5) 10%] v light load output logic low i ol 100 m a v ol1 v ss e 0.2 v light load output logic high ? i oh ? 100 m a v oh1 v ddq 0.2 e v ddq v clock input signal voltage v in 0.3 e v ddq + 0.3 v clock input differential voltage (see figure 2) v dif (dc) 0.1 e v ddq + 0.6 v clock input common mode voltage range (see figure 2) v cm (dc) 0.6 e 1.3 v notes: 1. the impedance controlled mode is expected to be used in pointtopoint applications, driving highimpedance inputs. 2. the zq pin is connected through rq to v ss for the controlled impedance mode. capacitance (f = 1.0 mhz, dv = 3.0 v, 0 c t a 70 c, periodically sampled rather than 100% tested) characteristic symbol typ max unit input capacitance all inputs except clocks and dqs g and w c in c ck 3.2 3.7 5 5 pf i/o capacitance dq c i/o 3.8 6 pf
mcm64e918 ? mcm64e836 9 motorola fast sram ac operating conditions and characteristics (2.375 v v dd 2.625 v, 1.4 v v ddq 1.9 v, unless otherwise noted) input pulse levels 0.25 v to 1.25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 1 v/ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . . . input timing measurement reference level v ddq /2 . . . . . . . . . . . . . output timing measurement reference level v ddq /2 . . . . . . . . . . . output load differential crosspoint . . . . . . . . . . . . . . . . . . . . . . . . . . r q ja device tbd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . read and write cycle timing p sbl 64e9183.0 64e8363.0 64e9183.3 64e8363.3 64e9184.0 64e8364.0 64e9184.4 64e8364.4 64e9185.0 64e8365.0 ui n parameter symbol min max min max min max min max min max unit notes cycle time t khkh 3 e 3.3 e 4 e 4.4 e 5 e ns ck clock high pulse width t khkl 1.2 e 1.3 e 1.6 e 1.8 e 2 e ns ck clock low pulse width t klkh 1.2 e 1.3 e 1.6 e 1.8 e 2 e ns cq low to cq high t clch t klkh 100 ps t klkh + 100 ps t klkh 100 ps t klkh + 100 ps t klkh 100 ps t klkh + 100 ps t klkh 100 ps t klkh + 100 ps t klkh 100 ps t klkh + 100 ps cq high to cq low t chcl t khkl 100 ps t khkl + 100 ps t khkl 100 ps t khkl + 100 ps t khkl 100 ps t khkl + 100 ps t khkl 100 ps t khkl + 100 ps t khkl 100 ps t khkl + 100 ps setup times: address valid to ck crossing burst control valid to ck crossing data in valid to ck crossing t avkh t bvkh t dvkx 0.5 0.5 0.3 e e e 0.5 0.5 0.3 e e e 0.5 0.5 0.3 e e e 0.5 0.5 0.3 e e e 0.5 0.5 0.3 e e e ns 1 hold times: ck crossing to address don't care ck crossing to burst control don't care ck crossing to data in don't care t khax t khbx t kxdx 0.5 0.5 0.3 e e e 0.5 0.5 0.3 e e e 0.5 0.5 0.3 e e e 0.5 0.5 0.3 e e e 0.5 0.5 0.3 e e e ns 1 ck crossing to cq high t kxch 0.7 1.5 0.7 1.65 0.7 2 0.7 2.2 0.7 2.5 ns ck crossing to cq low t kxcl 0.7 1.5 0.7 1.65 0.7 2 0.7 2.2 0.7 2.5 ns cq high to output valid t chqv e 0.20 e 0.20 e 0.20 e 0.20 e 0.20 ns 1 cq low to output valid t clqv e 0.20 e 0.20 e 0.20 e 0.20 e 0.20 ns 1 cq high to output hold t chqx 0.20 e 0.20 e 0.20 e 0.20 e 0.20 e ns 1, 2 cq low to output hold t clqx 0.20 e 0.20 e 0.20 e 0.20 e 0.20 e ns 1, 2 ck high to output lowz t khqx1 0.5 e 0.5 e 0.5 e 0.5 e 0.5 e ns 2, 3 cq high to output highz t chqz 0.20 0.25 0.20 0.3 0.20 0.35 0.20 0.35 0.20 0.35 ns 2, 4 notes: 1. guaranteed by design and characterization. 2. this parameter sampled and not 100% tested. 3. measured at 200 mv from steady state. 4. measured at 200 mv from steady state. see figure 1b.
mcm64e918 ? mcm64e836 motorola fast sram 10 device under test zq 50 w 50 w 0.75 v 0.75 v v ref 250 w figure 1. test loads 50 w 50 w 0.75 v 0.75 v 50 w 50 w 5 pf 5 pf 16.7 w dq 16.7 w 16.7 w 0.75 v (a) test load (b) test load ac input characteristics (see notes 1 through 3) parameter symbol min max notes ac input logic high (see figure 2) v ih (ac) v ref + 200 mv e ac input logic low (see figure 3) v il (ac) e v ref 200 mv input reference peaktopeak ac voltage v ref (ac) e 5% v ref (dc) 4 clock input differential voltage v dif (ac) 400 mv v ddq + 600 mv notes: 1. inputs may undershoot to v ss 1 v (peak) for up to 35% t khkh or 1.0 ns, whichever is smaller, and v ss 1.5 v instantaneous peak undershoot. 2. inputs may overshoot to 3.3 v for up to 35% t khkh or 1.0 ns, whichever is smaller, and 3.6 v instantaneous peak overshoot. 3. minimum instantaneous differential input voltage required for differential input clock operation. 4. although considerable latitude in the selection of the nominal dc value (i.e., rms value) of v ref is supported, the peaktopeak ac compo- nent superimposed on v ref may not exceed 5% of the dc component of v ref . crossing point v ddq v ss v tr v dif v cp v cm * figure 2. differential inputs/common mode input voltage *v cm , the common mode input voltage, equals v tr [(v tr v cp )/2].
mcm64e918 ? mcm64e836 11 motorola fast sram v ih v ss 0.5 v 35% t khkh figure 3. undershoot voltage v ih (ac) v ref v il (ac) figure 4. differential inputs/common mode input voltage
mcm64e918 ? mcm64e836 motorola fast sram 12 functional description using deselect function control pins b1:b2 set to 1:0 will be latched on a rising edge of the input clock (ck), and launch a deselect at the next ck clock (pipelined). deselect puts the data bus into a highimpedance state. deselect can be used to avoid bus contention by putting the data bus into a highimpedance state before performing a write. the sequence for switching from a read to a write should be: read, deselect, write. coherency this part is fully coherent. this means that when a write is performed at an address, and a read of that same address follows immediately, the data just written is read back. bursting function control pins are used to select single or double reads and writes. when a double read or write is selected, the data is managed on both the rising and falling edges of the echo clock, which is the double data rate feature of this fsram. all burst sequences are determined with the lbo pin per the burst sequence table. function control pins b1:b2 set to 1:1 increments the address and continues the previous function. this com- bination of b1:b2 can immediately follow any of the other read or write functions. as long as the b1:b2 pins are set to 1:1 on rising edges of the input clock, a continuous read or write from sequential addresses can be performed without having to resupply the address (refer to the bus cycle state diagram and threewire synchronous function control table). reads/writes the ddr latches address and control lines on the rising edge of the input (ck) clock. single reads are selected by setting function control lines b1:b2:b3 = 0:1:1. this functionality resembles the nonburst read timing of a pipelined burstram (preddr). only 1 byte of data will result from each address and control clocked into the part. data changes only on the rising edge of the clock. double reads are selected by setting b1:b2:b3 = 0:1:0. this will cause a burst of two, but at twice the input clock rate. data is available after the rising and the falling clock edges of the output clock (refer to the double and single read timing diagram). single writes have late write functionality. single writes are selected with b1:b2:b3 = 0:0:1. data in must meet setup and hold times with respect to the rising edge of the input clock, ck. double writes are also late writes. double writes are selected with b1:b2:b3 = 0:0:0. the data rate is twice the applied clock in a double write, so data in must meet setup and hold times with respect to the rising and falling edges of the input clock, ck. echo clock this part is equipped with an echo clock. the echo clock is an output clock that aids in the synchronization of data. after power up, the echo clock is free running. the data that is out- put during a read cycle is referenced to the echo clock out- puts. startup conditions/stop clock power up conditions are expected to vary from application to application. echo clocks (cq and cq ) are not pipelined, and will respond to the input clock (ck) immediately. one way to design for this situation is to power up and start the ddr, run until all signals are transitioning smoothly, and then stop the clock and start it again, using the echo clock edges after the stop clock and not before the stop clock. this will allow for synchronization of the echo clock. the stop clock can be used anywhere as long as the minimum and maxi- mum clock pulse specifications are not violated. output impedance circuitry the designer can program the rams output buffer imped- ance by terminating the zq pin to v ss through a precision resistor (rq). the value of rq is five times the output imped- ance desired. for example, a 250 w resistor will give an out- put impedance of 50 w . impedance updates occur during write and deselect cycles. the actual change in the impedance occurs in small incre- ments and is binary. the binary impedance has 256 values and therefore, there are no significant disturbances that occur on the output because of this smooth update method. at power up, the output impedance will take up to 65,000 cycles for the impedance to be completely updated.
mcm64e918 ? mcm64e836 13 motorola fast sram ck sa dq t khkh function control cq t avkh a b ck t khax cq a1 t khkl t klkh t kxch (min/max) t khbx a2 b t kxcl (min/max) t chqx (min) t chqv (max) t clqx (min) t clqv (max) t clqx (max) double and single read timing read read highz x b1 , b2, b3 b1 , b2, b3 b1, b2 , x x x t bvkh ck sa dq function control cq f x ck cq f1 f2 t dvkx double write timing write write continue burst f3 f4 t kxdx b1 , b2 , b3 b1, b2, x b1, b2 , x highz xx x
mcm64e918 ? mcm64e836 motorola fast sram 14 ck sa dq function control cq f x ck cq f1 t dvkx single write timing write write continue burst f2 b1 , b2 , b3 b1, b2, x b1, b2 , x xx x highz t khdx
mcm64e918 ? mcm64e836 15 motorola fast sram ck sa dq function control cq c d ck cq c1 c2 t dvkx write and read timing write write d1 d2 t kxdx read read continue burst highz ex b1, b2 , x e1 e2 e3 e4 b1 , b2 , b3 b1 , b2 , b3 b1 , b2, b3 b1, b2, x x ck sa dq function control cq c x ck cq t dvkx read and write timing read highz t kxdx write write continue burst highz ex b1, b2 , x e4 b1 , b2, b3 b1, b2 , x b1 , b2 , b3 b1, b2, x e3 e2 e1 c1 c2 x
mcm64e918 ? mcm64e836 motorola fast sram 16 serial boundary scan test access port operation overview the serial boundary scan test access port (tap) on this ram is designed to operate in a manner consistent with ieee standard 1149.11990 (commonly referred to as jtag), but does not implement all of the functions required for ieee 1149.1 compliance. certain functions have been modified or eliminated because their implementation places extra delays in the rams critical speed path. nevertheless, the ram supports the standard tap controller architecture (the tap controller is the state machine that controls the taps operation) and can be expected to function in a manner that does not conflict with the operation of devices with ieee 1149.1 compliant taps. the tap operates using conven- tional jedec standard 85 (2.5 v) logic level signaling. disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude midlevel inputs. tdi and tms are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a 1 k resistor. tdo should be left uncon- nected. tap dc operating characteristics (2.375 v v dd 2.625 v, 0 c t a 70 c, unless otherwise noted) parameter symbol min max unit notes logic input logic high v ih 1 1.2 v dd + 0.3 v logic input logic low v il 1 0.3 0.4 v logic input leakage current i lkg e 5 m a 1 cmos output logic low v ol 1 e 0.2 v 2 cmos output logic high v oh 1 v ddq 0.2 e v 3 notes: 1. 0 v v in v dd for all logic input pins. 2. i ol 1 100 m a @ v ol = 0.2 v. sampled, not 100% tested. 3. ? i oh 1 ? 100 m a @ v ddq 0.2 v. sampled, not 100% tested.
mcm64e918 ? mcm64e836 17 motorola fast sram tap ac operating conditions and characteristics (0 c t a 70 c, unless otherwise noted) input pulse levels 0 to 2.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 1 v/ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . . . input timing measurement reference level 1.1 v . . . . . . . . . . . . . . . output timing reference level 1.1 v . . . . . . . . . . . . . . . . . . . . . . . . . . output test load 50 w parallel terminated tline with 20 pf . . . . . receiver input capacitance test load termination supply voltage (v t ) 1.1 v . . . . . . . . . . . . . . . tap controller timing parameter symbol min max unit notes cycle time t thth 100 e ns clock high time t thtl 40 e ns clock low time t tlth 40 e ns tms setup t mvth 10 e ns tms hold t thmx 10 e ns tdi valid to tck high t dvth 10 e ns tck high to tdi don't care t thdx 10 e ns capture setup t cs 10 e ns 1 capture hold t ch 10 e ns 1 tck low to tdo unknown t tlqx 0 e ns tck low to tdo valid t tlov e 20 ns note: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure accurate pad data capture. ac test load device under test 50 w 50 w 1.1 v 20 pf t thdx t tlqv t tlqx t dvth t tlth t thmx t mvth tap controller timing diagram t thth test clock (tck) test mode select (tms) test data in (tdi) test data out (tdo) t thtl
mcm64e918 ? mcm64e836 motorola fast sram 18 test access port pins tck e test clock (input) clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms e test mode select (input) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a logic 1 input level. tdi e test data in (input) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is deter- mined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to figure 6). an undriven tdi pin will produce the same result as a logic 1 input level. tdo e test data out (output) output that is active depending on the state of the tap state machine (refer to figure 6). output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. trst e tap reset this device does not have a trst pin. trst is optional in ieee 1149.1. the testlogic reset state is entered while tms is held high for five rising edges of tck. power on reset cir- cuitry is included internally. this type of reset does not affect the operation of the system logic. the reset affects test logic only. test access port registers overview the various tap registers are selected (one at a time) via the sequences of 1s and 0s input to the tms pin as the tck is strobed. each of the tap registers are serial shift registers that capture serial input data on the rising edge of tck and push serial data out on subsequent falling edge of tck. when a register is selected, it is aplacedo between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run test/idle or the various data register states. the instructions are 3 bits long. the register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power up or whenever the controller is placed in testlogic reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the rams tap to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is identical in length to the number of active input and i/o connections on the ram (not counting the tap pins). this also includes a number of place holder locations (always set to a logic 1) reserved for density upgrade address pins. there are a total of 68 bits in the case of the x36 device and 49 bits in the case of the x18 device. the boundary scan register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capturedr state and then is placed between the tdi and tdo pins when the controller is moved to shiftdr state. several tap instructions can be used to activate the boundary scan register. the bump/bit scan order tables describe which device bump connects to each boundary scan register location. the first column defines the bit's position in the boundary scan register. the shift register bit nearest tdo (i.e., first to be shifted out) is defined as bit 1. the second column is the name of the input or i/o at the bump and the third column is the bump number. identification (id) register the id register is a 32bit register that is loaded with a device and vendor specific 32bit code when the controller is put in capturedr state with the idcode command loaded in the instruction register. the code is loaded from a 32bit onchip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shiftdr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register presence indicator bit no. 0 value 1 motorola jedec id code (compressed format, per ieee standard 1149.11990 bit no. 11 10 9 8 7 6 5 4 3 2 1 value 0 0 0 0 0 0 0 1 1 1 0 reserved for future use bit no. 17 16 15 14 13 12 value x x x x x x device width configuration bit no. 22 21 20 19 18 256k x 36 value 0 0 1 0 0 512k x 18 value 0 0 0 1 1 device depth configuration bit no. 27 26 25 24 23 256k x 36 value 0 0 1 1 0 512k x 18 value 0 0 1 1 1 revision number bit no. 31 30 29 28 value x x x x figure 5. id register bit meanings
mcm64e918 ? mcm64e836 19 motorola fast sram mcm64e918 x18 boundary scan order bit signal bump bit signal bump bit no. signal name bump id bit no. signal name bump id 1 sa1 5r 36 dq 1h 2 sa0 5t 37 zq 5a 3 sa 6r 38 b1 5b 4 sa 7t 39 b2 5k 5 sa 7p 40 b3 5l 6 dq 8t 41 lbo 4l 7 dq 9p 42 dq 2k 8 cq 8m 43 dq 1m 9 dq 7k 44 dq 3m 10 dq 9k 45 dq 2p 11 nc 1, 2 6l 46 dq 1t 12 ck 5h 47 sa 3p 13 ck 5g 48 sa 3t 14 g 5c 49 sa 4r 15 dq 8h 16 dq 9f 17 dq 7f 18 dq 8d 19 dq 9b 20 sa 7d 21 sa 7c 22 sa 7b 23 sa 7a 24 sa 6c 25 sa 6a 26 sa 4a 27 sa 4c 28 sa 3a 29 sa 3b 30 sa 3c 31 nc 1, 3 3d 32 dq 2b 33 dq 1d 34 cq 2f 35 dq 3h mcm64e836 x36 boundary scan order bit signal bump bit signal bump bit no. signal name bump id bit no. signal name bump id 1 sa1 5r 36 sa 4a 2 sa0 5t 37 sa 4c 3 sa 6r 38 sa 3a 4 sa 7t 39 sa 3b 5 sa 7p 40 sa 3c 6 dq 8t 41 nc 1, 3 3d 7 dq 9t 42 dq 2b 8 dq 8p 43 dq 1b 9 dq 7m 44 dq 2d 10 dq 9p 45 dq 3f 11 cq 8m 46 dq 1d 12 dq 9m 47 cq 2f 13 dq 7k 48 dq 1f 14 dq 8k 49 dq 3h 15 dq 9k 50 dq 2h 16 nc 1, 2 6l 51 dq 1h 17 ck 5h 52 zq 5a 18 ck 5g 53 b1 5b 19 g 5c 54 b2 5k 20 dq 9h 55 b3 5l 21 dq 8h 56 lbo 4l 22 dq 7h 57 dq 1k 23 dq 9f 58 dq 2k 24 cq 8f 59 dq 3k 25 dq 9d 60 dq 1m 26 dq 7f 61 cq 2m 27 dq 8d 62 dq 1p 28 dq 9b 63 dq 3m 29 dq 8b 64 dq 2p 30 sa 7d 65 dq 1t 31 sa 7c 66 dq 2t 32 sa 7b 67 sa 3t 33 sa 7a 68 sa 4r 34 sa 6c 35 sa 6a notes: 1. nc pads are place holder bits and are true noconnects. when reading out the boundary scan register, these bits are forced high. 2. place holder for mode pin. 3. placeholder for 16m ddr.
mcm64e918 ? mcm64e836 motorola fast sram 20 tap controller instruction set overview there are two classes of instructions defined in the ieee standard 1149.11990; the standard (public) instructions and device specific (private) instructions. some public instructions are mandatory for ieee 1149.1 compliance. optional public instructions must be implemented in pre- scribed ways. although the tap controller in this device follows the ieee 1149.1 conventions, it is not ieee 1149.1 compliant because some of the mandatory instructions are not fully imple- mented. the tap on this device may be used to monitor all input and i/o pads, but can not be used to load address, data, or control signals into the ram or to preload the i/o buffers. in other words, the device will not perform ieee 1149.1 extest, intest, or the preload portion of the sample/preload command. when the tap controller is placed in captureir state, the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shiftir state, the instruction register is placed between tdi and tdo. in this state, the desired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to updateir state. the tap instruction sets for this device are listed in the following tables. standard (public) instructions bypass the bypass instruction is loaded in the instruction regis- ter when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shiftdr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is an ieee 1149.1 mandatory public instruction. when the sample/preload instruction is loaded in the instruction register, moving the tap controller into the capturedr state loads the data in the rams input and i/o buffers into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck), it is possible for the tap to attempt to capture the i/o ring con- tents while the input buffers are in transition (i.e., in a metast- able state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results can not be expected. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shiftdr state then places the boundary scan register between the tdi and tdo pins. because the preload portion of the command is not implemented in this device, moving the controller to the updatedr state with the sample/preload instruction loaded in the instruction register, has the same effect as the pausedr command. this functionality is not ieee 1149.1 compliant. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. extest is not implemented in this device. therefore, this device is not ieee 1149.1 compliant. nevertheless, this rams tap does respond to an all 0s instruction, as follows. with the extest (000) instruction loaded in the instruction register, the ram responds just as it does in response to the sample/preload instruction described above, except the dq pins are forced to highz (cq pins are not) any time the instruction is loaded. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capturedr mode and places the id register between the tdi and tdo pins in shiftdr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the testlogicreset state. device specific (public) instruction samplez if the samplez instruction is loaded in the instruction register, all dq pins are forced to an inactive drive state (highz) and the boundary scan register is connected be- tween tdi and tdo when the tap controller is moved to the shiftdr state. device specific (private) instruction no op do not use these instructions; they are reserved for future use.
mcm64e918 ? mcm64e836 21 motorola fast sram standard (public) instruction codes instruction code* description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all dq pins to highz state. not ieee 1149.1 compliant. idcode 001** preloads id register and places it between tdi and tdo. does not affect ram operation. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect ram operation. does not implement ieee 1149.1 preload function. not ieee 1149.1 compliant. bypass 111 places bypass register between tdi and tdo. does not affect ram operation. samplez 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all dq pins to highz state. * instruction codes expressed in binary; msb on left, lsb on right. ** default instruction automatically loaded at powerup and in testlogicreset state. standard (private) instruction codes instruction code* description no op 011 do not use these instructions; they are reserved for future use. no op 101 do not use these instructions; they are reserved for future use. no op 110 do not use these instructions; they are reserved for future use. * instruction codes expressed in binary; msb on left, lsb on right. capturedr exit1dr exit2dr updatedr captureir exit1ir exit2ir updateir shiftir pauseir shiftdr pausedr testlogic reset runtest/ idle select drscan select irscan 1 1 1 1 1 1 1 11 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: the value adjacent to each state transition represents the signal present at tms at the rising edge of tck. 0 figure 6. tap controller state diagram 0 1
mcm64e918 ? mcm64e836 motorola fast sram 22 motorola powerpc prefix part number full part numbers e mcm64e918fc3.0 mcm64e918fc3.0r mcm64e836fc3.0 mcm64e836fc3.0r mcm64e918fc3.3 mcm64e918fc3.3r mcm64e836fc3.3 mcm64e836fc3.3r mcm64e918fc4.0 mcm64e918fc4.0r mcm64e836fc4.0 mcm64e836fc4.0r mcm64e918fc4.4 mcm64e918fc4.4r mcm64e836fc4.4 mcm64e836fc4.4r mcm64e918fc5.0 mcm64e918fc5.0r mcm64e836fc5.0 mcm64e836fc5.0r speed (3.0 = 3.0 ns, 3.3 = 3.3 ns, 4.0 = 4.0 ns, 4.4 = 4.4 ns, 5.0 = 5.0 ns) package (fc = flipped chip pbga, rs = flipped chip cbga) 64e918 mcm 64e836 fc x x shipping method (r = tape and reel, blank = rails) ordering information (order by full part number) mcm64e918rs3.0 mcm64e918rs3.0r mcm64e836rs3.0 mcm64e836rs3.0r mcm64e918rs3.3 mcm64e918rs3.3r mcm64e836rs3.3 mcm64e836rs3.3r mcm64e918rs4.0 mcm64e918rs4.0r mcm64e836rs4.0 mcm64e836rs4.0r mcm64e918rs4.4 mcm64e918rs4.4r mcm64e836rs4.4 mcm64e836rs4.4r mcm64e918rs5.0 mcm64e918rs5.0r mcm64e836rs5.0 mcm64e836rs5.0r
mcm64e918 ? mcm64e836 23 motorola fast sram package dimensions fc package 153bump flipped chip pbga case 1107a01 a b c d e f g h j k l m n p r t u 153x bottom view d 0.2 7 6 5 4 3 2 1 b 0.15 a e e2 d2 c b e 0.3 a bc pin a1 index 4x top view 16x m m e 8x e1 d1 3 a seating side view plane a1 a2 a3 a4 0.2 a 0.35 a 0.25 a notes: 1. dimensioning and tolerancing per asme y14.5m,1992. 2. all dimensions in millimeters. 3. dimension b is the maximum solder ball diameter measured parallel to datum plane a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. 5. d2 and e2 define the area occupied by the die. d3 and e3 are the minimum clearance from the package edge to the chip capacitors. 6. capacitors may not be present on all devices. 7. caution must be taken not to short exposed metal capacitor pads on package top. dim min max millimeters a 2.77 a1 0.50 0.70 a2 1.75 2.07 a3 0.80 0.92 a4 0.92 1.15 d 22.00 bsc d1 20.32 bsc d2 11.60 11.90 e 14.00 bsc e1 7.62 bsc e2 6.80 6.11 b 0.60 0.90 e 1.27 bsc a 153x 9 8
mcm64e918 ? mcm64e836 motorola fast sram 24 rs package 153bump flipped chip cbga case 1107b01 a b c d e f g h j k l m n p r t u 153x bottom view d 0.2 7 6 5 4 3 2 1 b 0.15 a e e2 d2 c b e 0.3 a bc pin a1 index 4x top view 16x m m e 8x e1 d1 3 a seating side view plane a1 a2 a3 a4 0.15 a 0.35 a 0.25 a notes: 1. dimensioning and tolerancing per asme y14.5m,1992. 2. all dimensions in millimeters. 3. dimension b is the maximum solder ball diameter measured parallel to datum plane a. 4. datum a, the seating plane, is defined by the spherical crowns of the solder balls. 5. d2 and e2 define the area occupied by the die. d3 is the minimum clearance from the package edge to the chip capacitors. 6. capacitors may not be present on all devices. 7. caution must be taken not to short exposed metal capacitor pads on package top. dim min max millimeters a 3.02 a1 0.80 1.00 a2 1.70 2.02 a3 0.80 0.92 a4 0.90 1.10 d 22.00 bsc d1 20.32 bsc d2 11.60 11.90 e 14.00 bsc e1 7.62 bsc e2 6.80 6.11 b 0.82 0.93 e 1.27 bsc a 153x 9 8 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed: motorola literature distribution; japan : motorola japan ltd.; sps, technical information center, p.o. box 5405, denver, colorado, 80217. 1-303-675-2140 or 1-800-441-2447 3201, minamiazabu. minatoku, tokyo 1068573 japan. 81334403569 mfax ? : rmfax0@email.sps.mot.com t ouchtone 1-602-244-6609 asia / pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, motorola fax back system us & c anada only 1-800-774-1848 2 dai king street, tai po industrial estate, tao po, n.t., hong kong. http ://sps.motorola.com /mfax / 852-26668334 home page : http ://motorola.com/sps / customer focus center: 1-800-521-6274 mcm64e918/d ?

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