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CYRF89235 proc? usb cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-77748 rev. *f revised may 15, 2013 proc? usb proc-usb features single device, two functions ? 8-bit, flash based usb peripher al mcu function and 2.4-ghz radio transceiver function in a single device rf attributes ? fully integrated 2.4-ghz radio on a chip ? 1-mbps over-the-air data rate ? transmit power typical: 0 dbm ? receive sensitivity typical: ?87 dbm ? 1 a typical current cons umption in sleep state ? closed-loop frequency synthesis ? supports frequency-hopping spread spectrum ? on-chip packet framer with 64-byte first in first out (fifo) data buffer ? built-in auto-retry-acknowledge protocol simplifies usage ? built-in cyclic redundancy check (crc), forward error correction (fec), data whitening ? supports dc ~ 12-mhz spi bus interface ? additional outputs for interrupt request (irq) generation ? digital readout of received signal strength indication (rssi) mcu attributes ? powerful harvard-architecture processor ? m8c processor speeds running up to 24 mhz ? low power at high processing speeds ? interrupt controller ? 1.9 v to 3.6v operating voltage without usb ? operating voltage with usb enabled: ? 3.15 v to 3.45 v when supply voltage is around 3.3 v ? commercial temperature range: 0c to +70c flexible on-chip memory ? 32 kb flash program storage: ? 50,000 erase and write cycles ? flexible protection modes ? up to 2048 bytes sram data storage ? in-system serial programming (issp) complete development tools ? free development tool psoc designer? ? full-featured, in-circuit emulator and programmer ? full-speed emulation ? complex breakpoint structure ? 128-kb trace memory precision, programmable clocking ? crystal-less oscillator with support for an external crystal or resonator ? internal 5.0% 6, 12, or 24 mhz main oscillator (imo): ? 0.25% accuracy with oscillator lock to usb data, no external components required ? internal low-speed oscillator (ilo) at 32 khz for watchdog and sleep. the frequency range is 19 to 50 khz with a 32-khz typical value programmable pin configurations. ? up to 13 general-purpose i/os (gpios) ? 25 ma sink current on all gpio ? 60 ma total sink current on even port pins and 60 ma total sink current on odd port pins ? 120 ma total sink current on all gpios ? pull-up, high z, open drain, cmos drive modes on all gpio ? cmos drive mode a ?5 ma source current on ports 0 and 1 and 1 ma on port 2 ? 20 ma total source current on all gpios ? low dropout voltage regulator for port 1 pins: ? programmable to output 3.0, 2.5, or 1.8 v ? selectable, regulated digital i/o on port 1 ? configurable input threshold for port 1 ? hot-swappable capability on port 1 full-speed usb (12 mbps) ? eight unidirectional endpoints ? one bidirectional control endpoint ? usb 2.0-compliant ? dedicated 512 bytes buffer ? no external crystal required additional system resources ? configurable communication speeds ? i 2 c slave: ? selectable to 50 khz, 100 khz, or 400 khz ? implementation requires no clock stretching ? implementation during sleep modes with less than 100 ? a ? hardware address detection ? spi master and spi slave: ? configurable between 46.9 khz and 12 mhz ? three 16-bit timers ? 10-bit adc used to monitor ba ttery voltage or other signals with external components ? watchdog and sleep timers ? integrated supervisory circuit
CYRF89235 document number: 001-77748 rev. *f page 2 of 45 proc-usb logical block diagram system bus 6/12/24 mhz internal main oscillator cpu core (m8c) srom 32k flash system resources i2c slave/spi master-slave por and lvd system resets port 1 port 0 sleep and watchdog full speed usb port 2 prog. ldo sram 2048 bytes interrupt controller encore v core 3 16-bit timers adc rst_n fifo pkt xtalo synthesizer brclk xtali v out v dd_io v in ant xtal osc x vco lna + bpf gfsk modulator ldo linear regulator pa image rej . mxr. spi registers framer antb receive gfsk demodulator pwr/ reset wirelessusb nl system
CYRF89235 document number: 001-77748 rev. *f page 3 of 45 contents functional overview ........................................................ 4 the encore v core .................................................... 4 full-speed usb ........................................................... 4 10-bit adc ................................................................... 5 spi ............................................................................... 5 i2c slave ..................................................................... 6 wirelessusb-nl subsystem .. .............. .............. ......... 7 transmit power control ............................................... 7 power-on and register initialization sequence ........... 7 additional system resources ..................................... 8 getting started .................................................................. 8 application notes ........................................................ 8 development kits ........................................................ 8 training ....................................................................... 8 cypros consultants .................................................... 8 solutions library .......................................................... 8 technical support ....................................................... 8 development tools .......................................................... 9 psoc designer software subsyst ems .......... .............. 9 designing with psoc designer ..................................... 10 select user modules ................................................. 10 configure user modules ............................................ 10 organize and connect .............. .............. ........... ....... 10 generate, verify, and debug ..................................... 10 pin configuration ........................................................... 11 pin definitions ................................................................ 12 register reference ......................................................... 13 register conventions ................................................ 13 register mapping tables .......................................... 13 electrical specifications ................................................ 16 absolute maximum ratings .... ................................... 16 operating temperature ............................................. 16 dc chip-level specifications .................................... 17 dc usb interface specifications ............................... 18 adc electrical specifications .................................... 19 dc analog mux bus specifications ........................... 20 dc low power comparator sp ecifications ............... 20 comparator user module electrical specifications ... 20 dc gpio specifications ............................................ 21 dc por and lvd specifications .............................. 23 dc programming specifications ............................... 24 dc i2c specifications ........ ....................................... 25 dc reference buffer specificat ions .......................... 25 dc idac specifications ............................................ 25 ac chip level specifications .................................... 26 ac usb data timings specifications ........................ 27 ac usb driver specifications ................................... 27 ac general purpose i/o specifications .................... 28 ac comparator specifications .................................. 29 ac external clock specifications .............................. 29 ac programming specifications ................................ 30 ac i2c specifications ................................................ 31 spi master ac specifications ................................... 32 spi slave ac specifications ..................................... 33 electrical specifications - rf section .......................... 35 initialization timing requirements ............................ 38 spi timing requirements ......................................... 39 packaging information ................................................... 40 packaging dimensions .............................................. 40 thermal impedances ................................................. 41 capacitance on crystal pins .. ............. .............. ........ 41 solder reflow peak temperat ure ............................. 41 ordering information ...................................................... 42 ordering code definitions ..... .................................... 42 acronyms ........................................................................ 43 document conventions ................................................. 43 units of measure ....................................................... 43 numeric naming .................... .................................... 43 document history page ................................................. 44 sales, solutions, and legal information ...................... 45 worldwide sales and design s upport ......... .............. 45 products .................................................................... 45 psoc solutions ......................................................... 45
CYRF89235 document number: 001-77748 rev. *f page 4 of 45 functional overview the encore v family of devices are designed to replace multiple traditional full-speed usb microcontroller system components with one, low cost single-chip programmable component. communication peripherals (i 2 c/spi), a fast cpu, flash program memory, sram data memory, and configurable i/o are included in a range of convenient pinouts. the architecture for this device family, as illustrated in the proc-usb logical block diagram on page 2 , consists of three main areas: the cpu core, th e wirelessusb? nl subsystem and the system resources. this product is an enhanced version of cypress?s successful full speed-usb peripheral controllers. enhancements include faster cpu at lower voltage operation, lower current consumption, twice the ram and flash, hot-swappable i/os, i 2 c hardware address recognition, new very low current sleep mode, and new package options. the encore v core the encore v core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo and ilo. the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four-mips, 8-bit harvard architecture microprocessor. system resources provide additional capability, such as a configurable i 2 c slave and spi master-slave communication interface and various system re sets supported by the m8c. full-speed usb the encore v usb system resource adheres to the usb 2.0 specification for full-speed devices operating at 12 mb/second with one upstream port and one usb address. encore v usb consists of these components: serial interface engine (sie) block. psoc memory arbiter (pma) block. 512 bytes of dedicated sram. a full-speed usb transceiver with internal regulator and two dedicated usb pins. figure 1. usb transceiver regulator at the encore v system level, the full-speed usb system resource interfaces to the rest of the encore v by way of the m8c's register access instructions and to the outside world by way of the two usb pins. the sie supports nine endpoints including a bidirectional control endpoint (endpoint 0) and eight unidirectional data endpoints (endpoints 1 to 8). the unidirectional data endpoints are individually configurable as either in or out. the usb serial interface engine (sie) allows the encore v device to communicate with the usb host at full-speed data rates (12 mb/s). the sie simplifies the interface to usb traffic by automatically handling the following usb processing tasks without firmware intervention: translates the encoded received data and formats the data to be transmitted on the bus. generates and checks cyclical redundancy checks (crcs). incoming packets failing che cksum verification are ignored. checks addresses. ignores all transactions not addressed to the device. sends appropriate ack/ nak/stall handshakes. identifies token type (setup, in, out) and sets the appropriate token bit once a valid token in received. identifies start-of-frame (sof) and saves the frame count. sends data to or retrieves data from the usb sram, by way of the psoc memory arbiter (pma). voltage regulator 5v 3.3v 1.5k 5k ps2 pull up dp dm ten td pdn rd dpo rse0 dmo receivers transmitter
CYRF89235 document number: 001-77748 rev. *f page 5 of 45 firmware is required to handle various parts of the usb interface. the sie issues interrupts after key usb events to direct firmware to appropriate tasks: fill and empty the usb data buffers in usb sram. enable pma channels appropriately. coordinate enumeration by decoding usb device requests. suspend and resume coordination. verify and select data toggle values. 10-bit adc the adc on encore v device is an independent block with a state machine interface to cont rol accesses to the block. the adc is housed together with the temperature sensor core and can be connected to this or the analog mux bus. as a default operation, the adc is connec ted to the tem perature sensor diodes to give digital values of the temperature. figure 2. adc system performance block diagram the adc user module contains an integrator block and one comparator with positive and ne gative input set by the muxes. the input to the integrator stage comes from the analog global input mux or the temperature se nsor with an input voltage range of 0 v to v refadc . in the adc only configuration (the adc mux selects the analog mux bus, not the default tem perature sensor connection), an external voltage can be connected to the input of the modulator for voltage conversion. the ad c is run for a number of cycles set by the timer, depending upon the desired resolution of the adc. a counter counts the number of trips by the comparator, which is proportional to the input voltage. the temp sensor block clock speed is 36 mhz and is divided down to 1 to 12 mhz for adc operation. spi the serial peripheral interconn ect (spi) 3-wire protocol uses both edges of the clock to enable synchronous communication without the need for stringent setup and hold requirements. figure 3. basic spi configuration a device can be a master or sl ave. a master outputs clock and data to the slave device and inputs slave data. a slave device inputs clock and data from the master device and outputs data for input to the master. together, the master and slave are essentially a circular shift register, where the master generates the clocking and initiates data transfers. a basic data transfer occurs when the master sends eight bits of data, along with eight clocks. in any transfer, both master and slave transmit and receive simultaneously. if the master only sends data, the received data from the slave is ignored. if the master wishes to receive data from the slave, the master must send dummy bytes to generate the clocking for the slave to send data back. figure 4. spi block diagram interface block command/ status adc temp diodes v in system bus temp sensor/ adc interface to the m8 c ( processor ) core spi master spi slave mosi miso sclk data is output by both the master and slave on one edge of the clock. data is registered at the input of both devices on the opposite edge of the clock. spi block registers sysclk data_out data_in clk_in clk_out int ss_ sclk mosi, miso sclk mosi, miso configuration[7:0] control[7:0] transmit[7:0] receive[7:0]
CYRF89235 document number: 001-77748 rev. *f page 6 of 45 spi configuration register (spi_cfg) sets master/slave functionality, clock speed, and interrupt select. spi control register (spi_cr) provides four control bits and four status bits for device interfacing and synchronization. the spim hardware has no support for driving the slave select (ss_) signal. the behavior and use of this signal is dependent on the application and encore v device and, if required, must be implemented in firmware. there is an additional data input in the spis, slave select (ss_), which is an active low signal. ss_ must be asserted to enable the spis to receive and transmit. ss_ has two high level functions: to allow for the selection of a given slave in a multi-slave environment. to provide additional clocking for tx data queuing in spi modes 0 and 1. i 2 c slave the i 2 c slave enhanced communications block is a serial-to-parallel processor, designed to interface the encore v device to a two-wire i 2 c serial communications bus. to eliminate the need for excessive cpu intervention and overhead, the block provides i 2 c-specific support for stat us detection and generation of framing bits. by default, the i 2 c slave enhanced module is firmware compatible with the previous generation of i 2 c slave functionality. however, this module provides new features that are configurable to implement significant flexibility for both internal and external interfacing. the basic i 2 c features include: slave, transmitter, and receiver operation. byte processing for low cpu overhead. interrupt or polling cpu interface. support for clock rates of up to 400 khz. 7- or 10-bit addressing (through firmware support). smbus operation (through firmware support). enhanced features of the i 2 c slave enhanced module include: support for 7-bit hardware address compare. flexible data buffering schemes. a "no bus stalling" operating mode. a low power bus monitoring mode. the i 2 c block controls the data (sda) and the clock (scl) to the external i 2 c interface through direct connections to two dedicated gpio pins. when i 2 c is enabled, these gpio pins are not available for general purpose use. the encore v cpu firmware interacts with the block through i/o register reads and writes, and firmware synchronization is implemented through polling and/or interrupts. in the default operating mode, which is firmware compatible with previous versions of i 2 c slave modules, the i 2 c bus is stalled upon every received address or byte, and the cpu is required to read the data or supply data as required before the i 2 c bus continues. however, this i 2 c slave enhanced module provides new data buffering capability as an enhanced feature. in the ezi 2 c buffering mode, the i 2 c slave interface appears as a 32-byte ram buffer to the external i 2 c master. using a simple predefined protocol, t he master controls the read and write pointers into the ram. when this method is enabled, the slave never stalls the bus. in this pr otocol, the data available in the ram (this is managed by the cpu) is valid. figure 5. i 2 c block diagram i2c core i2c basic configuration i2c_cfg i2c_scr i2c_dr plus features hw addr cmp buffer module cpu port buffer ctl 32 byte ram i2c plus slave i2c_addr sda_out scl_in sysclk i2c_en to/from gpio pins standby scl_out sda_in i2c_xstat i2c_xcfg i2c_buf i2c_bp i2c_cp mcu_cp mcu_bp system bus
CYRF89235 document number: 001-77748 rev. *f page 7 of 45 wirelessusb-nl subsystem wirelessusb-nl, optimized to operate in the 2.4-ghz ism band, is cypress's third generation of 2.4-ghz low-power rf technology. wirelessusb-nl implements a gaussian frequency-shift keying (gfsk) radio using a differentiated single-mixer, closed-loop modul ation design that optimizes power efficiency and interference immunity. closed-loop modulation effectively eliminates the problem of frequency drift, enabling wirelessusb-nl to transmit up to 255-byte payloads without repeatedly having to pay power penalties for re-locking the phase-locked loop (pll) as in open-loop designs among the advantages of wirelessusb-nl are its fast lock times and channel switching, along wit h the ability to transmit larger payloads. use of longer payload packets, compared to multiple short payload packets, can reduce overhead, improve overall power efficiency, and help alleviate spectrum crowding. combined with cypress's encore v based full-speed usb controllers, wirelessusb-nl also provides the lowest bill of materials (bom) cost solution fo r sophisticated pc peripheral applications such as wireless keyboards and mice, as well as best-in-class wireless performance in other demanding applications, such as toys, remo te controls, fitness, automation, presenter tools, and gaming. with proc-usb, the wirelessusb-nl transceiver can add wireless capability to a wide variety of full speed usb applications. the wirelessusb-nl is a fully-i ntegrated cmos rf transceiver, gfsk data modem, and packet framer, optimized for use in the 2.4-ghz ism band. it contains transmit, receive, rf synthesizer, and digital modem functions, with few external components. the transmitter supports digital power control. the receiver uses extensive digital processing for excellent overall performance, even in the presence of interference and transmitter impairments. the product transmits gfsk data at approximately 0-dbm output power. sigma-delta pll delivers high-quality dc-coupled transmit data path. the low-if receiver architectu re produces good selectivity and image rejection, with typical sens itivity of ?87 dbm or better on most channels. sensitivity on cha nnels that are integer multiples of the crystal reference oscillator frequency (12 mhz) may show approximately 5 db degradation. digital rssi values are available to monitor channel quality. on-chip transmit and receive fifo registers are available to buffer the data transfer with m cu. over-the-air data rate is always 1 mbps even when connected to a slow, low-cost mcu. built-in crc, fec, data whitening, and automatic retry/acknowledge are all ava ilable to simplify and optimize performance for individual applications. for more details on the radio?s implementation details and timing requriements, please go through the wirelessusb-nl datasheet in www.cypress.com. figure 6. wirelessusb- nl logic block diagram transmit power control the following table lists recommended settings for register 9 for short-range applications, where reduced transmit rf power is a desirable trade off for lower current. power-on and register initialization sequence for proper initialization at power up, v in must ramp up at the minimum overall ramp rate no slower than shown by t vin specification in the following figure. during this time, the rst_n line must track the v in voltage ramp-up profile to within approximately 0.2 v. since most mcu gpio pins automatically default to a high-z condition at power up, it only requires a pull-up resistor. when power is stable and the mcu por releases, and mcu begins to execute instructio ns, rst_n must then be pulsed low as shown in figure 18 on page 39 , followed by writing reg 27 = 0x4200. during or after this spi transaction, the state machine status can be read to confirm framer_st = 1, indicating a proper initialization. table 1. transmit power control power setting description typical transmit power (dbm) value of register 9 silicon id 0x1002 silicon id 0x2002 pa0 - highest power +1 0x1820 0x7820 pa2 - high power 0 0x1920 0x7920 pa4 - high power ?3 0x1a20 0x7a20 pa8 - low power ?7.5 0x1c20 0x7c20 pa12 - lower power ?11.2 0x1e20 0x7e20 note: silicon id can be read from register 31. miso rst_n clk mosi spi_ss pkt xtalo synthesizer brclk xtali v out v dd_io v in ant xtal osc x vco lna + bpf gfsk modulator ldo linear regulator pa image rej. mxr. spi registers framer antb gfsk demodulator gnd gnd pwr/ reset v dd1 ...v dd7
CYRF89235 document number: 001-77748 rev. *f page 8 of 45 additional system resources system resources, some of which have been previously listed, provide additional ca pability useful to complete systems. additional resources include low-voltage detection and power-on reset. the following statements describe the merits of each system resource. low-voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced power-on reset (por) circuit eliminates the need for a syst em supervisor. the 5 v maximum input, 1.8, 2.5, or 3 v selectable output, ldo regulator provides regulation for i/os. a register controlled bypass mode enables the user to disable the ldo. standard cypress psoc ide tools are available for debugging the encore v family of parts. getting started the quickest path to understanding the proc-usb silicon is by reading this data sheet and using the psoc ? designer? integrated development env ironment (ide). th is datasheet is an overview of the psoc integrated circuit and presents specific pin, register, and electrical specific ations. for in-depth information, along with detailed programming information, see the encore? v cy7c643xx, encore? v lv cy7c604xx technical reference manual (trm) for this psoc device. for up-to-date ordering, packaging , and electrical specification information, see the latest psoc device data sheets on the web at http://www.cypress.com . application notes application notes are an excellent introduction to the wide variety of possible psoc designs and are available at http://www.cypress.com . development kits psoc development kits are available online from cypress at http://www.cypress.com and through a growing number of regional and global distributors, including arrow, avnet, digi-key, farnell, future elec tronics, and newark. training free psoc technical traini ng (on demand, webinars, and workshops) is available online at http://www.cypress.com . the training covers a wide variety of topics and skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant, go to http://www.cypress.com and look for cypros consultants. solutions library visit our growing library of solution-focused designs at http://www.cypress.com . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support for assistance with technical issues, search knowledgebase articles and forums at http://www.cypress.com . if you cannot find an answer to your question, call technical support at 1-800-541-4736.
CYRF89235 document number: 001-77748 rev. *f page 9 of 45 development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application requirements. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical us er interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (dacs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this allows you to use more than 100 percent of psoc's resources for a given application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs fo r the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu regist ers, set and clear breakpoints, and provide program run, halt , and step control. the debugger also allows you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-se nsitive help. th is system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a ba se unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation p ods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full-speed (24-mhz) operation. device programmers firmware needs to be downloaded to proc usb device only at 3.3 v using miniprog3 programmer. this programmer kit can be purchased from cypress store using part# ?cy8ckit-002 - miniprog3?. it is a small, co mpact programmer which connects pc via a usb 2.0 cable (provided along with cy8ckit-002) note : miniprog1 programmer should not be used as it does not support programming at 3.3 v.
CYRF89235 document number: 001-77748 rev. *f page 10 of 45 designing with psoc designer the development process for the psoc device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of use r-selectable functions. the psoc development process is: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called user modules. user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the selected function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pulse-width modulator (pwm) user module configures one or more digital psoc blocks, one for each eight bits of resolution. using these parameters, you can establish the pulse width and duty cycle. configure the pa rameters and properties to correspond to your chosen application. enter values directly or by selecting values from dr op-down menus. all of the user modules are documented in datasheets that may be viewed directly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the user module and provide performance specifications. each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. organize and connect build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate configuration files? step. this causes psoc designer to generate source code that automat ically configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. a complete code development environment allows you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer's debugger (accessed by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full speed. psoc designer debugging capabilities rival those of syst ems costing many times more. in addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. it allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals.
CYRF89235 document number: 001-77748 rev. *f page 11 of 45 pin configuration the proc-usb device is available in a 40-pin qfn pa ckage, which is illustrated in the subsequent tables. figure 7. 40-pin qfn pinout
CYRF89235 document number: 001-77748 rev. *f page 12 of 45 pin definitions pin no pin name pin description 1 p1[3]/sclk digital i/o, analog i/o, spi clk 2 p1[1]/mosi [1, 2] digital i/o, analog i/o, tc clk, i2c scl, spi mosi 3 gnd ground connection 4, 20, 25, 33, 34, 37 v dd core power supply voltage. connect all v dd pins to vout pin. 5 d+ usb phy, digital i/o 6 d- usb phy, digital i/o 7 fifo fifo status indicator bit 8, 21, 24 vin unregulated input voltage to the on-chip low drop out (ldo) voltage regulator 9 p1[0] [1, 2] analog i/o, digital i/o, tc data, i 2 c sda 10 vdd_io vdd for the digital interface 11 p1[2] analog i/o, digital i/o 12 p1[4] analog i/o, digital i/o, ext clk 13 xres active high external reset with internal pull-down 14 spi_ss enable input for spi, active low. also used to bring device out of sleep state. 15 pkt transmit/receive packet status indicator bit 16 spi_clk clock input for spi interface 17 spi_mosi data input for the spi bus 18 spi_miso data output (tristate when not active) 19 rst_n rst_n low: chip shutdown to conserve power. register values lost rst_n high: turn on chip, registers restored to default value 22 vout 1.8 v output from on-chip ldo. connect to all v dd pins, do not connect to external loads. 23 p0[4] analog i/o, digital i/o, vref 26 xtalo output of the crys tal oscillator gain block 27 xtali input to the crystal oscillator gain block 28 p0[7] analog i/o, digital i/o,spi clk 29 p0[3] analog i/o, digital i/o, integrating input 30 p0[1] analog i/o, digital i/o, integrating input 31 p2[5] analog i/o, digital i/o, xtal out 32 p2[3] analog i/o, digital i/o, xtal in 35 antb differential rf input/output. each of these pins must be dc grounded, 20 k ? or less 36 ant differential rf input/output. each of these pins must be dc grounded, 20 k ? or less 38 p1[7]/ss_n digital i/o, analog i/o, i 2 c scl, spi ss 39 p1[5]/miso digital i/o, analog i/o, i 2 c sda, spi miso 40 vdd core power supply voltage. connect all v dd pins to vout pin. notes 1. during power up or reset event, device p1[0] and p1[1] may disturb the i 2 c bus. use alternate pins if issues are encountered. 2. these are the in-system serial programming (issp) pins that are not high z at power-on reset (por).
CYRF89235 document number: 001-77748 rev. *f page 13 of 45 register reference the section discusses the registers of the encore v device. it lists all the registers in mapping tables, in address order. register conventions the register conventions specific to this section are listed in the following table. register mapping tables the encore v device has a total register address space of 512 bytes. the register space is also referred to as i/o space and is broken into two parts: bank 0 (user space) and bank 1 (configuration space). the xio bi t in the flag register (cpu_f) determines which bank the user is currently in. when the xio bit is set, the user is said to be in the ?extended? address space or the ?configuration? registers. table 2. register conventions convention description r read register or bits w write register or bits l logical register or bits c clearable register or bits # access is bit specific
CYRF89235 document number: 001-77748 rev. *f page 14 of 45 table 3. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw ep1_cnt0 40 # 80 c0 prt0ie 01 rw ep1_cnt1 41 rw 81 c1 02 ep2_cnt0 42 # 82 c2 03 ep2_cnt1 43 rw 83 c3 prt1dr 04 rw ep3_cnt0 44 # 84 c4 prt1ie 05 rw ep3_cnt1 45 rw 85 c5 06 ep4_cnt0 46 # 86 c6 07 ep4_cnt1 47 rw 87 c7 prt2dr 08 rw ep5_cnt0 48 # 88 i2c_xcfg c8 rw prt2ie 09 rw ep5_cnt1 49 rw 89 i2c_xstat c9 r 0a ep6_cnt0 4a # 8a i2c_addr ca rw 0b ep6_cnt1 4b rw 8b i2c_bp cb r prt3dr 0c rw ep7_cnt0 4c # 8c i2c_cp cc r prt3ie 0d rw ep7_cnt1 4d rw 8d cpu_bp cd rw 0e ep8_cnt0 4e # 8e cpu_cp ce r 0f ep8_cnt1 4f rw 8f i2c_buf cf rw prt4dr 10 rw 50 90 cur_pp d0 rw prt4ie 11 rw 51 91 stk_pp d1 rw 12 52 92 d2 13 53 93 idx_pp d3 rw 14 54 94 mvr_pp d4 rw 15 55 95 mvw_pp d5 rw 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 pma0_dr 58 rw 98 i2c_dr d8 rw 19 pma1_dr 59 rw 99 d9 1a pma2_dr 5a rw 9a int_clr0 da rw 1b pma3_dr 5b rw 9b int_clr1 db rw 1c pma4_dr 5c rw 9c int_clr2 dc rw 1d pma5_dr 5d rw 9d dd 1e pma6_dr 5e rw 9e int_msk2 de rw 1f pma7_dr 5f rw 9f int_msk1 df rw 20 60 a0 int_msk0 e0 rw 21 61 a1 int_sw_en e1 rw 22 62 a2 int_vc e2 rc 23 63 a3 res_wdt e3 w 24 pma8_dr 64 rw a4 e4 25 pma9_dr 65 rw a5 e5 26 pma10_dr 66 rw a6 e6 27 pma11_dr 67 rw a7 e7 28 pma12_dr 68 rw a8 e8 spi_txr 29 w pma13_dr 69 rw a9 e9 spi_rxr 2a r pma14_dr 6a rw aa ea spi_cr 2b # pma15_dr 6b rw ab eb 2c tmp_dr0 6c rw ac ec 2d tmp_dr1 6d rw ad ed 2e tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 pt0_cfg b0 rw f0 usb_sof0 31 r 71 pt0_data1 b1 rw f1 usb_sof1 32 r 72 pt0_data0 b2 rw f2 usb_cr0 33 rw 73 pt1_cfg b3 rw f3 usbio_cr0 34 # 74 pt1_data1 b4 rw f4 usbio_cr1 35 # 75 pt1_data0 b5 rw f5 ep0_cr 36 # 76 pt2_cfg b6 rw f6 ep0_cnt0 37 # 77 pt2_data1 b7 rw cpu_f f7 rl ep0_dr0 38 rw 78 pt2_data0 b8 rw f8 ep0_dr1 39 rw 79 b9 f9 ep0_dr2 3a rw 7a ba fa ep0_dr3 3b rw 7b bb fb ep0_dr4 3c rw 7c bc fc ep0_dr5 3d rw 7d bd fd ep0_dr6 3e rw 7e be cpu_scr1 fe # ep0_dr7 3f rw 7f bf cpu_scr0 ff # gray fields are reserved; do not access these fields. # access is bit specific.
CYRF89235 document number: 001-77748 rev. *f page 15 of 45 table 4. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw pma4_ra 40 rw 80 c0 prt0dm1 01 rw pma5_ra 41 rw 81 c1 02 pma6_ra 42 rw 82 c2 03 pma7_ra 43 rw 83 c3 prt1dm0 04 rw pma8_wa 44 rw 84 c4 prt1dm1 05 rw pma9_wa 45 rw 85 c5 06 pma10_wa 46 rw 86 c6 07 pma11_wa 47 rw 87 c7 prt2dm0 08 rw pma12_wa 48 rw 88 c8 prt2dm1 09 rw pma13_wa 49 rw 89 c9 0a pma14_wa 4a rw 8a ca 0b pma15_wa 4b rw 8b cb prt3dm0 0c rw pma8_ra 4c rw 8c cc prt3dm1 0d rw pma9_ra 4d rw 8d cd 0e pma10_ra 4e rw 8e ce 0f pma11_ra 4f rw 8f cf prt4dm0 10 rw pma12_ra 50 rw 90 d0 prt4dm1 11 rw pma13_ra 51 rw 91 d1 12 pma14_ra 52 rw 92 ec0_enbus d2 rw 13 pma15_ra 53 rw 93 ec0_trim d3 rw 14 ep1_cr0 54 # 94 d4 15 ep2_cr0 55 # 95 d5 16 ep3_cr0 56 # 96 d6 17 ep4_cr0 57 # 97 d7 18 ep5_cr0 58 # 98 mux_cr0 d8 rw 19 ep6_cro 59 # 99 mux_cr1 d9 rw 1a ep7_cr0 5a # 9a mux_cr2 da rw 1b ep8_cr0 5b # 9b mux_cr3 db rw 1c 5c 9c io_cfg1 dc rw 1d 5d 9d out_p1 dd rw 1e 5e 9e io_cfg2 de rw 1f 5f 9f mux_cr4 df rw 20 60 a0 osc_cr0 e0 rw 21 61 a1 eco_cfg e1 # 22 62 a2 osc_cr2 e2 rw 23 63 a3 vlt_cr e3 rw 24 64 a4 vlt_cmp e4 r 25 65 a5 e5 26 66 a6 e6 27 67 a7 e7 28 68 a8 imo_tr e8 w spi_cfg 29 rw 69 a9 ilo_tr e9 w 2a 6a aa ea 2b 6b ab slp_cfg eb rw 2c tmp_dr0 6c rw ac slp_cfg2 ec rw 2d tmp_dr1 6d rw ad slp_cfg3 ed rw 2e tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef usb_cr1 30 # 70 b0 f0 31 71 b1 f1 32 72 b2 f2 33 73 b3 f3 pma0_wa 34 rw 74 b4 f4 pma1_wa 35 rw 75 b5 f5 pma2_wa 36 rw 76 b6 f6 pma3_wa 37 rw 77 b7 cpu_f f7 rl pma4_wa 38 rw 78 b8 f8 pma5_wa 39 rw 79 b9 f9 pma6_wa 3a rw 7a ba imo_tr1 fa rw pma7_wa 3b rw 7b bb fb pma0_ra 3c rw 7c bc fc pma1_ra 3d rw 7d usb_misc_cr bd rw fd pma2_ra 3e rw 7e be fe pma3_ra 3f rw 7f bf ff gray fields are reserved; do not access thes e fields. # access is bit specific.
CYRF89235 document number: 001-77748 rev. *f page 16 of 45 electrical specifications this section presents the dc and ac electrical specifications of the encore v usb devices. for the most up-to-date electrical specifications, verify that you have t he most recent data sheet available by visiting the company web site at http://www.cypress.com figure 8. voltage versus cpu frequency figure 9. imo frequency trim options absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. operating temperature 3.6 v 750 khz 24 mhz cpu frequency vin voltage 1.9 v 3 mhz v a l i d o p e r a t i n g r e g io n 3.6v 750 khz 6 mhz 24 mhz imo frequency vdd voltage 3 mhz 1.9v slimo mode = 01 12 mhz slimo mode = 00 slimo mode = 10 table 5. absolute maximum ratings symbol description conditions min typ max units t stg storage temperature higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 85 c degrades reliability. ?55 25 125 c v in [3] ? 1.9 ? 3.63 v v io dc input voltage ? ?0.5 ? v in + 0.5 v v ioz [4] dc voltage applied to tristate ? ?0.5 ? v in + 0.5 v i mio maximum current into any port pin ? ?25 ? +50 ma esd electrostatic discharge voltage human body model esd i) rf pins (ant, antb) ii) analog pins (xtali, xtalo) iii) remaining pins 500 500 2000 ? ? v lu latch-up current in accordance with jesd78 standard ? ? 140 ma table 6. operating temperature symbol description conditions min typ max units t a ambient temperature ? 0 ? 70 c notes 3. program the device at 3.3 v only. h ence use miniprog3 only since miniprog1 do es not support programming at 3.3 v. 4. port1 pins are hot-swap capable with i/o configured in high-z mode, and pin input voltage above v in .
CYRF89235 document number: 001-77748 rev. *f page 17 of 45 dc chip-level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 7. dc chip-level specifications symbol description conditions min typ max units v in [5, 6, 7, 8] supply voltage no usb activity. refer the table dc por and lvd specifications on page 23 1.9 ? 3.6 v v inusb [5, 6, 7, 8] operating voltage usb activity, usb regulator bypassed 3.15 3.3 3.45 v i dd24 supply current, imo = 24 mhz conditions are vin ? 3.0 v, t a = 25 c, cpu = 24 mhz. no i/o sourcing current ? 2.88 4.00 ma i dd12 supply current, imo = 12 mhz conditions are vin ? 3.0 v, t a = 25 c, cpu = 12 mhz. no i/o sourcing current ? 1.71 2.60 ma i dd6 supply current, imo = 6 mhz conditions are vin ? 3.0 v, t a = 25 c, cpu = 6 mhz. no i/o sourcing current ? 1.16 1.80 ma i sb0 deep sleep current vin ? 3.0 v, t a = 25 c, i/o regulator turned off ? 0.10 1.05 ? a i sb1 standby current with por, lvd and sleep timer vin ? 3.0 v, t a = 25 c, i/o regulator turned off ? 1.07 1.50 ? a i sbi2c standby current with i 2 c enabled conditions are vin = 3.3 v, t a = 25 c and cpu = 24 mhz ? 1.64 ? ? a notes 5. if powering down in standby sleep mode, to properly detect and recover from a vin brown out c ondition any of the following ac tions must be taken: bring the device out of sleep before powering down. assure that vin falls below 100 mv before powering back up. set the no buzz bit in the osc_cr0 register to keep the voltage monitoring circuit powered during sleep. increase the buzz rate to assure that the falling edge of vin is captured. the rate is configured through the pssdc bits in the slp_cfg register. for the referenced registers, refer to t he encore v technical reference manual. in deep sleep mode, additional low power voltag e monitoring circuitry allows vin brown out conditions to be detect ed for edge rates slower than 1 v/ms. 6. always greater than 50 mv above v ppor1 voltage for falling supply. 7. always greater than 50 mv above v ppor2 voltage for falling supply. 8. always greater than 50 mv above v ppor3 voltage for falling supply.
CYRF89235 document number: 001-77748 rev. *f page 18 of 45 dc usb interface specifications table 8. dc usb interface specifications symbol description conditions min typ max units r usbi usb d+ pull-up resistance with idle bus 900 ?1575 ? r usba usb d+ pull-up resistance while receiving traffic 1425 ?3090 ? v ohusb static output high ? 2.8 ?3.6v v olusb static output low ? ? ?0.3v v di differential input sensitivity ? 0.2 ?v v cm differential input common mode range ?0.8 ?2.5v v se single ended receiver threshold ? 0.8 ?2.0v c in transceiver capacitance ? ? ?50pf i io high z state data line leakage on d+ or d? line ?10 ?+10 ? a r ps2 ps/2 pull-up resistance ? 3000 5000 7000 ? r ext external usb series resistor in series with each usb pin 21.78 22.0 22.22 ?
CYRF89235 document number: 001-77748 rev. *f page 19 of 45 adc electrical specifications table 9. adc user module electrical specifications symbol description conditions min typ max units input v in input voltage range ? 0 ? vrefadc v c iin input capacitance ???5pf r in input resistance equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution 1/(500ff data clock) 1/(400ff data clock) 1/(300ff data clock) ? reference v refadc adc reference voltage ? 1.14 ? 1.26 v conversion rate f clk data clock source is chip?s internal main oscillator. see ac chip-level specifications for accuracy 2.25 ? 6 mhz s8 8-bit sample rate data cl ock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 23.43 ? ksps s10 10-bit sample rate data clock set to 6 mhz. sample rate = 0.001/ (2^resolution/data clock) ? 5.85 ? ksps dc accuracy res resolution can be set to 8-, 9-, or 10-bit 8 ? 10 bits dnl differential nonlinearity ? ?1 ? +2 lsb inl integral nonlinearity ? ?2 ? +2 lsb e offset offset error 8-bit resolution 0 3.20 19.20 lsb 10-bit resolution 0 12.80 76.80 lsb e gain gain error for any resolution ?5 ? +5 %fsr power i adc operating current ? ? 2.10 2.60 ma psrr power supply rejection ratio psrr (vin > 3.0 v) ? 24 ? db psrr (vin < 3.0 v) ? 30 ? db
CYRF89235 document number: 001-77748 rev. *f page 20 of 45 dc analog mux bus specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. dc low power compar ator spec ifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. comparator user module electrical specifications the following table lists the guaranteed maximum and minimum spec ifications. unless stated otherwis e, the specifications are fo r the entire device voltage and temperature operating range: 0 c ? t a ? 70 c, 1.9 v ? v in ? 3.6 v. table 10. dc analog mux bus specifications symbol description conditions min typ max units r sw switch resistance to common analog bus ? ? ? 800 ? r gnd resistance of initialization switch to gnd ? ? ? 800 ? the maximum pin voltage for measuring r w and r gnd is 1.8 v table 11. dc comparator specifications symbol description conditions min typ max units v lpc low power comparator (lpc) common mode maximum voltage limited to v in 0.0?1.8v i lpc lpc supply current ? ? 10 40 ? a v oslpc lpc voltage offset ? ? 3 30 mv table 12. comparator user module electrical specifications symbol description conditions min typ max units t comp comparator response time 50 mv overdrive ? 70 100 ns offset valid from 0.2 v to v in ? 0.2 v ? 2.5 30 mv current average dc current, 50 mv overdrive ? 20 80 a psrr supply voltage > 2 v power supply rejection ratio ? 80 ? db supply voltage < 2 v power supply rejection ratio ? 40 ? db input range ? 0 1.5 v
CYRF89235 document number: 001-77748 rev. *f page 21 of 45 dc gpio specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 2.4 v to 3.0 v and 0 c ? t a ? 70 c, or 1.9 v to 2.4 v and 0 c ? t a ????? c, respectively. typical parameters apply to 3.3 v at 25 c and are for design guidance only. table 13. 2.4 v to 3.0 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 or 4 pins i oh < 10 ? a, maximum of 10 ma source current in all i/os vin ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 or 4 pins i oh = 0.2 ma, maximum of 10 ma source current in all i/os vin ? 0.40 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh < 10 ? a, maximum of 10 ma source current in all i/os vin ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os vin ? 0.50 ? ? v v oh5a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh < 10 ? a, vin > 2.4 v, maximum of 20 ma source current in all i/os 1.50 1.80 2.10 v v oh6a high output voltage port 1 pins with ldo enabled for 1.8 v out i oh = 1 ma, vin > 2.4 v, maximum of 20 ma source current in all i/os 1.20 ? ? v v ol low output voltage iol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.75 v v il input low voltage ? ? ? 0.72 v v ih input high voltage ? 1.40 ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent temp = 25 ? c 0.50 1.70 7 pf v illvt2.5 input low voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 0.7 v ? v ihlvt2.5 input high voltage with low threshold enable set, enable for port1 bit3 of io_cfg1 set to enable low threshold voltage of port1 input 1.2 ? v
CYRF89235 document number: 001-77748 rev. *f page 22 of 45 table 14. 1.9 v to 2.4 v dc gpio specifications symbol description conditions min typ max units r pu pull-up resistor ? 4 5.60 8 k ? v oh1 high output voltage port 2 or 3 or 4 pins i oh = 10 ? a, maximum of 10 ma source current in all i/os vin ? 0.20 ? ? v v oh2 high output voltage port 2 or 3 or 4 pins i oh = 0.5 ma, maximum of 10 ma source current in all i/os vin ? 0.50 ? ? v v oh3 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 100 ? a, maximum of 10 ma source current in all i/os vin ? 0.20 ? ? v v oh4 high output voltage port 0 or 1 pins with ldo regulator disabled for port 1 i oh = 2 ma, maximum of 10 ma source current in all i/os vin ? 0.50 ? ? v v ol low output voltage i ol = 5 ma, maximum of 20 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]) ? ? 0.40 v v il input low voltage ? ? ? 0.30 vin v v ih input high voltage ? 0.65 vin ? ? v v h input hysteresis voltage ? ? 80 ? mv i il input leakage (absolute value) ? ? 1 1000 na c pin capacitive load on pins package and pin dependent temp = 25 c 0.50 1.70 7 pf
CYRF89235 document number: 001-77748 rev. *f page 23 of 45 dc por and lvd specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 15. dc por and lvd specifications symbol description conditions min typ max units v por1 2.36 v selected in psoc designer vin must be greater than or equal to 1.9 v during startup, reset from the xres pin, or reset from watchdog. ?2.362.41v v por2 2.60 v selected in psoc designer ?2.602.66 v por3 2.82 v selected in psoc designer ?2.822.95 v lvd0 2.45 v selected in psoc designer ? 2.40 2.45 2.51 v v lvd1 2.71 v selected in psoc designer 2.64 [9] 2.71 2.78 v lvd2 2.92 v selected in psoc designer 2.85 [10] 2.92 2.99 v lvd3 3.02 v selected in psoc designer 2.95 [11] 3.02 3.09 v lvd4 3.13 v selected in psoc designer 3.06 3.13 3.20 v lvd5 1.90 v selected in psoc designer 1.84 1.90 2.32 notes 9. always greater than 50 mv above v ppor1 voltage for falling supply. 10. always greater than 50 mv above v ppor2 voltage for falling supply. 11. always greater than 50 mv above v ppor3 voltage for falling supply.
CYRF89235 document number: 001-77748 rev. *f page 24 of 45 dc programming specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 16. dc programming specifications symbol description conditions min typ max units v in supply voltage for flash write operations ? 1.91 ? 3.6 v i ddp supply current during programming or verify ? ? 5 25 ma v ilp input low voltage during programming or verify see the appropriate dc analog mux bus specifications on page 20 ? ? v il v v ihp input high voltage during programming or verify see the appropriate dc analog mux bus specifications on page 20 v ih ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 0.2 ma i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor ? ? 1.5 ma v olp output low voltage during programming or verify ? ? 0.75 v v ohp output high voltage during programming or verify see appropriate dc analog mux bus specifications on page 20 . for vin > 3 v use v oh4 in ta b l e 6 on page 16. v oh ? vin v flash enpb flash write endurance erase/write cycles per block 50,000 ? ? ? flash dr flash data retention following maximum flash write cycles; ambient temperature of 55 c 20 ? ? years
CYRF89235 document number: 001-77748 rev. *f page 25 of 45 dc i 2 c specifications the following tables list guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 3, 2.4 v to 3.0 v and 0 c ? t a ? 70 c, or 1.9 v to 2.4 v and 0 c ? t a ? 70 c, respectively. typical parameters apply to 3.3 v at 25 c and are for design guidance only. dc reference buffer specifications the following tables list guaranteed maximum and minimum specific ations for the voltage and temperature ranges: 2.4 v to 3.0 v and 0 c ? t a ? 70 c, or 1.9 v to 2.4 v and 0 c ? t a ? 70 c, respectively. typical parameters apply to 3.3 v at 25 c and are for design guidance only. dc idac specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 17. dc i 2 c specifications symbol description conditions min typ max units v ili2c input low level 3.1 v vin 3.6 v ? ? 0.25 vin v 2.5 v vin 3.0 v ? ? 0.3 vin v 1.9 v vin 2.4 v ? ? 0.3 vin v v ihi2c input high level 1.9 v vin 3.6 v 0.65 vin ? ? v table 18. dc reference buffer specifications symbol description conditions min typ max units v ref reference buffer output 1.9 v to 3.6 v 1 ? 1.05 v v refhi reference buffer output 1.9 v to 3.6 v 1.2 ? 1.25 v table 19. dc idac specifications symbol description min typ max units notes idac_dnl differential nonlinearity ?4.5 ? +4.5 lsb idac_inl integral nonlinearity ?5 ? +5 lsb idac_gain (source) range = 0.5x 6.64 ? 22.46 a dac setting = 128 dec. range = 1x 14.5 ? 47.8 a range = 2x 42.7 ? 92.3 a range = 4x 91.1 ? 170 a dac setting = 128 dec. range = 8x 184.5 ? 426.9 a dac setting = 128 dec.
CYRF89235 document number: 001-77748 rev. *f page 26 of 45 ac chip level specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 20. ac chip-level specifications symbol description conditions min typ max units f imo24 imo frequency at 24 mhz setting ? 22.8 24 25.2 mhz f imo12 imo frequency at 12 mhz setting ? 11.4 12 12.6 mhz f imo6 imo frequency at 6 mhz setting ? 5.7 6.0 6.3 mhz f cpu cpu frequency ? 0.75 ? 25.20 mhz f 32k1 ilo frequency ? 19 32 50 khz f 32k_u ilo untrimmed frequency ? 13 32 82 khz dc imo duty cycle of imo ? 40 50 60 % dc ilo ilo duty cycle ? 40 50 60 % sr power_up power supply slew rate vin slew rate during power-up ? ? 250 v/ms t xrst external reset pulse width at power-up after supply voltage is valid 1 ? ? ms t xrst2 external reset pulse width after power-up applies after part has booted 10 ? ? ? s t os startup time of eco ? ? 1 ? s t jit_imo n=32 6 mhz imo cycle-to-cycle jitter (rms) ? 0.7 6.7 ns 6 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ? 4.3 29.3 ns 6 mhz imo period jitter (rms) ? 0.7 3.3 ns 12 mhz imo cycle-to-cycle jitter (rms) ? 0.5 5.2 ns 12 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ? 2.3 5.6 ns 12 mhz imo period jitter (rms) ? 0.4 2.6 ns 24 mhz imo cycle-to-cycle jitter (rms) ? 1.0 8.7 ns 24 mhz imo long term n (n = 32) cycle-to-cycle jitter (rms) ? 1.4 6.0 ns 24 mhz imo period jitter (rms) ? 0.6 4.0 ns
CYRF89235 document number: 001-77748 rev. *f page 27 of 45 ac usb data timings specifications ac usb driver specifications table 21. ac characteristics ? usb data timings symbol description conditions min typ max units t drate full speed data rate average bit rate 12 ? 0.25% 12 12 + 0.25% mhz t jr1 receiver jitter tolerance to next transition ?18.5 ? 18.5 ns t jr2 receiver jitter tolerance to pair transition ?9.0 ? 9 ns t dj1 fs driver jitter to next transition ?3.5 ? 3.5 ns t dj2 fs driver jitter to pair transition ?4.0 ? 4.0 ns t fdeop source jitter for differential transition to se0 transition ?2.0 ? 5 ns t feopt source se0 interval of eop ? 160.0 ? 175 ns t feopr receiver se0 interval of eop ? 82.0 ? ? ns t fst width of se0 interval during differential transition ? ? ? 14 ns table 22. ac characteristics ? usb driver symbol description conditions min typ max units t fr transition rise time 50 pf 4 ? 20 ns t ff transition fall time 50 pf 4 ? 20 ns t frfm rise/fall time matching ? 90 ? 111 % v crs output signal crossover voltage ? 1.30 ? 2.00 v
CYRF89235 document number: 001-77748 rev. *f page 28 of 45 ac general purpose i/o specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 10. gpio timing diagram table 23. ac gpio specifications symbol description conditions min typ max units f gpio gpio operating frequency normal strong mode port 0, 1 0 0 ? ? 6 mhz for 1.9 v CYRF89235 document number: 001-77748 rev. *f page 29 of 45 ac comparator specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. ac external clock specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 24. ac low power comparator specifications symbol description conditions min typ max units t lpc comparator response time, 50 mv overdrive 50 mv overdrive does not include offset voltage. ? ? 100 ns table 25. ac external clock specifications symbol description conditions min typ max units f oscext frequency (external oscillator frequency) ? 0.75 ? 25.20 mhz high period ? 20.60 ? 5300 ns low period ? 20.60 ? ? ns power-up imo to switch ? 150 ? ? ? s
CYRF89235 document number: 001-77748 rev. *f page 30 of 45 ac programming specifications the following table lists the guaranteed maximum and minimum s pecifications for the entire vo ltage and temperature ranges. figure 11. ac waveform table 26. ac programming specifications symbol description conditions min typ max units t rsclk rise time of sclk ? 1 ? 20 ns t fsclk fall time of sclk ? 1 ? 20 ns t ssclk data setup time to falling edge of sclk ? 40 ? ? ns t hsclk data hold time from falling edge of sclk ? 40 ? ? ns f sclk frequency of sclk ? 0 ? 8 mhz t eraseb flash erase time (block) ? ? ? 18 ms t write flash block write time ? ? ? 25 ms t dsclk3 data out delay from falling edge of sclk 3.0 ? v dd ? 3.6 ? ? 85 ns t dsclk2 data out delay from falling edge of sclk 1.9 ? v dd ? 3.0 ? ? 130 ns t xrst3 external reset pulse width after power-up required to enter programming mode when coming out of sleep 300 ? ? ? s t xres xres pulse length ? 300 ? ? ? s t vddwait v dd stable to wait-and-poll hold off ? 0.1 ? 1 ms t vddxres v dd stable to xres assertion delay ? 14.27 ? ? ms t poll sdata high pulse time ? 0.01 ? 200 ms t acq ?key window? time after a v dd ramp acquire event, based on 256 ilo clocks. ? 3.20 ? 19.60 ms t xresini ?key window? time after an xres event, based on 8 ilo clocks ? 98 ? 615 ? s sclk ( p1[ 1]) t rsclk t fsclk sdata (p1[0]) t ssclk t hsclk t dsclk
CYRF89235 document number: 001-77748 rev. *f page 31 of 45 ac i 2 c specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. figure 12. definition for timing for fast/standard mode on the i 2 c bus table 27. ac characteristics of the i 2 c sda and scl pins symbol description standard mode fast mode units min max min max f scl scl clock frequency 0 100 0 400 khz t hd;sta hold time (repeated) start cond ition. after this period, the first clock pulse is generated 4.0 ? 0.6 ? s t low low period of the scl clock 4.7 ? 1.3 ? s t high high period of the scl clock 4.0 ? 0.6 ? s t su;sta setup time for a repeated start condition 4.7 ? 0.6 ? s t hd;dat data hold time 0 3.45 0 0.90 s t su;dat data setup time 250 ? 100 [12] ? ns t su;sto setup time for stop condition 4.0 ? 0.6 ? s t buf bus free time between a stop and start condition 4.7 ? 1.3 ? s t sp pulse width of spikes are suppressed by the input filter ? ? 0 50 ns note 12. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 c with s n-pb or 245 5 c with sn-ag-cu paste. refer to the solder manufacturer specifications.
CYRF89235 document number: 001-77748 rev. *f page 32 of 45 spi master ac specifications figure 13. spi master mode 0 and 2 figure 14. spi master mode 1 and 3 table 28. spi master ac specifications symbol description conditions min typ max units f sclk sclk clock frequency vin ? ? 2.4 v vin < 2.4 v ? ? ? ? 6 3 mhz mhz dc sclk duty cycle ? ? 50 ? % t setup miso to sclk setup time vin ? 2.4 v vin < 2.4 v 60 100 ? ? ? ? ns ns t hold sclk to miso hold time ? 40 ? ? ns t out_val sclk to mosi valid time ? ? ? 40 ns t out_high mosi high time ? 40 ? ? ns 1/f sclk t low t high t out_h t hold t setup t out_su msb lsb spi master, modes 0 and 2 sclk (mode 0) sclk (mode 2) miso (input) mosi (output) 1/f sclk t high t low t out_h t hold t setup sclk (mode 1) sclk (mode 3) miso (input) mosi (output) spi master, modes 1 and 3 t out_su msb msb lsb lsb
CYRF89235 document number: 001-77748 rev. *f page 33 of 45 spi slave ac specifications figure 15. spi slave mode 0 and 2 table 29. spi slave ac specifications symbol description conditions min typ max units f sclk sclk clock frequency ? ? ? 4 mhz t low sclk low time ? 42 ? ? ns t high sclk high time ? 42 ? ? ns t setup mosi to sclk setup time ? 30 ? ? ns t hold sclk to mosi hold time ? 50 ? ? ns t ss_miso ss high to miso valid ? ? ? 153 ns t sclk_miso sclk to miso valid ? ? ? 125 ns t ss_high ss high time ? 50 ? ? ns t ss_clk time from ss low to first sclk ? 2/sclk ? ? ns t clk_ss time from last sclk to ss high ? 2/sclk ? ? ns t clk_ss t ss_high 1/f sclk t low t high t out_h t hold t setup t ss_miso t ss_clk msb lsb spi slave, modes 0 and 2 /ss sclk (mode 0) sclk (mode 2) miso (output) mosi (input)
CYRF89235 document number: 001-77748 rev. *f page 34 of 45 figure 16. spi slave mode 1 and 3 t clk_ss 1/f sclk t high t low t sclk_miso t out_h t hold t setup t ss_clk /ss sclk (mode 1) sclk (mode 3) miso (output) mosi (input) spi slave, modes 1 and 3 t ss_miso msb msb lsb lsb
CYRF89235 document number: 001-77748 rev. *f page 35 of 45 electrical specifications - rf section symbol description min typ max units test condition and notes supply voltage v in dc power supply voltage range 1.9 ? 3.6 vdc input to v in pins current consumption i dd_tx2 current consumption ? tx ? 18.5 ? ma transmit power pa2. i dd_tx12 ? 13.7 ? ma transmit power pa12. i dd_rx current consumption ? rx ? 18 ? ma i dd_idle1 current consumption ? idle ? 1.1 ? ma i dd_slpx current consumption ? sleep ? 1 ? a temperature = +25 c. using firmware sleep patch. register 27 = 0x1200, for v in 3.00 vdc only i dd_slpr ? 8 ? a temperature = +25 c; using firmware sleep patch register 27 = 0x4200. i dd_slph ? 38 ? a temperature = +70 c ?c? grade part; using firmware sleep patch register 27 = 0x4200 v ih logic input high 0.8 vin ? 1.2 vin v v il logic input low 0 ? 0.8 v i _leak_in input leakage current ? ? 10 a v oh logic output high 0.8 vin ? ? v i oh = 100 a source v ol logic output low ? ? 0.4 v i ol = 100 a sink i _leak_out output leakage current ? ? 10 a miso in tristate t _rise_out rise/fall time (spi miso) ? 8 25 ns 7 pf cap. load t _rise_in rise/fall time (spi mosi) ? ? 25 ns t r_spi clk rise, fall time (spi) ? ? 2 5 ns requirement for error-free register reading, writing. f _op operating frequency range 2400 ? 2482 mhz usage on-the-air is subject to local regulatory agency restrictions regarding operating frequency. v swr_i antenna port mismatch (z 0 = 50 ? ) ? <2:1 ? vswr receive mode. measured using lc matching circuit vswr _o ? <2:1 ? vswr transmit mode. measured using lc matching circuit receive section measured using lc matching circuit for ber ? 0.1%
CYRF89235 document number: 001-77748 rev. *f page 36 of 45 rxs base receiver sensitivity (fec off) ? ?87 ? dbm room temperature only 0-ppm crystal frequency error. rxs temp ? ?84 ? dbm over temperature; 0-ppm crystal frequency error. rxs ppm ? ?84 ? dbm room temperature only 80-ppm total frequency error ( 40-ppm crystal frequency error, each end of rf link) rxs temp+ppm ? ?80 ? dbm over temperature; 80-ppm total frequency error ( 40-ppm crystal frequency error, each end of rf link) r xmax-sig maximum usable signal ?20 0 ? dbm room temperature only ts data (symbol) rate ? 1 ? s minimum carrier/interference ratio for ber ? 0.1%. room temperature only. ci _cochannel co-channel interference ? +9 ? db ?60-dbm desired signal ci _1 adjacent channel interference, 1-mhz offset ? +6 ? db ?60-dbm desired signal ci _2 adjacent channel interference, 2-mhz offset ? ?12 ? db ?60-dbm desired signal ci _3 adjacent channel interference, 3-mhz offset ? ?24 ? db ?67-dbm desired signal obb out-of-band blocking ? ? ?27 ? dbm 30 mhz to 12.75 ghz measured with acx bf2520 ceramic filter on ant. pin. ?67-dbm desired signal, ber ? 0.1%. room temperature only. transmit section measured using a lc matching circuit p avh rf output power ? +1 ? dbm pa0 (pa_gn = 0, reg9 = 0x1820). room temperature only p avl ??11.2?dbmpa12 (pa_gn = 12, reg9 = 0x1e20). room temperature only. txp fx2 second harmonic ? ?45 ? dbm measured using a lc matching circuit. room temperature only. txp fx3 third and higher harmonics ? ?? ?45 ? dbm measured using a lc matching circuit. room temperature only. modulation characteristics df1 avg ? 263 ? khz modulation pattern: 11110000... df2 avg ? 255 ? khz modulation pattern: 10101010... in-band spurious emission ibs_2 2-mhz offset ? ? ?20 dbm ibs_3 3-mhz offset ? ? ?30 dbm ibs_4 ? 4-mhz offset ? ?? ?30 ? dbm electrical specifications - rf section (continued) symbol description min typ max units test condition and notes
CYRF89235 document number: 001-77748 rev. *f page 37 of 45 rf vco and pll section f step channel (step) size 1 ? mhz l 100k ssb phase noise ?75 ? dbc/hz 100-khz offset l 1m ?105 ? dbc/hz 1-mhz offset df x0 crystal oscillator frequency error ?40 ? +40 ppm relative to 12-mhz crystal reference frequency t hop rf pll settling time ? 100 150 s settle to within 30 khz of final value. autocal off. t hop_ac ? 250 350 s settle to within 30 khz of final value. autocal on. ldo voltage regulator section v do dropout voltage ? 0.17 0.3 v measured during receive state electrical specifications - rf section (continued) symbol description min typ max units test condition and notes
CYRF89235 document number: 001-77748 rev. *f page 38 of 45 initialization timing requirements figure 17. initialization flowchart table 30. initialization timing requirements timing parameter min max unit notes t rsu ? 30 / 150 ms 30 ms reset setup time ne cessary to ensure complete reset for vin = 6.5 mv/s, 150 ms reset setup time necessary to ensure complete reset for vin = 2 mv/s t rpw 1 10 s reset pulse width necessary to ensure complete reset t cmin 3 ? ms minimum recommended crystal oscillator and apll settling time t vin ? 6.5 / 2 mv/s maximum ramp time for v in , measured from 0 to 100% of final voltage. for example, if v in = 3.3 v, the max ramp time is 6.5 3.3 = 21.45 ms. if v in = 1.9 v, the max ramp time = 6.5 1.9 = 12.35 ms. reset setup time necessary to ensure complete reset for vin = 6.5mv/s reset setup time necessary to ensure complete reset for vin = 6.5mv/s reset setup time necessary to ensure complete reset for vin = 6.5mv/s initialize CYRF89235 at power-up mcu generates negative- going rst_n pulse wait crystal enable time initialize registers, beginning with reg[27] initialization done rst_n pulls up along with vin
CYRF89235 document number: 001-77748 rev. *f page 39 of 45 spi timing requirements figure 18. power-on and re gister programming sequence after register initialization, CYRF89235 is ready to transmit or receive. table 31. spi timing requirements timing parameter min max unit notes t sss 20 ? ns setup time from assertio n of spi_ss to clk edge t ssh 200 ? ns hold time required deassertion of spi_ss t sckh 40 ? ns clk minimum high time t sckl 40 ? ns clk minimum low time t sck 83 ? ns maximum clk clock is 12 mhz t ssu 30 ? ns mosi setup time t shd 10 ? ns mosi hold time t ss_su 10 ? ns before spi_ss enable, clk hold low time requirement t ss_hd 200 ? ns minimum spi inactive time t sdo ? 35 ns miso setup time, ready to read t sdo1 ? 5 ns if miso is configured as tristate, miso assertion time t sdo2 ? 250 ns if miso is configured as tr istate, miso deassertion time t1 min_r50 350 ? ns when reading register 50 (fifo) t1 min 83 ? ns when writing register 50 (fifo), or reading/writing any registers other than register 50. v in rst_n brclk spi_ss clock unstable clock stable spi activity t rsu t rpw t cmin (not drawn to scale) write reg[27]= 0x4200 t vin
CYRF89235 document number: 001-77748 rev. *f page 40 of 45 packaging information this section illustrates the packaging specifications for the proc-usb device, along with the thermal impedances for each packa ge. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. packaging dimensions figure 19. 40-pin qfn (6 6 1.0 mm) lt40b 3.5 3.5 mm e-pad (sawn) packa ge outline, 001-13190 001-13190 *h
CYRF89235 document number: 001-77748 rev. *f page 41 of 45 thermal impedances capacitance on crystal pins solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 32. thermal impedances per package package typical ? ja [13] typical ? jc 40-pin qfn [14] 27 c/w 34 c/w table 33. typical package capacitance on crystal pins package package capacitance 40-pin qfn 3.6 pf table 34. solder reflow peak temperature package minimum peak temperature [15] maximum peak temperature 40-pin qfn 260 265 notes 13. t j = t a + power x ? ja. 14. to achieve the thermal impe dance specified for the package, solder the center thermal pad to the pcb ground plane. 15. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 c with s n-pb or 245 5 c with sn-ag-cu paste. refer to the solder manuf acturer specifications.
CYRF89235 document number: 001-77748 rev. *f page 42 of 45 ordering information ordering code definitions table 35. ordering information ordering code package information flash (kb) sram (kb) no. of gpios CYRF89235-40ltxc 40-pin qfn (6 6 mm) 32 2 13 c = commercial , i = industrial , e = extended cy rf family code 89 = wireless 89 40 marketing code company id : cy = cypress radio frequency : rf = wireless ( ) product family package : lt = qfn 40 pin 235 235 = proc-usb lt x c thermal rating x = lead-free, x absent = leaded
CYRF89235 document number: 001-77748 rev. *f page 43 of 45 acronyms document conventions units of measure numeric naming hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, ?01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or ?0x? are decimal. acronym description api application programming interface cpu central processing unit gpio general purpose i/o ice in-circuit emulator ilo internal lowspeed oscillator imo internal main oscillator i/o input/output lsb least significant bit lvd low voltage detect msb most significant bit por power-on reset ppor precision power-on reset psoc programmable system-on-chip slimo slow imo sram static random access memory symbol unit of measure ? c degree celsius db decibels ff femtofarad hz hertz kb 1024 bytes kbit 1024 bits khz kilohertz k ? kilohm mhz megahertz m ? megaohm ? a microampere ? f microfarad ? h microhenry ? s microsecond ? v microvolt ? vrms microvolts root-mean-square ? w microwatts ma milliampere ms millisecond mv millivolt na nanoampere ns nanosecond nv nanovolt w ohm pa picoampere pf picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second ? sigma: one standard deviation v volt
CYRF89235 document number: 001-77748 rev. *f page 44 of 45 document history page document title: CYRF89235, proc? usb document number: 001-77748 rev. ecn no. orig. of change submission date description of change ** 3554967 antg 04/03/2012 new data sheet. *a 3605878 antg 05/02/2012 modified title. updated status ?company confidential? of the datasheet. changed ?proc nl dongle? to ?proc-usb? everywhere in the datasheet. *b 3714928 akhl 08/16/2012 major text update. added electrical specifications - rf section . *c 3747532 akhl 09/18/2012 removed ?company confidential? tag in the header. replaced package diagram spec with 001-13190. *d 3784571 akhl 10/26/2012 updated functional overview (added transmit power control ). updated development tools (updated psoc designer software subsystems (added device programmers )). updated electrical specifications - rf section (replaced cyrf8935 with CYRF89235 in figure 17 and also in the last bullet point below figure 18 ). updated packaging information (no update in package diagram, updated thermal impedances (updated ta b l e 3 2 )). updated in new template. *e 3872679 akhl 01/19/2013 updated proc-usb features (replaced ?up to 37 general-purpose i/os (gpios)? with ?up to 13 g eneral-purpose i/os (gpios)?). updated electrical specifications (updated dc chip-level specifications (changed maximum value of v inusb parameter from 3.60 v to 3.45 v in table 7 )). *f 3982770 akhl 05/15/2013 updated proc-usb features . updated proc-usb logical block diagram . updated functional overview : updated wirelessusb-nl subsystem (updated figure 6 ). updated transmit power control (updated table 1 ). updated electrical specifications : updated absolute maximum ratings (updated ta b l e 5 ). updated operating temperature (updated ta b l e 6 ). updated dc chip-level specifications (updated ta b l e 7 ). updated dc idac specifications (updated ta b l e 1 9 ). updated electrical specifications - rf section : updated spi timing requirements (updated ta b l e 3 1 ). updated packaging information : no change in package diagram revision. removed ?package handling?. updated capacitance on crystal pins (updated ta b l e 3 3 ). updated solder reflow peak temperature (updated ta b l e 3 4 ). updated ordering information : no change in part numbers. added ordering code definitions .
document number: 001-77748 rev. *f revised may 15, 2013 page 45 of 45 psoc designer? is a trademark and psoc? and capsense? are registered trademarks of cypress semiconductor corporation. purchase of i 2 c components from cypress or one of its sublicensed a ssociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. as from october 1st, 2006 philips semiconductors has a new trade name - nxp sem iconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. CYRF89235 ? cypress semiconductor corporation, 2012-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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