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5.5 v input, 300 ma, low quiescent current, cmos linear regulator data sheet adp122 / adp123 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 C 2012 analog devices, inc. all rights reserved. features input voltage supply range: 2.3 v to 5.5 v 30 0 ma maximum output current fixed and adjustable output voltage versions very low dropout voltage: 85 mv at 30 0 ma load low quiescent current: 4 5 a at no load low shutdown current : <1 a i nitial accura cy: 1% accuracy up to 31 fixed - output voltage options available from 1.75 v to 3.3 v adjustable - output voltage range 0.8 v to 5.0 v (adp123) excellent psrr performance: 60 db at 10 0 khz excellent load/line transient response optimized for small 1.0 f ceramic capacitors current limit and thermal overload protection logic controlled enable comp act packages: 5 - lead tsot and 6 - lead 2 mm 2 mm lfcsp applications digital camera and audio devices portable and battery - powered equipm ent automatic meter reading (amr) meters gps and location management units medical instrumentation point - of - sale equipment general description the adp122/adp123 are low quiescent current, low dropout linear regulators. they are designed to operate from an input voltage between 2.3 v and 5.5 v and to provide up to 300 ma of output current. the low 85 mv dropout voltage at a 300 ma load improves efficiency and allows operation over a wide input voltage range. the low 170 a of quiescent current at full load makes the adp122 ideal for battery - operated portable equipment. the adp122 is capable of 31 fixed output voltages from 1.75 v to 3.3 v. the adp123 is the adjustable version of the device and allows the output voltage to be set between 0.8 v and 5.0 v by an external voltage divider. the adp122/adp123 are specifically designed for stable operation with tiny 1 f ceramic input and output capacitors to meet the requirements of high performance, space constrained applications . typical application circuit s 2 3 1 4 5 v in = 2.3v t o 5.5v v out = 1.8v vin gnd en vout nc c in 1f c out 1f adp122 08399-001 off on figure 1. adp122 with fixed output v oltage (tsot version ) v in = 2.3v t o 5.5v v out = 0.5v(1 + r1/r2) r1 r2 c in 1f c out 1f 08399-002 2 3 1 4 5 vin gnd en vout adj adp123 off on figure 2. adp12 3 with adjustable output vo ltage (tsot version ) 08399-135 nc = not connect. this pin can be left floating or connected to ground. top view (not to scale) adp122 3 gnd 1 vout 2 nc 4 en 6 vin = 2.3v to 5.5v vout = 1.8v c1 1f gnd on off vin 5 nc c2 1f gnd gnd figure 3 . adp 12 2 with fixed output voltage (lfcsp version ) 08399-136 nc = not connect. this pin can be left floating or connected to ground. top view (not to scale) adp123 3 gnd 1 vout 2 adj 4 en 6 vin = 2.3v to 5.5v vout = 0.5v (1 + r1/r2) c1 1f gnd on off vin 5 nc c2 1f r1 r2 gnd gnd gnd figure 4 . adp 123 with adjustable output voltage (lfcsp version ) the adp122/adp123 have an internal soft start that gives a constant start - up time of 350 s. short - circuit protection and ther mal overload protection circuits prevent damage in adverse conditions. the adp122/adp123 are availabl e in a tiny, 5 - lead tsot package and 6 - lead lfcsp package for the smallest footprint solution to meet a variety of portable applications.
adp122/adp123 data sheet rev. e | page 2 of 24 table of conten ts features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical application circuits ............................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 recommended specifications ..................................................... 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configurations and function descr iptions ........................... 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 11 applications information .............................................................. 12 capacitor selection .................................................................... 12 undervoltage lockout ............................................................... 13 enable feature ............................................................................ 13 current limit and thermal overload protection ................. 14 thermal considerations ............................................................ 14 junction temperature calculations for tsot package ....... 15 junction temperature calculations for lfcsp package ...... 17 printed circuit board layout considerations ........................ 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 21 revision history 6 /12 rev. d to rev. e changes to table 3 ............................................................................. 5 4/12 rev. c to rev. d changes to ordering guide ........................................................... 21 4/12 rev. b to rev. c changes to operating ambient temperature range ; table 3 ................................................................................................. 5 3 /1 2 rev. a to rev. b added v out = 2.8 v t o figure 23 caption ...................................... 9 updated outline dimensions ....................................................... 20 6 /11 rev. 0 to rev. a added 6 - lead lfcsp package .................................... throughout added figure 3 and figure 4 ( renumbered sequentially ) .......... 1 changes to table 4 ............................................................................. 5 changes to pin configuration and function descriptions section ................................................................................................. 6 changes to thermal considerations section ............................. 14 added junction temperature calculations for lfcsp package section .............................................................................................. 1 7 updated outline dimensions ...................................................... 20 changes to ordering guide .......................................................... 21 10/0 9 revision 0: initial version
data s heet adp122/adp123 rev. e | page 3 of 24 specifications unless otherwise noted, v in = ( v out + 0.3 v ) or 2.3 v , whichever is greater ; adj connected to vout; i out = 1 0 ma; c in = 1.0 f; c out = 1.0 f; t a = 2 5c . table 1 . parameter symbol test conditions min typ max unit input voltage range v in 2.3 5.5 v opera ting supply current 1 i gnd i out = 0 a 4 5 a i out = 0 a, t j = ?40c to +125c 105 a i out = 1 ma 60 a i out = 1 ma, t j = ?40c to +125c 120 a i out = 1 5 0 ma 130 a i out = 1 5 0 ma, t j = ?40c to +125c 190 a i out = 300 ma 170 a i out = 300 ma, t j = ?40c to +125c 240 a shutdown c urrent i sd en = gnd 0.1 a en = gnd, t j = ?40c to +125c 1 a output voltage accuracy 2 v out fixed output i out = 10 ma ? 1 +1 % 100 a < i out < 300 ma, v in = (v out + 0.5 v) to 5.5 v , t j = ?40c to +125c ?2 +1.5 % adjustable output i ou t = 10 ma 0.495 0.500 0.505 v 100 a < i out < 300 ma, v in = 2.3 v to 5.5 v , t j = ?40c to +125c 0.490 0.500 0.5075 v line regulation ?v out /?v in v in = v in = 2.3 v to 5.5 v, t j = ?40c to +125c ?0.05 +0.05 %/v load regulation 3 ?v out /?i out i out = 1 ma to 300 ma 0.0005 %/ma i out = 1 ma to 300 ma , t j = ?40c to +125c 0.001 %/ma adj input bias current adj i - bias 2.3 v v in 5.5 v, adj connected to vout 15 na dropout voltage 4 v dropout i out = 10 ma, v out > 2.3 v 3 mv i out = 10 ma, t j = ?40c to +125c 5 mv i out = 150 ma, v out > 2.3 v 45 mv i out = 150 ma, t j = ?40c to +125c 75 mv i out = 300 ma, v out > 2.3v 85 mv i out = 300 ma, t j = ?40c to +125c 150 mv start - up time 5 t start - up v out = 3.0 v 350 s curren t limit threshold 6 i limit 350 500 650 ma thermal shutdown thermal shutdown threshold ts sd t j rising 150 c thermal shutdown hysteresis ts sd - hys 15 c en input en input logic high v ih 2.3 v v in 5.5 v 1.2 v en input logic low v i l 2.3 v v in 5.5 v 0.4 v en input leakage current v i - leakage en = vin or gnd 0.1 a en = vin or gnd, t j = ?40c to +125c 1 a undervoltage lockout uvlo input voltage rising uvlo rise t j = ?40c to +125c 2.1 v input voltage falling u vlo fal l t j = ?40c to +125c 1.5 v hysteresis uvlo hys t a = 25c 1 25 mv
adp122/adp123 data sheet rev. e | page 4 of 24 parameter symbol test conditions min typ max unit output noise out noise 10 hz to 100 khz, v in = 5.5 v, v out = 1.2 v 2 5 v rms 10 hz to 100 khz, v in = 5.5 v, v out = 1.8 v 35 v rms 10 hz to 100 khz, v in = 5.5 v, v out = 2.5 v 45 v rms 10 hz to 100 khz, v in = 5.5 v, v out = 3.3 v 55 v rms 10 hz to 100 khz, v in = 5.5 v, v out = 4.2 v 65 v rms power supply rejection ratio psrr 10 khz, v out = 3.3 v 60 db (v in = v out + 0.5 v) 10 khz, v out = 2.5 v 60 db 10 khz, v out = 1.8 v 60 db 100 khz, v out = 3.3 v 60 db 100 khz, v out = 2.5 v 60 db 100 khz, v out = 1.8 v 60 db 1 the current from the external resistor divider network in the case of adjustable voltage output (as with the adp123) should be subtracted from the ground current measured. 2 accuracy when vout is connected directly to adj. when vout voltage is set by external feedback resistors, absolute accuracy i n adjust mode d epends on the tolerances of the resistors used . 3 based on an endpoint calculation using 1 ma and 300 ma loads. 4 dropout voltage is defined as the input - to - output voltage differential when the input voltage is set to the nominal output voltage. this appli es only for output voltages greater than 2.3 v. 5 start - up time is defined as the time between the rising edge of en to vout being at 90 % of its nominal value. 6 current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. for example, the current limit for a 3.3 v output voltage is defined as the current that causes the output voltage to drop to 90% of 3.3v, or 2.97 v. recommended specific ations table 2 . parameter symbol test conditions min typ max unit minimum input and output capacitance 1 cap min t a = ?40c to +125c 0.70 f capacitor esr r esr t a = ?40c to +125c 0.001 1 1 the minimum input and output capacitance should be greater than 0.70 f ove r the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x 5r type capacitors are recommended; y5v and z5u capacitors are not recommended for use with any ldo.
data s heet adp122/adp123 rev. e | page 5 of 24 absolute maximum rat ings table 3 . parameter rating v in to gnd ? 0.3 v to + 6.5 v adj to gnd ? 0.3 v to + 6.5 v en to gnd ? 0.3 v to + 6.5 v v out to gnd ? 0.3 v to v in storage temperature range ? 65c to +150c operating ambient temperature range ? 40c to +12 5 c operating junction temperature ?40c to +125c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal data absolute maximum ratings apply individually only, not in combination. the adp122 / adp123 can be damaged when the junction temperature l imits are exceeded. monitoring ambient temperature does not guarantee that t j will remain within the specified temperature limits. in applications with high power dissipation and poor thermal resistance , the maximum ambient temperature may have to be derat ed. in applications with moderate power dissipation and low pcb thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature (t j ) of the devic e is dependent on the ambient temperature (t a ), the power dissipation of the device (p d ) , and the junction - to - ambient thermal resistance of the package ( ja ). maximum junction temperature (t j ) is calculated from the ambient temperature (t a ) and power diss ipation (p d ) using the formula t j = t a + ( p d ja ) the j unction - to - ambient thermal resistance ( ja ) of the package is based on modeling and calculation using a 4 - layer board. the junction - to - ambient thermal resistance is highly dependent on the applicati on and board layout. in applications in which high maxi - mum power dissipation exists, close attention to thermal board design is required. the value of ja may vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4 - layer, 4 inch 3 inch circuit board. refer to jesd 51 - 7 for detailed information on the board construction jb is the junction - to - board thermal characterization parameter and is measured in c / w. the jb of the package is based on model ing and calculation using a 4 - layer board. the guidelines for reporting and using package thermal information : jesd51 - 12 states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing throu gh multiple thermal paths rather than a single path as in thermal resistance, jb . therefore, jb thermal paths include convection from the top of the package as well as radiation from the package factors that make jb more useful in real - world application s. maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + ( p d jb ) r efer to jesd51 - 8 and jesd51 - 12 for more detailed information about jb . thermal resistance ja and jb ar e specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jb unit 5 - lead tsot 170 43 c/w 6 - lead 2 mm 2 mm lfcsp 68.9 44.1 c/w esd caution
adp122/adp123 data sheet rev. e | page 6 of 24 pin configuration s and function descrip tions adp122 t op view (not to scale) 1 vin 2 gnd 3 en 5 vout 4 nc nc = no connect 08399-004 figure 5. adp122 tsot fixed output pin configuration 08399-137 top view (not to scale) adp122 3 gnd 1 vout 2 nc 4 en 6 vin 5 nc notes 1. nc = not connect. this pin can be left floating or connected to ground. 2. exposed pad must be connected to gnd. figure 6 . adp122 lfcsp fixed output pin configuration adp123 top view (not to scale) 1 vin 2 gnd 3 en 5 vout 4 adj 08399- 003 figure 7. adp123 tsot adjustable output pin configuration 08399-138 top view (not to scale) adp123 3 gnd 1 vout 2 adj 4 en 6 notes 1. nc = not connect. this pin can be left floating or connected to ground. 2. exposed pad must be connected to gnd. vin 5 nc figure 8 . adp123 lfcsp adjustable output pin configuration table 5 . pin function descriptions pin no. mnemonic description adp1 22 adp123 tsot lfcsp tsot lfcsp 1 6 1 6 vin regulator input supply. bypass vin to gnd with a capacitor of at least 1 f. 2 3 2 3 gnd ground. 3 4 3 4 en enable input. drive en high to turn on the regulator; drive en low to turn off the regulator. fo r automatic startup, connect en to vin. n/a n/a 4 2 adj output voltage adjust input. connect the midpoint of an external divider from vout to gnd to this pin to set the output voltage. 4 2, 5 n/a 5 nc no connect. these pins are not internally bonded. the y can be left floating or connected to ground. 5 1 5 1 vout regulated output voltage. bypass vout to gnd with a capacitor of at least 1 f. n/a ep n/a ep epad exposed pad. the exposed pad must be connected to ground.
data s heet adp122/adp123 rev. e | page 7 of 24 typical performance characteristic s v i n = 3.6 v, v out = 3.3 v, i out = 1 0 ma, c in = 1.0 f , c out = 1 .0 f, t a = 25c, unless otherwise noted. 3.260 3.265 3.270 3.275 3.280 3.285 3.290 3.295 3.300 ?40 ?5 25 85 125 junction temperature (c) v out (v) i out = 100a i out = 1ma i out = 10ma i out = 100ma i out = 200ma i out = 300ma 08399-005 figure 9 . output voltage vs. junction temperature 3.2895 3.2900 3.2905 3.2910 3.2915 3.2920 3.2925 3.2930 3.2935 3.2940 3.2945 0.1 1 10 100 1000 i out (ma) v out (v) 08399-006 figure 10 . output voltage vs. load curren t 3.284 3.286 3.288 3.290 3.292 3.294 3.296 v in (v) v out (v) 08399-007 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 i out = 100a i out = 1ma i out = 10ma i out = 100ma i out = 200ma i out = 300ma figure 11 . output voltage vs. input voltage 0 50 100 150 200 250 ground current (a) ?40 ?5 25 85 125 junction temperature (c) i out = 100a i out = 10ma i out = 100ma i out = 200ma i out = 300ma i out = 1ma 08399-008 figure 12 . ground current vs. junction temperature 0 20 40 60 80 100 120 140 160 180 200 0.1 1 10 100 1000 i out (ma) ground current (a) 08399-009 figure 13 . ground current vs. load current 0 20 40 60 80 100 120 140 160 180 200 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 v in (v) ground current (a) i out = 100a i out = 1ma i out = 10ma i out = 100ma i out = 200ma i out = 300ma 08399-010 figure 14 . ground current vs. input voltage
adp122/adp123 data sheet rev. e | page 8 of 24 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 ?50 ?25 0 25 50 75 100 125 temperature (c) shutdown current (a) v in = 3.6v v in = 3.8v v in = 4.2v v in = 4.4v v in = 5.0v v in = 5.2v v in = 5.4v v in = 5.5v 08399-011 figure 15 . shutdown current vs. temperature at various input voltages 0 10 20 30 40 50 60 70 1 10 100 1000 i out (ma) dropout (mv) 08399-012 figure 16 . dropout voltage vs. load current 0 50 100 150 200 250 300 350 400 450 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 v in (v) i gnd (a) i out = 10ma i out = 100ma i out = 150ma i out = 300ma 08399-014 figure 17 . ground current vs. input voltage (in dropout) 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 v in (v) v out (v) i out = 10ma i out = 100ma i out = 150ma i out = 300ma 08399-013 figure 18 . output voltage vs. input voltage (in dropout) ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) i out = 100a v in = v out + 0.5v v ripple = 50mv c in = c out 1f i out = 1ma i out = 10ma i out = 100ma i out = 200ma i out = 300ma 08399-015 figure 19 . power supply rejection ratio vs. frequency, v out = 2.8 v, v in = 3.3 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) i out = 100a v in = v out + 0.5v v ripple = 50mv c in = c out 1f i out = 1ma i out = 10ma i out = 100ma i out = 200ma i out = 300ma 08399-016 figure 20 . power supply rejection ratio vs. frequency, v out = 3.3 v, v in = 3.8 v
data s heet adp122/adp123 rev. e | page 9 of 24 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) i out = 100a v in = v out + 0.5v v ripple = 50mv c in = c out 1f i out = 1ma i out = 10ma i out = 100ma i out = 200ma i out = 300ma 08399-017 figure 21 . power supply rejection ratio vs. frequency, v out = 4.2 v, v in = 4.7 v ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) v out = 2.8v, i out = 1ma v in = v out + 0.5v v ripple = 50mv c in = c out 1f v out = 3.3v, i out = 1ma v out = 4.2v, i out = 1ma v out = 2.8v, i out = 300ma v out = 3.3v, i out = 300ma v out = 4.2v, i out = 300ma 08399-018 figure 22 . power supp ly rejection ratio vs. frequency, various output voltages and load currents ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) v in = 3.1v, i out = 1ma v ripple = 50mv c in = c out 1f v in = 3.3v, i out = 1ma v in = 3.8v, i out = 1ma v in = 4.8v, i out = 1ma v in = 3.1v, i out = 300ma v in = 3.3v, i out = 300ma v in = 3.8v, i out = 300ma v in = 4.8v, i out = 300ma 08399-019 figure 23 . power supply rejection ratio vs. headroom voltage (v in ? v out ), v out = 2.8 v 0 1 2 3 4 5 10 100 1k 10k 100k frequency (hz) n o i se ( v / h z ) 08399-020 v out = 2.8v v out = 3.3v v out = 4.2v figure 24 . output noise spectrum 30 35 40 45 50 55 60 65 70 0.001 0.01 0.1 1 10 100 1000 i out (ma) rms noise (v) v out = 4.2v v out = 3.3v v out = 2.8v 08399-021 figure 25 . output noise vs. load current and output voltage 08399-022 ch1 200ma ? b w ch2 50.0mv b w m 40.0s a ch1 196ma 1 2 t 10.20% v out v in = 3.7v v out = 3.3v 1ma to 300ma load step i out figure 26 . load transient response, c out = 1 f
adp122/adp123 data sheet rev. e | page 10 of 24 08399-023 ch1 200ma ? b w ch2 20.0mv b w m 40.0s a ch1 196ma 1 2 t 10.40% v in = 3.7v v out = 3.3v 1ma to 300ma load step i out v out figure 27 . load transient response, c out = 4.7 f 08399-024 ch1 1.00v ? b w ch2 2.00mv b w m 10.0s a ch3 2.04v 1 2 t 10.00% 4v to 4.5v voltage step v in v out figure 28 . line transient response, load current = 1 ma 08399-025 ch1 1.00v b w ch2 2.00mv b w m 10.0s a ch3 2.04v 1 2 t 9.600% 4v to 4.5v voltage step v in v out figure 29 . line transient response, load current = 300 ma
data s heet adp122/adp123 rev. e | page 11 of 24 theory of operation the adp122/adp123 are low quiescent current, low - dropout linear regulat ors that operate from 2.3 v to 5.5 v and can provide up to 300 ma of output current. drawing a low 170 a of quies - cent current (typical) at full load makes the adp122/adp123 ideal for battery - operated portable equipment. shutdown current consumption is ty pically 100 na. optimized for use with small 1 f ceramic capacitors, the adp122/adp123 provide excellent transient performance. internally, the adp122 /a dp123 consist of a reference, an error amplifier, a feedback voltage divider, and a pmos pass transist or. output current is delivered via the pmos pass device, which is controlled by the error amplifier. the error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. if the feedback voltage is lowe r than the reference voltage, the gate of the pmos device is pulled lower, allowing more current to pass and increasing the output voltage. if the feedback voltage is higher than the reference voltage, the gate of the pmos device is pulled higher, allowing less current to pass and decreasing the output voltage. the adjustable adp12 3 has an output voltage range of 0.8 v to 5.0 v. the output voltage is set by the ratio of two external resistors, as shown in figure 2 . the device ser vos the output to maintain the voltage at the adj pin at 0.5 v referenced to ground. the current in r1 is then equal to 0.5 v/r2 and the current in r1 is the current in r2 plus the adj pin bias current. the adj pin bias current, 15 na at 25c, flows throug h r1 into the adj pin. the output voltage can be calculated using the equation: v out = 0.5 v(1 + r1 / r2 ) + ( adj i - bias )(r1 ) the value of r1 should be less than 200 k to minimize errors in the output voltage caused by the adj pin bias current. for example, when r1 and r2 each equal 200 k, the output voltage is 1.0 v. the output voltage error introduced by the adj pin bias current is 3 mv or 0.3%, assu ming a typical adj pin bias current of 15 na at 25c. note that in shutdown, the output is turned off and the divider current is 0 . the adp122/adp123 use the en pin to enable and disable the vout pin under normal operating conditions. when en is high, vout turns on; when en is low, vout turns off. for automatic startup, en can be tied to vin. short circui t , uvlo and therma l protect 0.5v reference adp122 shutdown vin vout r1 r2 gnd notes 1. r1 and r2 are interna l resis t ors, av ailable on the adp122 on l y . en 08399-121 figure 30 . adp122 internal block diagram (fixed output) short circui t , uvlo and therma l protect 0.5v reference shutdown vin vout gnd en adj 08399-122 adp123 figure 31 . adp123 internal block diagram (adjustable out put)
adp122/adp123 data sheet rev. e | page 12 of 24 application s information capacitor selection output capacitor the adp122 /adp 123 are designed for operation with small, space - saving ceramic capacitors, but these devices can function with most commonly used capacitors as long as care is taken to en sure an appropriate effective series resistance (esr) value. the esr of the output capacitor affects the stability of the ldo control loop. a minimum of 0.70 f capacitance with an esr of 1 ? or less is recommended to ensure stability of the adp122 / adp123 . t he t ransient response to changes in load current is also affected by the output capacitance. using a larger value of output capacitance improves the transien t response of the adp122 / adp123 to dynamic changes in load current. figure 32 and figure 33 show the transient responses for output capacitance values of 1 f and 4.7 f, respectively. 08399-026 ch1 200ma ? b w ch2 50.0mv b w m 400ns a ch1 196ma 1 2 t 14.80% v out v in = 3.7v v out = 3.3v 1ma to 300ma load step i out figure 32 . output transient response, c out = 1 f 08399-027 ch1 200ma ? b w ch2 20.0mv m 400ns a ch1 196ma 1 2 t 15.00% v out v in = 3.7v v out = 3.3v 1ma to 300ma load step i out figure 33 . output transient response, c out = 4.7 f input bypass capacitor connecting a 1 f capacitor from v in to gnd reduces the circuit sensitivity to the printed ci rcuit board (pcb) layout, especially when a long input trace or high source impedance is encountered. if greater than 1 f of output capacitance is required, the input capacitor should be increased to match it. inpu t and output capacitor properties any goo d quality ceramic capacitors can be used with the adp122 / adp123 , as long as the capacitor meet s the minimum capacitance and maximum esr requirements. ceramic capacitors are manu - factured with a variety of dielectrics, each with different behavior over tem perature and applied voltage. capacitors must have a n adequate dielectric to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. using an x5r or x7r dielectric with a voltage rating of 6.3 v or 10 v is recommended. h owever, using y5v and z5u dielectrics is not recommended for any ldo , due to their poor temperature and dc bias characteristics. figure 34 depicts the capacitance vs . capacitor voltage bias charac - teristic s of a 0603 , 1 f, 6.3 v x5r capacitor. the voltage stability of a capacitor is strongly influenced by the capacitor si ze and the voltage rating. in general, a capacitor in a larger package or of a higher voltage rating exhibit s better stability. the temperature variation of the x5r dielectric is about 15% over the ? 40c to + 85 c temperature range and is not a function of package or voltage rating. 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 0 1 2 3 4 5 6 7 bias vo lt age (v) ca p aci t ance (f) 08399-030 figure 34 . capacitance vs . capacitor voltage bias characteristic s equation 1 can be used to determine the worst - case capacitance , accounting for capacitor variation over temperature, component tolerance, and voltage. c eff = c (1 ? tempco ) (1 ? tol ) (1) where: c eff is the effective capacitance at the operating voltage. tempco is the worst - case capacitor temperature coefficient. tol is the worst - case component tolerance . in this example, the worst - case temperature coefficient (tempco) over ? 40c to +85c is assumed to be 15% for an x5r dielectric. the tolerance of the capacitor (tol) is assumed to be 10%, and c is 0.96 f at 4.2 v from the graph in figure 34. substituting these va lues in equation 1 yields c eff = 0.96 f (1 ? 0.15) (1 ? 0.1) = 0.734 f
data s heet adp122/adp123 rev. e | page 13 of 24 therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the ldo over tem - peratur e and tolerance at the chosen output voltage. to guarantee the performance of the adp122 / adp123 , it is imperative that the effects of dc bias, temperature , and tolerances on the behavior of the capacitors are evaluated for each application. undervoltage lo ckout the adp122 / adp123 ha ve an internal undervoltage lockout circuit that disables all inputs and the output when the input voltag e is less than approximately 2 v . this ensures that the adp122 / adp123 inputs and the output behave in a predictable manner du ring power - up. enable feature the adp122 / adp123 uses the en pin to enable and disable the v out pin under normal operating conditions. as shown in figure 35 , when a rising voltage on en crosses the active threshold, v o ut turns on. conversely, w hen a falling voltage on en crosses the inactive threshold, v out turns off. 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v en v out 08399-230 figure 35 . typical en pin operation as shown in figure 35 , the en pin has built - in hysteresis. this prevents on/ off oscillations that may occur due to noise on the en pin as it passes through the threshold points. the active and inactive thresholds of the en pin are derived from the v in voltage. therefore, these thresholds vary as the input voltage changes . figure 36 shows typical en active and inactive thresholds when the v i n voltage varies from 2.3 v to 5.5 v . 08399-034 0.5 0.6 0.7 0.8 0.9 1.0 1.1 2.2 2.7 3.2 3.7 4.2 4.7 5.2 v in (v) enable thresholds (v) rising falling figure 36 . typical en pin thresholds vs. input voltage the adp122 / adp123 utilize an internal soft start to limit the in - rush curre nt when the output is enabled. the start - up time for the 2 .8 v option is approximately 350 s from the time the en active threshold is crossed to when the output r eaches 90% of its final value. as shown in figure 37, t he start - up time is depend e nt on the output voltage setting and increases slightly as the output voltage increases. 08399-033 ch1 1.00v ch2 1.00v m200s a ch1 3.08v 2 1 t 600.000s v out = 2.8v v out = 3.3v v out = 4.2v v in = 5v figure 37 . typical start - up time
adp122/adp123 data sheet rev. e | page 14 of 24 current limit and th ermal overload protection the adp122 / adp12 3 are protected from damage due to excessive power dissipation by current and thermal overload protection circuits. the adp122 / adp123 are designed to limit the current when the output load reaches 500 ma (typical). when the output load exceeds 500 ma, the output voltage is reduced to maintain a constant current limit. thermal overload protection is included, which limits the junction temperature to a maximum of 150c typical. under extreme con - ditions (that is, high ambient temperature and power dissipation ) , when the junction temperature starts to rise above 150c, the output is turned off, reducing output current to zero. when the junction temperature cools to less than 135c, the output is turned on again and the output current is restored to its nominal value. consider the case where a hard short from v out to gnd occurs. at first , the adp122 / adp123 limit the current so that only 500 ma is co nducted into the short. if self - heating cause s the junction temperature to rise above 150c, thermal shutdown activa tes, turning off the output and reducing the output current to zero. when the junction temperature cools to less than 135c, the output turns on and conducts 500 ma into the short, again causing the junction temperature to rise above 150c. this thermal os cillation between 135c and 150c results in a current oscillation between 500 ma and 0 ma that continues as long as the short remains at the output. current and thermal limit protections are intended to protect the device from damage due to accidental ove rload conditions. for reliable operation, the device power dissipation must be externally limited so that the junction temperature do es not exceed 125c. thermal consideratio ns to guarantee reliable operation, the junction temperature of the adp122/adp123 must not exceed 125c. to ensure that the junction temperature is less than this maximum value, the user needs to be aware of the parameters that contribute to junction temperature changes. these parameters include ambient tem - perature, power dissipation i n the power device, and thermal resistances between the junction and ambient air ( ja ). the value of ja is dependent on the package assembly compounds used and the amount of copper to which the gnd p ins of the package are soldered on the pcb. table 6 shows typical ja values of the 5 - lead tsot package and 6 - lead lfcsp package for va rious pcb copper sizes. table 6 . typical ja values for specified pcb copper sizes copper size (mm 2 ) ja (c/w) tsot lfcsp 0 1 170 255 50 152 164 100 146 138 300 134 109 500 131 80 1 device soldered to narrow traces. the typical jb value s are 42.8c/w for tsot packages and 44.1c/w for lfcsp packages . the junction temperature of the adp122 / adp123 can be calculated from the following equation: t j = t a + ( p d ja ) ( 2 ) where: t a is the ambient temperature. p d is the power dissipation in the die, given by p d = [( v in ? v out ) i load ] + ( v in i gnd ) ( 3 ) where: i load is the load current. i gnd is the ground current. v in and v ou t are input and output voltages, respectively. the p ower dissipation due to ground current is quite small and can be ignored. therefore, the junction temperature equation can be simplified as follows: t j = t a + {[( v in ? v out ) i load ] ja } ( 4 ) as shown i n equation 4 , for a given ambient temperature, input - to - output voltage differential , and continuous load current, there exists a minimum copper size requirement for the pcb to ensure that the junction temperature does not rise above 125c. figure 38 through figure 44 show junction temperature calculations for different ambient temperatures, load currents, v in to v out differentials, and areas of pcb copper. in cases where the board temperature is known, t he thermal characterization parameter, jb , can be used to estimate the jun - ction temperature rise. the maximum junction temperature (t j ) is calculated from the board temperature (t b ) and power dissipation (p d ) using the formula t j = t b + ( p d jb ) (5)
data s heet adp122/adp123 rev. e | page 15 of 24 junction temperature calculations for tsot package 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 junction temperature (c) v out ? v in (v) i load = 1ma i load = 10ma i load = 25ma i load = 100ma i load = 150ma i load = 300ma t j max 08399-128 figure 38 . junction temperature vs. power dissipation, 500 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 junction temperature (c) v out ? v in (v) i load = 1ma i load = 10ma i load = 25ma i load = 100ma i load = 150ma i load = 300ma t j max 0.5 1.0 1.5 2.0 2.5 3.0 08399-129 figure 39 . junction temperature vs. power dissipation, 100 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 junction temperature (c) v out ? v in (v) i load = 1ma i load = 10ma i load = 25ma i load = 100ma i load = 150ma i load = 300ma t j max 0.5 1.0 1.5 2.0 2.5 3.0 08399-130 figure 40 . junction temperature vs. power dissipation, 0 mm 2 of pcb copper, t a = 25c 140 120 100 80 60 40 20 0 junction temperature (c) v out ? v in (v) i load = 1ma i load = 10ma i load = 25ma i load = 100ma i load = 150ma i load = 300ma t j max 0.5 1.0 1.5 2.0 2.5 3.0 08399-131 figure 41 . junction temperature vs. power dissipation, 500 mm 2 of pcb copper , t a = 50c
adp122/adp123 data sheet rev. e | page 16 of 24 140 120 100 80 60 40 20 0 junction temperature (c) v out ? v in (v) i load = 1ma i load = 25ma i load = 100ma i load = 150ma i load = 300ma t j max i load = 10ma 0.5 1.0 1.5 2.0 2.5 3.0 08399-132 figure 42 . junction temperature vs. power dissipation, 100 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 junction temperature (c) v out ? v in (v) i load = 1ma i load = 25ma i load = 100ma i load = 150ma i load = 300ma t j max i load = 10ma 0.5 1.0 1.5 2.0 2.5 3.0 08399-133 figure 43 . junction temperature vs. power dissipation, 0 mm 2 of pcb copper, t a = 50c 140 120 100 80 60 40 20 0 junction temperature (c) v in ? v out (v) i load = 1ma i load = 10ma i load = 50ma i load = 100ma i load = 150ma i load = 250ma i load = 300ma t j max 0.4 0.8 1.2 1.6 2.0 2.4 2.8 08399-134 figure 44 . junction temperature vs. power dissipation, board temperature = 85c
data s heet adp122/adp123 rev. e | page 17 of 24 junction temperature calculations f or lfcsp package 0 20 40 60 80 100 120 140 0.5 1.0 1.5 2.0 2.5 3.0 junction tempera ture (c) t j max v out ? v in (v) 08399-139 25ma 100ma 150ma 300ma 1ma 10ma figure 45 . junction temperature vs. power dissipation, 500 mm 2 of pcb copper, t a = 25c 0 20 40 60 80 100 120 140 0.5 1.0 1.5 2.0 2.5 3.0 junction tempera ture (c) t j max v out ? v in (v) 083 99-1 40 25ma 100ma 150ma 300ma 1ma 10ma figure 46 . junction temperature vs. power dissipation, 100 mm 2 of pcb copper, t a = 25c 3.0 0 20 40 60 80 100 120 140 0.5 1.0 1.5 2.0 2.5 junction tempera ture (c) t j max v out ? v in (v) 08 39 9- 14 1 25ma 100ma 150ma 300ma 1ma 10ma figure 47 . junction temperature vs. power dissipation, 500 mm 2 of pcb copper, t a = 50 c 0 20 60 80 100 120 140 0.5 1.0 1.5 2.0 2.5 3.0 junction tempera ture (c) t j max v out ? v in (v) 08399-142 25ma 100ma 150ma 300ma 1ma 10ma 40 figure 48 . junction temperature vs. power dissipation, 100 mm 2 of pcb copper, t a = 50c
adp122/adp123 data sheet rev. e | page 18 of 24 150ma 0 20 40 60 80 100 120 140 0.5 1.0 1. 5 2.0 2.5 3.0 junction tempera ture (c ) v ou t ? v in (v) t j max 08399-143 25m a 100ma 300ma 1ma 10ma figure 49 . junction temperature vs. power dissipation, 0 mm 2 of pcb copper, t a = 25c 0 20 40 60 80 100 120 140 0.5 1.0 1.5 2.0 2.5 3.0 junction tempera ture (c) v out ? v in (v) t j max 08399-145 25ma 100ma 150ma 300ma 1ma 10ma figure 50 . junction temperature vs. power dissipation, 0 mm 2 of pcb copper, t a = 50c 0 20 40 60 80 100 120 140 0.4 0.8 1.2 1.6 2.0 2.4 2.8 junct ion tempe ra ture (c) v out ? v in (v) 25ma 100ma 150 ma 300 ma t j max 1ma 10ma 083 99-1 44 figure 51 . junc tion temperature vs. power dissipation , board temperature = 85c
data s heet adp122/adp123 rev. e | page 19 of 24 printed circuit boar d layout considerati ons heat dissipation from the package can be improved by increasing the amount of copper attached to the pins of the adp122 / adp123 . however, as shown in table 6 , a point of diminishing returns eventually is reached, beyond which an increase in the copper size does not yield significant heat dissipation benefits. the input capacitor should be placed as close as possible to the v in and gnd p ins, and t he output capacitor should be placed as close as possible to the v out and gnd pins . use of 0402 or 0603 size capacitors and resistors achieves the smallest possible footprint solution on boards where the area is limited. 08399-041 figure 52 . example adp122 pcb layout 08399-042 figure 53 . example adp1 23 pcb layout
adp122/adp123 data sheet rev. e | page 20 of 24 outline dimensions 100708-a * compliant to jedec standards mo-193-ab with the exception of package height and thickness. 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 0.20 0.08 0.60 0.45 0.30 8 4 0 0.50 0.30 0.10 max * 1.00 max * 0.90 max 0.70 min 2.90 bsc 5 4 1 2 3 sea ting plane figure 54 . 5 - lead thin small outline transistor package [tsot] (uj - 5) dimensions show n in millimeters 1.70 1.60 1.50 0.425 0.350 0.275 t op view 6 1 4 3 0.35 0.30 0.25 bottom view pin 1 index are a sea ting plane 0.60 0.55 0.50 1.10 1.00 0.90 0.20 ref 0.05 max 0.02 nom 2.00 bsc sq 0.65 bsc exposed pa d pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 07- 1 1-20 1 1-b 0.175 ref figure 55 . 6- lead lead frame chip scale package [lfcsp _ud ] 2.00 m m 2.00 mm body, ultra thin, dual lead (cp - 6 - 3) dimensions shown in millimeters
data s heet adp122/adp123 rev. e | page 21 of 24 ordering guide model 1 temperature range output voltage (v) 2 package description package option branding adp122aujz - 1.8- r7 C 40c to +125c 1.8 5 - lead tsot uj -5 ljs adp122auj z - 2.5- r7 C 40c to +125c 2.5 5 - lead tsot uj -5 le6 adp122aujz - 2.7- r7 C 40c to +125c 2.7 5 - lead tsot uj -5 le9 adp122aujz - 2.8- r7 C 40c to +125c 2.8 5 - lead tsot uj -5 lea adp122aujz - 2.85-r7 C 40c to +125c 2.85 5 - lead tsot uj -5 lec adp122aujz - 2.9- r7 C 40c to +125c 2.9 5 - lead tsot uj -5 led adp122aujz - 3.0- r7 C 40c to +125c 3.0 5 - lead tsot uj -5 lee adp122aujz - 3.3- r7 C 40c to +125c 3.3 5 - lead tsot uj -5 lef adp122acpz - 1.8-r7 C 40c to +125c 1.8 6 - lead lfcsp _ud cp -6 -3 ljs adp122acpz - 2.0-r7 C 40c to +125 c 2.0 6 - lead lfcsp _ud cp -6 -3 ljt adp122acpz - 2.5-r7 C 40c to +125c 2.5 6 - lead lfcsp _ud cp -6 -3 le6 adp122acpz - 2.6-r7 C 40c to +125c 2.6 6 - lead lfcsp _ud cp -6 -3 lju adp122acpz - 2.8 - r7 C 40c to +125c 2.8 6 - lead lfcsp _ud cp - 6 - 3 lea adp122acpz - 3.0-r7 C 40c to +125c 3.0 6 - lead lfcsp _ud cp -6 -3 lee adp122acpz - 3.3-r7 C 40c to +125c 3.3 6 - lead lfcsp _ud cp -6 -3 lef adp123aujz -r7 C 40c to +125c 0.8 to 5.0 (adjustable) 5 - lead tsot uj -5 leg adp123acpz -r7 C 40c to +125c 0.8 to 5.0 (adjustable) 6 - lead lfcsp _ud cp -6 -3 leg adp122 - 3.3 - evalz 3.3 evaluation board adp123 - evalz adjustable evaluation board adp122ujz - redykit redykit 2.5,3.3 redykit 1 z = rohs compliant part. 2 up to 31 fixed - output voltage options from 1.75 v to 3.3 v are available. for additional voltage options, contact a local analog devices, in c., sales or distribution rep resentative.
adp122/adp123 data sheet rev. e | page 22 of 24 notes
data s heet adp122/adp123 rev. e | page 23 of 24 notes
adp122/adp123 data sheet rev. e | page 24 of 24 notes ? 2009 C 2012 analog devices, inc. all rights reserved. tradem arks and registered trademarks are the property of their respective owners. d08399 - 0- 6/12(e)

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