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the mark shows major revised points. 4-bit single chip microcontroller for remote control transmission document no. u12392ej4v0ds00 (4th edition) (previous no. ic-2014b) date published may 1997 n printed in japan m pd6125a, 6126a mos integrated circuit ? transmission-in-progress indication pin (s-out): 1 pin ? transmit carrier frequency (rem) f osc /12, f osc /8 ? standby operation (halt/stop mode) ? low power consumption ? current consumption in stop mode (t a = 25 c) 1 m a max. ? low-voltage operation: v dd = 2.0 to 6.0 v 1989 data sheet description the m pd6125a and 6126a are 4-bit single-chip microcontrollers for infrared remote controllers for tvs, vcrs, stereos, cassette decks, air conditioners, etc. these microcontrollers consist of rom, ram, a 4-bit parallel-processing alu, a programmable timer, key input/ output ports, and transmit output ports. functioning is controlled in software. caution to use the nec transmission format, ask nec to supply the custom code. the mask option (pla data) setting of m pd6125a, m pd6126a is different from that of the m pd6125, 6126. when a register is used as the operand of a branch instruction, do not use r 0 . features ? transmitter for programmable infrared remote controller ? 19 types of instructions ? instruction execution time: 17.6 m s (with 455-khz ceramic oscillator) ? program memory (rom) capacity: 1002 10 bits ? data memory (ram) capacity: 32 5 bits ? 9-bit programmable timer: 1 channel ? i/o pins (k i/o ): 8 pins ? i/o pins (i/o) ? m pd6125a: 4 pins ? m pd6126a: 8 pins ? input pins (k i ): 4 pins ? serial input pins (s-in): 1 pin the information in this document is subject to change without notice.
m pd6125a, 6126a 2 ordering information part number package m pd6125aca-xxx 24-pin plastic shrink dip (300 mil) m pd6125ag-xxx 24-pin plastic sop (300 mil) m pd6126ag-xxx 28-pin plastic sop (375 mil) remark xxx indicates a rom code suffix. pin configuration (top view) 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 i/o 03 i/o 02 i/o 01 i/o 00 s-in s-out rem v dd osc-out osc-in v ss ac k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 pd6125a m 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 i/o 11 i/o 10 i/o 03 i/o 02 i/o 01 i/o 00 s-in s-out rem v dd osc-out osc-in i/o 12 i/o 13 k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 pd6126a m 13 16 v ss k i2 14 15 ac k i3
m pd6125a, 6126a 3 block diagram i0 i3 k -k l h 32 5 bit ac i/o s-in rem s-out osc-in osc-out mod 10 bit osc note rom d.p. rom d.p. pc(h) mpx add dec mpx ram ram cntl (h) cntl (l) sp timer (l) timer (h) acc key in key out(h) key out(l) alu watchdog timer function pc(l) rom (l) rom (h) 1002 10 bit i/o k i/o0 -k i/07 note m pd6125a: i/o 00 -i/o 03 m pd6126a: i/o 00 -i/o 03 , i/o 10 -i/o 13 differences among products part number m pd6125a m pd6126a item rom capacity 1002 10 bits (mask rom) ram capacity 32 5 bits i/o pins 12 (k i/o0-7 , i/o 00-03 ) 16 (k i/o0-7 , i/o 00-03 , i/o 10-13 ) s-in pins provided current consumption (f osc = stop) (max.) 1 m a s-in high level input current (max.) 15 m a transmit carrier frequency f osc /12, f osc /8 low-voltage detection (reset) circuit not provided supply voltage v dd = 2.0 to 6.0 v package ? 24-pin plastic sop ? 28-pin plastic sop (300 mil) (375 mil) ? 24-pin plastic shrink dip (300 mil)
m pd6125a, 6126a 4 1. program counter (pc) 10 bits the program counter (pc) is a binary counter, which holds the address information for the program memory. figure 1-1. program counter organization pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc 8 pc 9 pc normally, the program counter contents are automatically incremented each time an instruction is executed, according to the number of instruction bytes. when executing a jump instruction (jmp0, jc, jf), the program counter indicates the jump destination. immediate data or the data memory contents are loaded to all or some bits of the pc. when executing the call instruction (call0), the pc contents are incremented (+1) and saved into the stack memory. then, a value needed for each jump instruction will be loaded. when executing the return instruction (ret), the stack memory contents are double incremented (+2) and loaded into the pc. when all clear is input or on reset, the pc contents are cleared to 000h. 2. stack pointer (sp) 2 bits this 2-bit register holds the start address information for the stack area. the stack area is shared with the data memory. the sp contents are incremented, when the call instruction (call0) is executed. they are decremented, when the return instruction (ret) is executed. the stack pointer is cleared to 00b after reset or all clear is input, and indicates the highest address fh for the data memory as the stack area. the figure below shows the relationship for the stack pointer and the data memory area. r c data memory r d r e r f (sp) 11b 10b 01b 00b if the stack pointer overflows or underflows, it is determined that the cpu overflows, and the pc internal reset signal will be generated.
m pd6125a, 6126a 5 3. program memory (rom) 1002 steps 10 bits the program memory (rom) is configured in 10 bits steps. it is addressed by the program counter. program and table data are stored in the program memory. figure 3-1. program memory map test program area 000h 0ffh 100h 1ffh 200h 2ffh 300h 3e9h 3eah 3ffh 4. data memory (ram) 32 words 5 bits the data memory is a ram of 32 words 5 bits. the data memory stores processing data. in some cases, the data memory is processed in 8-bit units. r 0 may be used as the data pointer for the rom. after power application, the ram will be undefined. the ram retains the previous data on reset. figure 4-1. data memory organization 1 r 0 0 r f r r b c sp-3 sp-2 sp-1 sp-0 to to caution avoid using the ram areas r d , r e , and r f in a call routine as much as possible because these areas are also used as stack memory areas (to prevent program hang-up in case the value of the sp is destroyed due to some reason such as noise). when using these ram areas as general-purpose ram areas, be sure to include stack pointer checking in the main routine.
m pd6125a, 6126a 6 5. data pointer (r 0 ) r 0 (r 10 , r 00 ) for the data memory can serve as the data pointer for the rom. r 0 specifies the low-order 8 bits in the rom address. the high-order 2 bits in the rom address are specified by the control register. table referencing for rom data can be easily executed by calling the rom contents by setting the rom address to the data pointer. when all clear is input or on reset, it becomes undefined. figure 5-1. data pointer organization ad 0 ad 1 ad 2 ad 3 ad 4 ad 5 ad 6 ad 7 ad 8 ad 9 control registers (p ) 1 r 0 r 10 r 00 6. accumulator (a) 4 bits the accumulator (a) is a 4-bit register. the accumulator plays a major role in each operation. when all clear is input or on reset, it becomes undefined. figure 6-1. accumulator organization a 0 a 1 a 2 a 3 a 7. arithmetic logic unit (alu) 4 bits the arithmetic logic unit (alu) is a 4-bit operation circuit, and executes simple operations, such as arithmetic operations. 8. flags (1) status flag when the status for each pin is checked by the stts instruction, if the condition coincides with the condition specified by the stts instruction, the status flag (f) is set (to 1). when all clear is input or on reset, it becomes undefined. (2) carry flag when the inc (increment) instruction or the rl (rotate left) instruction is executed, if a carry is generated from the msb for the accumulator, the carry flag (c) is set (to 1). the carry flag (c) is also set (to 1), if the contents for the accumulator are fh, when the scaf instruction is executed. when all clear is input or on reset, it becomes undefined.
m pd6125a, 6126a 7 9. system clock generation circuit the system clock generation circuit consists of an oscillation circuit, which uses a ceramic resonator (400khz to 500khz). figure 9-1. system clock generation circuit stop mode system clock osc-out osc-in in the stop mode (oscillation stop halt instruction), the oscillation circuit in the system clock generation circuit stops its operation, and the system clock ? is stopped.
m pd6125a, 6126a 8 10. timer the timer block determines the transmission output pattern. the timer consists of 10 bits, of which 9 bits serve as the 9-bit down counter and the remaining 1 bit serves as the 1-bit latch, which determines the carrier output validity. the 9-bit down counter is decremented (-1) every 8/f osc (s) in synchronization with the machine cycle, after starting down count operation. down counting stops after all of the 9 bits become 0. when down counting is stopped, the signal indicating that the timer operation has stopped, is output. if the cpu is at standby (halt timer) for the timer operation completion, the standby (halt) condition is released and the next instruction will be executed. if the next instruction again sets the value of the down counter, down counting continues without any error (the carrier output of the rem pin is not affected). set the down count time according to the following calculation; (set value (hex) + 1) x 8/f osc . setting the value to the timer is done by the timer manipulation instruction. when the down counter is operating, the remote control transmission carrier can be output to the rem pin. whether or not to output the carrier can be selected by the msb for the timer register block. set 1, when outputting the carrier, or 0, when not outputting the carrier. if all the down counter bits become 0, when outputting the carrier, the carrier output will be stopped. when not outputting the carrier, the rem pin output will become low level. a signal in synchronization with the rem output is output to the s-out pin. however, the waveform for the s- out pin is low, when the carrier is being output to the rem pin, or it is high, when the carrier is not being output to the rem pin. if the halt instruction, which initiates the oscillation stop mode, is executed when the down counter is operating, the oscillation stop mode is initiated after down counting is stopped (after 0). timer operation stop/run is controlled by the control register (p 1 ). (refer to 13. control register (p 1 ).) when all clear is input or on reset, the rem pin goes low and s-out pin goes high. all 10 bits of the timer are cleared to 000h. caution because the timer clock is not synchronized with the carrier output, the pulse width may be shortened at the beginning and end of the carrier output. figure 10-1. timer block organization sout rem carrier (fosc/12, fosc/8) selected by control register clear set by timer mainpulation instruction 9-bit down counter zero detection circuit d of control register p ( timer run/stop ) 21 1/0 msb fosc / 8
m pd6125a, 6126a 9 11. pin functions 11.1 k i/o pin (p 0 ) this is the 8-bit i/o pin for key-scan output. when the control register (p 1 ) is set for the input port, the port can be used as an 8-bit input pin. when the port is set for the input mode, all of these pins are pulled down to the v ss level inside the lsi. when all clear is input or on reset, input/output mode goes into effect, and the value of output latch becomes undefined. figure 11-1. k i/o pin organization k i/o7 k i/o6 k i/o5 k i/o4 k i/o3 k i/o2 k i/o1 k i/o0 p 0 p 10 p 00 (p ) countrol register 1 11.2 k i/o pull-down resistor organization v dd v ss cmos n-ch pin pull-down resistor input signal output signal input/output selection n-ch p-ch r when k i/o is set to the input mode, pull-down resistor r is turned on.
m pd6125a, 6126a 10 11.3 i/o pin (p 3 , p 4 note ) p 3 /p 4 are input/output pins for adding a key matrix. the lsb of control registers p 13 and p 14 switches between input and output modes. when in input mode, all pins are pulled down by the lsi to the v ss level. when all clear is input or on reset, input mode goes into effect, and the output latch value becomes undefined. figure 11-2. i/o pin organization in/out i/o 3 i/o 2 i/o 1 i/o 0 p 3 /p 4 in/out 0 ?input mode 1 ?output mode p 13 , p 14 note p 03 , p 04 note p3 ?i/o 00 to i/o 03 , p4 ?i/o 10 to i/o 13 note m pd6125a is not equipped with p 13 , p 14 , p 03 , and p 04 . 11.4 i/o pull-down resistor organization input/output selection cmos r nch pull-down resistor i/o pull-down resistor switch (mask option) v dd p-ch n-ch v ss pin output signal input signal the use of pull-down resistors for i/o can be selected by using the mask option. when the pull-down resistor switch is turned on (1 is set) by the mask option, the pull-down resistor r is turned on only in input mode. caution when using the pins as key switches, turn on the pull-down resistor switch by the mask option.
m pd6125a, 6126a 11 11.5 k i pin (p 12 ) this is the 4-bit pin for key input. all of these pins can be pulled down to the v ss level by mask option. figure 11-3. k i pin organization p 12 k i3 k i2 k i1 k i0 p 2 mask option 11.6 k i pull-down resistor organization v dd v ss n-ch v ss pin input signal k pull-down resistor switch (mask option) pull-down resistor i p-ch when the pull-down resistor switch is turned on (set 1) by the mask option, pull-down resistor r is turned on. caution when using the pin as the key switch, turn on the pull-down resistor switch by the mask option.
m pd6125a, 6126a 12 11.7 s-out pin by going low whenever the carrier frequency is output from the rem pin, the s-out pin indicates that communication is in progress. the s-out pin is a cmos output pin. the s-out pin goes high on reset. 11.8 s-in pin (d 0 bit of p 1 ) to input serial data, use the s-in pin. when control register (p 1 ) is set to serial input mode, the s-in pin is connected as an input to the lsb of the accumulator. the s-in pin can be pulled down to the v ss level by a mask option from within the lsi. in this state, if the rotate-left accumulator instruction (rl a) is executed, the data on the s-in pin is copied to the lsb of the accumulator. if the control register is released from serial input mode, the s-in pin goes into a high-impedance state, but no through current flows internally. when the rl a instruction is executed, the msb is copied to the lsb. when all clear is input or on reset, the s-in pin goes into a high-impedance state. figure 11-4. the s-in pin organization a 3 a 2 a 1 a 0 cy control register s-in mask option
m pd6125a, 6126a 13 12. port register (p ) k i/o , i/o, k i , and the control register are handled as port registers. the table below shows the relations between the port registers and pins. table 12-1. relations between port registers and pins pin input mode output mode name read write read write on reset k i/o pin status output latch pin status output latch undefined [i/o mode, output latch] k i pin status C C C input mode i/o 0 input mode i/o 1 output latch is undefined. s-in pin status is read by rl a instruction when d 0 of p 1 register = 1. high impedance (d 0 of p 1 register = 0) p 1 (h) p 0 (l) p 10 p 11 p 12 p 00 p 01 p 02 k i/o7-4 k i/o3-0 p 0 p 1 p 2 control register (h) control register (l) k i3-0 in/out in/out i/o 0 i/o 1 p 13 p 03 p 14 p 04 p 3 p 4 caution the m pd6125a is not equipped with i/o 10 -i/o 13 pins. pin status output latch pin status output latch
m pd6125a, 6126a 14 13. control register (p 1 ) the control register contains of 10 bits. the controllable items are shown in table 13-1. table 13-1. control register (p1) d 0 .......................... specifies data to be input to a 0 when the accumulator is shifted to the left. 0: a 3 , 1: s-in d 1 .......................... specifies the status of k i/o , as follows: 0: input mode, 1: output mode d 2 .......................... specifies the status of the timer, as follows: 0: count stop, 1: count execution d 3 .......................... specifies the carrier frequency output from the rem pin. 0: f osc /8, 1: f osc /12 d 4 , d 5 ................. specify the high-order 2 bits of the rom data pointer. d 6 .......................... determines what happen to the oscillation circuit when the halt instruction is executed. 0: oscillation does not stop 1: oscillation stops (stop mode) d 7 .......................... be sure to reset this bit to 0. d 8 , d 9 ................. these bits specify test modes. be sure to reset them to 0. remark d 0 = d 8 = d 9 = 0 on reset, and the other bits are undefined. bit d 9 name test mode be sure to reset to 0. 0 1 set value timer d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 halt d.p. ad mod k i/o 9 d.p. ad 8 rl a a cc 0 ? stop nop f /8 ad =0 9 ad =0 8 osc in run osc stop f /12 ad =1 9 ad =1 8 osc out a 3 s-in
m pd6125a, 6126a 15 14. standby function (halt instruction) the m pd6600a is provided with the standby mode (halt instruction), in order to reduce the power consumption, when not executing the program. clock oscillation can be stopped in the standby mode (stop mode). in the standby mode, the program execution stops. however, the contents of the internal registers and the data memory are all retained. 14.1 stop mode (oscillation stop halt instruction) in the stop mode, the operation of the system clock generation circuit (ceramic resonator oscillation circuit) stops. therefore, operations requiring the system clock will stop. if the halt instruction is executed during timer operation, the program counter stops. the oscillation stop mode will be initiated, after the timer count down operation is completed. 14.2 halt mode (oscillation continue halt instruction) the cpu stops its operation, until the halt release condition is satisfied. the system clock operation continues in this mode. 14.3 standby release conditions (1) s-in input (2) k i/o input (3) k i input (4) timer count down operation completion (5) i/o input (6) k i , i/o input remark either high level or low level can be specified for setting a release condition by input. table 14-1. standby mode releasing condition d 3 0/1 0 releasing condition: 0 1 timer 01 00 k 0 0 s-in d 2 d 1 d 0 releasing condition 1 0 1 0 i/o k i remarks released when 0. valid only in the in mode. when rl a is selected, the standby mode is always released. 3 ? "0"?ow level detection "1"?igh level detection 10 1 0 i/o 1 0 0 i/o 1 valid only in the in mode. 111 k i , i/o 0 , i/o 1 0 judged as an error and initialized even if one of the i/o is in out mode. 0/1 caution m pd6125a is not equipped with i/o 10 - i/o 13 pins.
m pd6125a, 6126a 16 15. ac pin (all clear pin) internal part of the cpu including the program counter can be reset by setting the ac pin to the low level. watchdog timer function a power-on reset function and a cr watchdog timer function, that can be controlled by program, can be realized by connecting a 0.1 m f capacitor across the ac pin and the v ss . v dd 0.1 f m 0.1 f m v v dd v thl t charge mode charge start instruction execute halt instruction immediately before nop. (charge for 0.4 ms or more) discharge mode charge-discharge pattern discharge start instruction discharge starts after the nop instruction execution. (discharge time is about 5 ms from v to v ) the pattern must be controlled by the program, in such a manner that the c charge level will not go below v . thl dd th caution when the watchdog timer function is not used, switch to charging mode by executing a nop instruction immediately before a halt instruction at the beginning of the program. (be sure to connect the capacitor.)
m pd6125a, 6126a 17 16. mask options (pla data) the following items can be selected by mask option selection: ? provide/not provide k i , i/o, s-in pin pull-down resistor ? carrier duty selection (1/2, 1/3) at f osc /12 ? hang-up detection specification mask option data should be registered at the object code end. bit assignment by switch selection msb lsb corresponding portion 765432 10 0 k i k i0 k i1 k i2 k i3 0 pull-down resistor s-in 1 duty 00 0 duty 0 0 pull-down 0 s-in selection resistor 2 hang up detection k i/o halt halt halt halt halt i/o 0 i/o 1 all s-in k i/o k i i/o 0 i/o 1 all all 3 i/o 0 i/o 00 i/o 01 i/o 02 i/o 03 0 pull-down resistor 4 i/o 1 i/o 10 i/o 11 i/o 12 i/o 13 0 pull-down resistor caution m pd6125a is not equipped with i/o 10 - i/o 13 pins. switch for data (1) pull-down resistor when 0 not provided (off) when 1 provided (on) (2) modulation duty (at f osc /12) when 0 1/2 duty when 1 1/3 duty (3) hang-up detection <1> k i/o all, i/o 0 all, i/o 1 all if the switch for hang-up detection k i/o all (i/o 0 all, i/o 1 all) is set to on (1) by mask option, the system is reset, if in oscillation halt (stop) mode, the k i/o (i/o 0 , i/o 1 ) pin is in input mode, or if at least one of the k i/o (i/o 0 , i/o 1 ) pins is low (ac pin discharge mode). when 0 no reset function (off) when 1 reset function (on) caution to use a pin as a key source of a key matrix, be sure to set the switch to on by mask option. address
m pd6125a, 6126a 18 figure 16-1. hang-up detection k i/o all organization v dd to reset circuit hang-up detection k all switch (mask option) k output signal i/o0 k output signal i/o1 k output signal i/o2 k output signal i/o3 k output signal i/o4 k output signal i/o5 k input/output selection i/o k output signal i/o6 k output signal i/o7 i/o remark the above is also applicable to i/o 0 all, i/o 1 all. <2> halt releasing condition specification (s-in, k i/o , k i , i/o 0 , i/o 1 ) if the condition specified by mask option to be unused is satisfied in the halt mode, the system is reset. when 0 used when 1 unused caution be sure to specify the halt mode of the unused releasing condition to be unused (set).
m pd6125a, 6126a 19 17. program development tools to develop programs for the m pd6125a, 6126a, an assembler and an emulator for the m pd612x series are available from i.c. corp. for details, contact ic corp. 18. ordering rom code <1> to generate the data required for ordering a mask rom, after assembling the program, convert the hex file to a rom file by using the prom utility program "updprom". caution when using "updprom" select "27256" for prom type. <2> confirm that the instruction rom code data is stored in addresses 0 through 7d3h of the prom. also confirm that the mask option rom code data are stored in the following addresses. m pd6125a: addresses 7ff0h through 7ff3h m pd6126a: addresses 7ff0h through 7ff4h
m pd6125a, 6126a 20 19. instruction set accumulator manipulation instructions anl anl anl anl orl orl orl orl xrl xrl xrl xrl inc rl a, r a, @r h a, @r l a, #data a a d10 d30 d31 e00 e10 e30 e31 a00 a10 a30 a31 a13 f13 d00 e01 a01 d01 e02 a02 d02 e0f a0f d0f e20 a20 d20 e21 a21 d21 e2f a2f d2f r 10 r 11 r 12 r 1f r 00 r 01 r 0f r r r 0 0 a, r a, @r h a, @r l a, #data r 0 0 a, r a, @r h a, @r l a, #data r 0 0 input/output instructions p a, p , a, a, a, in out anl orl xrl f19 219 d19 e19 a19 p p 11 p p p a p p p p p p p f18 218 d18 e18 a18 p 10 f1a 21a d1a e1a a1z p 12 f39 239 d39 e39 a39 p 01 f38 238 d38 e38 a38 p 00 f3c 23c d3c e3c a3c 04 p out 319 p p 1 p p #data 318 p 0 31a p 2 p f3a 23a d3a e3a a3a 02 f1b 21b d1b e1b a1b p 13 f1c 21c d1c e1c a1c p 14 p f3b 23b d3b e3b a3b 03 31b p 3 31c p 4 p 1p and p 0p operate in pair format data transfer instructions mov mov f00 f10 f01 f02 f0f f20 f21 f2f a, r a, @r h r 0 r 10 r 11 r 12 r 1f r 00 r 01 r 0f r r mov f30 a, @r h 0 mov f31 a, #data mov mov 300 301 302 30f r , #data r , @r r r r 0 r 1 r 2 r f r r 320 321 322 32f mov r , a r 200 201 202 20f 220 221 22f 0 r 1r and r 0r operate in pair format
m pd6125a, 6126a 21 branch instructions r r r 0 r 1 r 2 r f jmp0 jc jc jnc jnc jf jf jnf jnf addr addr r addr addr addr 411 611 631 711 731 r r r r r r r 601 621 701 721 602 622 702 722 60f 62f 70f 72f ? pair register jmp0 r r 401 402 40f note note note note note note r = 1 C f r = 0 cannot be used. subroutine instructions addr call0 ret 411 p 1 p p 312 412 p 0 timer/counter manipulation instructions a, t , t, t, mov mov mov mov f1f 21f t 1 t t t a #data @r t 0 31f 33f t 0-1 t 0 t f3f 23f other instructions halt #data stts r stts #data scaf nop 00 r 111 131 d13 000 01 r 02 r 0f r 120 121 122 12f 0r
m pd6125a, 6126a 22 20. typical application circuit example (1) m pd6125a application circuit example 1 2 3 4 5 i/o 03 i/o 02 i/o 01 i/o 00 s-in k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 24 23 22 21 20 19 18 17 16 15 14 13 s-out rem v dd osc-out osc-in v ss ac pd6125a m mode selection switch key matrix (8 8 = 64 keys) 6 7 8 9 10 11 12 c2 c1 0.1 f m + 47 f m 2.0 w se303a-c se307-c se313 se1003-c 2sc2001, 3616 2sd1513, 1614 2sd1616 v dd (no carrier) (with carrier) 3.0 v caution the ceramic resonator start-up capacitor value must be determined, by taking the voltage level and the oscillation start-up characteristics for the ceramic resonator into consideration.
m pd6125a, 6126a 23 (2) m pd6126a application circuit example 1 2 3 4 5 i/o 11 i/o 10 i/o 03 i/o 02 i/o 01 k i/o0 k i/o1 k i/o2 k i/o3 k i/o4 k i/o5 k i/o6 k i/o7 k i0 k i1 k i2 k i3 26 25 24 23 22 21 20 19 18 17 16 15 s-out rem v dd osc-out osc-in v ss ac pd6126a m mode selection switch key matrix (8 12 = 96 keys) 8 9 10 11 12 13 14 100 pf 100 pf 0.1 f m + 47 f m 2.0 w se303a-c se307-c se313 se1003-c 2sc2001, 3616 2sd1513, 1614 2sd1616 v dd (no carrier) (with carrier) 3.0 v 6 i/o 00 7 s-in i/o 12 i/o 13 28 27 caution the ceramic resonator start-up capacitor value must be determined, by taking the voltage level and the oscillation start-up characteristics for the ceramic resonator into consideration.
m pd6125a, 6126a 24 21. electrical specifications absolute maximum ratings (t a =25 c) parameter symbol ratings unit supply voltage v dd C0.3 to +7.0 v input voltage v in C0.3 to v dd +0.3 v operating ambient temperature t a C20 to +75 c storage temperature t stg C40 to +125 c caution if the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. absolute maximum ratings therefore specify the values exceeding which the product may be physically damaged. never exceed these values when using the product. recommended operating range (t a = C20 to +75 c) parameter symbol min. typ. max. unit supply voltage v dd 2.0 6.0 v oscillation frequency f osc 400 500 khz
m pd6125a, 6126a 25 dc characteristics (v dd = 3.0v, f osc = 455khz, t a =25 c) parameter symbol conditions min. typ. max. unit supply voltage v dd 2.0 6.0 v current dissipation 1 i dd1 f osc = 455 khz 0.3 1.0 ma current dissipation 2 i dd2 f osc = stop 1.0 m a rem high level output current i oh1 v o = 1.0 v C5 C8 ma rem low level output current i ol1 v o = 0.3 v 0.5 1.5 2.5 ma s-out high level output current i oh2 v o = 2.7 v C0.3 C1.0 C2.0 ma s-out low level output current i ol2 v o = 0.3 v 1 1.5 ma k i high level input current i ih1 v i = 3.0 v 10 30 m a k i high level input current i ih1' v i = 3.0 v, without pull-down resistor 0.2 m a k i low level input current i il1 v i = 0 v C0.2 m a k i/o , i/o high level input current i ih2 v i = 3.0 v 10 30 m a k i/o , i/o high level input current i ih2' v i = 3.0 v, without pull-down resistor 0.2 m a k i/o , i/o low level input current i il2 v i = 0 v C0.2 m a k i/o , i/o high level output current i oh3 v o = 2.5 v C1.5 C2.0 C4.0 ma k i/o , i/o low level output current i ol3 v o = 2.1 v 25 50 100 m a k i , i/o high level input voltage v ih1 2.1 3.0 v k i , i/o low level input voltage v il1 0 0.9 v k i/o high level input voltage v ih2 1.3 3.0 v k i/o low level input voltage v il2 0 0.4 v ac pull-up resistor r 1 v i = 0 v 0.3 3.0 k w ac pull-down resistor r 2 v i = 2.7 v 150 400 1500 k w ac high level input voltage v ih3 1.8 3.0 v ac low level input voltage v il3 0 1.2 v recommended ceramic resonator external capacitance (pf) oscillation voltage range (v) manufacturer product c1 c2 min. max. remarks csb375p 220 220 2.0 3.3 csb400p 220 220 2.0 5.0 murata mfg. co., ltd. csb455e 100 100 2.0 5.0 csb480e 100 100 2.0 5.0 csb500e 100 100 2.0 3.3 crk400 100 100 2.0 6.0 toko ceramic co., ltd. crk455 100 100 2.0 6.0 crk500 100 100 2.0 6.0
m pd6125a, 6126a 26 22. characteristics curve (target value) 5.0 (t = 25 3 ?) a 0 0.2 low-level output voltage v [v] ol i vs v characteristic examples (rem) ol ol 4.0 3.0 2.0 1.0 low-level output current i [ma] ol 0.4 0.6 0.8 1.0 (t = 25 3 ?) a i vs v characteristic examples (rem) oh oh 10.0 5.0 high-level output current i [ma] oh 0 0.5 high-level output voltage v [v] oh 1.0 1.5 2.0 2.5 3.0 (t = 25 3 ?) a i vs v characteristic examples (s-out) ol ol (t = 25 3 ?) a i vs v characteristic examples (s-out) oh oh 3.0 2.0 low-level output current i [ma] ol 4.0 5.0 1.0 00 2.0 high-level output current i [ma] oh 1.0 3.0 0.2 low-level output voltage v [v] ol 0.4 0.6 0.8 1.0 2.0 high-level output voltage v [v] oh 2.2 2.4 2.6 2.8 3.0 (t = 25 3 ?) a i vs v characteristic examples (k -k , i/o) ol ol (t = 25 3 ?) a i vs v characteristic examples (k -k ) ol ol 50 low-level output current i [ a] ol 00 50 low-level output current i [ a] ol low-level output voltage v [v] ol 1.0 2.0 3.0 low-level output voltage v [v] ol 1.0 2.0 3.0 m m i/o0 i/o3 i/o0 i/o7 v = 3 v dd v = 3 v dd v = 3 v dd v = 3 v dd v = 3 v dd v = 3 v dd
m pd6125a, 6126a 27 (t = 25 3 ?) a i vs v characteristic examples (k , i/o) oh oh i/o 2.2 2.4 2.6 2.8 3.0 4.0 3.0 2.0 1.0 0 high-level output voltage v [v] oh high-level output current i [ma] oh v = 3 v dd
m pd6125a, 6126a 28 23. package drawings (1) m pd6125a package drawings (1/2) 16-pin plastic sop (300 mil) (units in mm) fig. blank a 24 pin plastic shrink dip (300 mil) i h j g f d b n m c k l m r note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. s24c-70-300b-1 item millimeters inches a b c d f g h i j k 23.12 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 7.62 (t.p.) 5.08 max. 6.5 n 0~15 0.50?.10 0.85 min. r 0.911 max. 0.070 max. 0.020 0.033 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.300 (t.p.) 0.256 0.010 0.007 0~15 +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 24 13 112 a
m pd6125a, 6126a 29 item millimeters inches a b c e f g h i j 15.54 max. 1.27 (t.p.) 1.8 max. 1.55 7.7?.3 0.78 max. 0.12 1.1 5.6 m 0.1?.1 n 0.612 max. 0.031 max. 0.004?.004 0.071 max. 0.061 0.303?.012 0.220 0.043 0.005 0.050 (t.p.) p24gm-50-300b-4 p3 3 +7 note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. d 0.40 0.016 +0.10 ?.05 k 0.20 0.008 +0.10 ?.05 l 0.6?.2 0.024 0.10 ? +7 ? 0.004 +0.008 ?.009 +0.004 ?.002 +0.004 ?.003 a c d g p detail of lead end f e b h i l k m j n m 112 13 24 24 pin plastic sop (300 mil)
m pd6125a, 6126a 30 (1) m pd6125a package drawings (2/2) 24-pin shrink dip for es (reference) (unit in mm) fig. blank c
m pd6125a, 6126a 31 24-pin ceramic mini flat package for es (reference) (unit in mm)
m pd6125a, 6126a 32 (2) m pd6126a package drawings (1/2) 20-pin plastic sop (300 mil) (units in mm) fig. blank e 28 pin plastic sop (375 mil) item millimeters inches a b c e f g h i j 18.07 max. 1.27 (t.p.) 2.9 max. 2.50 10.3?.3 0.78 max. 0.12 1.6 7.2 m 0.1?.1 n 0.712 max. 0.031 max. 0.004?.004 0.115 max. 0.098 0.406 0.283 0.063 0.005 0.050 (t.p.) p28gm-50-375b-3 p3 3 +7 a g note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. d 0.40 0.016 +0.10 ?.05 k 0.15 0.006 +0.10 ?.05 l 0.8?.2 0.031 0.15 ? +7 ? 0.006 +0.009 ?.008 +0.004 ?.002 +0.004 ?.003 +0.012 ?.013 p detail of lead end 114 28 15 m f e c dm b l k h i j n
m pd6125a, 6126a 33 (2) m pd6126a package drawings (2/2) 28-pin ceramic sop for es (reference) (unit in mm) fig. blank f
m pd6125a, 6126a 34 24. recommended soldering conditions it is recommended that m pd6125a and 6126a be soldered under the following conditions. for details on the recommended soldering conditions, refer to information document semiconductor device mounting technology manual (c10535e) . for other soldering methods and conditions, consult nec. table 24-1. surface-mount type soldering conditions (1) m pd6125ag-xxx: 24-pin plastic sop (300 mil) symbol for soldering method soldering conditions recommended condition infrared reflow package peak temperature: 230 c, time: 30 seconds max. (210 c min.), ir30-00-1 number of times: 1 vps package peak temperature: 215 c, time: 40 seconds max. (200 c min.), vp15-00-1 number of times: 1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per device side) C (2) m pd6126ag-xxx: 28-pin plastic sop (375 mil) symbol for soldering method soldering conditions recommended condition infrared reflow package peak temperature: 230 c, time: 30 seconds max. (210 c min.), ir30-00-1 number of times: 1 vps package peak temperature: 215 c, time: 40 seconds max. (200 c min.), vp15-00-1 number of times: 1 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., number of times: 1 ws60-00-1 pre-heating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per device side) C caution use more than one soldering method should be avoided (except in the case of partial heating). table 24-2. insertion type soldering conditions m pd6125aca-xxx: 24-pin plastic shrink dip (300 mil) soldering method soldering conditions wave soldering (only for pin) solder bath temperature: 260 c max., time: 10 seconds max. partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin) caution wave soldering is only for pins in order that jet solder can not contact with the chip directly.
m pd6125a, 6126a 35 appendix m pd612x series products part number m pd6124a m pd6600a m pd61p24 m pd6125a m pd6126a item rom capacity 1002 10 bits 512 10 bits 1002 10 bits 1002 10 bits (mask rom) (mask rom) (one-time prom) (mask rom) ram capacity 32 5 bits i/o pins 8 pins (k i/o0-7 ) 12 pins 16 pins (k i/o0-7 ,(k i/o0-7 , i/o 00-03 ) i/o 00-03 , i/o 10-13 ) s-in pins provided current consumption 2 m a1 m a (f osc = stop) (max.) s-in high level input 30 m a 15 m a current (max.) transmit carrier frequency f osc /12, f osc /8 low-voltage detector provided not provided (reset) circuit mask option provided not provided provided (fixed) supply voltage v dd = 2.0 to 5.5 v v dd = 2.2 to 3.6 v v dd = 2.2 to 5.5 v v dd = 2.0 to 6.0 v package ? 20-pin plastic sop (300 mil) ? 24-pin plastic ? 28-pin plastic ? 20-pin plastic shrink dip (300 mil) sop (300 mil) sop (375 mil) ? 24-pin plastic shrink dip (300 mil)
m pd6125a, 6126a 36 [memo]
m pd6125a, 6126a 37 [memo]
m pd6125a, 6126a 38 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconduc- tor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
m pd6125a, 6126a 39 nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd6125a, 6126a no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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