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tundra semiconductor corporation tsi148 ? pci/x-to-vme bus bridge user manual document number: 80a3020_ma001_08 document status: final release date: september 2006 this document discusses the features, capabilities, and configuration requirements of tsi148. it is intended for hardware and software engineers who are designing system interconnect applications with tsi148. titlepage - 80a3020_ma001_08
trademarks tundra is a registered trademark of tundra semiconductor corporation (canada, u.s., and u.k.). tundra, the tundra logo, tsi148, and silicon behind the network, are trademarks of tundra semiconductor corporation. all other registered and unregistered marks (including trad emarks, service marks and logos) are the property of their respective owners. the absence of a mark identifier is not a representation that a particular product name is not a mark. copyright copyright ? september 2006 tundra semiconductor corporation. all rights reserved. published in canada this document contains information which is propri etary to tundra and may be used for non-commercial purposes within your organization in support of tundra products. no other use or transmission of all or any part of this document is permitted without written permission from tundra, and must include all copyright and other proprietary notices. use or transmission of all or any part of this document in violation of any applicable canadian or other legislation is hereby expressly prohibited. user obtains no rights in the information or in any product, process, technology or trademark which it includes or describes, and is expressly prohibited from modifying the information or creating derivative works without the express written consent of tundra. disclaimer tundra assumes no responsibility for the accuracy or completeness of the information presented which is subject to change without notice. in no event will tundra be liable for any direct, indir ect, special, incidental or consequential damages, including lost profits, lost business or lost data, resulting from the use of or reliance upon the information, whether or not tundra has been advised of the possibility of such damages. mention of non-tundra products or services is for information purposes only and constitutes neither an endorsement nor a recommendation.
tsi148 pci/x-to-vme bus bridge user manual 3 80a3020_ma001_08 corporate profile about tundra tundra semiconductor corporation (tundra)(tsx:tun) designs, develops, and markets system interconnect for use by the world's leading communications infrastructure equipment and storage companies. tundra system interconnect is a vital communications technology that enables customers to connect critical system components while compressing development cycles and maximizing performance. tundra products offer value to a range of applications, including wireless infrastructure, storage, networking access, military applications, and industrial automation. tundra headquarters are located in ottawa, ontario, canada. the company also has a design center in south portland, maine, united states and a sales office in maidenhead, u.k. tundra sells its products worldwide through a network of direct sales personnel, independent distributors and manufacturing representatives. tundra employs about 200 employees worldwide. greater demand, greater opportunity the ever-increasing demand for bandwidth, scalability, and reliability, driven by the growth of the internet, has created unprecedented performance challenges for interconnect technologies. regardless of whether it is a high-speed router, a next-generation wireless base station, or a storage sub system, tundra provides the system interconnect to meet the bandwidth demands for greater performance throughout the communications and data pipeline. tundra system interconnect tundra uses the term system interconnect to refer to the technology used to connect all the components and sub-systems in almost any embedded system. this concept applies to the interfacing of functional elements (cpu, memory, i/o complexes) within a single-board system, and the interconnection of multiple boards in a larger system. advanced communications networks need advanced system interconnect. it is a vital enabling technology for the networked world. tundra system interconnect provides the latest interface and throughput features, which enable communications infrastructure vendors to design and build more powerful, faster equipment in shorter timeframes.
corporate profile tsi148 pci/x-to-vme bus bridge user manual 4 80a3020_ma001_08 partnerships fundamental to the success of tundra is its partnerships with leading technology companies, including ibm, intel and motorola. as a result of these alliances, tundra devices complement our partners? products, and greatly influence the design of customers? architecture. customers are changing their designs to incorporate tundra products. this is evidence of tundra?s commitment to be a significant part of its customers? success. customers the world's leading communications infrastructure and storage vendors use tundra semiconductor products. these vendors include cisco systems, motorola, siemens, nortel networks, lucent technologies, nokia, ericsson, alcatel, and hewlett-packard. the tundra design philosophy is one in which a number of strategic customers are invited to participate in the definition, design, test, and early silicon phases of product development. close working relationships with customers and clear product roadmaps ensure that tundra can anticipate and meet the future directions and needs of communications systems designers and manufacturers. support tundra is respected throughout the industry for its outstanding commitment to customer support. tundra ensures that its customers can take immediate advantage of the company?s products through telephone access to its in-house applications engineering group, unmatched design support tools, and full documentation accessible though the web. tundra system interconnect ? silicon behind the network ?
tsi148 pci/x-to-vme bus bridge user manual 5 80a3020_ma001_08 contact information tundra is dedicated to providing tsi148 custom ers with superior technical documentation and support. tsi148 collateral and support are available on the tundra web site at www.tundra.com. customers may also contact tundra through the following means: email technical support use http://www.tundr a.com/support/supportform.com to send technical questions and feedback to our technical support team. documentation feedback use docfeedback@tundra.com to provide feedback on the tsi148 pci/x-to-vme bus bridge user manual. mailing address tundra semiconductor corporation 603 march road ottawa, on k2k 2m5
contact information tsi148 pci/x-to-vme bus bridge user manual 6 80a3020_ma001_08
tsi148 pci/x-to-vme bus bridge user manual 7 80a3020_ma001_08 contents corporate profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 contact information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 about this document. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 document conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 related information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1. functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.1 overview of tsi148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.1.1 vme renaissance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.1.2 tsi148 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.1.3 tsi148 benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.1.4 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.2 vmebus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.2.1 2evme protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.2.2 2esst protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.2.3 vme slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.2.4 vme master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 1.2.5 tsi148 as a vmebus system controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.3 pci/x interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.3.1 pci/x target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.3.2 pci/x master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.4 linkage module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1.5 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.5.1 control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.6 dma controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 1.6.1 data movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
contents tsi148 pci/x-to-vme bus bridge user manual 8 80a3020_ma001_08 1.7 interrupter and interrupt handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 1.8 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2. vme interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 2.1 overview of the vme interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.2 vme slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.2.1 vme slave buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.3 vme master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 2.3.1 addressing capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 2.3.2 vme master buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.3 vme master read-modify write (rmw) cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 2.3.4 vme master bandwidth control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.3.5 vmebus exception handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.3.6 utility functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2.3.7 tsi148 as a vmebus system controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3. pci/x interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.1 overview of the pci/x interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.2 pci mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.2.1 pci target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 3.2.2 pci master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.2.3 pci bus exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.3 pci-x mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.3.1 pci-x target. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.3.2 pci-x master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 3.3.3 pci-x bus exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4. dma interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 4.1 overview dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2 architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.3 dma buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.4 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.4.1 linked-list descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
contents tsi148 pci/x-to-vme bus bridge user manual 9 80a3020_ma001_08 4.5 direction of data movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.5.1 pci/x-to-vme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.5.2 vme-to-pci/x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.5.3 pci/x-to-pci/x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.5.4 vme-to-vme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 14 4.5.5 data patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.5.6 dma transaction termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.5.7 dma interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 4.5.8 transfer throttling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 5. resets, clocks, and power-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.1 overview of resets, clocks, and power-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.2 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.2.1 reset inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 5.2.2 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.3 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 5.4 power-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.4.1 pci/x power-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.4.2 vmebus power-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 5.4.3 system controller (scon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6. interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.1 overview of the interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.2 vmebus interrupter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.3 local interrupter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.4 vmebus interrupt handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 7. jtag module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 7.1 overview of jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 7.2 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8. signals and pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 8.1 overview of signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 8.2 signal grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8.3 signal summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.4 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 8.4.1 pci/x signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 8.4.2 vmebus signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.4.3 miscellaneous signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
contents tsi148 pci/x-to-vme bus bridge user manual 10 80a3020_ma001_08 8.5 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 8.5.1 sorted by pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 9. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 9.1 overview of electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 9.1.1 pci/x electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 9.1.2 non-pci electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 9.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 9.2.1 absolute maximum operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 9.2.2 recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 9.3 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 9.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 9.5 electrostatic discharge (esd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 9.5.1 esd precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 10. registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 10.1 overview of registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 10.2 register groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 10.2.1 combined register group (crg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 10.2.2 pci/x configuration space registers (pcfs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10.2.3 local control and status registers (lcsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10.2.4 global control and status registers (gcsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10.2.5 control and status registers (csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10.2.6 cr/csr register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.3 register endian mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 10.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 10.4.1 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 10.4.2 pcfs register group overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 10.4.3 lcsr register group overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 10.4.4 gcsr register group overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 10.4.5 cr/csr register group overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 10.4.6 pcfs register group description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 10.4.7 vendor id/ device id registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 10.4.8 command/status registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 10.4.9 revision id / class code registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 10.4.10 cache line size / master latency timer / header type registers . . . . . . . . . . . . . . . 220 10.4.11 memory base address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 10.4.12 memory base address upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
contents tsi148 pci/x-to-vme bus bridge user manual 11 80a3020_ma001_08 10.4.13 subsystem vendor id/ subsystem id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 10.4.14 capabilities pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 10.4.15 interrupt line/interrupt pin/minimum grant/maximum latency registers . . . . . . . . 226 10.4.16 pci-x capabilities register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 10.4.17 pci-x status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 10.4.18 lcsr register group description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 10.4.19 outbound translation starting address upper (0-7) registers . . . . . . . . . . . . . . . . . . 234 10.4.20 outbound translation starting address lower (0-7) registers. . . . . . . . . . . . . . . . . . 235 10.4.21 outbound translation ending address upper (0-7) registers . . . . . . . . . . . . . . . . . . 236 10.4.22 outbound translation ending address lower (0-7) registers . . . . . . . . . . . . . . . . . . 237 10.4.23 outbound translation offset upper (0-7) registers . . . . . . . . . . . . . . . . . . . . . . . . . . 238 10.4.24 outbound translation offset lower (0-7) registers . . . . . . . . . . . . . . . . . . . . . . . . . . 239 10.4.25 outbound translation 2esst broadcast select (0-7) registers . . . . . . . . . . . . . . . . . 240 10.4.26 outbound translation attribute (0-7) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 10.4.27 vmebus iack (1-7) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 10.4.28 vmebus read-modify-write (rmw) address upper register . . . . . . . . . . . . . . . . . 246 10.4.29 vmebus rmw address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 10.4.30 vmebus rmw enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 10.4.31 vmebus rmw compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 10.4.32 vmebus rmw swap register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 10.4.33 vme master control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 10.4.34 vmebus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 10.4.35 vmebus status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 10.4.36 pci/x control / status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 10.4.37 vmebus filter register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 10.4.38 vmebus exception address upper register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 10.4.39 vmebus exception address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 10.4.40 vmebus exception attributes register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 10.4.41 error diagnostic pci/x address upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 10.4.42 error diagnostic pci/x address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 10.4.43 error diagnostic pci-x attribute register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 10.4.44 error diagnostic pci-x split completion message register . . . . . . . . . . . . . . . . . . . 275 10.4.45 error diagnostic pci/x attributes register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 10.4.46 inbound translation starting address upper (0-7) registers . . . . . . . . . . . . . . . . . . . 279 10.4.47 inbound translation starting address lower (0-7) registers . . . . . . . . . . . . . . . . . . . 280 10.4.48 inbound translation ending address upper (0-7) registers. . . . . . . . . . . . . . . . . . . . 281 10.4.49 inbound translation ending address lower (0-7) registers . . . . . . . . . . . . . . . . . . . 282
contents tsi148 pci/x-to-vme bus bridge user manual 12 80a3020_ma001_08 10.4.50 inbound translation offset upper (0-7) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 10.4.51 inbound translation offset lower (0-7) registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 10.4.52 inbound translation attribute (0-7) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 10.4.53 gcsr base address upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 10.4.54 gcsr base address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 10.4.55 gcsr attribute register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 10.4.56 crg base address upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 10.4.57 crg base address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 10.4.58 crg attribute register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 10.4.59 cr/csr offset upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 10.4.60 cr/csr offset lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 10.4.61 cr/csr attribute register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 10.4.62 location monitor base address upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 10.4.63 location monitor base address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 10.4.64 location monitor attribute register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 10.4.65 64-bit counter upper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 10.4.66 64-bit counter lower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 05 10.4.67 broadcast pulse generator timer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 10.4.68 broadcast programmable clock timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 10.4.69 vmebus interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 10.4.70 interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 10.4.71 interrupt enable out register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 10.4.72 interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 10.4.73 interrupt clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 10.4.74 interrupt map 1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 25 10.4.75 interrupt map 2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 27 10.4.76 dma control (0-1) registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 10.4.77 dma status (0-1) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 10.4.78 dma current source address upper (0-1) registers . . . . . . . . . . . . . . . . . . . . . . . . . 337 10.4.79 dma current source address lower (0-1) registers . . . . . . . . . . . . . . . . . . . . . . . . . 338 10.4.80 dma current destination address upper (0-1) registers . . . . . . . . . . . . . . . . . . . . . 339 10.4.81 dma current destination address lower (0-1) registers . . . . . . . . . . . . . . . . . . . . . 340 10.4.82 dma current link address upper (0-1) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 10.4.83 dma current link address lower (0-1) registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 342 10.4.84 dma source address upper (0-1) registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 10.4.85 dma source address lower (0-1) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 10.4.86 dma destination address upper (0-1) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
contents tsi148 pci/x-to-vme bus bridge user manual 13 80a3020_ma001_08 10.4.87 dma destination address lower (0-1) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 10.4.88 dma source attribute (0-1) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 10.4.89 dma destination attribute (0-1) registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 10.4.90 dma next link address upper (0-1) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 10.4.91 dma next link address lower (0-1) registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 10.4.92 dma count (0-1) registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 10.4.93 dma destination broadcast select (0-1) registers . . . . . . . . . . . . . . . . . . . . . . . . . . 358 10.4.94 gcsr register group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 10.4.95 vendor id / device id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 10.4.96 control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 0 10.4.97 semaphore registers (0-3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 10.4.98 semaphore registers (4-7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 10.4.99 mail box registers (0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 65 10.4.100 cr/csr register group description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 10.4.101 cr/csr bit clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 10.4.102 cr/csr bit set register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 10.4.103 cr/csr base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 a. typical applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 a.1 typical application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 a.2 tsi148 connection schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 b. hardware implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 b.1 filter recommendations for the tsi148 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 b.1.1 production tsi148 pll filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 b.1.2 alpha tsi148 pll filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 b.2 capacitance decoupling recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 b.3 recommended board layout guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 b.3.1 trace length recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 b.3.2 recommended stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 c. package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 c.1 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 c.1.1 package notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 d. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 d.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 bit index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
contents tsi148 pci/x-to-vme bus bridge user manual 14 80a3020_ma001_08 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
tsi148 pci/x-to-vme bus bridge user manual 15 80a3020_ma001_08 list of figures figure 1: tsi148 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 2: typical application ? tsi148 in single board com puter application. . . . . . . . . . . . . . . . . . . 34 figure 3: divisions of the crg register space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 4: cr/csr register space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 5: slave image programmable address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 6: vmebus to pci/x read request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 7: vmebus to pci/x read completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 8: vmebus to pci/x write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 9: steps used to perform rmw cycles on the vmebus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 10: pci target image programmable address offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 11: pci-vme delayed read request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 12: pci-to-vme delayed read completion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 figure 13: pci-to-vme posted write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 14: target image programmable address offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 figure 15: pci-x-to-vme delayed read request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 16: pci-x-to-vme delayed read completion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 17: pci-x-to-vme posted write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 18: direct mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 19: linked-list mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 20: dma transaction: pci/x-to-vme request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 21: dma transaction: pci/x-to-vme completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 22: dma transaction: vme-to-pci/x request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 23: dma transaction: vme-to-pci/x completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 24: dma transaction: pci/x-to-pci/x request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 figure 25: dma transaction: pci/x-to-pci/x completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
list of figures tsi148 pci/x-to-vme bus bridge user manual 16 80a3020_ma001_08 figure 26: dma transaction: vme-to-vme request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 figure 27: dma transaction: vme-to-vme completion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 figure 28: 8-bit pattern writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 figure 29: 32-bit pattern writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 figure 30: tsi148 reset structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 figure 31: timing for power-up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 figure 32: jtag functional diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 figure 33: signal grouping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 figure 34: pinout ? bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 figure 35: combined register group (crg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 figure 36: cr/csr address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 figure 37: big to little endian data swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 figure 38: tsi148 schematic (page 38) - tsi148 device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 figure 39: tsi148 schematic (page 39) - power pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374 figure 40: tsi148 schematic (page 40) - pull-up and pull-down requirements . . . . . . . . . . . . . . . . . . . .375 figure 41: tsi148 schematic (page 41) - vme data buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376 figure 42: tsi148 schematic (page 42) - vme address buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .377 figure 43: tsi148 schematic (page 43) - vme control buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378 figure 44: tsi148 schematic (page 44) - vme transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379 figure 45: tsi148 schematic (page 45) - vme transceivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380 figure 46: tsi148 schematic (page 56) - pci bus 0.0 and 1.0 pull-ups . . . . . . . . . . . . . . . . . . . . . . . . . .381 figure 47: tsi148 schematic (page 58) - pci bus 0.0 configura tion header . . . . . . . . . . . . . . . . . . . . . .382 figure 48: recommended pll filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .384 figure 49: tsi148 pbga orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386 figure 50: 456-pin pbga package diagram ? bottom and side views . . . . . . . . . . . . . . . . . . . . . . . . .390 figure 51: 456-pin pbga package diagram ? top and side view. . . . . . . . . . . . . . . . . . . . . . . . . . . . .390
tsi148 pci/x-to-vme bus bridge user manual 17 80a3020_ma001_08 list of tables table 1: vmebus address mode codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 2: location monitor interrupt addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 3: pci read data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 4: dma controller linked-list descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 table 5: pci bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 6: pci/x bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 7: vmebus power-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 8: asiden and gsiden definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 9: cr/csr base address configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 table 10: vmebus system controller configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 table 11: signal conventions - i/o type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 12: signal conventions - i/o level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 13: signal conventions - i/o drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 14: pin list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 table 15: vmebus signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 16: miscellaneous signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 17: pinout ? sorted by pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 18: vss (ground) ? sorted by pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9 table 19: core power (1.8 v) ? sorted by pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 20: i/o power (3.3 v) ? sorted by pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table 21: pci/x electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 22: 3.3 v lvttl dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 table 23: 5.0 v lvttl dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 table 24: common receiver dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 25: lvttl driver dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
list of tables tsi148 pci/x-to-vme bus bridge user manual 18 80a3020_ma001_08 table 26: 1.8 v cmos driver dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 table 27: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188 table 28: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 table 29: tsi148 total power dissipation (core + io). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 table 30: tsi148 power dissipation division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 table 31: 456 epbga package thermal performance for an 8 layer pcb . . . . . . . . . . . . . . . . . . . . . . .190 table 33: tsi148 esd classification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 table 32: 456 epbga package thermal performance for a 4 layer pcb . . . . . . . . . . . . . . . . . . . . . . . .191 table 34: endian register views. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 table 35: pcfs register group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 table 36: lcsr register group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 table 37: gcsr register group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 table 38: cr/csr register group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 table 39: vendor id/ device id registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 table 40: command/status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 table 41: revision id / class code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219 table 42: cache line size / master latency timer / header type register . . . . . . . . . . . . . . . . . . . . . .220 table 43: memory base address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 table 44: memory base address upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 table 45: subsystem vendor id/ subsystem id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4 table 46: capabilities pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 table 47: interrupt line/interrupt pin/minimum grant/maximum latency register . . . . . . . . . . . . . . .226 table 48: crg space type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 table 49: intp intx encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 table 50: pci-x capabilities register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 table 51: most encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 table 52: mmrbc encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 table 53: pci-x status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 table 54: dmcrs encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 table 55: outbound translation starting address upper (0-7) re gister . . . . . . . . . . . . . . . . . . . . . . . . .234 table 56: outbound translation starting address lower (0-7) re gister . . . . . . . . . . . . . . . . . . . . . . . . .235 table 57: outbound translation ending address upper (0-7) regi ster . . . . . . . . . . . . . . . . . . . . . . . . . .236 table 58: outbound translation ending address lower (0-7) regi ster. . . . . . . . . . . . . . . . . . . . . . . . . .237
list of tables tsi148 pci/x-to-vme bus bridge user manual 19 80a3020_ma001_08 table 59: outbound translation offset upper (0-7) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 table 60: outbound translation offset lower (0-7) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 table 61: outbound translation 2esst broadcast select (0-7) register . . . . . . . . . . . . . . . . . . . . . . . . . 240 table 62: outbound translation attribute (0-7) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 table 63: prefetch size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 table 64: 2esst transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 65: vmebus transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 66: vmebus data bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 table 67: vmebus address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 table 68: vmebus iack (1-7) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 table 69: vmebus rmw address upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 table 70: vmebus rmw address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 table 71: vmebus rmw enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 table 72: vmebus rmw compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 table 73: vmebus rmw swap register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 table 74: vme master control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 table 75: vme master time off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 table 76: vme master time on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 table 77: vme master release mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 table 78: vmebus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 table 79: deadlock timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 table 80: vmebus global time-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 table 81: vmebus status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 table 82: pci/x control / status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 table 83: pci-x split read time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 table 84: pci/x control / status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 table 85: acknowledge delay time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 table 86: vmebus exception address upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 table 87: vmebus exception address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 table 88: vmebus exception attributes register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 table 89: error diagnostic pci/x address upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2 table 90: error diagnostic pci/x address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 table 91: error diagnostic pci-x attribute register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
list of tables tsi148 pci/x-to-vme bus bridge user manual 20 80a3020_ma001_08 table 92: error diagnostic pci-x split completion message register . . . . . . . . . . . . . . . . . . . . . . . . . .275 table 93: error diagnostic pci/x attributes register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 table 94: inbound translation starting address upper (0-7) regi ster. . . . . . . . . . . . . . . . . . . . . . . . . . .279 table 95: inbound translation starting address upper (0-7) regi ster. . . . . . . . . . . . . . . . . . . . . . . . . . .280 table 96: inbound translation ending addres s upper (0-7) register . . . . . . . . . . . . . . . . . . . . . . . . . . .281 table 97: inbound translation ending addres s lower (0-7) register . . . . . . . . . . . . . . . . . . . . . . . . . . .282 table 98: inbound translation offset upper (0-7) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 table 99: inbound translation offset lower (0-7) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 84 table 100: inbound translation attribute (0-7 ) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 table 101: virtual fifo size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 table 102: 2esst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 table 103: vmebus address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 table 104: gcsr base address upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 table 105: gcsr base address lower (0-7) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 table 106: gcsr attribute register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 table 107: vmebus address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 table 108: crg base address upper register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 table 109: crg base address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 table 110: crg attribute register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 table 111: vmebus address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 table 112: cr/csr offset upper register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 table 113: cr/csr offset lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 table 114: crg attribute register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 table 115: location monitor base address upper register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 00 table 116: location monitor base address lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 1 table 117: location monitor register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 table 118: vmebus address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 table 119: 64-bit counter upper register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 table 120: 64-bit counter lower register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 table 121: broadcast pulse generator timer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 table 122: broadcast programmable clock timer register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 7 table 123: vmebus interrupt control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 table 124: counter source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
list of tables tsi148 pci/x-to-vme bus bridge user manual 21 80a3020_ma001_08 table 125: edge interrupt source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 table 126: vmebus irq[1]o function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 table 127: vmebus irq[2]o function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 table 128: interrupt enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 table 129: interrupt enable out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 table 130: interrupt status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 table 131: interrupt clear register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 table 132: interrupt map 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 table 133: interrupt map 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 table 134: dma control (0-1) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 table 135: dctl bks encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 table 136: dctl vbot encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 table 137: dctl pbks encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 table 138: dctl pbot encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 table 139: dma status (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 table 140: dsta ert encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 table 141: dma current source address upper (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 table 142: dma current source address lower (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 table 143: dma current destination address upper (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 table 144: dma current destination address lower (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 table 145: dma current link address upper (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 table 146: dma current link address lower (0-1) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 table 147: dma source address upper (0-1) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 table 148: dma source address lower (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 44 table 149: dma destination address upper (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 table 150: dma destination address lower (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 table 151: dma source attribute (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 table 152: dsat typ encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 table 153: 2esst transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 table 154: vmebus transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 table 155: vmebus data bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 table 156: vmebus address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 table 157: dma destination attribute (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
list of tables tsi148 pci/x-to-vme bus bridge user manual 22 80a3020_ma001_08 table 158: ddat typ encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 table 159: 2esst transfer rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .352 table 160: vmebus transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 table 161: vmebus data bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 table 162: vmebus address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 table 163: dma next link address upper (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 5 table 164: dma next link address lower (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6 table 165: dma count (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 table 166: dma destination broadcast select (0-1) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 8 table 167: vendor id / device id register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359 table 168: control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 table 169: semaphore register (0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 table 170: semaphore registers (0-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364 table 171: mail box registers (0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 table 172: cr/csr bit clear register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 table 173: cr/csr bit set register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368 table 174: cr/csr base address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370 table 175: package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389 table 176: ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391
tsi148 pci/x-to-vme bus bridge user manual 23 80a3020_ma001_08 about this document this chapter discusses general document information about the tsi148 pci/x-to-vme bus bridge user manual. the following topics are described: ? ?revision history? on page 23 ? ?document conventions? on page 24 ? ?related information? on page 27 revision history 80a3020_ma001_08, final, september 2006 this revision of the tsi148 pci/x-to-vme bus bridge user manual has the following changes: ? the reset value for the seltim0 bit in the ?command/status registers? on page 216 was changed from 0 to 1. ? the mechanical outline drawing in the ?package information? on page 389 chapter was updated. 80a3020_ma001_07, final, march 2006 this revision of the tsi148 pci/x-to-vme bus bridge user manual has the following changes: ? the perrm field in the interrupt map 2 register had the function description corrected from dma0 interrupt map to the pci/x bus error interrupt map (see section 10.4.75 on page 327 ).
about this document tsi148 pci/x-to-vme bus bridge user manual 24 80a3020_ma001_08 ? the naming nip bit in the dma source attr ibute (0-1) registers was corrected. it was previously was called the nin bit (see section 10.4.88 on page 347 ). table 152 on page 348 was also corrected to reflect the correct nip data pattern. ? the lead free commercial part number was added to the ordering information chapter (see section d. on page 391 ). document conventions this section explains the document conventions used in this manual. non-differential signal notation non-differential signals, such as those used by the pci/x standard, are either active high or active low. active low signals are defined as true (asserted) when they are at a logic low. similarly, active high signals are defined as true at a logic high. non- differential signals are considered asserted when active and negated when inactive, irrespective of voltage levels. for voltage levels, the use of 0 indicates a lo w voltage while a 1 indicates a high voltage. non-differential signals that assume a logic low state when asserted are followed by an underscore sign as the last non-numerical character, ?_?. for example, signal_[0] is asserted low to indicate an active low signa l. non-differential signals not followed by an underscore are asserted when they assume the logic high state. for example, signal[0] is asserted high to indicate an active high signal. bit ordering notation when referring to pci/x transactions, this docu ment assumes the most significant bit is the largest number (also known as little-endian bit ordering). for example, the pci address/data bus consists of ad[31:0], where ad[31] is the most significant bit and ad[0] is the least-significant bit of the field. both bits and bytes have an ordering convention. the bit ordering convention for the pci bus interface is little-endian bit ordering in which bit 0 is the least significant bit. the byte ordering convention of the pci bus is little-endian . byte 0 represents the least significant data bits of the word. this corresponds to the bit and byte ordering convention of the pci bus. pci is consistent in the bit and byte ordering. the bit ordering convention for the vmebus inte rface is little-endian bit ordering in which bit 0 is the least significant bit. the byte ordering convention is big-endian. byte 0 represents the most significant bits of the word. this corresponds to the bit and byte ordering convention of the vmebus. the vmebus is not consistent in the bit and byte ordering.
about this document tsi148 pci/x-to-vme bus bridge user manual 25 80a3020_ma001_08 object size notation the following object size conventions are used for pci/x transactions: ?a byte is an 8-bit object. ?a word is a 16-bit (2-byte) object. ?a doubleword (dword) is a 32-bit (4-byte) object. ?a quadword is a 64-bit (8-byte) object. numeric notation the following numeric conventions are used: ? hexadecimal numbers are denoted by the prefix 0x . for example, 0x04. ? binary numbers are denoted by the suffix b . for example, 10b. typographic notation the following italic typographic conventions are used in this manual: ? book titles: for example, pci local bus specification (revision 2.2). ? important terms: for example, when a device is granted access to the pci bus it is called the bus master . ? undefined values: for example, the device supports four channels depending on the setting of the pci_d x register. terminology the following terms are used in this manual: ? pci/x: refers to both the pci and pci-x bus. the pci/x interface can be configured for either pci or pci-x operation.
about this document tsi148 pci/x-to-vme bus bridge user manual 26 80a3020_ma001_08 symbols used the following symbols are used in this manual: this symbol indicates important configuration information or suggestions. this symbol indicates procedures or operating levels that may result in misuse or damage to the device. tip this symbol indicates a basic design conc ept or information considered helpful.
about this document tsi148 pci/x-to-vme bus bridge user manual 27 80a3020_ma001_08 related information the following information is useful for reference purposes when using this manual: american national standard for vme64 this specification defines the vme64 hardware system including the protocol, electrical, mechanical and configuration specification for the vmebus components and expansion boards. american national standard for vme64 extensions (ansi/vita 6.1 1996 (r2003)) this specification defines extensions to the vme64 standard including the protoc ol, electrical, mechanical and configuration specification for the vmebus components and expansion boards. source synchronous transfer (2esst) standard (vita 1.5 2003) this specification defines the 2esstincluding the protocol, electrical, and configuration specifications. pci local bus specification (revision 2.2) this specification defines the pci hardware system including the protocol, electrical, mechanical and configuration specificatio n for the pci local bus components and expansion boards. for more information, see www.pcisig.com. pci-x addendum to pci local bus specification (revision 1.0b) this specification addresses the need for increased bandwidth of pci devices. pci-x enables the design of systems and devices that can operate at speeds significantly higher than t oday's specification allows. for more information, see www.pcisig.com.
about this document tsi148 pci/x-to-vme bus bridge user manual 28 80a3020_ma001_08
tsi148 pci/x-to-vme bus bridge user manual 29 80a3020_ma001_08 1. functional overview this chapter describes the main features and functions of the tsi148 ? . the following topics are discussed: ? ?overview of tsi148? on page 30 ? ?tsi148 features? on page 32 ? ?tsi148 benefits? on page 32 ? ?typical applications? on page 33 ? ?vmebus interface? on page 35 ? ?pci/x interface? on page 40 ? ?linkage module? on page 42 ? ?register overview? on page 43 ? ?dma controllers? on page 45 ? ?interrupter and interrupt handler? on page 46 ? ?jtag? on page 47
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 30 80a3020_ma001_08 1.1 overview of tsi148 the tundra tsi148 device is the next generation component in our industry leading, high performance vmebus system interconnect product family. tsi148 is fully compliant with the 2esst and vme64 extension standards. this en ables you to take advantage of the higher performance vme protocols, while preserving your existing investment in vme boards that implement legacy protocols. tsi148 increases a system?s usable bus bandwidth because its local bus interface is designed for the next generation pci/x processors and peripherals that support either a 66 mhz pci bus or a 133 mhz pci-x bus interface. tsi148 eases design constraints of vme singl e board computers (sbcs) by requiring less board real estate and power than the previous generation of vme-to-pci/x bridge components. these capabilities make tsi148 a key buildi ng block of the vme renaissance and the development of next generation vme single board computers.
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 31 80a3020_ma001_08 figure 1: tsi148 block diagram 1.1.1 vme renaissance vme renaissance is a term defined by motorola tm that describes an intense period of intellectual activity and technology infusion fo cused on the vmebus. the renaissance is a period of innovation and performance improvement which maintains backwards compatibility to legacy vmebus standards. this compatibility requirement protects existing customer investments. the vme renaissance gives vme a faster parallel backplane interconnect, a switched serial interconnect on the backplane coincident with the traditional parallel interconnect, point-to-point mezzanines on the cards and many other significant innovations. 33-to-66 mhz pci bus 50-to-133 mhz pci-x bus 64-bit address / 64-bit data pci/x bus ieee1149.1 boundary scan jtag 80a3020_bk001_01 64-bit address / 64-bit data vmebus supports: sct, blt, mblt, 2evme, 2esst arbiter, clocks, daisy chain drivers, global bus timer linkage module registers interrupter, interrupt handler interrupts dma pci/x target pci/x master vme master vme slave vmebus system controller posted writes, split reads, prefetched reads posted writes, prefetched reads configuration, m emory mapped, mailbox, sem aphores pci/x bus interface vmebus interface
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 32 80a3020_ma001_08 1.1.2 tsi148 features tsi148 has the following key features: vmebus interface ? standards supported: ? legacy protocols to protect existing vme investment ? vme64 extensions ? 2evme and 2esst protocols to bring support for higher bandwidth ? full vmebus system controller functionality pci/x interface ? fully compliant, programmable pci or pci-x bus interface ? multiple modes of bus operation ? interface can be configured as pci-x or pci ? pci-x interface operates from 50-to-133 mhz ? pci interface operates from 33-to-66 mhz ? 32-bit or 64-bit addressing and data in pci and pci-x modes other features ? two, programmable dma controllers with direct mode and linked-list mode support ? interrupt and interrupt handling capability ? flexible register set; programmable from both pci/x and vmebus ? ieee 1149.1 interface ? 456 pbga package, 1.0 mm ball pitch 1.1.3 tsi148 benefits tsi148 offers the following benefits to designers: ? increased bandwidth ?8 x increase in usable system bus bandwidth over current solutions ? less power required than existing devices due to reduced voltages ? 3.3v i/o supply ? 1.8v core supply
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 33 80a3020_ma001_08 ? small device footprint ? 40% less space required than existing products ? reliable customer support with experience supporting the vme community for the past decade. 1.1.4 typical applications tsi148 is intended for vme single board computers and vme i/o peripheral cards that serve the following markets: ? telecommunications ? industrial automation ?medical ? military ?aerospace
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 34 80a3020_ma001_08 1.1.4.1 typical application ? single board computers the tsi148 can be used on vme-based single board computers (sbc) that employ pci/x as their local bus and vme as the backplane bus, as shown in the accompanying diagram. these sbc cards support a variety of applications including telecommunications, datacommunications, medical, industrial automation, and military equipment. the tsi148 high performance architecture se amlessly bridges the pci/x and vme busses, and is the vme industry's standard for single board computer interconnect device. figure 2: typical application ? tsi148 in single board computer application memory tempe pmc connection pci-x bus 64-bit address/ 64-bit data 133 mhz vmebus 64-bit address/ 64-bit data processor bus processor host bridge processor 80a3020_ta001_01
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 35 80a3020_ma001_08 1.2 vmebus interface the tsi148 vmebus interface is compliant with the following standards: ? american national standard for vme64 (ansi/vita 1.0 - 1994 (r2002)) ? american national standard for vme64 extensions (ansi/vita 1.1 - 1997) ? source synchronous transfer (2esst) standard for more information on the vme interface refer to section 2. on page 49 . 1.2.1 2evme protocol the 2evme protocol doubles the vme64 peak bl ock data rate to 160 mbytes/s by utilizing both edges of the ds* signal and the dtack sign al to validate data. the addressing phase of the transaction also differs from vme64 transa ctions because the address broadcast is split into three phases. the three phase address broadcast transmits extended am codes (programmable limit of 256 codes), vme master information, and the transaction beat count. the 2evme protocol doubles peak block data rate and has flexibility in transaction terminations. the following terminations of transactions are allowed in 2evme: ? master termination: before the beat count expires ? slave terminated transactions: using the retry* and berr* signals ? slave suspended terminations: using the retry* and dtack* signals refer to the american national standard for vme64 extensions for more information on the 2evme protocol. 1.2.2 2esst protocol the 2esst protocol further increases vme transaction bandwidth with programmable transfer rates of 160, 267, and 320 mbytes/s. although the 2esst protocol is similar to the 2evme protocol there are a number of differences and specific requirements for 2esst protocol. transactions are source synchronous in 2esst; there is no acknowledgement from receiver of the data. this lack of acknowledgement enables transactions to happen at a faster rate; there are no delays caused by multiple acknowledgments as in the original vme standard. performance enhancements delivered by 2esst require careful management of system-wide skew. 2esst protocol implementation is possible on standard vme64x five row backplanes with texas instrument?s high performance bus transceivers
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 36 80a3020_ma001_08 refer to the source synchronous transfer (2esst) standard for more information on the 2esst protocol. 1.2.3 vme slave the tsi148 vme slave accepts most of the addressing and data transfer modes documented in the vme64 specification , the vme64x specification , and source synchronous transfer (2esst) standard specification. the supported transactions include: ? address: a16, a24, a32, and a64 ? data: d8, d16, and d32 si ngle cycle transaction (sct) ? data: d8, d16, d32 block transaction (blt) ? data: d64 multiple block transaction (mblt) ? data: d64 2evme ? data: d64 2esst incoming write transactions from the vmebus are posted. with posted write transactions, data is written to a vme slave write buffer. the vme slave write buffer is a 4 kbyte buffer. when the tsi148 vme slave accepts a write re quest, the initiating vmebus master receives a data acknowledgment from tsi148. write data is transferred from the vme slave write buffer, through the internal linkage module, to the pci/x master write buffer without involving the initiating vmebus master. refer to section 2.2.1 on page 50 for a detailed description of transaction flow and buffer usage in tsi148. the vme slave read operations depend on whether the transfer is a sct or blt transfer. if the transfer is a sct transfer, the vme slave requests a single beat transfer from the linkage module (see section 1.4 on page 42 ). a pci/x prefetched read is initiated when a vmebus master initiates a block read (blt, mblt, 2evme, or 2esst) transaction on the vmebus. when the tsi148 pci/x master receives a read request (after the vme slave sends the read request requirements through the linkage module) , the pci/x master fills its read buffer by issuing burst requests to the pci/x bus target. the vme slave read buffer is a 2 kbyte read buffer with a programmable size and refill threshold . the design enables the initiating vmebus master to acquire its block read data from the vme slave (after the pci/x master has transferred the data through the linkage module to the vme slave ) instead of directly from the pci/x resources. refer to section 2.5 on page 79 for a detailed description of transaction flow and buffer usage in tsi148.
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 37 80a3020_ma001_08 1.2.3.1 features not supported the following features are not supported by the tsi148 vme slave: ? a40 address modes ? d32 mblt transfers ? vmebus lock commands ? rmw cycles are not guaranteed indivisible on the pci bus 1.2.4 vme master the tsi148 is vme master when the vme master is internally requested by the linkage module to service the pci/x target, dma, or interrupts. the internal linkage module arbitrates requests for each interface. refer to section 1.4 on page 42 for more information on the linkage module. the tsi148 ?s vme master can generate the following addressing and data transfer modes : ? address: a16, a24, a32, and a64 ? data: d8, d16, and d32 si ngle cycle transaction (sct) ? data: d16, d32 block transaction (blt) ? data: d64 multiple block transaction (mblt) ? data: d64 2evme ? data: d64 2esst as vme master, tsi148 supports read-modify-write (rmw) generation, and retry* as a termination from the external vmebus slave . the vme master has two 4 kbyte posted write buffers and two 4 kbyte prefetch read buffers. these buffers enable the vme master to buffer two read or write transactions simultaneously. tsi148 provides several mechanisms to control vmebus usage, including: time-on timer, time-off timer, and additional release mode control (see section 2. on page 49 ). 1.2.4.1 features not supported the following features are not supported by the tsi148 vme master: ? a40 address modes ? d32 mblt transfers tip refer to the american national standard for vme64 extensions for more information on the retry* signal.
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 38 80a3020_ma001_08 ? vmebus lock commands 1.2.5 tsi148 as a vmebus system controller the tsi148 supports the following vmebus system controller functions: ? vmebus arbiter with three modes of programmable arbitration: ? priority (pri) ? round-robin-select (rrs) ? single level (sgl) ? iack daisy-chain driver ? sysreset driver: provides a global system reset ? global vmebus timer: monitors the vmebus and generates a berr_ when there is no vmebus activity for the programmed value ? system clock driver: generates a 16 mhz system clock ? 1.2.5.1 arbiter the tsi148 vmebus arbiter is programmable. all three of the following arbitration modes defined by the vmebus standard are supported: ? priority (pri) ? round-robin-select (rrs) ? single level (sgl) a 16 us arbitration timer is included in the tsi148 to prevent a bus lock-up from occurring when no requester assumes mastership of the bu s after the arbiter has issued a grant. this timer can be enabled or disabled in the vmebus control and status register (see section 10.4.34 on page 255 ). 1.2.5.2 iack daisy-chain driver an iack daisy-chain driver is included in the tsi148 as part of the system controller functionality. this feature ensures that th e timing requirements for starting the iack daisy-chain are satisfied.
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 39 80a3020_ma001_08 1.2.5.3 sysreset driver a sysreset driver is included in the tsi148 to provide a global system reset. the srsto signal is asserted in the following cases: th e lsrsti_ pin is asserted, the sreset bit is asserted in the vmebus control status register, or the pursti_ pin is asserted. the srsto signal is always asserted for at least 200 ms . srsto is normally connected to the vmebus sysreset_ signal through an inverting open collector buffer. 1.2.5.4 global vmebus timer the tsi148 has a vmebus global timer that monitors vmebus cycles and generates a berr signal when there is no vmebus slave response for the programmed time period. the global timer only monitors vmebus cycles when the system controller function is enabled. the global timer is compatible with sct, blt, mblt, 2evme, and 2esst transfers. the global time-out period can be programmed for 8, 16, 32, 64, 128, 256, 512 s. this timer can be enabled or disabled in the vmebus control and status register (see section 10.4.34 on page 255 ). 1.2.5.5 system clock driver tsi148 generates the system clock (sysclk) signal when it is configured as the system controller. the sysclk signal is in spec for the following pci/x clock frequencies: 33.3, 66.6, 100, or 133 mhz. the sysclk pin is connected through an external driver to the vmebus. sysclk operates at 16 mhz. the external driver is enabled through the scon pin (see section 8.4.2 on page 161 ). 1.2.5.6 configuration the system controller functions can be configured at power-up. the system controller functionality can be enabled or disabled, or th e auto system controller (scon) function can be used. the auto scon function automatically enables the system controller functions when the board is installed in slot 1. table 10 on page 135 shows the different signal combinations that enable or disable the scon functionality.
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 40 80a3020_ma001_08 1.3 pci/x interface the tsi148 pci/x interface can operate either in pci mode or pci-x mode. the pci interface is compliant with the pci local bus specification (revision 2.2) , while the pci-x interface is compliant with the pci-x addendum to pci local bus specification (revision 1.0b) the pci mode can operate at 33 to 66 mhz and has 32-bit/64-bit addressing and data capability. the pci-x mode can operate at 50 to 133 mhz and has 32-bit/64-bit addressing and data capability. for more information on the pci/x interface refer to section 3. on page 73 . 1.3.1 pci/x target the pci and pci-x targets are described separately in the following sections because they respond differently to read requests and use different buffering techniques for read transactions. 1.3.1.1 pci target read transactions from the pci bus are always processed as delayed transactions. the pci target has a 4 kbyte read buffer, however, in conventional pci mode a maximum of 512 bytes are used for storing prefetched data. when processing a read request the requesting pci bus master is issued a retry from the tsi148 pci target. the read request is then forwarded to the linkage module and then to the tsi148 vme master to be serviced. one delayed read is supported by the pci target. during write transactions, the pci target posts write data in its write buffer. the write buffer consists of a 40 entry command queue and a 4 kbyte data queue. tsi148 issues the initiating pci bus master immediate acknowledgement upon the write completing. once the posted write completes on pci, tsi148 obtains the vmebus and writes the data to the vmebus resource independent of the initiating pci master. for more information on buffer structure and data flow in tsi148 refer to section 3. on page 73 . 1.3.1.2 features not supported the following features are not supported by the tsi148 pci target: ? no response to pci i/o transfers ? pci/x lock_ signal the term pci/x refers to functionality that applies to both pci and pci-x operating modes.
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 41 80a3020_ma001_08 ? message signalled interrupts 1.3.1.3 pci-x target read transactions from the pci-x bus are always processed as split transactions. the pci-x target has a 4 kbyte read buffer used for storing prefetched data. the requesting external pci-x master is issued a split response from the tsi148 pci-x target. the pci-x target supports up to six split read transactions. when the read data has been retrieved from the vmebus and sent to the pci-x target?s read buffer, tsi148 issues a split completion on the pci-x bus and transfers the data from the pci-x target?s read data buffer to the original master . during write transactions, the pci-x target posts write data in its write buffer. the write buffer consists of a 40 entry command queue and a 4 kbyte data queue. tsi148 issues the initiating pci bus master immediate acknowledgement upon the write completing. once the posted write completes on pci-x, tsi148 obtains the vmebus and writes the data to the vmebus resource independent of the initiating pci-x master. 1.3.1.4 features not supported the following features are not supported by the tsi148 pci-x target: ? no response to pci-x i/o transfers ? pci/x lock_ signal ? message signalled interrupts 1.3.2 pci/x master tsi148 requests pci/x ownership when the pci/x master is internally requested by linkage module to service the vme slave or the dma controllers. the pci/x master has a 4 kbyte read buffer and 4 kbyte write buffer. 1.3.2.1 features not supported the following features are not supported in tsi148: ? pci/x lock_ signal prefetching is based on the byte count received by the tsi148 pci-x target. the size of the read buffer is dependent on what pci/x mode (pci or pci-x) is used in the system (see section 1.3.1.1 on page 40 ).
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 42 80a3020_ma001_08 ? message signalled interrupts 1.4 linkage module the tsi148 linkage module interconnects all the different modules that comprise tsi148. the following modules are directly-connected to, and serviced by, the linkage module: ? vmebus: master and slave ? pci/x: master and target ? dma controllers ? registers the linkage module is used to arbitrate access to each interface. it controls the flow of data and data requests through the device. every transaction processed through tsi148 passes through the linkage module.
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 43 80a3020_ma001_08 1.5 register overview tsi148?s 4 kbyte register space is called the combined register group (crg). the crg is divided into the following groups: ? pci configuration space registers (pfcs) ? local control and status registers (lcsr) ? global control and status registers (gcsr) ? control and status registers (csr) for more information on tsi148?s registers, refer to section 10.2 on page 194 . tsi148?s registers can only be accessed through the linkage module. the interfaces that can access registers are the pci/x interface and the vmebus interface. figure 3: divisions of the crg register space 4 kbyte crg 256 bytes 1280 bytes 32 bytes 1504 bytes 1024 bytes pcfs lcsr gcsr reserved csr
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 44 80a3020_ma001_08 1.5.1 control and status registers the 512 kbyte cr/csr space, shown in figure 4 , can be accessed from the vmebus using the special a24 cr/csr am code (see section 2.3.1 on page 61 ). the base address is defined by either geographical address implementation or auto slot id. tsi148?s vme slave can be configured at power-up to use one of the two methods (see section 5.4 on page 128 ). the cr/csr offset registers cons ist of an enable and a translation offset (located at offsets 0x418 ? 0x420). the address space is separated into the following areas: ? the upper 4 kbytes defines the tsi148 crg ? the remaining 508 kbytes maps to the pci/x bus. ? when an access is initiated on the vmeb us using a24 cr/csr am code, tsi148 initiates an access on the pci/x bus when the cr/csr offset register is enabled. figure 4: cr/csr register space 512 kbyte cr/csr 4 kbyte 508 kbyte tempe crg maps to pci bus 512 kbyte cr/csr are a is defined in the vme6 4 extensions standard 0x00000 0x7ffff
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 45 80a3020_ma001_08 1.6 dma controllers tsi148 has two internal, independent, single channel dma controllers for high performance data transfers. dma operations between the source and destination bus are managed as separate transactions through the linkage module. transactions are buffered in each dma controller?s 64-bit by1024 (8 kbyte) entry buffer . the tsi148 dma controllers support both direct mode and linked-list mode operation. there are no restrictions on addressing alignment or transfer sizes (transfer sizes can range anywhere from 1 byte to 4 gbytes). there is support for transfer throttling through programmable transaction block sizes. there is also a back-off timer, which enables dma transfers to occur in certain (programmable) periods of time. parameters for dma transfers are configured by software, or linked-list, activity. the principal mechanism for dma transfers is the same for operations in either direction (pci-to-vmebus, or vmebus-to-pci), only the identity of the source and destination bus changes. in a dma transfer, the tsi148 gains control of the source bus and reads data into the read buffer of the source master, then passes the data through the linkage module and into the dma data buffer. the dma controller then requests a transaction through the linkage and passes the data through the linkage and into the destination write buffer. the destination master then acquires the des tination bus and empties its write buffer. the dma controller can be programmed to perform multiple blocks of transfers using linked-list mode. the dma works through the transfers in the linked-list following pointers at the end of each linked-list entry. linked-list operation is initiated through a pointer in an internal tsi148 register, but the linked-list itself resides in pci/x memory. for more information on tsi148?s dma controller refer to section 4. on page 101 .
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 46 80a3020_ma001_08 1.6.1 data movement the dma controllers support the following data movement scenarios: ? pci/x-to-vme: data is read from pci/x and written to vme. the dma buffer is emptied while being filled. ? vme-to-pci/x: data is read from vme and written to pci/x. the dma buffer is emptied while being filled. ? pci/x-to-pci/x: data is read from pci and written back later. ? vme-to-vme: data is read from vme and written back later ? data pattern-to-vme: data pattern written in to dma buffer, then written to vmebus. the dma buffer is emptied while being filled. ? data pattern-to-pci/x: data pattern written into dma buffer, then written to pci/x bus. the dma buffer is emptied while being filled. 1.7 interrupter and interrupt handler tsi148 can be programmed to act as interrupter and an interrupt handler in a vme system. as an interrupter, tsi148 is capable of asserting interrupts on irq[7:1]o. as an interrupt handler, tsi148 has several vmebus interrupt acknowledge registers which, when read, generate an iack cycle on the vmebus (see section 10.4.70 on page 311 ). tip data patterns can be used for syst em debugging or clearing registers.
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 47 80a3020_ma001_08 1.8 jtag tsi148 has a dedicated user-accessible test logic that is fully compatible with the ieee 1149.1 standard test access port and boundary-scan architecture ; also referred to as jtag (joint test action group). for more information on tsi148? s jtag capability refer to section 7. on page 141 .
1. functional overview tsi148 pci/x-to-vme bus bridge user manual 48 80a3020_ma001_08
tsi148 pci/x-to-vme bus bridge user manual 49 80a3020_ma001_08 2. vme interface this chapter describes the main features and functions of the tsi148 vme interface. the following topics are discussed: ? ?overview of the vme interface? on page 50 ? ?vme slave? on page 50 ? ?vme master? on page 61
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 50 80a3020_ma001_08 2.1 overview of the vme interface the tsi148 vme interface is comp liant with the following standards: ? american national standard for vme64 ? american national standard for vme64 extensions ? source synchronous transfer (2esst) standard the interface is separated into vme slave a nd vme master modules. the tsi148 has been designed so that it can accept its own transa ction on the vmebus. if the tsi148 vme master initiates a transaction on the vmebus, and the address falls within the inbound address window for the tsi148 vme slave, then the vme slave accepts the cycle. for more information on vme master and slave transactions, refer to section 2.2.1.2 on page 54 and section 2.3 on page 61 . 2.2 vme slave the vme slave is responsible for tracking and maintaining coherency to the vmebus protocols. the vme slave supports a16, a24, a32, and a64 address spaces and d8, d16, d32, and d64 data transfer sizes. the vme slave supports sct, blt, mblt, 2evme, and 2esst protocols. during a read transaction, the vme slave does not assert the dtack* signal to acknowledge the data until after the data has been receive d from the pci/x bus. during write transactions, the vme slave posts the data into the writ e buffer. the vmebus considers the write complete, and tsi148 manages the completion of the write posted transaction on the pci/x bus. all transactions are completed on the pci/x bus in the same order that they are completed on the vmebus. a read transaction forces all previ ously issued posted write transactions to be flushed from the write buffers. all posted write transfers are completed before a read is begun to make sure that all transfers are completed in the order issued. 2.2.1 vme slave buffers the vme slave has a single read buffer that st ores command information when servicing a transaction from the vmebus, and receives the read data from the linkage module after the pci/x master has retrieved the data from the pci/x bus. the read buffer is segmented into two parts: a data queue and a command queue. the command queue stores address and command information for a single vmebus transaction. the amount of data in read buffer depends on the type of transaction requested. the data queue can store up to 2 kbyte of data.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 51 80a3020_ma001_08 the single write buffer receives data and commands from the vmebus. the write buffer is segmented into two parts: data queue and co mmand queue. the data queue designed for large burst transfers and supports up to 4 kbyte of data. the command queue stores address and command information and can accept six entries. the write buffer is considered full when either the command or data queue is full. 2.2.1.1 transaction mapping the vmebus is capable of many different transa ction types, including one to four byte single beat transactions and burst transactions. thes e transactions must be mapped to corresponding transactions on the pci/x bus. the tsi148 supports all the different modes and protocols supported by the pci/x bus and has numerous programmable options. because of this flexibility there are many possible types of transactions between vme and pci/x. the following rules can be applied to transactions: 1. a one, two, three, or four byte read or write on the vmebus always maps to a corresponding read or write on the destination bus. vmebus block reads can cause data to be prefetched from the pci/x bus. any lo cations with read sensitive bits should be accessed using a single cycle transaction (sct) read that matches the width of the location. there is a one-to-one correspondence between the bytes written on the vmebus and bytes written on the pci/x bus. 2. the vme slave does not merge, combine, or gather transactions. a transaction that completes in a single bus tenure on the vmebus may not complete in a single bus tenure on the destination bus. 3. the vme master does not generate the two and three byte unaligned transactions defined in the american national standard for vme64 . vmebus-to-pci address mapping the vme slave interface maps a vmebus addres s to the pci/x bus address space using eight programmable slave images (see section 10.4.46 on page 279 ). these slave images provide windows into the pci/x bus from the vmebus. the vmebus address is compared with the address range of each slave image, and if the a ddress falls within the specified range, an offset is added to the incoming address to form the pci/x bus address. the incoming address is within the slave images window if the incoming address is greater than or equal to the starting address and less than or equal to the ending address. all programmable slave images should decode unique address ranges. however, if the slave images overlap, slave image zero has the highest priority and slave image seven has the lowest priority.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 52 80a3020_ma001_08 the address space of the current vme transaction determines how address comparisons are performed. the following list gives example programming and comparisons for the address mapping: ? if the vmebus address is 64-bits, then bits 31 to 0 of the starting address in the inbound translation starting address upper (itsau x ) register (see section 10.4.46 on page 279 ) and bits 31 to 16 of the starting address in the inbound translation starting address lower (itsalx) register (see section 10.4.51 on page 284 ) and bits 31 to 0 of the ending address in the inbound translation ending address upper (iteau x ) register (see section 10.4.48 on page 281 ) and bits 31 to 16 of the ending address in the translation ending address lower (iteal x ) register (see section 10.4.49 on page 282 ), are compared against vmebus address bits 63 to 16. ? if the vmebus address is 32-bits, then bits 31 to 16 of the starting address in the itsal x register and bits 31 to 16 of the ending address in the iteal x register are compared against vmebus address bits 31 to 16. the granularity is 64 kbytes. ? if the vmebus address is 24-bits, then bits 23 to 12 of the starting address in the itsal x register and bits 23 to 12 of the ending address in the iteal x register are compared against vmebus address bits 23 to 12. the granularity is 4 kbytes. ? if the vmebus address is 16-bits, then bits 15 to 4 of the starting address in the itsal x register and the bits 15 to 4 of the ending address in the iteal x register are compared against vmebus address bits 15 to 4. the granularity is 16 bytes. each slave image has a set of attributes that are used to enable the image and define the vmebus transfer characteristics. each image is has an attribute register (see section 10.4.52 on page 285 ) with the following fields: ?image enable ? programmable threshold for read-ahead prefetching ? programmable virtual fifo size for inbound prefetch reads ? 2esst slave response rate control: 160, 267, or 320 mb/s ? slave response control: sct, blt, mblt, 2evme, 2esst, 2esst broadcast ? slave address space response control: a16, a24, a32, or a64 ? slave response control: vmebus non-privileged, supervisory, program and data access cycles there are no limits imposed on how large an address space a slave image can represent.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 53 80a3020_ma001_08 each slave image also includes a programmable address offset. the offset is added to the vmebus address, and the result is used as the pci/x bus address. figure 5 shows the programmable starting address, ending address, and translation offset. figure 5: slave image programmable address offset in figure 5 the width of the starting address, the en ding address, and the translation offset depends on the vme address bus size. in figure 5 this dependency is represented by a?. the following lists illustrates the address tran slation process for va rious vmebus address spaces: ? if the vmebus address is 64-bits, then bits 31 to 0 of the offset in the inbound translation offset upper (itofu x ) register (see section 10.4.50 on page 283 ) and bits 31 to 16 of the offset in the inbound translation offset lower (itofl x ) register (see section 10.4.51 on page 284 ) are added to vmebus address bits 63 to 16. ? if the vmebus address is 32-bits, then the incoming vmebus address bits 63 to 32 are forced to zero and then bits 31 to 0 of the of fset in the itofux register and bits 31 to 16 of the offset in the itoflx register are added to vmebus address bits 31 to 16. ? if the vmebus address is 24-bits, then the incoming vmebus address bits 63 to 24 are forced to zero and then bits 31 to 0 of the of fset in the itofux register and bits 31 to 12 of the offset in the itoflx register are added to vmebus address bits 23 to 12. ? if the vmebus address is 16-bits, then the incoming vmebus address bits 63 to 16 are forced to zero and then bits 31 to 0 of the offset in the itofux register and bits 31 to 4 of the offset in the itoflx register are added to vmebus address bits 15 to 4. starting address ending address translation offset p ci/x a ddress vme addre ss a63 a63 a63 a? a? a?
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 54 80a3020_ma001_08 2.2.1.2 vme slave transactions the tsi148 vmebus interface supports different transaction types, including one to four byte single beat transactions, and burst transacti ons. these transactions must be mapped to corresponding transactions on the destination bus. for more information on transaction mapping, refer to section 2.2.1.1 on page 51 . vme slave read transaction vme slave read operation depends on whether the transfer is a block or single cycle. if the transfer is a sct, the vme slave requests a single beat transfer from the linkage module. the vmebus acknowledgement is held until the data is received from pci/x. if the read operation is a block transfer, the vme slave requests a block of data from the linkage module. the vme slave read buffer is used to store the data received from the linkage module. the data is stored in the buffer until it is needed to complete a vmebus transaction. the vme slave read buffer has a programmable vi rtual buffer size and re fill threshold. this flexibility enables the buf fer to be optimized for various block sizes. the virtual buffer size can be set to 64, 128, 256 or 512 bytes. the virtual buffer size and refill threshold are programmable in the slave image registers (see section 10.4.46 on page 279 ). when the vme slave receives a blt or mblt read command, the vme slave prefetches data (through the linkage module to get the data) based on the virtual buffer size. as data is removed from the vme slave read buf fer, it is refilled based on the refill threshold. the refill threshold can be set to half-full or empt y. when the refill threshold is set to half-full, the vme slave read buffer is refilled when it is less than half-full. this functionality enables the vmebus master to read data from pci/x without interruption. in applications where the packet size is small, the data from the initial read can be all that is required and reading additional data would waste pci/x bus bandwidth. in this case, the refill threshold can be set to empty to conserve bandwidth on the pci/x bus. if the buffer is drained and additional data is required by the vme master, the buffer is re filled based on the buffer size and address. when the vme slave receives a 2evme or 2esst read command, the prefetch size is determined by the byte count received from the vmebus master. the entire byte count is read on the pci/x bus. tsi148 supports the maximum 2evme/2esst byte-count of 2 kbytes. prefetching is not used during single cycle transfers.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 55 80a3020_ma001_08 example vme slave read transaction in this example vme-to-pci-x read, the transaction is separated into request and completion phases. the following list, and figure 6 , show the steps taken in the first part of the transaction (request) and in the second part of the list, and figure 7 , shows the next part of the transaction (completion). 1. a vmebus master initiates a sct, blt, mblt, 2evme, or 2esst read request to a pci/x peripheral. figure 6: vmebus to pci/x read request 2. tsi148 stores the command and address inform ation, as well as byte count information (if it is a a 2evme or 2esst request) in the vme slave?s read buffer command queue ? tsi148 supports one read request at a time pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module command data command data
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 56 80a3020_ma001_08 3. the vme slave makes a read request to the linkage module. the initial amount of data requested is determined by the block transfer type. ? if the transaction is a sct, the vme slave requests a single beat transfer from the linkage module. ? if the transaction is a block transfer the vme slave uses the virtual size buffer to determine how many bytes to request from the linkage module. ? since 2evme and 2esst transfers include a byte count, the vme slave requests the entire byte counts. 4. after arbitration, the linkage module command and address information is passed to the pci/x master?s read buffer command queue. the pci/x master?s command queue is six entries deep. 5. the pci/x master issues the read request to the pci/x target .
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 57 80a3020_ma001_08 figure 7: vmebus to pci/x read completion 6. the pci/x target satisfies the read request a nd the data is stored in the pci/x master?s read buffer data queue. 7. the pci/x master makes a request to the linkage module. 8. after arbitration, the read data is passed through the linkage module to the vme slave?s read buffer data queue. the 2 kbyte vme slave?s read buffer data queue is used to store data received from the linkage module. 9. once the vme slave?s read buffer data queue is full (based on the virtual size programmed or byte count received), the read data is passed to the initiating vmebus master. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module command data command data
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 58 80a3020_ma001_08 ? if the as signal is asserted and the ref ill threshold has been reached in the vme slave?s read buffer data queue, the vme slave requests the linkage module to return to the pci/x bus for more data. vme slave write transaction during write transactions, the external master po sts write data into the write buffer. all writes are posted and the write buffer stores the data necessary to complete the transfer and immediately acknowledges the transaction on the vmebus. tsi148 manages the completion of the posted write transaction.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 59 80a3020_ma001_08 example vme slave write transaction in this example vme-to-pci/x write transaction, the data passes through tsi148 through the vme slave, to the linkage module, and ends at the pci/x master. the following list, and figure 8 , show the steps taken in the write transaction. 1. a vmebus master initiates a write to a pci/x target. figure 8: vmebus to pci/x write 2. the vme slave queues the address and command information within its write buffer command queue. the command queue is six entries deep. ? all write transactions are posted within the vme slave?s write buffer data queue. ? the vme slave?s write buffer data queue is 4 kbytes. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module command data command data
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 60 80a3020_ma001_08 3. once the transaction completes on the vme bus (that is, all the data is placed within the vme slave?s write buffer data queue) the vme slave sends a request to the linkage module. 4. after arbitration by the linkage module, the command and address information, as well as the write data, is passed to the pci/x master?s write command and data queue. ? the pci/x master?s write buffer data queue is 4 kbytes and the command queue (which is used to store commands from linkage module) is six entries deep. 5. the pci/x master completes the write transaction to the pci/x target. 2.2.1.3 vme slave read-modify write (rmw) cycles the tsi148 vme slave responds to rmw cycles. the vme slave does not complete vmebus rmw cycles as indivisible cycles on the pci/x bus. the pci/x bus lock_ signal is not supported by the tsi148 pci/x master and therefore the read and write cycles are divisible on the pci/x bus. for information on how tsi148 generates rmw cycles as a vme master, refer to section 2.3.3 on page 62 . 2.2.1.4 terminations the vme slave can terminate a sct, blt, or mblt cycle with a dtack_ signal or a retry_ signal. the vme slave never terminates a sct, blt, or mblt cycle with a berr_ signal. all 2evme and 2esst cycles are terminated w ith a normal termination or retry signal. the vme slave never terminates a 2evme or 2esst cycle with a slave termination or error termination.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 61 80a3020_ma001_08 2.3 vme master the vme master provides the interface from linkage module to the vmebus. the vme master can generate a16, a24, a32, and a64 vmebus address cycles and d8 even, d8 odd, d16, d32, and d64 data transfers. the vme master generates transfers using the sct, blt, mblt, 2evme, and 2esst protocols. the vme master supports the vmebus retry_ signal. 2.3.1 addressing capabilities the tsi148's vmebus addressing mode is controlled by programming the outbound translation attribute registers (see section 10.4.26 on page 241 ). the tsi148 is capable of generating a16, a24, a32, a64, and cr/csr address phases. the address mode and type (supervisor and program) are also programmed through the outbound translation attribute registers. the address and address modifier (am) codes that are generated by the tsi148 are functions of the mapping of the pci/x memory space as defined above or through dma programming (see section 10.4.88 on page 347 and section 10.4.89 on page 351 ). table 1 shows the am codes used for the vmebus. table 1: vmebus address mode codes amode address mode 0x0000 a16 0x0001 a24 0x0010 a32 0x0011 reserved 0x0100 a64 0x0101 cr/csr 0x0110 reserved 0x0111 reserved 0x1000 user1 (am 0x0100 xx ) 0x1001 user2 (am 0x0101 xx ) 0x1010 user3 (am 0x0110 xx ) 0x1011 user4 (am 0x0111 xx ) 0x1100 reserved
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 62 80a3020_ma001_08 there are four user defined am codes. when the user defined am codes are used, the am[1] bit is defined by the vmebus supervisory mode (sup) bit and the am[0] bit is defined by the vmebus program mode (pgm) bit in the outbound translation attribute register (see section 10.4.26 on page 241 ) . 2.3.2 vme master buffers the vme master interfaces to the linkage module through separate read and write buffers. the vme master has two write buffers and two read buffers. the read buffers are each segmented into two parts: the data queue and the command queue. the read buffers are used to store data received from the vmebus. the data queue can accept up to 4 kbytes of data. the command queue stores a single entry. the two read buffers allows the tsi148 to perform back-to-back reads from the vmebus. the write buffers are each segmented into two parts: the data queue and the command queue. the data queue can have up to 4 kbytes of data. the command queue can accept one entry. the write buffers are used to receive writes from the linkage module. the two write buffers allow the vme master to accept two linkage module commands. the two write buffers allows the tsi148 to perform ba ck-to-back writes from the vmebus. 2.3.3 vme master read-modify write (rmw) cycles a rmw cycle allows the vme master to read from a vmebus slave and then write to the same resource without relinquishing bus tenur e between the two operations. rmw cycles can be generated by the tsi148 vme master. the vme master generates rmw cycles on 8, 16, and 32-bit aligned transfers. for more information on the vme rmw registers, refer to section 10.4.29 on page 247 . the following registers are used when the rmw functionality is enabled ? the vmebus rmw address upper (rmwau) and vmebus rmw address lower (rmwal) registers: these registers specify the pci/x address, both the upper bits (63:32) and lower bits (31:2), for the rmw cycle. 0x1101 reserved 0x1110 reserved 0x1111 reserved table 1: vmebus address mode codes amode address mode
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 63 80a3020_ma001_08 ? vmebus rmw enable (rmwen): this register defines the bits that are involved in the compare and swap operations of the rmw cycle. ? vmebus rmw compare (rmwc): this register defines the bits which are compared with the data read from the vmebus. ? vmebus rmw swap (rmws): this register defines the bits written to the vmebus when the compare is successful. the following steps are used to perform rmw cycles on the vmebus (see figure 9 ). 1. a pci/x bus read access address matches the target address ? the target address must be mapped to the vmebus by one of the pci/x bus-to-vme slave images. 2. the vme master reads the data at the target address. 3. the vme master completes the read on the vmebus. 4. the data read from the target address is comp ared with the data in the compare register. ? the bits in the rmw enable register determine which bits are compared. 5. when the enable register is set and the co mpare is true, the enabled bits which compare are replaced with the data in the swap regi ster and are written to the vmebus. the bits which do not compare are written to the vmebus without modification. 6. the data read from the vmebus is returned to the pci/x master.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 64 80a3020_ma001_08 figure 9: steps used to perform rmw cycles on the vmebus for information on how tsi148 responds to rmw cycles as a vme slave, refer to section 2.2.1.3 on page 60 . 2.3.4 vme master bandwidth control the vme master has features to control vmebus usage which can all be programmed in the vme master control register (see section 10.4.33 on page 251 ). the features include the following: ? time-on timer ? the time-on timer specifies the length of time the vme master can use the vmebus. a pci/x read access address matches the target address within the rmw address register the read data is bit compared with the data in the rmw compare register the data in the rmw swap register is written to the vmebus. all other bits are unaffected. provided the bit is enabled in the rmw enable register and the compare is true the tempe vme master complete s the read on the vmebus
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 65 80a3020_ma001_08 ? time-off timer ? the time-off timer specifies the length of time the vme master must wait before re-requesting the vmebus. ? release mode control ? the release mode control bits define wh en the vme master releases the vmebus. the vme master requests the vmebus when it receives a command from the linkage module or if a previously received command is not completed and the time-off timer has expired. once the vme master has acquired the vmebus, it maintains bus ownership until one of the release conditions is met (see section 2.3.4.1 on page 65 ). 2.3.4.1 vme master release conditions tsi148 releases control of the vmebus after it has been granted control as the vme master when one of the following vmebus release conditions are met: ? the vmebus is released when the time-on timer has reached its terminal count or the master is done ? the vmebus is released when the time-on-timer has reached its terminal count and there is a vmebus request or the vme master is done . this mode enables the master to continue using the vmebus, if no other master is requesting the bus, even though the time has expired. ? the vmebus is released when the time-on timer has reached its terminal count and the vmebus bclr_ signal is asserted or the vme master is done . this mode enables the master to continue using the vmebus, if no other master is requesting the bus at a higher priority, even though the time has expired. the bclr_ signal is asserted by the arbiter when a higher priority request is received (see section 8.4.2 on page 161 ). ? the vmebus is released when the time-on timer has reached its terminal count or the vme master is done and there is a vmebus request. this enables the vme master to maintain vmebus ownership even when there is no transfer in progress. bus mastery is maintained until another master requests the bus. tip the term done means the vme master has completed the transfer and has no other requests in the queue.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 66 80a3020_ma001_08 2.3.5 vmebus exception handling when a vmebus transfer initiated by the vme master does not complete successfully, the status is saved in the vmebus exception regist ers. the exception registers are updated when a transaction is terminated with a bus error, or a 2evme or 2esst transfer is terminated with a slave termination. the vmebus exception registers include: ? vmebus exception address upper (veau) ? vmebus exception address lower (veal) ? vmebus exception attributes (veat) for more information on the vmebus exception registers, refer to section 10.4.38 on page 267 ). when the vme master encounters one of these conditions, any write data in the buffers is removed (flushed). if the transaction was a vmebus read, the vme master completes the linkage module command by filling the buffer with a data pattern of all ones. if a second exception occurs before the software has acknowledged the first exception, the status registers are not updated, however, the overflow bit is set to indicate that more than one exception occurred. 2.3.6 utility functions tsi148 provides the following vmebus utility functions: ? vmebus location monitor which allows one vm ebus board to broadcast an interrupt to multiple boards. the processor sends an inte rrupt by reading, or writing to, one of the vmebus monitored addresses. other boards in the system monitor this address and interrupt their processors when an access is detected. the monitored vmebus addresses are programmable and works in a16, a24, a32, and a64 vmebus address space (see section 2.3.6.1 on page 67 ). three registers are provided for this function: location monitor base address upper register (lmbau), location monitor base address lower register (lmbal), and location monitor attribute register (lmat) (see section 10.4.62 on page 300 ). ? eight semaphore registers for resource sharing (see section 2.3.6.2 on page 68 ). ? four mailbox registers used to provide a communication path between the vmebus and pci/x logic (see section 2.3.6.3 on page 69 ). tip the interrupt controller can be programmed to generate an interrupt when the exception registers are updated.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 67 80a3020_ma001_08 ? logic is provided to generate vmebus system fail and board fail signals (see section 5.4.2.4 on page 134 ) ? power-up options are provided for cr/csr base address configuration. tsi148?s vme slave can be configured at power-up to use 1 of 2 methods: geographical address implementation or auto slot id (see section 5.4.2 on page 130 ). ? supports the following two non-standard vmebus features: broadcast interrupt, clock and 64-bit counter (see section 2.3.6.4 on page 69 ). 2.3.6.1 vmebus location monitor location monitor functionality allows one vme bus board to broadcast an interrupt to multiple boards. all boards which are particip ating in the broadcast are programmed to monitor a set of vmebus addresses. the tsi148 location monitor is enabled in th e location monitor (lmat) register by setting the enable (en) bit (see section 10.4.64 on page 302 ). the monitored vmebus addresses are programmable in the location monitor base address upper (lmbau) register (see section 10.4.62 on page 300 ) and location monitor base address lower (lmbal) register (see section 10.4.63 on page 301 ). the location monitor can monitor addresses in vmebus a16, a24, a32 or a64 space. if the vmebus address is 64-bits, then bits 31 to 0 of the base address in the lmbau register and bits 31 to 5 of the base address in the lmbal register are compared against vmebus address bits 63 to 5. if the vmebus address is 32-bit, then bits 31 to 5 of th e base address in the lmbal register are compared against vmebus address bits 31 to 5. if the vmebus address is 24-bits, then bits 23 to 5 of the base address in the lmbal register are compared against vmebus address bits 23 to 5. if the vmebus address is 16-bits, then bits 15 to 5 of the base address in the lmbal register are compared against vmebus address bits 15 to 5.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 68 80a3020_ma001_08 the processor sends an interrupt by reading or writing one to the vmebus monitored address. the other boards in the system monitor this address and interrupt their processors when an access is detected. there are four locations which are monitored and each location is eight bytes. vmebus address bits 3 and 4 are used to define the specific location. table 2 shows the relationship between the vmebus address and the location monitor interrupt. when the location monitor detects an access to one of the locations being monitored, an interrupt is sent to the interrupter. if the interrupt is enabled, then the selected intx signal is asserted. the status of the inte rrupt is available in the global control and status (gcsr) registers (see section 10.2.4 on page 195 ) and local control and status (lcsr) registers (see section 10.2.3 on page 195 ). no data is transferred during a location monitor access. the slave boards monitoring the location do not respond. the board generating the location monitor cycle is responsible for terminating the vmebus cycle with a dtack* signal. the board generating a location monitor cycle must have its location monitor en abled and programmed to monitor the location monitor address. 2.3.6.2 semaphore registers the gcsr registers include eight semaphore re gisters. these semaphore registers can be used to allow processes running on the local processor and processes running on processors on other vmebus boards to share resources. each semaphore register is 8-bits and there are four semaphore registers in a 32-bit register. the most significant bit (bit 7) is the semaphore bit and the remaining seven bits (b its 6 to 0) are the tag field. to gain ownership of the semaphore, a process writes to the semaphore with bit 7 set and a unique code in the tag field. the process has gained ownership if a subsequent read returns the unique code. the process releases the se maphore by setting the semaphore register to 0. a semaphore register is only updated when bit 7 in the register is zero and a one is written to bit 7 of the register, or when a zero is written to bit 7. table 2: location monitor interrupt addresses vmebus address location monitor interrupt lmba + (0-7) lm0 lmba + (8-f) lm1 lmba + (10-17) lm2 lmba + (18-1f) lm3
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 69 80a3020_ma001_08 2.3.6.3 mailbox registers the gcsr includes four mailbox registers which can be used to provide a communication path between the vmebus and the pci/x bus. these registers support read and write access from the pci/x bus and the vmebus. when the le ast significant byte of a mailbox register is written, an interrupt is sent to the interrupter. if the interrupt is enabled, an intx signal is generated. 2.3.6.4 broadcast interrupt and 64-bit counter there are two tsi148 vmebus features which use the irq[1]_ or irq[2]_ signal lines in a device specific way: the broadcast interrupt and 64-bit counter. the irq[1]_ and irq[2]_ signal lines received from the vmebus can be routed to several internal modules. they are always sent to the local bus interrupter as standard interrupts. they may be sent to the local bus interrupter as an e dge sensitive interrupt or they can be sent to a 64-bit counter. the following functions can be assigned to the irq[1] or irq[2] signal lines: ? vmebus interrupter: the vmebus interrupter allows vmebus interrupts to be generated as defined in the vmebus standard. for more information see ?interrupt controller? on page 137 . ? programmable pulse generator: this generator allows a pulse on the vmebus irq[1]o or irq[2]o signal line to be generated. the width of the pulse generated is programmable from 120 ns to 1.97 ms in approximately 30ns increments. ? programmable clock generator: enables a free running clock to be generated on irq[1] or irq[2]. the period of the clock generator is programmable from 2.04us to 17.11sec in approximately 1.02us increments. this provides frequencies from 0.49mhz to 0.06hz. ? fixed 0.98mhz clock: generated on irq[1] or irq[2] signal line. rmw access to a mailbox register from the vmebus is not guaranteed to be indivisible. the semaphore re gisters should be used to control access if the rmw feature is required. when the irq[1]_ or irq[2]_ signal lines are used for the broadcast interrupt or 64-bit counter features, they must not be used for vmebus interrupt signals by any other boards. these features are not defined in the vmebus standards. the features can be programmed in the vme bus interrupt control registers (see section 10.4.70 on page 311 ).
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 70 80a3020_ma001_08 broadcast interrupt although the tsi148 irq[1] and irq[2] signal s can be used as vmebus interrupts (as defined by the american national standard for vme64 extensions ), the tsi148 can also use one of the irq[1] or irq[2] signals as a broadcast interrupt. the broadcast interrupt allows a board to send an interrupt to multiple boards. si nce all the boards receiv e the interrupt at the same time, the interrupt can be used as a synchronizing event. in this mode, the transmitting board transmits a pulse on the irq[1] or irq[2] signal line. the receiving boards are programmed to treat the ir q[1]_ or irq[2]_ signal as an edge sensitive interrupt. there is no vmebus interrupt acknow ledge cycle for a broadcast interrupt. the interrupt is treated as a local interrupt on the receiving boards. an interrupt can be broadcast in multiple ways . either the pulse generator can be programmed to generate a single broadcast interrupt or the programmable clock generator can be used to generate periodic broadcast interrupts. when the pulse generator is enabled and the bip bit is set in the vmebus interrupt control register (see section 10.4.69 on page 308 ), a single interrupt is broadcast. the broadcast pulse generator timer register (see section 10.4.67 on page 306 ) is used to program the pulse width. a new pul se should not be generated when the bips bit is set in the vmebus interrupt control register. when th e programmable clock generator is enabled, periodic interrupts are broadcast. the broadc ast programmable clock timer register (see section 10.4.68 on page 307 ) is used to program the interrupt rate. 64-bit counter there is a 64-bit counter which can be incremented by a signal on the irq[1]_ or irq[2]_ signal line. in this mode, one board transmits a clock on either the irq[1] or irq[2] signal lines and the receiving boards use this clock si gnal to increment their 64-bit counter. this feature provides a reference counter that is synchronized on all the boards. the transmitting board can also be a receivin g board. the clock can be derived from the programmable clock generator or the 0.98 mhz clock. when the 0.98 mhz clock is used, the 64-bit counter can provide a unique time stamp every 1.02 s. 2.3.6.5 sysfail operation for more information on sysfail functionality refer to section 5.4.2 on page 130 . 2.3.6.6 vmebus configuration for more information on vmebus configuration refer to section 5.4.2 on page 130 . the transmitting board can also be a receiving board.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 71 80a3020_ma001_08 2.3.7 tsi148 as a vmebus system controller the tsi148 supports the following system controller functions: ? vmebus arbiter with three modes of programmable arbitration: ? priority (pri) ? round-robin-select (rrs) ? single level (sgl) ? iack daisy-chain driver ? sysreset driver: provides a global system reset ? global vmebus timer: monitors the vmebus and generates a berr_ when there is no vmebus activity for the programmed value ? system clock driver: generates a 16 mhz system clock 2.3.7.1 arbiter the tsi148 vmebus arbiter is programmable. all three of the following arbitration modes defined by the vmebus standard are supported: ? priority (pri) ? round-robin-select (rrs) ? single level (sgl) a 16 us arbitration timer is included in the tsi148 to prevent a bus lock-up from occurring when no requester assumes mastership of the bu s after the arbiter has issued a grant. this timer can be enabled or disabled in the vmebus control and status register (see section 10.4.34 on page 255 ). 2.3.7.2 iack daisy-chain driver an iack daisy-chain driver is included in the tsi148 as part of the system controller functionality. this feature ensures that th e timing requirements for starting the iack daisy-chain are satisfied. 2.3.7.3 sysreset driver a sysreset driver is included in the tsi148 to provide a global system reset. the srsto signal is asserted in the following cases: th e lsrsti_ pin is asserted, the sreset bit is asserted in the vmebus control status register, or the pursti_ pin is asserted. the srsto signal is always asserted for at least 200 ms . srsto is normally connected to the vmebus sysreset_ signal through an inverting open collector buffer.
2. vme interface tsi148 pci/x-to-vme bus bridge user manual 72 80a3020_ma001_08 2.3.7.4 global vmebus timer the tsi148 has a vmebus global timer that monitors vmebus cycles and generates a berr signal when there is no vmebus slave response for the programmed time period. the global timer only monitors vmebus cycles when the system controller function is enabled. the global timer is compatible with sct, blt, mblt, 2evme, and 2esst transfers. the global time-out period can be programmed for 8, 16, 32, 64, 128, 256, 512, 1024, 2048 s. this timer can be enabled or disabled in the vmebus control and status register (see section 10.4.34 on page 255 ). 2.3.7.5 system clock driver tsi148 generates the system clock (sysclk) signal when it is configured as the system controller. the sysclk signal is in spec for the following pci/x clock frequencies: 33.3, 66.6, 100, or 133 mhz. the sysclk pin is connected through an external driver to the vmebus. sysclk operates at 16 mhz. the external driver is enabled through the scon pin (see section 8.4.2 on page 161 ). 2.3.7.6 configuration the system controller functions can be configured at power-up. the system controller functionality can be enabled or disabled, or th e auto system controller (scon) function can be used. the auto scon function automatically enables the system controller functions when the board is installed in slot 1. table 10 on page 135 shows the different signal combinations that enable or disable the scon functionality.
tsi148 pci/x-to-vme bus bridge user manual 73 80a3020_ma001_08 3. pci/x interface this chapter describes the main features and functions of the tsi148 ? . the following topics are discussed: ? ?overview of the pci/x interface? on page 74 ? ?pci mode? on page 74 ? ?pci-x mode? on page 88
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 74 80a3020_ma001_08 3.1 overview of the pci/x interface the pci/x interface can be configured to operate in pci mode or pci-x mode. pci-x mode is described in section 3.3 on page 88 . 3.2 pci mode tsi148 is compliant with the pci local bus specification (revision 2.2) . 3.2.1 pci target the pci target supports the pci protocol, 32-bit and 64-bit data transfers, and 32-bit and 64-bit addresses. the pci target supports configuration cycles to pci configuration registers and memory space accesses. the linkage module provides acc ess to the combined register group (crg) and the vmebus (see section 10.1 on page 194 for more register information). the vme master provides the interface between the linkage module and the vmebus. the pci target does not respond to pci i/o transfers. 3.2.1.1 pci target buffers the pci target shares buffers between the pci and pci-x protocols. when the pci/x bus is configured for pci mode, only 512 bytes of the 4 kbyte read buffer can be used. the read buffer is segmented into two parts: a data queue and a command queue. the command queue stores address and command information from the pci bus and can accept one delayed transaction. the data queue stores up to 512 bytes of data. the pci target stores the address and command information in the command queue when servicing a read request from the pci bus master. the amount of data pre-fetched and stored in the read buffer is determined by the read command (see table 3 on page 78 ). the write buffer receives data and commands from the pci bus. the write buffer is segmented into two parts: data queue a nd command queue. the 4 kbyte data queue is designed for large, burst transfers. the command queue stores address and command information and can accept up to 40 entries. th e write buffer is full when either the command or data queue is full.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 75 80a3020_ma001_08 3.2.1.2 transaction mapping the pci bus is capable of many different tr ansaction types, incl uding: single beat transactions, burst transactions, each with flex ible byte enable patterns. these transactions must be mapped to corresponding transactions on the vmebus. there are many different modes and protocols supported by the vme bus and the numerous programmable options. the following rules can be applied to transactions: ? writes ? during a pci bus write, the selected bytes on the pci bus maps directly to the destination bus. the chip does not write to bytes on the destination bus that are not selected on the pci bus. ?reads ? single byte reads on pci maps to a single byte read on the destination bus. if the pci master inserts initial wait states during a read transaction (irdy_ is not asserted one clock after frame_), the transaction is a burst and the pci target prefetches data from the vmebus based on the programming in the outbound translation attribute register (see section 10.4.26 on page 241 ). ? read line and read multiple commands from a pci master causes data to be prefetched from the vmebus based on the programming in the outbound translation attribute register. ? the pci target does not merge, combine, or gather transactions. because of the different bus widths, a single beat transaction on the pci bus may map to a multi beat transaction on the destination bus. a transa ction that completes in a single bus tenure on the pci bus may not complete in a sing le bus tenure on the destination bus. pci-to-vme address mapping the pci target has eight programmable pci bus target images which map pci transactions to vme address space. the pci target maps a pci address to the destination address space using eight programmable target images. these target im ages provide windows into the vmebus from the pci bus. the pci address is compared with the address range of each target image, and if the address falls within the specified range, an of fset is added to the incoming address to form the destination address. any locations with read sensitive bits should be accessed using a byte read or a read that matches the width of the location. there is a one-to-one correspondence between the bytes written on the pci bus and bytes written on the destination bus. pci bus writes with byte holes do not result in writes to the non-selected bytes.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 76 80a3020_ma001_08 the incoming address is within the target images window if the incoming address is greater than or equal to the starting address and less than or equal to the ending address. figure 10 shows the programmable starting address, ending address, and translation offset. figure 10: pci target image programmable address offset 3.2.1.3 pci transactions all transactions through the pci target are co mpleted on the vmebus in the same order that they are completed on the pci bus. a read transaction forces all previously issued posted write transactions to be flushed from the buff ers. all posted write transfers are completed before a read is begun to make sure that all transfers are completed in the order issued. for more information on transaction mapping, refer to section 3.2.1.2 on page 75 . commands the pci target responds to the following pci bus commands: ? memory read ? memory write ? configuration read ? configuration write ? memory read multiple ? dual address cycle ? 64-bit address transactions ? memory read line ? memory write and invalidate all programmable target images should decode unique address ranges. however, if the target images overlap, slave image zero has the highest priority and slave image seven has the lowest priority. starting address ending address translation offset p ci/x a ddress vme addre ss a63 a63 a63 a16 a16 a16
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 77 80a3020_ma001_08 pci read transaction during a read, the pci target uses delayed trans actions. delayed read transactions are used in order to free the pci bus from waiting for th e potentially long vmebus arbitration and transfer. the pci target supports one delayed read transaction. tsi148 manages the completion of the read transaction on the vmebus. when the pci target receives a read request, the pci target saves the information required to complete the transfer and then retries the pci bus master. this allows the pci bus to be used by other pci bus masters while tsi148 completes the transfer. the pci target continues to retry the pci bus master until the vmebus transf er has been completed. if any other pci bus masters try to use the pci target, they are re tried. if the read transfer completes on the vmebus and the pci master does not return within 2 15 pci bus clocks, the read data is discarded (flushed) and the transfer is terminated. the pci target uses its 512 byte data queue for storing prefetched read data. a prefetch read does not extend past the ending address defined by the pci target image (see section 10.4.20 on page 235 ). the pci bus command and pci frame_ signal are used to define how much data to read from the vmebus. if frame_ is asserted for a si ngle clock, the transfer is considered to be a single beat transfer (regardless of the pci command). in this case, a single beat read command is passed to the linkage module. if frame_ is as serted for more than one clock, the transfer is considered a burst transfer and the data size depends on the pci bus command, and the programming of the memory read prefetch disable (mrpfd) bit and the prefetch size (pfs) field of the outbound translation attribute (otat x ) registers (see section 10.4.26 on page 241 ). if the pci bus request is a memory read burst transfer, and the mrpfd bit is clear, the read command passed to the linkage module requests 32 bytes (see table 3 ). if the mrpfd bit is set, a single beat read command is passed to the linkage module. the size of a single beat read command depends on the size of the pci bus. if the pci bus is 32-bit the single beat read command transfers 4 bytes, on a 64-bit bus the command transfers 8 bytes.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 78 80a3020_ma001_08 when a pci bus memory read line burst transfer is received, the read command passed to the linkage module requests 32 bytes. when a pci bus memory read multiple command is received, the data size depends on the pfs bits. the read sizes are 64, 128, 256, or 512 bytes. the pci read operations are summarized in table 3 . the pci bus master is retried until all the request ed data is available in the pci target read buffer. the read then completes on the pci bus. table 3: pci read data size pci transfer pci command mrpfd bit pfs bits linkage command single beat x x x single beat burst read 1 x single beat burst read 0 x 32 bytes burst read line x x 32 bytes burst read multiple x 0 64 bytes burst read multiple x 1 128 bytes burst read multiple x 2 256 bytes burst read multiple x 3 512 bytes tip care must be used when setting the value in the pfs field because the vmebus read is completed before data is transf erred on the pci bus. if the value is too large, time is wasted reading data that is not used. if the value is too small, additional pci bus commands are required. the optimum setting depends on the pci bus masters and the requirements of the application. in many cases, the only read transfers from the pci bus to the vmebus are single beat processor load operations and prefetching is not required.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 79 80a3020_ma001_08 example pci read transaction in this example read, the transaction is sepa rated into request and completion phases. the following list, and figure 11 and figure 12 , show the steps taken in the first part of the transaction, request, and in the second part of the transaction, completion. 1. a pci bus master initiates a read request to a vme peripheral figure 11: pci-vme delayed read request 2. the tsi148 pci target decodes the request and issues a retry to the pci bus master 3. the pci target stores the command and address information in the pci target?s read buffer command queue ? tsi148 supports one delayed read request 4. the pci target makes a read request to the linkage module pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module command data command data
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 80 80a3020_ma001_08 ? table 3 describes the pci bus read commands and the parameters which define the command that is passed to the linkage module 5. after arbitration, the linkage module command and address information is passed to one of the vme master?s read buffer command queues. 6. the vme master issues the read request to the vmebus slave. 7. the vmebus slave satisfies the read request and the data is stored in one of the two 4 kbyte vme master?s read buffer data queues. 8. when the read request is satisfied and the data is queued in the vme master?s data buffer, the vme master makes a return request to the linkage module. tip the linkage module provides a common interface for all the modules and has the following ports: vmebus, pci bus, dma 0, dma1, and registers. the linkage module uses a round-robin arbitration scheme to fairly arbitrate between the ports. tip having two buffers to store data allows the tsi148 vme master to do back-to-back reads on the vmebus.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 81 80a3020_ma001_08 figure 12: pci-to-vme delayed read completion 9. after linkage module arbitration, the read data is passed through the linkage module to the pci target?s read buffer data queue. 10. once the entire read request is queued in the pci target?s read buffer data queue the initial read request can be satisfied on pci. ? if the initiating pci bus master makes a request for the data before the full request is satisfied in the read buffer data que ue, tsi148 retries the pci bus master. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module command data command data
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 82 80a3020_ma001_08 write transaction during write transactions, the external master wr ites data into the pci target write buffer. all writes are posted. the buffer stores the data ne cessary to complete a pci write transfer and immediately acknowledges the transaction on the pci bus. acknowledging the transaction frees the pci bus from waiting for the potentially long vmebus arbitration and transfer. this allows the pci bus to be used by other pci bus masters while tsi148 completes the posted write transaction on the vmebus. if the posted write buffer is full, the pci target retries the pci bus master until there is space available in the write buffer. the pci target write buffer includes a 40 deep command queue and a 4 kbyte data queue. the pci target write buffer stores the commands and data in any combination of single and burst transactions. when a transfer is completed on the pci bus, the data is transferred to the linkage module.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 83 80a3020_ma001_08 example pci write transaction in this example posted write transaction, the transaction completes in one phase through the device. the following list, and figure 13 , show the steps taken in the transaction. 1. an external pci bus master initiates a write to a vmebus slave. figure 13: pci-to-vme posted write 2. the pci target puts the address and command information in its command queue ? all write transactions are posted within the pci target?s write buffer data queue. the pci target?s write buffer data queue is 4 kbytes. 3. the pci target puts the corresponding data into its data queue 4. the pci target accepts write data until the write buffer fills or the transaction ends. 5. the pci target then sends a transaction request to the linkage module. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer module linkage command data command data
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 84 80a3020_ma001_08 6. after arbitration, the linkage module passes the command information, address information, and the write data to one of the vme master?s write buffers. 7. the vme master completes the write tran saction to the addressed vmebus slave. transaction terminations the pci target can terminate a transaction with a retry or a disconnect. the pci target terminates the transaction with a retry in the following cases: ? the transaction is a memory write and the pci target write buffer is full ? the transaction is the first transaction of a memory read ? the transaction is a memory read that does not match a pending memory read ? the transaction is a memory read that matches a pending memory read but the data is not available the pci target terminates the transaction with a disconnect in the following cases: ? a write with byte holes is received and th e stop on byte holes (sbh) bit in the pci control register is set (see section 10.4.36 on page 261 ) ? a transfer reaches the end of a pci target image ? the burst ordering is non-linear ? a burst read requires more data than was prefetched ? a write burst fills the pci target write buffer tip having two write buffers allows the vme ma ster to accept two write transactions from the linkage module. the tsi148 pci target never terminates a transaction with a target-abort.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 85 80a3020_ma001_08 3.2.2 pci master the pci master provides the interface between linkage module and the pci bus. the pci master supports a 32-bit and 64-bit data bus and 32-bit and 64-bit addresses. 3.2.2.1 pci master commands the pci master can generate the following pci bus commands: ? memory read: a memory read command is used when the requested byte count is less than or equal to 4 bytes. ? memory read multiple: the memory read mult iple command is used when the requested byte count is greater than 32 bytes. ? memory read line: a memory read line command is used when the requested byte count is greater than 4 bytes and less than or equal to 32 bytes. ? memory write ? dual address cycle: a dual address cycle is generated when the pci address is greater than 32-bits. 3.2.2.2 pci master buffers the pci master has one read buffer and one write buffer. the buffers are segmented into two parts: a data queue and a command queue. both the read and write buffer command queues are six entries deep. the read buffer data queue is 512 byte while the write data buffer is 4 kbyte. the read buffer stores linkage module commands when servicing a read request from the vmebus to the pci bus. the pci master reque sts the pci bus when it receives a read command from the linkage module. after the read transaction has been satisfied on the pci bus, and the pci read buffer data queue has the requested data, the pci master transfers the data through the linkage module to the vmebus. the write buffer stores linkage module commands and data. the pci master requests the pci bus when it receives write data from the li nkage module. the write buffer is considered full when either the command queue or data queue is full. 3.2.2.3 pci master bandwidth control the pci bus latency timer can be used to cont rol the pci bus bandwidth used by tsi148. the pci master requests the pci bus when it has a tran saction to complete (for example, when the pci master receives a command from the linkage module or when the master needs to complete a previously received command). the pc i master maintains mastership of the pci bus until the linkage module command is completed or until the pci bus grant is removed and the latency timer has expired.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 86 80a3020_ma001_08 3.2.3 pci bus exception handling tsi148 includes error diagnostic registers which capture information when an error occurs. the information captured includes the pci bus address and command (see section 10.4.41 on page 272 ). the error diagnostic registers are updated when the first error occurs. if another error occurs before software has examined the registers, the information is not captured and the overflow bit is set. the following list details the error diagnostic registers in tsi148: ? error diagnostic pci address upper (edpau) ? error diagnostic pci address lower (edpal) ? error diagnostic pci attributes (edpat) 3.2.3.1 pci master exception handling the error diagnostic registers are updated when tsi148 is pci master and one of the following errors occurs: the master retry count is exceeded (programmed in the pci control / status register, see section 10.4.36 on page 261 ), a master-abort or target-abort is received. when the pci master receives a master-abort, target-abort, or the maximum count is exceeded the following steps are taken: ? returns all ffs on vmebus with the dtack signal ? log status information and update pci bus error diagnostic registers ? optional step: generate interrupt when the pci master detects a data parity error the following steps are taken: ? generate perr (if enabled) ? log status information and update pci bus error diagnostic registers ? optional step: generate interrupt 3.2.3.2 pci target exception handling the error diagnostic registers are updated when the pci target detects an address parity error, a data parity error, or a delayed transaction time-out occurred. tip the tsi148 interrupt controller can be programmed to generate an interrupt when the exception registers are updated.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 87 80a3020_ma001_08 when the pci target detects a address pa rity error the following steps are taken: ? generate serr (if enabled) ? log status information when the pci target detects a data pa rity error the following steps are taken: ? generate perr (if enabled) ? log status information and update pci bus exception registers ? optional step: generate interrupt when the pci target detects a delayed trans action time-out the following steps are taken: ? discard data ? log status information and update pci bus exception registers ? optional step: generate interrupt if the pci target detects the assertion of the serr_ signal, no action is taken.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 88 80a3020_ma001_08 3.3 pci-x mode tsi148 is compliant with the pci-x addendum to pci local bus specification (revision 1.0b) . 3.3.1 pci-x target the pci-x target supports 32-bit and 64-bit data transfers and 32-bit and 64-bit addresses. the pci-x target supports configuration cycles to pci-x configuration registers and memory space accesses. the linkage module provides acces s to the combined register group and the vmebus. the vme master provides the interface between the linkage module and the vmebus. the pci-x target does not respond to pci-x i/o transfers. 3.3.1.1 pci-x target buffers the pci-x target shares buffers between the pci and pci-x protocols. when the pci-x bus is configured for pci-x mode, the entire 4 kbyte pci-x target read buffer can be used. the read buffer is segmented into two parts: a data queue and a command queue. the command queue stores address and attributes from th e pci-x bus and can accept up to six split transactions. the data queue stores up to 4 kbyte of data. the pci-x target read buffer stores the address and attributes of the transaction in the command queue when servicing a read request from the pci-x bus master. the requested data comes from the vmebus, through linkage module, to the pci-x target read buffer data queue. the amount of data in read buffer depends on the requested byte-count in the attribute phase of the pci-x transaction. the write buffer receives data and commands from the pci-x bus. the write buffer segmented into two parts: data queue a nd command queue. the 4 kbyte data queue is designed for large, burst transfers. the command queue stores address and attributes from pci-x transactions and can accept up to 40 entr ies. the write buffer is full when either the command or data queue is full.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 89 80a3020_ma001_08 3.3.1.2 transaction mapping the pci-x bus is capable of many different transaction types, in cluding: single beat transactions, burst transactions, each with flex ible byte enable patterns. these transactions must be mapped to corresponding transactions on the vmebus. there are many different modes and protocols supported by the vme bus and the numerous programmable options. the following rules can be applied to transactions: ? writes ? during a pci-x bus write, the selected bytes on the pci-x bus map directly to the destination bus. the tsi148 does not write to bytes on the destination bus that are not selected on the pci-x bus. ? during a pci-x bus memory write block, the number of bytes in the byte count, along with the starting address map directly to the destination bus. ?reads ? the pci-x bus protocol includes a byte count. the number of bytes requested from the destination bus generally matches the byte count requested by the pci-x bus master. ? the pci-x target does not merge, combine, or gather transactions. because of the different bus widths, a single beat transaction on the pci-x bus may map to a multi beat transaction on the destination bus. a tr ansaction that completes in a single bus tenure on the pci-x bus may not complete in a single bus tenure on the destination bus. pci-x-to-vme address mapping the pci-x target has eight programmable pci-x bus target images which map pci-x transactions to vme address space. the pci-x target maps a pci-x address to the destination address space using eight programmable target images. these target im ages provide windows into the vmebus from the pci-x bus. the pci-x address is compared with the address range of each target image, and if the address falls within the specified rang e, the offset is added to the incoming address to form the destination address. any locations with read sensitive bits should be accessed using a byte read or a read that matches the width of the loca tion (preferably the memory read dword command). there is a one-to-one correspondence between the bytes written on the pci-x bus and bytes written on the destination bus.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 90 80a3020_ma001_08 the incoming address is within the target images window if the incoming address is greater than or equal to the starting address and less than or equal to the ending address. figure 14 shows the programmable starting address, ending address, and translation offset. figure 14: target image programmable address offset 3.3.1.3 pci-x transactions all transactions through the pci-x target are completed on the vmebus in the same order that they are completed on the pci-x bus. a read transaction forces all previously issued posted write transactions to be flushed from the buffers. all posted write transfers are completed before a read is begun to make sure that all transfers are completed in the order they are issued. for more information on transaction mapping, refer to section 3.3.1.2 on page 89 . commands the pci-x target responds to the following pci-x bus commands: ? memory read dword ? memory write ? configuration read ? configuration write ? split completion ? dual address cycle ? memory read block ? memory write block all programmable target images should decode unique address ranges. however, if the target images overlap, slave image zero has the highest priority and slave image seven has the lowest priority. starting address ending address translation offset p ci/x a ddress vme addre ss a63 a63 a63 a16 a16 a16
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 91 80a3020_ma001_08 pci-x read transaction the pci-x target uses split read transactions for all reads, which frees the pci/x bus from waiting for the potentially long vmebus arbitration and transfer. tsi148 supports up to six split reads. when the pci-x target receives a read request, the pci-x target saves the information required to complete the transfer and then is sues a split response termination to the pci-x bus master. this allows the pci-x bus to be used by other pci-x bus masters while tsi148 completes the transfer. if the pci-x target receives a read request from a pci-x bus master and the pci-x target read buffer command queue is full, the pci-x target retries the pci-x bus master until there is space available in the read buffer. after the pci-x target has issued the split re sponse to the pci-x bus master, the pci-x target then issues a read command to the linkage module for the requested byte count. as defined in the pci-x addendum to pci local bus specification (revision 1.0b) , byte counts up to 4 kbyte are supported. when the data is returned from the vme master through the linkage module to the pci-x target read buffer, the tsi148 pci-x master initiates a split completion and transfers the data from the pci-x target read buffer to the requesting pci-x bus master. if the requested read extends past the ending address defined by the target image (see section 10.4.20 on page 235 ), the pci-x master provides data up to the end of the image and then terminates the transaction with a split completion error mess age to the initiating pci-x bus master (see section 3.3.3.1 on page 99 ). tip for more information on the pci-x impl ementation of split reads, refer to the pci-x addendum to pci local bus specification (revision 1.0b) . tip a split response means pci-x target does not have to issue retries as the read is being completed on the vmebus wh ile waiting for the requested data.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 92 80a3020_ma001_08 example pci-x read transaction in this example pci-x-to-vme read, the transaction is separated into request and completion phases. the following list, and figure 15 , show the steps taken in the first part of the transaction (request). the second part of the list, and figure 16 , shows the next part of the transaction (completion). 1. a pci-x master initiates a read request to a vmebus slave figure 15: pci-x-to-vme delayed read request 2. the tsi148 pci-x target decodes the request and issues a split response termination to the initiating pci-x bus master 3. the pci-x target stores the command, address, and attribute information in the pci-x target?s read buffer command queue ? tsi148 supports up to six split read transactions pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module command data command data
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 93 80a3020_ma001_08 4. the pci-x target sends a read request to the linkage module with the vme address information and required byte count ? tsi148 supports byte counts of up to 4 kbytes 5. after arbitration, the linkage module comma nd and address information is passed to a vme master read buffer command queue. 6. the vme master issues the read request to the vmebus slave . 7. the vme slave satisfies the read request and the data is stored in one of the two, 4 kbyte vme master read buffer data queues. 8. once the full byte count of the read request is satisfied and the data is queued in a vme master?s buffer, the vme master makes a return request to the linkage module. tip the linkage module provides a common interface for all the modules. the linkage module interface has the following ports: vmebus, pci bus, dma 0, dma1, and registers. the linkage module uses a round-robin arbitration scheme to fairly arbitrate between the ports. tip having two buffers to store data allows the tsi148, through the vme master, to do back-to-back reads on the vmebus.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 94 80a3020_ma001_08 figure 16: pci-x-to-vme delayed read completion 9. after linkage module arbitration, the read data is passed through the linkage to the pci-x target read buffer data queue. 10. once the entire read request is queued in the pci-x target?s read buffer data queue, tsi148 issues a split completion through the pci-x master onto the pci-x bus to the original, initiating pci-x bus master. 11. the pci-x master transfers the data from the pci-x target?s read buffer data queue to the pci-x bus master. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer module linkage command data command data
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 95 80a3020_ma001_08 3.3.1.4 pci-x write transaction during write transactions, the external master writes data into the pci-x target write buffer. all writes are posted and the buffer stores the data necessary to complete a pci-x write transfer and immediately acknowledges the transaction on the pci-x bus. acknowledging the transaction frees the pci-x bus from waiting for the potentially long vmebus arbitration and transfer. this allows the pci-x bus to be used by other pci-x bus masters while tsi148 completes the posted write transaction on the vmebus. if the posted write buffer is full, the pci-x target retries the pci-x bus master until there is space availabl e in the write buffer. the pci-x target write buffer has a 40 entry command queue and a 4 kbyte data queue (see section 3.3.1.1 on page 88 ). the pci-x target buffer stores the commands and data in any combination of single and burst transactions. when a transfer is completed on the pci-x bus, the data is transferred to the linkage module. if the pci-x target receives a write command that extends past the space programmed in the target image, the pci-x target accepts the data up to the end of the target image and then issues a disconnect.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 96 80a3020_ma001_08 example pci-x write transaction in this example pci-x-to-vme write transaction, the data passes through tsi148 through the pci-x target, to the linkage module, and ends at the vme master. the following list, and figure 17 , show the steps taken in the write transaction. 1. a pci-x master initiates a write to a vmebus slave. figure 17: pci-x-to-vme posted write 2. the pci-x target puts the address and command information in its write buffer command queue ? all write transactions are posted within the pci-x target write buffer data queue. the pci-x target write buffer data queue is 4 kbytes. 3. the pci-x target puts the corres ponding data into its data queue pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer module linkage command data command data
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 97 80a3020_ma001_08 4. the pci-x target accepts write data until th e write buffer fills or the transaction ends. 5. the pci-x target then sends a transaction request to the linkage module. 6. after arbitration, the linkage module passes the command information, address information, and the write data to a vme master write buffer. 7. the vme master completes the write tran saction to the addressed vmebus slave. 3.3.1.5 transaction termination the pci-x target can terminate a transaction w ith many of the terminations defined in the pci-x specification . for read requests, pci-x target uses split read terminations. the pci-x target terminates a transacti on with a retry in the following cases: ? the transaction is a memory write and the write buffer is full. ? the transaction is a read and the read buffer command queue is full the pci-x target terminates a transaction with a disconnect on an address data boundary (adb) in the following cases: ? a transfer reaches the end of a target image ? a burst write fills the write buffer tip having two sets of write buffers allows the vme master to accept two write commands and data from the linkage module.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 98 80a3020_ma001_08 3.3.2 pci-x master the pci-x master can generate the following pci-x bus commands: ? split completion ? dual address cycle (a dual address cycle is generated when the pci address is greater than 32 bits) ? memory read block ? memory write block 3.3.2.1 pci-x master buffers the pci-x master has one read buffer and one write buffer. the buffers are segmented into two parts: a data queue and a command queue. both the read and write buffer command queues are six entries deep. the read and write data buffers are 4 kbyte. the read buffer stores linkage module commands when servicing a read request from the vmebus to the pci-x bus. the pci-x master requests the pci-x bus when it receives a read command from the linkage module. after the read transaction has been satisfied on the pci-x bus, and the read buffer data queue has the requested data, the pci-x master transfers the data through the linkage module to the vmebus. the write buffer stores linkage module comma nds and data. the pci-x master requests the pci-x bus when it receives a command and write data from the linkage module. the write buffer is considered full when either the command or data queue is full. 3.3.2.2 pci-x master bandwidth control the pci-x bus latency timer can be used to control the pci-x bus bandwidth used by tsi148. the pci-x master requests the pci-x bus when it has a transaction to complete (for example, when the pci-x master receives a command from the linkage module or when it needs to complete a previously received command). the pci-x master maintain s mastership of the pci-x bus until the linkage command is completed or until the pci-x bus grant is removed and the latency timer has expired.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 99 80a3020_ma001_08 3.3.3 pci-x bus exception handling tsi148 includes error diagnostic registers which capture information when an error occurs. the information captured includes the pci-x bus address, attribute, and command (see section 10.4.43 on page 274 ). the error diagnostic registers are updated when the first error occurs. if another error occurs before software has examined the registers, the information is not captured and the overflow bit is set. the following list details the error diagnostic registers in tsi148: ? error diagnostic pci address upper (edpau) ? error diagnostic pci address lower (edpal) ? error diagnostic pci-x attribute (edpxa) ? error diagnostic pci-x split completion message (edpxs) ? error diagnostic pci attributes (edpat) for more information on tsi148 error diagnostic registers, refer to section 10.4.43 on page 274 . 3.3.3.1 pci-x master exception handling the error diagnostic registers are updated when tsi148 is pci-x master and one of the following errors occurs: the master retry count is exceeded, a split response time-out occurs, split completion error asserted, or a master-abort or target-abort is received. when the pci-x master receives a master-abort, target-abort, or the maximum retry count is exceeded the following steps are taken: ? return ff?s on vmebus with the dtack signal ? log status information and update pci-x bus exception registers (see section 10.4.43 on page 274 ) ? optional step: generate interrupt when the pci-x master detects a data pa rity error the following steps are taken: ? generate perr (if enabled) ? log status information and update pci-x bus exception registers (see section 10.4.43 on page 274 ) ? optional step: generate interrupt tip the tsi148 interrupt controller can be programmed to generate an interrupt, when the exception registers are updated.
3. pci/x interface tsi148 pci/x-to-vme bus bridge user manual 100 80a3020_ma001_08 3.3.3.2 pci-x target exception handling the error diagnostic registers are updated when the pci-x target detects an address parity error, a data parity error has occurred, or a unexpected split completion is received. when the pci-x target detects a address parity error the following steps are taken: ? generate serr (if enabled) ? log status information when the pci-x target detects a data parity error the following steps are taken: ? generate perr (if enabled) ? log status information and update pci-x bus exception registers (see section 10.4.43 on page 274 ) ? optional: step generate interrupt when the pci-x target receives an unexpect ed split completion the following steps are taken: ? the split completion is discarded and the split completion discarded (scd) bit is set in the error diagnostic pci attribute register (see section 10.4.43 on page 274 ). if the pci-x target detects the asserti on of the serr_ signal, no action is taken.
tsi148 pci/x-to-vme bus bridge user manual 101 80a3020_ma001_08 4. dma interface direct memory access (dma) allows a transa ction to occur between two devices without involving the host processor (for example, a read transaction between a peripheral device and host processor memory). because less time is requ ired to complete transactions, applications that contain one or more dma channels support faster read and write transfers than applications that support only host-assisted transactions. this chapter discusses the followi ng topics about the tsi148 dma: ? ?overview dma controller? on page 102 ? ?architecture? on page 102 ? ?dma buffers? on page 102 ? ?operating modes? on page 103 ? ?direction of data movement? on page 105
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 102 80a3020_ma001_08 4.1 overview dma controller the tsi148 has two independent, single channel dm a controllers that enable the transfer of large blocks of data without processor intervention. each dma controller is programmed by a set of registers that reside within the lcsr group (see section 10.2.3 on page 195 ). each dma controller supports 64-bit addressing on the vmebus and the pci/x bus. the amount of data moved during a command is onl y limited by the 32-bit byte counter, allowing transfer counts to range from 1 byte to 4 gbytes. 4.2 architecture each dma controller connects to the linkage module and uses the pci/x master and vme master to transfer data. the core of the dma controller is the dma buffer - an 8 kbyte buffer. the buffer is used for all transactions regardless of the direction. the dma controllers have been optimized to tr ansfer data over the pci/x bus in multiple cache-line bursts. all interactions with the vmebus are handled by the vme master. the controllers transfer data using 32-bit or 64-bit burst transfers on the pci/x bus and 16-bit, 32-bit, or 64-bit transfers on the vmebus. 4.3 dma buffers each dma controller has an 8 kbyte buffer that is used to hold data transferred between the source and destination bus. for example, if th e transfer is from the pci/x bus to the vmebus, the dma controller requests data from the pci/x master and then sends it to the vme master. the data moves from the pci/x bus into the pci/x master?s read buffer data queue and then through the linkage module to the buffer in the dma controller. the data then moves from the dma buffer through the linkage module to the vme master?s write buffer data queue. the data is then transferred to the vmebus. the combined register group (crg) map decoder can be programmed to allow access to the control registers from the vmebus.
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 103 80a3020_ma001_08 4.4 operating modes there are two operating modes for the dma controller: direct mode and linked-list mode. in direct mode, the dma control registers are programmed by the processor. once the command has completed, the status of the completed command is given within the dma status registers and an optional interrupt is asserted on the int x signal lines (see section 8.4.2 on page 161 ). in linked-list mode, the dma controller executes a list of commands which are stored in system memory. the dma fetches these commands from the pci/x bus. once all the commands have been fetched and executed, the status of the completed commands is given within the dma status registers and, optiona lly, an interrupt is asserted on the int x signal lines. figure 18 shows the direct mode of the dma controller. figure 18: direct mode figure 19 shows the linked-list mode of the dma controller. figure 19: linked-list mode direct mode, same start/end domain direct mode, different start/end domain direct mode, pattern write data read data write transfer program dgo (start) processor done transfer program dgo (start) processor done transfer processor done pattern write program registers program registers data read data write program registers program dgo (start) data write data write pattern write transfer processor desc fetch desc fetch done transfer transfer linked-list mode, various transfers linked list build desc table program dgo (start) desc fetch data read data read
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 104 80a3020_ma001_08 4.4.1 linked-list descriptors the pci/x master is responsible for fetching descriptors from local memory when using linked-list mode. each descriptor consumes 32 bytes and must be aligned on 64-bit boundaries. this structure helps minimize th e pci/x bus bandwidth used when fetching descriptors. table 4 shows the format of a descriptor. each field within the descriptor corresponds to a dma control register. when a descriptor is loaded by the dma controller, each field is placed into its corresponding dma control register (see section 10.4.76 on page 329 ). the descriptors are linked together by the dnla register (that is, the dnla field within a descriptor). this field contains the address with in pci address space where the next descriptor may be found. the last link-descriptor addres s field (lla) within the dnla indicates that this is the last descriptor. descriptors are not prefetched by the pci/x master. a linked-list mode command is started by the pci/x master reading one descriptor. the dma controller then performs the transfer associated with that descriptor. if there are more descriptors to be executed, the fetching of the next descriptor does not occur until the current transf er has completed. table 4: dma controller linked-list descriptors offset bits 63 32 31 0 0x00 dsau dsal 0x08 ddau ddal 0x10 dsat ddat 0x18 dnlau dnlal 0x20 dcnt ddbs
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 105 80a3020_ma001_08 4.5 direction of data movement there are four possible directions for data movement within a transfer. ? pci/x-to-vme: data is read from pci/x and written to the vmebus. the pci/x master fills the dma buffer at the same time the vme master empties the dma buffer. ? vme-to-pci/x: data is read from the vm ebus and written to the pci/x bus. the vme master fills the dma buffer at the same tim e that the pci/x master empties the dma buffer. ? pci/x-to-pci/x: data is read from the pci/x bus and written back sometime later to the pci/x bus. the pci/x master fills the dma buffer to a certain point, after which the pci/x master empties the dma buffer. ? vme-to-vme: data is read from the vme bus and written back sometime later to the vmebus. the vme master fills the dma buffer to a certain point, after which the vmebus master empties the dma buffer. ? data pattern to vme: a data pattern is wr itten into the dma buffer and then written to the vmebus. the pattern generator fills the dma buffer at the same time that the vme master empties the dma buffer. the data patte rn can either be a fixed pattern or an incrementing pattern. for data pattern programming information refer to section 10.4.89 on page 351 . ? data pattern to pci/x: a data pattern is wr itten into the dma buffer and then written to the pci/x bus. the pattern generator fills th e dma buffer at the same time that the pci/x master empties the dma buffer. the data pattern can either be a fixed pattern or an incrementing pattern. for data pattern programming information refer to section 10.4.89 on page 351 . 4.5.1 pci/x-to-vme the tsi148 dma controllers support pci/x-to-vme dma transactions. example dma pci/x-to-vme transaction in this example, there is a dma transaction between the pci/x bus and vmebus. the following list, and figure 20 and figure 21 , show the steps taken in the dma transaction. 1. program the registers in the lcsr group. ? the dma registers set-up the following information: ? source and destination buses, and starting address ? mode of operation
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 106 80a3020_ma001_08 ? attributes ? bus width ? transfer throttling ? dma transfer count figure 20: dma transaction: pci/x-to-vme request 2. once these registers have been programmed, writing to the dgo bit in the dma control register to initiates the dma transfer. 3. the dma controller issues a read request to the linkage module. transfer counts can be between 1byte and 4 gbytes. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module dma controller command data command data buffer control registers
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 107 80a3020_ma001_08 4. after arbitration the linkage module passes the command, address information and transfer size to the pci/x master read buffer command queue. 5. the pci/x master issues a read request to the pci/x target. figure 21: dma transaction: pci/x-to-vme completion 6. once the read request is satisfied or the pci/x master?s read buffer data queue becomes full, the pci/x master makes a request to the linkage module. ? the block size is programmed in the pbks field in the dma control register when the pci/x bus is the source bus (see section 10.4.76 on page 329 ). 7. after arbitration, the read data is passed through the linkage module to the dma controller?s data buffer. the data buffer is us ed to hold data that is transferred between the source and destination bus. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module dma controller command data command data buffer control registers
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 108 80a3020_ma001_08 8. the dma controller issues a write request to the linkage module. 9. after arbitration, the linkage module passes the command information, address information, and write data to a vme master?s write buffer. 10. the vme master completes the write tran saction to the vmebus slave. for large transfers the pci/x master attempts to fill the dma buffer while the vme master transfers data from the dma buffer. 4.5.2 vme-to-pci/x the tsi148 dma controllers support vme-to-pci/x dma transactions. 4.5.2.1 example dma vme-to-pci/x transaction in this example, there is a dma transaction between the vmebus and pci/x bus. the following list, and figure 22 and figure 23 , show the steps taken in the dma transaction. 1. program the registers in the lcsr group. ? the dma registers set-up the following information: ? source and destination buses, and starting address ? mode of operation ? attributes ? bus width ? transfer throttling ? dma transfer count transfer counts can be between 1byte and 4 gbytes.
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 109 80a3020_ma001_08 figure 22: dma transaction: vme-to-pci/x request 2. once these registers have been programmed, writing the dgo bit in the dma control register initiates the dma transfer. 3. the dma controller issues a read request to the linkage module. 4. after arbitration, the linkage module passes the command information and address information to a vme master read buffer. 5. the vme master issues a read request to the vmebus slave. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module dma controller command data buffer control registers command data
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 110 80a3020_ma001_08 figure 23: dma transaction: vme-to-pci/x completion 6. once the read request is satisfied, or the programmed vmebus block size value is satisfied, the vme master makes a request to the linkage module. ? the block size is programmed in the vbks field in the dma control register when vme is the source bus (see section 10.4.76 on page 329 ). 7. after arbitration, the read data is passed through the linkage module to the dma controller?s data buffer. the data buffer is us ed to hold data that is transferred between the source and destination bus. 8. the dma controller then issues a write request to the linkage module. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module dma controller buffer control registers command data command data
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 111 80a3020_ma001_08 9. after arbitration, the linkage module passes command information, address information, and the write data to the pci/x master write buffer?s command and data queues. 10. the pci/x master initiates the write transac tion to the pci/x target . for large transfers the vme master fills the dma buffer while th e pci-x master attempts to transfer data from the dma buffer. 4.5.3 pci/x-to-pci/x the tsi148 dma controllers support pci/x-to-pci/x dma transactions. 4.5.3.1 example dma pci/x-to-pci/x transaction in this example, there is a dma transaction between the pci/x bus and pci/x bus. the following list, and figure 24 and figure 25 , show the steps taken in the dma transaction. 1. program the registers in the lcsr group. ? the dma registers set-up the following information: ? source and destination buses, and starting address ? mode of operation ? attributes ? bus width ? transfer throttling ? dma transfer count transfer counts can be between 1 byte and 4 gbytes.
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 112 80a3020_ma001_08 figure 24: dma transaction: pci/x-to-pci/x request 2. once these registers have been programmed writing the dgo bit in the dma control register initiates the dma transfer. 3. the dma controller issues a read request to the linkage module. 4. after arbitration, the linkage module passes the command, address information, and transfer size are passed to the pci/x master read buffer command queue. 5. the pci/x master issues a read request to the pci/x target . pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module dma controller command data buffer control registers command data
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 113 80a3020_ma001_08 figure 25: dma transaction: pci/x-to-pci/x completion 6. the pci/x target satisfies the read request a nd the data is stored in the pci/x master?s read buffer data queue. 7. once the read request is satisfied, or the pci/x master?s read buffer data queue becomes full, the pci/x master makes a request to the linkage module. 8. after arbitration the read data is passed through the linkage to the dma controllers data buffer. the data buffer is used to hold data that is transferred between the source and destination bus. in this example between the pci/x bus and pci/x bus. 9. the dma controller then issues a write request to the linkage module. 10. upon arbitration the command, address information as well as the write data is passed to the pci/x master write buffer command and data queues. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module dma controller command data buffer control registers command data
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 114 80a3020_ma001_08 11. the pci/x master initiates the write tran saction to the pci/x peripheral. the pci/x master fills the dma buffer to a certain poi nt, after which the pci/x master empties the dma buffer. 4.5.4 vme-to-vme the tsi148 dma controllers support vme-to-vme dma transactions. 4.5.4.1 example dma vme-to-vme transaction in this example, there is a dma transaction between the vmebus and vmebus. the following list, and figure 26 and figure 27 , show the steps taken in the dma transaction. 1. program the registers in the lcsr group. ? the dma registers set-up the following information: ? source and destination buses ? mode of operation ? attributes ? bus width ? transfer throttling ? dma transfer count transfer counts can be between 1 byte and 4 gbytes.
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 115 80a3020_ma001_08 figure 26: dma transaction: vme-to-vme request 2. once these registers have been programmed writing the dgo bit in the dma control register initiates the dma transfer. 3. the dma controller issues a read request to the linkage module. 4. after arbitration, the linkage module passes command information, address information, and transfer size to one of the vme master?s two read buffer command queues. 5. the vme master issues a read request to the vmebus slave. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module dma controller command data buffer control registers command data
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 116 80a3020_ma001_08 figure 27: dma transaction: vme-to-vme completion 6. once the read request is satisfied, or the programmed vmebus block size value is satisfied, the vme master makes a request to the linkage module. ? the block size is programmed in the vbks field in the dma control register when vme is the source bus (see section 10.4.76 on page 329 ). 7. after arbitration, the linkage module passes the read data to the dma controllers data buffer. the data buffer is used to hold data that is transferred between the source and destination bus. 8. the dma controller issues a write request to the linkage module. 9. after arbitration, the command, information, address information, and write data is passed to a vme master write buffer command and data queue. pci/x bus pci/x target read buffer write buffer vme master read buffer write buffer vmebus pci/x master read buffer write buffer vme slave write buffer read buffer linkage module dma controller command data buffer control registers command data
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 117 80a3020_ma001_08 10. the vme master initiates the write transac tion to the vmebus slave. the vme master fills the dma buffer to a certain point, af ter which the vme master empties the dma buffer. 4.5.5 data patterns the tsi148?s dma controller can write data patterns to either vme or pci/x space. the data patterns can be any size transfer, and there are no restrictions on the starting address. the is a starting data pattern is supplied by software. software can also specify whether the pattern should be static or incrementing. the dma controller can be programmed to work in terms of 8-bit patterns (see figure 28 ) or 32-bit patterns (see figure 29 ). figure 28: 8-bit pattern writes xx xx xx 20 .. .. .. 02 00 00 00 1b 20 20 20 20 xx xx 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 xx xx xx 20 20 20 20 ...00 ...08 ...10 ...18 63 0 21 20 xx xx 25 24 23 22 29 28 27 26 2d 2c 2b 2a 31 30 2f 2e 35 34 33 32 39 38 37 36 xx xx xx 3a ...00 ...08 ...10 ...18 63 0 dma control registers static pattern to vme space... incrementing pattern to pci space... start pattern = 0x20 destination address = 0x...02 transfer count = 27 dsad ddad dctl 22 23 24 25 xx xx 20 21 2a 2b 2c 2d 26 27 28 29 32 33 34 35 2e 2f 30 31 3a xx xx xx 36 37 38 39 ...00 ...08 ...10 ...18 63 0 20 20 xx xx 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 xx xx xx 20 ...00 ...08 ...10 ...18 63 0 incrementing pattern to vme space... static pattern to pci space...
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 118 80a3020_ma001_08 figure 29: 32-bit pattern writes 4.5.5.1 data patterns and endianness when writing 32-bit patterns to pci/x space, th e pattern is not endian byte swapped. also, when writing 332-bit patterns, a transfer count that is not an even multiple of four is rounded off of the last data pattern written to either vme or pci/x space. the rounding off occurs on the pattern according to the address space bei ng written to. for example, a pattern written to pci/x space is rounded off starting from the left side (most significant bit) of the pattern, while a pattern written to vme space is rounded off starting from the right (or least significant bit) side of the pattern. f1 11 11 20 .. .. .. 02 00 00 00 1b dma control registers start pattern = 0xf1111120 destination address = 0x...02 transfer count = 27 dsad ddad dctl 11 20 f1 11 xx xx f1 11 11 20 f1 11 11 20 f1 11 11 20 f1 11 11 20 f1 11 11 xx xx xx 11 20 f1 11 ...00 ...08 ...10 ...18 63 0 11 20 xx xx 11 21 f1 11 11 22 f1 11 11 23 f1 11 11 24 f1 11 11 25 f1 11 11 26 f1 11 xx xx xx 11 ...00 ...08 ...10 ...18 63 0 static pattern to vme space... incrementing pattern to pci space... 11 20 f1 11 xx xx f1 11 11 22 f1 11 11 21 f1 11 11 24 f1 11 11 23 f1 11 11 xx xx xx 11 25 f1 11 ...00 ...08 ...10 ...18 63 0 11 20 xx xx 11 20 f1 11 11 20 f1 11 11 20 f1 11 11 20 f1 11 11 20 f1 11 11 20 f1 11 xx xx xx 11 ...00 ...08 ...10 ...18 63 0 incrementing pattern to vme space... static pattern to pci space...
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 119 80a3020_ma001_08 4.5.6 dma transaction termination tsi148 dma activity can be terminated through either a transfer completion, commanded stop, commanded abort, or a detected error abort. 4.5.6.1 transfer completion in most cases, a direct mode transfer or a linked-list mode transaction finishes without intervention or error. in direct mode operation, the end of the transfer is considered completion. in linked-list mode operation, the end of the last transfer of a command is considered completion. when the transaction is complete, the dma controller returns a done status to the dma status (dsta) register (see section 10.4.77 on page 334 ) and, when enabled, interrupts the processor. 4.5.6.2 commanded stop the commanded stop termination can be used during linked-list transactions. software is used to set the commanded stop bit (pau) in the dma control register (see section 10.4.76 on page 329 ). this bit can be set at any time during a dma transaction. when the dma controller reaches a transfer boundary (that is, ready to fetch the next descriptor), it stops all dma activity. if there are more linked-list commands to be performed, the dma controller returns a paused status to the dsta register and, optionally, interrupts the processor. if the last command ha s completed, then the dma controller returns a done status to the dsta register (see section 10.4.77 on page 334 ). once the transaction has been stopped, the linke d list transaction can be started again at any time. the dma controller starts the transaction where it left off. the first descriptor fetch occurs from the address that was placed within the dma next link address (dnla) register during the previously completed transfer (see section 10.4.90 on page 355 ). 4.5.6.3 commanded abort the commanded abort termination can occur on either direct mode or linked-list mode. software is used to set the commanded abort bit in the dma control (ctl) register (see section 10.4.76 on page 329 ). this bit can be set at any time during a transaction. when the commanded abort bit is set, the dma controller aborts all dma activity. this is considered a non-recoverable termination, and it takes affect immediately after the bit has been set. if the commanded abort took affect before all commands were completed, then the dma controller returns an abort status to the dsta register and, optionally, interrupts the processor. if all commands completed before the commanded abort took affect, then the controller returns a done status to the dma status (dsta) register (see section 10.4.77 on page 334 ).
4. dma interface tsi148 pci/x-to-vme bus bridge user manual 120 80a3020_ma001_08 4.5.6.4 detected error abort if any of following system errors are encountered, the dma controller aborts all dma activity: ? pci/x master received a master abort ? pci/x master received a target abort ? pci/x master exceeds the maximum retry count ? vme master received a bus error ? vme master received slave termination this is considered a non-recoverable termination, and takes affect immediately after the condition has been detected. once all dma activity has ceased, the dma controller returns the appropriate error status to the dsta register and, if enabled, interrupts the processor. 4.5.7 dma interrupts the dma controller sends an interrupt to the in terrupt controller when it returns to the idle state. if the dma interrupt in the in terrupt controller is enabled, an int x signal line is asserted to signal the interrupt. 4.5.8 transfer throttling the tsi148 has the ability to throttle dma transfer s. this features is for situations where the vmebus or pci/x bus bandwidth that is consumed by the dma controller could swamp the system with dma activity. there are several methods available to control the bandwidth consumed by the dma controller. the pci/x bus latency timer and the vmebus time-on timer can be used to control the vmebus and pci/x bus time allocated to the tsi148. in addition the dma controller has a programmable block size and back-off timer. the block size can be set from 32 to 4096 bytes. the back-off value can be set from 0 to 64 us. the block size and back-off time are independently programmable for each bus. the dma controller requests the selected block size and when that request is satisfied, it waits for the time set by the back-off timer before requesting a new block. the dsta register can be read at any time to obtain the operating status of the controller. tip larger dma block sizes are more efficient but increase latency. smaller dma block sizes reduce latency but are less efficient.
tsi148 pci/x-to-vme bus bridge user manual 121 80a3020_ma001_08 5. resets, clocks, and power-up options reset options include how a device or components of a device are reset, and how the device responds to a reset event. clock characteris tics include how a device?s operating frequency is set, and if required, how it should be synchronized with other devices in a system. power-up options include device-specific capabilities th at are configured upon the completion of a power-up reset sequence. these include functions such as bus mode (pci versus pci/x) and data width size (32-bit versus 64-bit). this chapter discusses the following topics about tsi148 resets, clocks, and power-up options: ? ?overview of resets, clocks, and power-up options? on page 122 ? ?resets? on page 122 ? ?clocks? on page 127 ? ?power-up options? on page 128
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 122 80a3020_ma001_08 5.1 overview of resets, clocks, and power-up options this section describes the reset capabilities, cl ocking requirements, and power-up options for the tsi148 device. 5.2 resets tsi148 can be reset from both the vmebus and the pci/x bus. the device responds to both hardware and software reset events. figure 30 shows the logical representation of the tsi148 reset structure. figure 30: tsi148 reset structure vme services clock services general services power-up and reset > 200ms pursti_ srsti_ lrsti_ lsrsti_ vctrl register sreset lreset csrbsr and csrbcr register lrsts and lrstc bit lrsto_ srsto (power-up, reset registers, vme transceiver control) (vme arbiter, vmebus timer, vmebus interrupter, gscr and csr registers) (sysclk, pll and pll clock dividers) (most registers, internal logic) hold for lrsto_ held for >= 15us gctrl register lrst bit pll_rsti_ (from the vmebus, sysreset_) (from the pci/x bus) (from local reset logic) (self-clearing) (from vme board) (vme cr/csr registers) (to vmebus) (to pci/x bus)
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 123 80a3020_ma001_08 5.2.1 reset inputs and outputs tsi148 has the following reset inputs and reset outputs: ? reset inputs ? power-up reset (pursti_): this signal resets all of the tsi148 logic. when it is asserted both the pci/x and vmebus can be reset through the tsi148 reset outputs lrsto_ and srsto. ? vmebus system reset in (srsti_): this si gnal resets all of the tsi148 logic which is sensitive to sysreset. typically, the backplane sysreset_ is connected to this signal through a transceiver. when srsti_ is asserted the pci/x bus can be reset through the tsi148 reset output lrsto_. ? pll reset (pll_rsti_): this signal resets the tsi148 pll. the pll_rsti_ pin has to be asserted until the clock and power are stable. ? jtag test reset (trst_): provides asynchronous initialization of the tap controller in the tsi148. this signal must be tied to ground if jtag is not used in the system. ? local bus (pci/x) reset in (lrsti_): assertion of this signal resets all tsi148?s internal logic except the logic required for vme services and clock service (see figure 30 ). this signal should be connected to the board?s local bus (pci/x) reset. ? local system reset (lsrsti_): this sign al is used to reset the vmebus from the pci/x bus. when this signal is asserted the tsi148 output srsto is asserted. this signal allows on board logic to generate a vmebus system reset.
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 124 80a3020_ma001_08 ? reset outputs ? vmebus system reset out (srsto): this signal is used to reset the vmebus. typically, this signal is connected to the backplane sysreset_ signal through an inverting open collector buffer. when srsto is asserted, the vmebus sysreset_ signal is asserted. srsto can be asserted either through hardware or software events. the hardware reset events are detailed in figure 30 . the signal can be asserted through software by setting the sreset bit in the vmebus control (vctrl) register (see section 10.4.34 on page 255 ). the sreset bit is self-clearing. ? local bus (pci/x) reset out (lrsto_): this signal resets local (pci/x) resources. lrsto_ can be combined with other board sources to generate a local (pci/x) reset signal. lrsto_ can be asserted either through hardware or software events. the hardware reset events are detailed in figure 30 . this signal can be asserted through software by the following methods: if the sreset bit is set, the tsi148 asse rts srsto output even if it is not the system controller. the srsto signal is asserted for a minimum of 200ms.
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 125 80a3020_ma001_08 ? setting the lreset bit in the vctrl register (see section 10.4.34 on page 255 ). the lreset bit is self clearing. when the lreset bit is set the lrsto_ signal remains asserted for a minimum of 15us. because this bit only resets the board and not the entire system , setting this bit can have side effects. for example, if there are vmebus transfers in progress, local resources required to complete the transfers are reset an d unavailable. this may cause aborted vmebus cycles, vmebus time-outs, or a vmebus lockup. to avoid these side effects, the following rules must be used when setting the lreset bit: 1. the lreset bit must only be used in exceptional cases and not during normal system operation. 2. the software must set vmebus stop ( vs) bit and wait for the vmebus stop acknowledge bit (vsa) to be set (see section 10.4.33 on page 251 ). when the vs bit is set, tsi148 acquires vmebus ownership. this prevents any other vmebus masters from acquiring the vmebus. setting the vs bit also prevents tsi148 from starting any vmebus cycles. this ensures that the vmebus is in an idle state when the lrsto_ signal is as serted. the lreset bit can then be set. ? setting the local reset ( lrst) bit in the gctrl register (see section 10.4.96 on page 360 ). the lrsto_ reset remains asserted as long as the lrst bit is set. ? setting the local reset set (lrsts) bit in the cr/csr bit set (csrbsr) register (see section 10.4.102 on page 368 ). when the bit is set the board is held in reset until a 1 is written to the lrstc bit in the csrbcr register.
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 126 80a3020_ma001_08 5.2.2 reset timing figure 31 shows the power-up reset timing of tsi148. the numbers in the figure correspond to the following values: ? 1 = pll_rst_ hold time (0ns) ? pll_rst_ can be released once the pclk and power are stable ? 2 = purst_ hold time (150us) ? pursti_ must be held after negation of pll_rsti_ to make sure the pll is locked to the pclk frequency ? 3 = assertion of srsto (200ms) ? minimum assertion of srsto output (as required by the american national standard for vme64 ) figure 31: timing for power-up reset v dd p clk v dd2 p ll_rst_ p ursti_ l rsto_ s rsto 1 2 3 p ll_vdd
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 127 80a3020_ma001_08 5.3 clocks tsi148 clocks are derived from the pci/x bus clock. the pci/x bus clock frequency can be 33, 66, 100, or 133 mhz. the pci/x clock frequency and bus mode is configured on the rising edge of lrsti_ (see table 5 ) the pci local bus specification (revision 2.2) does not require the pci bus configuration signals to be valid until 10 clocks before the negation of pci reset, however tsi148 has tighter requirements. tsi148 expects the pci bus configuration signals to be valid when the pci clock starts and remain valid until the lrsti_ si gnal is negated. this allows the internal pll to lock to the pci/x bus clock. the configuration signals are only latched on th e first rising edge of lrsti_. if lrsti_ is asserted at a later time, the configuration signals are not latched again. however, if both pursti_ and lrsti_ are reasserted, then the configuration signal latches are opened and the configuration signals are latched on the rising edge of lrsti_. the configuration signals are only latched once to make sure the pll clock remains stable through a pci/x bus reset. this stability enable s a subset of the vme bus logic to function while the pci/x bus is in reset, including: the vmebus sysclk, vmebus arbiter, vmebus daisy chain signals, vmebus general contro l and status register access, and vmebus control and control and status register accesses. pclk operation below 33 mhz is not recommended. table 5: pci bus configuration pci bus signal pci bus mode pci clock frequency (mhz) frame__ irdy_ devsel_ stop_ trdy_ m66en min max 1 1 1 1 1 0 pci 33.3 33.3 11 1 111pci5066.6 11 1 10xpci-x5066.6 11 1 01xpci-x66.6100 1 1 1 0 0 x pci-x 100 133.3
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 128 80a3020_ma001_08 the pci/x bus clock input provides the reference clock for the internal pll. the pll is used to derive the 16 mhz vmebus sysclk. if the pci/x clock input is below the maximum frequency defined for a specific configuration, the pll frequency is scaled accordingly. when the pll frequency is scaled down the vmebus timing parameters are not violated, but the vmebus performance and timer accuracy is affected. when this situ ation occurs the vmebus sysclk output should not be used. 5.4 power-up options tsi148 samples various vmebus and pci/x bus signals during reset to enable or disable certain functions. 5.4.1 pci/x power-up options the pci/x interface has power-up options that control how the interface is configured for use in a system. 5.4.1.1 bus width the pci/x interface supports 32-bit or 64-bit pci/x bus widths. the pci/x bus width is configured during a pci/x bus reset. if req64_ is high during the rising edge of lrsti_, then the chip is configured for 32-bit pci/x. if req64_ is low during the rising edge of lrsti_, then the chip is configured for 64-b it pci/x. when the chip is used on a 32-bit pci/x bus, req64_ should be pulled high with a weak pull-up resistor. when the tsi148 is used on a 32-bit pci/x bus, it drives cbe[7:4]_, ad[63:32], par64 and ack64_ at all times. these signals may be left unconnected when the chip is used on a 32-bit pci/x bus. when the chip is used on a 64-bit pci/x bus, it must not be configured for 32-bit operation. other pci/x devices may drive their 64 -bit extension signals and this could cause excessive currents in the output drivers.
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 129 80a3020_ma001_08 table 6 on page 129 shows tsi148?s pci/x bus width configurations. 5.4.1.2 frequency the mode and frequency of the pci/x bus is de termined the first time lrsti_ is negated. the m66en, frame_, irdy_, trdy_, stop_ and devsel_ signals are sampled on the rising edge of lrsti_ and the pci/x bus is configured (as defined in the pci-x addendum to pci local bus specification (revision 1.0b) ). for more information, refer to section 5.3 on page 127 . table 6: pci/x bus configuration function register reset sample signal(s) sample state description pci/x bus data width pci/x configuration status register lrsti_ req64_ 0 64-bit pci/x bus 1 32-bit pci/x bus pci/x mode lrsti_ m66en, frame_, irdy_, trdy_, stop_, devsel_ refer to table 5 on page 127 .
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 130 80a3020_ma001_08 5.4.2 vmebus power-up options the tsi148 vmebus interface supports a number of power-up options. power-up options are latched during the assertion of pursti_. during power-up reset tsi148 negates the external transceiver enable (dboe_) signal, which puts the vd[31:0], va[31:1], lword transceivers into a high impedance state. external pull-ups or pull-downs placed between tsi148 and the external transceivers bring these power-up option signals to their proper state while dboe_ is negated. table 7 shows the data signal and the functionality it enables through power-up configuration. table 7: vmebus power-up options description power-up option vmebus data signal control register detailed information sfailen control bit reset value sfailen_rv vd[0] control and status register ? sfailen bit section 5.4.2.4 on page 134 sfailai control bit auto clear sfailai_ac vd[1] vmebus control register ? sfailai bit section 5.4.2.2 on page 132 auto slot id enable asiden vd[2] none - power-up option only table 8 and section 5.4.2.2 on page 132 geographical slot id enable gsiden vd[3] none - power-up option only table 8 and section 5.4.2.3 on page 133
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 131 80a3020_ma001_08 5.4.2.1 asiden and gsiden power-up options assigning the cr/csr base address the data signals and the functionality they enable through power- up configuration are described individually, however the functi ons are not independent. the asiden and gsiden functions define the method for assignin g the cr/csr base address. the interaction of these two functions is shown in table 8 . table 9 defines all combinations of the four vmebus data bits. table 8: asiden and gsiden definition asiden gsiden description 0 0 cr/csr disabled 0 1 geographical address 1 0 auto slot id 1 1 geographical address defaults to auto slot id if ga[4:0] pins are all high table 9: cr/csr base address configuration vd[3:0] ga (all high) description 00x0 x cr/csr disabled crat register, en cleared by s reset vctrl register, sfailai cleared by s reset gctrl register, sfailen cleared by s reset 00x1 x cr/csr disabled crat.en cleared by s reset vctrl.sfailai cleared by s reset gctrl.sfailen set by s reset 0100 x auto slot id crat register, en cleared by s reset vctrl register, sfailai set by s reset gctrl register, sfailen cleared by s reset 01x1 x illegal configuration 0110 x auto slot id crat register, en cleared by s reset vctrl register, sfailai set by s reset, cleared 1 ms after s reset gctrl register, sfailen cleared by s reset
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 132 80a3020_ma001_08 5.4.2.2 auto slot id operation tsi148 has auto slot id functi onality which is described in the american national standard for vme64 . when the auto slot id functiona lity is enabled in a system, after system reset each board in the system generates an interrupt on level irq2_. a level two interrupt handler module, called the monarch , performs interrupt acknowledge cycles in response to each interrupt request. before the monarch can respond with its interrupt acknowledge cycle all boards in the system must have sysfail_ negated. once sysfail_ is negated, the monarch performs the interrupt service routine. each vmebus sl ave responds with an initial cr/csr address space of zero. the monarch then configures the cr/csr base address of each board through its cr/csr base address register. 10x0 x geographical addressing crat register, en set by s reset vctrl register, sfailai cleared by s reset gctrl register, sfailen cleared by s reset 10x1 x geographical addressing crat register, en set by s reset vctrl register, sfailai cleared by s reset gctrl register, sfailen set by s reset 11x0 0 geographical addressing crat register, en set by s reset vctrl register, sfailai cleared by s reset gctrl register, sfailen cleared by s reset 11x1 x illegal configuration 1100 1 default to auto slot id crat register, en cleared by s reset vctrl register, sfailai set by s reset gctrl register, sfailen cleared by s reset 1110 1 default to auto slot id crat register, en cleared by s reset vctrl register, sfailai set by s reset, cleared 1 ms after s reset gctrl register, sfailen cleared by s reset table 9: cr/csr base address configuration vd[3:0] ga (all high) description
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 133 80a3020_ma001_08 auto slot id enable the auto slot id enable (asiden) feature is controlled through a power-up option. the asiden feature allows the cr/csr base addres s to be configured using the auto slot id protocol. asiden can be enabled through a power-up option (shown in table 7 on page 130 ). the power-up option is sampled at the rising edge of the pursti_ signal. system failure auto slot id (sfailai) configuration the system failure auto slot id (sfailai) bit is used when the auto slot id protocol is enabled in the system to assign the cr/csr ba se address. the initial value of the sfailai bit can be configured at power-up reset through the sfailai_ac power-up option or a value can be programmed by software in the sfailai bit in the vmebus control register (vctrl) (see section 10.4.34 on page 255 ). when auto slot id is used to assign the cr/csr base address, the sfailai bit is set by the assertion of the srsti_ signal. the sfailai bit must be cleared in order for tsi148?s system fail output (sfailo) signal to be negated. sfailo is automatically negated if the sfailai_ac power-up option is selected, othe rwise sfailo is negated when software clears the sfailai bit in the vctrl register. this feature can be enabled through the sfailai_ac power-up option as shown in table 7 on page 130 . the power-up option is sampled at the rising edge of the pursti_ signal. 5.4.2.3 geographic slot id enable the geographic slot id enable function initiali zes the cr/csr base address register using the vmebus ga signals. the geographic slot id enable feature allows a board to come out of reset with the cr/csr registers visible from the vmebus and the base address of the cr/csr is determined by the vmebus ga signals. the initial value of the cr/csr enable bit in the cr/csr attribute (crat) register and cbar bits in the cr/csr base address (cbar) register can be configured at power-up reset using the geographic slot id enable function (see table 7 on page 130 ). if the vd[3] signal is zero at the rising edge of the pursti _ signal, the cr/csr enable bit and cbar bits are cleared. if the vd[3] signal is one at the rising edge of the pursti_ signal, the cr/csr enable bit is set and the cbar bits 7 to 3 are set to the inverted value of the vmebus geographic address signals. when the srsti_ si gnal is asserted, the cr/csr en bit and the cbar bits are loaded with th e power-up option reset values.
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 134 80a3020_ma001_08 5.4.2.4 system fail enable (sfailen) configuration the tsi148 system failure enable (sfailen) bit controls the assertion of the tsi148 system fail output (sfailo) signal. the only exception to this is when the auto slot id method of assigning the cr/csr base address is being implemented (as described in section 5.4.3 on page 135 ). the initial value of the sfailen bit can be configured at power-up reset through the sfailen_rv power-up option. additionally, a value can be programmed by software in the control and status register. the board fail (bdfail_) signal, along with the sfailen bit, determine if the tsi148 generates the sfailo signal, in all cases except for the case where the auto slot id method is being implemented. the board fail signal (bdfail_) can be generated either through software, by writing to the board fail bit (brdfl) in the vmebus sataus register (see section 10.4.35 on page 259 ), or by external logic on the board. the sfailo signal is controlled through the following registers: ? gcsr control and status register ? the sfailo signal can be enabled or disabled through the sfailen bit ? cr/csr bit clear register ? the sfailo signal can be disabled through the sfailc bit ? cr/csr bit set register ? the sfailo signal can be enabled through the sfails bit an access to any one of these three registers is transparent to the other registers. for example if the system failure enable is enabled through writing a 1 to the sfails bit in the cr/csr register, the sfailen bit in the gcsr is also set. this feature can be enabled through the sfailen_rv power-up option as shown in table 7 on page 130 . the power-up option is sampled at the rising edge of the pursti_ signal. the sfailen_rv power-up option must be cleared when using the auto slot id (asiden) power-up option to configure the cr/csr base address register. software must not set the sfailen bit unti l the auto slot id process is complete.
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 135 80a3020_ma001_08 5.4.3 system controller (scon) tsi148 has vmebus system controller (scon) functionality. the sconen_ and scondis_ signals are used to control the scon function. if the sconen_ signal is low and the scondis_ signal is high at the rising edge of pusrti_, the scon function is enabled. if the sconen_ signal is high and the scondis_ signal is low at the rising edge of pursti_, the scon function is disabled. if the sconen_ signal and the scondis_ signal are both high at the rising edge of pusrti_, the auto system controller feature is used. the auto system controller feature uses the bg3i n_ signal to enable a board to determine if it is in vmebus slot 1. if the board is in vm ebus slot 1, the bg3in_ signal is low and the scon function is enabled. if the board is not in vmebus slot 1, the bg3in_ signal is high and the scon function is disabled. tip the american national standard for vme64 extensions defines the auto system controller feature. table 10: vmebus system controller configuration function register reset sample signal(s) sample state description scon vmebus status register pursti_ sconen_ scondis_ 0 1 scon enabled sconen_ scondis_ 1 0 scon disabled sconen_ scondis_ vbg3in_ 1 1 0 auto system controller scon enabled sconen_ scondis_ vbg3in_ 1 1 1 auto system controller scon disabled
5. resets, clocks, and power-up options tsi148 pci/x-to-vme bus bridge user manual 136 80a3020_ma001_08
tsi148 pci/x-to-vme bus bridge user manual 137 80a3020_ma001_08 6. interrupt controller an interrupt is a process by which a program is informed that an event has occurred in the system (for example, an interrupt signal is asserted to indicate an error). when a program receives an interrupt, it temporarily suspends normal processing and diverts the execution of instructions to a sub-routine handled by an interrupt controller. the controller communicates with the host processor and the device that initi ated the interrupt to determine how to handle the interrupt. interrupt events originate from a variety of sources; however, they can be classified as one of two types: hardware and software interrupts. interrupts generated by devices (for example, a printer) indicate an event has occurred and ar e called hardware interrupts. interrupt events generated by software programs are called software interrupts. this chapter discusses the following topi cs about the tsi148 interrupt features: ? ?overview of the interrupt controller? on page 138 ? ?vmebus interrupter? on page 138 ? ?local interrupter? on page 138 ? ?vmebus interrupt handler? on page 139
6. interrupt controller tsi148 pci/x-to-vme bus bridge user manual 138 80a3020_ma001_08 6.1 overview of the interrupt controller tsi148 can be programmed to act as interrupter and an interrupt handler in a vme system. as an interrupter, tsi148 is capable of asserting interrupts on irq[7:1]. as an interrupt handler, tsi148 has seven vmebus interrupt acknowledge registers which, when read, generate an iack cycle on the vmebus (see section 10.4.69 on page 308 ). 6.2 vmebus interrupter tsi148 has a vmebus interrupter which enables software to generate vmebus interrupts. the interrupter operates in release-on-acknowledge (roak) mode. an 8-bit status/id is provided upon receiving the iack cycle. the following steps illustrate how a vmebus interrupt is generated: 1. the status/id and irql fields must be set in the vmebus interrupt control (vicr) register. the irql field defines the level of vmebus interrupt output signals (irq[7:1]o). a vmebus interrupt is genera ted when the irql field is written. the interrupter asserts the requested interrupt onto the vmebus and sets the vmebus irq status ( irqs) bit in the vmebus interrupt control (vicr) register (see section 10.4.69 on page 308 ). 2. once the interrupt is acknowledged the irqs bit is cleared and the interrupt can be sent to the local bus interrupter (if enabled). 6.3 local interrupter tsi148?s local interrupter provides a mechanism to control the interrupts generated by internal and external sources. the local interrupter rece ives interrupts from internal and external sources and routes them to one of four interrupt output lines (inta_, intb_, intc_, intd_). there are the following internal and external sources of interrupts: ? vmebus irq[7:1]i_ ?acfaili_ ? sfaili_ ? vmebus error only one interrupt at a time can be generated.
6. interrupt controller tsi148 pci/x-to-vme bus bridge user manual 139 80a3020_ma001_08 ? dma controllers ? vmebus interrupter acknowledged ? vmebus edge (broadcast inte rrupt, clock and 64-bit counter) ? pci error ? mailbox[3:0] ? location monitor [3:0] each interrupt source has an enable bit, status bit, interrupt out enable bit, and two map bits. the edge sensitive interrupts also have a clear bit. these bits can be programmed in the tsi148 interrupt registers (see section 10.4.69 on page 308 ). 6.4 vmebus interrupt handler tsi148 has seven vmebus interrupt acknowledge registers which generate an iack cycle on the vmebus when they are read. there is one iack register for each of the vmebus irq[7:1] signals. these features can be programmed in the vmebus interrupt control registers (see section 10.4.69 on page 308 ). the interrupt handler has the following features: ? supports 8, 16, and 32-bit iack cycles ? a word read of the iack registers causes a 32-bit iack cycle on the vmebus ? a half-word read causes a 16-bit iack cycle on the vmebus ? a byte read causes an 8-bit iack cycle on the vmebus ? once the iack cycle is generated th e interrupter supplies its status/id. the tsi148 expects the interrupt handli ng intelligence to exist on the local (pci/x) bus. the tsi148 does not have the ability to route local interrupt outputs (inta_, intb_, intc_, intd_) to vmebus interrupt outputs (irq[7:1])
6. interrupt controller tsi148 pci/x-to-vme bus bridge user manual 140 80a3020_ma001_08
tsi148 pci/x-to-vme bus bridge user manual 141 80a3020_ma001_08 7. jtag module the joint test action group (jtag) created the boundary-scan testing standard (documented in the ieee 1149.1 standard ) for testing printed circuit boards (pcbs). the boundary-scan approach involves designing boundary-scan circuitry into the integrated circuit. pcbs populated with 1149.1 compliant devices can be tested for connectivity, correct device orientation, correct device loca tion, and device identification. all the pins on compliant devices can be cont rolled and observed using (typically) five pins that are routed to the board edge connector. board designers can develop a standard test for all 1149.1 compliant devices regardless of devi ce manufacturer, package type, technology, or device speed. this chapter discusses the following topics about tsi148?s jtag features: ? ?overview of jtag? on page 142 ? ?instructions? on page 142
7. jtag module tsi148 pci/x-to-vme bus bridge user manual 142 80a3020_ma001_08 7.1 overview of jtag tsi148 has a dedicated user-accessible jtag (j oint test action group) module that is fully compatible with the ieee 1149.1 standard test access port and boundary-scan architecture . the jtag logic includes a test access port (tap ) consisting of five dedicated signals (tck, trst_, tms, tdi, tdo), a tap controller, inst ruction register, bypass register, other test data registers (for example, device identity re gister, etc.), and boundary-scan register (see figure 32 ). figure 32: jtag functional diagram 7.2 instructions tsi148?s ieee 1149.1 implementation includes the following instructions: ? extest: this instruction drives the data loaded into the boundary scan register through the output pin to drive another chip with the value loaded in the boundary scan cell by the sample/preload instruction. at the same time, this instruction also captures the data at the inputs. this process is useful for board interconnect testing. boundary scan cell tdi tms tck tdo test access port (tap) boundary scan path trst_ multiplexer multiplexer other te s t d a ta registers bypass register instruction register tap controller
7. jtag module tsi148 pci/x-to-vme bus bridge user manual 143 80a3020_ma001_08 ? sample/preload: this instruction loads th e boundary scan chain with proper values before driving it to another chip us ing the extest or intest instruction. ? idcode: this instruction configures a 32-b it identification register between the tdi and tdo pins. the instruction selects the id re gister and shifts out the identity of the manufacturer, the version, and device identification number. the value of the identification register for revision 1 is 0x xxxxxxxx . ? bypass: this instruction places a one-bit re gister between the tdi and tdo pins. this provides a short path through the device for shifting data from one chip to another without going through the boundary scan chain. ? highz: this instruction is the same as by pass except that all the bidirect and 3-state outputs are 3-stated when this instruction is active. the boundary scan cell cannot be updated with a new value during this instruction.
7. jtag module tsi148 pci/x-to-vme bus bridge user manual 144 80a3020_ma001_08
tsi148 pci/x-to-vme bus bridge user manual 145 80a3020_ma001_08 8. signals and pins this chapter discusses the following topics about tsi148?s signals: ? ?overview of signals? on page 145 ? ?signal summary? on page 147 ? ?detailed signal descriptions? on page 160 ? ?pinout? on page 171 8.1 overview of signals the tsi148 is a 456-pin device. the following sections explain tsi148?s signal groups and characteristics.
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 146 80a3020_ma001_08 8.2 signal grouping the signal grouping is shown in figure 33 . figure 33: signal grouping tsi148 64 1 72 32 5 1 i nterrupts ground vmebus 1 1 1 1 jtag 1 1 1 1 4 pci/x vd[31:0] iack_ am[5:0] va[31:1] lword_ aso_ asi_ write_ ds1i_ ds0o_ ds0i_ ds1o_ retryi_ dtacko_ dtacki_ retryo_ br[3:0]i_ berro_ berri_ br[3:0]o bg[3:0]inout_ bg[3:0]out_ iackin_ iackout_ irq[7:1]i_ irq[7:1]o bbsyi_ bbsyo bclro_ 6 1 1 1 1 1 1 31 1 1 1 1 1 1 1 1 1 4 4 4 4 1 1 1 1 1 7 7 1 1 1 1 srsti_ srsto sfaili_ sfailo acfaili_ amout dbout adbout asoe dsoe dtackoe irdy_ stop_ devsel_ idsel req64_ serr_ par64 cbe[7:0]_ frame_ trdy_ ad[63:0] perr_ ack64_ par req_ gnt_ 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 lrsti_ lrsto_ lsrsti_ pursti_ pclk 1 1 1 1 1 1 1 tck tms trst_ tdi tdo vdd2 inta_- intd_ pll_vss pll_vdd power/ 1 ga[4:0]_ gap_ sconen_ scondis_ scon 1 1 1 1 retryoe 1 berroe dboe_ bclri_ 1 1 1 bdfail_ 1 1 vdd 32 sysclk 1 bg[3:0]in_ 4 m66en 1 vss 72 pll_tune[9:0] ce0_test pll_outa 10 1 1 hwc_pfu pcimc tm_in tm_out misc. 1 1 1 1 pll_ten pcipuen clocks/ resets pll_rsti_ 1
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 147 80a3020_ma001_08 8.3 signal summary the following tables describe the terminology used in table 11 on page 147 . table 11 shows the i/o type conventions used for signal descriptions. table 12 shows the i/o level conventions used for signal descriptions. this specifies the dc electrical characteristics of the signal. refer to section 9 on page 185 for information on tsi148 ?s electrical specification. table 11: signal conventions - i/o type symbol type input input only output output only, totem pole output (t/s) output only, tri-state output (o/d) output only, open-drain bidirect bidirectional, tri-state bidirect (o/d) bidirectional, open-drain table 12: signal conventions - i/o level symbol type 3.3v ttl 3.3v i/o cell, ttl compliant 5vtlr ttl 3.3v i/o cell, ttl compliant, 5v tolerant 3.3v pci/x pci/pci-x compliant 1.8v 1.8v i/o cell
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 148 80a3020_ma001_08 table 13 describes the current capabilities (driver impedance) of the i/o cell. for information on tsi148?s electrical specification, refer to section 9 on page 185 . a signal list summary is shown in table 14 . table 13: signal conventions - i/o drive symbol type 35 ohm nominal impedance 35 ohms 65 ohm nominal impedance 65 ohms pci/x for a 3.3v pci/x i/o cell, the driver impedance for a point-to-point application is 40 ohms. for a 3.3v pci/x i/o cell, the driver impedance for a multi-point application is 20 ohms. driver impedance is controlled by the pcimc signal. table 14: pin list signal function i/o type i/o level i/o drive pin ad0 pci address/data bus [0] bidirect 3.3vttl pci-x ad19 ad1 pci address/data bus [1] bidirect 3.3vttl pci-x ae18 ad2 pci address/data bus [2] bidirect 3.3vttl pci-x af19 ad3 pci address/data bus [3] bidirect 3.3vttl pci-x ad18 ad4 pci address/data bus [4] bidirect 3.3vttl pci-x ae17 ad5 pci address/data bus [5] bidirect 3.3vttl pci-x af18 ad6 pci address/data bus [6] bidirect 3.3vttl pci-x ad17 ad7 pci address/data bus [7] bidirect 3.3vttl pci-x ae16 ad8 pci address/data bus [8] bidirect 3.3vttl pci-x ad16 ad9 pci address/data bus [9] bidirect 3.3vttl pci-x ae15 ad10 pci address/data bus [10] bidirect 3.3vttl pci-x ad15 ad11 pci address/data bus [11] bidirect 3.3vttl pci-x ae14 ad12 pci address/data bus [12] bidirect 3.3vttl pci-x af15 ad13 pci address/data bus [13] bidirect 3.3vttl pci-x af14
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 149 80a3020_ma001_08 ad14 pci address/data bus [14] bidirect 3.3vttl pci-x ad13 ad15 pci address/data bus [15] bidirect 3.3vttl pci-x ad14 ad16 pci address/data bus [16] bidirect 3.3vttl pci-x af13 ad17 pci address/data bus [17] bidirect 3.3vttl pci-x ae13 ad18 pci address/data bus [18] bidirect 3.3vttl pci-x ad12 ad19 pci address/data bus [19] bidirect 3.3vttl pci-x ae12 ad20 pci address/data bus [20] bidirect 3.3vttl pci-x ad11 ad21 pci address/data bus [21] bidirect 3.3vttl pci-x af10 ad22 pci address/data bus [22] bidirect 3.3vttl pci-x ae11 ad23 pci address/data bus [23] bidirect 3.3vttl pci-x ad10 ad24 pci address/data bus [24] bidirect 3.3vttl pci-x af9 ad25 pci address/data bus [25] bidirect 3.3vttl pci-x ad9 ad26 pci address/data bus [26] bidirect 3.3vttl pci-x af8 ad27 pci address/data bus [27] bidirect 3.3vttl pci-x ae9 ad28 pci address/data bus [28] bidirect 3.3vttl pci-x ad8 ad29 pci address/data bus [29] bidirect 3.3vttl pci-x af7 ad30 pci address/data bus [30] bidirect 3.3vttl pci-x ae8 ad31 pci address/data bus [31] bidirect 3.3vttl pci-x ad7 ad32 pci address/data bus [32] bidirect 3.3vttl pci-x y1 ad33 pci address/data bus [33] bidirect 3.3vttl pci-x w3 ad34 pci address/data bus [34] bidirect 3.3vttl pci-x v2 ad35 pci address/data bus [35] bidirect 3.3vttl pci-x w1 ad36 pci address/data bus [36] bidirect 3.3vttl pci-x v3 ad37 pci address/data bus [37] bidirect 3.3vttl pci-x u2 ad38 pci address/data bus [38] bidirect 3.3vttl pci-x v1 ad39 pci address/data bus [39] bidirect 3.3vttl pci-x u3 table 14: pin list signal function i/o type i/o level i/o drive pin
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 150 80a3020_ma001_08 ad40 pci address/data bus [40] bidirect 3.3vttl pci-x t2 ad41 pci address/data bus [41] bidirect 3.3vttl pci-x t3 ad42 pci address/data bus [42] bidirect 3.3vttl pci-x r2 ad43 pci address/data bus [43] bidirect 3.3vttl pci-x r3 ad44 pci address/data bus [44] bidirect 3.3vttl pci-x p2 ad45 pci address/data bus [45] bidirect 3.3vttl pci-x r1 ad46 pci address/data bus [46] bidirect 3.3vttl pci-x p1 ad47 pci address/data bus [47] bidirect 3.3vttl pci-x n3 ad48 pci address/data bus [48] bidirect 3.3vttl pci-x p3 ad49 pci address/data bus [49] bidirect 3.3vttl pci-x n1 ad50 pci address/data bus [50] bidirect 3.3vttl pci-x n2 ad51 pci address/data bus [51] bidirect 3.3vttl pci-x m3 ad52 pci address/data bus [52] bidirect 3.3vttl pci-x m2 ad53 pci address/data bus [53] bidirect 3.3vttl pci-x l3 ad54 pci address/data bus [54] bidirect 3.3vttl pci-x k1 ad55 pci address/data bus [55] bidirect 3.3vttl pci-x l2 ad56 pci address/data bus [56] bidirect 3.3vttl pci-x k3 ad57 pci address/data bus [57] bidirect 3.3vttl pci-x j1 ad58 pci address/data bus [58] bidirect 3.3vttl pci-x j3 ad59 pci address/data bus [59] bidirect 3.3vttl pci-x h1 ad60 pci address/data bus [60] bidirect 3.3vttl pci-x j2 ad61 pci address/data bus [61] bidirect 3.3vttl pci-x h3 ad62 pci address/data bus [62] bidirect 3.3vttl pci-x g1 ad63 pci address/data bus [63] bidirect 3.3vttl pci-x h2 cbe0_ pci command/byte enable [0] bidirect 3.3vttl pci-x af5 cbe1_ pci command/byte enable [1] bidirect 3.3vttl pci-x ad6 table 14: pin list signal function i/o type i/o level i/o drive pin
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 151 80a3020_ma001_08 cbe2_ pci command/byte enable [2] bidirect 3.3vttl pci-x ae6 cbe3_ pci command/byte enable [3] bidirect 3.3vttl pci-x af4 cbe4_ pci command/byte enable [4] bidirect 3.3vttl pci-x aa3 cbe5_ pci command/byte enable [5] bidirect 3.3vttl pci-x ab1 cbe6_ pci command/byte enable [6] bidirect 3.3vttl pci-x y2 cbe7_ pci command/byte enable [7] bidirect 3.3vttl pci-x y3 frame_ pci cycle frame bidirect 3.3vttl pci-x ae3 irdy_ pci initiator ready bidirect 3.3vttl pci-x ad5 trdy_ pci target ready bidirect 3.3vttl pci-x af3 stop_ pci stop bidirect 3.3vttl pci-x ae4 devsel_ pci device select bidirect 3.3vttl pci-x af2 idsel pci initialization device select input 3.3vttl pci-x ae5 req64_ pci 64-bit transfer request bidirect 3.3vttl pci-x ac1 ack64_ pci 64-bit transfer acknowledge bidirect 3.3vttl pci-x aa2 req_ pci bus request out(ts) 3.3vttl pci-x ad2 gnt_ pci bus grant input 3.3vttl pci-x ab3 par pci bus parity bidirect 3.3vttl pci-x ae7 par64 pci bus parity bidirect 3.3vttl pci-x w2 perr_ pci data parity error bidirect 3.3vttl pci-x ab2 serr_ pci system error out(od) 3.3vttl pci-x ac2 m66en pci frequency capability select input 3.3vttl pci-x ad1 pclk pci clock input 3.3vttl pci-x d7 inta_ pci interrupt a out(o/d) 3.3vttl 35ohm f3 intb_ pci interrupt b out(o/d) 3.3vttl 35ohm e1 intc_ pci interrupt c out(o/d) 3.3vttl 35ohm g2 intd_ pci interrupt d out(o/d) 3.3vttl 35ohm g3 table 14: pin list signal function i/o type i/o level i/o drive pin
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 152 80a3020_ma001_08 lrsto_ local bus reset out output 3.3vttl 65ohm w25 lrsti_ local bus reset in input 3.3vttl w23 lsrsti_ local sysrst in input 3.3vttl y26 pursti_ power-up reset in input 3.3vttl w24 bdfail_ board fail bi(o/d) 3.3vttl 65ohm y24 va1 vmebus address bus [1] bidirect 3.3vttl 35ohm k24 va2 vmebus address bus [2] bidirect 3.3vttl 35ohm l25 va3 vmebus address bus [3] bidirect 3.3vttl 35ohm k26 va4 vmebus address bus [4] bidirect 3.3vttl 35ohm l23 va5 vmebus address bus [5] bidirect 3.3vttl 35ohm l24 va6 vmebus address bus [6] bidirect 3.3vttl 35ohm m25 va7 vmebus address bus [7] bidirect 3.3vttl 35ohm n23 va8 vmebus address bus [8] bidirect 3.3vttl 35ohm m24 va9 vmebus address bus [9] bidirect 3.3vttl 35ohm m23 va10 vmebus address bus [10] bidirect 3.3vttl 35ohm n25 va11 vmebus address bus [11] bidirect 3.3vttl 35ohm m26 va12 vmebus address bus [12] bidirect 3.3vttl 35ohm n26 va13 vmebus address bus [13] bidirect 3.3vttl 35ohm p24 va14 vmebus address bus [14] bidirect 3.3vttl 35ohm n24 va15 vmebus address bus [15] bidirect 3.3vttl 35ohm p26 va16 vmebus address bus [16] bidirect 3.3vttl 35ohm r26 va17 vmebus address bus [17] bidirect 3.3vttl 35ohm p25 va18 vmebus address bus [18] bidirect 3.3vttl 35ohm r24 va19 vmebus address bus [19] bidirect 3.3vttl 35ohm r23 table 14: pin list signal function i/o type i/o level i/o drive pin
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 153 80a3020_ma001_08 va20 vmebus address bus [20] bidirect 3.3vttl 35ohm p23 va21 vmebus address bus [21] bidirect 3.3vttl 35ohm r25 va22 vmebus address bus [22] bidirect 3.3vttl 35ohm t24 va23 vmebus address bus [23] bidirect 3.3vttl 35ohm t23 va24 vmebus address bus [24] bidirect 3.3vttl 35ohm u26 va25 vmebus address bus [25] bidirect 3.3vttl 35ohm t25 va26 vmebus address bus [26] bidirect 3.3vttl 35ohm u24 va27 vmebus address bus [27] bidirect 3.3vttl 35ohm v26 va28 vmebus address bus [28] bidirect 3.3vttl 35ohm u23 va29 vmebus address bus [29] bidirect 3.3vttl 35ohm u25 va30 vmebus address bus [30] bidirect 3.3vttl 35ohm v24 va31 vmebus address bus [31] bidirect 3.3vttl 35ohm w26 vd0 vmebus data bus [0] bidirect 3.3vttl 35ohm d6 vd1 vmebus data bus [1] bidirect 3.3vttl 35ohm a4 vd2 vmebus data bus [2] bidirect 3.3vttl 35ohm b6 vd3 vmebus data bus [3] bidirect 3.3vttl 35ohm b7 vd4 vmebus data bus [4] bidirect 3.3vttl 35ohm c7 vd5 vmebus data bus [5] bidirect 3.3vttl 35ohm d8 vd6 vmebus data bus [6] bidirect 3.3vttl 35ohm d9 vd7 vmebus data bus [7] bidirect 3.3vttl 35ohm b9 vd8 vmebus data bus [8] bidirect 3.3vttl 35ohm a8 vd9 vmebus data bus [9] bidirect 3.3vttl 35ohm c9 vd10 vmebus data bus [10] bidirect 3.3vttl 35ohm b10 vd11 vmebus data bus [11] bidirect 3.3vttl 35ohm b11 vd12 vmebus data bus [12] bidirect 3.3vttl 35ohm a10 vd13 vmebus data bus [13] bidirect 3.3vttl 35ohm d11 table 14: pin list signal function i/o type i/o level i/o drive pin
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 154 80a3020_ma001_08 vd14 vmebus data bus [14] bidirect 3.3vttl 35ohm c11 vd15 vmebus data bus [15] bidirect 3.3vttl 35ohm b12 vd16 vmebus data bus [16] bidirect 3.3vttl 35ohm d13 vd17 vmebus data bus [17] bidirect 3.3vttl 35ohm c12 vd18 vmebus data bus [18] bidirect 3.3vttl 35ohm d12 vd19 vmebus data bus [19] bidirect 3.3vttl 35ohm b13 vd20 vmebus data bus [20] bidirect 3.3vttl 35ohm a12 vd21 vmebus data bus [21] bidirect 3.3vttl 35ohm a13 vd22 vmebus data bus [22] bidirect 3.3vttl 35ohm c14 vd23 vmebus data bus [23] bidirect 3.3vttl 35ohm c13 vd24 vmebus data bus [24] bidirect 3.3vttl 35ohm a14 vd25 vmebus data bus [25] bidirect 3.3vttl 35ohm a15 vd26 vmebus data bus [26] bidirect 3.3vttl 35ohm b14 vd27 vmebus data bus [27] bidirect 3.3vttl 35ohm c15 vd28 vmebus data bus [28] bidirect 3.3vttl 35ohm d15 vd29 vmebus data bus [29] bidirect 3.3vttl 35ohm d14 vd30 vmebus data bus [30] bidirect 3.3vttl 35ohm b15 vd31 vmebus data bus [31] bidirect 3.3vttl 35ohm c16 am0 vmebus am bus [0] bidirect 3.3vttl 35ohm h24 am1 vmebus am bus [1] bidirect 3.3vttl 35ohm j23 am2 vmebus am bus [2] bidirect 3.3vttl 35ohm j25 am3 vmebus am bus [3] bidirect 3.3vttl 35ohm h26 am4 vmebus am bus [4] bidirect 3.3vttl 35ohm j24 am5 vmebus am bus [5] bidirect 3.3vttl 35ohm k25 iack_ vmebus interrupt acknowledge bidirect 3.3vttl 35ohm g26 write_ vmebus write bidirect 3.3vttl 35ohm k23 table 14: pin list signal function i/o type i/o level i/o drive pin
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 155 80a3020_ma001_08 lword_ vmebus long word bidirect 3.3vttl 35ohm j26 asi_ vmebus address strobe in input 3.3vttl g23 aso_ vmebus address strobe out output 3.3vttl 35ohm f24 ds0i_ vmebus data strobe 0 in input 3.3vttl e25 ds0o_ vmebus data strobe 0 out output 3.3vttl 35ohm d25 ds1i_ vmebus data strobe 1 in input 3.3vttl d26 ds1o_ vmebus data strobe 1 out output 3.3vttl 35ohm f23 dtacki_ vmebus data acknowledge in input 3.3vttl e23 dtacko_ vmebus data acknowledge out output 3.3vttl 35ohm d24 retryi_ vmebus retry in input 3.3vttl h25 retryo_ vmebus retry out output 3.3vttl 35ohm h23 berri_ vmebus bus error in input 3.3vttl c22 berro_ vmebus bus error out output 3.3vttl 35ohm a24 br0i_ vmebus bus request 0 in input 5vtlrnt d20 br0o vmebus bus request 0 out output 3.3vttl 35ohm b20 br1i_ vmebus bus request 1 in input 5vtlrnt c21 br1o vmebus bus request 1 out output 3.3vttl 35ohm a22 br2i_ vmebus bus request 2 in input 5vtlrnt a23 br2o vmebus bus request 2 out output 3.3vttl 35ohm b21 br3i_ vmebus bus request 3 in input 5vtlrnt b22 br3o vmebus bus request 3 out output 3.3vttl 35ohm d21 bg0in_ vmebus bus grant 0 in input 5vtlrnt b17 bg1in_ vmebus bus grant 1 in input 5vtlrnt b18 bg2in_ vmebus bus grant 2 in input 5vtlrnt a20 bg3in_ vmebus bus grant 3 in input 5vtlrnt c20 bg0inout_ vmebus bus grant 0 inout out(t/s) 5vtlrnt 35ohm d17 table 14: pin list signal function i/o type i/o level i/o drive pin
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 156 80a3020_ma001_08 bg1inout_ vmebus bus grant 1 inout out(t/s) 5vtlrnt 35ohm a19 bg2inout_ vmebus bus grant 2 inout out(t/s) 5vtlrnt 35ohm c19 bg3inout_ vmebus bus grant 3 inout out(t/s) 5vtlrnt 35ohm d19 bg0out_ vmebus bus grant 0 out output 5vtlrnt 35ohm a18 bg1out_ vmebus bus grant 1 out output 5vtlrnt 35ohm c18 bg2out_ vmebus bus grant 2 out output 5vtlrnt 35ohm d18 bg3out_ vmebus bus grant 3 out output 5vtlrnt 35ohm b19 bbsyi_ vmebus bus busy in input 3.3vttl a17 bbsyo vmebus bus busy out output 3.3vttl 35ohm d16 bclri_ vmebus bus clear in input 3.3vttl c17 bclro_ vmebus bus clear out output 3.3vttl 35ohm b16 iackin_ vmebus interrupt acknowledge in input 5vtlrnt g25 iackout_ vmebus interrupt acknowledge out output 5vtlrnt 35ohm e26 irq1i_ vmebus interrupt request 1 in input 5vtlrnt aa25 irq1o vmebus interrupt request 1 out output 3.3vttl 65ohm ac26 irq2i_ vmebus interrupt request 2 in input 5vtlrnt ac25 irq2o vmebus interrupt request 2 out output 3.3vttl 65ohm aa23 irq3i_ vmebus interrupt request 3 in input 5vtlrnt ab24 irq3o vmebus interrupt request 3 out output 3.3vttl 65ohm ad26 irq4i_ vmebus interrupt request 4 in input 5vtlrnt ad25 irq4o vmebus interrupt request 4 out output 3.3vttl 65ohm ac24 irq5i_ vmebus interrupt request 5 in input 5vtlrnt ad23 irq5o vmebus interrupt request 5 out output 3.3vttl 65ohm ad22 irq6i_ vmebus interrupt request 6 in input 5vtlrnt ae23 irq6o vmebus interrupt request 6 out output 3.3vttl 65ohm af24 irq7i_ vmebus interrupt request 7 in input 5vtlrnt ae21 table 14: pin list signal function i/o type i/o level i/o drive pin
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 157 80a3020_ma001_08 irq7o vmebus interrupt request 7 out output 3.3vttl 65ohm af23 srsti_ vmebus system reset in input 5vtlrnt ab26 srsto vmebus system reset out output 3.3vttl 65ohm y25 sfaili_ vmebus system fail in input 5vtlrnt aa24 sfailo vmebus system fail out output 3.3vttl 65ohm y23 acfaili_ vmebus ac fail in input 5vtlrnt v23 ga0_ geographic address [0] input 3.3vttl af22 ga1_ geographic address [1] input 3.3vttl ae20 ga2_ geographic address [2] input 3.3vttl ad20 ga3_ geographic address [3] input 3.3vttl ae19 ga4_ geographic address [4] input 3.3vttl af20 gap_ geographic address parity input 3.3vttl ad21 sysclk vmebus system clock output 3.3vttl 35ohm e24 amout vmebus address bus out output 3.3vttl 35ohm b24 dbout vmebus data bus out output 3.3vttl 35ohm d22 adbout vmebus a/d bus out output 3.3vttl 35ohm a25 dboe_ vmebus data bus oe output 3.3vttl 35ohm c23 asoe vmebus address strobe oe output 3.3vttl 35ohm f25 dsoe vmebus data strobe oe output 3.3vttl 35ohm c26 dtackoe vmebus data acknowledge oe output 3.3vttl 35ohm c25 berroe vmebus bus error oe output 3.3vttl 35ohm b23 retryoe vmebus retry oe output 3.3vttl 35ohm g24 sconen_ system controller enable input 3.3vttl e3 scondis_ system controller disable input 3.3vttl c2 scon system controller output 3.3vttl 65ohm b1 table 14: pin list signal function i/o type i/o level i/o drive pin
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 158 80a3020_ma001_08 tck jtag clock input 3.3vttl d2 tms jtag mode select input 3.3vttl e2 tdi jtag data in input 3.3vttl c1 tdo jtag data out output 3.3vttl 65ohm f2 trst_ jtag reset input 3.3vttl d1 ceo_test factory test note: this signal is used during factory test and should be pulled low. input 1.8v ae22 pcimc pci driver mode control input 3.3vttl ab25 hwc_pfu float pci upper signals input 3.3vttl ad4 pcipuen pci pullup enable input 3.3vttl ac3 pll_ten enable pll tune input 3.3vttl b5 tm_in temperature monitor in ab23 tm_out temperature monitor out ae26 pll_rsti_ pll reset in input 3.3vttl d5 pll_tune0 pll tune 0 input 3.3vttl c10 pll_tune1 pll tune 1 input 3.3vttl d10 pll_tune2 pll tune 2 input 3.3vttl c8 pll_tune3 pll tune 3 input 3.3vttl b8 pll_tune4 pll tune 4 input 3.3vttl a5 pll_tune5 pll tune 5 input 3.3vttl c6 pll_tune6 pll tune 6 input 3.3vttl b4 pll_tune7 pll tune 7 input 3.3vttl a3 pll_tune8 pll tune 8 input 3.3vttl c4 pll_tune9 pll tune 9 input 3.3vttl b3 pll_outa pll output output 1.8v 65ohm c5 pll_vdd pll 1.8v analog supply input a7 table 14: pin list signal function i/o type i/o level i/o drive pin
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 159 80a3020_ma001_08 pll_vss pll analog ground input a9 vdd18 1.8v digital supply inputs e5, e10, e11, e12, e15, e16, e17, e22, k5, k22, l5, l22, m5, m22, r5, r22, t5, t22, u5, u22, ab5, ab10, ab11, ab12, ab15, ab16, ab17, ab22, m14, n12, p15, r13 vdd33 3.3v digital supply inputs e4, e6, e7, e8, e13, e19, e20, e21, f4, f5, f22, g4, g5, g22, h4, h5, h22, j4, k4, l4, m4, n4, n22, p4, p5, r4, t4, u4, v4, w4, w5, w22, y4, y5, y22, aa4, aa5, aa22, ab14, ab19, ab20, ab21, ab4, ab6, ab7, ab8, ac5, ac6, ac7, ac8, ac9, ac10, ac11, ac12, ac13, ac14, ac15, ac16, ac17, ac18, ac19, ac20, ac21, ac22, l12, l15, m11, m16, r11, r16, t12, t15 vss digital ground inputs a1, a2, a6, a11, a16, a21, a26, b2, b25, b26, c3, c24, d4, d23, e9, e14, e18, f1, f26, j5, j22, l1, l26, n5, p22, t1, t26, v5, v22, aa1, aa26, ab9, ab13, ab18, ac4, ac23, ad3, ad24, ae1, ae2, ae25, af1, af6, af11, af16, af21, af25, af26, l11, l13, l14, l16, m12, m13, m15, n11, n13, n14, n15, n16, p11, p12, p13, p14, p16, r12, r14, r15, t11, t13, t14, t16 spares unused pins n/a table 14: pin list signal function i/o type i/o level i/o drive pin
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 160 80a3020_ma001_08 8.4 detailed sign al descriptions this section describes individual signals. 8.4.1 pci/x signal descriptions the pci/x interface is designed to be connected directly to any 3.3v, 32-bit or 64-bit pci or pci-x bus. the timing and functionality of all pci/x signals is with respect to the pclk clock signal. all pci/x signals detailed in the pinout ( table 17 on page 172 ) are compliant with the pci local bus specification (revision 2.2) and the pci-x addendum to pci local bus specification (revision 1.0b) . for detailed descriptions of the operations of the signals, please refer to the specifications.
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 161 80a3020_ma001_08 8.4.2 vmebus signal descriptions the tsi148 vme interface is designed to be connected to the vmebus through external buffers. refer to the american national standard for vme64 , american national standard for vme64 extensions , and source synchronous transfer (2esst) standard documents for a complete description of the vmebus. table 15: vmebus signal descriptions signal group signal name active i/o description buffer requirements data transfer va[31:1] address high i the vmebus address signals are monitored by the vme slave. during mblt transfers, the address lines are used to transfer data. these signals are connected to the vmebus through external bidirectional buffers. since lword_ is also used to transfer data, it should be included in the same buffer group as the vmebus address signals. o the vmebus address signals are driven by tsi148 when it is the vme master. during mblt transfers, the address lines are used to transfer data. vd[31:0] data high i the vmebus data signals are used to receive data from the vmebus during master read cycles and slave write cycles. they are also used to receive address information during a64 cycles. these signals are connected to the vmebus through external bidirectional buffers. o the vmebus data signals are driven by tsi148 to transmit data during master write cycles and slave read cycles. they are also used to transmit address information during a64 cycles. am[5:0] address modifier high i the vmebus address modifier signals are monitored by the vme slave. these signals are connected to the vmebus through an external bidirectional buffer. write_ and iack_ should be included in the same buffer. o the vmebus address modifier signals are driven by tsi148 when it is the vme master.
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 162 80a3020_ma001_08 data transfer lword_ long word low i the lword_ signal is monitored by the vme slave. the lword_ signal is also used as a data signal during mblt transfers. this signal is connected to the vmebus through an external bidirectional buffer. lword_ should be included in the same buffer group as the vmebus address signals. o the lword_ signal is driven by tsi148 when it is the vme master. the lword_ signal is also used as a data signal during mblt transfers. iack_ interrupt acknowledge low i the iack_ signal is monitored by the vme slave. this signal is connected to the vmebus through an external bidirectional buffer. iack_ should be included in the same buffer as the am and write_ signals. o the lword_ signal is driven by tsi148 when it is the vme master. write_ write low i the write_ signal is monitored by the vme slave. this signal is connected to the vmebus through an external bidirectional buffer. write_ should be included in the same buffer as the am and iack_ signals. o the write_ signal is driven by tsi148 when it is the vme master. asi_ address strobe input low i the asi_ signal is monitored by the vvme master and vme slave. this signal is received from the vmebus with an external non-inverting buffer. table 15: vmebus signal descriptions signal group signal name active i/o description buffer requirements
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 163 80a3020_ma001_08 data transfer aso_ address strobe output low o the aso_ signal is driven by tsi148 when it is the vme master. this signal is connected to the vmebus through an external tri-state buffer. ds0i_ data strobe 0 input low i vmebus data strobe 0 is monitored by tsi148?s vme slave. this signal is received from the vmebus with an external non-inverting buffer. ds0o_ data strobe 0 output low o vmebus data strobe 0 is driven by tsi148 during vme master cycles. this signal is connected to the vmebus through an external tri-state buffer. ds1i_ data strobe 1 input low i vmebus data strobe 1 is monitored by tsi148 vme slave. this signal is received from the vmebus with an external non-inverting buffer. ds1o_ data strobe 1 output low o vmebus data strobe 1 is driven by tsi148 during vme master cycles. this signal is connected to the vmebus through an external tri-state buffer. dtacki_ data acknowledge input low i the vmebus data acknowledge is monitored by tsi148?s vme master. this signal is received from the vmebus with an external non-inverting buffer. dtacko_ data acknowledge output low o the vmebus data acknowledge is driven by tsi148?s vme slave. this signal is connected to the vmebus through an external tri-state buffer. retryi_ retry input low i the vmebus retry is monitored by tsi148?s vme master. this signal is received from the vmebus with an external non-inverting buffer. retryo_ retry output low o the vmebus retry is driven by tsi148?s vme slave this signal is connected to the vmebus through an external tri-state buffer. table 15: vmebus signal descriptions signal group signal name active i/o description buffer requirements
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 164 80a3020_ma001_08 data transfer berri_ bus error input low i the vmebus bus error is monitored by tsi148?s vme master. this signal is received from the vmebus with an external non-inverting buffer. berro_ bus error output low o the vmebus bus error is driven by tsi148?s vme slave and global time-out timer. this signal is connected to the vmebus through an external tristate buffer. arbitration br[3:0]i_ bus request input low i the vmebus bus request signals are monitored by tsi148?s vmebus arbiter and requester. these signals are 5 volt tolerant and may be connected directly to the vmebus. br[3:0]o bus request output high o the vmebus bus request signals are driven by tsi148?s vmebus requester. these signals are connected to the vmebus through external inverting open collector buffers. bg[3:0]in_ bus grant input low i the vmebus bus grant in signals are monitored by tsi148?s vmebus requester. these signals are 5 volt tolerant and may be connected directly to the vmebus. bg[3:0]inout_ bus grant input low o the vmebus standard requires board in slot 1 to drive the bus grant in signals as outputs. these signals are connected to the bg[3:0]in_ signals. separate signals are provided to allow for external buffers. these signals are 5 volt tolerant and may be connected directly to the vmebus. these signals may be connected to the vmebus bg[3:0]in_ signals through external tri-state drivers. when external drivers are used, scon is the enable signal. bg[3:0]out_ bus grant input low o the vmebus grant out signals are driven by tsi148?s vmebus requester. these signals are 5 volt tolerant and may be connected directly to the vmebus. table 15: vmebus signal descriptions signal group signal name active i/o description buffer requirements
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 165 80a3020_ma001_08 arbitration bbsyi_ bus busy input low i the vmebus bus busy signal is monitored by tsi148?s vmebus requester and arbiter. this signal is received from the vmebus with an external non-inverting buffer. bbsyo bus busy output high o the vmebus bus busy signal is driven by tsi148?s vmebus requester. this signal is connected to the vmebus through an external inverting open collector buffer. bclri_ bus clear input low i the vmebus bus clear signal is monitored by tsi148?s vvme master. this signal is received from the vmebus with an external non-inverting buffer. bclro_ bus clear output low o the vmebus bus clear signal is driven by tsi148?s vmebus arbiter. this signal is connected to the vmebus through an external tri-state buffer. interrupt iackin_ interrupt acknowledge input low i the vmebus interrupt acknowledge in signal is monitored by tsi148?s vmebus interrupter. this signal is 5 volt tolerant and may be connected directly to the vmebus. iackout_ interrupt acknowledge output low o the vmebus interrupt acknowledge out signal is driven by tsi148?s vmebus interrupter. this signal is 5 volt tolerant and may be connected directly to the vmebus. irq[7:1]i_ interrupt input low i the vmebus interrupt request signals are monitored by tsi148?s vmebus interrupt handler. these signals are 5 volt tolerant and may be connected directly to the vmebus. irq[7:1]o interrupt output high o the vmebus interrupt request signals are driven by tsi148?s vmebus interrupter. these signals are connected to the vmebus through external inverting open collector buffers. table 15: vmebus signal descriptions signal group signal name active i/o description buffer requirements
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 166 80a3020_ma001_08 utility srsti_ system reset input low i the vmebus system reset signal is used to reset the vmebus logic. it causes the lrsto_ signal to be asserted which causes a local bus reset. this signal is 5 volt tolerant and may be connected directly to the vmebus. srsto system reset output high o the vmebus system reset signal is driven to reset the vmebus. this signal is connected to the vmebus through an external inverting open collector buffer. sfaili_ system fail input low i the vmebus system fail signal is monitored by tsi148?s interrupter logic. if enabled, an interrupt is generated on the falling edge of sfaili_. this signal is 5 volt tolerant and may be connected directly to the vmebus. sfailo system fail output high o the vmebus system fail signal is driven by tsi148 when the bdfail_ signal is asserted and the sysfail signal is not inhibited. this signal is connected to the vmebus through an external inverting open collector buffer. acfaili_ ac fail input low i the vmebus ac fail signal is monitored by tsi148?s interrupter logic. if enabled, an interrupt is generated on the falling edge of acfaili_. this signal is 5 volt tolerant and may be connected directly to the vmebus. sysclk system clock output o the system clock signal is driven by tsi148 when the system controller function is enable. this signal is connected to the vmebus through an external tri-state buffer. utility ga[4:0]_ geographic address input low i these signals are connected to the geographic address signals on the vmebus. since these signals are either grounded or open on the backplane, they can be connected directly to tsi148. gap_ geographic address parity input low i this signal is connected to the geographic address parity signal on the vmebus. since this signal is either grounded or open on the backplane, it can be connected directly to tsi148. table 15: vmebus signal descriptions signal group signal name active i/o description buffer requirements
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 167 80a3020_ma001_08 buffer control amout address bus out high o this signal is used to control the direction of the external buffers on the am, iack_ and write_ signals. dbout data bus out high o this signal is used to control the direction of the external buffers on the d bus signals. dboe_ data bus output enable low o this signal is used to control the enable of the external buffers on the d bus, a bus and lword_ signals. adbout address/data bus out high o this signal is used to control the direction of the external buffers on the a bus and lword_ signals. these signal are used to transfer data during mblt transfers. asoe address strobe output enable high o this signal is used to enable the address strobe driver. dsoe data strobe output enable high o this signal is used to enable the data strobe 0 and 1 drivers. dtackoe data transfer acknowledge output enable high o this signal is used to enable the data transfer acknowledge driver. berroe bus error output enable high o this signal is used to enable the bus error driver. retryoe retry output enable high o this signal is used to enable the retry driver. table 15: vmebus signal descriptions signal group signal name active i/o description buffer requirements
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 168 80a3020_ma001_08 buffer control scon system controller enabled high o this signal is asserted when the system controller function is enabled. this signal is used to enable the bclr_ and sysclk drivers. configuration sconen_ system controller enable low i when this signal is asserted and the scondis_ signal is negated. the system controller functions are enabled. when sconen_ and scondis_ signals are negated, the auto scon function is enabled. scondis_ system controller disable low i when this signal is asserted and the sconen_ signal is negated. the system controller functions are disabled. when sconen_ and scondis_ signals are negated, the auto scon function is enabled. table 15: vmebus signal descriptions signal group signal name active i/o description buffer requirements
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 169 80a3020_ma001_08 8.4.3 miscellaneous signal descriptions table 16: miscellaneous signal descriptions signal group signal name active i/o description utility bdfail_ board fail low i/o when this signal is asserted, the sfailo signal is asserted if the sysfail inhibit bit is not set. reset control lrsti_ local reset input low i when this signal is asserted, the pci bus internal logic is reset. this signal should be connected to the boards local bus reset signal. lrsto_ local reset output low o when this signal is asserted, the pci bus logic on the board should be reset. this signal should be co mbined with other reset signals to generate the local bus reset signal. lsrsti_ local system reset input low i when this signal is asserted, the lrsto signal is asserted. this signal allows on board logic to generate a vmebus system reset. pursti_ power up reset input low i pursti_ is asserted at power up. interrupt inta_- intd_ low o these pins are the pci bus interrupt outputs. hardware configuration hwc_pfu high i when tsi148 is configured in 32-bit pci mode and this signal is low, the 64-bit extension signals are driven. when tsi148 is configured in 32-bit pci mode and this signal is high, the 64-bit extension signals are tri-stated. pcipuen high i when this signal is asserted, the internal pci bus pull ups are enable. when this signal is negated, the internal pci bus pull ups are disabled. pcimc high i when this signal is asserted, the pci drivers are configured with a 40 ohm impedance for point-to-point operation. when this signal is negated, the pci drivers are configured with a 20 ohm impedance for multi-point operation.
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 170 80a3020_ma001_08 pll pll_ten high i when this signal is high, the pll_tune signals are used to tune the pll. pll_tune [9:0] high i when the pll_ten signal is asserted, these signals are used to tune the pll. when pll_ten signal is negated, the pll tune bits are internally controlled. pll_rsti_ low i when this signal is asserted, the pll is reset. pll_outa - - pll output: this output is internally disabled. temperature tm_in the tm_in and tm_out signals can be used to measure the die temperature. tn_out test tck high i this signal is used to clock state information and test data into and out of tsi148 during ieee 1149.1 test operation. tms high i this signal is used to control the state of the tap controller during ieee 1149.1 test operation. tdi high i this signal is used to serially shift test data and test instructions into tsi148 during ieee 1149.1 test operation. tdo high o this signal is used to serially shift test data and test instructions out of tsi148 during ieee 1149.1 test operation. trst_ low i this signal provides an asynchronous initialization of the ieee 1149.1 compliant tap controller. ceo_test high i this signal is used during factory test. it should be pulled down on the pwb. power vdd2 i the +3.3v pins provide power for the i/o buffers. vdd i the +1.8v pins provide power for the internal core logic. vss i these pins form the ground connections for all of the input macros, output macros, and core logic. pll_vdd i the +1.8v pin provides clean power to the internal analog phase locked loop. pll_vss i this input provides clean ground to the internal analog phase locked loop. table 16: miscellaneous signal descriptions signal group signal name active i/o description
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 171 80a3020_ma001_08 8.5 pinout tsi148?s pinout is illustrated in the figure 34 use this diagram along with the tables in the following sections to locate pin assignments on the tsi148: ? table 17 on page 172 lists the pinout according to pin assignment ? table 18 on page 179 lists ground pins according to pin assignment ? table 19 on page 182 lists core power pins according to pin assignment ? table 20 on page 183 lists i/o power pins according to pin assignment figure 34: pinout ? bottom view 20 21 22 23 24 25 26 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b a f a e a d a c a a y w v u t r p n m l k j h g f e d c b a
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 172 80a3020_ma001_08 8.5.1 sorted by pin assignment the following table lists tsi148?s pinout in num erical order according to pin assignment. use this table along with figure 34 on page 171 to locate tsi148 signal names or pin assignments. table 17: pinout ? sorted by pin assignment pin assignment signal name a03 pll_tune7 a04 vd1 a05 pll_tune4 a07 pll_vdda a08 vd8 a09 pll_gnda a10 vd12 a12 vd20 a13 vd21 a14 vd24 a15 vd25 a17 bbsyi_ a18 bg0out_ a19 bg1inout_ a20 bg2in_ a22 br1o a23 br2i_ a24 berro_ a25 adbout b01 scon b03 pll_tune9 b04 pll_tune6 b05 pll_ten b06 vd2 b07 vd3 b08 pll_tune3 b09 vd7 b10 vd10 b11 vd11 b12 vd15 b13 vd19 b14 vd26 b15 vd30 b16 bclro_ b17 bg0in_
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 173 80a3020_ma001_08 b18 bg1in_ b19 bg3out_ b20 br0o b21 br2o b22 br3i_ b23 berroe b24 amout c01 tdi c02 scondis_ c04 pll_tune8 c05 pll_outa c06 pll_tune5 c07 vd4 c08 pll_tune2 c09 vd9 c10 pll_tune0 c11 vd14 c12 vd17 c13 vd23 c14 vd22 c15 vd27 c16 vd31 c17 bclri_ c18 bg1out_ c19 bg2inout_ c20 bg3in_ c21 br1i_ c22 berri_ c23 dboe_ c25 dtackoe c26 dsoe d01 trst_ d02 tck d03 no connect d05 pll_rsti_ d06 vd0 d07 pclk d08 vd5 table 17: pinout ? sorted by pin assignment (continued) pin assignment signal name
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 174 80a3020_ma001_08 d09 vd6 d10 pll_tune1 d11 vd13 d12 vd18 d13 vd16 d14 vd29 d15 vd28 d16 bbsyo d17 bg0inout_ d18 bg2out_ d19 bg3inout_ d20 br0i_ d21 br3o d22 dbout d24 dtacko_ d25 ds0o_ d26 ds1i_ e01 intb_ e02 tms e03 sconen_ e23 dtacki_ e24 sysclk e25 ds0i_ e26 iackout_ f02 tdo f03 inta_ f23 ds1o_ f24 aso_ f25 asoe g01 ad62 g02 intc_ g03 intd_ g23 asi_ g24 retryoe g25 iackin_ g26 iack_ h01 ad59 h02 ad63 table 17: pinout ? sorted by pin assignment (continued) pin assignment signal name
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 175 80a3020_ma001_08 h03 ad61 h23 retryo_ h24 am0 h25 retryi_ h26 am3 j01 ad57 j02 ad60 j03 ad58 j23 am1 j24 am4 j25 am2 j26 lword_ k01 ad54 k02 no connect k03 ad56 k23 write_ k24 va1 k25 am5 k26 va3 l02 ad55 l03 ad53 l23 va4 l24 va5 l25 va2 m01 no connect m02 ad52 m03 ad51 m23 va9 m24 va8 m25 va6 m26 va11 n01 ad49 n02 ad50 n03 ad47 n23 va7 n24 va14 n25 va10 n26 va12 table 17: pinout ? sorted by pin assignment (continued) pin assignment signal name
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 176 80a3020_ma001_08 p01 ad46 p02 ad44 p03 ad48 p23 va20 p24 va13 p25 va17 p26 va15 r01 ad45 r02 ad42 r03 ad43 r23 va19 r24 va18 r25 va21 r26 va16 t02 ad40 t03 ad41 t23 va23 t24 va22 t25 va25 u01 no connect u02 ad37 u03 ad39 u23 va28 u24 va26 u25 va29 u26 va24 v01 ad38 v02 ad34 v03 ad36 v23 acfaili_ v24 va30 v25 no connect v26 va27 w01 ad35 w02 par64 w03 ad33 w23 lrsti_ w24 pursti_ table 17: pinout ? sorted by pin assignment (continued) pin assignment signal name
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 177 80a3020_ma001_08 w25 lrsto_ w26 va31 y01 ad32 y02 cbe6_ y03 cbe7_ y23 sfailo y24 bdfail_ y25 srsto y26 lsrsti_ aa02 ack64_ aa03 cbe4_ aa23 irq2o aa24 sfaili_ aa25 irq1i_ ab01 cbe5_ ab02 perr_ ab03 gnt_ ab23 tm_in ab24 irq3i_ ab25 pcimc ab26 srsti_ ac01 req64_ ac02 serr_ ac03 pcipuen ac24 irq4o ac25 irq2i_ ac26 irq1o ad01 m66en ad02 req_ ad04 hwc_pfu ad05 irdy_ ad06 cbe1_ ad07 ad31 ad08 ad28 ad09 ad25 ad10 ad23 ad11 ad20 ad12 ad18 table 17: pinout ? sorted by pin assignment (continued) pin assignment signal name
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 178 80a3020_ma001_08 ad13 ad14 ad14 ad15 ad15 ad10 ad16 ad8 ad17 ad6 ad18 ad3 ad19 ad0 ad20 ga2_ ad21 gap_ ad22 irq5o ad23 irq5i_ ad25 irq4i_ ad26 irq3o ae03 frame_ ae04 stop_ ae05 idsel ae06 cbe2_ ae07 par ae08 ad30 ae09 ad27 ae10 no connect ae11 ad22 ae12 ad19 ae13 ad17 ae14 ad11 ae15 ad9 ae16 ad7 ae17 ad4 ae18 ad1 ae19 ga3_ ae20 ga1_ ae21 irq7i_ ae22 ce0_test ae23 irq6i_ ae24 no connect ae26 tm_out af02 devsel_ af03 trdy_ table 17: pinout ? sorted by pin assignment (continued) pin assignment signal name
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 179 80a3020_ma001_08 8.5.1.1 ground pins the following table lists tsi148?s ground pins in numerical order according to pin assignment. use this table along with figure 34 on page 171 to locate tsi148 signal names or pin assignments. af04 cbe3_ af05 cbe0_ af07 ad29 af08 ad26 af09 ad24 af10 ad21 af12 no connect af13 ad16 af14 ad13 af15 ad12 af17 no connect af18 ad5 af19 ad2 af20 ga4_ af22 ga0_ af23 irq7o af24 irq6o table 18: vss (ground) ? sorted by pin assignment pin assignment signal name a01 vss a02 vss a06 vss a11 vss a16 vss a21 vss a26 vss b02 vss b25 vss b26 vss c03 vss c24 vss d04 vss table 17: pinout ? sorted by pin assignment (continued) pin assignment signal name
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 180 80a3020_ma001_08 d23 vss e09 vss e14 vss e18 vss f01 vss f26 vss j05 vss j22 vss l01 vss l11 vss l13 vss l14 vss l16 vss l26 vss m12 vss m13 vss m15 vss n05 vss n11 vss n13 vss n14 vss n15 vss n16 vss p11 vss p12 vss p13 vss p14 vss p16 vss p22 vss r12 vss r14 vss r15 vss t01 vss t11 vss t13 vss t14 vss t16 vss t26 vss table 18: vss (ground) ? sorted by pin assignment (continued) pin assignment signal name
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 181 80a3020_ma001_08 v05 vss v22 vss aa01 vss aa26 vss ab09 vss ab13 vss ab18 vss ac04 vss ac23 vss ad03 vss ad24 vss ae01 vss ae02 vss ae25 vss af01 vss af06 vss af11 vss af16 vss af21 vss af25 vss af26 vss table 18: vss (ground) ? sorted by pin assignment (continued) pin assignment signal name
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 182 80a3020_ma001_08 8.5.1.2 power pins the following tables lists tsi148?s core and i/o power pins in numerical order according to pin assignment. use this table along with figure 34 on page 171 to locate tsi148 signal names or pin assignments. table 19: core power (1.8 v) ? sorted by pin assignment pin assignment signal name e05 vdd e10 vdd e11 vdd e12 vdd e15 vdd e16 vdd e17 vdd e22 vdd k05 vdd k22 vdd l05 vdd l22 vdd m05 vdd m14 vdd m22 vdd n12 vdd p15 vdd r05 vdd r13 vdd r22 vdd t05 vdd t22 vdd u05 vdd u22 vdd ab05 vdd ab10 vdd ab11 vdd ab12 vdd ab15 vdd ab16 vdd ab17 vdd ab22 vdd
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 183 80a3020_ma001_08 table 20 shows tsi148?s i/o power pins in numerical order according to pin assignment. use this table along with figure 34 on page 171 to locate tsi148 signal names or pin assignments. table 20: i/o power (3.3 v) ? sorted by pin assignment pin assignment signal name e04 vdd2 e06 vdd2 e07 vdd2 e08 vdd2 e13 vdd2 e19 vdd2 e20 vdd2 e21 vdd2 f04 vdd2 f05 vdd2 f22 vdd2 g04 vdd2 g05 vdd2 g22 vdd2 h04 vdd2 h05 vdd2 h22 vdd2 j04 vdd2 k04 vdd2 l04 vdd2 l12 vdd2 l15 vdd2 m04 vdd2 m11 vdd2 m16 vdd2 n04 vdd2 n22 vdd2 p04 vdd2 p05 vdd2 r04 vdd2 r11 vdd2 r16 vdd2 t04 vdd2 t12 vdd2 t15 vdd2 u04 vdd2
8. signals and pins tsi148 pci/x-to-vme bus bridge user manual 184 80a3020_ma001_08 v04 vdd2 w04 vdd2 w05 vdd2 w22 vdd2 y04 vdd2 y05 vdd2 y22 vdd2 aa04 vdd2 aa05 vdd2 aa22 vdd2 ab14 vdd2 ab19 vdd2 ab20 vdd2 ab21 vdd2 ab04 vdd2 ab06 vdd2 ab07 vdd2 ab08 vdd2 ac05 vdd2 ac06 vdd2 ac07 vdd2 ac08 vdd2 ac09 vdd2 ac10 vdd2 ac11 vdd2 ac12 vdd2 ac13 vdd2 ac14 vdd2 ac15 vdd2 ac16 vdd2 ac17 vdd2 ac18 vdd2 ac19 vdd2 ac20 vdd2 ac21 vdd2 ac22 vdd2 table 20: i/o power (3.3 v) ? so rted by pin assignment (continued) pin assignment signal name
tsi148 pci/x-to-vme bus bridge user manual 185 80a3020_ma001_08 9. electrical characteristics the electrical characteristics of a device depend on its design and intended application. device signals that are protoc ol-compliant must conform with a set of electrical operating characteristics for that protocol. dc electrical characteristics for a device define parameters such as supply, input, and output voltages. ac characteristics specify the input requirements (for example, setup and hold times) and output re sponses (that is, delays from clock to signal) and are normally defined for each clock domain for a device. absolute maximum ratings, if available, define the maximum operating conditions such as supply voltage, power, and operating temperature. this chapter discusses the following topics about tsi148?s electrical characteristics: ? ?operating conditions? on page 188 ? ?power consumption? on page 189 ? ?thermal characteristics? on page 190 ? ?electrostatic discharge (esd)? on page 191
9. electrical characteristics tsi148 pci/x-to-vme bus bridge user manual 186 80a3020_ma001_08 9.1 overview of electrical characteristics tempe?s electrical characteristics are defined by pci/x electrical characteristics and non-pci/x electrical characteristics. 9.1.1 pci/x electrical characteristics the tsi148's pci/x interface is electrically co mpatible with the 3.3v signaling interface as defined by the pci-x addendum to pci-x addendum to pci local bus specification (revision 1.0b) and the pci local bus specification (revision 2.2) . table 21 specifies dc characteristics of all tsi148?s pci/x signal pins. table 21: pci/x electrical characteristics symbol parameter condition pci-x 3.3v conventional pci units min max min max v v dd supply voltage 3.0v 3.6v 3.0v 3.6v v v ih input high voltage 0.5*v dd v dd + 0.5 0.5*v dd v dd + 0.5 v v il input low voltage -0.5 0.35*v dd -0.5 0.3*v dd v v ipu input pull-up voltage 0.7*v dd 0.7*v dd v v oh output high voltage i out = -500a 0.9*v dd 0.9*v dd v v ol output low voltage i out = 1500a 0.1*v dd 0.1*v dd v c in input pin capacitance 810pf
9. electrical characteristics tsi148 pci/x-to-vme bus bridge user manual 187 80a3020_ma001_08 9.1.2 non-pci electrical characteristics the following tables detail the dc characteristics of all non-pci/x tsi148 signal pins. table 22: 3.3 v lvttl dc electrical characteristics symbol parameter condition min max units v il input low voltage - 0.0 0.8 v v ih input high voltage - 2.0 vdd2 v table 23: 5.0 v lvttl dc electrical characteristics symbol parameter condition min max units v il input low voltage - 0.0 0.8 v v ih input high voltage - 2.0 5.5 v table 24: common receiver dc electrical characteristics symbol parameter condition min max units i in input leakage current - 0 a i in input leakage current (pull-up) v = 0v -150 a i in input leakage current (pull-down) v = vdd io max 200 a table 25: lvttl driver dc electrical characteristics symbol parameter condition min max units v oh a a. vdd is 1.65v and the temperature is 100 c output high voltage i oh = -15.3 ma (35 ohm output) 2.4 v v ol a output low voltage i ol = 10.2 ma (35 ohm output) 0.4 v v oh a output high voltage i oh = -8.2 ma (65 ohm output) 2.4 v v ol a output low voltage i ol = 5.4 ma (65 ohm output) 0.4 v
9. electrical characteristics tsi148 pci/x-to-vme bus bridge user manual 188 80a3020_ma001_08 9.2 operating conditions 9.2.1 absolute maximum operating conditions stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this spec ification is not implied. exposure to absolute maximum rating conditions for extended pe riods may affect device reliability. table 26: 1.8 v cmos driver dc electrical characteristics symbol parameter condition min max units v oh output high voltage i oh = -6.1 ma (65 ohm output) 1.2 v v ol output low voltage i ol = 6.0 ma (65 ohm output) 0.45 v table 27: absolute maximum ratings symbol parameter min max unit v dd 1.8v dc supply voltage -0.3 2.0 v v dd2 3.3v dc supply voltage -0.3 3.6 v v in lvttl input voltage -0.6 v dd33 + 0.3 v v in 5v-tolerant input voltage -0.6 +5.5 v i in dc input current -10 +10 a t stg storage temperature range -65 +150 c
9. electrical characteristics tsi148 pci/x-to-vme bus bridge user manual 189 80a3020_ma001_08 9.2.2 recommended operating conditions this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. unused inputs must always be tied to an appropriate logic voltage level. 9.3 power consumption table 29 shows the power dissipation for tsi148 using different frequency parameters and bus loading. table 30 shows how the power dissipation is divided in the tsi148. the io portion can be determined by subtracting the total core logic power from the total power dissipation. table 28: recommended operating conditions symbol parameter min max unit v dd 1.8v dc supply voltage +1.65 +1.95 v v dd2 3.3v dc supply voltage +3.0 +3.6 v pll_vdd pll 1.8v analog supply 1.65 1.95 v t a operating ambient temperature range (commercial) 0 +70 c t a operating ambient temperature range (industrial) -40 +85 c tj junction temperature +122 c table 29: tsi148 total power dissipation (core + io) pci/x clock frequency (mhz) pci/x load (pf) minimum (w) nominal (w) maximum (w) 133 10 1.19 1.41 1.64 100 20 1.24 1.46 1.71 66 40 1.34 1.58 1.84 table 30: tsi148 power dissipation division source nominal (w) total core logic power 1.322 pll power 0.030
9. electrical characteristics tsi148 pci/x-to-vme bus bridge user manual 190 80a3020_ma001_08 9.4 thermal characteristics based on the worst case die power dissipation of 1.84w the tsi148?s thermal performance does meet the industrial grade requirements. th ese results are based on the tsi148 being routed on an 8 layer pcb. it should be noted that the thermal simulations for a jedec standard 4 layer pcb with a worst case power dissipation of 1.84w, the tsi148 does not have sufficient thermal performance to meet the indust rial grade requirements. if the worst case die power dissipation is less than or equal to 1.7w the tsi148 does have sufficient thermal performance to meet the industrial grade requirements when routed on a 4 layer pcb. the maximum ambient temperature of the tsi148 can be calculated as follows: ta <= tj - theta ja * p where, ta = ambient temperature ( c ) tj = maximum tsi148 junction temperature (c) = 122c theta ja = ambient to junction thermal impedance ( c /watt) p = tsi148 power consumption (watts) ( section 9.3 on page 189 ). the ambient to junction thermal impedance (theta ja) is dependent on the air flow in meters per second over the tsi148. tables 31 and 32 show the package thermal performance for the tsi148 device according to the number of layers on the pcb. table 31: 456 epbga package thermal performance for an 8 layer pcb air flow (m/s) power consumption (w) theta ja (c/w) 01.8419 1 1.84 16.1 2 1.84 15.1
9. electrical characteristics tsi148 pci/x-to-vme bus bridge user manual 191 80a3020_ma001_08 9.5 electrostatic discharge (esd) the tsi148 is a charge device model test (c dm) class ii device as classified in the jedec jesd22-c101-a specification . table 33 shows the varying esd tests and jedec classifications for the tsi148 device. the tsi148 has passed a cdm of 200v protection, but failed 500v protection. this rates the tsi148 as jedec class ii (200v to <500v). the exact threshold voltage has not yet been determined but is between 200v and 500v. the most sensitive cdm tsi148 pins are pll_vdd, pll_vss, pll_outa, and ceo_test. all other pins meet cdm class iii (500v to <1000v). 9.5.1 esd precautions precautions must be taken to reduce esd exposure. the following practices are recommended to help reduce esd exposure: ? wear wrist straps while seated ? wear footwear or heal straps while standing ? wear esd smocks ? regularly check wrist straps and footwear table 32: 456 epbga package thermal performance for a 4 layer pcb air flow (m/s) power consumption (w) theta ja (c/w) 0 1.84 21.5 1 1.84 18.0 2 1.84 16.8 table 33: tsi148 esd classification esd test protection value jedec rating jedec specification human body model (hbm) 2000v class 2 jesd22-a114-b machine model (mm) 200v class b jesd22-a115-a charge device model (cdm) 200v class ii jesd22-c101-a
9. electrical characteristics tsi148 pci/x-to-vme bus bridge user manual 192 80a3020_ma001_08 ? ensure esd dissipative flooring and work surfaces ? ensure work surfaces and equipment connected to electrical ground ? use esd compliant chairs and carts, or ?drag-chain? to the floor ? maintain humidity between 30% and 70% in all inspection and assembly areas ? minimize inspection and handling. if inspectio n is required, keep parts within trays (if possible) ? ensure conductive and electrostatic generating materials are not in close proximity to the tsi148 when unprotected. for example, shop travelers, labels, cardboard, plexiglas, wood, crt screens, etc. ? use ionization systems to help dissipate resi dual charge built up on any material that is static generating and is in close proximity to the tsi148 ? use a field strength meter to check items th at come into contact with the tsi148. the field strength meter tool is useful in conf irming safe surfaces and those that contain residual charges needing neutralizing ionizers.
tsi148 pci/x-to-vme bus bridge user manual 193 80a3020_ma001_08 10. registers this appendix describes the tsi148?s regist ers. the following topics are discussed: ? ?overview of registers? on page 194 ? ?register groupings? on page 194 ? ?register endian mapping? on page 197 ? ?register map? on page 199
10. registers tsi148 pci/x-to-vme bus bridge user manual 194 80a3020_ma001_08 10.1 overview of registers this chapter provides a detailed description of the tsi148?s internal registers. these registers are separated into four groups: the pci/x configuration space registers (pcfs), the local control and status registers (lcsr), the vm ebus global control and status registers (gcsr) and the vmebus configuration rom / control and status registers (cr/csr). registers can be accessed by the tsi148 pci/x target or the vme slave through the internal linkage module. 10.2 register groupings tsi148 register space is separated into different groups within tsi148. figure 35 shows the complete register map and individual groups. figure 35: combined register group (crg) 10.2.1 combined register group (crg) the crg requires 4 kbytes of address space. the address space can be mapped into pci/x address space using the standard pci/x bar (located at offsets 0x10h and 0x14h). all crg accesses through the pci/x bar pass through the pci/x target interface. 4 kbyte crg 256 bytes 1280 bytes 32 bytes 1504 bytes 1024 bytes pcfs lcsr gcsr reserved csr
10. registers tsi148 pci/x-to-vme bus bridge user manual 195 80a3020_ma001_08 the crg can also be mapped into a16, a24, a32 and a64 vme address space through the crg image (located at offsets 0x40ch ? 0x414h). the crg can be accessed using d8, d16 and d32 sct transactions. all accesses pass through the vme slave interface. alternatively, the crg can be accessed as part of the 512 kbyte cr/csr area defined in the american national standard for vme64 by using the special a24 cr/csr am code. 10.2.2 pci/x configuration space registers (pcfs) this register area is the standard pci/x configuration space and is accessible from the pci/x bus using pci/x configuration cycles. the pcfs area includes a standard 64-bit base address register (see mbarl and mbaru registers in section 10.4.2 on page 200 ) which enables the crg to be mapped into pci/x memory space. the pcfs can also be accessed from the vmebus as part of the crg group. 10.2.3 local control and status registers (lcsr) the lcsr register group contains the inbo und and outbound map decoder registers, dma, interrupt control registers, and other miscellane ous registers. it can accessed from either the pci/x bus or vmebus as part of the crg. 10.2.4 global control and status registers (gcsr) the gcsr register group contains control bits, semaphore, and mailbox registers which allow information to be passed between processors on other vmebus boards and the local processor. it can accessed from either the pci/x bus or vm ebus as part of the crg. alternatively, the gcsr group can be independently accessed from the vmebus by using the gcsr image (located at offsets 0x418h ? 0x420h). the gcsr can be mapped to the vmebus a16, a24, a32 or a64 address spaces and accepts d8, d16 and d32 sct transactions. 10.2.5 control and status registers (csr) the csr register group is a sub-set of the cr/csr section of the cr/csr registers defined in the american national standard for vme64 extensions . tsi148 implementation of these standard registers include: the cr/csr bit clear, cr/csr bit set, and cr/csr base address registers.
10. registers tsi148 pci/x-to-vme bus bridge user manual 196 80a3020_ma001_08 10.2.6 cr/csr register access the 512 kbyte cr/csr space, shown in figure 36 , can be accessed from the vmebus using the special a24 cr/csr am code. the base address is defined by either geographical address implementation or auto slot id. tsi148?s vme slave can be configured at power-up to use one of the two methods (see section 5.4 on page 128 ). when an access is initiated on the vmebus using the a24 cr/csr am code, the tsi148 initiates an access on the pci/x bus when the enable bit in the cr/csr attribute register is set (locat ed at offset 0x420). the address generated on the pci/x bus is determined by the values in the cr/csr offset registers (located at offsets 0x418 and 0x41c). these values are added to the internal vmebus address to create the pci/x bus address. the address space is separated into the following areas: ? the upper 4 kbytes defines the tsi148 crg ? the remaining 508 kbytes maps to the pci/x bus. ? when an access is initiated on the vmeb us using a24 cr/csr am code, tsi148 initiates an access on the pci/x bus when the cr/csr offset register is enabled. figure 36: cr/csr address space 512 kbyte cr/csr 4 kbyte 508 kbyte tempe crg maps to pci bus 512 kbyte cr/csr are a is defined in the vme6 4 extensions standard 0x00000 0x7ffff
10. registers tsi148 pci/x-to-vme bus bridge user manual 197 80a3020_ma001_08 10.3 register en dian mapping the vmebus uses big-endian byte ordering and the pci/x bus uses little-endian byte ordering. the byte ordering differences are accommodated by swapping the data in the pci/x master and pci/x target before it is passed to the linkage module. data transferred between the pci/x bus and the linkage module is swapped as shown in figure 37 . this method of handling the endian problem is called a ddress invariance . if data is accessed using byte operations, little endian and big endian processors view the same data. if data is accessed using 32-bit accesses, little endian and big endian processors see different views of the same data. figure 37: big to little endian data swap when viewed from the vmebus, the lcsr, gcsr and cr/csr registers appear as presented in the programming section. when viewed from the vmebus, the pcfs registers appear swapped. d39-32 d47-40 d55-48 d63-56 d07-00 d15-08 d23-16 d31-24 d63-56 d55-48 d47-40 d39-32 d31-24 d23-16 d15-08 d07-00 linkage 64-bit pci/x d39-32 d47-40 d55-48 d63-56 d07-00 d15-08 d23-16 d31-24 d31-24 d23-16 d15-08 d07-00 linkage 32-bit pci/x d7 d6 d5 d4 d3 d2 d1 d0 d0 d1 d2 d3 d4 d5 d6 d7 d7 d6 d5 d4 d3 d2 d1 d0 d0 d1 d2 d3 d4 d5 d6 d7
10. registers tsi148 pci/x-to-vme bus bridge user manual 198 80a3020_ma001_08 when viewed from the pci/x bus, the lcsr, gcsr and cr/csr registers appear swapped. when viewed from the pci/x bus, the pcfs registers appear as presented in the programming section. table 34 summarizes the register views. this table assumes the processor is operating in big endian mode and that the bridge between the processor bus and pci/x bus swaps the data. this table assumes the 32-bit value abcd is stored in a register and that the data is accessed using a 32-bit read. data transferred between the vmebus and the pci/x bus is swapped. when a processor operating in big endian mode transfers data from the vmebus, the data is swapped in the vme bridge and swapped again in the host bridge. the two swaps effectively cancel each other and processor sees the vmebus data in the correct order. when a processor operating in little endian mode is used, th e vmebus data appears swapped. table 34: endian register views register group value in register value on pci/x bus value on processor bus value on vmebus pcfs abcd abcd dcba dcba lcsr abcd dcba abcd abcd gcsr abcd dcba abcd abcd cr/csr abcd dcba abcd abcd
10. registers tsi148 pci/x-to-vme bus bridge user manual 199 80a3020_ma001_08 10.4 register map the register map shows all the tsi148 register groupings in the combined register group (crg). the crg requires 4 kbytes of address space. the address space can be mapped into pci/x address space or vmebus address space. refer to section 10.2.1 on page 194 for more information on the crg and all the group that comprise the tsi148 registers. 10.4.1 conventions the following conventions are used to describe the operation of a register bit and are found in the ?type? column of the register description table: ? r: read only field ? r/w: read/write field. ? s: writing a 1 to this field sets this field. ? c: writing a1 to this field clears an associated field. ? r/s: writing a 1 to this field sets an associat ed field. reading this field returns the current value of the associated field. ? r/c: writing a1 to this field clears an asso ciated field. reading this field returns the current value of the associated field the following conventions are used to describe the effect of the reset signals on a register bit and are found in the ?reset by? heading of the register description table: ? l: the field is affected by pci/x local bus reset. ? s: the field is affected by vmebus system reset. ? p: the field is affected by power up reset. ? x : the reset value depends on configuration options. bits that are reset by multiple signals show the signals with a slash (/) separating them. for example, if a bit is reset by all the reset signals , the register table shows the following value: l/s/p/x.
10. registers tsi148 pci/x-to-vme bus bridge user manual 200 80a3020_ma001_08 10.4.2 pcfs register group overview this register area is the standard pci/x configuration space and is accessible from the pci/x bus using pci/x configuration cycles. refer to section 10.2.2 on page 195 for more information on the pcfs registers. table 35: pcfs register group function bits offset pcfs/ crg 31 24 23 16 15 8 7 0 pci/x configuration header device id (devi) vendor id (veni) 0x00/ 0x000 status (stat) command (cmmd) 0x04/ 0x004 class code (clas) revision id (revi) 0x08/ 0x008 reserved header type (head) master latency timer (mlat) cache line size (clsz) 0x0c/ 0x00c memory base address lower (mbarl) 0x10/ 0x010 memory base address upper (mbaru) 0x14/ 0x014 reserved 0x18/ 0x018 reserved 0x1c/ 0x01c reserved 0x20/ 0x020 reserved 0x24/ 0x024
10. registers tsi148 pci/x-to-vme bus bridge user manual 201 80a3020_ma001_08 pci/x configuration header reserved 0x28/ 0x028 subsystem id (subi) subsystem vendor id (subv) 0x2c/ 0x02c reserved 0x30/ 0x030 reserved capabilities pointer (capp) 0x34/ 0x034 reserved 0x38/ 0x038 maximum latency (mxla) minimum grant (mngn) interrupt pin (intp) interrupt line (intl) 0x3c/ 0x03c pci-x capabilities pci-x capabilities (pcixcap) 0x40/ 0x040 pci-x status (pcixstat) 0x44/ 0x044 reserved reserved 0x48/ 0x048 reserved - reserved 0xff/ 0x0ff table 35: pcfs register group function bits offset pcfs/ crg 31 24 23 16 15 8 7 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 202 80a3020_ma001_08 10.4.3 lcsr register group overview the lcsr register group contains the inbo und and outbound slave image registers, dma, interrupt control registers, and other miscellane ous registers. it can accessed from either the pci/x bus or vmebus as part of the crg. table 36: lcsr register group function bits offset crg 31 24 23 16 15 8 7 0 outbound functions outbound translation 0 outbound translation starting address upper 0 (otsau0) 0x100 outbound translation starting address lower 0 (otsal0) 0x104 outbound translation ending address upper 0 (oteau0) 0x108 outbound translation ending address lower 0 (oteal0) 0x10c outbound translation offset upper 0 (otofu0) 0x110 outbound translation offset lower 0 (otofl0) 0x114 outbound translation 2esst broadcast select 0 (otbs0) 0x118 outbound translation attribute 0 (otat0) 0x11c
10. registers tsi148 pci/x-to-vme bus bridge user manual 203 80a3020_ma001_08 outbound functions outbound translation 1 otsau1 0x120 otsal1 0x124 oteau1 0x128 oteal1 0x12c otofu1 0x130 otofl1 0x134 otbs1 0x138 otat1 0x13c outbound translation 2 otsau2 0x140 otsal2 0x144 oteau2 0x148 oteal2 0x14c otofu2 0x150 otofl2 0x154 otbs2 0x158 otat2 0x15c outbound translation 3 otsau3 0x160 otsal3 0x164 oteau3 0x168 oteal3 0x16c otofu3 0x170 otofl3 0x174 otbs3 0x178 otat3 0x17c table 36: lcsr register group function bits offset crg 31 24 23 16 15 8 7 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 204 80a3020_ma001_08 outbound functions outbound translation 4 otsau4 0x180 otsal4 0x184 oteau4 0x188 oteal4 0x18c otofu4 0x190 otofl4 0x194 otbs4 0x198 otat4 0x19c outbound translation 5 otsau5 0x1a0 otsal5 0x1a4 oteau5 0x1a8 oteal5 0x1ac otofu5 0x1b0 otofl5 0x1b4 otbs5 0x1b8 otat5 0x1bc outbound translation 6 otsau6 0x1c0 otsal6 0x1c4 oteau6 0x1c8 oteal6 0x1cc otofu6 0x1d0 otofl6 0x1d4 otbs6 0x1d8 otat6 0x1dc table 36: lcsr register group function bits offset crg 31 24 23 16 15 8 7 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 205 80a3020_ma001_08 outbound functions outbound translation 7 otsau7 0x1e0 otsal7 0x1e4 oteau7 0x1e8 oteal7 0x1ec otofu7 0x1f0 otofl7 0x1f4 otbs7 0x1f8 otat7 0x1fc reserved vmebus interrupt acknowledge vmebus iack 1 (viack1) 0x204 viack2 0x208 viack3 0x20c viack4 0x210 viack5 0x214 viack6 0x218 viack7 0x21c rmw vmebus rmw address upper (rmwau) 0x220 vmebus rmw address lower (rmwal) 0x224 vmebus rmw enable (rmwen) 0x228 vmebus rmw compare (rmwc) 0x22c vmebus rmw swap (rmws) 0x230 vmebus control vme master control (vmctrl) 0x234 vmebus control (vctrl) 0x238 vmebus status (vstat) 0x23c pci/x status pci/x control / status (pcsr) 0x240 reserved table 36: lcsr register group function bits offset crg 31 24 23 16 15 8 7 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 206 80a3020_ma001_08 vme filters vme filter vmebus filter (vmefl) 0x250 reserved vme exception vme exception status vmebus exception address upper (veau) 0x260 vmebus exception address lower (veal) 0x264 vmebus exception attributes (veat) 0x268 reserved 0x26c pci/x error pci/x error status error diagnostic pci address upper (edpau) 0x270 error diagnostic pci address lower (edpal) 0x274 error diagnostic pci-x attribute (edpxa) 0x278 error diagnostic pci-x split completion message (edpxs) 0x27c error diagnostic pci attributes (edpat) 0x280 reserved inbound functions inbound translation 0 inbound translation starting address upper 0 (itsau0) 0x300 inbound translation starting address lower 0 (itsal0) 0x304 inbound translation ending address upper 0 (iteau0) 0x308 inbound translation ending address lower (iteal0) 0x30c inbound translation offset upper 0 (itofu0) 0x310 inbound translation offset lower 0 (itofl0) 0x314 inbound translation attribute 0 (itat0) 0x318 reserved 0x31c table 36: lcsr register group function bits offset crg 31 24 23 16 15 8 7 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 207 80a3020_ma001_08 inbound functions inbound translation 1 itsau1 0x320 itsal1 0x324 iteau1 0x328 iteal1 0x32c itofu1 0x330 itofl1 0x334 itat0 0x338 reserved 0x33c inbound translation 2 itsau2 0x340 itsal2 0x344 iteau2 0x348 iteal2 0x34c itofu2 0x350 itofl2 0x354 itat2 0x358 reserved 0x35c inbound translation 3 itsau3 0x360 itsal3 0x364 iteau3 0x368 iteal3 0x36c itofu3 0x370 itofl3 0x374 itat3 0x378 reserved 0x37c table 36: lcsr register group function bits offset crg 31 24 23 16 15 8 7 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 208 80a3020_ma001_08 inbound functions inbound translation 4 itsau4 0x380 itsal4 0x384 iteau4 0x388 iteal4 0x38c itofu4 0x390 itofl4 0x394 itat4 0x398 reserved 0x39c inbound translation 5 itsau5 0x3a0 itsal5 0x3a4 iteau5 0x3a8 iteal5 0x3ac itofu5 0x3b0 itofl5 0x3b4 itat5 0x3b8 reserved 0x3bc inbound translation 6 itsau6 0x3c0 itsal6 0x3c4 iteau6 0x3c8 iteal6 0x3cc itofu6 0x3d0 itofl6 0x3d4 itat6 0x3d8 reserved 0x3dc table 36: lcsr register group function bits offset crg 31 24 23 16 15 8 7 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 209 80a3020_ma001_08 interrupt functions inbound translation 7 itsau7 0x3e0 itsal7 0x3e4 iteau7 0x3e8 iteal7 0x3ec itofu7 0x3f0 itofl7 0x3f4 itat7 0x3f8 reserved 0x3fc inbound translation gcsr gcsr base address upper (gbau) 0x400 gcsr base address lower (gbal) 0x404 gcsr attribute (gcsrat) 0x408 inbound translation crg crg base address upper (cbau) 0x40c crg base address lower (cbal) 0x410 crg attribute (crgat) 0x414 inbound translation cr/csr cr/csr offset upper (crou) 0x418 cr/csr offset lower (crol) 0x41c cr/csr attribute (crat) 0x420 table 36: lcsr register group function bits offset crg 31 24 23 16 15 8 7 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 210 80a3020_ma001_08 interrupt functions inbound translation location monitor location monitor base address upper (lmbau) 0x424 location monitor base address lower (lmbal) 0x428 location monitor attribute (lmat) 0x42c vmebus interrupt control 64-bit counter upper (64bcu) 0x430 64-bit counter lower (64bcl) 0x434 broadcast pulse generator timer (bpgtr) 0x438 broadcast programmable clock timer (bpctr) 0x43c vmebus interrupt control (vicr) 0x440 reserved 0x444 local bus interrupt control interrupt enable (inten) 0x448 interrupt enable out (inteo) 0x44c interrupt status (ints) 0x450 interrupt clear (intc) 0x454 interrupt map 1 (intm1) 0x458 interrupt map 2 (intm2) 0x45c reserved table 36: lcsr register group function bits offset crg 31 24 23 16 15 8 7 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 211 80a3020_ma001_08 dma controller dma controller 0 dma control (dctl0) 0x500 dma status (dsta0) 0x504 dma current source address upper (dcsau0) 0x508 dma current source address lower (dcsal0) 0x50c dma current destination address upper (dcdau0) 0x510 dma current destination address lower (dcdal0) 0x514 dma current link address upper (dclau0) 0x518 dma current link address lower (dclal0) 0x51c dma source address upper (dsau0) 0x520 dma source address lower (dsal0) 0x524 dma destination address upper (ddau0) 0x528 dma destination address lower (ddal0) 0x52c dma source attribute (dsat0) 0x530 dma destination attribute (ddat0) 0x534 dma next link address upper (dnlau0) 0x538 dma next link address lower (dnlal0) 0x53c dma count (dcnt0) 0x540 dma destination broadcast select (ddbs0) 0x544 reserved table 36: lcsr register group function bits offset crg 31 24 23 16 15 8 7 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 212 80a3020_ma001_08 dma controller dma controller 1 dctl1 0x580 dsta1 0x584 dcsau1 0x588 dcsal1 0x58c dcdau1 0x590 dcdal1 0x594 dclau1 0x598 dclal1 0x59c dsau1 0x5a0 dsal1 0x5a4 ddau1 0x5a8 ddal1 0x5ac dsat1 0x5b0 ddat1 0x5b4 dnlau1 0x5b8 dnlal1 0x5bc dcnt1 0x5c0 ddbs1 0x5c4 table 36: lcsr register group function bits offset crg 31 24 23 16 15 8 7 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 213 80a3020_ma001_08 10.4.4 gcsr register group overview table 37: gcsr register group function bits offset gcsr/ crg 31 24 23 16 15 8 7 0 gcsr header device id (devi) vendor id (veni) 0x00/ 0x600 control control and status (gctrl) geographic address (ga) revision id (revid) 0x04/ 0x604 semaphore semaphore0 semaphore1 semaphore2 semaphore3 0x08/ 0x608 semaphore4 semaphore5 semaphore6 semaphore7 0x0c/ 0x60c mail box mbox0 0x10/ 0x610 mbox1 0x14/ 0x614 mbox2 0x18/ 0x618 mbox3 0x1c/ 0x61c
10. registers tsi148 pci/x-to-vme bus bridge user manual 214 80a3020_ma001_08 10.4.5 cr/csr register group overview table 38: cr/csr register group function bits offset cr/csr/ crg 31 24 23 16 15 8 7 0 cr/csr csr cr/csr bit clear (csrbcr) 0x7fff4/ 0xff4 cr/csr bit set (csrbsr) 0x7fff8/ 0xff8 cr/csr base address (cbar) 0x7fffc/ 0xffc
10. registers tsi148 pci/x-to-vme bus bridge user manual 215 80a3020_ma001_08 10.4.6 pcfs register group description this register group represents the pci/x configuration space. this register group can be viewed from pci/x configuration space and from the crg. 10.4.7 vendor id/ device id registers device id register (devi): this is a read-only register that uniquely identifies this particular device. this tsi148 always returns a value of 0x0148. v endor id register (veni): this is a read-only register that identifies the manufacturer of the device. this identifier is allocated by the pci/x special interest group to ensure uniqueness. 0x10e3 has been assigned to tundra and is hard wired as a read-only value. tip in many cases a register represented within the pcfs register group has different read/write characteristics than the same register represented within the crg. generally, the read/write characteristics of the registers within the pcfs register group are strictly limited to the abilities defined by the pci local bus specification (revision 2.2) and pci-x addendum to pci local bus specification (revision 1.0b) . table 39: vendor id/ device id registers register name: devi/veni reset value: 0x014810e3 register offset: pcfs + 0x00 - crg + 0x000 bits 7 6 5 4 3 2 1 0 31:24 devi 23:16 devi 15:8 veni 7:0 veni vendor id/ device id register bits name function type reset by reset value 31:16 devi device id r n/a 0x0148 15:0 veni vendor id r n/a 0x10e3
10. registers tsi148 pci/x-to-vme bus bridge user manual 216 80a3020_ma001_08 10.4.8 command/status registers the status functionality in this register is us ed to record information for pci/x bus related events while the command functionality in this re gister provides course control over the chips ability to generate and respond to pci/x cycles. table 40: command/status register register name: stat/cmmd pci reset value: 0x pci-x reset value: 0x register offset: pcfs + 0x04 - crg + 0x004 bits 7 6 5 4 3 2 1 0 31:24 dpe sigse rcvma rcvta sigta seltim1 seltim0 dped 23:16 fast reserved p66m capl reserved 15:8 reserved serr 7:0 reserved perr reserved mstr memsp iosp command/status register bits name function type reset by pci reset value pci-x reset value 31 dpe detected parity error r/c p/s/l 0 0 30 sigse signaled system error r/c p/s/l 0 0 29 rcvma received master abort r/c p/s/l 0 0 28 rcvta received target abort r/c p/s/l 0 0 27 sigta signalled target abort r n/a 0 0 26 seltim1 devsel timing r n/a 0 0 25 seltim0 devsel timing r n/a 1 1 24 dped data parity error detected r/c p/s/l 0 0 23 fast fast back-to-back capable r n/a 1 0 22 reserved n/a r n/a 0 0 21 p66m pci 66 mhz r n/a 1 1 20 capl capabilities list r n/a 1 1 19:9 reserved n/a r n/a 0 0
10. registers tsi148 pci/x-to-vme bus bridge user manual 217 80a3020_ma001_08 dpe (data parity error): this bit is set whenever a parity error is detected, even if the parity error response is disabled (see bit perr in the section 10.4.8 on page 216 ). it is cleared by writing it to 1 - writing a 0 has no effect. sigse (signaled system error): this bit is set whenever the tsi148 asserts serr_. the register is cleared by writing it to 1 while writing a 0 has no effect. rcvma (received master abort): this bit is set when a master transaction (except for special cycles) is terminated by a master-abort. it is cleared by writing it to 1; writing a 0 has no effect. rcvta (received target abort): this bit is set when a master transaction is terminated by a target-abort. the register is cleared by writing it to 1 while writing a 0 has no effect. sigta (signalled target abort): the tsi148 does not generate a target abort, therefore this bit is hard-wired to a logic 0. seltim (devsel timing): this field indicates that tsi148 always asserts devsel_ as a medium responder. dped (data parity error detected): this bit is set when three conditions are met: 1. the tsi148 asserted perr_ itself or observed perr_ asserted 2. the tsi148 was the pci/x master for the transfer in which the error occurred 3. the perr bit is set. this bit is cleared by writing it to 1; writing a 0 has no effect. fast (fast back-to-back capable): this bit indicates that the tsi148 is capable of accepting fast back-to-back transactions with different targets. 8 serr system error enable r/w p/s/l 0 0 7 reserved n/a r n/a 0 0 6 perr parity error response r/w p/s/l 0 0 5:3 reserved n/a r n/a 0 0 2 mstr bus master enable r/w p/s/l 0 0 1 memsp memory space enable r/w p/s/l 0 0 0 iosp i/o space enable r n/a 0 0 command/status register bits name function type reset by pci reset value pci-x reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 218 80a3020_ma001_08 p66m (pci 66 mhz): this bit indicates the tsi148 is capable of supporting a 66.67 mhz pci/x bus. capl (capabilities list): this bit indicates that the addres s at offset 0x34 is a pointer for a new capabilities linked list. serr (system error enable): this bit enables the serr_ output pin. if cleared, the tsi148 never drives serr_. if set, the tsi148 drives serr_ active when a system error is detected. perr (parity error response): this bit enables the perr_ output pin. if cleared, the tsi148 never drives perr_. if set, the tsi148 driv es perr_ active when a data parity error is detected. mstr (bus master enable): if set, the tsi148 may act as a master on pci/x. if cleared, the tsi148 may not act as a master. memsp (memory space enable): if set, the tsi148 does respond to pci/x memory space accesses when appropriate. if cleared, the tsi148 does not respond to pci/x memory space accesses. iosp (i/o space enable): this bit is hard wired to zero. the tsi148 does not respond to pci/x i/o space accesses.
10. registers tsi148 pci/x-to-vme bus bridge user manual 219 80a3020_ma001_08 10.4.9 revision id / class code registers bclas ( base class code register): this is a read-only register that identifies the base class code of the tsi148 . the tsi148 always returns a value of 0x06. sclas ( sub class code register): this is a read-only register that identifies the sub class code of the tsi148. the tsi148 always returns a value of 0x80. pic ( program interface code register): this is a read-only regi ster that identifies the program interface code of the tsi148. the tsi148 always returns a value of 0x00. revi (revision id register) : this is a read-only register that identifies the tsi148 revision level. table 41: revision id / class code register register name: clas/revi reset value: 0x register offset: pcfs + 0x08 - crg + 0x008 bits 7 6 5 4 3 2 1 0 31:24 bclas 23:16 sclas 15:8 pic 7:0 revi revision id / class code register bits name function type reset by reset value 31:24 bclas base class code register r n/a 0x06 23:16 sclas sub class code register r n/a 0x80 15:8 pic program interface code register r n/a 0x00 7:0 revi revision id register r n/a 0x01
10. registers tsi148 pci/x-to-vme bus bridge user manual 220 80a3020_ma001_08 10.4.10 cache line size / master latency timer / header type registers clsz ( cache line): these bits represent the number of 32-bit words that define a cache-line. a cache line is defined as 32-bytes, which is eight 32-bit words. if a value of 0x08 is written to this register, the value is retained . if any other value is written to this register, a value of 0x00 is retained. the pci local bus specification (revision 2.2) states that this register must power up to all zeros. the tsi148 does not generate memory write and invalidate command. this register is only used to inform other pci/x masters of the supported cache-line size for read, read line, and read multiple commands. mlat ( master latency timer): these bits represent the value used for the master latency timer. the master latency timer specifies the amount of pci/x clock periods that tsi148 can remain on the pci/x bus during burst cycles after gnt_ is taken away. the mlat bits provides a minimum granularity of the 8 pci/x clock periods. table 42: cache line size / master latency timer / header type register register name: head/mlat/clsz pci reset value: 0x pci-x reset value: 0x register offset: pcfs + 0x0c - crg + 0x00c bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 head 15:8 mlat 7:0 clsz cache line size / master latency timer / header type register bits name function type reset by pci reset value pci-x reset value 31:24 reserved n/a r n/a 0x00 0x00 23:16 head header type r n/a 0x00 0x00 15:08 mlat master latency timer r/w p/s/l 0x00 0x40 7:0 clsz cache line size r/w p/s/l 0x00 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 221 80a3020_ma001_08 the pci local bus specification (revision 2.2) states that this register must power up to all zeros in pci mode. severe performance degradation may result if this register is not adjusted from the reset value. this register is initialized to 0x40 in pci-x mode. head ( header type): this is a read-only register that identifies this tsi148 as a single function device.
10. registers tsi148 pci/x-to-vme bus bridge user manual 222 80a3020_ma001_08 10.4.11 memory base address lower register the mbarl register controls access to the combined register group (crg). basel ( base address lower): these bits define the memory space base address of the (crg). pre ( prefetch ): this is a read-only register that refl ects the ability of the function to support prefetching. the crg does not support prefetching. mtypx ( memory type): these bits are hard-wired to 10b to indicate that the crg can be located anywhere in the 64-bit address space. io/mem ( i/o space indicator): this bit is set to a zero indi cating this resource is a memory space resource. the crg can only be mapped to memory space. table 43: memory base address lower register register name: mbar reset value: 0x register offset: pcfs + 0x10 - crg + 0x010 bits 7 6 5 4 3 2 1 0 31:24 basel 23:16 basel 15:8 basel reserved 7:0 reserved pre mtyp1 mtyp0 io/mem memory base address lower register bits name function type reset by reset value 31:12 basel base address lower r/w p/s/l 0x00 11:4 reserved n/a r n/a 0x00 3 pre prefetch r n/a 0x00 2 mtyp1 memory type r n/a 0x01 1 mtyp0 memory type r n/a 0x00 0 io/mem i/o space indicator r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 223 80a3020_ma001_08 10.4.12 memory base address upper register the mbaru register controls access to the combined register group (crg) . baseu ( base address upper): these bits define the memory space base address of the (crg). table 44: memory base address upper register register name: mbaru reset value: 0x register offset: pcfs + 0x14 - crg + 0x014 bits 7 6 5 4 3 2 1 0 31:24 baseu 23:16 baseu 15:8 baseu 7:0 baseu memory base address upper register bits name function type reset by reset value 31:0 baseu base address upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 224 80a3020_ma001_08 10.4.13 subsystem vendor id/ subsystem id registers subi ( subsystem id): this is a read-only register from within the pci/x configuration space (pcfs), and may be written at any time from within the combined register group (crg). the subi register provides a second leve l of identification for this particular device. this register defaults to 0x0000 upon the release of reset. subv ( subsystem vendor id): this is a read-only register from within the pci/x configuration space, and may be written at a ny time from within the combined register group. the subv register provides a second level of identification for the manufacturer of this particular device. this identifier is allocated by the pci/x special interest group to ensure uniqueness. this register is configured to the tundra value of 0x10e3 upon release of reset. table 45: subsystem vendor id/ subsystem id register register name: subi/subv reset value: 0x register offset: pcfs + 0x2c - crg + 0x02c bits 7 6 5 4 3 2 1 0 31:24 subi 23:16 subi 15:8 subv 7:0 subv subsystem vendor id/ subsystem id register bits name function pcfs space type crg space type reset by reset value 31:16 subi subsystem id r r/w p/s/l 0x0000 15:0 subv subsystem vendor id r r/w p/s/l 0x10e3
10. registers tsi148 pci/x-to-vme bus bridge user manual 225 80a3020_ma001_08 10.4.14 capabilities pointer register this register contains the offset to the first entry in the capabilities list. table 46: capabilities pointer register register name: capp reset value: 0x register offset: pcfs + 0x3c - crg + 0x03c bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:8 reserved 7:0 capp capabilities pointer register bits name function type reset by reset value 31:8 reserved n/a r n/a 0x00 15:0 capp capabilities pointer r n/a 0x40
10. registers tsi148 pci/x-to-vme bus bridge user manual 226 80a3020_ma001_08 10.4.15 interrupt line/interrupt pin/minimum grant/maximum latency registers mxla ( maximum latency): this is a read-only register from the pci/x configuration space, and may be written at any time from within the combined register group. the mxla register specifies how often access to the pci/ x bus is required. the value is presented in units of 0.25 us. this register defaults 0x00 fo llowing the release of reset which indicates that there are no particular latency requirements. mngn ( minimum grant): this is a read-only register from the pci/x configuration space, and may be written at any time from within the combined register group. the mngn register specifies how long of a burst period is required. the value is presented in units of 0.25 us. this register defaults to 0x00 following the release of reset which indicates that there are no particular grant requirements. table 47: interrupt line/interrupt pin/minimum grant/maximum latency register register name: mxla/mngn/intp/intl reset value: 0x register offset: pcfs + 0x3c - crg + 0x03c bits 7 6 5 4 3 2 1 0 31:24 mxla 23:16 mngn 15:8 intp 7:0 intl interrupt line/interrupt pin/minimum grant/maximum latency register bits name function pcfs space type crg space type reset by reset value 31:24 mxla maximum latency r r/w p/s/l 0x00 23:16 mngn minimum grant r r/w p/s/l 0x00 15:8 intp interrupt pin r see table 48 p/s/l 0x01 7:0 intl interrupt line r/w r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 227 80a3020_ma001_08 intp ( interrupt pin): this register contains information pertaining to the pci/x interrupt pin being driven. this register is read-only from the pci/x configuration space, and may be written at any time from within the combined register group. table 48 shows which bits in the intp field are read only from within the crg register group and which bits are both read and write. this tsi148 is a single functio n device and is limited by the pci local bus specification (revision 2.2) to only driving inta_. in special cases, this tsi148 can be programmed to drive any one of the four pci/x interrupts. this register may be modified to show which of the four interrupt lines is being driven. the recommended encoding of this field is shown in table 49 : table 48: crg space type register bit intp field 15 r 14 r 13 r 12 r 11 r 10 r/w 9r/w 8r/w table 49: intp int x encoding intp pci/x interrupt 0x000 undefined 0x001 inta_ 0x010 intb_ 0x011 intc_ 0x100 intd_ 0x101 - 0x111 undefined
10. registers tsi148 pci/x-to-vme bus bridge user manual 228 80a3020_ma001_08 note that the selection of a particular intx lin e is handled by the interrupt map registers. the intp register is for reference only and does not control any hardware. intl ( interrupt line): this register contains interrupt routing information. this tsi148 does not have any hardware associated with this register, and is not affected by the contents of this register. initialization software can write interrupt routing information into this register during system configuration.
10. registers tsi148 pci/x-to-vme bus bridge user manual 229 80a3020_ma001_08 10.4.16 pci-x capabilities register table 50: pci-x capabilities register register name: pcixcap reset value: 0x register offset: pcfs + 0x40 - crg + 0x040 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved most mmrbc ero dpere 15:8 ncapp 7:0 capid pci-x capabilities register bits name function pcfs space type reset by reset value 31:23 reserved n/a r n/a 0x00 22:20 most maximum outstanding split transactions r/w p/s/l 010b 19:18 mmrbc maximum memory read byte count r/w p/s/l 0x00 17 ero enable relaxed ordering r n/a 0x00 16 dpere data parity recovery enable r/w p/s/l 0x00 15:8 ncapp next capabilities pointer r n/a 0x00 7:0 capid capabilities id r n/a 0x07
10. registers tsi148 pci/x-to-vme bus bridge user manual 230 80a3020_ma001_08 most ( maximum outstanding split transactions): three outstanding split transactions are supported. changing the value of this field decreases the maximum number of outstanding split transactions: mmrbc (maximum memory read byte count): this field sets the maximum byte count the device uses when initiating a read sequence with one of the burst memory commands: ero (enable relaxed ordering): the tsi148 does not support relaxed ordering. when this field is read, the value is always zero. dpere (data parity recovery enable): when this bit is set and the device is in pci-x mode, the tsi148 does not assert serr_ when th e master data parity error bit is set. when this bit is clear and the device is in pci-x mode, the tsi148 asserts serr_ when the master data parity error bit is set. ncapp (next capabilities pointer): this field points to the next item in the capabilities list. a zero indicates that this is the final item in the list. capid (capabilities id): this field defines this item in the capabilities list as a pci-x register set. when this field is read, the value is always 0x07. table 51: most encoding most maximum outstanding 000b 1 001b 2 010b 3 011b - 111b 3 table 52: mmrbc encoding mmrbc byte count 00b 512 01b 1024 10b 2048 11b 4096
10. registers tsi148 pci/x-to-vme bus bridge user manual 231 80a3020_ma001_08 10.4.17 pci-x status register rscem ( received split completion error message): this bit is set if a split completion message is received w ith the split completion error attribut e set. this bit is cleared by table 53: pci-x status register register name: pcixstat reset value: 0x register offset: pcfs + 0x44 - crg + 0x044 bits 7 6 5 4 3 2 1 0 31:24 reserved rscem dmcrs dmost 23:16 dmost dmmrc dc usc scd 133c 64d 15:8 bn 7:0 dn fn pci-x status register bits name function pcfs space type reset by reset value 31:30 reserved n/a r n/a 0x00 29 rscem received split completion error message r p/s/l 0x00 28:26 dmcrs designed maximum cumulative read size r/c n/a 0x01 25:23 dmost designed maximum outstanding split transactions r n/a 0x02 22:21 dmmrc designed maximum memory read byte count r n/a 0x03 20 dc device complexity r n/a 0x01 19 usc unexpected split completion r/c p/s/l 0x00 18 scd split completion discarded r/c p/s/l 0x00 17 133c 133 mhz capable r n/a 0x01 16 64d 64-bit device r n/a 0x01 15:8 bn bus number r n/a 0xff 7:3 dn device number r n/a 0x1f 2:0 fn function number r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 232 80a3020_ma001_08 writing a one to it. dmcrs ( designed maximum cumu lative read size): these bits depend on the value of the mmrbc field (see table 10.4.16 on page 229 ) as shown in the following table: dmost (d esigned maximum outstanding split transactions): these bits always return a value of two. the tsi148 can have up to three outstanding read transactions. dmmrc (d esigned maximum memory read byte count): these bits always return a value of three indicating that the tsi148 has a maximum memory read byte count of 4096 bytes. dc (de vice complexity): this bit always returns a value of one indicating that the tsi148 is a bridge device. usc ( unexpected split completion): this bit is set if an unexpected split completion is received. this bit is cleared by writing a one to it. scd ( split completion discarded): this bit is set if a split completion is discarded because the requestor would not accept it. this bit is cleared by writing a one to it. 133c ( 133 mhz capable): this bit always returns a value of one indicating that the tsi148 is capable of operating at 133 mhz. 64d ( 64-bit device): this bit always returns a value of one indicating that the tsi148 has a 64-bit ad interface. bn ( bus number): this field indicates the number of the bus segment the tsi148 is attached to. during the attribute phase of a configuration write, the bus number is latched from ad[7:0]. this number is used as part of the requester id and completer id. dn ( device number): this field indicates the chips device number. during the address phase of a configuration write, the device number is latched from ad[15:11]. this number is used as part of the requester id and completer id. table 54: dmcrs encoding mmrbc dmrcs 00b 001b 01b 010b 10b 011b 11b 100b
10. registers tsi148 pci/x-to-vme bus bridge user manual 233 80a3020_ma001_08 fn ( function number): this field indicates the number of this function and always returns a value of zero. this number is used as part of the requester id and completer id.
10. registers tsi148 pci/x-to-vme bus bridge user manual 234 80a3020_ma001_08 10.4.18 lcsr register group description this section defines the local control and status registers. 10.4.19 outbound translation starting address upper (0-7) registers the outbound translation starting address upper registers (otsau0-otsau7) contain address information associated with the mapping of pci/x memory space to vmebus space. the outbound pci/x address is decoded when the pci/x address is greater than or equal to the start address and less than or equal to the end address. stau ( start address upper): this field determines the start address of a particular memory area on the pci/x bus which is used to access vmebus resources. the value of this field is compared with a63-a32 of the pci/x bus address. table 55: outbound translation starting address upper (0-7) register register name: otsaux reset value: 0x00000000 register offset: otsau0: crg + 0x100 otsau1: crg + 0x120 otsau2: crg + 0x140 otsau3: crg + 0x160 otsau4: crg + 0x180 otsau5: crg + 0x1a0 otsau6: crg + 0x1c0 otsau7: crg + 0x1e0 bits 7 6 5 4 3 2 1 0 31:0 stau outbound translation starting address upper (0-7) register bits name function pcfs space type reset by reset value 31:0 stau start address upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 235 80a3020_ma001_08 10.4.20 outbound translation starting address lower (0-7) registers the outbound translation starting address lower registers (otsal0-otsal7) contain address information associated with the mapping of pci/x memory space to vmebus space. the outbound pci/x address is decoded when the pci/x address is greater than or equal to the start address and less than or equal to the end address. stal ( start address lower): this field determines the start address of a particular memory area on the pci/x bus which is used to access vmebus resources. the value of this field is compared with a31-a16 of the pci/x bus address. table 56: outbound translation starting address lower (0-7) register register name: otsalx reset value: 0x00000000 register offset: otsal0: crg + 0x104 otsal1: crg + 0x124 otsal2: crg + 0x144 otsal3: crg + 0x164 otsal4: crg + 0x184 otsal5: crg + 0x1a4 otsal6: crg + 0x1c4 otsal7: crg + 0x1e4 bits 7 6 5 4 3 2 1 0 31:16 stal 15:0 reserved outbound translation starting address lower (0-7) register bits name function pcfs space type reset by reset value 31:16 stal start address lower r/w p/s/l 0x00 15:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 236 80a3020_ma001_08 10.4.21 outbound translation ending address upper (0-7) registers the outbound translation ending address u pper registers (oteau0-oteau7) contain address information associated with the mapping of pci/x memory space to vmebus space. the outbound pci/x address is decoded when the pci/x address is greater than or equal to the start address and less than or equal to the end address. endu ( end address upper): this field determines the end address of a particular memory area on the pci/x bus which is used to access vmebus resources. the value of this field is compared with a63-a32 of the pci/x bus address. table 57: outbound translation ending address upper (0-7) register register name: oteaux reset value: 0x00000000 register offset: oteau0: crg + 0x108 oteau1: crg + 0x128 oteau2: crg + 0x148 oteau3: crg + 0x168 oteau4: crg + 0x188 oteau5: crg + 0x1a8 oteau6: crg + 0x1c8 oteau7: crg + 0x1e8 bits 7 6 5 4 3 2 1 0 31:0 endu outbound translation ending address upper (0-7) register bits name function pcfs space type reset by reset value 31:0 endu end address upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 237 80a3020_ma001_08 10.4.22 outbound translation ending address lower (0-7) registers the outbound translation ending address lo wer registers (oteal0-oteal7) contain address information associated with the mapping of pci/x memory space to vmebus space. the outbound pci/x address is decoded when the pci/x address is greater than or equal to the start address and less than or equal to the end address. endl ( end address lower): this field determines the end address of a particular memory area on the pci/x bus which is used to access vmebus resources. the value of this field is compared with a31-a16 of the pci/x bus address. table 58: outbound translation e nding address lower (0-7) register register name: otealx reset value: 0x00000000 register offset: oteal0: crg + 0x10c oteal1: crg + 0x12c oteal2: crg + 0x14c oteal3: crg + 0x16c oteal4: crg + 0x18c oteal5: crg + 0x1ac oteal6: crg + 0x1cc oteal7: crg + 0x1ec bits 7 6 5 4 3 2 1 0 31:16 endl 15:0 reserved outbound translation starting address lower (0-7 register bits name function pcfs space type reset by reset value 31:16 endl end address lower r/w p/s/l 0x00 15:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 238 80a3020_ma001_08 10.4.23 outbound translation offset upper (0-7) registers the outbound translation offset upper regi sters (otofu0-otofu7) contain information associated with the mapping of pci/x memory space to vmebus space. offu ( offset upper): this field contains the offset that is added to pci/x address lines a63-a32 to create the vmebus address. table 59: outbound translation offset upper (0-7) register register name: otofux reset value: 0x00000000 register offset: otofu0: crg + 0x110 otofu1: crg + 0x130 otofu2: crg + 0x150 otofu3: crg + 0x170 otofu4: crg + 0x190 otofu5: crg + 0x1b0 otofu6: crg + 0x1d0 otofu7: crg + 0x1f0 bits 7 6 5 4 3 2 1 0 31:0 offu outbound translation offset upper (0-7) register bits name function pcfs space type reset by reset value 31:0 offu offset upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 239 80a3020_ma001_08 10.4.24 outbound translation offset lower (0-7) registers the outbound translation offset lower re gisters (otofl0-otofl7) contain address information associated with the mapping of pci/x memory space to vmebus space. offl ( offset lower): this field contains the offset that is added to pci/x address lines a31-a16 to create the vmebus address. table 60: outbound translation offset lower (0-7) register register name: otoflx reset value: 0x00000000 register offset: otofl0: crg + 0x114 otofl1: crg + 0x134 otofl2: crg + 0x154 otofl3: crg + 0x174 otofl4: crg + 0x194 otofl5: crg + 0x1b4 otofl6: crg + 0x1d4 otofl7: crg + 0x1f4 bits 7 6 5 4 3 2 1 0 31:16 offl 15:0 reserved outbound translation starting address lower (0-7) register bits name function pcfs space type reset by reset value 31:16 offl offset lower r/w p/s/l 0x00 15:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 240 80a3020_ma001_08 10.4.25 outbound translation 2esst broadcast select (0-7) registers the outbound translation 2esst broadcast select registers (otbs0-otbs7) contain information associated with the mapping of pci/x memory space to vmebus space. the 2esst protocol supports broadcast transfers which allow a master to write the same data to multiple slaves with a single transfer. wh en this functionality is used, this register determines which vmebus slaves particip ates and receives the broadcast data. 2ebs (2esst broadcast select): this register contains the 2esst broadcast select bits. each bit corresponds to one of the 21 possible slaves. the 2esst master broadcasts this field during address phase three. register bit 20 corresponds to vmebus address line a21 and register bit 0 corresponds to vmebus address line a1. table 61: outbound translation 2esst broadcast select (0-7) register register name: otbsx reset value: 0x00000000 register offset: otbs0: crg + 0x118 otbs1: crg + 0x138 otbs2: crg + 0x158 otbs3: crg + 0x178 otbs4: crg + 0x198 otbs5: crg + 0x1b8 otbs6: crg + 0x1d8 otbs7: crg + 0x1f8 bits 7 6 5 4 3 2 1 0 31:21 reserved 20:0 2ebs outbound translation 2esst broadcast select (0-7) register bits name function pcfs space type reset by reset value 31:21 reserved n/a r n/a 0x00 20:0 2ebs 2esst broadcast select r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 241 80a3020_ma001_08 10.4.26 outbound translation attribute (0-7) registers the outbound translation attribute regist ers (otat0-otat7) contain information associated with the mapping of pci/x memory space to vmebus space . table 62: outbound translation attribute (0-7) register register name: otatx reset value: 0x00000000 register offset: otat0: crg + 0x11c otat1: crg + 0x13c otat2: crg + 0x15c otat3: crg + 0x17c otat4: crg + 0x19c otat5: crg + 0x1bc otat6: crg + 0x1dc otat7: crg + 0x1fc bits 7 6 5 4 3 2 1 0 31:24 en reserved 23:16 reserved mrpfd pfs1 pfs0 15:8 reserved 2esstm2 2esstm1 2esstm0 tm2 tm1 tm0 7:0 dbw1 dbw0 sup pgm admode3 admode2 admode1 admode0 outbound translation attr ibute (0-7) register bits name function pcfs space type reset by reset value 31 en enable r/w p/s/l 0x00 30:19 reserved n/a r n/a 0x00 18 mrpfd memory read prefetch disable r/w p/s/l 0x00 17 pfs1 prefetch size r/w p/s/l 0x00 16 pfs0 prefetch size r/w p/s/l 0x00 15:14 reserved n/a r n/a 0x00 13 2esstm2 2esst mode r/w p/s/l 0x00 12 2esstm1 2esst mode r/w p/s/l 0x00 11 2esstm0 2esst mode r/w p/s/l 0x00 10 tm2 transfer mode r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 242 80a3020_ma001_08 en ( enable): if set, the corresponding outbound translation function is enabled. mrpfd ( memory read prefetch disable): if set, prefetching is disabled for all memory read commands. if cleared, a cache line is prefetched when a pci/x bus memory read burst is received. pfs ( prefetch size): this field sets the data read prefetch size for pci/x bus read multiple commands. 9 tm1 transfer mode r/w p/s/l 0x00 8 tm0 transfer mode r/w p/s/l 0x00 7 dbw1 vmebus data bus width r/w p/s/l 0x00 6 dbw0 vmebus data bus width r/w p/s/l 0x00 5 sup vmebus supervisory mode r/w p/s/l 0x00 4 pgm vmebus program mode r/w p/s/l 0x00 3 admode3 address mode r/w p/s/l 0x00 2 admode2 address mode r/w p/s/l 0x00 1 admode1 address mode r/w p/s/l 0x00 0 admode0 address mode r/w p/s/l 0x00 table 63: prefetch size pfs prefetch size 00b 2 cache lines 01b 4 cache lines 10b 8 cache lines 11b 16 cache lines outbound translation attr ibute (0-7) register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 243 80a3020_ma001_08 2esstm ( 2esst mode): this field defines the 2esst transfer rate. tm ( transfer mode ): this field defines the vmebus transfer mode. dbw ( vmebus data bus width): these bits define the maximum data bus width for vmebus transfers initiated by the corresponding outbound translation function. these bits apply to sct and blt transfers. mblt, 2evme and 2esst transfers are always 64-bit. table 64: 2esst transfer rate 2esstm transfer rate 000b 160 mb/s 001b 267 mb/s 010b 320 mb/s 011b-111b reserved table 65: vmebus transfer mode tm transfer mode 000b sct 001b blt 010b mblt 011b 2evme 100b 2esst 101b 2esst broadcast 110b reserved 111b reserved table 66: vmebus data bus width dbw data bus width 00b 16 bit 01b 32 bit 10b reserved 11b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 244 80a3020_ma001_08 sup ( vmebus supervisory mode): when this bit is set the am code indicates supervisory access, when required. when this bit is cl eared the am code indicates non-privileged access. pgm ( vmebus program mode): when this bit is set the am code indicates program access. when this bit is cleared the am code indicates data access. amode ( address mode): this field defines the vmebus address mode. when the user1-user4 modes are used, the am[1] bit is defined by the sup bit and the am[0] bit is defined by the pgm bit. table 67: vmebus address mode amode address mode 0000b a16 0001b a24 0010b a32 0011b reserved 0100b a64 0101b cr/csr 0110b reserved 0111b reserved 1000b user1 (am 0100xxb) 1001b user2 (am 0101xxb) 1010b user3 (am 0110xxb) 1011b user4 (am 0111xxb) 1100b reserved 1101b reserved 1110b reserved 1111b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 245 80a3020_ma001_08 10.4.27 vmebus iack (1-7) registers reading these registers causes an interrupt acknowledge cycle on the vmebus. a 32-bit read of these registers causes a 32-bit iack cycle on the vmebus. a 16-bit read of these registers causes a 16-bit iack cycle on the vmebus. an 8-bit read of these registers causes an 8-bit iack cycle on the vmebus. sinc e most vmebus interrupters support 8-bit iack cycles, byte reads from offset three should be used to retrieve the interrupt vector. writes to this register are ignored. table 68: vmebus iack (1-7) register register name: viackx reset value: 0x xxxxxxxx register offset: viack1: crg + 0x204 viack2: crg + 0x208 viack3: crg + 0x20c viack4: crg + 0x210 viack5: crg + 0x214 viack6: crg + 0x218 viack7: crg + 0x21c bits 7 6 5 4 3 2 1 0 31:0 viack vmebus iack (1-7) register bits name function pcfs space type reset by reset value 31:0 viack vmebus iack r n/a 0x xx
10. registers tsi148 pci/x-to-vme bus bridge user manual 246 80a3020_ma001_08 10.4.28 vmebus read-modify-write (rmw) address upper register this register defines the upper bits (63:32) of the pci/x bus address for the rmw cycle. refer to section 2.5 on page 79 for more information on rmw cycles. table 69: vmebus rmw address upper register register name: rmwau reset value: 0x00000000 register offset: crg + 0x220 bits 7 6 5 4 3 2 1 0 31:0 rmwau vmebus rmw address upper register bits name function pcfs space type reset by reset value 31:0 rmwau vmebus rmw address upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 247 80a3020_ma001_08 10.4.29 vmebus rmw address lower register this register defines the lower bits (31:2) of the pci/x bus address for the rmw cycle. table 70: vmebus rmw address lower register register name: rmwal reset value: 0x00000000 register offset: crg + 0x224 bits 7 6 5 4 3 2 1 0 31:0 rmwal vmebus rmw address lower register bits name function pcfs space type reset by reset value 31:0 rmwal vmebus rmw address lower r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 248 80a3020_ma001_08 10.4.30 vmebus rmw enable register this register defines the bits which are invol ved in the compare and swap operation of the rmw cycle. table 71: vmebus rmw enable register register name: rmwen reset value: 0x00000000 register offset: crg + 0x228 bits 7 6 5 4 3 2 1 0 31:0 rmwen vmebus rmw enable register bits name function pcfs space type reset by reset value 31:0 rmwen vmebus rmw enable r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 249 80a3020_ma001_08 10.4.31 vmebus rmw compare register this register defines the bits which are co mpared with the data read from the vmebus. table 72: vmebus rmw compare register register name: rmwc reset value: 0x00000000 register offset: crg + 0x22c bits 7 6 5 4 3 2 1 0 31:0 rmwc vmebus rmw compare register bits name function pcfs space type reset by reset value 31:0 rmwc vmebus rmw compare r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 250 80a3020_ma001_08 10.4.32 vmebus rmw swap register this register defines the bits which are written to the vmebus when the compare is successful. table 73: vmebus rmw swap register register name: rmws reset value: 0x00000000 register offset: crg + 0x230 bits 7 6 5 4 3 2 1 0 31:0 rmws vmebus rmw swap register bits name function pcfs space type reset by reset value 31:0 rmws vmebus rmw swap r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 251 80a3020_ma001_08 10.4.33 vme master control register the vme master control registers gives the user various control mechanisms on how tsi148 behaves on the vmebus as a master. the va rious data throttling methods are used by the tsi148 vme master in all cases when tsi148 is master on the vmebus including dma accesses. table 74: vme master control register register name: vmctrl reset value: 0x register offset: crg + 0x234 bits 7 6 5 4 3 2 1 0 31:24 reserved vsa vs dhb dwb 23:16 reserved rmwen reserved a64ds 15:8 reserved vtoff reserved vton 7:0 reserved vrel vfair vreql vme master control register bits name function pcfs space type reset by reset value 31:28 reserved n/a r n/a 0x00 27 vsa vmebus stop acknowledge r - 0x00 26 vs vmebus stop r/w p/s/l 0x00 25 dhb device has bus r - 0x00 24 dwb device wants bus r/w p/s/l 0x00 23:22 reserved n/a r n/a 0x00 20 rmwen rmw enable r/w p/s/l 0x00 19:17 reserved n/a r n/a 0x00 16 a64ds a64 data strobes r/w p/s/l 0x00 15 reserved n/a r n/a 0x00 14:12 vtoff vme master time off r/w p/s/l 0x00 11 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 252 80a3020_ma001_08 vsa ( vmebus stop acknowledge): when this bit is set, the vme master has obtained mastership of the vmebus in response to th e vs request. this bit is not set if the vme master has obtained vmebus ow nership for any other reason. vs ( vmebus stop): when this bit is set, the tsi148 requests the vmebus. when vmebus ownership has been obtained, the vsa bit is se t. vmebus ownership is maintained until the vs bit is cleared. while the vs bit is set, the pci/x to vmebus channel and dma controllers are prevented for accessing the vmebus. this bit is used to ensure that the vmebus is idle before the lreset bit is set. this bit is cleared and the vme bus released when the lrsti_ signal is received. dhb ( device has bus): when this bit is set, the vme mast er has obtained mastership of the vmebus in response to the dwb request. this bit is not set if the vme master has obtained vmebus ownership for any other reason. dwb ( device wants bus): when this bit is set, the vm e master requests the vmebus. when vmebus ownership has been obtained, the dhb bit is set. vmebus ownership is maintained until the dwb bit is cleared. while the dwb bit is set, the pci/x to vmebus channel and dma controllers may access the vmebus. rmwen ( rmw enable): if set, the vme master rmw function is enabled. if cleared, the vme master rmw function is disabled. a64ds (a64 data strobes): if set, the vme master asserts both the ds0_ and ds1_ signals during an a64 address phase. if cleared, the vme master asserts the data strobes based on the following data phase. 10:8 vton vme master time on r/w p/s/l 0x00 7:5 reserved n/a r n/a 0x00 4:3 vrel vme master release mode r/w p/s/l 0x00 2 vfair vme master fair mode r/w p/s/l 0x00 1:0 vreql vme master request level r/w p/s/l 11b vme master control register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 253 80a3020_ma001_08 vtoff (vme master time off): these bits define the time the vme master must wait before re-requesting the vmebus. vton (vme master time on): these bits define the time the vme master is allowed to spend on the vmebus. the time on timer is defined in microseconds for the sct, blt and mblt protocols. the time on timer is defined in bytes for the 2evme and 2esst protocols once the tsi148 vme master satisfies vton it can then access the vmebus again based on the value programmed for vtoff. table 75: vme master time off vtoff time 000b 0 s 001b 1 s 010b 2 s 011b 4 s 100b 8 s 101b 16 s 110b 32 s 111b 64 s table 76: vme master time on vton time count 000b 4 s 128 bytes 001b 8 s 128 bytes 010b 16 s 128 bytes 011b 32 s 256 bytes 100b 64 s 512 bytes 101b 128 s 1024 bytes 110b 256 s 2048 bytes 111b 512 s 4096 bytes
10. registers tsi148 pci/x-to-vme bus bridge user manual 254 80a3020_ma001_08 vrel (vme master release mode): these bits define the vmebus release modes for the vmebus interface. vfair (vme master fair mode): if set, the vmebus requester operates in fair mode. if cleared, the vmebus requester operates in normal mode. vreql (vme master request level): these bits define the vmebus request level for the vme master. table 77: vme master release mode vrel mode 00b time on or done 01b (time on and req) or done 10b (time on and bclr) or done 11b (time on or done) and req
10. registers tsi148 pci/x-to-vme bus bridge user manual 255 80a3020_ma001_08 10.4.34 vmebus control register table 78: vmebus control register register name: vctrl reset value: 0x00000000 register offset: crg + 0x238 bits 7 6 5 4 3 2 1 0 31:24 reserved dlt 23:16 reserved nelbb reserved sreset lreset 15:8 sfailai reserved bid 7:0 atoen robin reserved gto vmebus control register bits name function pcfs space type reset by reset value 31 reserved n/a r/w n/a 0x00 30:28 reserved n/a r n/a 0x00 27:24 dlt deadlock timer r/w p/s/l 0x00 23:21 reserved n/a r n/a 0x00 20 nelbb no early release of bus busy r/w p/s 0x00 19:18 reserved n/a r n/a 0x00 17 sreset system reset s - 0x00 16 lreset local reset s - 0x00 15 sfailai system fail auto slot id r/w p/s 0x xx 14:13 reserved n/a r n/a 0x00 12:8 bid broadcast id r/w p/s/l 0x00 7 atoen arbiter time-out enable r/w p/s 0x00 6 robin round robin mode r/w p/s 0x00 5:4 reserved n/a r n/a 0x00 3:0 gto vme master release mode r/w p/s 4'b1000
10. registers tsi148 pci/x-to-vme bus bridge user manual 256 80a3020_ma001_08 dlt ( deadlock timer): these bits define the time the vm e slave waits after detecting a potential deadlock before asserting the retryo_ signal. nelbb (no early release of bus busy): when this bit is set, the tsi148 asserts bbsyo_ whenever asi_ is asserted. this disables the early release of bus busy function for all vmebus masters. this can sometimes help debug systems when noise is causing arbitration problems. the timer checks only for a potential deadlock. the deadlock condition it monitors is when the tsi148's pci/x to vme write buffers are completely full and a vmebus initiator attempts a read to a pci/x target through the tsi148. this is the only potential deadlock condition this timer monitors. table 79: deadlock timer dlt time 0000b deadlock retry disabled 0001b 16 vclks a a. a vclk is a tsi148 internal clock which is a 133 mhz clock. 0010b 32 vclks 0011b 64 vclks 0100b 128 vclks 0101b 256 vclks 0110b 512 vclks 0111b 1024 vclks 1000b 2048 vclks 1001b 4096 vclks 1010b 8192 vclks 1011b 16384 vclks 1100b 32768 vclks 1101b reserved 1110b reserved 1111b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 257 80a3020_ma001_08 sreset (system reset): when this bit is set, the srst o signal is asserted. this bit is automatically cleared. lreset (local reset): when this bit is set, the lrsto_ signal is asserted. this bit is automatically cleared. before this bit is set, the software should set the vs bit and wait for the vsa bit to be set. sfailai ( sysfail auto slot id): when this bit is set, the sfailo signal is asserted. when this bit is cleared, the sfailo signal is negated. when the auto slot id function is enabled, this bit is set by srsti_. it is cleared automatically when the auto clear mode is selected. otherwise it is cleared by software. bid ( broadcast id): this field defines the broadcast id which is used to receive 2esst broadcast transfers. this field is compared w ith the broadcast slave select bits which are transmitted during address phase three of a 2e sst transfer. a value of one corresponds to address bit one set, a value of two corresponds to address bit two set and so on through a value of 21. if this field is zero, the vme slave does not respond to a 2esst broadcast transfer. atoen ( arbiter time-out enable): when this bit is set, the vmebus arbiter time-out function is enabled. when the time-out function is enabled, the arbiter asserts bbsy* if a bus grant out signal remains asserted for 16 microseconds. this causes the arbiter to re-arbitrate. robin ( round robin): when this bit is set, the vmebus arbiter operates in round robin mode. when this bit is cleared, the vmebus arb iter operates in priority mode. this bit may be set or cleared at any time. gto ( vmebus global time-out): these bits define the vmebus global time-out period. table 80: vmebus global time-out gto time 0000b 8 s 0001b 16 s 0010b 32 s 0011b 64 s 0100b 128 s 0101b 256 s 0110b 512 s 0111b 1024 s 1000b 2048 s
10. registers tsi148 pci/x-to-vme bus bridge user manual 258 80a3020_ma001_08 1001b reserved 1010b reserved 1011b reserved 1100b reserved 1101b reserved 1110b reserved 1111b disabled table 80: vmebus global time-out gto time
10. registers tsi148 pci/x-to-vme bus bridge user manual 259 80a3020_ma001_08 10.4.35 vmebus status register cpurst ( clear power up reset): when this bit is set, the purs ts bit is cleared. this bit always returns zero when read. table 81: vmebus status register register name: vstat reset value: 0x register offset: crg + 0x23c bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:8 cpurst bdfail reserved pursts bdfails sysfls acfails scons 7:0 reserved gap ga vme master control register bits name function pcfs space type reset by reset value 31:16 reserved n/a r n/a 0x00 15 cpurst clear power up reset c n/a 0x00 14 bdfail board fail r/w p/s/l 0x01 13 reserved n/a r n/a 0x00 12 pursts power up reset status r p 0x01 11 bdfails board fail status r n/a 0x01 10 sysfls system fail status r n/a 0x xx 9 acfails ac fail status r n/a 0x xx 8 scons system controller status r p 0x xx 7:6 reserved n/a r n/a 0x00 5 gap geographic address parity r 0x xx 4:0 ga geographic address r n/a 0x xx
10. registers tsi148 pci/x-to-vme bus bridge user manual 260 80a3020_ma001_08 bdfail ( board fail): this is the board fail control bit. when this bit is high, the bdfail_ signal is asserted by the tsi148. when this bit is low, the bdfail_ signal is not asserted by the tsi148. board fail is set by a local bus reset and is cleared by software when the board is ready. pursts ( power up reset status): this bit is set when the pursti_ signal is asserted. it can be cleared by setting the cpurst bit. bdfails ( board fail status): this is the board fail status b it. when this bit is high, the bdfail_ signal is asserted. when this b it is low, the bdfail_ signal is negated. sysfls ( system fail status): this bit indicates the current state of the sfaili_ signal. when this bit is high, the sfaili_ signal is asse rted. when this bit is low, the sfaili_ signal is negated. acfails ( ac fail status): this bit indicates the current state of the acfaili_ signal. when this bit is high, the acfaili_ signal is asserted. when this bit is low, the acfaili_ signal is negated. scons ( system controller status): when this bit is high, the vmebus system controller is enabled. when this bit is low, the vm ebus system controller is not enabled. gap ( geographic address parity): this bit is the parity bit for the geographic address. this bit is inverted from the vmebus gap_ signal. ga ( geographic address): these bits represent the geographic address of the board. these bits are inverted from the vmebus ga[4:0]_ signals.
10. registers tsi148 pci/x-to-vme bus bridge user manual 261 80a3020_ma001_08 10.4.36 pci/x control / status register the pci/x control status register (pcsr) contains the pci/x bus configuration information captured from the pci/x bus on the rising edge of the lrsti_ signal. this information is used to define the mode, clock frequency and bus width. table 82: pci/x control / status register register name: pcsr reset value: 0x register offset: crg + 0x240 bits 7 6 5 4 3 2 1 0 31:24 reserved srto 23:16 reserved srtt cctm drq dttt mrct mrc sbh 15:8 reserved srte dtte mrce 7:0 reserved req64s m66ens frames irdys devsels stops trdys pci/x control / status register bits name function pcfs space type reset by reset value 31:27 reserved n/a r n/a 0x00 26:24 srto pci-x split response time-out r/w p/s/l 111b 23 reserved n/a r n/a 0x00 22 srtts split response time-out test r/w p/s/l 0x00 21 cctm configuration cycle test mode r/w p/s/l 0x00 20 drq disregard req64_ qualification r/w p/s/l 0x00 19 dttt delayed transaction time-out test r/w p/s/l 0x00 18 mrct maximum retry count test r/w p/s/l 0x00 17 mrc maximum retry count r/w p/s/l 0x00 16 sbh stop on byte holes r/w p/s/l 0x00 15:11 reserved n/a r n/a 0x00 10 srte split response time-out error r/c p/s/l 0x00 9 dtte delayed transaction time-out error r/c p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 262 80a3020_ma001_08 srto (pci-x split response time-out): these bits define the pci-x split response time-out period. the split response time-out shoul d be set to a time that is longer than the vmebus global time-out time. the vmebus gl obal time-out timer is a vmebus system controller function may be controlled by another device. 8 mrce maximum retry count error r/c p/s/l 0x00 7 reserved n/a r n/a 0x00 6 req64s req64 status r p/s/l 0x xx 5 m66ens 66 mhz enable status r p/s/l 0x xx 4 frames frame status r p/s/l 0x xx 3 irdys irdy status r p/s/l 0x xx 2 devsels devsel status r p/s/l 0x xx 1 stops stop status r p/s/l 0x xx 0 trsdys trdy status r p/s/l 0x xx table 83: pci-x split read time-out srto time 000b 16 s 001b 32 s 010b 64 s 011b 128 s 100b 256 s 101b 512 s 110b 1024 s 111b disabled pci/x control / status register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 263 80a3020_ma001_08 srtt (split response time-out test): when this bit is set, the split response time-out time is reduced for test purposes. only single beat transfers are supported. when this bit is cleared, the split response time-out time is controlled by the srto field. this bit is provided for test purposes. cctm (configuration cycle test mode): when this bit is set, any vme to pci/x cycle that uses inbound map decoder number 7 generates pci/x configuration read and write cycles. only single beat transfers are supported. when this bit is cleared, inbound map decoder 7 behaves normally. this bit is provided for test purposes. drq (disregard req64_ qualification): this bit must be cleare d to comply with the pci local bus specification (revision 2.2) . dttt (delayed transaction time-out test): when this bit is set, a delayed transaction times-out after 160 pci/x bus clocks. when this bit is cleared, a delayed transaction times-out after 2^15 clocks. this bit reduces the time-out count for test purposes. mrct (maximum retry count test): when this bit is set and the mrc bit is set, the pci/x master retries 16 times before indicating an error. when this bit is cleared and the mrc bit is set, the pci/x master retries 2^24 times before indicating an error. this bit reduces the retry count for test purposes. mrc (maximum retry count): when this bit is set, the pci/x master counts the number of sequential cycles that are retried. if the count is exceeded, thepci/x master aborts the transfer. when this bit is cleared, there is no limit to the number of retry attempts. sbh (stop on byte holes): when this bit is set and the pci/x bus is configured for conventional mode, the pci target issues a stop command when a transfer has non contiguous byte enables. when this bit is clear, thepci target issues multiple linkage commands to handle transfers with non contiguous byte enables. this bit is provided for diagnostic purposes. srte (split response time-out error): this bit is set when a split response time-out error occurs. this bit is cleared by writing a one to this bit. dtte (delayed transaction time-out error): this bit is set when a delayed transaction time-out error occurs. this bit is cleared by writing a one to this bit. mrce (maximum retry count error): this bit is set when the mrc bit is set and the maximum number of retries is exceeded. this bit is cleared by writing a one to this bit. this bit should be cleared to comply with the pci local bus specification (revision 2.2) .
10. registers tsi148 pci/x-to-vme bus bridge user manual 264 80a3020_ma001_08 req64s (req64 status): when this bit is set, the req64_ signal was sampled high at the rising edge of lrsti_ and the pci/x a/d bus is configured for 32-bit. when this bit is clear, the req64_ signal was sampled low at the risi ng edge of reset and the pci/x a/d bus is configured for 64-bit operation. m66ens (66 mhz enable status): when this bit is set, the m66en signal was sampled high at the rising edge of lrsti_. when this bit is clear, the m66en signal was sampled low at the rising edge of lrsti_. frames (frame status): when this bit is set, the frame_ signal was sampled high at the rising edge of lrsti_. when this bit is cl ear, the frame_ signal was sampled low at the rising edge of lrsti_. irdys (irdy status): when this bit is set, the irdy_ signal was sampled high at the rising edge of lrsti_. when this bit is clear, the irdy_ signal was sampled low at the rising edge of lrsti_. devsels (devsel status): when this bit is set, the devsel_ signal was sampled high at the rising edge of lrsti_. when this bit is clear, the devsel_ signal was sampled low at the rising edge of lrsti_. stops (stop status): when this bit is set, the stop_ si gnal was sampled high at the rising edge of lrsti_. when this b it is clear, the stop_ signal was sampled low at the rising edge of lrsti_. trdys (trdy status): when this bit is set, the trdy_ signal was sampled high at the rising edge of lrsti_. when this bit is clear, the trdy_ signal was sampled low at the rising edge of lrsti_.
10. registers tsi148 pci/x-to-vme bus bridge user manual 265 80a3020_ma001_08 10.4.37 vmebus filter register. ackd (acknowledge delay): these bits define the delay time from when the vmebus data strobes are negated until the acknowledge signals (dtacko_, berro_, and retryo_) table 84: pci/x control / status register register name: vmefl reset value: 0x register offset: crg + 0x250 bits 7 6 5 4 3 2 1 0 31:24 reserved ackd 23:16 reserved 15:8 reserved bgfc brfc bcfc bbfc 7:0 reserved akfc reserved stfc pci/x control / status register bits name function pcfs space type reset by reset value 31:26 reserved n/a r n/a 0x00 25:24 ackd acknowledge delay r/w p 10b 23:12 reserved n/a r n/a 0x00 11 bgfc bus grant filter control r/w p 0x01 10 brfc bus request filter control r/w p 0x01 9 bcfc bus clear filter control r/w p 0x01 8 bbfc bus busy filter control r/w p 0x01 7:5 reserved n/a r n/a 0x00 4 akfc acknowledge filter control r/w p 0x00 3:1 reserved n/a r n/a 0x00 0 stfc strobe filter control r/w p 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 266 80a3020_ma001_08 are negated. bgfc (bus grant filter control): when this bit is set, th e vmebus bg[3:0]in_ and iackin_ signals are filtered with a digital filter to remove noise and glitches. when this bit is clear, the vmebus bgin[3:0]_ and iackin_ signals are not filtered. brfc (bus request filter control): when this bit is set, th e vmebus br[3:0]i_ signals are filtered with a digital filter to remove noi se and glitches. when this bit is clear, the vmebus br[3:0]i_ signals are not filtered. bcfc (bus clear filter control): when this bit is set, the vmebus bclri_ signal is filtered with a digital filter to remove noise and glitches. when this bit is clear, the vmebus bclri_ signal is not filtered. bbfc (bus busy filter control): when this bit is set, the vmebus bbsyi_ signal is filtered with a digital filter to remove noise and glitches. when this bit is clear, the vmebus bbsyi_ signal is not filtered. akfc (acknowledge filter control): when this bit is set, filtering is applied to the vmebus acknowledge signals (dtacki_, berri_, and retryi_). when this bit cleared, no filtering is applied to the vmebus acknowledge signals. stfc (strobe filter control): when this bit is set, filtering is applied to the vmebus strobe signals (asi_, ds0i_, and ds1i_). when this bit cleared, no filtering is applied to the vmebus strobe signals. table 85: acknowledge delay time ackd time 00b slow 01b medium 10b fast 11b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 267 80a3020_ma001_08 10.4.38 vmebus exception address upper register this register captures vmebus address bits 63 to 32 whenever the tsi148 is vme master and a vmebus exception occurs. this register is only updated when the ves bit in the vmebus exception attributes register is clear. table 86: vmebus excepti on address upper register register name: veau reset value: 0x00000000 register offset: crg + 0x260 bits 7 6 5 4 3 2 1 0 31:0 veau vmebus exception address upper register bits name function pcfs space type reset by reset value 31:0 veau vmebus exception address upper r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 268 80a3020_ma001_08 10.4.39 vmebus exception address lower register this register captures vmebus address bits 31 to 1 whenever the tsi148 is vme master and a vmebus exception occurs. this register is only updated when the ves bit in the vmebus exception attributes register is clear. table 87: vmebus excepti on address lower register register name: veal reset value: 0x00000000 register offset: crg + 0x264 bits 7 6 5 4 3 2 1 0 31:0 veal vmebus exception address lower register bits name function pcfs space type reset by reset value 31:0 veal vmebus exception address lower r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 269 80a3020_ma001_08 10.4.40 vmebus exception attributes register table 88: vmebus exception attributes register register name: veat reset value: 0x register offset: crg + 0x268 bits 7 6 5 4 3 2 1 0 31:24 ves veof vescl reserved 23:16 reserved 2eot 2est berr lword write iack 15:8 ds1 ds0 am 7:0 xam pci/x control / status register bits name function pcfs space type reset by reset value 31 ves vmebus exception status r p/s/l 0x00 30 veof vmebus exception overflow r p/s/l 0x00 29 vescl vmebus exception status clear c p/s/l 0x00 28:22 reserved n/a r n/a 0x00 21 2eot 2e odd termination r p/s/l 0x10 20 2est 2e slave terminated r p/s/l 0x00 19 berr vmebus error r p/s/l 0x00 18 lword lword r p/s/l 0x00 17 write write r p/s/l 0x00 16 iack iack r p/s/l 0x00 15 ds1 ds1 r p/s/l 0x00 14 ds0 ds0 r p/s/l 0x00 13:8 am am r p/s/l 0x00 7:0 xam xam r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 270 80a3020_ma001_08 ves (vmebus exception status): this bit is set when the vmebus exception registers are updated. the vmebus error diagnostic registers are updated when the ves bit is clear and the a vmebus master transfer is terminated w ith an error condition, a 2evme transfer is terminated by the slave or 2esst transfer is terminated with the last word invalid. if an exception occurs and the ves bit is set, then the current status is retained and the veof bit is set. this bit is cleared by writing a one to the vescl bit. veof (vmebus exception overflow): if the ves bit is clear and a vmebus exception occurs, the vmebus error diagnostic registers capture the vmebus address and attributes. if another error occurs and the ves bit is set, then the veof bit is set and the registers are not updated. the veof and ves bits are cleared by writing a one to the vescl bit. vescl (vmebus exception status clear): when this bit is set, the ves and veof bits are cleared. this bit always reads zero and writing a zero has no effect. 2eot (2e odd termination): this bit is set when the error diagnostic registers are updated because a 2esst transfer was terminated with a la st word invalid excepti on. this bit is also set when a 2evme transfer receives a slave termination or error termination on an odd beat. this bit is only updated when the ves bit is clear. 2est (2e slave terminated): this bit is set when the error diagnostic registers are updated because a 2evme or 2esst transfer was terminat ed by the slave. this bit is only updated when the ves bit is clear. berr (vmebus error): this bit is set when the error diagnostic registers are updated because a vmebus transfer was te rminated with an e rror. this bit is only updated when the ves bit is clear. lword (lword): this bit captures the state of the vmebus lword_ signal when the tsi148 is vme master and an exception occurs. this bit is set when the lword_ signal is asserted.this bit is only updated when the ves bit is clear. write (write): this bit captures the state of the vmebus write_ signal when the tsi148 is vme master and an exception occurs. this bit is set when the writei_ signal is asserted.this bit is only updated when the ves bit is clear. iack (iack): this bit captures the state of the vm ebus iack_ signal when the tsi148 is vme master and an exception occurs. this bit is set when the iack_ signal is asserted.this bit is only updated when the ves bit is clear. ds1 (ds1): this bit captures the state of the vm ebus ds1_ signal when the tsi148 is vme master and an exception occurs. this bit is set when the ds1i_ signal is asserted. this bit is only updated when the ves bit is clear.
10. registers tsi148 pci/x-to-vme bus bridge user manual 271 80a3020_ma001_08 ds0 (ds0): this bit captures the state of the vm ebus ds0_ signal when the tsi148 is vme master and an exception occurs. this bit is set when the ds0i_ signal is asserted. this bit is only updated when the ves bit is clear. am (am): these bits capture the state of the vmebus am signals when the tsi148 is vme master and an exception occurs. these bits are only updated when the ves bit is clear. xam (xam): these bits captures the state of the vmebus xam signals when the tsi148 is vme master and an exception occurs. these bits are only updated when the ves bit is clear.
10. registers tsi148 pci/x-to-vme bus bridge user manual 272 80a3020_ma001_08 10.4.41 error diagnostic pci/x address upper register this register captures pci/x bus address bits 63 to 32 whenever pci/x bus error occurs. this register is only updated when the edpst bit in the error diagnostic pci/x attributes register is clear. table 89: error diagnostic pci/x address upper register register name: edpau reset value: 0x00000000 register offset: crg + 0x270 bits 7 6 5 4 3 2 1 0 31:0 edpau error diagnostic pci/x addres s upper register bits name function pcfs space type reset by reset value 31:0 edpau error diagnostic pci/x address upper r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 273 80a3020_ma001_08 10.4.42 error diagnostic pci/x address lower register this register captures pci/x address bits 31 to 0 whenever a pci/x bus error occurs. this register is only updated when the edpst bit in the error diagnostic pci/x attributes register is clear. table 90: error diagnostic pci/x address lower register register name: edpal reset value: 0x00000000 register offset: crg + 0x274 bits 7 6 5 4 3 2 1 0 31:0 edpal error diagnostic pci/x addres s lower register bits name function pcfs space type reset by reset value 31:0 edpal error diagnostic pci/x address lower r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 274 80a3020_ma001_08 10.4.43 error diagnostic pci-x attribute register this register captures the pci-x bus ad bits 31 to 0 during the attribute phase whenever a pci-x bus error occurs. this register is only updated when the edpst bit is clear. table 91: error diagnostic pci-x attribute register register name: edpxa reset value: 0x00000000 register offset: crg + 0x278 bits 7 6 5 4 3 2 1 0 31:0 edpxa error diagnostic pci-x attribute register bits name function pcfs space type reset by reset value 31:0 edpxa error diagnostic pci-x attribute r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 275 80a3020_ma001_08 10.4.44 error diagnostic pci-x split completion message register this register captures the pci-x bus split completion message whenever a pc-x bus error occurs. this register is only updated when the edpst bit in the error diagnostic pci-x attributes register is clear. table 92: error diagnostic pci-x split completion message register register name: edpxs reset value: 0x00000000 register offset: crg + 0x27c bits 7 6 5 4 3 2 1 0 31:0 edpxs e rror diagnostic pci-x split completion message register bits name function pcfs space type reset by reset value 31:0 edpxs error diagnostic pci-x split completion message r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 276 80a3020_ma001_08 10.4.45 error diagnostic pci/x attributes register table 93: error diagnostic pci/x attributes register register name: edpat reset value: 0x00000000 register offset: crg + 0x280 bits 7 6 5 4 3 2 1 0 31:24 edpst edpof edpcl reserved 23:16 reserved scd usc 15:8 srt scem dped dpe mrc rma rta dtt 7:0 cbea3 cbea2 cbea1 cbea0 comm3 comm2 comm1 comm0 error diagnostic pci/x attributes register bits name function pcfs space type reset by reset value 31 edpst error diagnostic pci/x status r p/s/l 0x00 30 edpof error diagnostic pci/x overflow r p/s/l 0x00 29 edpcl error diagnostic pci/x clear c p/s/l 0x00 28:18 reserved n/a r n/a 0x00 17 scd split completion discarded. r p/s/l 0x00 16 usc unexpected split completion r p/s/l 0x00 15 srt split response time-out r p/s/l 0x00 14 scem split completion error message r p/s/l 0x00 13 dped data parity error detected. r p/s/l 0x00 12 dpe detected parity error r p/s/l 0x00 11 mrc maximum retry count r p/s/l 0x00 10 rma received master abort r p/s/l 0x00 9 rta received target abort r p/s/l 0x00 8 dtt delayed transaction time-out r p/s/l 0x00 7:4 cbeax cbe attribute r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 277 80a3020_ma001_08 edpst (error diagnostic pci/x status): this bit is set when the pci/x bus error diagnostic registers are updated. this bit is cleared by writing a one to the edpcl bit. edpof (error diagnostic pci/x overflow): if the edpst bit is clear and a pci/x bus error occurs, the pci/x bus error diagnostic registers capture the pci/x bus address and attributes. if another error occurs and the edpst is set, then the edpof bit is set and the registers are not updated. the edpof bit is cleared by writing a one to the edpcl bit. edpcl (error diagnostic pci/x clear): when this bit is set, all bits in the edpau, edpal and edpat registers are cleared. this bit always read zero and writing a zero has no effect. scd (split completion discarded): this bit is set when a split completion is discarded. this bit is only updated when the edpst bit is clear. usc (unexpected split completion): this bit is set when an unexpected split completion is received. this bit is only updated when the edpst bit is clear. srt (split response time-out): this bit is set when a split response time-out occurs. this bit is only updated when the edpst bit is clear. scem (split completion error message): this bit is set when a split completion error message is received. this bit is only updated when the edpst bit is clear. dped (data parity error detected): this bit is set when three conditions are met: 1) the tsi148 asserted perr_ itself or observed perr_ asserted; 2) the tsi148 was the pci/x master for the transfer in which the error occurre d; 3) the perr bit in the cmmd register is set. this bit is only updated when the edpst bit is clear. dpe (detected parity error): this bit is set when the pci/x master detects a data parity error during a read transaction or the pci/x target detects a parity error during a write transaction. this bit is only updated when the edpst bit is clear. mrc (maximum retry count): this bit is set when the maxi mum retry count is exceeded. this bit is only updated when the edpst bit is clear. 3:0 commx command r p/s/l 0x00 error diagnostic pci/x attributes register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 278 80a3020_ma001_08 rma (received master abort): this bit is set when the master receives a master abort. this bit is only updated when the edpst bit is clear. rta (received target abort): this bit is set when the master receives a target abort. this bit is only updated when the edpst bit is clear. dtt (delayed transaction time-out): this bit is set when there is a delayed transaction time-out. this bit is only update d when the edpst bit is clear. cbeax (cbe attribute): these bits capture the pci-x bus cbe signals during the attribute phase whenever a pci/x bus error occurs. these bits are only updated when the edpst bit is clear. commx (command): these bits capture the pci/x bus command whenever a pci/x bus error occurs. these bits are only updated when the edpst bit is clear.
10. registers tsi148 pci/x-to-vme bus bridge user manual 279 80a3020_ma001_08 10.4.46 inbound translation starting address upper (0-7) registers the inbound translation starting address upper registers (its au0-itsau7) contain address information associated with the mapping of vmebus space to pci/x space. the inbound vmebus address is decoded when the vmebus address is greater than or equal to the start address and less than or equal to the end address . stau (start address upper): this field determines the start address of a particular area on the vmebus which is used to access local resour ces. the value of this field is compared with the incoming vmebus address. if the vmebus address is 64-bit, then the start address upper is compared with vmebus address bit 63 to 32. this field is only used when the vmebus address is 64-bits. table 94: inbound translation starti ng address upper (0-7) register register name: itsaux reset value: 0x00000000 register offset: itsau0: crg + 0x300 itsau1: crg + 0x320 itsau2: crg + 0x340 itsau3: crg + 0x360 itsau4: crg + 0x380 itsau5: crg + 0x3a0 itsau6: crg + 0x3c0 itsau7: crg + 0x3e0 bits 7 6 5 4 3 2 1 0 31:0 stau inbound translation starting address upper (0-7) register bits name function pcfs space type reset by reset value 31:0 stau start address upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 280 80a3020_ma001_08 10.4.47 inbound translation starting address lower (0-7) registers the inbound translation starting address lo wer registers (itsal0-itsal7) contain address information associated with the mapping of vmebus space to pci/x space. the inbound vmebus address is decoded when the vmebus address is greater than or equal to the start address and less than or equal to the end address. stal (start address lower): if the vmebus address bus is 64-bit or 32-bit, then the start address lower bits 31 to 16 are compared with vmebus address bits 31 to 16 and the granularity is 64 kbytes. if the vmebus address is 24-bits, then the start address lower bits 23 to 12 are compared with vmebus address bits 23 to 12 and the granularity is 4 kbytes. if the vmebus address is 16-bits, then the start addr ess lower bits 15 to 4 are compared with vmebus address bits 15 to 4 and the granularity is 16 bytes. table 95: inbound translation starti ng address upper (0-7) register register name: iitsalx reset value: 0x00000000 register offset: itsal0: crg + 0x304 itsal1: crg + 0x324 itsal2: crg + 0x344 itsal3: crg + 0x364 itsal4: crg + 0x384 itsal5: crg + 0x3a4 itsal6: crg + 0x3c4 itsal7: crg + 0x3e4 bits 7 6 5 4 3 2 1 0 31:24 stal 23:16 stal 15:8 stal 7:0 stal reserved inbound translation starting address lower (0-7) register bits name function pcfs space type reset by reset value 31:4 stal start address lower r/w p/s/l 0x00 3:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 281 80a3020_ma001_08 10.4.48 inbound translation ending address upper (0-7) registers the inbound translation ending address upper registers (iteau0-iteau7) contain address information associated with the mapping of vmebus space to pci/x space. the inbound vmebus address is decoded when the vmebus address is greater than or equal to the start address and less than or equal to the end address. endu (end address upper): this field determines the end address of a particular area on the vmebus which is used to access local resour ces. the value of this field is compared with the incoming vmebus address. if the vmebus address is 64-bit, then the end address upper is compared with vmebus address bit 63 to 32. this field is only used when the vmebus address is 64-bits. table 96: inbound translation endi ng address upper (0-7) register register name: iteaux reset value: 0x00000000 register offset: iteau0: crg + 0x308 iteau1: crg + 0x328 iteau2: crg + 0x348 iteau3: crg + 0x368 iteau4: crg + 0x388 iteau5: crg + 0x3a8 iteau6: crg + 0x3c8 iteau7: crg + 0x3e8 bits 7 6 5 4 3 2 1 0 31:0 endu inbound translation ending address upper (0-7) register bits name function pcfs space type reset by reset value 31:0 endu end address upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 282 80a3020_ma001_08 10.4.49 inbound translation ending address lower (0-7) registers the inbound translation ending address lo wer registers (iteal0-iteal7) contain address information associated with the mapping of vmebus space to pci/x space. the inbound vmebus address is decoded when the vmebus address is greater than or equal to the start address and less than or equal to the end address. endl (end address lower): if the vmebus address bus is 64-bit or 32-bit, then the end address lower bits 31 to 16 are compared with vmebus address bits 31 to 16 and the granularity is 64 kbytes. if the vmebus address is 24-bits, then the end address lower bits 23 to 12 are compared with vmebus address bits 23 to 12 and the granularity is 4 kbytes. if the vmebus address is 16-bits, then the end addr ess lower bits 15 to 4 are compared with vmebus address bits 15 to 4 and the granularity is 16 bytes. table 97: inbound translation endi ng address lower (0-7) register register name: iitealx reset value: 0x00000000 register offset: iteal0: crg + 0x30c iteal1: crg + 0x32c iteal2: crg + 0x34c iteal3: crg + 0x36c iteal4: crg + 0x38c iteal5: crg + 0x3ac iteal6: crg + 0x3cc iteal7: crg + 0x3ec bits 7 6 5 4 3 2 1 0 31:24 endal 23:16 endal 15:8 endal 7:0 endal reserved inbound translation ending address lower (0-7) register bits name function pcfs space type reset by reset value 31:4 endal start address lower r/w p/s/l 0x00 3:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 283 80a3020_ma001_08 10.4.50 inbound translation offset upper (0-7) registers the inbound translation offset upper regist ers (itofu0-itofu7) contain information associated with the mapping of vmebus space to pci/x space. offu (offset upper): this field contains the offset that is added to vmebus address bits 63 to 32 to create the pci/x bus address. if the vm ebus address is not 64-bit, then the internal vmebus address bits 63 to 32 are zeroed before the offset is added. table 98: inbound translation offset upper (0-7) register register name: iitofux reset value: 0x00000000 register offset: itofu0: crg + 0x310 itofu1: crg + 0x330 itofu2: crg + 0x350 itofu3: crg + 0x370 itofu4: crg + 0x390 itofu5: crg + 0x3b0 itofu6: crg + 0x3d0 itofu7: crg + 0x3f0 bits 7 6 5 4 3 2 1 0 31:0 offu inbound translation offset upper (0-7) register bits name function pcfs space type reset by reset value 31:0 offu offset upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 284 80a3020_ma001_08 10.4.51 inbound translation offset lower (0-7) registers the inbound translation offset lower regi sters (itofl0-itofl7) contain information associated with the mapping of vmebus space to pci/x space. offl (offset lower): this field contains the offset that is added to the lower vmebus address bits to create the pci/x bus address. if the vmebus address is 24-bit, then the internal vmebus address bits 31 to 24 are zeroed and then offset bits 31 to 12 are added. if the vmebus address is 16-bit, then the internal vmebus address bits 31 to 16 are zeroed and offset bits 31 to 4 are added. table 99: inbound translation offset lower (0-7) register register name: iitofl reset value: 0x00000000 register offset: itofl0: crg + 0x314 itofl1: crg + 0x334 itofl2: crg + 0x354 itofl3: crg + 0x374 itofl4: crg + 0x394 itofl5: crg + 0x3b4 itofl6: crg + 0x3d4 itofl7: crg + 0x3f4 bits 7 6 5 4 3 2 1 0 31:24 offl 23:16 offl 15:8 offl 7:0 offl reserved inbound translation offset lower (0-7) register bits name function pcfs space type reset by reset value 31:4 offl offset lower r/w p/s/l 0x00 3:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 285 80a3020_ma001_08 10.4.52 inbound translation attribute (0-7) registers the inbound translation attribut e registers (itat0-itat7) contain information associated with the mapping of vmebus space to pci/x space. table 100: inbound translati on attribute (0-7) register register name: itatx reset value: 0x00000000 register offset: itat0: crg + 0x318 itat1: crg + 0x338 itat2: crg + 0x358 itat3: crg + 0x378 itat4: crg + 0x398 itat5: crg + 0x3b8 itat6: crg + 0x3d8 itat7: crg + 0x3f8 bits 7 6 5 4 3 2 1 0 31:24 en reserved 23:16 reserved th vfs1 vfs0 15:8 reserved 2esstm2 2esstm1 2esstm0 2esstb 2esst 2evme mblt 7:0 blt as2 as1 as0 supr npriv pgm data inbound translation attribute (0-7) register bits name function pcfs space type reset by reset value 31 en enable r/w p/s/l 0x00 30:19 reserved n/a r n/a 0x00 18 th threshold r/w p/s/l 0x00 17 vfs1 virtual fifo size r/w p/s/l 0x00 16 vfs0 virtual fifo size r/w p/s/l 0x00 15 reserved n/a r n/a 0x00 14 2esstm2 2esstm r/w p/s/l 0x00 13 2esstm1 2esstm r/w p/s/l 0x00 12 2esstm0 2esstm r/w p/s/l 0x00 11 2esstb 2esstb r/w p/s/l 0x00 10 2esst 2esst r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 286 80a3020_ma001_08 en (enable): if set, the corresponding vme slave window is enabled. th (threshold): this field sets a threshold for when re ad-ahead prefetching resumes. if set, prefetching resumes once the fifo is half empty. if cleared, prefetching resumes once the fifo is completely empty. vfs (virtual fifo size): this field is used to set the fifo size for inbound prefetch reads. the selection of a virtual fifo size affects th e number of initial prefetch read cycles and the number of subsequent prefetch read cycles. 9 2evme 2evme r/w p/s/l 0x00 8 mblt mblt r/w p/s/l 0x00 7 blt blt r/w p/s/l 0x00 6 as2 address space r/w p/s/l 0x00 5 as1 address space r/w p/s/l 0x00 4 as0 address space r/w p/s/l 0x00 3 supr supervisor r/w p/s/l 0x00 2 npriv non-privileged r/w p/s/l 0x00 1 pgm program r/w p/s/l 0x00 0 data data r/w p/s/l 0x00 table 101: virtual fifo size vfs fifo size bytes initial read bytes subsequent reads bytes 00b 64 64 32 01b 128 128 64 10b 256 256 128 11b 512 512 256 inbound translation attribute (0-7) register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 287 80a3020_ma001_08 2esstm (2esstm): these bits define the 2esst transfer rates the corresponding vme slave responds to. if sst320 is enabled, the vme slave also responds to sst267 and sst160. if sst267 is enabled, the vme slave also responds to sst160. 2esstb (2esstb): if set, the corresponding vme slave responds to 2esst broadcast cycles. 2esst (2esst): if set, the corresponding vme slave responds to standard 2esst cycles. 2evme (2evme): if set, the corresponding vme slave responds to 2evme cycles. mblt (mblt): if set, the corresponding vme slave responds to mblt cycles. blt (blt): if set, the corresponding vme slave responds to blt cycles. as (address space): these bits define the address space the corresponding vme slave responds to. table 102: 2esst mode 2esstm 2esst mode 000b sst160 001b sst267 010b sst320 011b-111b reserved table 103: vmebus address space as address space 000b a16 001b a24 010b a32 011b reserved 100b a64 101b reserved 110b reserved 111b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 288 80a3020_ma001_08 supr (supervisor): if set, the corresponding vme slave is enabled to respond to vmebus supervisor access cycles. npriv (non-privileged): if set, the corresponding vme slave is enabled to respond to non-privileged access cycles. pgm (program): if set, the corresponding vme slave is enabled to respond to vmebus program access cycles. data (data): if set, the corresponding vme slave is enabled to respond to vmebus data access cycles.
10. registers tsi148 pci/x-to-vme bus bridge user manual 289 80a3020_ma001_08 10.4.53 gcsr base address upper register this field contains the vmebus base address of the gcsr registers. the value in this register is compared with vmebus address bits 63 to 32. this register is only used for during a64 cycles. table 104: gcsr base address upper register register name: gbau reset value: 0x00000000 register offset: crg + 0x400 bits 7 6 5 4 3 2 1 0 31:0 gbau gcsr base address upper register bits name function pcfs space type reset by reset value 31:0 gbau gcsr base address upper r/w p/s 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 290 80a3020_ma001_08 10.4.54 gcsr base address lower register this field contains the vmebus base address of the gcsr registers. if the vmebus address is a64 or a32, the value in this register is compared with vmebus address bits 31 to 5. if the vmebus address is a24, the value in this regi ster is compared with vmebus address bits 23 to 5. if the vmebus address is a16, the value in this register is compared with vmebus address bits 15 to 5. table 105: gcsr base address lower (0-7) register register name: gbal reset value: 0x00000000 register offset: crg + 0x404 bits 7 6 5 4 3 2 1 0 31:24 offl 23:16 offl 15:8 offl 7:0 offl reserved gcsr base address lower (0-7) register bits name function pcfs space type reset by reset value 31:5 offl offset lower r/w p/s 0x00 4:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 291 80a3020_ma001_08 10.4.55 gcsr attribute register en (enable): if set, access to the gcsr registers is enabled. table 106: gcsr attribute register register name: gcsrat reset value: 0x00000000 register offset: crg + 0x408 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:8 reserved 7:0 en as2 as1 as0 supr npriv pgm data gcsr base address lower (0-7) register bits name function pcfs space type reset by reset value 31:8 reserved n/a r n/a 0x00 7 en enable r/w p/s 0x00 6 as2 address space r/w p/s 0x00 5 as1 address space r/w p/s 0x00 4 as0 address space r/w p/s 0x00 3 supr supervisor r/w p/s 0x00 2 npriv non-privileged r/w p/s 0x00 1 pgm program r/w p/s 0x00 0datadata r/wp/s0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 292 80a3020_ma001_08 as (address space): these bits define the address space the gcsr decoder responds to. npriv (non-privileged): if set, the gcsr decoder is enabled to respond to non-privileged access cycles. supr (supervisor): if set, the gcsr decoder is enabled to respond to vmebus supervisor access cycles. pgm (program): if set, the gcsr decoder is enabled to respond to vmebus program access cycles. data (data): if set, the gcsr decoder is enabled to respond to vmebus data access cycles. table 107: vmebus address space as address space 000b a16 001b a24 010b a32 011b reserved 100b a64 101b reserved 110b reserved 111b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 293 80a3020_ma001_08 10.4.56 crg base address upper register this field contains the vmebus base address of the crg registers. the va lue in this register is compared with vmebus address bits 63 to 32. this register is only used for during a64 cycles. table 108: crg base address upper register register name: cbau reset value: 0x00000000 register offset: crg + 0x40c bits 7 6 5 4 3 2 1 0 31:0 cbau crg base address upper register bits name function pcfs space type reset by reset value 31:0 cbau crg base address upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 294 80a3020_ma001_08 10.4.57 crg base address lower register this field contains the vmebus base address of the crg registers. if the vmebus address is a64 or a32, the value in this register is compared with vmebus address bits 31 to 12. if the vmebus address is a24, the value in this regi ster is compared with vmebus address bits 23 to 12. if the vmebus address is a16, the valu e in this register is compared with vmebus address bits 15 to 12. table 109: crg base address lower register register name: cbal reset value: 0x00000000 register offset: crg + 0x410 bits 7 6 5 4 3 2 1 0 31:24 cbal 23:16 cbal 15:8 cbal reserved 7:0 reserved cbal base address lower register bits name function pcfs space type reset by reset value 31:12 cbau crg base address lower r/w p/s/l 0x00 11:0 reserved n/a r/w n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 295 80a3020_ma001_08 10.4.58 crg attribute register en (enable): if set, access to the crg is enabled. table 110: crg attribute register register name: crgat reset value: 0x00000000 register offset: crg + 0x414 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:8 reserved 7:0 en as2 as1 as0 supr npriv pgm data crg base address lower (0-7) register bits name function pcfs space type reset by reset value 31:8 reserved n/a r n/a 0x00 7 en enable r/w p/s/l 0x00 6 as2 address space r/w p/s/l 0x00 5 as1 address space r/w p/s/l 0x00 4 as0 address space r/w p/s/l 0x00 3 supr supervisor r/w p/s/l 0x00 2 npriv non-privileged r/w p/s/l 0x00 1 pgm program r/w p/s/l 0x00 0 data data r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 296 80a3020_ma001_08 as (address space): these bits define the address space the crg decoder responds to. npriv (non-privileged): if set, the crg decoder is enabled to respond to non-privileged access cycles. supr (supervisor): if set, the crg decoder is enabled to respond to vmebus supervisor access cycles. pgm (program): if set, the crg decoder is enabled to respond to vmebus program access cycles. data (data): if set, the crg decoder is enabled to respond to vmebus data access cycles. table 111: vmebus address space as address space 000b a16 001b a24 010b a32 011b reserved 100b a64 101b reserved 110b reserved 111b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 297 80a3020_ma001_08 10.4.59 cr/csr offset upper register this field contains the offset that is added to the internal vmebus address bits 63 to 32 to create the pci/x bus address. during cr/csr cycles, the internal vmebus address bits 63 to 32 are forced to zero. table 112: cr/csr offset upper register register name: c rou reset value: 0x00000000 register offset: crg + 0x418 bits 7 6 5 4 3 2 1 0 31:0 crou cr/csr offset upper register bits name function pcfs space type reset by reset value 31:0 crou cr/csr offset upper r/w p/s 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 298 80a3020_ma001_08 10.4.60 cr/csr offset lower register this field contains the offset that is added to the internal vmebus address bits 31 to 19 to create the pci/x bus address. during cr/csr cycles, the internal vmebus address bits 31 to 19 are forced to zero. table 113: cr/csr offset lower register register name: crol reset value: 0x00000000 register offset: crg + 0x41c bits 7 6 5 4 3 2 1 0 31:24 crol 23:16 crol reserved 15:8 reserved 7:0 reserved cr/csr offset lower register bits name function pcfs space type reset by reset value 31:19 crol cr/csr base address lower r/w p/s 0x00 18:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 299 80a3020_ma001_08 10.4.61 cr/csr attribute register en (enable): if set, access to the cr/csr registers are enabled. the initial value of this bit is determined the hardware configuration (see section 5.4.2.1 on page 131 ). table 114: crg attribute register register name: crat reset value: 0x00000000 register offset: crg + 0x420 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:8 reserved 7:0 en reserved crg attribute register bits name function pcfs space type reset by reset value 31:8 reserved n/a r n/a 0x00 7 en enable r/w p/s 0x xx 6:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 300 80a3020_ma001_08 10.4.62 location monitor base address upper register this field contains the vmebus base address of the locations to be monitored. the value in this register is compared with vmebus address bits 63 to 32. this regi ster is only used for during a64 cycles. table 115: location monitor base address upper register register name: lmbau reset value: 0x00000000 register offset: crg + 0x424 bits 7 6 5 4 3 2 1 0 31:0 lmbau location monitor base address upper register bits name function pcfs space type reset by reset value 31:0 lmbau location monitor base address upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 301 80a3020_ma001_08 10.4.63 location monitor base address lower register this field contains the vmebus base address of the location to be monitored. if the vmebus address is a64 or a32, the value in this regist er is compared with vmebus address bits 31 to 5. if the vmebus address is a24, the value in this register is compared with vmebus address bits 23 to 5. if the vmebus address is a16, th e value in this register is compared with vmebus address bits 15 to 5. table 116: location monitor base address lower register register name: lmbal reset value: 0x00000000 register offset: crg + 0x428 bits 7 6 5 4 3 2 1 0 31:24 lmbal 23:16 lmbal 15:8 lmbal 7:0 lmbal reserved cr/csr offset lower register bits name function pcfs space type reset by reset value 31:5 lmbal location monitor base address lower r/w p/s/l 0x00 4:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 302 80a3020_ma001_08 10.4.64 location monitor attribute register en (enable): if set, the location monitor is enabled. table 117: location monitor register register name: lmat reset value: 0x00000000 register offset: crg + 0x42c bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:8 reserved 7:0 en as2 as1 as0 supr npriv pgm data location monitor register bits name function pcfs space type reset by reset value 31:8 reserved n/a r n/a 0x00 7 en enable r/w p/s/l 0x00 6 as2 address space r/w p/s/l 0x00 5 as1 address space r/w p/s/l 0x00 4 as0 address space r/w p/s/l 0x00 3 supr supervisor r/w p/s/l 0x00 2 npriv non-privileged r/w p/s/l 0x00 1 pgm program r/w p/s/l 0x00 0 data data r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 303 80a3020_ma001_08 as (address space): these bits define the address space the location monitor responds to: npriv (non-privileged): if set, the location monitor is enabled to respond to non-privileged access cycles. supr (supervisor): if set, the location monitor is enable d to respond to vmebus supervisor access cycles. pgm (program): if set, the location monitor is enabled to respond to vmebus program access cycles. data (data): if set, the location monitor is enabled to respond to vmebus data access cycles. table 118: vmebus address space as address space 000b a16 001b a24 010b a32 011b reserved 100b a64 101b reserved 110b reserved 111b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 304 80a3020_ma001_08 10.4.65 64-bit counter upper these bits are the most significant bits of the 64-bit counter. the 64-bit counter can be used to count events on the vmebus irq[1]i_ or irq[2]i_ signal lines. since the 64-bit counter is comprised of two 32-bit registers, it is possible that the lower counter may roll over between a read or write of the upper and lower portions. software must consider this case. table 119: 64-bit counter upper register register name: 64bcu reset value: 0x00000000 register offset: crg + 0x430 bits 7 6 5 4 3 2 1 0 31:0 64bcu 64-bit counter upper register bits name function pcfs space type reset by reset value 31:0 64bcu 64-bit counter upper r/w p/s 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 305 80a3020_ma001_08 10.4.66 64-bit counter lower these bits are the least significant bits of the 64-bit counter. the 64-bit counter can be used to count events on the vmebus irq[1]i_ or irq[2]i_ signal lines. since the 64-bit counter is comprised of two 32-bit registers, it is possible that the lower counter may roll over between a read or write of the upper and lower portions. software must consider this case. table 120: 64-bit counter lower register register name: 64bcl reset value: 0x00000000 register offset: crg + 0x434 bits 7 6 5 4 3 2 1 0 31:0 64bcl 64-bit counter lower register bits name function pcfs space type reset by reset value 31:0 64bcl 64-bit counter lower r/w p/s 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 306 80a3020_ma001_08 10.4.67 broadcast pulse generator timer register the value in this register is compared to that of the internal broadcast pulse generator counter. when they are equal, a broadcast interrupt pulse is generated and the counter is reset to 0. the value in this register determines the broadcast interrupt pulse width in approximately 30-ns increments. due to the requ ired glitch filters on the vmebus irq[1]i_ and irq[2]i_ signal lines, the value written to this register must be greater than 0x0003. approximately, the broadcast interrupt pulse width is programmable from 120 ns to 1.97 ms. after power-up, this register is initialized to 0x0022 which produces a 1.02- s pulse if broadcast pulse mode is enabled. writing a value of all zeros to this register has no effect. table 121: broadcast pulse generator timer register register name: bpgtr reset value: 0x0000022 register offset: crg + 0x438 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:8 bpgt 7:0 bpgt broadcast pulse generator timer register bits name function pcfs space type reset by reset value 31:16 reserved n/a r n/a 0x00 15:0 bpgt broadcast pulse generator timer r/w p/s 0x22
10. registers tsi148 pci/x-to-vme bus bridge user manual 307 80a3020_ma001_08 10.4.68 broadcast programmable clock timer register the value in this register is compared to that of the internal broadcast programmable clock counter. when they are equal, a broadcast interr upt clock is generated and the counter is reset to 0. the value in this register determines the broadcast interrupt clock rate in approximately 1.02- s increments. due to the required glitch filte rs on the vmebus irq[1]i_ and irq[2]i_ signal lines, the value written to this register must be greater than 0x000001. approximately, the broadcast interrupt clock rate is programmable from 2.04 s to 17.11 seconds. after power-up, this register is initialized to 0x0003e 8 which produces a 1.02-ms clock if broadcast programmable clock mode is enabled. writing a value of all zeros to this register has no effect. table 122: broadcast programmable clock timer register register name: bpctr reset value: 0x000003e8 register offset: crg + 0x43c bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 bpct 15:8 bpct 7:0 bpct broadcast programmable clock timer register bits name function pcfs space type reset by reset value 31:24 reserved n/a r n/a 0x00 23:0 bpct broadcast programmable clock timer r/w p/s 0x3e8
10. registers tsi148 pci/x-to-vme bus bridge user manual 308 80a3020_ma001_08 10.4.69 vmebus interrupt control register the vmebus interrupt control register is used to control the vmebus interrupt function. table 123: vmebus interrupt control register register name: vicr reset value: 0x0000000f register offset: crg + 0x440 bits 7 6 5 4 3 2 1 0 31:24 cnts edgis irqif irq2f 23:16 bip bips reserved 15:8 irqc irqls irqs irql 7:0 stid vmebus interrupt control register bits name function pcfs space type reset by reset value 31:30 cnts counter source r/w p/s 0x00 29:28 edgis edge interrupt source r/w p/s 0x00 27:26 irqif irq1 function r/w p/s 0x00 25:24 irq2f irq2 function r/w p/s 0x00 23 bip broadcast interrupt pulse s - 0x00 22 bips broadcast interrupt pulse status r p/s 0x00 21:16 reserved n/a r n/a 0x00 15 irqc vmebus irq clear s - 0x00 14:12 irqls vmebus irq level status r p/s 0x00 11 irqs vmebus irq status r p/s 0x00 10:8 irql vmebus irq level s - 0x00 7:0 stid status/id r/w p/s 0x0f
10. registers tsi148 pci/x-to-vme bus bridge user manual 309 80a3020_ma001_08 cnts (counter source): these bits define input to the 64-bit counter. edgis (edge interrupt source): these bits define input to vmebus edge interrupt logic. irq1f (irq1 function): these bits define the function of the vmebus irq[1]o signal line as an output. table 124: counter source cnts counter source 00b counter disable 01b irq[1]i_ to counter 10b irq[2]i_ to counter 11b reserved table 125: edge interrupt source edgis edge interrupt source 00b edge interrupt disable 01b irq[1]i_ to edge interrupt 10b irq[2]i_ to edge interrupt 11b reserved table 126: vmebus irq[1]o function irq1f vmebus irq[1]o function 00b normal 01b pulse generator 10b programmable clock 11b 1.02 s clock
10. registers tsi148 pci/x-to-vme bus bridge user manual 310 80a3020_ma001_08 irq2f (irq2 function): these bits define the function of the vmebus irq[2]o signal line as an output. bip (broadcast interrupt pulse): when the broadcast interrupt pulse mode is enabled, setting this bit causes a pulse to be genera ted on the vmebus irq[1]o or irq[2]o signal line. this bit always reads zero and writing a zero has no effect. bips (broadcast interrupt pulse status): when this bit is high, the broadcast interrupt pulse is still being generated by the pulse generator. when this bit is low, the pulse generator has finished generating the broadcast interrupt pulse. this is a read only status bit. irqc (vmebus irq clear): when this bit is set high, th e irql bits are reset and the vmebus interrupt is removed. this bit should only be used to recover from an error condition. normally vmebus interrupts should not be removed. this bit always reads zero and writing a zero has no effect. irqls (vmebus irq level status): these bits are read-only status bits and they define the current level of a pending vmebus interrupt. irqs (vmebus irq status): when this bit is high, the vmebus interrupt has not been acknowledged. when this bit is low, the vmeb us interrupt has been acknowledged. this is a read only status bit. irql (vmebus irq level): these bits define the level of the vmebus interrupt generated by the tsi148. a vmebus interrupt is generate d by writing the desired level to these bits. these bits always read 0 and writing a 0 to these bits has no effect. these bits are automatically cleared following the vmebus interrupt acknowledge cycle. stid (status/id): these bits define the vmebus vector that is returned during an interrupt acknowledge cycle. table 127: vmebus irq[2]o function irq2f vmebus irq[2]o function 00b normal 01b pulse generator 10b programmable clock 11b 1.02 s clock
10. registers tsi148 pci/x-to-vme bus bridge user manual 311 80a3020_ma001_08 10.4.70 interrupt enable register table 128: interrupt enable register register name: inten reset value: 0x00000000 register offset: crg + 448 bits 7 6 5 4 3 2 1 0 31:24 reserved dma1en dma0en 23:16 lm3en lm2en lm1en lm0en mb3en mb2en mb1en mb0en 15:8 reserved perren verren vieen iacken sysflen acflen 7:0 irq7en irq6en irq5en irq4en irq3en irq2en irq1en reserved interrupt enable register bits name function pcfs space type reset by reset value 31:26 reserved n/a r n/a 0x00 25 dma1en dmac 1 interrupt enable r/w p/s/l 0x00 24 dma0en dmac 0 interrupt enable r/w p/s/l 0x00 23 lm3en location monitor 3 interrupt enable r/w p/s/l 0x00 22 lm2en location monitor 2 interrupt enable r/w p/s/l 0x00 21 lm1en location monitor 1 interrupt enable r/w p/s/l 0x00 20 lm0en location monitor 0 interrupt enable r/w p/s/l 0x00 19 mb3en mail box 3 interrupt enable r/w p/s/l 0x00 18 mb2en mail box 2 interrupt enable r/w p/s/l 0x00 17 mb1en mail box 1 interrupt enable r/w p/s/l 0x00 16 mb0en mail box 0 interrupt enable r/w p/s/l 0x00 15:14 reserved n/a r n/a 0x00 13 perren pci/x bus error interrupt enable r/w p/s/l 0x00 12 verren vmebus error interrupt enable r/w p/s/l 0x00 11 vieen vmebus irq edge interrupt enable r/w p/s/l 0x00 10 iacken interrupt acknowledge interrupt enable r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 312 80a3020_ma001_08 dma1en (dmac 1 interrupt enable): when this bit is high, the dma 1 controller interrupt is enabled. when the interrupt is enab led, the status bit indicates the state of the dma 1 controller interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by se tting the enable bit and clearing the interrupt out bit. dma0en (dmac 0 interrupt enable): when this bit is high, the dma 0 controller interrupt is enabled. when the interrupt is enab led, the status bit indicates the state of the dma 0 controller interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by se tting the enable bit and clearing the interrupt out bit. lm3en (location monitor 3 interrupt enable): when this bit is high, the location monitor 3 interrupt is enabled. wh en the interrupt is enabled, th e status bit indicates the state of the location monitor 3 interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. 9 sysflen system fail interrupt enable r/w p/s/l 0x00 8 acflen ac fail interrupt enable r/w p/s/l 0x00 7 irq7en irq7 enable r/w p/s/l 0x00 6 irq6en irq6 enable r/w p/s/l 0x00 5 irq5en irq5 enable r/w p/s/l 0x00 4 irq4en irq4 enable r/w p/s/l 0x00 3 irq3en irq3 enable r/w p/s/l 0x00 2 irq2en irq2 enable r/w p/s/l 0x00 1 irq1en irq1 enable r/w p/s/l 0x00 0 reserved n/a r n/a 0x00 interrupt enable register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 313 80a3020_ma001_08 lm2en (location monitor 2 interrupt enable): when this bit is high, the location monitor 2 interrupt is enabled. wh en the interrupt is enabled, th e status bit indicates the state of the location monitor 2 interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. lm1en (location monitor 1 interrupt enable): when this bit is high, the location monitor 1 interrupt is enabled. wh en the interrupt is enabled, th e status bit indicates the state of the location monitor 1 interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. lm0en (location monitor 0 interrupt enable): when this bit is high, the location monitor 0 interrupt is enabled. wh en the interrupt is enabled, th e status bit indicates the state of the location monitor 0 interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. mb3en (mail box 3 interrupt enable): when this bit is high, the mail box 3 interrupt is enabled. when the interrupt is enabled, the status bit indicates the state of the mail box 3 interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. mb2en (mail box 2 interrupt enable): when this bit is high, the mail box 2 interrupt is enabled. when the interrupt is enabled, the status bit indicates the state of the mail box 2 interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. mb1en (mail box 1 interrupt enable): when this bit is high, the mail box 1 interrupt is enabled. when the interrupt is enabled, the status bit indicates the state of the mail box 1 interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. mb0en (mail box 0 interrupt enable): when this bit is high, the mail box 0 interrupt is enabled. when the interrupt is enabled, the status bit indicates the state of the mail box 0 interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. perren (pci/x bus error interrupt enable): when this bit is high, the pci/x bus error enabled. when the interrupt is enabled, the st atus bit indicates the state of the pci/x buss error interrupt. a local bus interr upt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by setting the enab le bit and clearing the interrupt out bit.
10. registers tsi148 pci/x-to-vme bus bridge user manual 314 80a3020_ma001_08 verren (vmebus error interrupt enable): when this bit is high, the vmebus error interrupt is enabled. when the interrupt is enab led, the status bit indicates the state of the vmebus error interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by settin g the enable bit and clearing the interrupt out bit. vieen (vmebus irq edge interrupt enable): when this bit is high, the vmebus irq edge interrupt is enabled. when the interrupt is enabled, the stat us bit indicates the state of the vmebus irq edge interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by se tting the enable bit and clearing the interrupt out bit. iacken (interrupt acknowl edge interrupt enable): when this bit is high, the vmebus interrupt acknowledge interrupt is enabled. wh en the interrupt is enabled, the status bit indicates the state of the vmebus interrupt acknowledge interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. sysflen (system fail interrupt enable): when this bit is high, the vmebus system fail interrupt is enabled. when the interrupt is enab led, the status bit indicates the state of the vmebus system fail interrupt. a local bus interr upt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by se tting the enable bit and clearing the interrupt out bit. acflen (ac fail interrupt enable): when this bit is high, the ac fail interrupt is enabled. when the interrupt is enabled, the status bit indicates th e state of the ac fail interrupt. a local bus interrupt is generated if the corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. irq7en (irq7 enable): when this bit is high, the vmebus irq7 interrupt is enabled. when the interrupt is enabled, the status bit i ndicates the state of the vmebus irq[7]i_ signal line. a local bus interrupt is generated if th e corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. irq6en (irq6 enable): when this bit is high, the vmebus irq6 interrupt is enabled. when the interrupt is enabled, the status bit i ndicates the state of the vmebus irq[6]i_ signal line. a local bus interrupt is generated if th e corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. irq5en (irq5 enable): when this bit is high, the vmebus irq5 interrupt is enabled. when the interrupt is enabled, the status bit i ndicates the state of the vmebus irq[5]i_ signal line. a local bus interrupt is generated if th e corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit.
10. registers tsi148 pci/x-to-vme bus bridge user manual 315 80a3020_ma001_08 irq4en (irq4 enable): when this bit is high, the vmebus irq4 interrupt is enabled. when the interrupt is enabled, th e status bit indicates the state of the vmebus irq[4]i_ signal line. a local bus interrupt is generated if th e corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. irq3en (irq3 enable): when this bit is high, the vmebus irq3 interrupt is enabled. when the interrupt is enabled, th e status bit indicates the state of the vmebus irq[3]i_ signal line. a local bus interrupt is generated if th e corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. irq2en (irq2 enable): when this bit is high, the vmebus irq2 interrupt is enabled. when the interrupt is enabled, th e status bit indicates the state of the vmebus irq[2]i_ signal line. a local bus interrupt is generated if th e corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit. irq1en (irq1 enable): when this bit is high, the vmebus irq1 interrupt is enabled. when the interrupt is enabled, th e status bit indicates the state of the vmebus irq[1]i_ signal line. a local bus interrupt is generated if th e corresponding interrupt out bit is set. the interrupt can be polled by setting the enable bit and clearing the interrupt out bit.
10. registers tsi148 pci/x-to-vme bus bridge user manual 316 80a3020_ma001_08 10.4.71 interrupt enable out register table 129: interrupt enable out register register name: inteo reset value: 0x00000000 register offset: crg + 44c bits 7 6 5 4 3 2 1 0 31:24 reserved dma1eo dma0eo 23:16 lm3eo lm2eo lm1eo lm0eo mb3eo mb2eo mb1eo mb0eo 15:8 reserved perreo verreo vieeo iackeo sysfleo acfleo 7:0 irq7eo irq6eo irq5eo irq4eo irq3eo irq2eo irq1eo reserved interrupt enable out register bits name function pcfs space type reset by reset value 31:26 reserved n/a r n/a 0x00 25 dma1eo dmac 1 interrupt enable out r/w p/s/l 0x00 24 dma0eo dmac 0 interrupt enable out r/w p/s/l 0x00 23 lm3eo location monitor 3 interrupt enable out r/w p/s/l 0x00 22 lm2eo location monitor 2 interrupt enable out r/w p/s/l 0x00 21 lm1eo location monitor 1 interrupt enable out r/w p/s/l 0x00 20 lm0eo location monitor 0 interrupt enable out r/w p/s/l 0x00 19 mb3eo mail box 3 interrupt enable out r/w p/s/l 0x00 18 mb2eo mail box 2 interrupt enable out r/w p/s/l 0x00 17 mb1eo mail box 1 interrupt enable out r/w p/s/l 0x00 16 mb0eo mail box 0 interrupt enable out r/w p/s/l 0x00 15:14 reserved n/a r n/a 0x00 13 perreo pci/x bus error interrupt enable out r/w p/s/l 0x00 12 verreo vmebus error interrupt enable out r/w p/s/l 0x00 11 vieeo vmebus irq edge interrupt enable out r/w p/s/l 0x00 10 iackeo interrupt acknowledge interrupt enable out r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 317 80a3020_ma001_08 dma1eo (dma 1 interrupt enable out): when this bit is high, the dma 1 controller interrupt is enabled to the one of the four intx pins. dma0eo (dma 0 interrupt enable out): when this bit is high, the dma 0 controller interrupt is enabled to the one of the four intx pins. lm3eo (location monitor 3 interrupt enable out): when this bit is high, the location monitor 3 interrupt is enabled to the one of the four intx pins. lm2eo (location monitor 2 interrupt enable out): when this bit is high, the location monitor 2 interrupt is enabled to the one of the four intx pins. lm1eo (location monitor 1 interrupt enable out): when this bit is high, the location monitor 1 interrupt is enabled to the one of the four intx pins. lm0eo (location monitor 0 interrupt enable out): when this bit is high, the location monitor 0 interrupt is enabled to the one of the four intx pins. mb3eo (mail box 3 interrupt enable out): when this bit is high, the mail box 3 interrupt is enabled to the one of the four intx pins. mb2eo (mail box 2 interrupt enable out): when this bit is high, the mail box 2 interrupt is enabled to the one of the four intx pins. 9 sysfleo system fail interrupt enable out r/w p/s/l 0x00 8 acfleo ac fail interrupt enable out r/w p/s/l 0x00 7 irq7eo irq7 enable out r/w p/s/l 0x00 6 irq6eo irq6 enable out r/w p/s/l 0x00 5 irq5eo irq5 enable out r/w p/s/l 0x00 4 irq4eo irq4 enable out r/w p/s/l 0x00 3 irq3eo irq3 enable out r/w p/s/l 0x00 2 irq2eo irq2 enable out r/w p/s/l 0x00 1 irq1eo irq1 enable out r/w p/s/l 0x00 0 reserved n/a r n/a 0x00 interrupt enable out register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 318 80a3020_ma001_08 mb1eo (mail box 1 interrupt enable out): when this bit is high, the mail box 1 interrupt is enabled to the one of the four intx pins. mb0eo (mail box 0 interrupt enable out): when this bit is high, the mail box 0 interrupt is enabled to the one of the four intx pins. perreo (pci/x bus error enable out): when this bit is high, the pci/x bus error interrupt is enabled to the one of the four intx pins. verreo (vmebus error interrupt enable out): when this bit is high, the vmebus error interrupt is enabled to th e one of the four intx pins. vieeo (vmebus irq edge interrupt enable out): when this bit is high, the vmebus irq edge interrupt is enabled to the one of the four intx pins. iackeo (interrupt acknowledge interrupt enable out): when this bit is high, the vmebus interrupt acknowledge interrupt is enabled to the one of the four intx pins. sysfleo (system fail interrupt enable out): when this bit is high, the vmebus system fail interrupt is enabled to the one of the four intx pins. acfleo (ac fail interrupt enable out): when this bit is high, the ac fail interrupt is enabled to the one of the four intx pins. irq7eo (irq7 enable out): when this bit is high, the vmebus irq[7]i_ interrupt is enabled to the one of the four intx pins. irq6eo (irq6 enable out): when this bit is high, the vmebus irq[6]i_ interrupt is enabled to the one of the four intx pins. irq5eo (irq5 enable out): when this bit is high, the vmebus irq[5]i_ interrupt is enabled to the one of the four intx pins. irq4eo (irq4 enable out): when this bit is high, the vmebus irq[4]i_ interrupt is enabled to the one of the four intx pins. irq3eo (irq3 enable out): when this bit is high, the vmebus irq[3]i_ interrupt is enabled to the one of the four intx pins. irq2eo (irq2 enable out): when this bit is high, the vmebus irq[2]i_ interrupt is enabled to the one of the four intx pins. irq1eo (irq1 enable out): when this bit is high, the vmebus irq[1]i_ interrupt is enabled to the one of the four intx pins.
10. registers tsi148 pci/x-to-vme bus bridge user manual 319 80a3020_ma001_08 10.4.72 interrupt status register table 130: interrupt status register register name: ints reset value: 0x00000000 register offset: crg + 450 bits 7 6 5 4 3 2 1 0 31:24 reserved dma1s dma0s 23:16 lm3s lm2s lm1s lm0s mb3s mb2s mb1s mb0s 15:8 reserved perrs verrs vies iacks sysfls acfls 7:0 irq7s irq6s irq5s irq4s irq3s irq2s irq1s reserved interrupt enable status register bits name function pcfs space type reset by reset value 31:26 reserved n/a r n/a 0x00 25 dma1s dmac 1 interrupt enable status r p/s/l 0x00 24 dma0s dmac 0 interrupt enable status r p/s/l 0x00 23 lm3s location monitor 3 interrupt enable status r p/s/l 0x00 22 lm2s location monitor 2 interrupt enable status r p/s/l 0x00 21 lm1s location monitor 1 interrupt enable status r p/s/l 0x00 20 lm0s location monitor 0 interrupt enable status r p/s/l 0x00 19 mb3s mail box 3 interrupt enable status r p/s/l 0x00 18 mb2s mail box 2 interrupt enable status r p/s/l 0x00 17 mb1s mail box 1 interrupt enable status r p/s/l 0x00 16 mb0s mail box 0 interrupt enable status r p/s/l 0x00 15:14 reserved n/a r n/a 0x00 13 perrs pci/x bus error interrupt enable status r p/s/l 0x00 12 verrs vmebus error interrupt enable status r p/s/l 0x00 11 vies vmebus irq edge interrupt enable status r p/s/l 0x00 10 iacks interrupt acknowledge interrupt enable status r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 320 80a3020_ma001_08 dma1s (dma 1 interrupt status): when this bit is high, a dma 1 controller interrupt is pending. dma0s (dma 0 interrupt status): when this bit is high, a dma 0 controller interrupt is pending. lm3s (location monitor 3 interrupt status): when this bit is high, a location monitor 3 interrupt is pending. lm2s (location monitor 2 interrupt status): when this bit is high, a location monitor 2 interrupt is pending. lm1s (location monitor 1 interrupt status): when this bit is high, a location monitor 1 interrupt is pending. lm0s (location monitor 0 interrupt status): when this bit is high, a location monitor 0 interrupt is pending. mb3s (mail box 3 interrupt status): when this bit is high, a mail box 3 interrupt is pending. mb2s (mail box 2 interrupt status): when this bit is high, a mail box 2 interrupt is pending. 9 sysfls system fail interrupt enable status r p/s/l 0x00 8 acfls ac fail interrupt enable status r p/s/l 0x00 7 irq7s irq7 enable status r p/s/l 0x00 6 irq6s irq6 enable status r p/s/l 0x00 5 irq5s irq5 enable status r p/s/l 0x00 4 irq4s irq4 enable status r p/s/l 0x00 3 irq3s irq3 enable status r p/s/l 0x00 2 irq2s irq2 enable status r p/s/l 0x00 1 irq1s irq1 enable status r p/s/l 0x00 0 reserved n/a r n/a 0x00 interrupt enable status register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 321 80a3020_ma001_08 mb1s (mail box 1 interrupt status): when this bit is high, a mail box 1 interrupt is pending. mb0s (mail box 0 interrupt status): when this bit is high, a mail box 0 interrupt is pending. perrs (pci/x bus error interrupt status): when this bit is high, a pci/x bus error interrupt is pending. verrs (vmebus error interrupt status): when this bit is high, a vmebus error interrupt is pending. vies (vmebus irq edge interrupt status): when this bit is high, a vmebus irq edge interrupt is pending. iacks (interrupt acknowledge interrupt status): when this bit is high, an interrupt acknowledge interrupt is pending. sysfls (system fail interrupt status): when this bit is high, a vmebus system fail interrupt is pending. acfls (ac fail interrupt status): when this bit is high, a vmebus ac fail interrupt is pending. irq7s (irq7 status): when this bit is high, a vmebus irq[7]i_ interrupt is pending. irq6s (irq6 status): when this bit is high, a vmebus irq[6]i_ interrupt is pending. irq5s (irq5 status): when this bit is high, a vmebus irq[5]i_ interrupt is pending. irq4s (irq4 status): when this bit is high, a vmebus irq[4]i_ interrupt is pending. irq3s (irq3 status): when this bit is high, a vmebus irq[3]i_ interrupt is pending. irq2s (irq2 status): when this bit is high, a vmebus irq[2]i_ interrupt is pending. irq1s (irq1 status): when this bit is high, a vmebus irq[1]i_ interrupt is pending.
10. registers tsi148 pci/x-to-vme bus bridge user manual 322 80a3020_ma001_08 10.4.73 interrupt clear register table 131: interrupt clear register register name: intc reset value: 0x00000000 register offset: crg + 454 bits 7 6 5 4 3 2 1 0 31:24 reserved dma1c dma0c 23:16 lm3c lm2c lm1c lm0c mb3c mb2c mb1c mb0c 15:8 reserved perrc verrc viec iackc sysflc acflc 7:0 reserved interrupt enable clear register bits name function pcfs space type reset by reset value 31:26 reserved n/a r n/a 0x00 25 dma1c dmac 1 interrupt clear c - 0x00 24 dma0c dmac 0 interrupt clear c - 0x00 23 lm3c location monitor 3 interrupt clear c - 0x00 22 lm2c location monitor 2 interrupt clear c - 0x00 21 lm1c location monitor 1 interrupt clear c - 0x00 20 lm0c location monitor 0 interrupt clear c - 0x00 19 mb3c mail box 3 interrupt clear c - 0x00 18 mb2c mail box 2 interrupt clear c - 0x00 17 mb1c mail box 1 interrupt clear c - 0x00 16 mb0c mail box 0 interrupt clear c - 0x00 15:14 reserved n/a r n/a 0x00 13 perrc pci/x bus error interrupt clear c - 0x00 12 verrc vmebus error interrupt clear c - 0x00 11 viec vmebus irq edge interrupt clear c - 0x00 10 iackc interrupt acknowledge interrupt clear c - 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 323 80a3020_ma001_08 dma1c (dma 1 interrupt clear): when this bit is set, the dma 1 controller interrupt is cleared. this bit always reads zero and writing a zero has no effect. dma0c (dma 0 interrupt clear): when this bit is set, the dma 0 controller interrupt is cleared. this bit always reads zero and writing a zero has no effect. lm3c (location monitor 3 interrupt clear): when this bit is set, the location monitor 3 interrupt is cleared. this bit always reads zero and writing a zero has no effect. lm2c (location monitor 2 interrupt clear): when this bit is set, the location monitor 2 interrupt is cleared. this bit always reads zero and writing a zero has no effect. lm1c (location monitor 1 interrupt clear): when this bit is set, the location monitor 1 interrupt is cleared. this bit always reads zero and writing a zero has no effect. lm0c (location monitor 0 interrupt clear): when this bit is set, the location monitor 0 interrupt is cleared. this bit always reads zero and writing a zero has no effect. mb3c (mail box 3 interrupt clear): when this bit is set, the mail box 3 interrupt is cleared. this bit always reads zero and writing a zero has no effect. mb2c (mail box 2 interrupt clear): when this bit is set, the mail box 2 interrupt is cleared. this bit always reads zero and writing a zero has no effect. mb1c (mail box 1 interrupt clear): when this bit is set, the mail box 1 interrupt is cleared. this bit always reads zero and writing a zero has no effect. mb0c (mail box 0 interrupt clear): when this bit is set, the mail box 0 interrupt is cleared. this bit always reads zero and writing a zero has no effect. perrc (pci/x bus error interrupt clear): when this bit is set, the pci/x bus error interrupt is cleared. this bit always reads zero and writing a zero has no effect. verrc (vmebus error interrupt clear): when this bit is set, th e vmebus error interrupt is cleared. this bit always reads zero and writing a zero has no effect. 9 sysflc system fail interrupt clear c - 0x00 8 acflc ac fail interrupt clear c - 0x00 7:0 reserved n/a r n/a 0x00 interrupt enable clear register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 324 80a3020_ma001_08 viec (vmebus irq edge interrupt clear): when this bit is set, the vmebus irq edge interrupt is cleared. this bit always reads zero and writing a zero has no effect. iackc (interrupt acknowledge interrupt clear): when this bit is set, the vmebus interrupt acknowledge interrupt is cleared. this bit always reads zero and writing a zero has no effect. sysflc (system fail interrupt clear): when this bit is set, the vmebus system fail interrupt is cleared. this bit always reads zero and writing a zero has no effect. acflc (ac fail interrupt clear): when this bit is set, the ac fail interrupt is cleared. this bit always reads zero and writing a zero has no effect.
10. registers tsi148 pci/x-to-vme bus bridge user manual 325 80a3020_ma001_08 10.4.74 interrupt map 1 register dma1m (dma 1 interrupt map): these bits indicate which in tx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. dma0m (dma 0 interrupt map): these bits indicate which in tx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. table 132: interrupt map 1 register register name: intm1 reset value: 0x00000000 register offset: crg + 458 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved dma1m dma0m 15:8 lm3m lm2m lm1m lm0m 7:0 mb3m mb2m mb1m mb0m interrupt map 1 register bits name function pcfs space type reset by reset value 31:20 reserved n/a r n/a 0x00 19:18 dma1m dma 1 interrupt map r/w p/s/l 0x00 17:16 dma0m dma 0 interrupt map r/w p/s/l 0x00 15:14 lm3m location monitor 3 map r/w p/s/l 0x00 13:12 lm2m location monitor 2 map r/w p/s/l 0x00 11:10 lm1m location monitor 1 map r/w p/s/l 0x00 9:8 lm0m location monitor 0 map r/w p/s/l 0x00 7:6 mb3m mail box 3 map r/w p/s/l 0x00 5:4 mb2m mail box 2 map r/w p/s/l 0x00 3:2 mb1m mail box 1 map r/w p/s/l 0x00 1:0 mb0m mail box 0 map r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 326 80a3020_ma001_08 lm3m (location monitor 3 map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. lm2m (location monitor 2 map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. lm1m (location monitor 1 map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. lm0m (location monitor 0 map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. mb3m (mail box 3 map): these bits indicate which intx si gnal line the interrupt is routed to. the values 0 - 3 maps the interr upts to inta_ - intd_ respectively. mb2m (mail box 2 map): these bits indicate which intx si gnal line the interrupt is routed to. the values 0 - 3 maps the interr upts to inta_ - intd_ respectively. mb1m (mail box 1 map): these bits indicate which intx si gnal line the interrupt is routed to. the values 0 - 3 maps the interr upts to inta_ - intd_ respectively. mb0m (mail box 0 map): these bits indicate which intx si gnal line the interrupt is routed to. the values 0 - 3 maps the interr upts to inta_ - intd_ respectively.
10. registers tsi148 pci/x-to-vme bus bridge user manual 327 80a3020_ma001_08 10.4.75 interrupt map 2 register table 133: interrupt map 2 register register name: intm2 reset value: 0x00000000 register offset: crg + 45c bits 7 6 5 4 3 2 1 0 31:24 reserved perrm verrm 23:16 viem iackm sysflm acflm 15:8 irq7m irq6m irq5m irq4m 7:0 irq3m irq2m irq1m reserved interrupt map 2 register bits name function pcfs space type reset by reset value 31:20 reserved n/a r n/a 0x00 27:26 perrm pci/x bus error interrupt map r/w p/s/l 0x00 25:24 verrm vmebus error interrupt map r/w p/s/l 0x00 23:22 viem vmebus irq edge interrupt map r/w p/s/l 0x00 21:20 iackm interrupt acknowledge interrupt map r/w p/s/l 0x00 19:18 sysflm system fail interrupt map r/w p/s/l 0x00 17:16 acflm ac fail interrupt map r/w p/s/l 0x00 15:14 irq7m irq7 map r/w p/s/l 0x00 13:12 irq6m irq6 map r/w p/s/l 0x00 11:10 irq5m irq5map r/w p/s/l 0x00 9:8 irq4m irq4 map r/w p/s/l 0x00 7:6 irq3m irq3 map r/w p/s/l 0x00 5:4 irq2m irq27 map r/w p/s/l 0x00 3:2 irq1m irq1 map r/w p/s/l 0x00 1:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 328 80a3020_ma001_08 perrm (pci/x bus error interrupt map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. verrm (vmebus error interrupt map): these bits indicate whic h intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. viem (vmebus irq edge interrupt map): these bits indicate whic h intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. iackm (interrupt acknowl edge interrupt map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. sysflm (system fail interrupt map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. acflm (ac fail interrupt map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. irq7m (irq7 map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. irq6m (irq6 map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. irq5m (irq5 map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. irq4m (irq4 map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. irq3m (irq3 map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. irq2m (irq2 map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively. irq1m (irq1 map): these bits indicate which intx signal line the interrupt is routed to. the values 0 - 3 maps the interrupts to inta_ - intd_ respectively.
10. registers tsi148 pci/x-to-vme bus bridge user manual 329 80a3020_ma001_08 10.4.76 dma control (0-1) registers the dma control register (dctl x ) provides the control fields for the dma function. table 134: dma control (0-1) register register name: dctl x reset value: 0x00000000 register offset: dctl0: crg + 0x500 dctl1: crg + 0x580 bits 7 6 5 4 3 2 1 0 31:24 reserved abt pau dgo reserved 23:16 mod reserved vfar pfar 15:8 reserved vbks reserved vbot 7:0 reserved pbks reserved pbot dma control (0-1) re g ister bits name function pcfs space type reset by reset value 31:28 reserved n/a r n/a 0x00 27 abt abort r/s p/s/l 0x00 26 pau pause r/s p/s/l 0x00 25 dgo dma go r/s p/s/l 0x00 26 reserved n/a r n/a 0x00 23 mod mode r/w p/s/l 0x00 22:18 reserved n/a r n/a 0x00 17 vfar vme flush on aborted read r/w p/s/l 0x00 16 pfar pci/x flush on aborted read r/w p/s/l 0x00 15 reserved n/a r n/a 0x00 14:12 vbks vmebus block size r/w p/s/l 0x00 11 reserved n/a r n/a 0x00 10:8 vbot vmebus back-off timer r/w p/s/l 0x00 7 reserved n/a r n/a 0x00 6:4 pbks pci/x block size r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 330 80a3020_ma001_08 abt ( abort): writing a one to this field aborts a dma tr ansaction. an abort is considered an unrecoverable operation to a dma transaction, meaning that an aborted transaction may not be restarted. when issuing an abort, both th e pci/x and/or vmebus masters are immediately stopped and all fifo contents are invalidated. once the abort has taken affect, the dsta bsy bit is cleared and the don and err bits is set. reading this field always returns a zero. pau ( pause): writing a one to this field pauses a dma transaction. this bit is only applicable to linked-list-mode transactions . when pausing a dma transaction, the dma controller stops at the completion of the current linked-list transfer. if the pause took affect before the completion of a transaction, then the dtsa. the pau field is set once the dma controller reaches the paused state. a paused transaction may be restarted by writing a one to the dgo field. reading this field always returns a zero. dgo ( dma go): writing a one to this field starts a dma transaction. reading this field always returns a zero. mod ( mode): this bit establishes the type of dma tr ansaction to be performed. if set, a direct-mode transaction is performed. a direct-mode transaction performs one transfer according to the contents of the dsad, ds at, ddad, ddat, and dcnt registers. if cleared, a linked-list-mode transaction is performed. a linked-list-mode transaction performs multiple transfers that are driven by a list of descriptors stored in pci/x memory space. a linked-list-mode transaction obtains the first descriptor from the starting address placed within the dnla register. vfar ( vme flush on aborted read): if this bit is set and a vmebus cycle is terminated with an exception, any data remaining in the fifo is transferred to the destination. if this bit is cleared and a vmebus cycle is terminated with an exception, any data remaining in the dma fifo is discarded. 3 reserved n/a r n/a 0x00 2:0 pbot pci/x back-off timer r/w p/s/l 0x00 abort (abt) has authority over pause (pau). if a commanded pause is followed by an commanded abort, then the dma controller honors the commanded abort. dma control (0-1) re g ister bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 331 80a3020_ma001_08 pfar ( pci/x flush on aborted read): if this bit is set and a pci/x bus cycle is terminated with an exception, any data remaining in the fifo is transferred to the destination. if this bit is cleared and a pci/x bus cycle is terminated with an exception, any data remaining in the dma fifo is discarded. vbks ( vmebus block size): this field is used to control the vmebus block size when the source is the vmebus. the encoding of this field is shown in table 135 vbot ( vmebus back-off timer): the back-off timer determines how long the dma controller waits before requesting the next block of data. this field controls the internal data flow between the dma controller and the vme master module. the dma does not attempt to read the next block until after the back-off timer has expired. to control the amount of time the vme master is allowed to spend on the bus during dma transfers please see the vme master control register ( table 10.4.34 on page 255 ). table 135: dctl bks encoding vbks transfer size (bytes) 000b 32 001b 64 010b 128 011b 256 100b 512 101b 1024 110b 2048 111b 4096
10. registers tsi148 pci/x-to-vme bus bridge user manual 332 80a3020_ma001_08 table 136 shows the encoding for this field. pbks ( pci/x block size): this field is used to control the pci/x bus block size when the source is the pci/x bus. the encoding of this field is shown in table 137 . pbot ( pci/x back-off timer): the back-off timer determines how long the dma waits before requesting the next block of data. this fi eld controls the internal data flow between the dma controller and the pci/x master. the dma does not attempt to read the next block until after the back-off timer has expired. table 136: dctl vbot encoding vbot back-off time 000b 0 s 001b 1 s 010b 2 s 011b 4 s 100b 8 s 101b 16 s 110b 32 s 111b 64 s table 137: dctl pbks encoding pbks transfer size bytes 000b 32 001b 64 010b 128 011b 256 100b 512 101b 1024 110b 2048 111b 4096
10. registers tsi148 pci/x-to-vme bus bridge user manual 333 80a3020_ma001_08 table 138 shows the encoding for this field. table 138: dctl pbot encoding pbot back-off time 000b 0 s 001b 1 s 010b 2 s 011b 4 s 100b 8 s 101b 16 s 110b 32 s 111b 64 s
10. registers tsi148 pci/x-to-vme bus bridge user manual 334 80a3020_ma001_08 10.4.77 dma status (0-1) registers the dma status register (dsta) provides the status fields for the dma function. the bsy field represents the current state of the dma controller, and the remaining fields indicate completion status. when the dma controller is starting a transaction (that is, the dgo field is set) the bsy field is asserted and all of the completion status fields are cleared. the bsy field remains asserted and the completion status fields remain cleared throughout the entire dma transaction. once the dma controller is finish ed, then the bsy field is cleared and only one of the completion status fields (don, pau, abt, or err) is asserted. a functional interrupt is sent to the exception module whenever the bsy field transitions to the deasserted state. the completion status fields are prioritized from le ft to right, with the left most status field holding the highest priority. for example, if the dma controller incurs a simultaneous err error and an abt, then the dsta register only reflects the err completion status. if the dma controller incurs multiple errors th at are not simultaneously detected, then the dsta register only reflects the status pertaining to the first occurring error. this is of particular importance to the pau and abt fields. if an error is detected before the pause or abort takes affect, then the dsta register onl y reflects the status pertaining to the error. table 139: dma status (0-1) register register name: dstax reset value: 0x00000000 register offset: dcsta0: crg + 0x504 dcsta1: crg + 0x584 bits 7 6 5 4 3 2 1 0 31:24 reserved err abt pau don bsy 23:16 reserved errs reserved ert1 ert0 15:8 reserved 7:0 reserved dma status (0-1) register bits name function pcfs space type reset by reset value 31:29 reserved n/a r n/a 0x00 28 err error r p/s/l 0x00 27 abt abort r p/s/l 0x00 26 pau pause r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 335 80a3020_ma001_08 err ( error ): this read-only field is set if the dma controller receives an error signal from the pci/x bus or vmebus. additional information is provided in the errs and ert fields. abt ( abort ): this read-only field is set if the dm a controller has successfully completed a commanded abort. a successful command abort must meet the following criteria: 1. a write of a logic 1 to the abt field. 2. the dma controller has not received any other errors (err) between the time the transaction was started and the time that th e dma controller goes to the idle state. 3. the commanded abort took place before the dma controller was able to complete a transaction. pau ( pause ): this read-only field is set if the dm a controller has successfully completed a commanded pause. a successful command pause must meet the following criteria: 1. a write of a logic 1 to the pau field. 2. the dma controller has not received any other errors (err) between the time the transaction was started and the time that th e dma controller goes to the idle state. 3. the dma controller has not been issued a commanded abort. 4. the commanded pause took place before the dma controller was able to complete a transaction. 25 don done r p/s/l 0x00 24 bsy busy r p/s/l 0x00 23:21 reserved n/a r n/a 0x00 20 errs error source r p/s/l 0x00 19:18 reserved n/a r n/a 0x00 17 ert1 error type r p/s/l 0x00 16 ert0 error type r p/s/l 0x00 15:0 reserved n/a r n/a 0x00 dma status (0-1) register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 336 80a3020_ma001_08 don ( done ): this read-only field is set if the dma controller has successfully completed a dma transaction. a successful transa ction must meet the following criteria: 1. the dma controller has not received any other errors (err) between the time the transaction was started and the time that th e dma controller goes to the idle state. 2. if a commanded abort was issued, then it did not take affect before the transaction was completed. 3. if a commanded pause was issued, then it did not take affect before the transaction was completed. bsy ( busy ): this read-only field reflects the status of the dma controller. if set, the dma controller is currently processing a dma transaction. if cleared, the dma controller has completed a previous transaction and is now idle. errs ( error source ): when the err bit is set, this b it indicates the source of the error. when this bit is set, the pci/x bus was the sour ce of the error. when this bit is clear, the vmebus was the source of the error. ert ( error type ): when the err bit is set, these bits indicate the type of error received. table 140: dsta ert encoding ers ert error type 0 00b bus error: sct, blt, mblt, 2evme even data, 2esst 0 01b bus error: 2evme odd data 0 10b slave termination: 2evme even data, 2esst read 0 11b slave termination: 2evme odd data, 2esst read last word invalid 1 00b pci/x bus error 1 01b reserved 1 10b reserved 1 11b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 337 80a3020_ma001_08 10.4.78 dma current source address upper (0-1) registers this is a read-only register that contains the upper bits (63:32) of the current source address for a dma transfer. if the source is vmebus sp ace, then this field represents a vmebus address. if the source is pci/x space, then this field represents a pci/x address. software can read this register after a dma error to determine how far along a dma transfer went before the error occurred. if vmebus error occurs during a fifo fill, w ith the vmebus as the transfer source, this register represents the vmebus address at which a read error occurred. if a pci/x bus error occurs during a fifo fill, with the pci/x bus as the transfer source, this register represents the pci/x address at which a read error occurred. table 141: dma current source address upper (0-1) register register name: dcsaux reset value: 0x00000000 register offset: dcsau0: crg + 0x508 dcsau1: crg + 0x588 bits 7 6 5 4 3 2 1 0 31:0 dcsaux dma current source address upper (0-1) register bits name function pcfs space type reset by reset value 31:0 dcsaux dma current source address upper r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 338 80a3020_ma001_08 10.4.79 dma current source address lower (0-1) registers this is a read-only register that contains the lo wer bits (31:0) of the current source address for a dma transfer. if the source is vmebus space, then this field represents a vmebus address. if the source is pci/x space, then this field represents a pci/x address. software can read this register after a dma error to determine how far along a dma transfer went before the error occurred. if a vmebus error occurs during a fifo fill, with the vmebus as the transfer source, this register represents the vmebus address at which a read error occurred. if a pci/x bus error occurs during a fifo fill, with the pci/x bus as the transfer source, this register represents the pci/x address at which a read error occurred. table 142: dma current source address lower (0-1) register register name: dcsalx reset value: 0x00000000 register offset: dcsal0: crg + 0x50c dcsal1: crg + 0x58c bits 7 6 5 4 3 2 1 0 31:0 dcsalx dma current source address upper (0-1) register bits name function pcfs space type reset by reset value 31:0 dcsalx dma current source address lower r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 339 80a3020_ma001_08 10.4.80 dma current destination address upper (0-1) registers this is a read-only register that contains th e upper bits (63:32) of the current destination address for a dma transfer. if the destination is vmebus space, then this field represents a vmebus address. if the destination is pci/x space , then this field represents a pci/x address. software can read this register after a dma error to determine how far along a dma transfer went before the error occurred. if a vmebus error occurs during a fifo empty, with the vmebus as the transfer destination, this register represents the vmebus address at which a read error occurred. if a pci/x bus error occurs during a fifo empty, with the pci/x bus as the transfer destination, this register represents the pci/x address at which a read error occurred. table 143: dma current destination address upper (0-1) register register name: dcdaux reset value: 0x00000000 register offset: dcdau0: crg + 0x510 dcdau1: crg + 0x590 bits 7 6 5 4 3 2 1 0 31:0 dcdaux dma current destination upper (0-1) register bits name function pcfs space type reset by reset value 31:0 dcdaux dma current destination address upper r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 340 80a3020_ma001_08 10.4.81 dma current destination address lower (0-1) registers this is a read-only register that contains th e lower bits (31:0) of the current destination address for a dma transfer. if the destination is vmebus space, then this field represents a vmebus address. if the destination is pci/x space , then this field represents a pci/x address. software can read this register after a dma error to determine how far along a dma transfer went before the error occurred. if a vmebus error occurs during a fifo empty, with the vmebus as the transfer destination, this register represents the vmebus address at which a write error occurred. if a pci/x bus error occurs during a fifo empty, with the pci/x bus as the transfer destination, this register represents the pci/x address at which a write error occurred. table 144: dma current destination address lower (0-1) register register name: dcdalx reset value: 0x00000000 register offset: dcdal0: crg + 0x514 dcdal1: crg + 0x594 bits 7 6 5 4 3 2 1 0 31:0 dcdalx dma current destination address lower (0-1) register bits name function pcfs space type reset by reset value 31:0 dcdalx dma current destination address lower r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 341 80a3020_ma001_08 10.4.82 dma current link address upper (0-1) registers this is a read-only register that contains the upper bits (63:32) of the current linked-list-mode descriptor address for a dma command. this always represents a pci/x address. software can read this register after a dma error to determine which command in the linked list was being executed when the error occurred. table 145: dma current link address upper (0-1) register register name: dclaux reset value: 0x00000000 register offset: dclau0: crg + 0x518 dclau1: crg + 0x598 bits 7 6 5 4 3 2 1 0 31:0 dclaux dma current link address upper (0-1) register bits name function pcfs space type reset by reset value 31:0 dclaux dma current link address upper r p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 342 80a3020_ma001_08 10.4.83 dma current link address lower (0-1) registers this is a read-only register that contains the lower bits (31:6) of the current linked-list-mode descriptor address for a dma command. this always represents a pci/x address. software can read this register after a dma error to determine which command in the linked list was being executed when the error occurred. table 146: dma current link address lower (0-1) register register name: dclalx reset value: 0x00000000 register offset: dclal0: crg + 0x51c dclal1: crg + 0x59c bits 7 6 5 4 3 2 1 0 31:24 dclalx 23:16 dclalx 15:8 dclalx 7:0 dclalx reserved dma current link address lower (0-1) register bits name function pcfs space type reset by reset value 31:6 dclalx dma current link address lower r p/s/l 0x00 5:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 343 80a3020_ma001_08 10.4.84 dma source address upper (0-1) registers this register contains the upper bits (63:32) of the source address for a dma transfer. if the source is vmebus space then this field represents a vmebus address. if the source is pci/x space then this field represents a pci/x address. software programs this register when pe rforming direct-mode transactions. when performing linked-list-mode transactions, this register is automatically loaded from the source address field of the current descriptor. table 147: dma source address upper (0-1) register register name: dsaux reset value: 0x00000000 register offset: dsau0: crg + 0x520 dsau1: crg + 0x5a0 bits 7 6 5 4 3 2 1 0 31:0 dsaux dma source address upper (0-1) register bits name function pcfs space type reset by reset value 31:0 dsaux dma source address upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 344 80a3020_ma001_08 10.4.85 dma source address lower (0-1) registers this register contains the lower bits (31:0) of the source address for a dma transfer. if the source is vmebus space then this field represents a vmebus address. if the source is pci/x space then this field represents a pci/x address. software programs this register when pe rforming direct-mode transactions. when performing linked-list-mode transactions, this register is automatically loaded from the source address field of the current descriptor. table 148: dma source address lower (0-1) register register name: dcalx reset value: 0x00000000 register offset: dsal0: crg + 0x524 dsal1: crg + 0x5a4 bits 7 6 5 4 3 2 1 0 31:0 dsalx dma source address lower (0-1) register bits name function pcfs space type reset by reset value 31:0 dsalx dma source address lower r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 345 80a3020_ma001_08 10.4.86 dma destination address upper (0-1) registers this register contains the upper bits (63:32) of the destination address for a dma transfer. if the destination is vmebus space then this field represents a vmebus address. if the destination is pci/x space then this field represents a pci/x address. software programs this register when pe rforming direct-mode transactions. when performing linked-list-mode transactions, this register is automatically loaded from the destination address field of the current descriptor. table 149: dma destination address upper (0-1) register register name: ddaux reset value: 0x00000000 register offset: ddaux: crg + 0x528 ddaux: crg + 0x5a8 bits 7 6 5 4 3 2 1 0 31:0 ddau dma destination address upper (0-1) register bits name function pcfs space type reset by reset value 31:0 ddaux dma destination address upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 346 80a3020_ma001_08 10.4.87 dma destination address lower (0-1) registers this register contains the lower bits (31:0) of the destination address for a dma transfer. if the destination is vmebus space then this field represents a vmebus address. if the destination is pci/x space then this field represents a pci/x address. software programs this register when pe rforming direct-mode transactions. when performing linked-list-mode transactions, this register is automatically loaded from the destination address field of the current descriptor. table 150: dma destination address lower (0-1) register register name: ddalx reset value: 0x00000000 register offset: ddalx: crg + 0x52c ddalx: crg + 0x5ac bits 7 6 5 4 3 2 1 0 31:0 ddal dma destination address lower (0-1) register bits name function pcfs space type reset by reset value 31:0 ddal dma destination address lower r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 347 80a3020_ma001_08 10.4.88 dma source attribute (0-1) registers the dma source attribute register (dsat) contains the source attributes for a dma transfer. not all fields are used for all transfer types. fields that do not pertain to a particular transfer type are ignored. software programs this register when pe rforming direct-mode transactions. when performing linked-list-mode transactions, this register is automatically loaded from the source attribute field of the current descriptor . table 151: dma source attribute (0-1) register register name: dsatx reset value: 0x00000000 register offset: dsat0: crg + 0x530 dsat1: crg + 0x5b0 bits 7 6 5 4 3 2 1 0 31:24 reserved typ1 typ0 reserved psz nip 23:16 reserved 15:8 reserved sstm1 sstm0 tm2 tm1 tm0 7:0 dbw1 dbw0 sup pgm amode3 amode2 amode1 amode0 dma source attribute (0-1) register bits name function pcfs space type reset by reset value 31:30 reserved n/a r n/a 0x00 29 typ1 type r/w p/s/l 0x00 28 typ0 type r/w p/s/l 0x00 27:26 reserved n/a r n/a 0x00 25 psz pattern size r/w p/s/l 0x00 24 nip no increment pattern r/w p/s/l 0x00 23:13 reserved n/a r n/a 0x00 12 sstm1 2esst mode r/w p/s/l 0x00 11 sstm0 2esst mode r/w p/s/l 0x00 10 tm2 transfer mode r/w p/s/l 0x00 9 tm1 transfer mode r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 348 80a3020_ma001_08 typ (type ): this field indicates the type of source to be used for a dma transfer. different fields within the dsat register are used depending on the type of source selected. table 152 shows the different source types and the associated fields within the dsat register that apply. psz (pattern size ): if set, the data size used during data pattern transfers is bytes (8-bit). if cleared, the data size is words (32-bit). this field only applies to the generation of the data patterns used for a transfer. it does not specif y how the patterns are actually placed into the destination space. (that is, selecting a byte pattern size does not result in a stream of single-beat bus cycles.) nip (no increment pattern ): if set, and the source is a da ta pattern, then the data pattern, will not be incremented. if cleared and the source is a data pattern, the data pattern will be incremented. 8 tm0 transfer mode r/w p/s/l 0x00 7 dbw1 vmebus data bus width r/w p/s/l 0x00 6 dbw0 vmebus data bus width r/w p/s/l 0x00 5 sup vmebus supervisory mode r/w p/s/l 0x00 4 pgm vmebus program mode r/w p/s/l 0x00 3 amode3 address mode r/w p/s/l 0x00 2 amode2 address mode r/w p/s/l 0x00 1 amode1 address mode r/w p/s/l 0x00 0 amode0 address mode r/w p/s/l 0x00 table 152: dsat typ encoding typ dma source applicable fields nip psz sstm tm dbw sup pgm amode 00b pci/x bus 01b vmebus x x x x x x 1xb data pattern x x dma source attribute (0-1) register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 349 80a3020_ma001_08 sstm (2esst mode ): this field defines the 2esst transfer rate. tm (transfer mode ): this field defines the vmebus transfer mode. dbw (vmebus data bus width ): these bits define the maximum data bus width for vmebus transfers initiated by the dma controller. these bits apply to sct and blt transfers. mblt, 2evme and 2esst transfers are always 64-bit. table 153: 2esst transfer rate sstm transfer rate 00b 160 mb/s 01b 267 mb/s 10b 320 mb/s 11b reserved table 154: vmebus transfer mode tm transfer mode 000b sct 001b blt 010b mblt 011b 2evme 100b 2esst 101b 2esst broadcast 110b reserved 111b reserved table 155: vmebus data bus width dwb data bus width 00b 16 bit 01b 32 bit 10b reserved 11b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 350 80a3020_ma001_08 sup (vmebus supervisory mode ): when this bit is set the am code indicates supervisory access. when this bit is cleared the am code indicates non-privileged access. pgm (vmebus program mode ): when this bit is set the am code indicates program access. when this bit is cleared the am code indicates data access. amode (address mode ): this field defines the vmebus address mode. when the user1-user4 modes are used, the am[1] bit is defined by the sup bit and the am[0] bit is defined by the pgm bit. table 156: vmebus address mode amode address mode 0000b a16 0001b a24 0010b a32 0011b reserved 0100b a64 0101b cr/csr 0110b reserved 0111b reserved 1000b user1 (am 0100xxb) 1001b user2 (am 0101xxb) 1010b user3 (am 0110xxb) 1011b user4 (am 0111xxb) 1100b reserved 1101b reserved 1110b reserved 1111b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 351 80a3020_ma001_08 10.4.89 dma destination attribute (0-1) registers the dma destination attribute register (ddat) contains the destination attributes for a dma transfer. not all fields are used for all tr ansfer types. fields that do not pertain to a particular transfer type are ignored. software programs this register when pe rforming direct-mode transactions. when performing linked-list-mode transactions, this register is automatically loaded from the destination attribute field of the current descriptor . table 157: dma destination attribute (0-1) register register name: ddatx reset value: 0x00000000 register offset: ddatx: crg + 0x534 ddatx: crg + 0x5b4 bits 7 6 5 4 3 2 1 0 31:24 reserved typ reserved 23:16 reserved 15:8 reserved sstm1 sstm0 tm2 tm1 tm0 7:0 dbw1 dbw0 sup pgm amode3 amode2 amode1 amode0 inbound translation attribute (0-7) register bits name function pcfs space type reset by reset value 31:29 reserved n/a r n/a 0x00 28 typ type r/w p/s/l 0x00 27:13 reserved n/a r n/a 0x00 12 sstm1 2esst mode r/w p/s/l 0x00 11 sstm0 2esst mode r/w p/s/l 0x00 10 tm2 transfer mode r/w p/s/l 0x00 9 tm1 transfer mode r/w p/s/l 0x00 8 tm0 transfer mode r/w p/s/l 0x00 7 dbw1 vmebus data bus width r/w p/s/l 0x00 6 dbw0 vmebus data bus width r/w p/s/l 0x00 5 sup vmebus supervisory mode r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 352 80a3020_ma001_08 typ (type ): this field indicates the type of dest ination to be used for a dma transfer. different fields within the ddat register ar e used depending on the type of destination selected. table 158 shows the different destination types and the associated fields within the ddat register that apply. sstm (2esst mode ): this field defines the 2esst transfer rate. 4 pgm vmebus program mode r/w p/s/l 0x00 3 amode3 address mode r/w p/s/l 0x00 2 amode2 address mode r/w p/s/l 0x00 1 amode1 address mode r/w p/s/l 0x00 0 amode0 address mode r/w p/s/l 0x00 table 158: ddat typ encoding typ dma destination applicable fields sstm tm dbw sup pgm amode 0 pci/x bus 1 vmebus xxxxx x table 159: 2esst transfer rate sstm transfer rate 00b 160 mb/s 01b 267 mb/s 10b 320 mb/s 11b reserved inbound translation attribute (0-7) register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 353 80a3020_ma001_08 tm (transfer mode ): this field defines the vmebus transfer mode. dbw (vmebus data bus width ): these bits define the maximum data bus width for vmebus transfers initiated by the dma controller. sup (vmebus supervisory mode ): when this bit is set the am code indicates supervisory access. when this bit is cleared the am code indicates non-privileged access. pgm (vmebus program mode ): when this bit is set the am code indicates program access. when this bit is cleared th e am code indicates data access. table 160: vmebus transfer mode tm transfer mode 000b sct 001b blt 010b mblt 011b 2evme 100b 2esst 101b reserved 110b reserved 111b reserved table 161: vmebus data bus width dwb data bus width 00b 16 bit 01b 32 bit 10b reserved 11b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 354 80a3020_ma001_08 amode (address mode ): this field defines the vmebus address mode. when the user1-user4 modes are used, the am[1] bit is defined by the sup bit and the am[0] bit is defined by the pgm bit. table 162: vmebus address mode amode address mode 0000b a16 0001b a24 0010b a32 0011b reserved 0100b a64 0101b cr/csr 0110b reserved 0111b reserved 1000b user1 (am 0100xxb) 1001b user2 (am 0101xxb) 1010b user3 (am0110xxb) 1011b user4 (am 0111xxb) 1100b reserved 1101b reserved 1110b reserved 1111b reserved
10. registers tsi148 pci/x-to-vme bus bridge user manual 355 80a3020_ma001_08 10.4.90 dma next link address upper (0-1) registers these are the upper address bits (63:32) of the next descriptor when using linked-list-mode. this is a pci/x address. this register is not used when performing direct-mode transactions. when starting a linked-list-mode transaction, software programs this register with the address of the first linked-list-mode descriptor. when continuing a linked-list-mode transaction, the register is automatically loaded from the next link address field of the current descriptor. table 163: dma next link address upper (0-1) register register name: dnlaux reset value: 0x00000000 register offset: dnlaux: crg + 0x538 dnlaux: crg + 0x5b8 bits 7 6 5 4 3 2 1 0 31:0 dnlau dma next link address upper (0-1) register bits name function pcfs space type reset by reset value 31:0 dnlau dma next link address upper r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 356 80a3020_ma001_08 10.4.91 dma next link address lower (0-1) registers dnlal (dma next link address lower ): these are the lower address bits (31:3) of the next descriptor when using linked-list-mode. this is a pci/x address. this register is not used when performing direct-mode transactions. when starting a linked-list-mode transaction, software programs this register with the address of the first linked-list-mode descriptor. when continuing a linked-list-mode transaction, the register is automatically loaded from the next link address field of the current descriptor. lla (last link address ): if set, the current descriptor is the last descriptor of a linked-list transaction. if cleared, the current descriptor is not the last descriptor. table 164: dma next link address lower (0-1) register register name: dnlalx reset value: 0x00000000 register offset: dnlal0: crg + 0x53c dnlal1: crg + 0x5bc bits 7 6 5 4 3 2 1 0 31:24 dnlalx 23:16 dnlalx 15:8 dnlalx 7:0 dnlalx reserved lla dma next link address lower (0-1) register bits name function pcfs space type reset by reset value 31:3 dnlalx dma next link address lower r/w p/s/l 0x00 2:1 reserved n/a r n/a 0x00 0 lla last link address r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 357 80a3020_ma001_08 10.4.92 dma count (0-1) registers this register contains the byte count for a dm a transfer. a zero value indicates that zero bytes are transferred. as the dma transfer progresses, the dcnt register is decremented. when a dma transfer completes with out errors, the final dcnt value is zero. software programs this register when pe rforming direct-mode transactions. when performing linked-list-mode transactions, this register is automatically loaded from the count field of the current descriptor. table 165: dma count (0-1) register register name: dcntx reset value: 0x00000000 register offset: dcntx: crg + 0x540 dcntx: crg + 0x5c0 bits 7 6 5 4 3 2 1 0 31:0 dcntx dma count (0-1) register bits name function pcfs space type reset by reset value 31:0 dcnt dma count register r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 358 80a3020_ma001_08 10.4.93 dma destination broadcast select (0-1) registers this register contains the 2esst broadcast select bits. each bit corresponds to one of the 21 possible slaves. the 2esst master broadcasts th is field during address phase three. register bit 11 corresponds to vmebus address line a21 and register bit 31 corresponds to vmebus address line a1. software programs this register when pe rforming direct-mode transactions. when performing linked-list-mode transactions, this register is automatically loaded from the broadcast select field of the current descriptor. table 166: dma destination broadcast select (0-1) register register name: ddbsx reset value: 0x00000000 register offset: ddbsx: crg + 0x544 ddbsx: crg + 0x5c4 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved ddbs 15:8 ddbs 7:0 ddbs dma destination broadcast select (0-1) register bits name function pcfs space type reset by reset value 31:21 reserved n/a r n/a 0x00 20:0 ddbs dma destination broadcast select register r/w p/s/l 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 359 80a3020_ma001_08 10.4.94 gcsr register group this section defines the global control and st atus registers (gcsr). these registers are accessible from the pci/x bus or vmebus. th e vmebus address and address space is programmable. rmw cycles from the vm ebus are not guarantied indivisible. 10.4.95 vendor id / device id registers devi (device id ): this register is a read only register that uniquely identifies this particular device. the tsi148 always returns 0x0148. veni (vendor id ): this register is a read-only register that identifies the manufacturer of the device. this identifier is allocated by the pci/x special interest group to ensure uniqueness. 0x10e3 has been assigned to motorola and is hard wired as a read-only value. table 167: vendor id / device id register register name: devi/veni reset value: 0x014810e3 register offset: gcsr + 0x00 - crg + 0x600 bits 7 6 5 4 3 2 1 0 31:24 devi 23:16 devi 15:8 veni 7:0 veni vendor id / device id register bits name function pcfs space type reset by reset value 31:21 devi device id r - 0x0148 20:0 veni vendor id r - 0x10e3
10. registers tsi148 pci/x-to-vme bus bridge user manual 360 80a3020_ma001_08 10.4.96 control and status register table 168: control and status register register name: gctrl reset value: 0x register offset: gcsr + 0x04 - crg + 0x604 bits 7 6 5 4 3 2 1 0 31:24 lrst sfailen bdfails scons men reserved 23:16 lmi3s lmi2s lmi1s lmi0s mbi3s mbi2s mbi1s mbi0s 15:8 reserved gap ga 7:0 revid control and status register bits name function pcfs space type reset by reset value 31 lrst local reset r/w p/s 0x00 30 sfailen system fail enable r/w p/s 0x xx 29 bdfails board fail status r p/s/l 0x01 28 scons system controller status r p 0x xx 27 men module enable r/w p/s/l 0x00 26:24 reserved n/a r n/a 0x00 23 lmi3s location monitor interrupt 3 status r p/s/l 0x00 22 lmi2s location monitor interrupt 2 status r p/s/l 0x00 21 lmi1s location monitor interrupt 1 status r p/s/l 0x00 20 lmi0s location monitor interrupt 0 status r p/s/l 0x00 19 mbi3s mail box interrupt 3 status r p/s/l 0x00 18 mbi2s mail box interrupt 2 status r p/s/l 0x00 17 mbi1s mail box interrupt 1 status r p/s/l 0x00 16 mbi0s mail box interrupt 0 status r p/s/l 0x00 15:14 reserved n/a r n/a 0x00 13 gap geographic address parity r - 0x xx
10. registers tsi148 pci/x-to-vme bus bridge user manual 361 80a3020_ma001_08 lrst (local reset ): when this bit is set. the lrsto_ signal is asserted. when this bit is cleared, the lrsto_ signal is not asserted. wh en this bit is set and cleared, the tsi148 ensures the minimum pulse wi dth for local reset is met. sfailen (system fail enable ): when this bit is set and th e bdfail_ signal is asserted, the sfailo signal line is asserted. when this bit is cleared, the sfailo signal line is not asserted. the initial valu e of this bit is a configurati on option. the system fail enable bit is al so accessible in the cr/csr. bdfails (board fail status ): reading a one indicates the bdfail_ signal is asserted. reading a zero indicates the bdfail_ signal is not asserted. scons (system controller status ): reading a one indicates, the vmebus system controller is enabled. men (module enable): this is a read/write bit that can be used to indicate a ready condition. the ready is cleared by reset. soft ware may set this bit, after the board is initialized, to indicate the board is ready. lmi3s (location monitor interrupt 3 status ): when set, a location monitor 3 interrupt is pending. lmi2s (location monitor interrupt 2 status ): when set, a location monitor 2 interrupt is pending. lmi1s (location monitor interrupt 1 status ): when set, a location monitor 1 interrupt is pending. lmi0s (location monitor interrupt 0 status ): when set, a location monitor 0 interrupt is pending. mbi3s (mail box interrupt 3 status ): when set, a mail box 3 interrupt is pending. mbi2s (mail box interrupt 2 status ): when set, a mail box 2 interrupt is pending. mbi1s (mail box interrupt 1 status ): when set, a mail box 1 interrupt is pending. 12:8 ga geographic address r - 0x xx 7:0 revid revision id r - 0x01 control and status register bits name function pcfs space type reset by reset value
10. registers tsi148 pci/x-to-vme bus bridge user manual 362 80a3020_ma001_08 mbi0s (mail box interrupt 0 status ): when set, a mail box 0 interrupt is pending. gap (geographic address parity ): this bit is the parity b it for the geographic address. this bit is inverted from the vmebus gap* signal. ga (geographic address ): these bits represent the geographic address of the board. these bits are inverted from the vmebus ga[4:0]_ signals. revid (revision id ): this register identifies the tsi148?s revision level.
10. registers tsi148 pci/x-to-vme bus bridge user manual 363 80a3020_ma001_08 10.4.97 semaphore registers (0-3) sema0 (semaphore 0 ): semaphore registers behave in the following way. a semaphore can only be written if the most significant bit in the register is 0 and the most significant bit of the write data is a one or the most significant bit of the write data is a 0. sema1 (semaphore 1 ): semaphore registers behave in the following way. a semaphore can only be written if the most significant bit in the register is 0 and the most significant bit of the write data is a one or the most significant bit of the write data is a 0. sema2 (semaphore 2 ): semaphore registers behave in the following way. a semaphore can only be written if the most significant bit in the register is 0 and the most significant bit of the write data is a one or the most significant bit of the write data is a 0. sema3 (semaphore 3 ): semaphore registers behave in the following way. a semaphore can only be written if the most significant bit in the register is 0 and the most significant bit of the write data is a one or the most significant bit of the write data is a 0. table 169: semaphore register (0-3) register name: semar0 reset value: 0x00000000 register offset: gcsr + 0x08 - crg + 0x608 bits 7 6 5 4 3 2 1 0 31:24 sema0 23:16 sema1 15:8 sema2 7:0 sema3 semaphore registers bits name function pcfs space type reset by reset value 31:24 sema0 semaphore 0 r/w p/s 0x00 23:16 sema1 semaphore 1 r/w p/s 0x00 15:8 sema2 semaphore 2 r/w p/s 0x00 7:0 sema3 semaphore 3 r/w p/s 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 364 80a3020_ma001_08 10.4.98 semaphore registers (4-7) sema4 (semaphore 4 ): semaphore registers behave in the following way. a semaphore can only be written if the most significant bit in the register is 0 and the most significant bit of the write data is a one or the most significant bit of the write data is a 0. sema5 (semaphore 5 ): semaphore registers behave in the following way. a semaphore can only be written if the most significant bit in the register is 0 and the most significant bit of the write data is a one or the most significant bit of the write data is a 0. sema6 (semaphore 6 ): semaphore registers behave in the following way. a semaphore can only be written if the most significant bit in the register is 0 and the most significant bit of the write data is a one or the most significant bit of the write data is a 0. sema7 (semaphore 7 ): semaphore registers behave in the following way. a semaphore can only be written if the most significant bit in the register is 0 and the most significant bit of the write data is a one or the most significant bit of the write data is a 0. table 170: semaphore registers (0-4) register name: semar1 reset value: 0x00000000 register offset: gcsr + 0x0c - crg + 0x60c bits 7 6 5 4 3 2 1 0 31:24 sema4 23:16 sema5 15:8 sema6 7:0 sema7 semaphore registers bits name function pcfs space type reset by reset value 31:24 sema4 semaphore 4 r/w p/s 0x00 23:16 sema5 semaphore 5 r/w p/s 0x00 15:8 sema6 semaphore 6 r/w p/s 0x00 7:0 sema7 semaphore 7 r/w p/s 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 365 80a3020_ma001_08 10.4.99 mail box registers (0-3) the mail box register can be used to pass information between the local processor and other vme boards. when the least significant byte is wr itten, an interrupt is sent to the interrupter. if the interrupt is enabled, an intx signal is generated. table 171: mail box registers (0-3) register name: mboxx reset value: 0x00000000 register offset: mbox0: gcsr + 0x10 - crg + 0x610 mbox1: gcsr + 0x14 - crg + 0x614 mbox2: gcsr + 0x18 - crg + 0x618 mbox3: gcsr + 0x1c - crg + 0x61c bits 7 6 5 4 3 2 1 0 31:0 mbox mail box registers (0-3) bits name function pcfs space type reset by reset value 31:0 mbox mail box r/w p/s 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 366 80a3020_ma001_08 10.4.100 cr/csr register group description the tsi148 implements a sub-set of the cr/csr register set. this section describes the csr registers that are included. 10.4.101 cr/csr bit clear register lrstc (local reset clear ): writing a one to this bit clears the lrst bit. reading a one indicates the lrst bit is set. reading a zero indicates the lrst bit is cleared. sfailc (system fail enable clear ): writing a one to this bit disables the sfailo driver. reading a one indicates the sfailo driver is enabled. reading a zero indicates the sfailo driver is disabled. the initial value of this bit is a configuration option. the system fail enable bit is also accessible from the gcsr. table 172: cr/csr bit clear register register name: csrbcr reset value: 0x00000000 register offset: cr/csr + 0x7fff4 - crg + 0xff4 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:8 reserved 7:0 lrstc sfailc bdfails menc berrsc reserved cr/csr bit clear register bits name function pcfs space type reset by reset value 31:8 reserved n/a r n/a 0x00 7 lrstc local reset clear c/r p/s 0x00 6 sfailc system fail enable clear c/r p/s 0x00 5 bdfails board fail status r p/s/l 0x01 4 menc module enable clear c/r p/s/l 0x00 3 berrsc bus error status clear c/r p/s/l 0x00 2:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 367 80a3020_ma001_08 bdfails (board fail status ): reading a one indicates the bdfail_ signal is asserted. reading a zero indicates the bdfail_ signal is not asserted. menc (module enable clear ): writing a one to this bit cl ears the module enable bit. reading a one indicates the module enable bit is set. reading a zero indicates the module enable bit is not set. the module enable bit can be used as a ready bit. the module enable bit is also accessible from the gcsr. berrsc (bus error status clear ): this bit is set when th e tsi148 asserts the vmebus berr* signal. writing a one to this bit clears the berr status bit. reading a one indicates that the tsi148 has asserted the berr* signal or that the berrss bit has been set. reading a zero indicates that the tsi148 has not asserted the berr* signal and berrs bit has not been set.
10. registers tsi148 pci/x-to-vme bus bridge user manual 368 80a3020_ma001_08 10.4.102 cr/csr bit set register lrsts (local reset set ): writing a one to this bit sets the lrst signal. this asserts the lrsto_ signal and hold the board in reset until a one is written to the lrstc bit. this bit should only be set from vmebus. it should not be set from the crg. reading a one indicates the lrst bit is set. reading a zero indicates the lrst bit is cleared. sfails (system fail enable set ): writing a one to this bit enables sfailo driver. reading a one indicates the sfailo driver is enabled. reading a zero indicates the sfailo driver is disabled. the initial value of this bit is a conf iguration option. the system fail enable bit is also accessible from the gcsr. bdfails (board fail status ): reading a one indicates the bdfail_ signal is asserted. reading a zero indicates the bdfail_ signal is not asserted. table 173: cr/csr bit set register register name: csrbsr reset value: 0x register offset: cr/csr + 0x7fff8 - crg + 0xff8 bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:8 reserved 7:0 lrsts sfails bdfails mens berrss reserved cr/csr bit clear register bits name function pcfs space type reset by reset value 31:8 reserved n/a r n/a 0x00 7 lrsts local reset set s/r n/a 0x00 6 sfails system fail enable set s/r p/s 0x xx 5 bdfails board fail status r p/s/l 0x01 4 mens module enable set s/r p/s/l 0x00 3 berrss bus error status set s/r p/s/l 0x00 2:0 reserved n/a r n/a 0x00
10. registers tsi148 pci/x-to-vme bus bridge user manual 369 80a3020_ma001_08 mens (module enable set ): writing a one to this bit sets the module enable bit. reading a one indicates the module enable bit is set. read ing a zero indicates the module enable bit is not set. the module enable bit can be used as a ready bit. the module enable bit is also accessible from the gcsr. berrss (bus error status set ): this bit is set when the tsi148 asserts the vmebus berr* signal. writing a one to this bit sets the berr status bit. readi ng a one indicates that the tsi148 has asserted the berr* signal or that the berr status bit has been set. reading a zero indicates that the tsi148 has not asserted the berr* signal and berr status bit has not been set.
10. registers tsi148 pci/x-to-vme bus bridge user manual 370 80a3020_ma001_08 10.4.103 cr/csr base address register the cbar is used to select one of the 31 available cr/csr regions (0x00 is reserved for use in auto slot id). the cbar values are in the range of 0x01 to 0x1f. bits 7 to 3 of the cbar are compared with vmebus address bits 23 to 19. the initial value of cbar is determined by the hardware configuration. table 174: cr/csr base address register register name: cbar reset value: 0x00000000 register offset: cr/csr + 0x7fffc - crg + 0xffc bits 7 6 5 4 3 2 1 0 31:24 reserved 23:16 reserved 15:8 reserved 7:0 cbar reserved cr/csr bit clear register bits name function pcfs space type reset by reset value 31:8 reserved n/a r n/a 0x00 7:3 cbar cr/csr base address r/w p/s 0x xx 2:0 reserved n/a r n/a 0x00
tsi148 pci/x-to-vme bus bridge user manual 371 80a3020_ma001_08 a. typical applications this appendix discusses typical application information for tsi148. the following topic is discussed: ? ?tsi148 connection schematics? on page 372
a. typical applications tsi148 pci/x-to-vme bus bridge user manual 372 80a3020_ma001_08 a.1 typical application overview this chapter describes the physical, electrical , and connection requirements for a board design using the tsi148 device. a.2 tsi148 connection schematics the schematics shown in figure 38 through figure 47 illustrate a typical way tsi148 can be connected into a system. indivi dual system requirements may imply the need for alternate configurations. the figures focus on connecting tsi148 to both the pci/x and vmebus, as well as power requirements, pull-up/down usage, and various buffer conventions. off-page references are used in these schema tics. the title of each schematic includes the page number used in the original schematic so that off-page references can be tracked. for example, in figure 38 , the page number in the original schematic is 38. in the following schematics the terms nc and opt are defined as follows: ? nc ? no connect ? opt ? optional figure 38 shows tsi148 connected to both the vmebus and pci/x bus. information shown in figure 38 through figure 47 is board dependent. some boards may not require the design elements or connections detailed in the schematics. the schematics focus solely on tsi148 requirements. all other design requirements are up to the individual board designer.
a. typical applications tsi148 pci/x-to-vme bus bridge user manual 373 80a3020_ma001_08 figure 38: tsi148 schematic (page 38) - tsi148 device connect the pll_vdda, pll_gnda signals to low noise power and ground.
a. typical applications tsi148 pci/x-to-vme bus bridge user manual 374 80a3020_ma001_08 figure 39: tsi148 schematic (page 39) - power pins
a. typical applications tsi148 pci/x-to-vme bus bridge user manual 375 80a3020_ma001_08 figure 40: tsi148 schematic (page 40) - pull-up and pull-down requirements tempe_pll_tune[0:3} should be connected to a 0 ohm resistor to ground. information in figure 40 is board dependent. some boards may not require the pull-up resistors detailed in this schematic.
a. typical applications tsi148 pci/x-to-vme bus bridge user manual 376 80a3020_ma001_08 figure 41: tsi148 schematic (page 41) - vme data buffers for more information on vme power-up options, refer to section 5.4 on page 128 .
a. typical applications tsi148 pci/x-to-vme bus bridge user manual 377 80a3020_ma001_08 figure 42: tsi148 schematic (page 42) - vme address buffers
a. typical applications tsi148 pci/x-to-vme bus bridge user manual 378 80a3020_ma001_08 figure 43: tsi148 schematic (page 43) - vme control buffers
a. typical applications tsi148 pci/x-to-vme bus bridge user manual 379 80a3020_ma001_08 figure 44: tsi148 schematic (page 44) - vme transceivers 3.3k
a. typical applications tsi148 pci/x-to-vme bus bridge user manual 380 80a3020_ma001_08 figure 45: tsi148 schematic (page 45) - vme transceivers
a. typical applications tsi148 pci/x-to-vme bus bridge user manual 381 80a3020_ma001_08 figure 46: tsi148 schematic (page 56) - pci bus 0.0 and 1.0 pull-ups
a. typical applications tsi148 pci/x-to-vme bus bridge user manual 382 80a3020_ma001_08 figure 47: tsi148 schematic (page 58) - pci bus 0.0 configuration header for more information on pci/x power-up options, refer to section 5.4 on page 128 . pci/x configuration options
tsi148 pci/x-to-vme bus bridge user manual 383 80a3020_ma001_08 b. hardware implementation this chapter discusses the following topics: ? ?filter recommendations for the tsi148 pll? on page 383 ? ?capacitance decoupling recommendations? on page 385 ? ?recommended board layout guidelines? on page 385 b.1 filter recommendati ons for the tsi148 pll when operating the device during heavy pci/x bus and vmebus activity, the internal pll may stop oscillating and then restart. the pll reset appears to be caused by internal ground bounce and cross coupling from the vmebus data signals to the pll_vdd and pll_vss signals. the tsi148 relies on the pll to generate al l of the clocks to its internal logic. this errata causes data corruption because the internal pll is reset. b.1.1 production tsi148 pll filtering 1. the pll_vdd and pll_vss signals will be re routed in the package to reduce crosstalk. 2. the pll_tune0, pll_tune1, pll_tune2 and pll_tune3 signals should be grounded on the board. these signals are adj acent to the pll power and ground signals. grounding the tune signals helps shield the pll power and ground signals. the pll tune bits 0, 1, 2 and 3 should have pull up and pull down resistors very close to the package ball. the pull up should not be populated and the pull down should be populated with a zero ohm resistor. 3. an improved pll filter shou ld be used as shown in figure 48 .
b. hardware implementation tsi148 pci/x-to-vme bus bridge user manual 384 80a3020_ma001_08 figure 48: recommended pll filter the following values should be used in conjunction with figure 48 in the production version of the tsi148 ? r1 = 2.2 ohm ? r2 = 2.2 ohm ? r3 = not installed ? l = 820 nh ? c1 = 2.2 uf ? c2 = 0.1 uf ? c3 = 10 uf b.1.2 alpha tsi148 pll filtering 1. the pll_tune0, pll_tune1, pll_tune 2 and pll_tune3 signals should be grounded on the board. these signals are adj acent to the pll power and ground signals. grounding the tune signals helps shield the pll power and ground signals. the pll tune bits 0, 1, 2 and 3 should have pull up and pull down resistors very close to the package ball. the pull up should not be populated and the pull down should be populated with a zero ohm resistor. 2. the pll filter circuit shown in figure 48 should be used with th e modified values in the alpha version of the tsi148 shown below. the modifications effectively raise the pll_vss by 50mv: ? r1 = 2.2 ohm ? r2 = 2.2 ohm ? r3 = 75 ohm ? l = 820 nh c1 c2 c3 c2 r3 l l r1 r2 pll_vdd pll_vss +1.8v gnd
b. hardware implementation tsi148 pci/x-to-vme bus bridge user manual 385 80a3020_ma001_08 ? c1 = 2.2 uf ? c2 = 0.1 uf ? c3 = 10 uf since the pll voltage is reduced by the voltage divider, the 1.8v supply should be set to 1.85v to help compensate for the loss in the divider. if a separate regulator is required to increase only the pll voltage by 50mv, the input current required for pll_vdd can be obtained from the information provided in section 9 on page 185 . b.2 capacitance decoup ling recommendations tundra considers it a good design practice to have decoupling capacitors closely positioned to tsi148?s 3.3v and 1.8v pins. tundra recommends at least 20 0.1uf ceramic surface mount capacitors on the 3.3v pin and 20 on the 1.8v pin. the inductance of the decoupling capacitors can be minimized by keeping the traces short and wide. for example, the traces should be as wide as the capacitor pad. b.3 recommended board layout guidelines when laying out a board with the tsi148 , the device should be placed as close as possible to the center of the board (that is, placed in between the p1 and p2 connectors). tundra recommends connecting all tsi148 vme signals to the vmebus backplane through the ti sn74vmeh22501 transceivers. in order to satisfy vme requirements, all sources of drive on the vmebus must be no further than two inches from the backplane. this design minimizes any potential loading and reflection problems. tundra recommends the traces from the ti sn74vmeh22501 transceivers to the p1 and p2 connectors be no more than two inches in length. tundra also recommends the tsi148 be placed in an orientation on the board that minimizes the distance to the p1 and p2 connectors however, the tsi148 device orientation is board specific. figure 49 shows an example of how the tsi148 device was oriented in a successful design. for more information on tundra board recommendations, refer to the tsi148 schematic review checklist available from the tundra website at www.tundra.com.
b. hardware implementation tsi148 pci/x-to-vme bus bridge user manual 386 80a3020_ma001_08 figure 49: tsi148 pbga orientation b.3.1 trace length recommendations it is good design practice to keep all tsi148 vme signal trace lengths from the device to the transceivers within a 15 to 20 percent nominal spread. for the majority of the tsi148 signals a trace length an inch to either side of the nominal is recommended. it is also recommended that the inputs and outputs of the key vme control signals (that is, as, ds0, ds1, dtack, retry, and berr) be routed with trace lengths equal to the nominal trace length. b.3.2 recommended stackup the tsi148 has been designed successfully using an 18 layer pcb stackup. it may be possible to use a lower layer count, however this design has not been tested. below is an example of the 18 layer count stackup used on a working tsi148 board design. board stackup: 1. signal 2. signal 3. signal 4. signal 5. vss 6. signal 7. signal 8. vss 9. vdd33 10. vdd18 tsi148 p2 p1 pin af01 transceivers transceivers less than 2? less than 2?
b. hardware implementation tsi148 pci/x-to-vme bus bridge user manual 387 80a3020_ma001_08 11. vss 12. signal 13. signal 14. vss 15. signal 16. signal 17. signal 18. signal
b. hardware implementation tsi148 pci/x-to-vme bus bridge user manual 388 80a3020_ma001_08
tsi148 pci/x-to-vme bus bridge user manual 389 80a3020_ma001_08 c. package information this appendix discusses tsi148?s packaging (mec hanical) features. the following topic is discussed: ? ?package characteristics? on page 389 c.1 package characteristics tsi148?s package characteristics are summarized in the following table. figure 50 illustrates the bottom and side views of the tsi148 package. figure 51 presents the top and side views of the device. table 175: package characteristics feature description package type 456 pbga package body size 27 x 27 mm jedec specification ms-034v variation aal-1
c. package information tsi148 pci/x-to-vme bus bridge user manual 390 80a3020_ma001_08 figure 50: 456-pin pbga package diagram ? bottom and side views figure 51: 456-pin pbga package diagram ? top and side view c.1.1 package notes 1. all dimensions are in mm 2. all dimensions and tolerances conform to ansiy14.5m-1994 notes: 1. all dimensions in mm. 2. all dimension and tolerances conform to ansi y14.5m-19 94. 3. conforms to jedec ms-034variation aal-1.
tsi148 pci/x-to-vme bus bridge user manual 391 80a3020_ma001_08 d. ordering information this appendix discusses tsi148?s ordering information. d.1 ordering information tundra products are designated by a product code. when ordering the tsi148, please refer to the device by its full part number, as displayed in the following table. table 176: ordering information part number frequency temperature package pin count tsi148-133cl 133 mhz commercial pbga 456 tsi148-133cly 133mhz commercial pbga 456 TSI148-133IL 133 mhz industrial pbga 456
d. ordering information tsi148 pci/x-to-vme bus bridge user manual 392 80a3020_ma001_08
bit index tsi148 pci/x-to-vme bus bridge user manual 393 80a3020_ma001_08 bit index numerics 133c 231 2ebs 240 2eot 269 2esst 285 2esstb 285 2esstm0 241 , 285 2esstm1 241 , 285 2esstm2 241 , 285 2est 269 2evme 286 64bcl 305 64bcu 304 64d 231 a a64ds 251 abt 329 , 334 acfails 259 acflc 323 acflen 312 acfleo 317 acfls 320 ackd 265 admode0 242 admode1 242 admode2 242 admode3 242 akfc 265 am 269 amode0 348 , 352 amode1 348 , 352 amode2 348 , 352 amode3 348 , 352 as0 286 , 291 , 295 , 302 as1 286 , 291 , 295 , 302 as2 286 , 291 , 295 , 302 atoen 255 b basel 222 baseu 223 bbfc 265 bcfc 265 bclas 219 bdfail 259 bdfails 259 , 360 , 366 , 368 berr 269 berrsc 366 berrss 368 bgfc 265 bid 255 bip 308 bips 308 blt 286 bn 231 bpct 307 bpgt 306 brfc 265 bsy 335 c capid 229 capl 216 capp 225 cbar 370 cbau 293 , 294 cbeax 276 cctm 261 clsz 220 cnts 308 commx 277 cpurst 259 crol 298 crou 297 d data 286 , 291 , 295 , 302 dbw0 242 , 348 , 351 dbw1 242 , 348 , 351 dc 231 dcdalx 340 dcdaux 339 dclalx 342 dclaux 341 dcnt 357 dcsalx 338 dcsaux 337 ddal 346 ddaux 345 ddbs 358 devi 215 , 359 devsels 262 dgo 329 dhb 251 dlt 255 dma0c 322 dma0en 311 dma0eo 316 dma0m 325
bit index tsi148 pci/x-to-vme bus bridge user manual 394 80a3020_ma001_08 dma0s 319 dma1c 322 dma1en 311 dma1eo 316 dma1m 325 dma1s 319 dmcrs 231 dmmrc 231 dmost 231 dn 231 dnlalx 356 dnlau 355 don 335 dpe 216 , 276 dped 216 , 276 dpere 229 drq 261 ds0 269 ds1 269 dsalx 344 dsaux 343 dtt 276 dtte 261 dttt 261 dwb 251 e edgis 308 edpal 273 edpau 272 edpcl 276 edpof 276 edpst 276 edpxa 274 edpxs 275 en 241 , 285 , 291 , 295 , 299 , 302 endal 282 endl 237 endu 236 , 281 ero 229 err 334 errs 335 ert0 335 ert1 335 f fast 216 fn 231 frames 262 g ga 259 , 361 gap 259 , 360 gbau 289 gto 255 h head 220 i iack 269 iackc 322 iacken 311 iackeo 316 iacks 319 intl 226 intp 226 io/mem 222 iosp 217 irdys 262 irq1en 312 irq1eo 317 irq1m 327 irq1s 320 irq2en 312 irq2eo 317 irq2f 308 irq2m 327 irq2s 320 irq3en 312 irq3eo 317 irq3m 327 irq3s 320 irq4en 312 irq4eo 317 irq4m 327 irq4s 320 irq5en 312 irq5eo 317 irq5m 327 irq5s 320 irq6en 312 irq6eo 317 irq6m 327 irq6s 320 irq7en 312 irq7eo 317 irq7m 327 irq7s 320 irqc 308 irqif 308 irql 308 irqls 308 irqs 308
bit index tsi148 pci/x-to-vme bus bridge user manual 395 80a3020_ma001_08 l lla 356 lm0c 322 lm0en 311 lm0eo 316 lm0m 325 lm0s 319 lm1c 322 lm1en 311 lm1eo 316 lm1m 325 lm1s 319 lm2c 322 lm2en 311 lm2eo 316 lm2m 325 lm2s 319 lm3c 322 lm3en 311 lm3eo 316 lm3m 325 lm3s 319 lmbal 301 lmbau 300 lmi0s 360 lmi1s 360 lmi2s 360 lmi3s 360 lreset 255 lrst 360 lrstc 366 lrsts 368 lword 269 m m66ens 262 mb0c 322 mb0en 311 mb0eo 316 mb0m 325 mb0s 319 mb1c 322 mb1en 311 mb1eo 316 mb1m 325 mb1s 319 mb2c 322 mb2en 311 mb2eo 316 mb2m 325 mb2s 319 mb3c 322 mb3en 311 mb3eo 316 mb3m 325 mb3s 319 mbi0s 360 mbi1s 360 mbi2s 360 mbi3s 360 mblt 286 mbox 365 memsp 217 men 360 menc 366 mens 368 mlat 220 mmrbc 229 mngn 226 mod 329 most 229 mrc 261 , 276 mrce 262 mrct 261 mrpfd 241 mstr 217 mtyp0 222 mtyp1 222 mxla 226 n ncapp 229 nelbb 255 nin 347 npriv 286 , 291 , 295 , 302 o offl 239 , 284 , 290 offu 238 , 283 p p66m 216 pau 329 , 334 pbks 329 pbot 330 perr 217 perrc 322 perren 311 perreo 316 perrs 319 pfar 329 pfs0 241 pfs1 241 pgm 242 , 286 , 291 , 295 , 302 , 348 , 352
bit index tsi148 pci/x-to-vme bus bridge user manual 396 80a3020_ma001_08 pic 219 pre 222 psz 347 pursts 259 r rcvma 216 rcvta 216 req64s 262 revi 219 revid 361 rma 276 rmwal 247 rmwau 246 rmwc 249 rmwen 248 , 251 rmws 250 robin 255 rscem 231 rta 276 s sbh 261 scd 231 , 276 scem 276 sclas 219 scons 259 , 360 seltim0 216 seltim1 216 sema0 363 sema1 363 sema2 363 sema3 363 sema4 364 sema5 364 sema6 364 sema7 364 serr 217 sfailai 255 sfailc 366 sfailen 360 sfails 368 sigse 216 sigta 216 sreset 255 srt 276 srte 261 srto 261 srtts 261 sstm0 347 , 351 sstm1 347 , 351 stal 235 , 280 stau 234 , 279 stfc 265 stid 308 stops 262 subi 224 subv 224 sup 242 , 348 , 351 supr 286 , 291 , 295 , 302 sysflc 323 sysflen 312 sysfleo 317 sysfls 259 , 320 t th 285 tm0 242 , 348 , 351 tm1 242 , 347 , 351 tm2 241 , 347 , 351 trsdys 262 typ 351 typ0 347 typ1 347 u usc 231 , 276 v vbks 329 vbot 329 veal 268 veau 267 veni 215 , 359 veof 269 verrc 322 verren 311 verreo 316 verrs 319 ves 269 vescl 269 vfair 252 vfar 329 vfs0 285 vfs1 285 viack 245 viec 322 vieen 311 vieeo 316 vies 319 vrel 252 vreql 252 vs 251 vsa 251
bit index tsi148 pci/x-to-vme bus bridge user manual 397 80a3020_ma001_08 vtoff 251 vton 252 w write 269 x xam 269
bit index tsi148 pci/x-to-vme bus bridge user manual 398 80a3020_ma001_08
tsi148 pci/x-to-vme bus bridge user manual 399 80a3020_ma001_08 index numerics 2esst protocol 35 2evme protocol 35 64bcl register 305 64bcu register 304 a acfaili_ signal 157 ack64_ signal 151 ad signals 148 adbout signal 157 am0 signal 154 am1 signal 154 am2 signal 154 am3 signal 154 am4 signal 154 am5 signal 154 amout signal 157 asi_ signal 155 aso_ signal 155 asoe signal 157 b bbsyi_ signal 156 bbsyo signal 156 bclri_ signal 156 bclro_ signal 156 bdfail_ signal 152 berri_ signal 155 berro_ signal 155 berroe signal 157 bg0in_ signal 155 bg0inout_ signal 155 bg0out_ signal 156 bg1in_ signal 155 bg1inout_ signal 156 bg1out_ signal 156 bg2in_ signal 155 bg2inout_ signal 156 bg2out_ signal 156 bg3in_ signal 155 bg3inout_ signal 156 bg3out_ signal 156 bpctr register 307 bpgtr register 306 br0i_ signal 155 br0o signal 155 br1i_ signal 155 br1o signal 155 br2i_ signal 155 br2o signal 155 br3i_ signal 155 br3o signal 155 c capp register 225 cbal register 294 cbar register 370 cbau register 293 cbe0_ signal 150 cbe1_ signal 150 cbe2_ signal 151 cbe3_ signal 151 cbe4_ signal 151 cbe5_ signal 151 cbe6_ signal 151 cbe7_ signal 151 ce0_test signal 158 clas/revi register 219 clocks 121 contact information 5 crat register 299 crgat register 295 crol register 298 crou register 297 csrbcr register 366 csrbsr register 368 customer support information 5
index tsi148 pci/x-to-vme bus bridge user manual 400 80a3020_ma001_08 d dboe_ signal 157 dbout signal 157 dcalx register 344 dcdalx register 340 dcdaux register 339 dclalx register 342 dclaux register 341 dcntx register 357 dcsalx register 338 dcsaux register 337 dctlx register 329 ddalx register 346 ddatx register 351 ddaux register 345 ddbsx register 358 devi/veni register 215 , 359 devsel_ signal 151 direct memory access (dma) 101 dma (direct memory access) 101 dma controller 102 architecture 102 buffers 102 direction of data movement 105 operating modes 103 direct mode 103 linked-list mode 103 transaction termination 119 commanded abort 119 commanded stop 119 detected error abort 120 transfer completion 119 dma controllers overview 45 dnlalx register 356 dnlaux register 355 document conventions 24 signals 24 documentation feedback 5 ds0i_ signal 155 ds0o_ signal 155 ds1i_ signal 155 ds1o_ signal 155 dsatx register 347 dsaux register 343 dsoe signal 157 dstax register 334 dtacki_ signal 155 dtacko_ signal 155 dtackoe signal 157 e edpal register 273 edpat register 276 edpau register 272 edpxa register 274 edpxs register 275 electrical characteristics 185 email 5 endian mapping 24 f frame_ signal 151 functional overview 29 , 49 , 73 g ga0_ signal 157 ga1_ signal 157 ga2_ signal 157 ga3_ signal 157 ga4_ signal 157 gap_ signal 157 gbal register 290 gbau register 289 gcsrat register 291 gctrl register 360 gnt_ signal 151 h head/mlat/clsz register 220 hwc_pfu signal 158 i iack_ signal 154 iackin_ signal 156 iackout_ signal 156 idsel signal 151 iitofl register 284 inta_ signal 151 intb_ signal 151 intc register 322 intc_ signal 151 intd_ signal 151 inten register 311 inteo register 316 interrupts 137 intm1 register 325 intm2 register 327 ints register 319 irdy_ signal 151 irq1i_ signal 156 irq1o signal 156 irq2i_ signal 156 irq2o signal 156 irq3i_ signal 156
index tsi148 pci/x-to-vme bus bridge user manual 401 80a3020_ma001_08 irq3o signal 156 irq4i_ signal 156 irq4o signal 156 irq5i_ signal 156 irq5o signal 156 irq6i_ signal 156 irq6o signal 156 irq7i_ signal 156 irq7o signal 157 itatx register 285 itealx register 282 iteaux register 281 itofux register 283 itsalx register 280 itsaux register 279 j jtag 47 , 141 instructions 142 l linkage module 42 lmat register 302 lmbal register 301 lmbau register 300 local interrupter 138 lrsti_ signal 152 lrsto_ signal 152 lsrsti_ signal 152 lword_ signal 155 m m66en signal 151 mailing address 5 mbar register 222 mbaru register 223 mboxx register 365 mechanical information 389 mxla/mngn/intp/intl register 226 o ordering information 391 otatx register 241 otbsx register 240 otealx register 237 oteaux register 236 otoflx register 239 otofux register 238 otsalx register 235 otsaux register 234 p packaging information 389 par signal 151 par64 signal 151 pci address/data bus signals 148 pci bus exception handling 86 master 86 target 86 pci master 85 bandwidth control 85 buffers 85 commands 85 pci target 74 buffers 74 commands 76 read transaction 77 transaction mapping 75 write transaction 82 pci/x bus exception handling 99 master 99 target 100 pci/x interface overview 40 pcimc signal 158 pcipuen signal 158 pci-x master 98 bandwidth control 98 buffers 98 pci-x target 88 buffers 88 commands 90 read transaction 91 transaction mapping 89 transactions 90 write transaction 95 pcixcap register 229 pcixstat register 231 pclk signal 151 pcsr register 261 perr_ signal 151 pll_outa signal 158 pll_rsti_ signal 158 pll_ten signal 158 pll_tune0 signal 158 pll_tune1 signal 158 pll_tune2 signal 158 pll_tune3 signal 158 pll_tune4 signal 158 pll_tune5 signal 158 pll_tune6 signal 158 pll_tune7 signal 158 pll_tune8 signal 158 pll_tune9 signal 158
index tsi148 pci/x-to-vme bus bridge user manual 402 80a3020_ma001_08 pll_vdd signal 158 pll_vss signal 159 power-up options pci/x 128 vmebus 130 power-up options 121 product benefits 32 product code 391 product features 32 pursti_ signal 152 r registers 193 registers overview 43 related documentation 27 req_ signal 151 req64_ signal 151 resets 121 retryi_ signal 155 retryo_ signal 155 retryoe signal 157 rmwal register 247 rmwau register 246 rmwc register 249 rmwen register 248 rmws register 250 s scon signal 157 scondis_ signal 157 sconen_ signal 157 semar0 register 363 semar1 register 364 serr_ signal 151 sfaili_ signal 157 sfailo signal 157 signal description 160 signals 145 , 383 spares signal 159 srsti_ signal 157 srsto signal 157 stat/cmmd register 216 stop_ signal 151 subi/subv register 224 sysclk signal 157 t tck signal 158 tdi signal 158 tdo signal 158 technical support 5 tm_in signal 158 tm_out signal 158 tms signal 158 trdy_ signal 151 trst_ signal 158 typical applications 33 , 371 v va signals 152 vctrl register 255 vd1 signal 153 vdd18 signal 159 vdd33 signal 159 veal register 268 veat register 269 veau register 267 viackx register 245 vicr register 308 vmctrl register 251 vme master 61 bandwidth control 64 buffers 62 read-modify write (rmw) cycles 62 release conditions 65 vme master interface overview 37 vme slave 50 buffers 50 read transaction 54 read-modify write (rmw) cycles 60 terminations 60 transaction mapping 51 transactions 54 write transaction 58 vme slave interface overview 36 vmebus interrupter and interrupt handler 46 vmebus address bus signals 152 vmebus data bus signals 153 vmebus interface 50 vmebus interrupt handler 139 vmebus interrupter 138 vmebus system controller arbiter 38 , 71 configuration 39 , 72 global vmebus timer 39 , 72 sysreset driver 39 , 71 system clock driver 39 , 72 vmefl register 265 vss signal 159 vstat register 259 w write_ signal 154

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