32 megabit high speed cmos sram dps2me16mkn3 description: the dps2me16mkn3 high speed sram ??stack?? modules are a revolutionary new memory subsystem using dense-pac microsystems? ceramic stackable leadless chip carriers (slcc). available in straight leaded, ??j?? leaded or gullwing leaded packages. the module packs 32-megabits of low-power cmos static ram in an area as small as 0.549 in 2 , while maintaining a total height as low as 0.545 inches. the dps2me16mkn3 stack modules contain eight individual 512k x 8 srams, each packaged in a hermetically sealed slcc, making the modules suitable for commercial, industrial and military applications. by using slccs, the ??stack?? family of modules offer a higher board density of memory than available with conventional through-hole, surface mount or hybrid techniques. features: organizations available: 2 meg x 16 or 4 meg x 8 access times: 20*, 25, 30, 35, 45ns fully static operation - no clock or refresh required single +5v power supply, 10% tolerance ttl compatible common data inputs and outputs low data retention voltage: 2.0v min. packages available: slcc stack straight leaded stack ??j?? leaded stack gullwing leaded stack * commercial and industrial grade only. functional block diagram pin names a0 - a18 address inputs i/o0 - i/o15 data input/output ce 0 - ce 3 low chip enables we 0, we 1 write enables oe 0, oe 1 output enables v dd power (+5v) v ss ground n.c. no connect 2mx16, 20 - 45ns, stack 30a129-28 b slcc stack straight leaded stack gullwing leaded stack ??j?? leaded stack this document contains information on a product presently under development at dense-pac microsystems, inc. dense-pac reserves the right to change products or specifications herein without prior notice. 30a129-28 rev. b 1
dps2me16mkn3 dense-pac microsystems, inc. recommended operating range 3 symbol characteristic min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v v ih input high voltage 2.2 v dd +0.3 v v il input low voltage -0.5 2 0.8 v t a operating temperature m/b -55 +25 +125 o c i -40 +25 +85 c 0 +25 +70 truth table mode ce we oe i/o pin supply current not selected h x x high-z standby d out disable l h h high-z active read l h l d out active write l l x d in active h = high l = low x = don?t care dc operating characteristics: over operating ranges symbol characteristics test conditions typ. (?) c i m/b unit min. max. min. max. min. max. i in input leakage current v in = 0v to v dd - -40 +40 -40 +40 -40 +40 m a i out output leakage current v i/o = 0v to v dd , ce or oe = v ih , or we = v il - -40 +40 -40 +40 -40 +40 m a i cc operating supply current cycle=min., duty=100% i out = 0ma x8 265 590 600 600 ma x16 370 700 720 720 i sb1 full standby supply current v in 3 v dd -0.2v or v in v ss +0.2v 8 80 80 120 ma i sb2 standby current (ttl) ce = v ih 160 480 480 480 ma i dr3 data retention supply current (3.0v) v dr = 3.0v, ce 3 v dr -0.2v 1.2 4.0 8.0 16.0 ma i dr2 data retention supply current (2.0v) v dr = 2.0v, ce 3 v dr -0.2v 0.8 2.4 6.4 14.4 ma v ol output low voltage i out = 8.0ma - 0.4 0.4 0.4 v v oh output high voltage i out = -4.0ma - 2.4 2.4 2.4 v ? typical measurements made at +25 o c, cycle = min., v dd = 5.0v. capacitance 4 : t a = 25 c, f = 1.0mhz symbol parameter max. unit condition c adr address input 80 pf v in 2 = 0v c ce chip enable 32 c we write enable 40 c oe output enable 40 c i/o data input/output 50 pin-out diagram dc output characteristics symbol parameter conditions min. max. unit v oh high voltage i oh = -4.0ma 2.4 v v ol low voltage i ol =8.0ma 0.4 v absolute maximum ratings 3 symbol parameter value unit t stc storage temperature -65 to +150 c t bias temperature under bias -55 to +125 c v dd supply voltage 1 -0.5 to +7.0 c v i/o input/output voltage 1 -0.5 to v dd +0.5 v 30a129-28 rev. b 2
dense-pac microsystems, inc. dps2me16mkn3 +5v 255 w 480 w c l * d out figure 1. output load * including probe and jig capacitance. output load load c l parameters measured 1 100pf except t lz , t hz , t ohz , t olz , and t whz 2 5pf t lz , t hz , t ohz , t olz , and t whz ac test conditions input pulse levels 0v to 3.0v input pulse rise and fall times 5ns input and output timing reference levels 1.5v data retention ac characteristics 8 symbol parameter test conditions min. typ. max. unit v dr v dd for data retention ce 3 v dr -0.2v 2.0 - - v v cdr chip disable to data retention time see data retention waveform 0 - - ns t r operation recovery time see data retention waveform 5 - - ms ac operating conditions and characteristics - read cycle: over operating ranges no. symbol parameter 20ns* 25ns 30ns 35ns 45ns unit min. max. min. max. min. max. min. max. min. max. 1 t rc read cycle time 20 25 30 35 45 ns 2 t aa address access time 20 25 30 35 45 ns 3 t co ce to output valid 20 25 30 35 45 ns 4 t oe output enable to output valid 10 12 15 20 25 ns 5 t lz ce to output in low-z 4, 5 3 3 3 3 3 ns 6 t olz output enable to output in low-z 4, 5 0 0 0 0 0 ns 7 t hz ce to output in high-z 4, 5 8 10 15 20 25 ns 8 t ohz output enable to output in high-z 4, 5 0 8 0 10 0 15 0 20 0 25 ns 9 t oh output hold from address change 4 5 5 5 5 ns ac operating conditions and characteristics - write cycle 6, 7 : over operating ranges no. symbol parameter 20ns* 25ns 30ns 35ns 45ns unit min. max. min. max. min. max. min. max. min. max. 10 t wc write cycle time 20 25 30 35 45 ns 11 t aw address valid to end of write 13 15 20 25 35 ns 12 t cw chip enable to end of write 13 15 20 25 35 ns 13 t as address set-up time ** 0 0 0 0 0 ns 14 t wp write pulse width 13 15 20 25 35 ns 15 t wr write recovery time 0 0 0 0 0 ns 16 t whz write enable to output in high-z 4, 5 0 8 0 10 0 12 0 15 0 20 ns 17 t dw data to write time overlap 9 10 12 15 20 ns 18 t dh data hold from write time 0 0 0 0 0 ns 19 t ow output active from end of write 3 3 3 3 3 ns * available in commercial and industrial grade only. ** valid for both read and write cycles. 30a129-28 rev. b 3
dps2me16mkn3 dense-pac microsystems, inc. read cycle address ce oe data i/o data retention waveform: ce controlled. v dd 4.5v 2.3v v dr1 ce 0v ce 3 v dd -0.2v write cycle 1: ce controlled. address ce we data in data out 30a129-28 rev. b 4
dense-pac microsystems, inc. dps2me16mkn3 write cycle 2: we controlled. oe is high. 8 address ce we data in data out write cycle 3: we controlled. oe is low. 8 address ce we data in data out 30a129-28 rev. b 5
dps2me16mkn3 dense-pac microsystems, inc. (52 - pin leadless stack) mechanical drawing (52 - pin straight leaded stack) mechanical drawing 30a129-28 rev. b 6
dense-pac microsystems, inc. dps2me16mkn3 (52 - pin ??j?? leaded stack) mechanical drawing (52 - pin gullwing leaded stack) mechanical drawing 30a129-28 rev. b 7
dps2me16mkn3 dense-pac microsystems, inc. ordering information dense-pac microsystems, inc. 7321 lincoln way, garden grove, california 92841-1431 (714) 898-0007 (800) 642-4477 fax: (714) 897-1772 http://www.dense-pac.com waveform key data valid transition from transition from data undefined high to low low to high or don?t care notes: 1. all voltages are with respect to v ss . 2. -2.0v min. for pulse width less than 20ns (v il min. = -0.5v at dc level). 3. stresses greater than those under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute max imum rating conditions for extended periods may affect reliability. 4. this parameter is guaranteed and not 100% tested. 5. transition is measured at the point of 500mv from steady state voltage. 6. when oe and ce are low and we is high, i/o pins are in the output state,and input signals of opposite phase to the outputs must not be applied. 7. the outputs are in a high impedance state when we is low. 8. ce and we can initiate and terminate write cycle. 30a129-28 rev. b 8
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