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YDA147 catalog catalog no.:lsi-4da147a61 2009.1 YDA147 d- 515 stereo 5w-15w digital audio power amplifier general description YDA147 (d-515) is a high-efficiency digital audio power amplifier ic with the maximum output of 15w 2ch. YDA147 has a ?pure pulse dir ect speaker drive circuit? th at directly drives speakers while reducing distortion of pulse output signal and reducing noise on the signal, which realizes the highest standard low distortion rate characteristics and low noise char acteristics among digital amplifier ics in the same class. in addition, supporting filterless design allows circuit design with fewer external parts to be realized depending on use conditions. YDA147 features power limit function, non-clip function, and drc (dynamic range control) function that were developed by yamaha original digital amplifier technology. YDA147 has overcurrent protection function for speaker output terminals, high temperature protection function, and lowsupply voltage malfunction prevention function. features ? operating supply voltage range pvdd: 8.0v to 16.5v ? maximum momentary output 20 w2ch (v ddp =14v, r l =4 ? , thd+n=10%) 15 w2ch (v ddp =12v, r l =4 ? , thd+n=10%) ? maximum continuous output 15 w* 1 2ch (v ddp =15v, r l =8 ? , thd+n=10%, ta=70c, sqfp48, 4 layers) 10.5w* 1 2ch (v ddp =15v, r l =4 ? , thd+n=10%, ta=25c, sqfp48, 4 layers) 10 w* 1 2ch (v ddp =12v, r l =8 ? , thd+n=10%, ta=25c, lqfp48, 1 layer) ? distortion rate (thd+n) 0.01 % (v ddp =12v, r l =8 ? , po=0.1w, 1khz) ? residual noise 48vrms (v ddp =12v, gain[1:0]=l,l, ncdrc[1:0]=l,l) ? efficiency 92 % (v ddp =12v, r l =8 ? ) ? s/n ratio 105 db (v ddp =12v, gain[1:0]=l,l, ncdrc[1:0]=l,l) ? channel separation -80 db (v ddp =12v, gain[1:0]=l,l, ncdrc[1:0]=l,l) ? psrr 60db (v ddp =12v,vripple=100mv, 1khz, gain[1:0]=l,l, ncdrc[1:0]=l,l) ? non-clip function/drc function (switchable) ? power limit function ? clock external synchronization function ? master/slave synchronization function using clock outputs ? over-current protection function, high temperature protection function, low voltage malfunction prevention function, and dc detection function ? sleep function using sleepn terminal and ou tput mute function using muten terminal ? stereo/monaural switching function ? spread clock function ? pop noise reduction function ? package lead-free 48-pin plastic sqfp (exposed stage) lead-free 48-pin plastic lqfp note) *1: a value based on yamaha's board implementation conditions (see note *2,*3 of page 28)
YDA147 2 catalog no.:lsi-4da147a61 terminal configuration inlp pvddreg avdd inlm vref inrp pvddmr inrm gain1 outpl pvddpr outml pvssl avss gain0 ckin ckout pvddml pvddpl n.c. protn pvssr outpr outmr muten sleepn n.c. n.c. n.c. plimit n.c. pvssr pvddmr outmr pvddpr outpr outpr outmr n.c. pvddpl outpl outpl pvddml pvssl outml outml 1 2 3 4 5 6 8 9 10 11 12 15 16 20 17 22 23 24 25 26 27 13 14 28 sqfp48 7 21 18 19 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ncdrc1 ncdrc0 < 48-pin sqfp top view >
YDA147 catalog no.:lsi-4da147a61 3 inlp pvddreg avdd inlm vref inrp vss inrm gain1 outpl outml pvssl avss gain0 ckin ckout pvddml vss protn outpr outmr muten sleepn vss vss plimit pvssr pvddmr pvddpr outpr outmr n.c. pvddpl outpl outml 1 2 3 4 5 6 8 9 10 11 12 15 16 20 17 22 23 24 25 26 27 13 14 28 lqfp48 7 21 18 19 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ncdrc1 ncdrc0 n.c. vss vss vss vss vss vss vss vss vss vss < 48-pin lqfp top view > (note) vss pin should be connected to the ground patter n as wide as possible to improve the heat radiation.
YDA147 4 catalog no.:lsi-4da147a61 terminal function <48-pin sqfp > no. name *4) i/o *1), *2), *3) function 1 nc normally, use this terminal with nothing connected. 2 nc normally, use this terminal with nothing connected. 3 pvddreg pvdd power supply terminal for regulators 4 avdd oa 3.3v regulator output terminal 5 inlp ia analog input terminal (lch+) 6 inlm ia analog input terminal (lch-) 7 vref oa reference voltage output terminal 8 inrm ia analog input terminal (rch-) 9 inrp ia analog input terminal (rch+) 10 avss gnd analog ground terminal 11 plimit ia power limit setting terminal 12 nc normally, use this terminal with nothing connected. 13 pvddpr pvdd power supply terminal for digital amplifier output (rch+) 14 pvddpr pvdd power supply terminal for digital amplifier output (rch+) 15 outpr o digital amplifier output terminal (rch+) 16 outpr o digital amplifier output terminal (rch+) 17 outpr o digital amplifier output terminal (rch+) 18 pvssr gnd ground terminal for digital amplifier output (rch) 19 pvssr gnd ground terminal for digital amplifier output (rch) 20 outmr o digital amplifier output terminal (rch-) 21 outmr o digital amplifier output terminal (rch-) 22 outmr o digital amplifier output terminal (rch-) 23 pvddmr pvdd power supply terminal for digital amplifier output (rch-) 24 pvddmr pvdd power supply terminal for digital amplifier output (rch-) 25 nc normally, use this terminal with nothing connected. 26 sleepn i sleep control terminal *5) 27 protn o/d error flag output terminal 28 muten i mute control terminal 29 ckout o clock output terminal for synchronization 30 ckin i external clock input terminal 31 ncdrc0 i non-clip/drc1/drc2 mode selection terminal 0 32 ncdrc1 i non-clip/drc1/drc2 mode selection terminal 1 33 gain0 i gain setting terminal 0 34 gain1 i gain setting terminal 1 35 nc normally, use this terminal with nothing connected. 36 nc normally, use this terminal with nothing connected. 37 pvddml pvdd power supply terminal for digital amplifier output (lch-) 38 pvddml pvdd power supply terminal for digital amplifier output (lch-) 39 outml o digital amplifier output terminal (lch-) 40 outml o digital amplifier output terminal (lch-) 41 outml o digital amplifier output terminal (lch-) 42 pvssl gnd ground terminal for digital amplifier output (lch) 43 pvssl gnd ground terminal for digital amplifier output (lch) 44 outpl o digital amplifier output terminal (lch+) 45 outpl o digital amplifier output terminal (lch+) 46 outpl o digital amplifier output terminal (lch+) 47 pvddpl pvdd power supply terminal for digital amplifier output (lch+) 48 pvddpl pvdd power supply terminal for digital amplifier output (lch+) (notes) *1: i: input terminal, o: output terminal, a: analog terminal, o/d: open/drain output terminal *2: pvdd should be connected each other on a board. *3: gnd should be connected each other on a board. *4: each output terminal with the same name (outpr, outmr, outpl, and outml) should be connected on a board. *5: don't use the terminal avdd to appl y ?h? level to the terminal sleepn. when the terminal sleepn is "l" level, the terminal avdd is not supplied.
YDA147 catalog no.:lsi-4da147a61 5 < 48-pin lqfp > no. name *4) i/o *1), *2), *3) function 1 vss gnd 2 pvddreg pvdd power supply terminal for regulators 3 avdd oa 3.3v regulator output terminal 4 nc normally, use this terminal with nothing connected. 5 inlp ia analog input terminal (lch+) 6 inlm ia analog input terminal (lch-) 7 vref oa reference voltage output terminal 8 inrm ia analog input terminal (rch-) 9 inrp ia analog input terminal (rch+) 10 avss gnd analog ground terminal 11 plimit ia power limit setting terminal 12 vss gnd 13 vss gnd 14 vss gnd 15 pvddpr pvdd power supply terminal for digital amplifier output (rch+) 16 outpr o digital amplifier output terminal (rch+) 17 outpr o digital amplifier output terminal (rch+) 18 pvssr gnd ground terminal for digital amplifier output (rch) 19 outmr o digital amplifier output terminal (rch-) 20 outmr o digital amplifier output terminal (rch-) 21 pvddmr pvdd power supply terminal for digital amplifier output (rch-) 22 vss gnd 23 vss gnd 24 vss gnd 25 vss gnd 26 sleepn i sleep control terminal *5) 27 protn o/d error flag output terminal 28 muten i mute control terminal 29 ckout o clock output terminal for synchronization 30 ckin i external clock input terminal 31 ncdrc0 i non-clip/drc1/drc2 mode selection terminal 0 32 ncdrc1 i non-clip/drc1/drc2 mode selection terminal 1 33 gain0 i gain setting terminal 0 34 gain1 i gain setting terminal 1 35 nc normally, use this terminal with nothing connected. 36 vss gnd 37 vss gnd 38 vss gnd 39 pvddml pvdd power supply terminal for digital amplifier output (lch-) 40 outml o digital amplifier output terminal (lch-) 41 outml o digital amplifier output terminal (lch-) 42 pvssl gnd ground terminal for digital amplifier output (lch) 43 outpl o digital amplifier output terminal (lch+) 44 outpl o digital amplifier output terminal (lch+) 45 pvddpl pvdd power supply terminal for digital amplifier output (lch+) 46 vss gnd 47 vss gnd 48 vss gnd (notes) *1: i: input terminal, o: output terminal, a: analog terminal, o/d: open/drain output terminal *2: pvdd should be connected each other on a board. *3: gnd should be connected each other on a board. *4: each output terminal with the same name (outpr, outmr, outpl, and outml) should be connected on a board. *5: don't use the terminal avdd to appl y ?h? level to the terminal sleepn. when the terminal sleepn is "l" level, the terminal avdd is not supplied.
YDA147 6 catalog no.:lsi-4da147a61 block diagram
YDA147 catalog no.:lsi-4da147a61 7 functional description digital amplifier function YDA147 has digital amplifiers with analog input, pwm pulse output, the maximum output of 20w 2ch. adopting ?pure pulse direct speaker drive circuit? reduces distortion and noise on pwm pulse output signal. ? digital amplifier gain the total gain of the digital amplifier varies depending on operation modes, as shown below. ncdrc1 ncdrc0 gain1 gain0 total gain operation mode l l +22db l h +28db h l +34db l l h h +16db normal mode non-clip: off drc: off l l +34db l h +40db h l +46db l h h h +28db non-clip mode l l +34db l h +40db h l +46db h l h h +28db drc1 mode l l +34db l h +40db h l +46db h h h h +28db drc2 mode ? audio signal input for a differential input, the signal should be input to inlp and inlm terminals (lch) and to inrp and inrm terminals (rch) through a dc-cut capacitor (c in ). on the contrary, for a single-ended input, the signal should be input to inlp terminal (lch) and to inrp terminal (rch) through a dc-cut capacitor (c in ). at this time, inlm and inrm terminals s hould be connected to avss through dc-cut capacitors (c in ) with the same value. in the differential input mode, use signal sources with the same impedance to reduce pop-noise. its value should be 10k ? or less. use a dc-cut capacitor (c in ) of 1f. (the capacitance value should be less than 1.5f throughout the operating temperature range.) (cautions) when inputting audio signals in power-off state ( pvdd < v huvll ) or sleep state, current may flow toward the former device from YDA147's ground, through each protection circuit of analog pins (inlp, inlm, inrp, and inrm). for this reason, audio signals should not be input in power-off state ( pvdd < v huvll ) or sleep state.
YDA147 8 catalog no.:lsi-4da147a61 avdd plimit avss voltage dividing resistor r1 voltage dividing resistor r2 plimit terminal setting circuit ? input impedance the input impedance (z in ) is 18.8k ? regardless of a gain setting. ? reference voltage output function half a voltage of avdd terminal is output to the reference voltage terminal (vref). connect a capacitor of 0.1 f for voltage stabilization. ? maximum output the output varies depending on load impedance and a supply voltage, as shown below. maximum momentary output: 20w 2ch (pvdd=14v, r l =4 ? , thd+n=10%) 15w 2ch (pvdd=12v, r l =4 ? , thd+n=10%) maximum continuous output: 15w 2ch (v ddp =15v, r l =8 ? , thd+n=10%, ta=70c, sqfp48, 4-layer board) 10.5w 2ch (v ddp =15v, r l =4 ? , thd+n=10%, ta=25c, sqfp48, 4-layer board) 10w 2ch (v ddp =12v, r l =8 ? , thd+n=10%, ta=25c, lqfp48, 1 layer board) the maximum momentary output means a possible maximum output by considering heat problems due to power loss separately. the maximum continuous output means a maximum ou tput with tjmax not ex ceeding 150c at a given temperature while outputting a sine wave continuously. in addition, this value is based on yamaha's board implementation conditions. (see note *2, *3 at page 28) a possible maximum continuous output in other settings can be converted by the following data: 1. graph of power dissipation vs output power of example of typical characteristics. (see page 32) 2. power dissipation of electrical characteristics. (see page 28) control function ? output power limit function this is the function to set a voltage at which the output is clipped. at this time, a value at which the output is clipped is defined as a power limit value (v pl ). using this function prevents increase of temperature in a device as well as allowing the maximum output power to be limited. the output power limit value is determined by a voltage (voltage dividing resistor 1, 2) applied to plimit terminal. in addition, changing the voltage at plimit terminal during power-on is prohibited. the relation between a resistor ratio (r2/(r1+r2) ( between voltage dividing resistor 1 and 2) and an output power with a 10% distortion is shown below. since it may vary between min and max due to variation of internal avdd, select resistors in consideration of the variation. the setting values shown here are common to stereo and monaural mode. plimit resistor r1 and r2 should be set as follows. r1+r2=500k ? or less r1//r2=50k ? to 70k ? (r1//r2 means a parallel resistance between r1 and r2) example 1: 4 ? max30w (8 ? max15w) r1=220k+4.7k, r2=75k example 2: 8 ? min10w r1=200k, r2=75k+1.5k
YDA147 catalog no.:lsi-4da147a61 9 * minimum value restriction on the output power limit. the minimum value of the output-power limit values is rest ricted by the value determined with the resistance voltage division ratio of ?0.45.? even though the resistance voltage division ratio is set beyond ?0.45,? the output-power limit value wouldn?t be set lower. * cancellation of the output power limit function. it is possible to disable the power limit by setting ?0?v (voltage division ratio ?0?) to the plimit pin. however, it is necessary to se t the power limit value when the following function is used. ? non-clip function (non-clip/drc function : p.11). ? drc function (non-clip/drc function : p.11). ? high temperature power limiter st ate of high temperature protection (high temperature protection function : p.20). for the relation between each function and the power limit value, see the item of each function.
YDA147 10 catalog no.:lsi-4da147a61 enlarged figures plimit voltage dividing ratio vs output power at 10 distortion 4? 0 5 10 15 20 25 30 35 0.200 0.250 0.300 0.350 0.400 0.450 0.500 plimit voltage dividing ratio output power at 10 distortion [w] typ min max plimit voltage dividing ratio vs output power at 10 distortion 4? 0 1 2 3 4 5 6 7 8 9 10 0.300 0.350 0.400 0.450 0.500 plimit voltage dividing ratio output power at 10 distortion [w] typ min max plimit voltage dividing ratio vs output power at 10 distortion 8? 0 2 4 6 8 10 12 14 16 18 0.200 0.250 0.300 0.350 0.400 0.450 plimit voltage dividing ratio output power at 10 distortion [w] typ min max plimit voltage dividing ratio vs output power at 10 distortion 8? 0 1 2 3 4 5 6 7 8 9 10 0.250 0.300 0.350 0.400 0.450 plimit voltage dividing ratio output power at 10 distortion [w] typ min max plimit voltage dividing ratio vs output power at 10 distortion 16? 0 1 2 3 4 5 6 7 8 9 0.200 0.250 0.300 0.350 0.400 0.450 plimit voltage dividing ratio output power at 10 distortion [w] typ min max plimit voltage dividing ratio vs output power at 10 distortion 16? 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0.250 0.300 0.350 0.400 0.450 plimit voltage dividing ratio output power at 10 distortion [w] typ min max
YDA147 catalog no.:lsi-4da147a61 11 ? non-clip/drc function this is the function to change the gain by detecting an inpu t level to the pwm amplifier and to raise an average output level while suppressing clipping. a mode is determined by the combination of ncdrc[1:0] terminals, as shown below. ncdrc1 ncdrc0 mode l l non-clip & drc mode off l h non-clip mode h l drc1 mode h h drc2 mode in non-clip mode, the gain increases by 12db. the gain is automatically adjusted so that an output peak voltage becomes a power limit value. the maximum attenuation is -12db. attack time is 0 second. the release time from -12db to 0db is 7.7 s (typ.). in drc1 mode, the gain increases by 12db. dynamic range compression (a half of gain in db) is performed within an output range of -12db (-24db for input range) from the power limit value. attack time is 0 s. the release time from -12db to 0db is 3.9 s (typ.). in drc2 mode, the gain increases by 12db. as with drc1, similar compression is performed, but power-limit operation is not performed. plimit terminal can be used to set a d rc operating point. therefore, the setting of a gain curve is possible regardless of the maximum output power, and this allows for drc operation from a low output power. ncdrc [1:0] terminal should be switched under either of the following conditions. ? before pvdd power-on (lower than the pvdd start-up threshold voltage (v huvlh )) ? sleepn=l pop noise may occur when switching it under an operating condition other than the above.
YDA147 12 catalog no.:lsi-4da147a61 output voltage [db] input voltage [db] 0 off ncdrc[1:0]=00 power limit value v pl a condition in which the power limit is being applied. non-clip/drc gain curve (off) output voltage [db] input voltage [db] 0 off ncdrc[1:0]=00 power limit value v pl a condition in which the power limit is being applied. -12 non-clip ncdrc[1:0]=01 non-clip/drc gain curve (non-clip) output voltage [db] output voltage [db]
YDA147 catalog no.:lsi-4da147a61 13 ?R[db] ?R[db] 0 off ncdrc[1:0]=00 ?`???v pl ?`??? ???B drc1 ncdrc[1:0]=10 -24 v pl -12db non-clip/drc gain curve (drc1 ) output voltage [db] input voltage [db] 0 off ncdrc[1:0]=00 power limit value v pl a condition in which it is not applied even if exceeding the power limit. drc2 ncdrc[1:0]=11 -24 v pl - 12db non-clip/drc gain curve (drc2 ) power limit value ( v pl ) a condition in which the power limit is being applied. output voltage [db] input voltage [db] output voltage [db]
YDA147 14 catalog no.:lsi-4da147a61 ? sleep function YDA147 shifts into sleep mode when sleepn terminal goes to ?l? level. in the sleep mode, all functions stop and consumption current is minimized ( sleep ). when shifting into sleep mode during any protection mode, the protection mode is cancelled and protn terminal output becomes hi-z state. the digital amplifier output becomes weak low (a state grounded through a high resistance). avdd and vref outputs are pulled down. when the level at sleepn terminal is changed from ?l? to ?h? under the condition th at the voltage at pvddreg terminal is higher than the threshold voltage (v huvlh ) for low voltage malfunction prevention cancellation, the sleep mode is cancelled and the state shifts into the normal ope ration state after the period of sleep recovery time (t wu ). ? mute function YDA147 shifts into mute mode when muten terminal goes to ?l? level. in the mute mode, the digital amplifier output becomes weak low (a state grounded through a high resistance). when the level at muten terminal is changed from ?l? to ?h? under the condition that the voltage at pvddreg terminal is higher than the threshold voltage (v huvlh ) for low voltage malfunction prevention cancellation and state of sleepn terminal=h, the mute mode is cancelled and the state shifts into the normal operatio n state after the period of mute recovery time (t mrcv ). ? clock control function the setting of ckin terminal controls the clock mode as shown below. ckin terminal setting mode ckout l fixed internal clock mode internal clock (frequency: f ck ) output h fixed internal clock (spread clock) mode internal clock (spread clock) frequency: (f ck ) output clock input external clock mode ckin input buffer output (frequency: f ckin ) when ckin terminal is held l or h level, internal clock mode is selected to generate a clock internally. and, when ckin terminal is held h level, spread clock function operates to reduce emi. when an external clock is input to ckin terminal, its frequency should be f ckin . do not use with ckin terminal left open. ? stereo/monaural switching function when inrp and inrm terminals (rch input) are connected to avdd, monaural mode is selected. in the monaural mode, input signals input to inlp and inlm terminals (lch input) are output from lch and rch digital amplifiers. with the monaural mode, parallel operation can be realized by connecting outpl to outpr and connecting outml to outmr. for details of connections, see ?single operation in monaur al mode? (see page 24) in the ?examples of application circuits.? the switching between stereo and monaural modes should be performed under the following conditions. ? before pvdd power-on (lower than the pvdd shutdown threshold voltage) ? digital amplifier pop noise reduction function pop noise that may occur at the power-on, power-off, power-down, and power-down cancel operations, etc. is reduced by minimizing an output offset voltage. ? multi-chip synchronization function the external clock synchronization function and clock output function are prepared and the use of master/slave configuration realizes carrier clock synchronization. when using it with multi chips synchronized, one is used as a ma ster chip and the other is used as a slave chip. at this time, connect ckout terminal of a master ch ip to ckin terminal of a slave chip. when using 3 chips (master/slave1/slave2), connect ckout terminal of a slave1 chip to ckin terminal of a slave2 chip. for details of connections, see ?master-slave operation? (see page 26 and 27) in the ?examples of application circuits.? pvdd pins should be connec ted each other on a board.
YDA147 catalog no.:lsi-4da147a61 15 ? startup sequence, shutdown sequence v huvlh pvdd outpl/outpr v ddp t wu outml/outmr digital amplifier output avdd v dda power supply startup sequence v huvlh pvdd outpl /outpr v ddp outml /outmr digital amplifier output stopping digital amplifier output avdd v dda power supply shutdown sequence
YDA147 16 catalog no.:lsi-4da147a61 v ih_slpn sleepn outpl /outpr t wu outml /outmr digital amplifier output avdd startup sequence from sleep state v il_slpn sleepn outpl /outpr outml /outmr digital amplifier output stopping digital amplifier output avdd transient sequence to sleep state
YDA147 catalog no.:lsi-4da147a61 17 regulator output when sleepn terminal is at h, YDA147 outputs v dda to avdd terminal. connect a capacitor of 1f to 4.7f to avdd terminal for stabilization. (0.8f or more should be secured including its varia tion and temperature change.) avdd output must be used only for YDA147. if this output is used in a peripheral circuit of YDA147, the maximum current that can be driven will be i dda. lc filter YDA147 adopts the modulation method that reduces speaker loss sufficiently at mute state by the use of only an inductance the speaker has, and this allows for direct c onnection to a speaker without an lc filter. when an lc filter is used, use the lc filter circuits shown below. at this time, the following constant should be used according to an impedance of a speaker. using these constants makes a low-pass filter with a cu t-off frequency of 50khz or so, q=0.7 or so. lc filter constants: rl l1 c1 c2 4 10h 0.33f 0.22f 8 22h 0.22f 0.1f c1 c2 c2 rl l1 l1 c1 c2 c2 rl l1 l1 lc filter circuit (stereo) lc filter circuit (monaural) * with use of lc filters, if there is a possibility of not usin g a speaker, audio signals within 20khz should be input. and, if its band limitation is not possible, remove the speaker under the following conditions: sleepn terminal = l or muten terminal = l, or pvdd = power off. speaker inductance in the following cases, use a speaker w ith an inductance of 20h or more (at around the switching frequency (f ckin or f ck )). 1. direct connection of a speaker to an output pi n of the digital amplifier without an lc filter. 2. connection of a speaker to a position after components fo r emi measures such as ferrite beads etc. (filterless). with an inductance of less than 20h, power lo ss in the speaker and this device may increase.
YDA147 18 catalog no.:lsi-4da147a61 protection function YDA147 has the following four digital amplifier protection functions: overcurrent protection function, high temperature protection function, low voltage malfunction prevention function, and dc detection function. protection functions protn terminal output protn terminal latch digital amplifier output state protection mode cancel over current protection function low latched wl *1) sleepn terminal=l or pvdd shutdown high temperature protection function (high temp. power limiter state) not latched power limit (-6db) sleepn terminal=l or pvdd shutdown or lower temperature high temperature protection function (high temp. shutdown state) low not latched wl *1) sleepn terminal=l or pvdd shutdown or lower temperature low voltage malfunction prevention function (hi-z) wl *1) dc detection function low latched wl *1) sleepn terminal=l or pvdd shutdown *1: wl=weak low (a state grounded with a high resistance) use a circuit as shown below when pulling up protn terminal output externally. 1) pull up the terminal to a voltage obtained by dividing the voltage between pvdd and gnd with voltage-dividing resistors. find values with reference to the following formula so th at a voltage at the terminal becomes 3.3v or less when protn terminal is in ?h? output (hi-z). 2.0v Q (r2 / (r1 + r2)) v ddp Q 3.3v ;however, r1 > 100k ? , 10k ? < r2 < 100k ? 2) the pull-up should be performed to an external supply vo ltage lower than 3.3v. the pull-up resistor r3 should be a value as follows. 40k ? < r3 < 200k ? (47k ? is recommended.) in each case, select these values so that 0.4ma or more curren t will not flow into the terminal while protn terminal is in l state. protn terminal pull-up connection 1 (a pull-up to pvdd)
YDA147 catalog no.:lsi-4da147a61 19 vcc(3.3v) protn r3 error flag protn terminal pull-up connection 2 (a pull-up to 3.3v) * if automatic return setting is given by connecting protn terminal to sleepn terminal, use a separate power supply as vcc, not the same power supply as avdd. * when vcc is used as avdd, see st artup sequence (page 14 and 15).
YDA147 20 catalog no.:lsi-4da147a61 ? digital amplifier over current protection function this is the function to protect the device by detecting short-circuiting (to the supply voltage, to the ground, and between terminals) at digital amplifier output terminals. in the protection mode, protn terminal becomes l level and output terminals become weak low state (a state grounded through a high resistance). the protection mode can be cancelled by turning off the power supply or inputting an l level si gnal to sleepn terminal momentarily. and, when protn terminal is externally connected to sleepn terminal, automatic return mode is selected. at this time, the protection mode is cancelled even if the protection mode is established by detecting an overcurrent state, and protn terminal output is turned from l level into hi-z state and a normal operation state is given after a given standby time (t wu ). (automatic return function) the current value to detect a short-circuiting between terminals is 8a (typ,v ddp =12v), 10a (typ,v ddp =15v). ? high temperature protection function this is the function to protect the device by detecting an unusual te mperature in YDA147. the protection mode operates in the following two modes according to the temperature. 1) high temperature power limiter state if the temperature rises and reaches 155 c (typ.), the high temperature power limiter state is given. this state decreases the power limit level by 6db in order to limit th e digital amplifier output power, and attempts to lower the temperature. in this way, when the temperature falls and lowers than 130c (typ.), the high temperature power limiter state is automatically cancelled and the gain is restored to the original setting value. in the power limiter state, this does not affect on protn terminal. 2) high temperature shutdown state if the temperature rises and reaches 165 c (typ.) during the high temperature po wer limiter state, the high temperature cutoff state is given. this state outputs an l level signal from protn terminal and digital amplifier output terminals become weak low state (a state grou nded through a high resistance). in this way, when the temperature goes down and lowers th an 130c (typ.), the high temperature shutdown state is automatically cancelled. and, even if the cutoff state is established by detecting an unusual temperature, when protn terminal is externally connected to sleepn terminal, the cutoff state is cancelle d and protn terminal output is turned from l into hi-z state and a normal operation state is given if the temperat ure is sufficiently lowered after a given standby time (t wu ). (automatic return function) if the temperature is not sufficiently lowered, the hi gh temperature protection mode will be established. ? low voltage malfunction prevention function this is the function to protect the device when the supp ly voltage at pvddreg termin al is unusually lowered. in this protection mode, the digital amplifier output terminals become weak low state (a state grounded through a high resistance). this protection mode is given if the supply voltage at pvddreg terminal becomes a voltage lower than pvdd shutdown threshold voltage (v huvll ). when the supply voltage at pvddreg termin al exceeds pvdd startup threshold voltage (v huvlh ), the protection mode is cancelled and a normal operation mode is given after a given standby time (t wu ). (automatic return function)
YDA147 catalog no.:lsi-4da147a61 21 ? dc detection function this is the function to protect the speaker connected to the digital amplifier output when a dc signal is continuously output from the digital amplifier. when muten terminal=l, the dc detection function is disabled. when a voltage in excess of a given time (t dcdet ) and a given level (v dcdet ) is output to the digital amplifier output, the dc detection mode is given. this state outputs an l level signal from protn terminal and digital amplifier output terminals become weak low state (a state grounded through a high resistance). once the dc detection mode is given, an l level signal keeps outputting from protn terminal even if the dc output state is cancelled. the protection mode is cancelled by turning off the power supply or inputting an l level signal to sleepn terminal momentarily. and, even if dc protection mode is established by detecti ng a dc signal, when protn term inal is externally connected to sleepn terminal, the protection mode is cancelled and protn terminal output is turned from l into hi-z state and a normal operation state is given after a given standby time (t wu ).
YDA147 22 catalog no.:lsi-4da147a61 examples of application circuits (caution) ? a ceramic capacitor of 1 f should be used as a bypass capacitor between the following terminals: pvddpl-pvssl, pvddml-pvssl, pvddpr-pvssr, and pvddmr-pvssr. please mount the cap acitor as close as possi ble to each terminal. ? a former-stage impe dance of input terminals should be 10k ? or less. ? select resistor values so that a voltage be comes 2.0v to 3.3v when protn terminal is at h level and current becomes 0.4ma or le ss when protn terminal is at l. ? for plimit terminal sett ing, see page 8 and 9. ? for a pull-up resistor for protn terminal, see pa ge 18 and 19. v ssa 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag external clock mute control sleep control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ (open) v ddp 220uf non-clip/drc1/drc2 mode select single operation in stereo mode (differential-input, external clock operation) sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr
YDA147 catalog no.:lsi-4da147a61 23 : v ddp 0.1uf 1uf 1uf 1uf 1uf 1uf 0.1uf lch input+ rch input+ single operation in stereo mode (single-ended input, external clock operation) 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp gain select v cc error flag external clock mute control sleep control (open) v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr v ssa single operation in stereo mode (differential-input, input signal level (externally set), external clock operation) v ddp 0.1uf 1uf 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp gain select v cc error flag external clock mute control sleep control (open) v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr v ssa
YDA147 24 catalog no.:lsi-4da147a61 single operation in stereo mode (single-ended input, input signal level (externally set), external clock operation) v ddp 0.1uf 1uf 1uf 1uf 1uf 1uf 0.1uf lch input+ rch input+ 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp gain select v cc error flag external clock mute control sleep control (open) v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr single operation in monaural mode (differential-input, external clock operation) v ddp 0.1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp gain select v cc error flag external clock mute control sleep control (open) v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr v ssa
YDA147 catalog no.:lsi-4da147a61 25 single operation in stereo mode (differential-input, internal clock operation) avss 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag mute control sleep control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ (open) v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr v ssa single operation in stereo mode (differential-input, external clock operation, automatic return setting) v ddp v ssp 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select external clock mute control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ (open) v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr v ssa
YDA147 26 catalog no.:lsi-4da147a61 master-slave operation (differential-input, external clock operation) master slave1 slave2 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag external clock mute control sleep control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag mute control sleep control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select v cc error flag (open) mute control sleep control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr v ssa v ssa v ssa
YDA147 catalog no.:lsi-4da147a61 27 master-slave operation (differential-input, external clock operation, automatic return setting) v ssp v ddp master slave1 slave2 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select external clock mute control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select mute control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr 1uf 1uf v ddp v ddp 1uf 1uf v ddp v ddp v ssp v ssp v ddp 0.1uf 1uf gain select mute control 1uf 1uf 1uf 1uf 0.1uf lch input- lch input+ rch input- rch input+ v ddp 220uf non-clip/drc1/drc2 mode select sleepn gain1 gain0 ckin ckout protn muten ncdrc1 avdd vref avss inrp inrm inlp pvddreg outpl outml pvssl pvddml pvddpl outml outpl plimit pvddpr pvddmr outpr pvssr outmr outpr outmr inlm ncdrc0 pvddpl outpl pvssl outml pvddml nc nc nc nc nc nc pvddpr outpr pvssr outmr pvddmr (open) v ssa v ssa v ssa
YDA147 28 catalog no.:lsi-4da147a61 electrical characteristics absolute maximum ratings *1) parameter symbol min. max. unit power supply terminal (pvdd) voltage range v ddp -0.3 20 v input terminal voltage range v in -0.3 4 v protn terminal voltage range v protn -0.3 4 v power dissipation (ta=25c) p d25 6.5 *2) w power dissipation (ta=70c) p d70 4.21 *2) w 4 layers power dissipation (ta=85c) p d85 3.4 *2) w power dissipation (ta=25c) p d25 3.72 *3) w power dissipation (ta=70c) p d70 2.38 *3) w sqfp48 2 layers power dissipation (ta=85c) p d85 1.93 *3) w power dissipation (ta=25c) p d25 2.67 *4) w power dissipation (ta=70c) p d70 1.70 *4) w lqfp48 1 layer power dissipation (ta=85c) p d85 1.38 *4) w junction temperature t jmax 150 c storage temperature t stg -40 150 c note) *1: absolute maximum ratings is values which must not be exceeded to guarantee device reliability and life, and when using a device in excess even a moment, it may immediately cause damage to device or may significantly deteriorate its reliability. *2: a value based on the following implementation conditions: board layer: 4 layers (fr-4), board size: 136 [mm] 85 [mm], board copper foil thickness: 35 [m], wiring density: 379%, exposed stage: soldering on the board through hole for heat radiation: 25 (55) holes from a point just below the exposed stage to the inner layer (vss) and b layer. *3: a value based on the following implementation conditions: board layer: 2 layers (fr-4), board size: 136 [mm] 85 [mm], board copper foil thickness: 35 [m], wiring density: 187%, exposed stage: soldering on the board through hole for heat radiation: 25 (55) holes from a point just below the exposed stage to b layer. *4: 1 layer board, copper foil thickness: 35 [m], wiring density: 80%, board size: 114.3 [mm] 76.2 [mm] recommended operating condition parameter symbol min. typ. max. unit power supply voltage (pvdd) v ddp 8 - 16.5 v digital terminals *1) h level input voltage v in 2.52 3.3 3.6 v sleepn terminal h level input voltage v in 2.0 3.3 3.6 v operating ambient temperature t a -40 25 85 c speaker impedance (stereo) r l 3.6 4 - ? speaker impedance (monaural) *2) r l 3.6 4 - ? note) *1: this specification is applicable to muten, ckin , ncdrc0, ncdrc1, gain0, and gain1(cmos i/f) pins *2: connect terminals between out pl and outpr and between out ml and outmr before use.
YDA147 catalog no.:lsi-4da147a61 29 dc characteristics (v ss =0v, v ddp =8v to 16.5v, ta=-40 c to 85 c , ckin=1mhz, unless otherwise specified. ) parameter symbol conditions min. typ. max. unit pvdd startup threshold voltage v huvlh - - 6.5 - v pvdd shutdown threshold voltage v huvll - - 6.0 - v dc detection voltage v dcdet pvdd=15v - 4 - v dc detection time t dcdet - - 0.5 - s digital terminal *1) h level input voltage v ih - 2.52 - - v digital terminal *1) l level input voltage v il - - - 0.9 v digital terminal *1) input impedance r in_d - 3.3 - - m ? sleepn terminal h level input voltage v ih_slpn - 2.0 - - v sleepn terminal l level input voltage v il_slpn - - - 0.8 v sleepn terminal input impedance r in_ slpn - 3.3 - - m ? ckout output voltage v ol i ol =4ma - - 0.4 v ckout output voltage v oh i oh =-4ma 2.4 - - v protn output voltage v ol i ol =0.4ma - - 0.4 v inlp, inlm, inrp, inrm terminals input impedance r in - - 18.8 - k ? avdd output voltage v dda 3.0 3.3 3.6 v avdd output current i dda - - 1 ma vref output voltage v ref - v dda /2 - v pvdd consumption current i ddp v ddp =12v, no-load - 32 - ma pvdd consumption current during power-down mode (sleepn=l) i sleep v ddp =15v, ta=25c - 20 - a pvdd consumption current during mute state (muten=l) i mute v ddp =15v, ta=25c - 16 - ma pvdd consumption current during no signal input i nosig v ddp =15v, ta=25c - 32 - ma note) *1: this specification is applicable to muten, ckin , ncdrc0, ncdrc1, gain0, and gai n1 (cmos i/f) terminals.
YDA147 30 catalog no.:lsi-4da147a61 ac characteristics (v ss =0v, v ddp =8v to 16.5v, ta=-40 c to 85 c , ckin=1mhz, unless otherwise specified.) parameter symbol min. typ. max. unit ckin input frequency f ckin 0.9 1,0 1.1 mhz ckin input duty dt ckext 40 - 60 % self-excited clock frequency f ck - 1.0 - mhz sleep recovery time t wu - 1 1.5 s mute recovery time t mrcv - - 1 ms analog characteristics (v ss =0v, v ddp =12v, ta=25 c , gain[1:0]=l,l, ncdrc[1:0]=l,l, ckin= ckin= l *2) , unless otherwise specified.) parameter symbol conditions min. typ. max. unit r l =4 ? , v ddp =12v, thd+n=10% 15 w r l =8 ? , v ddp =15v, thd+n=10% 15 w maximum momentary output (stereo) po r l =4 ? , v ddp =14v, thd+n=10%, 20 w r l =4 ? , v ddp =12v, thd+n=10% 20 w maximum momentary output (monaural) po r l =4 ? , v ddp =15v, thd+n=10% 30 w gain[1:0]=l,l 22 db gain[1:0]=l,h 28 db gain[1:0]=h,l 34 db voltage gain a v gain[1:0]=h,h 16 db total harmonic distortion rate (stereo) (bw::20khz) thd+n r l =4 ? ,p o =0.1w 0.01 % total harmonic distortion rate (monaural) (bw::20khz) thd+n r l =4 ? ,p o =0.2 w 0.02 % signal /noise ratio (stereo) (bw::20khz a-filter) snr r l =4 ? ,gain[1:0]=h,h 105 db signal /noise ratio monaural) (bw::20khz a-filter) snr r l =4 ? ,gain[1:0]=h,h 105 db residual noise (stereo) (bw::20khz a-filter) vn r l =4 ? ,gain[1:0]=h,h 48 vrms residual noise (monaural) (bw::20khz a-filter) vn r l =4 ? ,gain[1:0]=h,h 48 vrms channel separation ratio cs 1khz 80 db power supply rejection ratio (stereo) (pvdd applied) psrr vripple=200mv, f=1khz 60 db power supply rejection ratio (monaural) (pvdd applied) psrr vripple=200mv, f=1khz 60 db common mode rejection ratio (stereo) cmrr f=1khz 41 db common mode rejection ratio (monaural) cmrr f=1khz 41 db r l =4 ? 88 % maximum efficiency (stereo) r l =8 ? 92 % r l =4 ? , 20w output 93 % maximum efficiency (monaural) r l =8 ? , 10w output 93 % output offset voltage (stereo) *1) |vo| 5 15 mv output offset voltage (monaural) *1) |vo| 5 15 mv f=20hz -1 0 1 db frequency characteristics f res f=20khz -1 0 1 db note) *1: the offset voltage is denoted by considering a typical value and the maximum value as and 3 , respectively. *2: the same specification is applied to the external clock mode and internal clock (spread clock mode). all the values of analog characteristics were obtained in our ev aluation circumstance. depending upon pattern layout etc., characteristics may vary. the measurement is pe rformed with an 8 ? or 4 ? resistor connected in series with a 30h coil as an output load.
YDA147 catalog no.:lsi-4da147a61 31 example of typical characteristics (v ss =0v, v ddp =12v, ta=25 c, gain[1:0]=l,l, ncdrc[1:0]=l,l, ckin=1mhz, unless otherwise specified) power vs thd+n (YDA147, rl=4) (freq=1khz, with 20khz filter) 0.01% 0.10% 1.00% 10.00% 100.00% 0.0001 0.001 0.01 0.1 1 10 100 power [w] thd+n lch rch power vs thd+n (YDA147, rl=8) (freq=1khz, with 20khz filter) 0.01% 0.10% 1.00% 10.00% 100.00% 0.0001 0.001 0.01 0.1 1 10 100 power [w] thd+n lch rch power vs thd+n (YDA147, rl=4) (freq=1khz, with 20khz filter) 0.01% 0.10% 1.00% 10.00% 100.00% 0.0001 0.001 0.01 0.1 1 10 100 power [w] thd+n mono power vs thd+n (YDA147, rl=8) (freq=1khz, with 20khz filter) 0.01% 0.10% 1.00% 10.00% 100.00% 0.0001 0.001 0.01 0.1 1 10 100 power [w] thd+n mono freq vs thd+n (YDA147) (po=0.1w with 20khz filter) 0.01% 0.10% 1.00% 10.00% 100.00% 100 1000 10000 100000 freq [hz thd+n lch rch noise fft (YDA147) -160 -140 -120 -100 -80 -60 -40 -20 0 10 100 1000 10000 100000 freq [hz] noise level [dbv] lch rch frequency responce (YDA147) 0 10 20 30 10 100 1000 10000 100000 freq [hz] gain [dbv] lch rch power vs efficiency (YDA147,pvdd=12v) 50 55 60 65 70 75 80 85 90 95 100 051015 power [w] efficiency [%] 4 8
YDA147 32 catalog no.:lsi-4da147a61 pvdd vs max-power (YDA147 stereo) 0 5 10 15 20 25 30 35 40 5101520 pvdd [v] max power [w] 4 thd+n=1% 4 thd+n=10% 8 thd+n=1% 8 thd+n=10% pvdd vs max-power (YDA147 mono) 0 5 10 15 20 25 30 35 40 5101520 pvdd [v] max power [w] 4 thd+n=1% 4 thd+n=10% 8 thd+n=1% 8 thd+n=10% power dissipation vs output power (YDA147 stereo) 0 2 4 6 8 0 2 4 6 8 101214161820 output power [w] power dissipation [w] 12v_8_25 12v_8_70 power dissipation vs output power (YDA147 stereo) 0 2 4 6 8 0 2 4 6 8 10 12 14 16 18 20 output power [w] power dissipation [w] 15v_8_25 15v_8_70 power dissipation vs output power (YDA147 stereo) 0 2 4 6 8 02468101214161820 output power [w] power dissipation [w] 12v_4_25 12v_4_70 power dissipation vs output power (YDA147 stereo) 0 2 4 6 8 02468101214161820 output power [w] power dissipation [w] 15v_4_25 15v_4_70
YDA147 catalog no.:lsi-4da147a61 33 package outline < sqfp48 >
YDA147 34 catalog no.:lsi-4da147a61 < lqfp48 >
YDA147 catalog no.:lsi-4da147a61 35
YDA147 the specifications of this product are subject to improvement changes without prior notice. notice

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