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| 1 ' . $ p o u s p m m f e
4 u f q? 6 q % $ % $ $ p o w f s u f s . v m u j 7 p m u b h f % f u f d u p s 4 f s j f t 669 10 the xc651a series are step-up dc/dc converter and multi voltage detector ic s. cmos processes and laser trimming technology provide high accuracy and low power consumption. the xc651a comprises of a pfm controlled step-up dc/dc converter, a voltage detector with 4 x 5 level window comparators built-in, plus 2 other voltage detectors. the step-up dc/dc converter's en pin ( chip enable ) provides power consumption savings when the step-up operations are not operating ( stand-by mode ). the series is available in a small tssop-16 package. ( f o f s b m % f t d s j q u j p o independent power supply for each built-in block : each of the following built-in blocks is operated by a separate power supply : pfm controlled, step-up dc/dc converter ( pfm dc/dc ) 5 level window comparator ( mwvd ) negative logic : xc651a3 series positive logic : xc651a4 series voltage detector 1 with built-in delay circuit ( vd1 ) voltage detector 2 ( vd2 ) highly accurate set-up voltage : pfm controlled, step-up dc/dc converter : set-up voltage accuracy 2.5% 5 level window comparator : set-up voltage accuracy 2% voltage detectors 1, 2 : set-up voltage accuracy 2% set-up voltage range : pfm controlled, step-up dc/dc converter : 2.0v ~ 3.0v ( selectable in 0.1v steps) 5 level window comparator : 1.1v ~ 2.5v * ( selectable in 0.1v steps ) voltage detectors 1, 2 : 0.9v ~ 3.0v ( selectable in 0.1v steps ) operational voltage range : 0.9v ~ 6.0v small package : tssop-16 * note : the set-up voltage of the 5 level window comparator cannot be freely set-up due to the limitations of the circuit. please also note that the set-up voltage range of mwvd1 is 1.0v ~ 1.8v. battery powered equipment various portable equipment ' f b u v s f t " q q m j d b u j p o t cmos low power consumption pfm controlled, step-up dc/dc converter 5 level window comparator voltage detector 2 ( independent power supply ) tssop-16 package 4 @ 9 $ " ??
9 $ " 4 f s j f t 670 10 1 j o $ p o g j h v s b u j p o 1 j o " t t j h o n f o u . 8 7 % * / 3 * 1 . 8 0 6 5 $ % 7 0 6 5 5 4 4 0 1 5 0 1 7 * & 8 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 7 * / & 9 5 - 9 7 4 4 & / 7 * / 7 % & 5 7 % & 5 pin number pin name 1 mwvd in mwvd detect, mwvd current 2 rip mwvd ripple exclusion capacitor connection 3 mw out1 mwvd output 1 4 mw out2 mwvd output 2 5 mw out3 mwvd output 3 6 mw out4 mwvd output 4 7 cd vd1 delay time set-up capacitor connection 8 v in1 vd1 detect, vd1 current 9 v det1 vd1 output 10 v det2 vd2 output 11 v in2 vd2 detect, vd2 current 12 en dc/dc enable 13 v ss ground pin ( common ) 14 lx dc/dc built-in transistor switch output 15 ext dc/dc external transistor drive output 16 v out dc/dc output voltage monitor, dc/dc current function 1 b d l b h j o h * o g p s n b u j p o tssop-16 1 s p e v d u $ m b t t j g j d b u j p o ordering information e ' & n c p t t f e 5 b q f 3 j h i u ! & n c p t t f e 5 b q f - f g u q % & 4 $ 3 * 1 5 * 0 / 4 : . # 0 - % & 4 $ 3 * 1 5 * 0 / 4 : . # 0 - w ? ? ? ? ? ? qwe - 7 p m u b h f $ i b s b d u f s j t u j d t # b t f e p o j o u f s o b m t u b o e b s e t 1 b d l b h f 5 z q f +)(($% % f w j d f 0 s j f o u b u j p o % $ z c f " " " - & & 4 * ; & n n . * / 5 : 1 . " 9 " " " c $ % & & f - z 4 @ 9 $ " ?? 9 $ " 4 f s j f t 671 10 . b s l j o h tssop-16 5 4 4 0 1 y?y 3 f q s f t f o u t u i f e j g g v t j p o m p u y?y 3 f q s f t f o u t u i f q s p e v d u t f s j f t & y b n q m f 9 $ " 7 3 a a ? 5 0 1 7 * & 8 # m p d l % j b h s b n t . 8 7 % * / 3 * 1 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 $ % 7 * / 7 % & 5 7 % & 5 7 * / & / 7 4 4 - 9 & 9 5 7 0 6 5 . 8 0 6 5 . 8 7 % 1 ' . % $ % $ 7 % 7 % / p u f 1) overall composition note 1 : the v ss pin is common to each block. note 2 : the v dd pin is independent of each block. 4 @ 9 $ " ?? 9 $ " 4 f s j f t 672 10 - 9 & 9 5 & / 7 0 6 5 7 - 9 - j n j u t u f q 1 ' . $ p o u s p m 0 4 $ # v g g f s % $ % $ & o b c m f 7 % % 7 s f g 7 4 4 / p u f / p u f 7 % % . 8 7 % * / 3 * 1 3 3 * 1 7 s f g / p u f / p u f 7 4 4 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 / p u f / p u f / p u f / p u f 2) pfm dc/dc 3) mwvd note 1 : the v ss pin is common to each block. note 2 : v dd is independent for each block. note 1 : the v ss pin is common to each block. note 2 : v dd is independent for each block. note 3 : applies to the xc6514 series (positive logic) only. 4 @ 9 $ " ?? 9 $ " 4 f s j f t 673 10 7 * / $ % 7 4 4 7 % & 5 7 % % % f m b z $ j s d v j u 7 s f g / p u f / p u f 7 * / 7 4 4 7 % & 5 7 % % 7 s f g / p u f / p u f 4) vd 1 5) vd 2 note 1 : the v ss pin is common to each block. note 2 : v dd is independent for each block. note 1 : the v ss pin is common to each block. note 2 : v dd is independent for each block. 4 @ 9 $ " ?? 9 $ " 4 f s j f t 674 10 " c t p m v u f . b y j n v n 3 b u j o h t ta=25 o c parameter symbol conditions units output voltage v out 9 v lx pin voltage v lx 9 v lx pin current i lx 400 ma ext pin voltage v ext -0.3 ~ v out + 0.3 v ext pin current i ext 50 ma en input voltage v en -0.3 ~ v out + 0.3 v mwvdin input voltage mwvd in 9 v rip input voltage v rip -0.3 ~ mwvd in + 0.3 v mwout output voltage v mwout 9 v mwout output current i mwout 50 ma v in input voltage v in 9 v v det output voltage v det 9 v v det output current i det 50 ma cd input voltage v cd -0.3 ~ v in 1 + 0.3 v continuous total power dissipation operating ambient temperature topr -30 ~ +80 o c storage temperature tstg -40 ~ +125 o c mw pd 350 set-up voltage ? > $ ? q - + ' (note that the above is a sample part number and that actual part numbers will differ) ta=25 o c 1. pfm dc/dc v out 2.500 v v dfmw 1 1.275 v 2. mwvd v dfmw 2 1.245 v v dfmw 3 1.210 v v dfmw 4 1.060 v 3. vd1 v df 1 1.500 v 4.vd2 v df 2 0.950 v mw out 3 detect voltage mw out 4 detect voltage detect voltage 1 detect voltage 2 units output voltage mw out 1 detect voltage mw out 2 detect voltage set-up voltage value symbol block parameter & m f d u s j d b m $ i b s b d u f s j t u j d t 9 $ " " " 7 3 4 @ 9 $ " ?? 1. pfm dc/dc ta=25 o c parameter symbol conditions min typ max units circuit output voltage v out ext. components connected 2.438 2.500 2.563 v 1 operating voltage v in - - 6.0 v - operating start-up voltage v st ext. components connected, i out =1ma - 0.8 0.9 v 1 operating hold voltage v hld ext. components connected, i out =1ma 0.7 - - v 1 supply current 1 i dd 1 output voltage x 0.95 applied to v out - 35.0 56.9 a 2 supply current 2 i dd 2 output voltage + 0.5v applied to v out - 2.5 5.0 a 2 lx switch on resistance r swon output voltage x 0.95 applied to v out ,v lx =0.4v - 9.1 13.7 ? 2 lx leak current i lxl no ext. components, v out =v lx =10v - - 1.0 a 3 output voltage x 0.95 applied to v out , output voltage applied to l x , when the oscillator frequency is more than double ext h on resistance r exth output voltage x 0.95 applied to v out , v ext =v out - 0.4v - 140 210 ? 2 ext l on resistance r extl output voltage x 0.95 applied to v out , v ext =0.4v - 140 210 ? 2 duty ratio 1 dty1 output voltage x 0.95 applied to v out , ext waveform measurement 70 75 80 % 2 duty ratio 2 dty2 ext. components connected, i out =1ma, lx on time measurement -62- % 1 max oscillator frequency maxf osc output voltage x 0.95 applied to v out , ext waveform measurement 85 100 115 khz 2 stand-by current i stb output voltage x 0.95 applied to v out , v en =0v - 0.2 1.0 a 2 en h voltage v enh output voltage x 0.95 applied to v out , ext oscillation judgement 0.7 - - v 4 en l voltage v enl output voltage x 0.95 applied to v out , ext stopped judgement - - 0.2 v 4 en h current i enh output voltage x 0.95 applied to v out , v en =v out - - 0.25 a 4 en l current i enl output voltage x 0.95 applied to v out , v en =0v - - - 0.25 a 4 efficiency (note 1) effi ext. components connected -70- % 1 conditions : unless indicated, connect en to v out , v in =output voltage x 0.6, i out =10ma note : 1. effi={ [ (output voltage) x (output current) ] / [ (input voltage) x (input current) ] } x 100 - lx control voltage v lxlmt 0.7 1.1 v 2 9 $ " 4 f s j f t 675 10 4 @ 9 $ " ?? 9 $ " 4 f s j f t 676 10 2. mwvd (positive logic) ta=25 o c parameter symbol conditions min typ max units circuit mw out 1 detect voltage v dfmw 1 1.250 1.275 1.301 v 5 mw out 2 detect voltage v dfmw 2 1.220 1.245 1.270 v 5 mw out 3 detect voltage v dfmw 3 1.186 1.210 1.234 v 5 mw out 4 detect voltage v dfmw 4 1.039 1.060 1.081 v 5 mw out 1 hysteresis width v hysmw 1 (release voltage=v dfmw 1 + v hysmw 1) 4 10 - mv 5 mw out 2 hysteresis width v hysmw 2 (release voltage=v dfmw 2 + v hysmw 2 ) 410 - mv 5 mw out 3 hysteresis width v hysmw 3 (release voltage=v dfmw 3 + v hysmw 3 ) 410 - mv 5 mw out 4 hysteresis width v hysmw 4 (release voltage=v dfmw 4 x (1 + v hysmw 4 / 100) ) 2 - 8 % 5 supply current i ssmw mwvd in =2.0v - 5.0 20.0 a 6 operating voltage mwvd in 0.9 - 6.0 v - mw out 1 output current i outmw 1 nch v ds =0.5v, mwvd in =0.9v 0.18 1.8 - ma 7 mw out 2 output current i outmw 2 nch v ds =0.5v, mwvd in =0.9v 0.18 1.8 - ma 7 mw out 3 output current i outmw 3 nch v ds =0.5v, mwvd in =0.9v 0.18 1.8 - ma 7 mw out 4 output current i outmw 4 nch v ds =0.5v, mwvd in =0.9v 0.18 1.8 - ma 7 mw out 1 delay time t dlymw 1 release voltage output inversion, rip open - - 0.4 msec 8 mw out 2 delay time t dlymw 2 release voltage output inversion, rip open - - 0.4 msec 8 mw out 3 delay time t dlymw 3 release voltage output inversion, rip open - - 0.4 msec 8 mw out 4 delay time t dlymw 4 release voltage output inversion, rip open - - 0.4 msec 8 ripple rejection resistance r rip rip=1v, mwvd in =0v 250 500 1000 k ? 9 special parameter : v dfmw 1 v dfmw 2 v dfmw 3 4 @ 9 $ " ?? 9 $ " 4 f s j f t 677 10 3. vd 1 v df 1=1.5v ta=25 o c parameter symbol conditions min typ max units circuit detect voltage vd1 v df 1 1.470 1.500 1.530 v 5 hysteresis width vd1 v hys 1 (release voltage=v df 1 x (1 + v hys 1 / 100) ) 2 - 8 % 5 supply current i ss 1v in 1=2.0v - 1.5 3.0 a 6 operating voltage v in 1 0.7 - 6.0 v - output current v det 1 i out 1 n-ch vds=0.5v, v in 1=0.9v 0.22 2.2 - ma 7 4. vd 2 v df 2=0.95v ta=25 o c parameter symbol conditions min typ max units circuit detect voltage vd2 v df 2 0.931 0.950 0.969 v 5 hysteresis width vd2 v hys 2 (release voltage=v df 2 x (1 + v hys 2 / 100) ) 2 - 8 % 5 supply current i ss 2v in 2 =2.0v - 1.5 3.0 a 6 operating voltage v in 2 0.7 - 6.0 v - output current v det2 i out 2 n-ch v ds =0.5v, v in 2=0.9v 0.18 1.8 - ma 7 delay time v det2 t dly 2 release voltage output inversion - - 0.2 msec 8 50 100 msec 8 v det 1 h l delay time t hl 1 cd=3.3 f, v in 1=v df 1 x 1.1 v df 1 x 0.9 20 1000 2000 msec 8 v det 1 l h delay time t lh 1 cd=3.3 f, v in 1=v df 1 x 0.9 v df 1 x 1.1 500 4 @ 9 $ " ?? 9 $ " 4 f s j f t 678 10 5 f t u $ j s d v j u t 7 x b w f g p s n n f b t v s f n f o u 3 * 1 $ % & 9 5 & / 9 $ " 3 * 1 $ % & 9 5 & / 9 $ " 3 * 1 $ % 7 * / & 9 5 & / 9 $ . f b t v s f n f o u $ j s d v j u . 8 7 % * / . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 7 * / 7 0 6 5 - 9 7 4 4 7 * / 7 % & 5 7 % & 5 . 8 7 % * / . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 7 * / 7 0 6 5 - 9 7 4 4 7 * / 7 % & 5 7 % & 5 . 8 7 % * / . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 7 0 6 5 - 9 7 4 4 7 * / 7 % & 5 7 % & 5 4 % - * / 7 3 - $ - 7 - 9 7 & 9 5 & / 7 0 6 5 7 0 6 5 7 - 9 x b w f g p s n n f b t v s f n f o u x b w f g p s n n f b t v s f n f o u . f b t v s f n f o u $ j s d v j u . f b t v s f n f o u $ j s d v j u 4 @ 9 $ " ?? 9 $ " 4 f s j f t 679 10 7 0 6 5 7 & / " . 8 7 % * / 3 * 1 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 $ % 7 * / 7 0 6 5 & 9 5 - 9 7 4 4 & / 7 * / 7 % & 5 7 % & 5 9 $ x b w f g p s n n f b t v s f n f o u 7 % % % % l . 8 7 % * / 7 * / 7 * / l % % . 8 7 % * / 3 * 1 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 $ % 7 * / 7 0 6 5 & 9 5 - 9 7 4 4 & / 7 * / 7 % & 5 7 % & 5 9 $ 7 p m u b h f n f b t v s f n f o u q p j o u d p o o f d u f e u p 1 l l " . 8 7 % * / 3 * 1 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 $ % 7 * / 7 0 6 5 & 9 5 - 9 7 4 4 & / 7 * / 7 % & 5 7 % & 5 9 $ . 8 7 % * / 7 * / 7 * / . f b t v s f n f o u $ j s d v j u . f b t v s f n f o u $ j s d v j u . f b t v s f n f o u $ j s d v j u 4 @ 9 $ " ?? 9 $ " 4 f s j f t 680 10 % % % % % % . 8 7 % * / 3 * 1 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 $ % 7 * / 7 0 6 5 & 9 5 - 9 7 4 4 & / 7 * / 7 % & 5 7 % & 5 9 $ . 8 7 % * / 7 * / 7 * / " 7 % 4 7 7 % % % % l . 8 7 % * / 7 * / 7 * / l % % . 8 7 % * / 3 * 1 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 $ % 7 * / 7 0 6 5 & 9 5 - 9 7 4 4 & / 7 * / 7 % & 5 7 % & 5 9 $ $ % 7 ' 3 * 1 " . 8 7 % * / 3 * 1 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 . 8 0 6 5 $ % 7 * / 7 0 6 5 & 9 5 - 9 7 4 4 & / 7 * / 7 % & 5 7 % & 5 9 $ . f b t v s f n f o u $ j s d v j u 7 p m u b h f n f b t v s f n f o u q p j o u d p o o f d u f e u p 1 7 p m u b h f n f b t v s f n f o u q p j o u d p o o f d u f e u p 1 . f b t v s f n f o u $ j s d v j u . f b t v s f n f o u $ j s d v j u 4 @ 9 $ " ?? |
Price & Availability of XC651A1004VR
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