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1 www.semtech.com sc1480 ddr memory power supply controller power management revision: august 30, 2006 description features applications typical application circuit ? notebook computers ? cpu i/o supplies ? handheld terminals and pdas ? lcd monitors ? network power supplies ? constant on-time for fast dynamic response ? programmable vout based on external reference ? vin range = 1.8v ? 25v ? dc current sense using low-side rds(on) sensing or sense resistor ? 3ma reference output buffer ? low power s3 state ? resistor programmable frequency ? cycle-by-cycle current limit ? digital soft start ? output current source-sink capability ? overvoltage/under-voltage fault protection and pgood output ? under 10ua typical shutdown current ? low quiescent power dissipation ? 14-pin tssop package. also available in lead-free package which is fully weee and rohs compliant ? industrial temperature range ? integrated gate drivers with soft switching ? efficiency >90% the sc1480 is a single output, constant on-time synchronous-buck, pseudo-fixed frequency, pwm controller intended for use in notebook computers and other battery operated portable devices. features include high efficiency and fast dynamic response with no minimum on time, a reference input and a buffered refout pin capable of sourcing 3ma. the excellent transient response means that sc1480 based solutions will require less output capacitance than competing fixed frequency converters. the frequency is constant until a step in load or line voltage occurs, at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. after the transient event, the controller frequency will return to steady state operation. the sc1480 incorporates two power-reducing states, standby and shutdown. in standby mode, the switcher output is shutdown but the buffered reference output stays up, reducing quiescent current to a low 12 5a. this is particularly useful for reducing battery draw in systems which implement a suspend-to-ram (s3) state. the sc1480 can be completely shut down, drawing less than 10a. the integrated gate drivers feature adaptive shoot- through protection and soft switching. additional features include cycle-by-cycle current limit, digital soft-start, overvoltage and under-voltage protection, and a pgood output. r7 c9 c10 4.5v - 25v + c6 pgood +5vsb vdd = 2.5v r2 r4 c4 l1 r1 1.25vout c5 c2 r5 c3 u1 sc1480 1 2 3 4 5 6 7 8 9 10 11 12 13 14 refin ton refout vcca fbk pgood gnd pgnd dl vddp ilim lx dh bst c1 +5v d1 q2 c7 r6 d2 q1 c8 r3 refout +5vrun not recommended for new design not recommended for new design
2 ? 2006 semtech corp. www.semtech.com sc1480 power management absolute maximum ratings electrical characteristics noitanibmocni pl obmy sm umixa ms tinu dngaotnot 0.52+ot3.0 -v dngaottsb,hd 0.03+ot3.0 -v dngaotxl 0.52+ot0.2 -v dngpotdnga 3.0+ot3.0 -v xlottsb 0.6+ot3.0 -v dngaotpddv,accv 0.6+ot3.0 -v dngpotld,tuofer,mili,nifer,doogp,bf 0.6+ot3.0 -v tneibmaotnoitcnuj,ecnatsiserlamreht )4( aj 00 1w /c egnarerutarepmetnoitcnujgnitarep ot j 521+ot04 -c egnarerutarepmetegarot st gts 051+ot56 -c .ces01)gniredlos(erutarepmetdae lt dael 00 3c test conditions: v in = 2.5v, refin = 1.25, vcca = vddp = 5.0v, v out = 1.25v, r ton = 1m (300khz), 0.1% resistor dividers retemara ps noitidno cc 5 2c 521otc04 -s tinu ni mp y tx a mn i mx am seilppustupni egatlovtupniaccv 0. 55 . 45 . 5v egatlovtupnipddv 0. 55 . 45 . 5v egatlovtupnini v0 . 25 2v tnerrucgnitarepopdd vi ,tniopnoitaluger>bf daol a0 =5 0 1a tnerrucgnitarepoacc vi ,tniopnoitaluger>bf daol a0 =0 0 70 01 1a tnerrucybdnatsacc vd lohserhtvupddv 3 ? 2006 semtech corp. www.semtech.com sc1480 power management electrical characteristics cont. retemara ps noitidno cc 5 2c 521otc04 -s tinu ni mp y tx a mn i mx am emit-n or not )zhk003(m1= v5.2=niv 066 11 14 19 09 1s n r not )zhk006(k005= v5.2=niv 31 96 7 70 50 1s n emitffomuminim 00 40 5 5s n rorrenoitalugereni lv 5.5otv5.4=pddv,accv v52otv5.4=niv 40. 0v /% rorrenoitalugerdao l0 otv0=dngp-mili timil c3 . 0% ecnatsisertupnikbf 00 5k ? gnisnestnerruc-revo tnerrucknismili 0 191 1a tesfforotarapmoctnerru cm ili-dng p5 -5v m reffubecnerefer tnerrucecruostuofer 3a m dlohserhtelbanenifer 8. 05 5. 00 . 1v siseretsyhnifer 0 4v m egatlovtesff oa m0=tnerructuofe r0 1 -0 1v m am3=tnerructuofe r5 .21 -5 .2 1v m noitcetorptluaf )evitisop(timiltnerruc )2( r,xl-dngp mili k5 =0 50 40 6v m r,xl-dngp mili k01 =0 0 10 90 1 1v m r,xl-dngp mili k02 =0 0 20 8 10 2 2v m )evitagen(timiltnerru cx l-dng p0 41 -0 02 -0 01 -v m tluafegatlov-rednutuptu ot uoferottcepserhti w0 2 -8 2 -5 1 -% tluafegatlov-revotuptu ot uoferottcepserhti w0 1 +8 +2 1 +% yaledtluafegatlov-rev oh tvvoevobadecrofkb f0 . 2s egatlovtuptuowoldoog pa m1knis 4. 0v tnerrucegakaeldoog pv 5=doogp,noitalugernikb f1 a dlohserhtvudoog pt uoferottcepserhti w0 1 -2 1 -8 -% test conditions: v in = 2.5v, refin = 1.25, vcca = vddp = 5.0v, v out = 1.25v, r ton = 1m (300khz), 0.1% resistor dividers not recommended for new design not recommended for new design
4 ? 2006 semtech corp. www.semtech.com sc1480 power management notes: (1) when the inductor is in continuous conduction mode, the output voltage will have a dc regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) using a current sense resistor, this measurement relates to pgnd minus the voltage of the source on the low-side mosfet. (3) this device is esd sensitive. use of esd handling precautions is required. (4) measured in accordance with jesd51-1, jesd51-2 and jesd51-7. electrical characteristics cont. retemara ps noitidno cc 5 2c 521otc04 -s tinu ni mp y tx a mn i mx am yaledtluafdoog pd oogpedistuodecrofbf .wodniw 0. 2s dlohserhtegatlovrednuacc vv m001siseretsyhegdegnisi r0 . 47 . 33 . 4v dlohserhtegatlovrednupddv 3. 30 . 35 7. 3v siseretsyhegatlovrednupddv 05 2v m tuokcolerutarepmetrev os iseretsyhc0 15 6 1c tratstfos emitpmartrats-tfo s. timiltnerrucllufothgihnife r6 . 1s m emitknalbegatlov-redn un o-nrutspm s2s m srevirdetag emitdae dg nisirldroh d0 3s n ecnatsisernwod-llupl dw oll d8 . 06 .1 ? ? = ? = ? = = == = = = = = = = = () not recommended for new design not recommended for new design
5 ? 2006 semtech corp. www.semtech.com sc1480 power management pin configuration ordering information pin descriptions ecived )1( egakcap rtsti0841c s4 1-posst trtsti0841cs )2( 41-posst bve0841c sd raobnoitaulave #ni pe manni pn oitcnufnip 1n ifer .reffubecnereferdnaspmselbasidotdnuorgoteit.tupniecnereferlanretxe 2n ot .ylppustupniehtotrotsiserseiresaivtefsomreppufoemit-nostes.tupnitesemit-no 3t uofe r. am3ecruosnac.niptuptuoecnerefer 4a ccv .v5+otretlifcrahguorhttcennoc.ylppusgolanaehtroftupniegatlovylppus 5k bf .egatlovtuptuotcelesotspmsfotuptuotaredividrotsisermorftcennoc.tupnikcabdeef 6d oogp rewopgniwollofyaledelcyckcolcdexifaretfahgihseog.tuptuosomnniardnepodoogrewop .pu 7d ng a. dnuorggolana 8d ng p. dnuorgrewop 9l d. hctiwstefsomediswolehtroftuptuoevirdetag 0 1p ddv .spmselbasidotdnuorgoteit.srevirdetagehtroftupniegatlovylppusv5+ 1 1m ili rofecruosehtrognisnes)no(sdrroftefsomedis-wolfoniardottcennoc.tupnitimiltnerruc eromrofnoitcessnoitacilppaees.rotsisergnisnesdlohserhtahguorhtgnisnesrotsiser .noitamrofni 2 1x l. noitcennocrotcudniedongnihctiws 3 1h d. hctiwstefsomedishgihehtroftuptuoevirdetag 4 1t s b. evirdetagedishgihehtrofnoitcennocroticapactsoob notes: (1) only available in tape and reel packaging. a reel contains 2500 devices. (2) lead free product. this product is fully weee and rohs compliant. 1 2 3 4 5 6 7 bst refin top view (14 pin tssop) 13 12 14 11 10 dh ton lx refout ilim vcca vddp fbk dl pgood pgnd agnd 9 8 not recommended for new design not recommended for new design
6 ? 2006 semtech corp. www.semtech.com sc1480 power management 14 13 12 por/ss ot ref buffer + - fault monitor hi lo vddp vddq pwm ton vout control logic toff isense +5v oc zeroi on off pwm ov uv +5v vddq 1 refin 2 3 4 refout vin vcca 5 fbk vout 6 pgood 7 agnd 11 10 9 8 pgnd dl vddp ilim lx dh bst refout vddq = 2.5v + - vcca vddp ref+10% ref-10% ref-20% block diagram figure 1 not recommended for new design not recommended for new design
7 ? 2006 semtech corp. www.semtech.com sc1480 power management applications information +5v bias supply the sc1480 requires an external +5v bias supply in ad- dition to the battery. if stand-alone capability is required, the +5v supply can be generated with an external linear regulator. there are two inputs for the external +5v bias supply, vcca & vddp. the vcca input powers the analog section of the sc1480 while the vddp input provides power to the upper and lower gate drivers. vcca will need to be decoupled from the +5v supply through a 10 ohm resistor and the addition of a filter capacitor from vcca to ground. vcca and vddp must be separate in order to utilize the low power s3 state of the sc1480. the bat- tery input vin and the +5v input vcca can be tied to- gether if the input voltage is fixed from +4.5v to +5.5v; however, as before, vcca will need to be decoupled from the +5v supply through a 10 ohm resistor and the addi- tion of a filter capacitor from vcca to ground. pseudo-fixed frequency constant on-time pwm controller the pwm control architecture consists of a constant-on- time, pseudo fixed frequency pwm controller, (figure 1). the output ripple voltage developed across the output filter capacitors esr provides the pwm ramp signal elimi- nating the need for a current sense resistor. the high- side switch on-time is determined by a one-shot whose period is directly proportional to output voltage and in- versely proportional to input voltage. a second one-shot sets the minimum off-time to 400ns typically. on-time one-shot (t on ) the on-time one-shot comparator has two inputs. one input looks at the output voltage, while the other input samples the input voltage and converts it to a current. this input proportional current is used to charge an in- ternal on-time capacitor. the ton time is the time re- quired for the voltage on the capacitor to charge from zero volts to vout, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. this imple- mentation results in a nearly constant switching frequency without the need of a clock generator. s50 v v )10x37r(10x3.3t in out 3 ton 12 on + ? ? ? ? ? ? ? ? ?+? = ? r ton is a resistor connected from the input supply to the ton pin. the graph on page 19 shows the relationship between r ton and switching frequency. reference i/o the reference input can be generated off of a 2.5v or vddq supply by a simple resistive divider. resistors less than 100k ohms should be used and a small filter ca- pacitor from the reference input to ground of 0.1uf will remove any ripple voltage present on the input. the in- put has a common mode range of the refin threshold to 2.5v. the voltage on the reference input passes through a unity gain buffer prior to being sent to refout. this reference output has a class a output stage with 3ma of sourcing capacity. it has a pull-down impedance of 50k. the out- put will require a small rc filter of 10 ohms and 1f to maintain stability. shutdown, suspend to ram and run mode the sc1480 has three modes of operation: shutdown, suspend to ram, and run mode. all three modes must have vcca connected at all times. shutdown mode is controlled by refin. when refin is below 0.8v, the ref- erence buffer will be off and the smps is disabled. in this mode the bias current of the device will be less than 10 a. suspend to ram, or s3 state, is controlled by refin and vddp. with refin is above 0.8v and vddp is low (below 3v), the device will output the reference voltage onto refout, but the smps is disabled. in this mode the bias current is approximately 125 a. run mode is activated by maintaining refin above 0.8v and vddp above 3v. in this mode the reference and smps are active. current limit circuit current limiting of the sc1480 can be accomplished in two ways. first, the device can implement on-state re- sistance of the low-side mosfet as the current sensing element (rds on sensing). second, the device can accept a resistive element in the low-side source (r sense, resistor sensing). the second method offers greater accuracy of the current limit threshold over rds on sensing, at the added expense of a sense resistor and associated effi- ciency loss. whether rds on sensing or r sense resistor sensing is used, not recommended for new design not recommended for new design
8 ? 2006 semtech corp. www.semtech.com sc1480 power management applications information (cont.) a scaling resistor between lx and ilim is required. this resistor, r ilim , is connected to a 10 a current source within the sc1480 through the ilim pin. this sets a volt- age drop equal to 10 a times r ilim . as the current in- creases through the lower mosfet, the phase pin volt- age will decrease until the offset voltage caused by r ilim is reached and ilim < pgnd. at this point an overcurrent trip signal is issued. current limiting will prevent the firing of a dh on-pulse, thereby reducing the switching fre- quency. as the frequency decreases, the output voltage will drop until an under-voltage shutdown is reached. the current sensing circuit actually limits the inductor valley current (see figure 2). this means that if the cur- rent limit is set to 10a, the peak current through the inductor would be 10a plus the peak ripple current, and the average current through the inductor would be 10a plus 1/2 the peak-to-peak ripple current. the equations for setting the valley current and calculating the average current through the inductor are shown below: () on ilim oc rds r a10valleyil ?= ()() 2 i valleyil average il l oc oc ? + = i limit i load i peak inductor curren t time valley current-limit threshold point figure 2 sc1480 +5v l1 c2 8 9 10 11 12 13 14 pgnd dl vddp ilim lx dh bst d1 q1 + c1 q2 vout fbk d2 +vin + c3 r1 figure 3 schematic of rds on sensing circuit is shown in figure 3 with rds on of q2. similarly, for resistor sensing, the current through the lower mosfet and the source sense resistor develops a voltage that opposes the voltage developed across r ilim. when the voltage developed across the r sense resistor reaches voltage drop across r ilim, an overcurrent will be issued. the overcurrent equation when using an exter- nal sense resistor is: () sense ilim oc r r a10valleyil ?= schematic of resistor sensing circuit is shown in figure 4 with r ilim = r1 and r sense = r2. + c1 +5v sc1480 8 9 10 11 12 13 14 pgnd dl vddp ilim lx dh bst +vi n r1 q2 c2 d1 r2 q1 vout + c3 d2 fbk l1 figure 4 not recommended for new design not recommended for new design
9 ? 2006 semtech corp. www.semtech.com sc1480 power management applications information (cont.) power good output power good is an open-drain output and requires a pull- up resistor. when the output voltage is 10% above or below its set voltage, pgood gets pulled low. it is held low until the output voltage returns to within 10% of the output set voltage. pgood is also held low during start- up and will not be allowed to transition high until the out- put reaches 90% of its set voltage. there is a slight delay built into the pgood circuit to prevent false transitions. output overvoltage protection when the output exceeds 10% of the its set voltage the low-side mosfet is latched on. it stays latched and the smps is off until the enable input or por is toggled. there is a slight delay built into the ov protection circuit to pre- vent false transitions. output undervoltage protection when the output is 20% below its set voltage the output is latched in a tristated condition, and the smps is off until the enable input or por is toggled. there is a slight delay built into the uv protection circuit to prevent false transitions. por, uvlo and softstart an internal power-on reset (por) occurs when vcca ex- ceeds 3v, resetting the fault latch and soft-start counter, and preparing the pwm for switching. vcca undervoltage lockout (uvlo) circuitry inhibits switching and forces the dl gate driver high until vcca rises above 4.1v. at this time the circuit will come out of uvlo and begin switch- ing, and the softstart circuit being enabled, will progres- sively limit the output current over a predetermined time period. the ramp occurs in four steps: 25%, 50%, 75% and 100%, thereby limiting the slew rate of the output voltage. there is 100mv of hysteresis built into the uvlo circuit and when the vcca falls to 4.0v the output driv- ers are shutdown and tristated. mosfet gate drivers the dh and dl drivers are optimized for driving moder- ate-sized high-side, and larger low-side power mosfets. an adaptive dead-time circuit monitors the dl output and prevents the high-side mosfet from turning on, until dl is fully off, and conversely, monitors the dh output and prevents the low-side mosfet from turning on until dh is fully off. be sure there is low resistance and low induc- tance between the dh and dl outputs to the gate of each mosfet. the high-side gate driver is equipped with turn-on soft switching to reduce gate drive power dissipation. when a dh turn-on is initiated the pull-up resistance is 10 ohms. this limits the peak high-side gate current before the mosfet is conducting current. the peak gate current plays a large role in gate driver switching losses. when the high-side mosfet begins conducting, and lx starts to rise, the pull-up resistance on dh changes to 2 ohms. design procedure prior to any design of a switch mode power supply (smps) for notebook computers, determination of input voltage, load current, switching frequency and inductor ripple cur- rent must be specified. input voltage range the maximum input voltage (vin max ) is determined by the highest ac adaptor voltage. the minimum input voltage (vin min ) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. maximum load current there are two values of load current to consider. con- tinuous load current and peak load current. continuous load current has more to do with thermal stresses and therefore drives the selection of input capacitors, mosfets and commutation diodes. whereas, peak load current determines instantaneous component stresses and filtering requirements such as, inductor saturation, output capacitors and design of the current limit circuit. switching frequency switching frequency determines the trade-off between size and efficiency. increased frequency increases the switching losses in the mosfets, since losses are a func- tion of vin 2 . knowing the maximum input voltage and budget for mosfet switches usually dictates where the design ends up. inductor ripple current low inductor values create higher ripple current, result- ing in smaller size, but are less efficient because of the high ac currents flowing through the inductor. higher in- ductor values do reduce the ripple current and are more efficient, but are larger and more costly. not recommended for new design not recommended for new design
10 ? 2006 semtech corp. www.semtech.com sc1480 power management applications information (cont.) the selection of the ripple current is based on the maxi- mum output current and tends to be between 20% to 50% of the maximum load current. again, cost, size and efficiency all play a part in the selection process. design example the following design example is for the evaluation board schematic shown on page 16. while most ddr supplies have a maximum load of 3a, the following design was meant for applications beyond ddr memory. therefore, this design will have an input voltage from 5v to 19v, with an output voltage of 1.25v at 5a of load current. inductor selection the switching frequency is set to 300khz which yields a good trade-off of size and efficiency. r ton is chosen to be 1m ohm for a switching frequency of 300khz. be- cause ripple voltage is used as the feedback mechanism of this device, this leads to the choice of the ripple cur- rent being 10% of load current. this will give a nice ripple voltage waveform for ensuring proper pwm triggering for this type of controller. 0.5a 50.1 ?il =?= lin out in out ? iv t)v(vv l ? ??? = h4l = setting the current limit the minimum current-limit threshold must be high enough to support the maximum load current. the valley of the inductor current occurs at: 2 il iload(max) ? ? , (see figure 2) therefore: 2 il - iload(max) ilim(low) ? > the inductor must not saturate under all conditions of operation. if the current limit is set to 6.5a the maximum current through the inductor will be: a7il5.6 =?+ setting the over current to 6.5a is calculated as follows: a10 ilocrds rilim on ? = rdson of the mosfet is a nominal 0.013 ohms, ac- counting for increased temperature effects use 0.015 ohm. k10 a10 5.6 015 .0 rilim = ? = the inductor chosen was a panasonic 4 h, 11a induc- tor. similarly, using a sense resistor to obtain a more accu- rate current limit would make use of the valley current equation. thus, for a 0.015 ohm resistor the rilim would calculate to the same 10k ohm ilim resistor will be w54.0 015 .066 =?? effecting the efficiency budget. output capacitor selection the output filter capacitor must have low effective se- ries resistance (esr) to meet the output ripple and load transient requirements, at the same time have high enough esr to satisfy stability requirements. in addition, the value of output capacitance must be high enough to absorb the inductor energy going from full-load to no- load without tripping the overvoltage protection circuit. for cpu load transients, how much esr is needed de- pends upon output voltage variation limits under a cpu load transient. the esr for this condition is given: load(max) out i v esr ? = in non cpu applications, the output capacitor size de- pends on how much esr is needed to maintain an ac- ceptable level of output voltage ripple. under these con- ditions the esr value is given: load(max) p)-out(p i v esr ? = however, for most cpu applications the minimum capaci- tance required is limited by the energy absorption of the output capacitor. the equation for determining the mini- mum capacitance can be found by the following equa- tion: 2 i 2 f 2 outout min vv il c ? ? = not recommended for new design not recommended for new design
11 ? 2006 semtech corp. www.semtech.com sc1480 power management applications information (cont.) where v f is the final output voltage after release of the load and v i is the initial voltage prior to the release of load. if no more than 100mv of output voltage variation is required between v f and v i , plugging in the numbers for the application circuit yields minimum output capaci- tance of 1000 f. as shown, a large amount of capaci- tance is required to absorb the energy of the inductor during a load release of 5a. in typical ddr memory appli- cations a load release of this magnitude is not an issue and therefore the application circuit can get by with 300 f of output capacitance. stability considerations: unstable operation shows up in two related but distinctly different ways: double pulsing and fast-feedback loop instability. double-pulsing occurs due to noise on the output or be- cause the esr is too low, causing not enough voltage ramp in the output signal. this causes the error amplifier to trigger prematurely after the 400ns minimum off-time has expired. double-pulsing will result in higher ripple voltage at the output, but in most cases is harmless. however, in some cases double-pulsing can indicate the presence of loop instability, which is caused by insuffi- cient esr. one simple way to solve this problem is to add some trace resistance in the high current output path. a side effect of doing this is output voltage droop with load. sc1480 esr requirements the constant on-time control used in the sc1480 regulates the ripple voltage at the output capacitor. this signal consists of a term generated by the output esr of the capacitor and a term based on the increase in voltage across the capacitor due to charging and discharging during the switching cycle. the minimum esr is set to generate the required ripple voltage for regulation. for most applications the minimum esr ripple voltage is dominated by pcb layout and the properties of sp or poscap type output capacitors. for applications using ceramic output capacitors the absolute minimum esr must be considered. existing literature describing the esr requirements to prevent double pulsing does not accurately predict the performance of constant on-time controllers. a time domain model of the converter was developed to generate equations for the minimum esr empirically. if the esr is low enough the ripple voltage is dominated by the charging of the output capacitor. this ripple voltage lags the on-time due to the lc poles and can cause double pulsing if the phase delay exceeds the off-time of the converter. referring to figure 3, the equation for the minimum esr as a function of output capacitance and switching frequency and duty cycle is; () ? ? ? ? ? ? ? ? ? ? ? ? ????? ? ? ? ? ? ? ?+ > d1 2 fscout2 fs 200000 -fs 31 esr where d = vout/vin. plugging in the numbers for this design esr > 0.004 ohms. input capacitor selection input capacitors are selected based upon the input ripple current demand of the converter. first determine the input ripple current expected and then choose a capacitor to meet that demand. the input rms ripple current can be calculated as follows: in out out in out rms v i )v(vvi ? ? = ? therefore, for a maximum load current of 6.0a , the input capacitors should be able to safely handle 3a of ripple current. for the eval board, we chose two 10f, 25v ceramic capacitors. each capacitor has a ripple current capability of 2a. mosfet switch selection the current selection of mosfets are determined by the setting of the overcurrent limit circuit and the maximum input voltage. the next step is to determine their power handling capability. for the eval board the isi4484 meet the voltage and current requirements. this is a 30v, 10a fet. based on 85c ambient temperature, 150c junction temperature and thermal resistance, their power handling is calculated as follows: power limit for upper & lower fet: t j = 150c; t a = 85c; ja = 50c/w not recommended for new design not recommended for new design
12 ? 2006 semtech corp. www.semtech.com sc1480 power management applications information (cont.) 1.3w 50 85150tt p ja aj t = ? = ? = each fet must not exceed 1.3w of power dissipation. mosfet power dissipation worst-case conduction losses occur at the duty factor extremes. for the high-side mosfet, the worst-case conduction power dissipation occurs at minimum battery voltage: )on(ds load 2 minin out duc r i )(v v p ??= typically, a small high-side mosfet is selected to reduce switching losses at high input voltages. however, the rds(on) limits how small the mosfet can be. another element of loss in the upper mosfet is the switching loss, especially at high input voltages, those seen when the ac adaptor is applied. the upper mosfet switching losses can be estimated as follows: gate load )max(in 2 rss dus i if v c p ??? = where crss is the reverse transfer capacitance of the upper mosfet and igate is the peak gate-drive source/ sink current which is approximately 1a for the sc1480. for the low-side mosfet the there are only conduction loses to be concerned about since the commutation diode is active while the lower mosfet switches. the worst- case power dissipation occurs at maximum battery voltage: )on(ds load 2 maxin out dlc r i )(v v -1 p ?? ? ? ? ? ? ? = adding up the power dissipation for each mosfet can now proceed and the total for each mosfet should not exceed 1.3w which was calculated earlier to be the maximum power dissipation under worst-case conditions. dropout performance the output voltage adjust range for continuous- conduction operation is limited by the fixed 500ns (maximum) minimum off-time one-shot. for best dropout performance, use the slowest on-time setting of 200khz. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. the ic duty-factor limitation is given by: )(t)(t )(t duty maxoff minon minon + = be sure to include inductor resistance and mosfet on- state voltage drops when performing worst-case dropout duty-factor calculations. layout guidelines as with any high frequency switching regulator, it is advisable to practice a careful layout strategy. this includes keeping loop area as small as possible. and properly decoupling lines that pull large currents in short periods of time. to keep loop area small always use a ground plane and if possible split the plane in two areas, signal gnd and power gnd, then tie the two together at one point. be sure that high current paths have low inductance by making trace widths wide where possible. the sc1480 pin-outs contain digital signals on the right and analog signals on the left side of the device. this facilitates the isolation of digital and analog signals enabling effective layout of the device. in summary follow these guidelines for good pc board layout:: ? keep high-current paths short, especially at the ground terminals. ? tie agnd and pgnd together close to the ic. ? keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pc boards (2oz vs 1oz) can enhance full-load efficiency by 1% or more. ? connect the ilimit resistor as close to the lower mosfet drain as possible, and keep the resistance distance from the ilim pin to the drain short. this will improve current limit accuracy. 1480 system dc accuracy two ic parameters effect system dc accuracy, the error comparator offset voltage, and the switching frequency variation with line and load. the 1480 regulates to the refout voltage not the refin voltage. since ddr specifications are written with respect to refout, the offset of the reference buffer does not create a regulation error. not recommended for new design not recommended for new design
13 ? 2006 semtech corp. www.semtech.com sc1480 power management applications information (cont.) the error comparator offset is trimmed so that it trips when vout is 1.25 volts +/-1% at room temperature. this offset does not drift significantly with supply and temperature. thus, the error comparator contributes 1% or less to dc system inaccuracy. the on pulse in the sc1480 is calculated to give a pseudo fixed frequency. nevertheless, some frequency variation with line and load can be expected. this variation changes the output ripple voltage. because constant on regulators regulate to the valley of the output ripple, ? of the output ripple appears as a dc regulation error. for example, if refout=1.25 volts, then the valley of the output ripple will be 1.25 volts. if the ripple is 20mv with vin=6, then the dc output voltage will be 1.26 volts. if the ripple is 40mv with vin=25 volts, then the dc output voltage will be 1.27 volts. the best way to minimize this effect is to minimize the output ripple. to compensate for valley regulation it is usually desirable to use passive droop. take the feedback directly from the output side of the inductor incorporating a small amount of trace resistance between the inductor and output capacitor. this trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. passive droop also improves stability so it should be used when possible. thermal considerations the junction temperature of the device may be calculated as follows: c ptt jadaj ?+= where: t a = ambient temperature (c) p d = power dissipation in (w) ja = thermal impedance junction to ambient from absolute maximum ratings (c/w) the power dissipation may be calculated as follows: wfqvi vcca p gg vcca d ??+?= where: vcca = chip supply voltage (v) i vcca = operating current (a) v g = gate drive voltage, typically 5v (v) q g = fet gate charge, from the fet datasheet (c) f = switching frequency (khz) inserting the following values as an example: t a = 85c ja = 100c/w vcca = 5v i vcca = 1100a (data sheet maximum) v g = 5v q g = 60nc f = 300khz gives us: () c95100103001060510 1100 585t 3 9 6 j =?????+??+= ? ? as can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout. not recommended for new design not recommended for new design
14 ? 2006 semtech corp. www.semtech.com sc1480 power management 4.5v - 25v c6 1uf r6 10k 1.25vout c10 10uf pgood c7 1000pf + c9 150uf r1 20k r4 10 r7 no_pop r5 1m +5v_sus r3 20k 2.50v_sus +5v_ru n c2 10uf/25v q1 si4818dy 4 1 2 3 5 6 7 8 d1 zhcs400 refout u1 sc1480 1 2 3 4 5 6 7 8 9 10 11 12 13 14 refin ton refout vcca fbk pgood gnd pgnd dl vddp ilim lx dh bst +5v c8 0.01uf c1 10uf/10v l1 4.1uh c3 1uf c4 1uf c5 0.1uf r2 1m vin = 4.5v - 25v vout = 1.25v; iout = 3a reference design not recommended for new design not recommended for new design
15 ? 2006 semtech corp. www.semtech.com sc1480 power management met iy titnau qe cnerefe rt ra pr odnev 111 cv 01/fu01 212 cv 52/fu01 33 6 c,4c,3 cf u1 415 cf u1.0 517 cf p0001 618 cf u10.0 719 cf u051 810 1 cf u01 911 d0 04schz 0 111 lh u1.4 1 111 qy d8184is 2 12 3 r,1 rk 02 3 12 5 r,2 rm 1 4 114 r0 1 5 116 rk 01 6 117 rp opon 7 111 u0 841cs reference design - bill of material not recommended for new design not recommended for new design
16 ? 2006 semtech corp. www.semtech.com sc1480 power management evaluation board schematic r11 0 tp3 5vrun r1 750 +5v c2 10uf/6.3v vout_tp c1 10uf/6.3v j2 vin 1 2 tp8 rgnd c7 1uf l1 4uh d1 zhcs400 c5 10uf/25v tp6 rgnd r7 10k 1.25v c15 1uf u1 sc431l sp2 q1 si4884 4 5 3 1 2 6 7 8 tp1 +5v r5 1m r3 12.4k r10 no_pop tp5 refi tp2 gnd r2 100 q2 si4884 4 5 3 1 2 6 7 8 tp9 pgd r8 no_pop +5v r4 10 c8 0.1uf + c11 150uf u2 sc1480 1 2 3 4 5 6 7 8 9 10 11 12 13 14 refin ton refout vcca fbk pgood gnd pgnd dl vddp ilim lx dh bst tp4 gnd 1.25v d2 mbrs140t3 sp1 c9 1uf r6 1m r9 0 phase_tp c14 1000pf + c10 150uf c4 10uf/25v c13 1uf j1 5vrun 1 2 tp7 refo c6 0.1uf c16 no_pop c3 1uf j3 vout 1 2 c12 10uf/6.3v not recommended for new design not recommended for new design
17 ? 2006 semtech corp. www.semtech.com sc1480 power management evaluation board - bill of materials met iy titnau qe cnerefe rt rap 13 2 1c,2c,1 cv 3.6/fu01 25 5 1c,31c,9c,7c,3 cf u1 32 5 c,4 cv 52/fu01 42 8 c,6 cf u1.0 52 1 1c,01 cf u051 614 1 cf p0001 73 6 1c,01r,8 rp op_on 811 d0 04schz 912 d3 t041srbm 0 111 jt sopredaeh 1 12 3 j,2 jk cajananab 2 111 lh u4 3 12 2 q,1 q4 884is 4 111 r0 57 5 112 r0 01 6 113 rk 4.21 7 114 r0 1 8 12 6 r,5 rm 1 9 117 rk 01 0 22 1 1r,9 r0 1 22 2 ps,1p st nioptseteborp 2 29 9 pturht1pt 3 211 ul 134cs 4 212 u0 841cs not recommended for new design not recommended for new design
18 ? 2006 semtech corp. www.semtech.com sc1480 power management gerber plots silk screen layer bottom layer power ground layer analog ground layer top layer not recommended for new design not recommended for new design
19 ? 2006 semtech corp. www.semtech.com sc1480 power management sc1480evb efficiency at v out = 1.25v sc1480evb line regulation at v out = 1.25v sc1480evb load regulation at v out = 1.25v frequency vs. input voltage (i out = 1a, v out = 1.25v, rton = 1m) frequency vs. load current (v in = 15v, v out = 1.25v, rton = 1m) rton vs. frequency (v in = 15v, v out = 1.25v, i out = 1a) 60 65 70 75 80 85 90 95 100 0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 output current (amps) efficiency (%) vin=25v vin=14v vin=4.5v 0 0.1 0.2 0.3 0.4 0.5 0.6 012345 load current (amps) load regulation (%) vin=4.5v vin=10v vin=14v vin=19v vin=25v 200 210 220 230 240 250 260 270 280 290 0123456 load current (amps) frequency (khz) 0 0.1 0.2 0.3 0.4 0.5 0.6 4.5 10 14 19 25 input voltage (volts) line regulation (%) iout=0a iout=1a iout=2a iout=3a iout=4a iout=5a 0 100 200 300 400 500 600 400 500 600 700 800 1000 1500 rton (kohms) frequency (khz) 200 210 220 230 240 250 260 270 280 5 10152025 input voltage (volts) frequency (khz) typical characteristic (cont.) not recommended for new design not recommended for new design
20 ? 2006 semtech corp. www.semtech.com sc1480 power management upper trace: phase lower trace: output ripple voltage upper trace: 0a to -2a load transient lower trace: output ripple voltage upper trace: 0a to +2a and 0a to -2a transient lower trace: output ripple voltage upper trace: 0a to +2a transient lower trace: output ripple voltage typical characteristic (cont.) not recommended for new design not recommended for new design
21 ? 2006 semtech corp. www.semtech.com sc1480 power management marking diagram top mark bottom mark yy = two-digit year of manufacture ww = two-digit week of manufacture xxxxxx = wafer lot number xx = assembly lot number not recommended for new design not recommended for new design
22 ? 2006 semtech corp. www.semtech.com sc1480 power management outline drawing - tssop-14 land pattern - tssop-14 semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax (805) 498-3804 contact information visit us at: www .semt ech.com nom inches dimensions c n ccc aaa bbb 01 e l1 l e e1 d min a a1 a2 b dim millimeters min max nom max e reference jedec std mo-153, variation ab-1. 4. gage plane see detail detail a a 0.25 .026 bsc .252 bsc 14 .004 .169 .193 .173 .197 .007 - 14 0.10 0.65 bsc 6.40 bsc 4.40 5.00 - .177 .201 4.30 4.90 .012 0.19 4.50 5.10 0.30 pin 1 indicator seating bbb c a-b d ccc c plane dimensions "e1" and "d" do not include mold flash, protrusions 3. or gate burrs. datums and to be determined at datum plane controlling dimensions are in millimeters (angles in degrees). -b- notes: 1. 2. -a- -h- side view a b c d e h d 0 .008 - .004 .018 .003 (.039) .024 - .031 .002 - - - - 0.10 0.20 8 0 - 8 0.60 (1.0) .030 .007 0.45 0.09 .047 .042 .006 0.80 0.05 - 0.20 0.75 - 1.05 0.15 1.20 - - - bxn a a2 a1 e/2 2x e1 2x n/2 tips 12 3 aaa c l (l1) c 01 (.222) (5.65) z g y p (c) 4.10 .161 0.65 .026 0.40 .016 1.55 .061 7.20 .283 x inches dimensions z p y x dim c g millimeters this land pattern is for reference purposes only. consult your manufacturing group to ensure your company's manufacturing guidelines are met. notes: 1. not recommended for new design not recommended for new design

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