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1/24 october 1998 description the m29f040 is a non-volatile memory that may be erased electrically at the sector level, and programmed byte-by-byte. the interface is directly compatible with most microprocessors. ceramic dil 32, leadless chip carrier 32 and dual flat pack 32 packages are used. it is also available in plastic packages : dil 32, leaded chip carrier 32 and thin small out line package 32. for more density, the tsop package is available in reversed pinout. main features very fast access time : 90 ns (available also 120, 150 ns) 5 v 10% supply voltage for program and erase operations 5 v 10% supply voltage in read operations 10 m s typical programming time program/erase controller - program byte-by-byte - data polling and toggle protocol for p/e.c. status memory erase in sectors - 8 sectors of 64k bytes each - sector protection - multisector erase erase suspend and resume 100,000 program/erase cycles per sector low power consumption - 25 ma typical in standby standard eprom/otp memory packages : plastic (tbc) : pdip32, plcc32 and tsop32. ceramic : dil32, lccc32, cdfp32 (tbc) . military temperature ranges screening / quality this product is manufactured according to : mil-std-883, class b. tcs standard. qml planned tsop32 (n) 8 x 20 mm pdip32 (p) dil32 ceramic (c) plcc32 (fn) lccc32 (e) cdfp32 (z) (zt with tie bar) m29f040 cmos 4 megabit (512k x 8,8 sectors) single supply flash memory
m29f040 2/24 table 1 : signal names a0 a18 address inputs dq0 dq7 data input / outputs e chip enable g output enable w write enable v cc supply voltage v ss ground figure 1 : logic diagram vcc vss a0a18 dq0dq7 w e g 8 19 m29f040 figure 2 : dil, dual flat pack and normal tsop pin connections a18 1 a16 2 a15 3 a12 4 a7 5 a6 6 a5 7 a4 8 a3 9 a2 10 a1 11 a0 12 dq0 13 dq1 14 dq2 15 vss 16 32 vcc 31 w 30 a17 29 a14 28 a13 27 a8 26 a9 25 a11 24 g 23 a10 22 e 21 dq7 20 dq6 19 dq5 18 dq4 17 dq3 m29f040 figure 3 : plcc and lccc pin connections a7 a6 a5 a4 a3 9 a2 a1 a0 a14 a13 a8 a9 25 a11 g a10 e m29f040 dq0 dq7 17 dq1 dq2 vss dq3 dq4 dq5 dq6 32 a12 1 a15 a16 a18 vcc w a17 figure 4 : reverse tsop pin connections v cc 1 w a17 a14 a13 a8 a9 a11 8 g a10 e dq7 dq6 dq5 dq4 dq3 16 32 25 17 m29f040 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 v ss
m29f040 3/24 organisation the organisation is 512k x 8 bits with address lines a0-a18 and data inputs/outputs dq0dq7. memory control is provided by chip enable, output enable and write enable inputs. erase and program are performed through the internal program/erase controller (p/e.c.). data outputs bits dq7 and dq6 provide polling or toggle signals during automatic program or erase to indicate the ready/busy st ate of the internal program/erase controller. sectors erasure of the memory is in sectors. there are 8 sectors of 64k bytes each in the memory address space. erasure of each sector takes typically 1.5 seconds and each sector can be programmed and erased over 100,000 cycles. each sector may separately be protected and unprotected against program and erase. sector erasure may be suspended, while data is read from other blocks of the memory, and then resumed. table 2 : absolute maximum ratings (1) symbol parameter value unit t c case temperature 55 to +125 c t stg storage temperature 65 to +150 c v io (2) input or output voltages 0.6 to +7 v v cc supply voltage 0.6 to +7 v v a9 (2) a9 voltage 0.6 to +13.5 v notes : 1. except for the rating ooperating temperature rangeo, stresses above those listed in the table oabsolute maximum ragingso may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those in dicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect d evice reliability. 2. minimum voltage may undershoot to 2v during transition and for less than 20ns. bus operations seven operations can be performed by the appropriate bus cycles, read array, read electronic signature, output disable, standby , protect sector, unprotect sector, and write the command of an instruction. command interface command bytes can be written to a command interface (c.l.) latch to perform reading (from the array or electronic signature), e rasure or programming. for added data protection, command execution starts after 4 or 6 command cycles. first, second, fourth and fift h cycles are used to input a code sequence to the command interface (c.l.). this sequence is equal for all p/e.c. instructions. command itself and its confirmation if it applies are given on the third and fourth or sixth cycles. instructions seven instructions are defined to perform read memory array, read electronic signature, auto program, sector auto erase, auto b ulk erase, sector erase suspend and sector erase resume. the internal program/erase controller (p/e.c.) handles all timing and veri fica- tion of the program and erase instructions and provides data polling, toggle, and status data to indicate completion of program and erase operations. instructions are composed of up to six cycles. the first two input a code sequence to the command interface which is common to all p/e.c. instructions (see table 6 and table 7 for command descriptions). the third cycle inputs the instruction set up command i nstruction to the command interface. subsequent cycles output the addressed data for read operations. for added data protection, the instr uctions for program and sector or bulk erase require further command inputs. for a program instruction, the fourth command cycle inputs the address and data to be programmed. for an erase instruction (sector or bulk), the fourth and fifth cycles input a further code sequence before the erase confirm command on the sixth cycle. byte programming takes typically 10 m s while erase is performed in typically 1.5 seconds. erasure of a memory sector may be suspended, in order to read data from another sector, and then resumed. data polling, toggle and error data may be read at any time, including during the programming or erase cycles, to monitor the progress of the operation. when power is first applied or if vcc falls below v lko . the command interface is reset to read array.
m29f040 4/24 table 3 : operations operation e g w dq0 dq7 read v il v il v ih data output write v il v ih v il data input output disable v il v ih v ih hiz standby v ih x x hiz note 1 : x = v il or v ih table 4 : electronic signature code e g w a0 a1 a6 a9 other addresses dq0 dq7 manufact. code v il v il v ih v il v il v il v id don't care 20h device code v il v il v ih v ih v il v il v id don't care 0e2h table 5 : sector protection status code e g w a0 a1 a6 a16 a17 a18 other addresses dq0 dq7 protected sector v il v il v ih v il v ih v il sa sa sa don't care 01h unprotected sec- tor v il v il v ih v il v ih v il sa sa sa don't care 00h note 1 : sa = address of sector being checked device operations signal descriptions a0a18 address inputs. the address inputs for the memory array are latched during a write operation. the a9 address input is used also for the electronic signature read and sector protect verification. when a9 is raised to v id , either a read manufacturer code, read device code or verify sector protection is enabled depending on the combination of levels on a0, a1 and a6. when a0, a1 and a6 are low, the electronic signature manufacturer code is read, when a0 is high and a1 and a6 are low, the device code is read, and wh en a1 is high and a0 and a6 are low, the sector protection status is read for the sector addressed by a16, a17, a18. dq0dq7 data input/outputs. the data input a byte to be programmed or a command written to the c.l. both are latched when both chip enable e and write enable w are active. the data output is from the memory array, the electronic signature, the data polling bit (dq7), the toggle bit (dq6), the error bit (dq5) or the erase timer bit (dq3). ouputs are valid when chip enable e and output enable g are active. the output is high impedance when the chip is deselected or the outputs are disabled. e chip enable. the chip enable activates the memory control logic, input buffers, decoders and sense amplifiers. e high deselects the memory and reduces the power consumption to the standby level. e can also be used to control writing to the command register and to the memory array, while w remains at a low level. addresses are then latched on the falling edge of e while datas on the rising edge of e . the chip enable must be forced to v id during sector unprotect operations. g output enable. the output enable gates the outputs through the data buffers during a read operation. g is forced to v id level during sector protect and sector unprotect operations. w write enable. this input controls writing to the command register and address and data latches. addresses are latched on the falling edge of w , and data inputs are latched on the rising edge of w . vcc supply voltage. the power supply for all operations (read, program and erase). vss ground. vss is the reference for all voltage measurements.
m29f040 5/24 table 6 : instructions (notes are mentionned next page) mne. instr. cyc. 1st cycle 2nd cycle 3rd cycle 4th cycle op. addr. (1.5) data op. addr. (1.5) data op. addr. (1.5) data op. addr. (1) data rd read/ reset memory array 1+ write x 0f0h read read address data read read address data read read address data rd read memory array 3+ write x5555h 0aah write x2aaah 55h write x5555h 0f0h read read address data rsig read electronic signature 3+ write x5555h 0aah write x2aaah 55h write x5555h 90h read (2.3) signa- ture address signa- ture rsp read sector protection 3+ write x5555h 0aah write x2aaah 55h write x5555h 90h read ( 2.4) protec- tion address protect status(6) pg program 4 write x5555h 0aah write x2aaah 55h write x5555h 0a0h write address data input se sector erase 6 write x5555h 0aah write x2aaah 55h write x5555h 80h write x5555h (4) 0aah be bulk erase 6 write x5555h 0aah write x2aaah 55h write x5555h 80h write x5555h ( 4) 0aah es erase suspend 1 write x 0b0h read until toggle stops, then read all the data needed from any sector(s) not being erased then resume erase. er erase resume 1 write x 30h read data polling or toggle bit until erase completes or erase is suspended another time table 7 : instructions (notes are mentionned next page) mne. instr. cyc. 5th cycle 6th cycle 7th cycle op. addr. (1) data op. addr. data out op. addr. data out rd read/ reset memory array 1+ read read address data read read address data read read address data rd read memory array 3+ read read address data read read address data read read address data rsig read electronic signature 3+ read (2.3) signature address signature read (2.3) signature address signature read (2.3) signature address signature rsp read sector protection 3+ read (2.4) protection address protect status (6) read (2.4) protection address protect status (6) read (2.4) protection address protect status (6) pg program 4 read data polling or toggle bit until program completes se sector erase 6 write x2aaah (5) 55h write sector address 30h write (6) additional sector 30h be bulk erase 6 write x2aaah (5) 55h write x5555h (5) 10h read data polling or toogle bit until erase completes or erase is suspended another time es erase suspend 1 read until toggle stops, then read all the data needed from any sector(s) not being erased then resume erase. er erase resume 1 read data polling or toggle bit until erase completes or erase is suspended another time
m29f040 6/24 notes : 1. x = don't care. 2. the first cycle of the rd, rsp or rsig instruction is followed by read operations to read memory array, status register or el ectronic signature codes. any number of read cycles can occur after one command cycle. 3. signature address bits a0, a1, a6, at v il will output manufacturer code (20h). address bits a0 at v ih and a1, a6, at v il will output device code (0e2h). 4. protection address : a0, a6 at v il and a1 at v ih , other addresses within the sector to be checked a16, a17, a18 define this sector address. 5. address bits a16, a17, a18 are don't care for coded address inputs. 6. optional, additional sectors addresses must be entered within a 80 s delay after last write entry, timeout status can be verified through dq3 value. when full command is entered, read data polling or toggle bit until erase is completed. memory sectors the memory sectors of the m29f040 are shown in figure 7. the memory array is divided in 8 sectors of 64k bytes. each sector can be erased separately or any combination of sectors can be erased simultaneously. the sector erase operation is managed automatical ly by the p/e.c. the operation can be suspended in order to read from any another sector, and then resumed. sector protection provides additional data security. each sector can be separately protected or unprotected against program or erase. bringing a9 and g to v id initiates protection, while bringing a9, g and e to v id cancels the protection. the sector affected is addressed by the inputs on a16, a17, and a18. table 8 : commands hex code command 00h invalid / reserved 10h bulk erase confirm 30h sector erase resum / confirm 80h setup erase 90h read electronic signature / sector protection status 0a0h program 0b0h erase suspend 0f0h read array / reset table 9 : status register dq name logic level definition note 7 data polling o1o erase complete indicates the p/e.c. status, chek during program or erase and on com p letion before checking bits dq5 for o0o erase on going e rase, an d on comp l e ti on b e f ore c h ec ki ng bit s dq5 f or program or erase success. dq program complete dq program on going 6 toggle bit o1010101o erase or program on going successive read output complementary datas on dq6 while programming or erase o p erations are going on o0000000o program (o0o on dq6) complete w hil e p rogramm i ng or e rase opera ti ons are go i ng on. dq6 remain at constant level when p/e.c. operations are ld o1111111o erase or program (o1o on dq6) complete completed. 5 error bit o1o program or erase error es bit is set to o1o if p/e.c. has applied the maximum number of erase p ulses to the block without achieving an o0o program or erase success number of erase ulses to the block without achieving an erase verify. 4 reserved 3 erase time bit o1o erase timeout period expired p/e.c. erase operation has started. only possible com- mand entry is erase sus p end (es) additional sector to o0o erase timeout period on going mand entry is erase sus end (es) . additional sector to be erased in parallel can be entered to the p/e.c. 2 reserved 1 reserved 0 reserved note 1 : logic level o1o is high, o0o is low. 010001110 represent bit value in successive read operations.
m29f040 7/24 table 10 : ac measurement conditions interface levels input rise an fall times 10ns input pulse voltages 0.45v to 2.4v input ant output timing ref. voltages 0.8v and 2v figure 5 : ac testing input output waveform 2.4v 2.0v 0.45v 0.8v figure 6 : ac testing load circuit device under test 1.3v c l = 100 r f c l includes jig capacitance 1n914 3.3k w c l = 100 r f out table 11 : capacitance (1) (t a = 25 c, f = 1mhz) symbol parameter test condition min max unit c in input capacitance v in = 0v 20 pf c out output capacitance v out = 0v 20 pf note 1 : sampled only, not 100% tested. operations operations are defined as specific bus cycles and signals which allow memory read, command write, output disable, standby, read status bits, sector protect/unprotect, sector protection check and electronic signature read. they are shown in table 3. read. read operations are used to output the contents of the memory array, the status register or the electronic signature. both chi p enable e and output enable g must be low in order to read the output of the memory. the chip enable input also provides power control and should be used for device selection. output enable should be used to gate data onto the output independent of the device se lection. the data read depends on the previous command written to the memory (see instructions rd and rsig, and status bits). write. write operations are used to give instruction commands to the memory or to latch input data to be programmed. a write operatio n is initiated when chip enable e is low and write enable w is low with output enable g high. addresses are latched on the falling edge of w or e whichever occurs last. commands and input data are latched on the rising edge of w or e whichever occurs last.
m29f040 8/24 figure 7 : memory map and sector address table a18 a17 a16 1 11 1 10 1 01 1 00 0 11 0 10 0 01 000 64k bytes sector 64k bytes sector 64k bytes sector 64k bytes sector 64k bytes sector 7ffffh 70000h 6ffffh 60000h 5ffffh 50000h 4ffffh 40000h 3ffffh 30000h 2ffffh 20000h 1ffffh 10000h 0ffffh 00000h top address bottom address table 12 : dc characteristics (t c = 55 c, v cc = 5v 10 %) symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) ttl e = v il , g = v il , f = 6mhz 40 ma i cc2 supply current (standby) ttl e = v ih 1 ma i cc3 supply current (standby) cmos e = v cc 0.2v 100 a i cc4 supply current (program or erase) byte program, sector or bulk erase in progress 60 ma v il input low voltage 0.5 0.8 v v ih input high voltage 2 v cc + 0.5 v v ol output low voltage i ol = 12ma 0.45 v v oh output high voltage ttl i oh = 2.5ma 2.4 v output high voltage cmos i oh = 100 a v cc 0.4v v i oh = 2.5ma 0.85 x v cc v v id a9 voltage (electronic signature) 11.5 12.5 v i id a9 current (electronic signature) a9 = v id 50 a v lko supply voltage (erase and program lockout) 3.2 4.2 v
m29f040 9/24 table 13 : read ac characteristics (t c = 55 c ; v cc = 5 v 10 %) symbol alt parameter test condition 90 120 150 unit s ym b o l alt p arame t er t es t c on diti on min max min max min max u n it t avav t rc address valid to next address valid e = v il , g = v il 90 120 150 ns t avqv t acc address valid to output valid e = v il , g = v il 90 120 150 ns t elqx (1) t lz chip enable low to output transition g = v il 0 0 0 ns t elqv (2) t ce chip enable low to output valid g = v il 90 120 150 ns t glqx (1) t olz output enable low to output transition e = v il 0 0 0 ns t glqv (2) t oe output enable low to output valid e = v il 35 50 55 ns t ehqx t oh output enable high to output transition g = v il 0 0 0 ns t ehqz (1) t hz chip enable high to output hiz g = v il 20 30 35 ns t ghqx t oh output enable high to output transition e = v il 0 0 0 ns t ghqz (1) t df output enable high to output hiz e = v il 20 30 35 ns t axqx t oh address transition to output transition e = v il , g = v il 0 0 0 ns notes : 1. sampled only, not 100% tested. 2. g may be delayed by up to t elqv t glqv after the falling edge of e without increasing t elqv. output disable. the data outputs are high impedance when the output enable. (g ) is high with write enable (w ) high. standby. the memory is in standby when chip enable (e ) is high. the power consumption is reduced to the standby level and the outputs are high impedance, independent of the output enable (g ) or write enable (w ) inputs. electronic signature. two codes identifying the manufacturer and the device can be read from the memory, the manufacturer's code for tcs is 20h, and the device codes is e2h for the m29f040. these codes allow programming equipment or applications to automatical ly match their interface to the characteristics of the particular manufacturer's product. the electronic signature is output by a read operation when the voltage applied to a9 is at v id and address inputs a1 and a6 are at low. the manufacturer code is output when the address input a0 is low and the device code when this input is high. other address inp uts are ignored. the codes are output on dq0 dq7. this is shown in table 4. the electronic signature can also be read, without raising a9 to v id by giving the memory the instruction rsig (see below). sector protection. each sector can be separately protected against program or erase. sector protection provides additional data secu- rity, as it disables all program or erase operations. this mode is activated when both a9 and g are set to v id and the sector address is applied on a16, a17 and a18. sector protection is programmed using a presto f program like algorithm. protection is initiated b y edge of w fallin to v il . then after a delay of 100us, the edge of w rising to v ih will end the protection operation. protection verify is achieved by bringing g , e and a6 to v il while w is at v ih and a9 at v id . under these conditions, reading the data output will yield 01h if the sector defined by the inputs on a16, a17 and a18 is protected. any attempt to program or erase a protected sector will be ignored by t he device. any protected sector can be unprotected to allow content updating of bit contents. all sectors must be protected before an unpr otect operation. sector unprotect is activated when a9, g and e are at v id . the addresses inputs a6, a16, a12 must be maintained at v ih . sector unprotect is performed through a presto f erase like algorithm. unprotect is initiated by the edge of w falling to v il . after a delay of 10ms, the edge of w rising to v ih will end the unprotection operation. unprotect verify is achieved by bringing g and e to v il while a6 and w are at v ih and a9 at v id . in these conditions, reading the output data will yield 00h if the sector defined by the inputs on a16, a17 and a18 has been successfully unprotected. all combinations of a16, a17 and a18 must be addressed in order to ensure that all of th e 8 sectors have been unprotected. sector protection status is shown in table 5.
m29f040 10/24 figure 8 : read mode ac waveforms note : write enable (w ) = high instructions and commands the command interface (c.l.) iatches commands written to the memory. instructions are made up from one or more commands to per- form memory read, read electronic signature, sector erase, bulk erase, program, sector erase suspend and erase resume. com- mands are made of address and data sequences. addresses are latched on the falling edge of w or e and data is latched on the rising of w or e . the instructions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate t he command. they are followed by either further write cycles to confirm the first command or execute the command immediately. command seque ncing must be followed exactly. any invalid combination of commands will reset the device to read array. the increased number of cycl es has been chosen to assure maximum data security. commands are initialised by two preceding coded cycles which unlock the command interface. in addition, for erase, command confirmation is again preceeded by the two coded cycles. p/e.c. status is indicated during command execution by data polling on dq7, detection of toggle on dq6, or error on dq5 and era se timer dq3 bits. any read attempt during program or erase command execution will automatically output those four bits. the p/e.c . auto- matically sets bits dq3, dq5, dq6 and dq7. other bits (dq0, dq1, dq2 and dq4) are reserved for future use and should be masked. data polling bit dq7. when programming operations are in progress, this bit outputs the complement of the bit being programmed on dq7. during erase operation, it will outputs a '0'. after completion of the operation, dq7 will output the bit last programmed or a '1' after erasing. data polling is valid only effective during p/e.c. operation, that is after the fourth w pulse for programming or after the sixth w pulse for erase. it must be performed at the address being programmed or at an address within the sector being erased. if the b yte to be programmed belongs to a protected sector, the command is ignored. if all of the sectors are protected, dq7 will set to '0' for about 100 s, and then return to previous addressed memory data. see figure 11 for the data polling flowchart and figure 12 for the data poll ing wave- forms.
m29f040 11/24 table 14 : write ac characteristics, write enable controlled (t c = 55 c ; v cc = 5 v 10 %) symbol alt parameter 90 120 150 unit s ym b o l alt p arame t er min max min max min max u n it t avav t wc address valid to next address valid 90 120 150 ns t elwl t cs chip enable low to write enable low 0 0 0 ns t wlwh t wp write enable low to write enable high 45 50 50 ns t dvwh t ds input valid to write enable high 45 50 50 ns t whdx t dh write enable high to input transition 0 0 0 ns t wheh t ch write enable high to chip enable high 0 0 0 ns t whwl t wph write enable high to write enable low 20 20 20 ns t avwl t as address valid to write enable low 0 0 0 ns t wlax t ah write enable low to address transition 45 50 50 ns t ghwl output enable high to write enable low 0 0 0 ns t vchel t vcs v cc high to chip enable low 50 50 50 s t whqv1 (1) write enable high to output valid (program) 10 10 10 s t whqv2 (1) write enable high to output valid (erase) 1.5 30 1.5 30 1.5 30 sec t whgl t oeh write enable high to output enable low 0 0 0 ns note 1 : time is measured to data polling or toggle bit, t whqv = t whq7v + t q7vqv toggle bit dq6. when programming operations are in progress, successive attempts to read dq6 will output complementary data. dq6 will toggle following toggling of either g or e when g is low. the operation is completed when two successive reads yield the same output data. the next read will output the bit last programmed or a '1' after erasing. the toggle bit is valid only effective during p /e.c. operations, that is after the fourth w pulse for programming or after the sixth w pulse for erase. if the byte to be programmed belongs to a protected sector, the command will be ignored. if the sectors selected for erasure are protected, dq6 will toggle for about 100 s back to read. see figure 13 for toggle bit flowchart and figure 14 for toggle bit waveforms. error bit dq5. this bit is set to '1' by the p/e.c when there is a failure of byte programming, sector erase, or bulk erase that results in invalid data being programmed in the memory sector. in case of error in sector erase or byte program, the sector in which the e rror occured or to which the programmed byte belongs, must be discarded. other sectors may still be used. error bit resets to '0' after read /reset (rd) instruction. in case of success, the error bit will set to '0' during program or erase and to valid data after write operation is completed. erase timer bit dq3. this bit is set to '0' by the p/e.c. when the last erase command has been entered to the command interface and it is awaiting the erase start. when the waiting period is finished after 80 to 120 s dq3 returns back to '1'. coded cycles. the two coded cycles unlock the command interface. they are followed by a command input or a command confirma- tion. they consist in writing the data 0aah at address 5555h during first cycle and data 55h at address 2aaah during second cyc le. addresses are latched on the falling edge of w or e while data is latched on the rising edge of w or e. they happen on first and second cycles of the command write or on the fourth and fifth cycles. read (rd) instruction. the read instruction consists of one write operation giving the command 0f0h at address 2555h. it can be optionally preceded by the two coded cycles. subsequent read operations will read the memory array addressed and output the rea d byte. read electronic signature (rsig) instruction. this instruction uses the two coded cycles followed by one write cycle giving the com- mand 90h to address 5555h for command setup. subsequent read will output the manufacturer code, the device code or the sector protection status depending on the levels of a0, a1, a6, a16, a17 and a18. the manufacturer code, 20h, is output when the addre sses lines a0, a1 and a6 are low, the device code, 0e2h is output when a0 is high with a1 and a6 low. read sector protection. the use of read electronic signature (rsig) command also allows access to the sector protection status verify. after giving the rsig command, a0 and a6 are set to v il with a1 at v ih , while a16, a17 and a18 define the sector of the sector to be verified. a read in these conditions will output a 01h if sector is protected and a 00h if sector is not protected.
m29f040 12/24 figure 9 : write ac waveforms, w controlled figure 10 : write ac waveforms, e controlled note : address are latched on the falling edge of e , data is latched on the rising edge of e . bulk erase (be) instruction. this instruction uses six write cycles. the erase setup command 80h is written on third cycle to address 5555h after the two coded cycles. the bulk erase confirm command 10h is written at address 5555h on sixth cycle after another t wo coded cycles. if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts and the device is reset to read array. it is not necessary to program the array with 00h first as the p/e.c. will automatically do this before erasing to 0ffh. read operatlons after the sixth rising edge of w or e output the status register bits. during the execution of the erase by the p/e.c., data polling bit dq7 returns '0', then '1' on completion. the toggle bit dq6 toggles during erase operation and stops when erase is completed. after completion the status register bit dq5 returns '1 ' if there has been an erase failure because the erasure has not been v erified even after the maximum number of erase cycles have been executed.
m29f040 13/24 table 15 : write ac characteristics, chip enable controlled (t c = 55 c ; v cc = 5 v 10 %) sbl alt pt 90 120 150 uit symbol alt parameter min max min max min max unit t avav t wc address valid to next address valid 90 120 150 ns t wlel t ws write enable low to chip enable low 0 0 0 ns t eleh t cp chip enable low to chip enable high 45 50 50 ns t dveh t ds input valid to chip enable high 45 50 50 ns t ehdx t dh chip enable high to input transition 0 0 0 ns t ehwh t wh chip enable high to write enable high 0 0 0 ns t ehel t cph chip enable high to chip enable low 20 20 20 ns t avel t as address valid to chip enable low 0 0 0 ns t elax t ah chip enable low to address transition 45 50 50 ns t ghel output enable high to chip enable low 0 0 0 ns t vchwl t vcs v cc high to write enable low 50 50 50 ns t ehqv1 (1) chip enable high to output valid (program) 10 10 10 s t ehqv2 (1) chip enable high to output valid (erase) 1.5 30 1.5 30 1.5 30 sec t ehgl t oeh chip enable high to output enable low 0 0 0 ns note 1 : time is measured to data polling or toggle bit, t ehqv = t ehq7v + t q7vqv sector erase (se) instruction. this instruction uses a minimum of six write cycles. the erase setup command 80h is written on third cycle to address 5555h after the two coded cycles. the sector erase confirm command 30h is written on sixth cycle after another two coded cycles. during the input of the second command an address within the sector to be erased is given and latched into the me mory. additional sector erase confirm commands and sector addresses can be written subsequently to erase other sectors in parallel wi thout further coded cycles. the erase will start after an erase timeout period of about 100us. thus, additional sector erase commands must be given within this delay. the input of a new sector erase command will restart the timeout period. the status of the internal ti mer can be monitored through the level of dq3, if dq3 is '0' the sector erase command has been given and the timeout is running, if dq3 is '1', the timeout has expired and the p/e.c is erasing the sector(s). if the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to read array. it is not necessary to program the sector with 00h as the p/e.c. will do this automatically before to erasing to 0f fh. read operations after the sixth rising edge of w or e output the status register status bits. during the execution of the erase by the p/e.c., the memory accepts only the es (erase suspend) and rd (read/reset) instruction s. data polling bit dq7 returns '0' while the erasure is in progress and '1' when it has completed. the toggle bit dq6 toggles dur ing erase operation. it stops when erase is completed. after completion the status register bit dq5 returns '1' if there has been an eras e failure because erasure has not been completed even after the maximum number of erase cycles have been executed. in this case, it will be necessary to input a read/reset (rd) instruction to the command interface in order to reset the p/e.c. program (pg) instruction. this instruction uses four write cycles. the program command a0h is written to address 555h on third cycle after two coded cycles. a fourth write operation latches the address on the falling edge of w or e and the data to be written on its rising edge and starts the p/e.c. read operations output the status bits after the programming has started. memory programming is made only by writing '0' in place of '1' in a byte. erase suspend (es) instruction. the sector erase operation may be suspended by this instruction which consists of writing the com- mand 0b0h without any specific address code. no coded cycles are required. it allows reading of data from another sector while erase is in progress. erase suspend is accepted only during the sector erase instruction execution. writing this command during erase timeout will, in addition to suspending the erase, terminate the timeout. the toggle bit dq6 stops toggling when the p/e.c. is suspended. toggle bit status must be monitored at an address out of the sector being erased. toggle bit will stop toggling betwen 0.1 s and 15 s after the erase suspend (es) command has been written. the m29f040 will then automatically set to read memory array mode. when erase is suspended, read from sectors being erased will output invalid data, read from sector not being erased is valid. during the suspension the memory will respond only to erase resume (er) instruction. rd com- mand will definitively abort erasure and result in the invalid data on the sectors being erased. erase resume (er) instruction. if an erase suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any coded cycle.
m29f040 14/24 table 16 : data polling and toggle bit ac characteristics (1) (t c = 55 c ; v cc = 5 v 10 %) symbol alt parameter 90 120 150 unit s ym b o l alt p arame t er min max min max min max u n it t whq7v1 (2) write enable high to dq7 valid (program w control) 10 10 10 s t whq7v2 (2) write enable high to dq7 valid (erase w controller) 1.5 30 1.5 30 1.5 30 sec t ehq7v1 (2) chip enable high to dq7 valid (program e controller) 10 10 10 s t ehq7v2 (2) chip enable high to dq7 valid (erase e controlled) 1.5 30 1.5 30 1.5 30 sec t q7vqv q7 valid to output valid (data polling) 35 50 55 ns t whqv1 write enable high to output valid (program) 10 10 10 s t whqv2 write enable high to output valid (erase) 1.5 30 1.5 30 1.5 30 sec t ehqv1 chip enable high to output valid (program) 10 10 10 s t ehqv2 chip enable high to output valid (erase) 1.5 30 1.5 30 1.5 30 sec notes : 1. all other timings are defined in read ac characteristics table. 2. t whq7v is the program or erase time. programming. the memory can be programmed byte-by-byte. the program sequence is started by two coded cycles, followed by writ- ing the program command (0a0h) to the command interface. this is followed by writing the address and data byte to the memory. t he program/erase controller automatically starts and performs the programming after the fourth write operation. during programming the memory status is checked by reading the status bits dq3, dq5, dq6 and dq7 which shows the status of the p/e.c. dq6 and dq7 dete r- mine if programming is on going or has completed and dq5 allows a check to be made for any possible error. recommended conditions of use power up the memory command interface is reset on power up to read array. either e or w should be tied to v ih to allow maximum security and the possibility to write a command on the first rising edge of e or w . any write cycle initiation is blocked when v cc is below v lko . supply rails normal precautions must be taken for supply voltage decoupling, each device in a system should have the v cc rail decoupled with a 0.1 m f capacitor close to the v cc and vss pins. the pcb trace widths should be sufficient to carry the v cc program and erase currents required.
m29f040 15/24 figure 11 : data polling flowchart figure 12 : data polling dq7 ac waveforms notes : . 1. all other timings are as a normal read cycle. 2. dq7 and dq0dq6 can transmit to valid at any point during the data output valid period. 3. t whq7v is the program or erase time. 4. during erasing operation byte address must be within sector being erased.
m29f040 16/24 figure 13 : data toggle flowchart figure 14 : data toggling dq6 ac waveforms notes : . 1. all other timings are as a normal read cycle. 2. dq7 and dq0dq6 can transmit to valid at any point during the data output valid period. 3. t whq7v is the program or erase time. 4. during erasing operation byte address must be within sector being erased.
m29f040 17/24 table 17 : program, erase times and program, erase endurance cycles (t c = 55 c ; v cc = 5 v 10 %) parameter m29f040 unit min typ max chip program (byte) 6 sec chip erase (preprogrammed) 2.5 30 sec chip erase 8.5 1200 sec block erase 1.5 30 sec byte program 10 1500 s program/erase cycles 10,000 (tbc) cycles figure 15 : sector protection flowchart start sector address on a16, a17, a18 n = 0 g , a9 = v id , e = v il wait 4 s w = v il wait 100 s w = v ih g = v ih read dq0 at protection address : a0, a6 = v il , a1 = v ih and a16, a17, a18 defining sector dq0 = 1 a9 = v ih pass yes ++n = 25 a9 = v ih fail yes no no
m29f040 18/24 figure 16 : sector unprotecting flowchart start protect all sectors n = 0 a6, a12, a16 = v ih e, g , a9 = v ih wait 4 s e , g , a9 = v id wait 4 s w = v il w = v ih read at unprotection address : a0, a6 = v ih , a1 = v il and a16, a17, a18 defining sector data = 00h pass last sector fail wait 10 s e , g = v ih wait 4 s ++n = 1000 yes yes no increment sector yes no no
m29f040 19/24 outline dimensions pdip32 32 pin plastic dip, 600 mils width symb mm inches typ min max typ min max a 4.83 0.190 a1 0.38 0.015 a2 b 0.41 0.51 0.016 0.020 b1 1.14 1.40 0.045 0.055 c 0.20 0.30 0.008 0.012 d 41.78 42.04 1.645 1.655 e 15.24 15.88 0.600 0.625 e1 13.46 13.97 0.530 0.550 e1 2.54 0.100 ea 15.24 0.600 l 3.18 3.43 0.125 0.135 s 1.78 2.03 0.070 0.080 0 15 0 15 n 32 32 drawing is out of scale
m29f040 20/24 plcc32 32 lead plastic leaded chip carrier, rectangular symb mm inches typ min max typ min max a 2.54 3.56 0.100 0.140 a1 1.52 2.41 0.060 0.095 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 12.32 12.57 0.485 0.495 d1 11.35 11.56 0.447 0.455 d2 9.91 10.92 0.390 0.430 e 14.86 15.11 0.585 0.595 e1 13.89 14.10 0.547 0.555 e2 12.45 13.46 0.490 0.530 e 1.27 0.050 n 32 32 nd 7 7 ne 9 9 cp 0.10 0.004 drawing is out of scale
m29f040 21/24 tsop32 32 lead plastic thin small outline, 8 x 20mm symb mm inches typ min max typ min max a 1.20 0.047 a1 0.05 0.17 0.002 0.006 a2 0.95 1.50 0.037 0.059 b 0.15 0.27 0.006 0.011 c 0.10 0.21 0.004 0.008 d 19.80 20.20 0.780 0.795 d1 18.30 18.50 0.720 0.728 e 7.90 8.10 0.311 0.319 e 0.50 0.020 l 0.50 0.70 0.020 0.028 0 c 5 c 0 c 5 c n 32 32 cp 0.10 0.004 drawing is out of scale
drawing is out of scale m29f040 22/24 dil 32 32 pin ceramic dil, 600 mils width 1.616 (41.05) 1.584 (40.23) .175 (4.45) .125 (3.17) .050 (127) typ .070 (1.78) .030 (1.76) 1.05 (2.67) 0.95 (2.41) .020 (.508) .016 (.406) .012 (.305) .009 (.228) .610 (15.5) .590 (15.0) at standoff drawing is out of scale lccc 32 32 pin leadless ceramic chip carrier (rectangular) symb mm min max a1 11.23 11.63 a2 13.72 14.22 b1 11.63 b2 14.17 c2 1.78 2.92
m29f040 23/24 cdfp 32 - 32 pin ceramic dual flat pack (bottom brazed) drawing is out of scale cdfp 32 - 32 pin ceramic dual flat pack (bottom brazed) with tie bar 0.195* 0.250* (*) to be confirmed drawing is out of scale
m29f040 24/24 ordering information example : vcc range m29f040 90 e b/c f : 5 v speed 90 : 90ns 120 : 120ns 150 : 150ns package p : pdip32 fn : plcc32 n : tsop32 nr : tsop32 reverse c : dil32 e : lccc32 z : cdfp32 zt : cdfp32 tie bar screening level v : internal standard tc = 40, +85 c m : internal standard tc = 55; +125 c b/c : mil-std-883 ; tc = 55, +125 c b/t: according to mil-std-883 for availability of different packages, please contact your nearest thomsoncsf semiconductors specifiques sales office . information furnished is believed to be accurate and reliable. however thomson-csf semiconducteurs specifiques assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights o f third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of t homson- csf semiconducteurs specifiques. specifications mentioned in this publication are subject to change without notice. this pub- lication supersedes and replaces all information previously supplied. thomson-csf semiconducteurs specifiques products are not authorized for use as critical components in life support devices or systems without express written approval from thom son- csf semiconducteurs specifiques. ? 1996 thomson-csf semiconducteurs specifiques - printed in france - all rights reserved. this product is manufactured and commercialized by thomson-csf semiconducteurs specifiques - po box 123 - 38521 saint-egreve cedex - france. for further information please contact : thomson-csf semiconducteurs specifiques - route dpartementale 128 - po box 46 - 91401 orsay cedex - france - phone +33 01 69 33 00 00 - fax +33 01 69 33 03 21 internet: http://www.tcs.thomsoncsf.com

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