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preliminary: the specifications of this device are subject to change without notice. please contact your nearest hitachi?s sales dept. regarding specifications. hm66wp18101/hm66wp36513 18m flow through zero bus latency (zbl) sram (hm66wp18101) 1-mword 18-bit (hm66wp36513) 512-kword 36-bit ade-203-1299d (z) preliminary rev. 0.4 jun. 21, 2002 description the hm66wp18101 is a synchronous fast static ram organized as 1-mword 18-bit. the hm66wp36513 is a synchronous fast static ram organized as 512-kword 36-bit. it has realized high speed access time by employing the most advanced cmos process and high speed circuit designing technology. it is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. it is packaged in standard 100- pin lqfp and 119-pin bga. note: all power supply(v dd ,v ddq ) and ground(v ss ) pins must be connected for proper operation of the device. zbl: zero bus latency and compatible zbt tm sram. zbt tm is trademark of integrated device technology, inc., features ? 3.3 v or 2.5v power supply, 3.3 v or 2.5 v i/o supply voltage ? clock frequency: 133/100 mhz ? fast clock access time: 6.5/8.5 ns (max) ? low operating current: 250/200 ma (max) ? address data pipeline capability ? internal input registers (address, data, control) ? internal self-timed write cycle ? adv/ ld burst control pins ? asynchronous output enable controlled three-state outputs ? individual byte write control ? power down state via zz ? common data inputs and data outputs ? high board density 100-pin lqfp package and 119-pin bga package ? burst control selected pin lbo (interleave or linear burst order)
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 2 of 31 ordering information type no. access time cpu clock rate package hm66wp18101fp-65 hm66wp18101fp-85 6.5 ns 8.5 ns 133 mhz 100 mhz lqfp 100-pin (fp-100h) hm66wp36513fp-65 hm66wp36513fp-85 6.5 ns 8.5 ns 133 mhz 100 mhz hm66wp18101bp-65 hm66wp18101bp-85 6.5 ns 8.5 ns 133 mhz 100 mhz bga 119-pin (bp-119a) hm66wp36513bp-65 HM66WP36513BP-85 6.5 ns 8.5 ns 133 mhz 100 mhz
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 3 of 31 pin arrangement (hm66wp36513) 100pin-lqfp a6 a7 ce2 v v clk adv/ a18 a17 a8 a9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 dd ss a5 a4 a3 a2 a1 a0 nc nc nc nc a10 a11 a12 a13 a14 a15 a16 ss dd 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dqb0 dqb1 dqb2 v v dqb3 dqb4 dqb5 dqb6 v v dqb7 dqb8 v v v zz dqa8 dqa7 v v dqa6 dqa5 dqa4 dqa3 v v dqa2 dqa1 dqa0 ssq ddq ddq ssq ssq ddq ddq ssq ss ss (1) dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 dqc0 dqc1 dqc2 dqc3 dqc4 dqc5 dqc6 dqc7 dqc8 ss (1) dd dqd8 dqd7 dqd6 dqd5 dqd4 dqd3 dqd2 dqd1 dqd0 100-pin lqfp (top view) ddq ssq ssq ddq dd ss ddq ssq ssq ddq v v v v v v v v v v v v v v note: pins 14 and 66 are not v ss supply ,but have to be connected v ss .
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 4 of 31 pin arrangement (hm66wp18101) 100pin-lqfp a6 a7 ce2 nc nc v v clk adv/ a19 a18 a8 a9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 dd ss 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a10 nc nc v v nc dqa8 dqa7 dqa6 v v dqa5 dqa4 v v v zz dqa3 dqa2 v v dqa1 dqa0 nc nc v v nc nc nc ssq ddq ddq ssq ssq ddq ddq ssq ss ss (1) dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 nc nc nc nc nc dqb8 dqb7 dqb6 dqb5 dqb4 dqb3 dqb2 dqb1 dqb0 nc nc nc nc ddq ssq ssq ddq ss (1) dd dd ss ddq ssq ssq ddq 100-pin lqfp (top view) v v v v v v v v v v v v a5 a4 a3 a2 a1 a0 nc nc nc nc a11 a12 a13 a14 a15 a16 a17 ss dd v v note: pins 14 and 66 are not v ss supply ,but have to be connected v ss .
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 5 of 31 pin arrangement (hm66wp36513) 119pin-bga 1234567 av ddq a6 a4 a18 a8 a16 v ddq b nc ce2 a3 adv/ ld a9 ce3 nc cnca7a2v dd a12 a15 nc d dqc1 dqc0 v ss nc v ss dqb0 dqb1 e dqc3 dqc2 v ss ce1 v ss dqb2 dqb3 fv ddq dqc4 v ss oe v ss dqb4 v ddq g dqc6 dqc5 bwc a17 bwb dqb5 dqb6 h dqc8 dqc7 v ss we v ss dqb7 dqb8 jv ddq v dd nc v dd nc v dd v ddq k dqd8 dqd7 v ss clk v ss dqa7 dqa8 l dqd6 dqd5 bwd nc bwa dqa5 dqa6 mv ddq dqd4 v ss cen v ss dqa4 v ddq n dqd3 dqd2 v ss a1 v ss dqa2 dqa3 p dqd1 dqd0 v ss a0 v ss dqa0 dqa1 rnca5 lbo v dd nc a13 nc t nc nc a10 a11 a14 nc zz uv ddq tms tdi tck tdo nc v ddq (top view) pin arrangement (hm66wp18101) 119pin-bga 1234567 av ddq a6 a4 a19 a8 a16 v ddq b nc ce2 a3 adv/ ld a9 ce3 nc cnca7a2v dd a13 a17 nc ddqb8nc v ss nc v ss dqa8 nc encdqb7v ss ce1 v ss nc dqa7 fv ddq nc v ss oe v ss dqa6 v ddq gncdqb6 bwb a18 v ss (1) nc dqa5 hdqb5nc v ss we v ss dqa4 nc jv ddq v dd nc v dd nc v dd v ddq kncdqb4v ss clk v ss nc dqa3 ldqb3ncv ss (1) nc bwa dqa2 nc mv ddq dqb2 v ss cen v ss nc v ddq ndqb1nc v ss a1 v ss dqa1 nc pncdqb0v ss a0 v ss nc dqa0 rnca5 lbo v dd nc a12 nc t nca10a15nca14a11 zz uv ddq tms tdi tck tdo nc v ddq (top view) note: pin 3l and 5g are not v ss supply, but have to be connected v ss or have to be nc.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 6 of 31 pin description (see detailed pin description) name i/o type description notes a0, a1 and a2-18 (hm66wp36513) input 19 address inputs a0 ,a1 and a2-19 (hm66wp18101) input 20 address inputs bwm input byte write enables bwa controls dqa0 to dqa8 bwb controls dqb0 to dqb8 bwc controls dqc0 to dqc8 bwd controls dqd0 to dqd8 m = a, b, c, d (hm66wp36513) m = a, b (hm66wp18101) we input write enable clk input clock ce1 , ce3 , ce2 input chip enable oe input output enable adv/ ld input address load control cen input clock enable control zz input power down lbo input burst mode control nc ? no connection dqmn n = 0 ? 8 input/ output data input/output m = a, b, c, d (hm66wp36513) m = a, b (hm66wp18101) v dd supply power supply v ddq supply i/o power supply v ss supply ground
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 7 of 31 detailed pin description pin number(s) lqfp bga symbol type description 35, 34, 33, 32, 44, 45, 46, 47, 48,49,50,81,82 ,84,83, 99, 100 37, 36 2a, 2c, 2r, 3a, 3b, 3c, 3t, 4g, 5a, 5b, 5c, 5t, 6a, 6c, 6r, 4a 4p, 4n a ( 36-bit 18-bit common) a0,a1 input synchronous address inputs: these inputs are registered and must meet setup and hold times around the rising edge of clk burst address inputs 80 2t, 6t 4t a ( 18-bit) a ( 36-bit) 93, 94, 95, 96 5l, 5g, 3g, 3l bwa , bwb bwc , bwd ( 36-bit) input synchronous byte write enables: these active low inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of clk. a byte write enable is low for a write cycle and high for a read cycle. bwa controls dqa0 to dqa8. bwb controls dqb0 to dqb8. bwc controls dqc0 to dqc8. bwd controls dqd0 to dqd8. data i/o are tri-stated if any of these four inputs are low. 93, 94 5l, 3g bwa , bwb ( 18-bit) 87 4m cen input synchronous clock enable: this active low internal clock signal is active. 88 4h we input synchronous write enable: this active low input permits write operations and must meet the setup and hold times around the rising edge of clk. 89 4k clk input clock: this signal latches the address, data, chip enables, byte write enables and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock's rising edge. 98 4e ce1 input synchronous chip enable: this active low input is used to enable the device. this input is sampled only when an external address is loaded. this input can be used for memory depth expansion. 92 6b ce3 input 97 2b ce2 input synchronous chip enable: this active high input is used to enable the device. this input sampled only when a new external address is load. this input can be used for memory depth expansion. 86 4f oe input output enable: this active low asynchronous input enables the data i/o output drivers. 85 4b adv/ ld input synchronous address advance or load control: this active high input is used to advance the internal burst counter, controlling burst access after the external address is loaded. a low input is caused a new external address to be latched.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 8 of 31 detailed pin description (cont) pin number(s) lqfp bga symbol type description 38, 39, 42, 43 1b, 1c, 1r, 1t, 3j, 4d, 4l,5j,5r,6t,6u,7b,7c,7r nc ( 36-bit) ? no connect: these signals are internally not connected. 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 75, 78, 79, 95, 96 1b, 1c, 1e, 1g, 1k, 1p, 1r, 1t,2d,2f,2h,2l,2n,4l, 4t,5j,5r,6e,6g,6k,6m,6p, 6u,7b,7c,7d,7h,7l,7n,7r nc ( 18-bit) ? no connect: these signals are internally not connected. 51, 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 80, 1, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29, 30 6k, 6l, 6m, 6n, 6p, 7k, 7l, 7n, 7p, 6d, 6e, 6f, 6g, 6h, 7d, 7e, 7g, 7h, 1d, 1e, 1g, 1h, 2d, 2e 2f, 2g, 2h, 1k, 1l, 1n 1p,2k , 2l, 2m, 2n, 2p dqmn m = a, b, c, d n = 0 ? 8 ( 36-bit) input/ output sram data i/o: byte a is dqa0 to dqa8; byte b is dqb0 to dqb8; byte c is dqc0 to dqc8; byte d is dqd0 to dqd8. input data must meet setup and hold times around the rising edge of clk. 58, 59, 62, 63, 68, 69, 72, 73, 74, 8, 9, 12, 13, 18, 19, 22, 23, 24 6d, 6f, 6h, 6l, 6n, 7e, 7g, 7k, 7p, 1d, 1h, 1l, 1n, 1e, 1g, 1k, 1m, 1p dqmn m = a, b n = 0 ? 8 ( 18-bit) input/ output sram data i/o: byte a is dqa0 to dqa8; byte b is dqb0 to dqb8. input data must meet setup and hold times around the rising edge of clk. 15, 16, 41, 65, 91 2j, 4c, 4j, 4r, 6j, v dd supply power supply: 3.3 v (+5%/?5%) or 2.5 v (+5%/?5%) 4, 11, 20, 27, 54 61, 70, 77 1a, 1f, 1j, 1m, 1u, 7a, 7f, 7j, 7m, 7u v ddq supply i/o power supply: 3.3 v (+5%/?5%) or 2.5 v (+5%/?5%) 14, 17, 40, 66, 67, 90, 5, 10, 21, 26, 55, 60, 71, 76 3d,3e,3f,3h,3k,3m,3n,3p, 5d,5e,5f,5h,5k,5m,5n,5p v ss supply ground: gnd 3l, 5g v ss ( 18-bit) supply ground: gnd 64 7t zz input asynchronous power-down (snooze): this active high input enables sram to enter a power-down (snooze) state with data retention. during snooze state, data retention is guaranteed. at this time, internal state of the sram is not preserved. after snooze state, sram must be initiated with cen or adv/ ld using a new external address. this pin must be connected to v ss in systems that do not use zz feature. 31 3r lbo input burst order (interleave burst or linear burst) select pin (dc) this pin must connect v dd or v ddq or v ss .
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 9 of 31 block diagram (hm66wp36513) byte c write driver 1 st byte a write register input registers 1 st byte b write register 1 st byte c write register 1 st byte d write register enable register byte a write driver byte b write driver byte d write driver 2 nd byte a write register 2 nd byte b write register 2 nd byte c write register 2 nd byte d write register 512k 9 4 memory array ce2 dqa0 to dqa8 dqb0 to dqb8 dqc0 to dqc8 dqd0 to dqd8 19 36 36 36 9 19 19 9 9 9 note: the functional block diagram illustrates simplified device operation. see truth table, detailed pin descriptions and timing diagrams for detailed information. 1st address registers clk adv/ a0 to a18 17 19 19 binary counter clr a0 a0' a1 a1' write enable register 2nd address registers mux
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 10 of 31 block diagram (hm66wp18101) byte b write driver input registers enable register byte a write driver 1m 9 2 memory array ce2 dqa0 to dqa8 dqb0 to dqb8 18 18 18 9 9 note: the functional block diagram illustrates simplified device operation. see truth table, detailed pin descriptions and timin g dia g rams for detailed information. 1 st address registers clk adv/ a0 to a19 18 20 20 20 20 binary counter clr a0 a1 write enable register 1 st byte a write register 1 st byte b write register 2 nd byte a write register 2 nd byte b write register 20 a0' a1' 2nd address registers mux
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 11 of 31 synchronous truth table operation address ce1 ce1 ce1 ce1 ce3 ce3 ce3 ce3 ce2 adv / ld ld ld ld cen cen cen cen w w w we e e eb b b bw w w wm m m moe oe oe oe clk dq deselected cycle, power-down none h ll l-h high-z deselected cycle, power-down none h ll l-h high-z deselected cycle, power-down none lll l-h high-z write cycle, begin burst external l l h l l l l l-h d nop/write abort, begin burst external l l h l l l h l-h high-z read cycle, begin burst external l l h l l h ll-hq dummy read cycle, begin burst external l l h l l h h l-h high-z write cycle, continue burst next hl l l-h d write abort, continue burst next hl h l-h high-z read cycle, continue burst next hl ll-hq dummy read cycle, continue burst next hl h l-h high-z write cycle, suspend current h l-h - read cycle, suspend current h ll-hq dummy read cycle, suspend current h h l-h high-z notes: 1. h means logic high, l means logic low. means h or l. we = l means any one or more byte write enable signals ( bwa , bwb , bwc or bwd ) are low. we = h means all byte write enable signals are high. 2. bwa enables write to bytea (dqa0 to dqa8). bwb enables write to byteb (dqb0 to dqb8). bwc enables write to bytec (dqc0 to dqc8). bwd enables write to byted (dqd0 to dqd8). 3. all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 4. a write is performed by setting one or more byte write enable signals and we low for the subsequent l-h edge of clk. refer to write timing diagram for clarification. 5. the status for dq described in this synchronous truth table appears one clock after the cycle in which the read or write command is asserted. 6. if adv/ ld is sampled high that it is continue burst cycle follows before the operation cycle. 7. wait states are inserted by cen = high. when cen is sampled high after read cycle, the read data is maintain as output data. when cen is sampled high after write cycle, the write input data is ignored and is maintained high-z. refer to timing diagram for clarification.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 12 of 31 asynchronous truth table operation zz oe oe oe oe i/o status read l l data out read l h high-z write l high-z, data in deselect l high-z power down (snooze) h high-z note: h means logic high. l means logic low. means h or l. partial truth table for writes operation we we we we bwa bwa bwa bwa bwb bwb bwb bwb bwc bwc bwc bwc bwd bwd bwd bwd read h no write l h h h h write byte a l l h h h write all bytes l l l l l note: h means logic high. l means logic low. means h or l.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 13 of 31 interleave sequence table ( lbo = v dd or v ddq ) parameter sequence 1 (a1, a0) sequence 2 (a1, a0) sequence 3 (a1, a0) sequence 4 (a1, a0) external address 0 0 0 1 1 0 1 1 1st internal address 0 1 0 0 1 1 1 0 2nd internal address 1 0 1 1 0 0 0 1 3rd internal address 1 1 1 0 0 1 0 0 note: each sequence wraps around to its initial state upon completion. linear sequence table ( lbo = v ss ) parameter sequence 1 (a1, a0) sequence 2 (a1, a0) sequence 3 (a1, a0) sequence 4 (a1, a0) external address 0 0 0 1 1 0 1 1 1st internal address 0 1 1 0 1 1 0 0 2nd internal address 1 0 1 1 0 0 0 1 3rd internal address 1 1 0 0 0 1 1 0 note: each sequence wraps around to its initial state upon completion. absolute maximum ratings parameter symbol value unit supply voltage v dd ?0.5 to +4.6 v voltage on any pins relative to v ss (dq) v t ?0.5 to v ddq + 0.5 v except v dd (others) v t ?0.5 to v dd + 0.5 v power dissipation p t 1.6 w operating temperature topr 0 to +70 c storage temperature range (with bias) tstg (bias) ?10 to +85 c storage temperature range tstg ?55 to +125 c
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 14 of 31 recommended dc operating conditions (3.3v power supply) (ta = 0 to +70c) parameter symbol min typ max unit note supply voltage (operating voltage range) v dd 3.135 3.3 3.465 v supply i/o voltage (3.3 v i/o) v ddq 3.135 3.3 3.465 v supply i/o voltage (2.5 v i/o) v ddq 2.375 2.5 2.625 v supply voltage to v ss v ss 0.0 0.0 0.0 v input high voltage (3.3 v i/o) (dq) v ih 2.0 ? v ddq + 0.3 v (others) v ih 2.0 ? v dd + 0.3 v input high voltage (2.5 v i/o) (dq) v ih 1.7 ? v ddq + 0.3 v (others) v ih 1.7 ? v dd + 0.3 v input low voltage (3.3 v i/o) v il ?0.3 ? 0.8 v 1 input low voltage (2.5 v i/o) v il ?0.3 ? 0.7 v 1 note: 1. ?2.0 v for undershoot pulse width 20% t cyc . recommended dc operating conditions (2.5v power supply) (ta = 0 to +70c) parameter symbol min typ max unit note supply voltage (operating voltage range) v dd 2.375 2.5 2.625 v supply i/o voltage (2.5 v i/o) v ddq 2.375 2.5 2.625 v supply voltage to v ss v ss 0.0 0.0 0.0 v input high voltage (2.5 v i/o) (dq) v ih 1.7 - v ddq + 0.3 v (others) v ih 1.7 - v dd + 0.3 v input low voltage (2.5 v i/o) v il ?0.3 - 0.7 v 1 note: 1. ?2.0 v for undershoot pulse width 20% t cyc .
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 15 of 31 dc characteristics (ta = 0 to +70c, v dd = 3.3 v +5%/?5% or 2.5 v +5%/?5% ) hm66wp18101/hm66wp36513 -65 -85 parameter symbol min max min max unit test conditions input leakage current i li ?2 2 ?2 2 a all inputs vin = v ss to v dd output leakage current i lo ?5 5 ?5 5 a oe = v ih , vout = v ss to v ddq operating current i dd ? 250 ? 200 ma device selected, iout = 0 ma, all inputs = v ih or v il , cycle time = t cyc min. standby current i sb ? 80 ? 60 ma device deselected all inputs = fixed and all inputs v dd ? 0.2 v or 0.2 v, cycle time = t cyc min. i sb1 ? 30 ? 30 ma device deselected all inputs = fixed and all inputs v dd ? 0.2 v or 0.2 v, frequency = 0 mhz. i sbzz ? 10 ? 10 ma device deselected all inputs = fixed and all inputs v dd ? 0.2 v or 0.2 v, zz v dd ? 0.2 v, frequency = 0 mhz. output low voltage (3.3 v i/o) v ol ? 0.4 ? 0.4 v i ol = 8 ma output high voltage (3.3 v i/o) v oh 2.4 ? 2.4 ? v i oh = ?4 ma output low voltage (2.5 v i/o) v ol ? 0.4 ? 0.4 v i ol = 1 ma output high voltage (2.5 v i/o) v oh 2.0 ? 2.0 ? v i oh = ?1 ma note: 1. lbo pin has an internal pull-up, zz pin has an internal pull-down, and input leakage current < |5 a|.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 16 of 31 capacitance (ta = +25c, f = 1.0 mhz, v dd = 3.3 v and 2.5 v) parameter symbol min typ max unit note input capacitance cin ? 4 5 pf 1 input/output capacitance c i/o ?6 7 pf1 note: 1. this parameter is sampled and not 100% tested.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 17 of 31 ac characteristics (ta = 0 to +70c, v dd = 3.3 v +5%/?5% and 2.5 v +5%/?5%, v ss = 0 v) test conditions ? input timing measurement reference level: 1.4 v (3.3 v i/o) 1.2 v (2.5 v i/o) ? input pulse levels: 0 v to 2.8 v (3.3 v i/o) 0 v to 2.4 v (2.5 v i/o) ? input rise and fall time: 2 v/ns (10% ? 90%) ? output timing reference level: 1.4 v (3.3 v i/o) 1.2 v (2.5 v i/o) ? output load: see figure 50 ? 16.7 ? 16.7 ? 50 ? 5 pf* dq 50 ? 16.7 ? 50 ? 5 pf* v l v *(including scope and jig) = 1.4 v (3.3 v i/o) or 1.2 v (2.5 v i/o) l v l v l
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 18 of 31 hm66wp18101/hm66wp36513 symbol -65 -85 parameter standard alternate min max min max unit notes cycle time t khkh t cyc 7.5 ? 10.0 ? ns clock access time t khqv t ack ?6.5?8.5ns output enable to output valid t glqv t oe ?3.5?4.0ns clock high to output active t khqx2 t clz 2.5 ? 2.5 ? ns 1 clock high to output change t khqx t coh 2.5 ? 2.5 ns output enable to output active t glqx t olz 0?0?ns1 output disable to q high-z t ghqz t ohz ?3.5?4.0ns 1 clock high to q high-z t khqz t chz ?3.8?5.0ns 1 clock high pulse width t khkl t ch 2.5 ? 3.0 ? ns clock low pulse width t klkh t cl 2.5 ? 3.0 ? ns setup times: address clock enable input data write ( we , bwa-d ) address advance chip enable t avkh t cenvkh t dvkh t wvkh t advvk t evkh t sa t scen t sd t sw t sadv t sce 1.5 ? 1.5 ? ns hold times: address clock enable input data write ( we , bwa-d ) address advance chip enable t khax t khcenx t khdx t khwx t khadvx t khex t ha t hcen t hd t hw t hadv t hce 0.5 ? 0.5 ? ns zz active to input ignored t pds 2?2?cycle4 zz inactive to input sampled t pus 2?2?cycle4 zz active to sleep current t zzi ?2 ?2 cycle4 zz inactive to exit sleep current t rzzi 0?0?cycle4 notes: 1. transition is measured 100 mv from steady-state voltage. this parameter is sampled. 2. a read cycle is defined by we high for the required setup and hold times. a write cycle is defined by we low for the required setup and hold times. 3. this is a synchronous device. all address must meet the specified setup and hold times for all rising edges of clk when chip enabled. all other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (clk) when chip is enabled. chip enable must be valid at each rising edge of clk to remain enabled. 4. data-output is not guaranteed during the cycle when transition of zz from low to high occurs.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 19 of 31 timing waveforms read cycle clk adv/ q t cyc ch t tt cl t address a1 a3 a2 ha sa burst continues with new base address t t sw hw * 2 t t sce hce deselect cycle * 3 t clz t oe t t ohz t olz t t ack q (a1) q (a2) q (a2+1) q (a2+2) * 1 q (a2+3) q (a2+1) q (a2) q (a3) single read burst wraps around to its initial state. burst read h or l undefined ack coh notes: 1. q (a2) refers to output from address a2. q (a2 + 1) refers to output from next internal burst address following a2. 2. and ce2 have timing identical to . on this diagram, when is low, is low and ce2 is high. when is high, is high and ce2 is low. 3. outputs are disabled within one clock cycle after deselect. 4. zz is low.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 20 of 31 write cycle clk adv/ t cyc t cl t ch t address a1 a2 ha t sa t t sw hw * 1 t t sce hce d d (a1) d (a2) d (a2+1) d (a2+2) d (a3) d (a2) d (a3+1) d (a2+3) t t sd hd q t ohz single write burst write burst write h or l undefined notes: 1. and ce2 have timing identical to . on this diagram, when is low, is low and ce2 is high. when is high, is high and ce2 is low. 2. must be high before the input data setup and held high throughout the data hold time. this prevents input/output data contention for the time period prior to the byte write enable inputs being sampled. 3. full width write can be initiated by , to are low. 4. zz is low. a3 * 2
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 21 of 31 read-write cycle ch cl clk adv/ q t cyc t t address a1 a3 a4 a2 t ha t sa * 2 t t sce hce t clz t clz t chz t ack t ack t chz q (a1) q (a3 ) single read single write single read h or l undefined t t sw hw d (a2) d (a4+2) d (a4+2) d (a4) d (a4+3) d high-z high-z t t sd hd burst write notes: 1. q (a3) refers to output from address a3. 2. and ce2 have timing identical to . on this diagram, when is low, is low and ce2 is high. when is high, is high and ce2 is low. 3. timing is shown assuming that the device was not enabled before entering into this sequence. does not cause q to be driven until after the following clock rising edge. 4. zz is low. * 3 * 3 high-z
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 22 of 31 power-down state zz clk outputs(q) power-down state with data retention all inputs (except zz) i supply i isb2z t rzzi t pus t zzi t pds high-z deselect or read only deselect or read only don' t care notes: 1. the terms of t pds and t pus have to be that is low. 2. data-output is not guaranteed during the cycle when transition of zz from low to high occurs.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 23 of 31 boundary scan test access port operations (only bga) overview in order to perform the interconnect testing of the modules that include this sram, the serial boundary scan test access port (tap) is designed to operate in a manner consistent with ieee standard 1149.1 - 1990. but does not implement all of the functions required for 1149.1 compliance the hm66wp series contains a tap controller. instruction register, boundary scans register, bypass register and id register. test access port pins symbol i/o name tck test clock tms test mode select tdi test data in tdo test data out notes: this device does not have a trst (tap reset) pin. trst is optional in ieee 1149.1. to disable the tap, tck must be connected to vss. tdo should be left unconnected. to test boundary scan, zz pin need to be kept below v il . tap dc operating characteristics (ta = 0c to 70c) parameter symbol min max notes boundary scan input high voltage (3.3v i/o) v ih 2.0 v v dd +0.3v boundary scan input high voltage (2.5v i/o) v ih 1.7 v v dd +0.3v boundary scan input low voltage (3.3v i/o) v il ?0.3 v 0.8 v boundary scan input low voltage (2.5v i/o) v il ?0.3 v 0.7 v boundary scan input leakage current i li ?5 a +5 a 1 boundary scan output leakage current i lo ?5 a +5 a 1 boundary scan output low voltage (3.3v/2.5v) v ol ? 0.4 v/0.4 v 2 boundary scan output high voltage (3.3v/2.5v) v oh 2.4 v/2.0 v ? 3 notes: 1. 0 vin v dd for all logic input pin 2. i ol = ?8 ma at v dd = 3.3 v , i ol = ?1 ma at v dd = 2.5 v. 3. i oh = 4 ma at v dd = 3.3 v , i oh = 1 ma at v dd = 2.5 v.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 24 of 31 tap ac operating characteristics (ta = 0c to 70c) parameter symbol min max unit note test clock cycle time t thth 20 ? ns test clock high pulse width t thtl 8?ns test clock low pulse width t tlth 8?ns test mode select setup t mvth 5?ns test mode select hold t thmx 5?ns capture setup t cs 5?ns1 capture hold t ch 5?ns1 tdi valid to tck high t dvth 5?ns tck high to tdi don?t care t thdx 5?ns tck low to tdo unknown t tlqx 0?ns tck low to tdo valid t tlqv ?10ns note: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to assure pad data capture. tap ac test conditions (v dd = 3.3 v and 2.5v) v dd =3.3v v dd =2.5v ? temperature 0c ta 70c 0c ta 70c ? input timing measurement reference level 1.4 v 1.2 v ? input pulse levels 0 to 2.8 v 0 to 2.4 v ? input rise/fall time(10% to 90%) 2.0 ns typical 2.0 ns typical ? output timing measurement reference level 1.4 v 1.2 v ? test load termination supply voltage (v t ) 1.4 v 1.2 v ? output load see figures see figures dut boundary scan ac test load tdo z 0 =50 ? 50 ? v t
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 25 of 31 tap controller timing diagram tck tms tdi tdo ram address t thth t thtl t mvth t thmx t dvth t thdx t tlqv t tlqx t cs t ch t tlth tap controller timing diagram test access port registers register name length symbol note instruction register 3 bits ir [0;2] bypass register 1 bits bp id register 32 bits id [0;31] boundary scan register 70 bits bs [1;70] tap controller instruction set ir2 ir1 ir0 instruction operation 0 0 0 sample-z tristate all data drivers and capture the pad value 0 0 1 idcode 0 1 0 sample-z tristate all data drivers and capture the pad value 0 1 1 bypass 1 0 0 sample 1 0 1 bypass 1 1 0 bypass 1 1 1 bypass note: this device does not perform extest, intest or the preload portion of the preload command in ieee 1149.1.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 26 of 31 boundary scan order (hm66wp36513bp) bit # bump id signal name bit # bump id signal name 12r a5 366b ce3 2 3t a10 37 5l bwa 3 4t a11 38 5g bwb 4 5t a14 39 3g bwc 5 6r a13 40 3l bwd 63b a3 412b ce2 75b a9 424e ce1 86p dqa0 433a a4 97n dqa3 442a a6 10 6m dqa4 45 2d dqc0 11 7l dqa6 46 1e dqc3 12 6k dqa7 47 2f dqc4 13 7p dqa1 48 1g dqc6 14 6n dqa2 49 2h dqc7 15 6l dqa5 50 1d dqc1 16 7k dqa8 51 2e dqc2 17 7t zz 52 2g dqc5 18 6h dqb7 53 1h dqc8 19 7g dqb6 54 5r nc 20 6f dqb4 55 2k dqd7 21 7e dqb3 56 1l dqd6 22 6d dqb0 57 2m dqd4 23 7h dqb8 58 1n dqd3 24 6g dqb5 59 2p dqd0 25 6e dqb2 60 1k dqd8 26 7d dqb1 61 2l dqd5 27 6a a16 62 2n dqd2 28 5a a8 63 1p dqd1 29 4g a17 64 3r lbo 30 4a a18 65 2c a7 31 4b adv/ ld 66 3c a2 32 4f oe 67 5c a12 33 4m cen 68 6c a15 34 4h we 69 4n a1 35 4k clk 70 4p a0 notes: 1. bit#1 is the first scan bit to exit the chip. 2. the nc pads listed in this table are indeed no connects, but are represented in the boundary scan register by a ?place holder?. place holder registers are internally connected to v ss . 3. zz must remain at v il during boundary scan.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 27 of 31 boundary scan order (hm66wp18101bp) bit # bump id signal name bit # bump id signal name 12r a5 362e dqb7 2 2t a10 37 2g dqb6 3 3t a15 38 1h dqb5 4 5t a14 39 5r nc 5 6r a12 40 2k dqb4 63b a3 411l dqb3 75b a9 422m dqb2 8 7p dqa0 43 1n dqb1 9 6n dqa1 44 2p dqb0 10 6l dqa2 45 3r lbo 11 7k dqa3 46 2c a7 12 7t zz 47 3c a2 13 6h dqa4 48 5c a13 14 7g dqa5 49 6c a17 15 6f dqa6 50 4n a1 16 7e dqa7 51 4p a0 17 6d dqa8 18 6t a11 19 6a a16 20 5a a8 21 4g a18 22 4a a19 23 4b adv/ ld 24 4f oe 25 4m cen 26 4h we 27 4k clk 28 6b ce3 29 5l bwa 30 3g bwb 31 2b ce2 32 4e ce1 33 3a a4 34 2a a6 35 1d dqb8 notes: 1. bit#1 is the first scan bit to exit the chip. 2. the nc pads listed in this table are indeed no connects, but are represented in the boundary scan register by a ?place holder?. place holder registers are internally connected to v ss . 3. zz must remain at v il during boundary scan.
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 28 of 31 id register part revision number (31:28) device density and configuration (27:18) vendor definition (17:12) vendor jedec code (11:1) start bit (0) hm66wp36513 xxxx 0011100100 00000000111 1 hm66wp18101 xxxx 0100000011 00000000111 1 tap controller state diagram 1 111 0 0 00 00 0 0 0 1 11 11 0 1 11 1 10 10 0 0 0 0 1 test-logic- reset run-test/ idle select- dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir select- ir-scan notes: the value adjacent to each state transition in this figure represents the signal present at tms at the time of a rising edge at tck. no matter what the original state of the controller, it will enter test-logic-reset when tms is held high for at least five rising edges of tck
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 29 of 31 package dimensions hm66wp18101fp, hm66wp36513fp series (fp-100h) hitachi code jedec jeita mass (reference value) fp-100h conforms ? 0.95 g *dimension including the plating thickness base material dimension 0.10 m *0.32 0.08 *0.17 0.05 1.60 max 0.50 0.10 22.00 0.10 20.00 80 51 50 31 30 1 100 81 16.00 0.10 14.00 0.65 1.40 1.00 0.1 0.10 0.05 0.575 0.825 0.30 0.06 0.15 0.04 as of january, 2002 unit: mm 0? ? 10? preliminary
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 30 of 31 hm66wp18101bp, hm66wp36513bp series (bp-119a) hitachi code jedec jeita mass (reference value) bp-119a conforms ? 1.2 g a 0.20 4 14.00 1.27 1.27 0.15 c 22.00 c 0.35 c 0.30 119 0.75 0.15 cab m 0.15 c m 21.0 0.10 4 c1.2 pin 1 index a 1 2 3 4 5 6 7 b c d e f g h j k l m n p r t u y 13.0 0.10 0.60 0.10 2.10 0.25 details of the part y b as of january, 2002 unit: mm
hm66wp18101, hm66wp36513 rev.0.4, jun. 2002, page 31 of 31 disclaimer 1. hitachi neither warrants nor grants licenses of any rights of hitachi ? s or any third party ? s patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party ? s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi ? s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi ? s sales office for any questions regarding this document or hitachi semiconductor products. sales offices hitachi, ltd. semiconductor integrated circuits nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: (03) 3270-2111 fax: (03) 3270-5109 copyright hitachi, ltd., 2002. all rights reserved. printed in japan. hitachi asia ltd. hitachi tower 16 collyer quay #20-00 singapore 049318 tel : <65-6538-6533/6538-8577 fax : <65-6538-6933/6538-3877 url : http://semiconductor.hitachi.com.sg url http://www.hitachisemiconductor.com/ hitachi asia ltd. (taipei branch office) 4/f, no. 167, tun hwa north road hung-kuo building taipei (105), taiwan tel : <886-(2)-2718-3666 fax : <886-(2)-2718-8180 telex : 23222 has-tp url : http://www.hitachi.com.tw hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel : <852-2735-9218 fax : <852-2730-0281 url : http://semiconductor.hitachi.com.hk hitachi europe gmbh electronic components group dornacher strae 3 d-85622 feldkirchen postfach 201, d-85619 feldkirchen germany tel: <49 (89) 9 9180-0 fax: <49 (89) 9 29 30 00 hitachi europe ltd. electronic components group whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44 (1628) 585000 fax: <44 (1628) 585200 hitachi semiconductor (america) inc. 179 east tasman drive san jose,ca 95134 tel: <1 (408) 433-1990 fax: <1(408) 433-0223 for further information rite to: colophon 6.0

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