1.8v, 500 mhz, 10-output jedec-compliant zero delay buffe r cy2sstu877 rev 1.0, november 21, 2006 page 1 of 8 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com features ? operating frequency: 125 mhz to 500 mhz ? supports ddrii sdram ? 1 to 10 differential clock buffer (sstl_18) ? spread-spectrum-compatible ? low jitter (cycle-to-cycle): 40 ps ? very low output-to-output skew: 40 ps ? auto power-down feature when input is low ? 1.8v operation ? fully jedec-compliant (jesd 82-8) ? 52-ball bga functional description the cy2sstu877 is a high-performance, low-skew, low-jitter zero delay buffer designed to distribute differential clocks in high-speed applications. this phase-locked loop (pll) clock buffer is designed for a v dd of 1.8v, an av dd of 1.8v and sstl18 differential data input and output levels. this device is a zero delay buffer that distributes a differential clock input pair (ck, ck#) to ten differ- ential pair of clock outputs (y[0:9], y#[0:9]) and one differential pair of feedback clock outputs (fbout, fbout#). the input clocks (ck, ck#), the feedback clocks (fbin, fbin#), the lvcmos (oe, os), and the analog power input (avdd) control the clock outputs. the pll in the cy2sstu877 clock driver uses the input clocks (ck, ck#) and the fee dback clocks (fbin, fbin#) to provide high-performance, low- skew, low-jitter output differ- ential clocks (y[0:9], y#[0:9]) . the cy2sstu877 is also able to track spread spectrum clocking (ssc) for reduced emi. when avdd is grounded, the pll is turned off and bypassed for test purposes. when both clock signals (ck, ck#) are logic low, the device will enter a low-power mode. an input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low-power state where all out puts, the feedback, and the pll are off. when the inputs transition from both being logic low to being differential signals, the pll will be turned back on, the inputs and outputs will be enabled and the pll will obtain phase lock between the feedback clock pair (fbin, fbin#) and the input clock pair (ck, ck#) within the specified stabili- zation time t l . block diagram pin configuration 52 bga 123456 a clkt1 clkt0 clkc0 clkc5 clkt5 clkt6 b clkc1 gnd gnd gnd gnd clkc6 c clkc2 gnd nb nb gnd clkc7 d clkt2 vddq vddq vddq os clkt7 e clk_i nt vddq nb nb vddq fb_i nt f clk_inc vddq nb nb oe fb_inc g agnd vddq vddq vddq vddq fb_outc h avdd gnd nb nb gnd fb_outt j clkt3 gnd gnd gnd gnd clkt8 k clkc3 clkc4 clkt4 clkt9 clkc9 clkc8
cy2sstu877 rev 1.0, november 21, 2006 page 2 of 8 pin description pin no. name description g1 agnd ground for 1.8v analog supply h1 avdd 1.8v analog supply e1, f1 clk_int, clk_inc differential clock input with a (10k?100k ) pull-down resistor e6, f6 fb_int, fb_inc feedback differential clock input h6, g6 fb_outt, fb_outc feedback differential clock output b2, b3, b4, b5, c2, c5, h2, h5, j2, j3, j4, j5 gnd ground f5 oe output enable (async) fo r clkt[0:9] and clkc [0:9] d5 os output select (tied to gnd or vddq) d2, d3, d4, e2, e5 , f2, g2, g3, g4, g5 vddq 1.8v supply a2, a1, d1, j1, k3, a5, a6, d6 , j6, k4, clkt [0:9] buffered output of input clock, clk a3, b1, c1, k1, k2, a4, b6, c6, k6, k5 clkc [0:9] buffered output of input clock, clk table 1. function table inputs outputs pll avdd oe os clk_int clk_inc clkt clkc fb_outt fb_outc gnd h x l h l h l h bypassed/off gnd h x h l h l h l bypassed/off gnd l h l h lz lz l h bypassed/off gnd l l h l lz,clkt7 active lz,clkc7 active hlbypassed/off vdd l h l h lz lz l h on vdd l l h l lz,clkt7 active lz,clkc7 active hl on vdd h x l h l h l h on vdd h x h l h l h l on vdd x x l l lz lz lz lz off x x x h h reserved recommended operating conditions parameter description condition min. max. unit t a (com.) ambient operating temp 0 70 c v dd , av dd operating voltage 1.7 1.9 v
cy2sstu877 rev 1.0, november 21, 2006 page 3 of 8 absolute maximum conditions parameter description condition min. max. unit v in input voltage range ?0.5 v ddq + 0.5 v v out output voltage range ?0.5 v ddq + 0.5 v t s storage temperature ?65 150 c v cc, av cc supply voltage range ?0.5 2.5 v i ik input clamp current ?50 50 ma i ok output clamp current ?50 50 ma i o continuous output current ?50 50 ma continuous current through v dd /gnd ?100 100 ma dc electrical specifications parameter description conditions min. max. unit v ik input clamping voltage i i = ?18 ma ?1.2 v v od output differential voltage 0.5 v v ox output differential crossing voltage v ddq /2 ? 0.08 v ddq /2 + 0.08 v v ix input differential crossing voltage (v ddq /2) ? 0.15 (v ddq /2) + 0.15 v v id dc input differential voltage (dc values) 0.3 v ddq + 0.4 v v id ac input differential voltage (ac values) 0.6 v ddq + 0.4 v v il input low voltage (oe, os, clk_int, clk_inc) 0.35 * v ddq v v ih input high voltage (oe, os, clk_int, clk_inc) 0.65 * v ddq v v ol output low voltage i ol = 100 a0.1v i ol = 9 ma 0.6 v v oh output high voltage i oh = ?100 av ddq ? 0.2 v i oh = ?9 ma 1.1 v i ih input high current v in = v ddq or gnd ?250 250 a i il input low current v in = v ddq or gnd ?10 10 a i odl output disabled low current v odl = 100 mv oe = gnd 100 a i ddld static supply current i ddq + i add, clk_int = clk_inc = gnd 500 a i dd dynamic supply current c l = 0 @ 270 mhz 300 ma i oh output high current ?9 ma i ol output low current 9 ma c in input capacitance (i nput capacitance of clk_int, clk_inc, fb_int, fb_inc) v i = v ddq or gnd 23pf c out pf c in(delta) ci(delta) (clk_int, clk_inc, fb_int, fb_inc) v i = v ddq or gnd ?0.25 0.25 pf
cy2sstu877 rev 1.0, november 21, 2006 page 4 of 8 notes: 1. operating clock frequency indicates a range over which the pll mu st be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). 2. application clock frequency indicates a range over which the pll must meet all timing requirements. ac timing specifications parameter description co nditions min. max. unit f clk [1,2] clock frequency (max) room temp and nominal v ddq 125 500 mhz clock frequency (application) room temp and nominal v ddq 250 500 mhz t dc input duty cycle 40 60 % t odc output duty cycle 48 52 % t lock pll lock time ? 15 s t oenb output enable time oe to any clkt/ clkc[0:9] ? 8 ns t odis output disable time oe to any clkt/ clkc[0:9] ? 8 ns tjitt (cc) cycle-to-cycle jitter ?40 40 ps tjit (period) period jitter ?30 30 ps tjit (h-period) half period cycle-to-cycle jitter above 270 mhz ?45 45 ps below 270 mhz ?60 60 ps t ( ) static phase offset average 1000 cycles ?50 50 ps t ( )dyn dynamic phase offset ?40 40 ps t skew clock skew ? 40 ps s lr(o) output slew rate clkt/ clkc[0:9], fb_outt, fb_outc 1.5 4 v/ns s lr(i) input slew rate clk_int, clk_inc, fb_int, fb_inc 14v/ns oe 0.5 v/ns figure 1. test loads for timing measurement
cy2sstu877 rev 1.0, november 21, 2006 page 5 of 8 figure 2. cycle-to-cycle jitter - figure 3. period jitter - t jit(per) figure 4. half period jitter -
cy2sstu877 rev 1.0, november 21, 2006 page 6 of 8 figure 5. static phase offset (differential probes) figure 6. dynamic phase offset (differential probes) figure 7. output skew
cy2sstu877 rev 1.0, november 21, 2006 page 7 of 8 clkt/clkc clkt clkc figure 8. output enable and disable times figure 9. input/output slew rates clkt clkc pll avdd agnd 0.1 f 2200 pf 4.7 pf 1 r1 card via card via vddq gnd bead 1206 0603 0603 figure 10. av dd filtering [3,4,5] ordering information part number package type product flow lead-free and rohs compliant cy2sstu877bvxc-32 52-pin vfbga for ddr400 commercial, 0 to 70 c CY2SSTU877BVXC-32T 52-pin vfbga for ddr400 ? tape& reel commercial, 0 to 70 c cy2sstu877bvxi-32 52-pin vfbga for ddr400 industrial, ?40 to 85 c cy2sstu877bvxi-32t 52-pin vfbga for ddr400 ? tape& reel industrial, ?40 to 85 c cy2sstu877bvxc-43 52-pin vfbga for ddr533 commercial, 0 to 70 c cy2sstu877bvxc-43t 52-pin vfbga for ddr533 ? tape& reel commercial, 0 to 70 c cy2sstu877bvxi-43 52-pin vfbga for ddr533 industrial, ?40 to 85 c cy2sstu877bvxi-43t 52-pin vfbga for ddr533 ? tape& reel industrial, ?40 to 85 c notes: 3. place the 2200-pf capacitor close to the pll. 4. use a wide trace for the pll analog power and ground. connect pl l & caps to agnd trace & connec t trace to one gnd via (farthe st from pll). 5. recommended bead: fair-rite p/n 2506036017y0 or equivalent (0.9 ohm dc max, 600 ohms@100 mhz).
rev 1.0, november 21, 2006 page 8 of 8 cy2sstu877 while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimensions a 1 a1 corner 0.65 0.65 ?0.300.05(52x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.210.05 1.00 max c seating plane 0.55 max. 0.25 c 0.15 c a1 corner top view bottom view 2 3 4 3.25 5.85 b c d e f g h 65 46 5 23 1 4.500.10 7.000.10 a 7.000.10 4.500.10 b 1.625 2.925 0.26 max. j k k j h e g f d c b a reference jedec mo-225 dimension in mm 52 vfbga 4.5 7.0 1.0 mm bv52a
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