1 features v cc gnd osc v fb comp sense v ref v out output enable 5v reference internal bias nor s r pwm latch current sensing comparator oscillator 1 v r 2 r v c error amplifier + ? 2.50v set/ reset undervoltage lock-out circuit 34v ( ) indicates cs-2843a/3843a 16v/10v (8.4v/7.6v) v cc pwr pwr gnd optimized for off-line control internally trimmed temperature compensated oscillator maximum duty-cycle clamp v ref stabilized before output stage is enabled low start-up current pulse-by-pulse current limiting improved undervoltage lockout double pulse suppression 1% trimmed bandgap reference high current totem pole output package options cs2842a/3843a series off-line current mode pwm control circuit with undervoltage lockout cs2842a/cs3842a cs2843a/cs3843a description block diagram absolute maximum ratings supply voltage (i cc <30ma).........................................................................self limiting supply voltage (low impedance source) .................................................................30v output current..............................................................................................................1a output energy (capacitive load) ................................................................................5j analog inputs (v fb , sense) ...........................................................................-0.3v to 5.5v error amp output sink current .............................................................................10ma lead temperature soldering wave solder (through hole styles only) ..........10 sec. max, 260c peak reflow (smd styles only) ...........60 sec. max above 183c, 230c peak 1 comp 2 3 4 v fb sense osc v ref v cc v out gnd 8 7 6 5 8 lead pdip & so narrow 10 7 14 13 12 8 1 2 3 4 5 6 11 9 comp nc v fb nc sense nc osc v ref nc v cc v cc pwr v out pwr gnd gnd 14 lead so narrow the cs284xa, cs384xa provides all the necessary features to implement off-line fixed frequency current-mode control with a minimum number of external components. the cs384xa family incorporates a new precision temperature-controlled oscillator with an internally trimmed discharge current to minimize varia- tions in frequency. a precision duty- cycle clamp eliminates the need for an external oscillator when a 50% duty- cycle is used. duty-cycles greater than 50% are also possible. on board logic ensures that v ref is stabilized before the output stage is enabled. ion implant resistors provide tighter con- trol of undervoltage lockout. other features include low start-up current, pulse-by-pulse current limit- ing, and a high-current totem pole out- put for driving capacitive loads, such as the gate of power mosfet. the out- put is low in the off state, consistent with n-channel devices. the cs384xa series of current-mode control ics are available in 8 and14 lead packages for surface mount (so) applications as well as 8 lead pdip packages. a company ? rev. 7/9/99 cherry semiconductor corporation 2000 south county trail, east greenwich, ri 02818 tel: (401)885-3600 fax: (401)885-5786 email: info@cherry-semi.com web site: www.cherry-semi.com
2 electrical characteristics: -25 t a 85 ? c for cs2842a/2843a, 0 t a 70 ? c for cs3842a/3843a. v cc = 15v (note 1); r t = 680 ? , c t = .022f for triangular mode, r t = 10k ? , c t = 3.3nf for sawtooth mode (see figure 3), unless otherwise stated. cs2842a/cs2843a cs3842a/cs3843a parameter test conditions min typ max min typ max units cs2842a/3843a series reference section output voltage t j = 25 ? c, i out = 1ma 4.95 5.00 5.05 4.90 5.00 5.10 v line regulation 12 v in 25v 6 20 6 20 mv load regulation 1 i out 20ma 6 25 6 25 mv temperature stability (note 2) 0.2 0.4 0.2 0.4 mv/ ? c total output variation line, load, temp. (note 2) 4.90 5.10 4.82 5.18 v output noise voltage 10hz f 10khz, t j = 25 ? c (note 2) 50 50 v long term stability t a = 125 ? c, 1khrs. (note 2) 5 25 5 25 mv output short circuit t a = 25 ? c -30 -100 -180 -30 -100 -180 ma oscillator section initial accuracy sawtooth mode (see fig. 3), t j = 25 ? c475257475257khz triangular mode (see fig. 3), t j = 25 ? c475257445260khz voltage stability 12 v cc 25v 0.2 1.0 0.2 1.0 % temp. stability sawtooth mode t min t a t max (note 2) 5 5 % triangular mode t min t a t max (note 2) 8 8 % amplitude osc peak to peak 1.7 1.7 v discharge current t j = 25 ? c 7.5 8.3 9.3 7.5 8.3 9.3 ma t min t a t max 7.2 9.5 7.2 9.5 ma error amp section input voltage v comp = 2.5v 2.45 2.50 2.55 2.42 2.50 2.58 v input bias current v fb = 0 -0.3 -1.0 -0.3 -2.0 a a vol 2 v out 4v 65 90 65 90 db unity gain bandwidth (note 2) 0.7 1.0 0.7 1.0 mhz psrr 12 v cc 25v 60 70 60 70 db output sink current v fb = 2.7v, v comp = 1.1v 2 6 2 6 ma output source current v fb = 2.3v, v comp = 5v -0.5 -0.8 -0.5 -0.8 ma v out high v fb = 2.3v, r l = 15k ? to ground 5 6 5 6 v v out low v fb = 2.7v, r l = 15k ? to v ref 0.7 1.1 0.7 1.1 v current sense section gain (notes 3 & 4) 2.85 3.00 3.15 2.85 3.00 3.15 v/v maximum input signal v comp = 5v (note 3) 0.9 1.0 1.1 0.9 1.0 1.1 v psrr 12 v cc 25v (note 3) 70 70 db input bias current v sense = 0 -2 -10 -2 -10 a delay to output t j = 25 ? c (note 2) 150 300 150 300 ns output section output low level i sink = 20ma 0.1 0.4 0.1 0.4 v i sink = 200ma 1.5 2.2 1.5 2.2 v output high level i source = 20ma 13.0 13.5 13.0 13.5 v i source = 200ma 12.0 13.5 12.0 13.5 v
3 cs2842a/3843a series electrical characteristics: continued cs2842a/cs2843a cs3842a/cs3843a parameter test conditions min typ max min typ max units cs2842a cs3842a cs2843a/cs3843a parameter test conditions min typ max min typ max min typ max units notes: 1. adjust v cc above the start threshold before setting at 15v. 3. parameter measured at trip point of latch with vfb=0. 2.these parameters, although guaranteed, are not 100% tested in production. 4. gain defined as: a = ; 0 vsense 0.8v. ? v comp ? v sense under-voltage lockout section start threshold 15 16 17 14.5 16.0 17.5 7.8 8.4 9.0 v min. operating after turn on 9 10 11 8.5 10.0 11.5 7.0 7.6 8.2 v voltage output section: continued rise time t j = 25 ? c, c l = 1nf (note 2) 50 150 50 150 ns fall time t j = 25 ? c, c l = 1nf (note 2) 50 150 50 150 ns output leakage uvlo active, v out = 0 -0.01 -10.00 -0.01 -10.00 a total standby current start-up current 0.5 1.0 0.5 1.0 ma operating supply current v fb = v sense = 0v, r t = 10k ? , c t = 3.3nf 11 17 11 17 ma v cc zener voltage i cc = 25ma 34 34 v package pin description package pin # pin symbol function 8l pdip/so 14l so narrow 1 1 comp error amp output, used to compensate error amplifier 23 v fb error amp inverting input 3 5 sense noninverting input to current sense comparator 4 7 osc oscillator timing network with capacitor to ground, resistor to v ref 5 8 gnd ground 9 pwr gnd output driver ground 610v out output drive pin 11 v cc pwr output driver positive supply 712v cc positive power supply 814v ref output of 5v internal reference 2,4,6,13 nc no connection
4 cs2842a/3843a series v ref v cc v out 1k ? 1w 0.1 f 0.1 f v ref v cc v out gnd v fb sense osc comp 5k ? 100k ? 4.7k ? 1k ? error amp adjust 4.7k ? sense adjust r t 2n2222 c t gnd a test circuit undervoltage lockout during undervoltage lockout (figure 1), the output driv- er is biased to a high impedance state. the output should be shunted to ground with a resistor to prevent output leakage current from activating the power switch. pwm waveform to generate the pwm waveform, the control voltage from the error amplifier is compared to a current sense signal which represents the peak output inductor current (figure 2). an increase in v cc causes the inductor current slope to increase, thus reducing the duty cycle. this is an inherent feed-forward characteristic of current mode control, since the control voltage does not have to change during changes of input supply voltage. when the power supply sees a sudden large output cur- rent increase, the control voltage will increase allowing the duty cycle to momentarily increase. since the duty cycle tends to exceed the maximum allowed to prevent trans- v cc on/off command to reset of ic v on 16v 8.4v v off 10v 7.6v csx842a csx843a <15ma <1ma v on v off i cc v cc circuit description typical performance characteristics .0005 .001 .002 .003 .005 .01 .02 .03 .04 800 900 freq. (khz) c t ( f) 700 600 500 400 300 200 100 .05 r t =1.5k ? r t =680 ? r t =10k ? ? ) 70 60 50 40 30 20 10 4k 3k 500 400 300 100 oscillator duty cycle vs r t oscillator frequency vs c t figure 1: typical undervoltage characteristics
5 cs2842a/3843a series former saturation in some power supplies, the internal oscillator waveform provides the maximum duty cycle clamp as programmed by the selection of oscillator com- ponents. setting the oscillator oscillator timing capacitor, c t , is charged by v ref through r t and discharged by an internal current source. during the discharge time, the internal clock signal blanks out the output to the low state, thus providing a user selected maximum duty cycle clamp. charge and discharge times are determined by the formula: t c = r t c t ln t d = r t c t ln substituting in typical values for the parameters in the above formulas: v ref = 5.0v, v upper = 2.7v, v lower = 1.0v, i d = 8.3ma t c 0.5534r t c t t d = r t c t ln the frequency and maximum duty cycle can be deter- mined using the typical performance characteristic graphs. grounding high peak currents associated with capacitive loads neces- sitate careful grounding techniques. timing and bypass capacitors should be connected close to gnd pin in a sin- gle point ground. the transistor and 5k ? potentiometer, shown in the test circuit, are used to sample the oscillator waveform and apply an adjustable ramp to sense . ) 2.3 - 0.0083 r t 4.0 - 0.0083 r t ( ) v ref - i d r t - v lower v ref - i d r t - v upper ( ) v ref - v lower v ref - v upper ( v ref osc gnd r t c t circuit description: continued v osc internal clock large r t ( 10k ? ) v ref internal clock small r t ( 700 ? ) sawtooth mode triangular mode v upper v lower t c t d v cc i out v out switch current ea output v osc osc reset figure 2: timing diagram for key cs2841b parameters figure 3: oscillator timing network and parameters timing parameters
thermal data 8 l 8 l 14 l pdip so narrow so narrow r jc typ 52 45 30 ? c/w r ja typ 100 165 125 ? c/w 6 ordering information part number 0 ? c to -25 ? c to description 70 ? c85 ? c cs2842aln8 8l pdip cs2843aln8 8l pdip cs3842agn8 8l pdip cs3842agd8 8l so narrow cs3842agdr8 8l so narrow (tape & reel) CS3842AGD14 14l so narrow cs3842agdr14 14l so narrow (tape & reel) cs3843agn8 8l pdip cs3843agd8 8l so narrow cs3843agdr8 8l so narrow (tape & reel) cs3843agd14 14l so narrow cs3843agdr14 14l so narrow (tape & reel) rev. 7/9/99 cs2842a/3843a series d lead count metric english max min max min 8 lead pdip 10.16 9.02 .400 .355 8 lead so narrow 5.00 4.80 .197 .189 14 lead so narrow 8.75 8.55 .344 .337 package specification package dimensions in mm (inches) package thermal data ? 1999 cherry semiconductor corporation cherry semiconductor corporation reserves the right to make changes to the specifications without notice. please contact cherry semiconductor corporation for the latest available information. plastic dip (n); 300 mil wide 0.39 (.015) min. 2.54 (.100) bsc 1.77 (.070) 1.14 (.045) d some 8 and 16 lead packages may have 1/2 lead at the end of the package. all specs are the same. .203 (.008) .356 (.014) ref: jedec ms-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022) surface mount narrow body (d); 150 mil wide 1.27 (.050) bsc 0.51 (.020) 0.33 (.013) 6.20 (.244) 5.80 (.228) 4.00 (.157) 3.80 (.150) 1.57 (.062) 1.37 (.054) d 0.25 (0.10) 0.10 (.004) 1.75 (.069) max 1.27 (.050) 0.40 (.016) ref: jedec ms-012 0.25 (.010) 0.19 (.008)
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