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64-bit intel ? xeon? processor with 2 mb l2 cache datasheet september 2005 document number: 306249-002
2 datasheet information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, in tel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products includi ng liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instruct ions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 64-bit intel ? xeon? processor with 2 mb l2 cache may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current ch aracterized errata are available on request. mpeg is an international standard for video compression/decompressi on promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various entities, including intel corporation. contact your local intel sales office or your distributor to obt ain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are refer enced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. intel, pentium, intel xeon, speedstep, intel netburst, intel extended memory 64 technology, and itanium are trademarks or regis tered trademarks of intel corporation or its subsidiaries in the united states and other countries. intel? extended memory 64 technology (intel? em64t) requires a computer system with a processor, chipset, bios, os, device driv ers and applications enabled for intel em64t. processor will not opera te (including 32-bit operation) without an intel em64t-enabled bi os. performance will vary depending on your hardware and software configurations. in tel em64t-enabled os, bios, device drivers and applications may not be available. check with your vendor for more information. *other names and brands may be claimed as the property of others. copyright ? 2005, intel corporation
datasheet 3 contents 1 introduction.................................................................................................................. ..... 11 1.1 terminology......................................................................................................... 12 1.2 references .......................................................................................................... 14 1.3 state of data ....................................................................................................... 15 2 electrical specifications................................................................................................... 1 7 2.1 power and ground pins ...................................................................................... 17 2.2 decoupling guidelines ........................................................................................ 17 2.2.1 vcc decoupling ..................................................................................... 17 2.2.2 vtt decoupling...................................................................................... 17 2.2.3 front side bus agtl+ decoupling ........................................................ 18 2.3 front side bus clock (b clk[1:0]) and processor clocking................................ 18 2.3.1 front side bus frequency select signals (bsel[1:0]) ................ .......... 18 2.3.2 phase lock loop (pll) and filter.......................................................... 19 2.4 voltage identification (vid).................. ................................................................ 20 2.5 reserved or unused pins...................... ............................................................. 22 2.6 front side bus signal groups............................................................................. 22 2.7 gtl+ asynchronous and agtl+ asynchr onous signals ................................... 24 2.8 test access port (tap) connection.................................................................... 24 2.9 mixing processors ............................................................................................... 25 2.10 absolute maximum and minimum ratings .......................................................... 25 2.11 processor dc specifications............................................................................... 26 2.11.1 flexible motherboard guidelines (fmb)................................................. 26 2.11.2 vcc overshoot specification.................................................................31 2.11.3 die voltage validation ............................................................................ 32 3 mechanical specifications ................................................................................................ 35 3.1 package mechanical drawings ........................................................................... 36 3.2 processor component kee pout zones ............................................................... 39 3.3 package loading specifications ......................................................................... 39 3.4 package handling guidelines ............................................................................. 40 3.5 package insertion specifications ........................................................................ 40 3.6 processor mass specificat ions ........................................................................... 40 3.7 processor materials......... .................................................................................... 40 3.8 processor markings............................................................................................. 41 3.9 processor pin-out coordinates........................................................................... 42 4 signal definitions............................................................................................................ .. 45 4.1 signal definitions................................................................................................. 45 5 pin listing................................................................................................................... ...... 55 5.1 64-bit intel ? xeon? processor with 2 mb l2 cache pin assignments .............. 55 5.1.1 pin listing by pin name ......................................................................... 55 5.1.2 pin listing by pin number ...................................................................... 63 6 thermal specifications .................................................................................................... 71 6.1 package thermal specifications ......................................................................... 71 6.1.1 thermal specifications ........................................................................... 71
4 datasheet 6.1.2 thermal metrology ................................................................................. 78 6.2 processor thermal features............................................................................... 79 6.2.1 thermal monitor ..................................................................................... 79 6.2.2 thermal monitor 2 .................................................................................. 79 6.2.3 on-demand mode.................................................................................. 81 6.2.4 prochot# signal pin .......................................................................... 81 6.2.5 forcepr# signal pin .......................................................................... 81 6.2.6 thermtrip# signal pin ....................................................................... 82 6.2.7 tcontrol and fan speed reduction................................................. 82 6.2.8 thermal diode........................................................................................ 82 7 features ...................................................................................................................... ..... 85 7.1 power-on configuration options ........................................................................ 85 7.2 clock control and low power states..... ............................................................. 85 7.2.1 normal state .......................................................................................... 86 7.2.2 halt or enhanced halt power down states ...................................... 86 7.2.3 stop grant state .................................................................................... 87 7.2.4 enhanced halt snoop or ha lt snoop state, stop grant snoop state ........................................................................................... 88 7.2.5 sleep state............................................................................................. 88 7.3 demand based switching (dbs) with enhanced intel speedstep ? technology..................................................................................... 89 8 boxed processor specifications....................................................................................... 91 8.1 introduction ......................................................................................................... 91 8.2 mechanical specifications ................................................................................... 93 8.2.1 boxed processor heatsink dimensions (cek) ...................................... 93 8.2.2 boxed processor heatsink weight ....................................................... 101 8.2.3 boxed processor retention mechanism and heatsink support (cek) ....................................................................... 101 8.3 electrical requirements .................................................................................... 101 8.3.1 fan power supply (active cek) .......................................................... 101 8.3.2 boxed processor coo ling requirements ............................................. 103 8.4 boxed processor contents ............................................................................... 104 9 debug tools specifications............................................................................................ 105 9.1 debug port system requirements......... ........................................................... 105 9.2 target system implementation ......................................................................... 105 9.2.1 system implementation........................................................................ 105 9.3 logic analyzer interface (lai) ........... ............................................................... 105 9.3.1 mechanical considerations .................................................................. 106 9.3.2 electrical considerations...................................................................... 106 figures 2-1 phase lock loop (pll) f ilter requirements ...................................................... 19 2-2 64-bit intel ? xeon? processor and 64-bit intel ? xeon? mv 3.20 ghz processor load current vs. time ................................................ 29 2-3 64-bit intel ? xeon? lv 3 ghz processor load current vs. time ..................... 29 2-4 vcc static and transient tolerance................................................................... 31 2-5 vcc overshoot example waveform................................................................... 32 3-1 processor package assembly sketch ................................................................ 35
datasheet 5 3-2 processor package drawing (sheet 1 of 2) ........................................................ 37 3-3 processor package drawing (sheet 2 of 2) ........................................................ 38 3-4 processor top-side markings (example). ........................................................... 41 3-5 processor bottom-side mark ings (example) ...................................................... 41 3-6 processor pin- out coordinates, top view .......... ................................................ 42 3-7 processor pin-ou t coordinates, bottom view ..................................................... 43 6-1 64-bit intel ? xeon? processor with 2 mb l2 cache thermal profiles a and b (prb = 1)............................................................................................... 73 6-2 64-bit intel ? xeon? mv 3.20 ghz processor thermal profiles a and b (prb = 1)............................................................................................... 75 6-3 64-bit intel ? xeon? lv processor thermal prof iles a and b (prb = 0) ............ 77 6-4 case temperature (tcase) measurement location ...... ............. ............ .......... 78 6-5 demand based switching frequency and voltage ordering .............................. 80 7-1 stop clock state machine ................................................................................... 87 8-1 1u passive cek heatsink................................................................................... 91 8-2 2u passive cek heatsink................................................................................... 92 8-3 active cek heatsink (representation only) ....................................................... 92 8-4 passive 64-bit intel ? xeon? processor with 2 mb l2 cache thermal solution (2u and larger) ..................................................................................... 93 8-5 top-side board keepout zones (part 1)............................................................. 94 8-6 top-side board keepout zones (part 2)............................................................. 95 8-7 bottom-side board keepout zones........ ............................................................. 96 8-8 board mounting hole ke epout zones .................................................................97 8-9 volumetric height keep-ins................................................................................. 98 8-10 4-pin fan cable connector (for active cek heatsink)...................................... 99 8-11 4-pin base board fan he ader (for active cek heatsink) ...............................100 8-12 fan cable connector pin out for 4-pin active cek thermal solution .............102 tables 1-1 features of the 64-bit intel ? xeon? processor with 2 mb l2 cache ................. 12 2-1 core frequency to front side bus multiplier configur ation ................................ 18 2-2 bsel[1:0] freq uency table ...... ................ ................ ................ ................ .......... 19 2-3 voltage identification definition 2, 3 .................................................................... 21 2-4 front side bus signal groups............. ................................................................ 23 2-5 signal description table . .................................................................................... 24 2-6 signal reference voltages .................................................................................. 24 2-7 absolute maximum and minimum ratings .......................................................... 25 2-8 voltage and current specifications ..................................................................... 27 2-9 vcc static and transient tolerance................................................................... 30 2-10 vcc overshoot specifications ............................................................................ 31 2-11 bsel[1:0] and vid[ 5:0] signal group dc specificat ions....... ................ ............. 32 2-12 agtl+ signal group dc specifications ............................................................. 33 2-13 pwrgood input and tap signal group dc specifications.............................. 33 2-14 gtl+ asynchronous and agtl+ asynchronous signal group dc specifications ...................................................................................................... 34 2-15 vidpwrgd dc specifications ........................................................................... 34 3-1 processor load ing specifications ....................................................................... 39 3-2 package handling guidelines ................... .......................................................... 40 3-3 processor materials ............................................................................................. 40 4-1 signal definitions................................................................................................. 45 5-1 pin listing by pin name ...................................................................................... 55
6 datasheet 5-2 pin listing by pin number ................................................................................... 63 6-1 64-bit intel ? xeon? processor with 2 mb l2 cache thermal specifications........................................................................................ 72 6-2 64-bit intel ? xeon? processor with 2 mb l2 cache thermal profile a (prb = 1) ............................................................................................................ 74 6-3 64-bit intel ? xeon? processor with 2 mb l2 cache thermal profile b (prb = 1) ............................................................................................................ 74 6-4 64-bit intel ? xeon? mv 3.20 ghz processor thermal specifications ............... 75 6-5 64-bit intel ? xeon? mv 3.20 ghz processor thermal profile a (prb = 1) ............................................................................................................ 76 6-6 64-bit intel ? xeon? mv 3.20 ghz processor thermal profile b (prb = 1) ............................................................................................................ 76 6-7 64-bit intel ? xeon? lv 3 ghz processor thermal specifications ..................... 77 6-8 64-bit intel ? xeon? lv 3 ghz processor thermal profile (prb = 0) ................ 78 6-9 thermal diode parameters ................................................................................. 82 6-10 thermal diode interface. ..................................................................................... 83 7-1 power-on configuration option pins .................................................................. 85 8-1 pwm fan frequency specific ations for 4-pin active cek thermal solution ................ ............................................................................... 102 8-2 fan specifications for 4- pin active cek thermal solution ............................... 102 8-3 fan cable connector pin out for 4-pin active cek th ermal solution ............. 102 8-4 fan cable connector supplier and part number ............................................. 103
datasheet 7 revision history version number description date -001 initial release of the document. february 2005 -002 updated to include 2.8 ghz, 3.8 ghz, and power-optimized versions. september 2005
8 datasheet
datasheet 9 64-bit intel ? xeon? processor with 2 mb l2 cache product features the 64-bit intel ? xeon? processor with 2 mb l2 cache is designed for high-perfor mance dual-processor workstation and server app lications. based on the intel netburst mi croarchitecture and the hyper-threading technology, it is binary compatible with previous in tel architecture (ia-32) processors. the 64-bit intel xeon processor with 2 mb l2 cache is scalable to two proce ssors in a multiprocessor sy stem providing exceptional performance for applications running on advanced operating systems such as windows xp*, windows server* 2003, linux*, and unix*. the 64-bit intel xeon processor with 2 mb l2 cache delivers compute power at unparalleled value and flexibility for powerf ul workstations, internet infrastructure, and departmental server applications. th e intel netburst micro-architecture and hyper-threading technology deliver outstanding performance and headroom for peak internet server workloads, resulting in faster response times, support for more users, and improved scalability. ? available at 2.80, 3, 3.20, 3.40, 3.60, and 3.80 ghz ? available in power-optimized configurations with lv 3 ghz (55 w tdp) and mv 3.2 ghz (90 w tdp) processors ? 90 nm process technology ? dual processing server/workstation support ? binary compatible with applications running on previous members of intel?s ia-32 microprocessor line ? intel netburst ? microarchitecture ? hyper-threading technology ? hardware support for multithreaded applications ? fast 800 mhz system bus ? rapid execution engine: arithmetic logic units (alus) run at twice the processor core frequency ? hyper pipelined technology ? advanced dynamic execution ? very deep out-of-order execution ? enhanced branch prediction ? execute disable bit ? includes 16-kb level 1 data cache ? intel ? extended memory 64 technology (intel ? em64t) ? 2 mb advanced transfer ca che (on-die, full speed level 2 (l2) cache) with 8-way associativity and error correcting code (ecc) ? enables system support of up to 64 gb of physical memory ? 144 streaming simd ex tensions 2 (sse2) instructions ? 13 streaming simd extensions 3 (sse3) instructions ? enhanced floating-point and multimedia unit for enhanced video, audio, encryption, and 3d performance ? system management mode ? thermal monitor ? machine check architecture (mca) ? demand based switching (dbs) with enhanced intel speedstep ? technology
10 datasheet
datasheet 11 1 introduction this document details specifications and features of the 64-bit intel ? xeon? processor with 2 mb l2 cache, including new processors in lv (55 w tdp) and mv (90 w tdp) configurations. in this document, ?processor? and ?64-bit intel xeon pr ocessor with 2 mb l2 cache? are generic terms for all of these processors. details specific to a pa rticular processor will be specifically called out in the applicable text, table or figure. the 64-bit intel ? xeon? processor with 2 mb l2 cache, 64-bit intel ? xeon? lv 3 ghz processor and 64-bit intel ? xeon? mv 3.20 ghz processor are server / workstation processors based on improvements to the intel netburst microarchitecture. they maintain the tradition of compatibility with ia-32 software and include featur es found in the intel xeon processor such as hyper pipelined technology, a rapid execution engine, and an execution trace cache. hyper pipelined technology includes a multi-stage pipeline, allowing the processor to reach much higher core frequencies. the 800 mhz system bus is a quad-pumped bus running off a 200 mhz system clock making 6.4 gb per second data transfer ra tes possible. the execution trace cache is a level 1 cache that stores decoded micro-operations, whic h removes the decoder fr om the main execution path, thereby increasing performance. in addition, enhanced thermal and power mana gement capabilities are implemented including thermal monitor and thermal monitor 2. these cap abilities are targeted for dual processor (dp) servers and workstations in data center and office environments. ther mal monitor and thermal monitor 2 provide efficient and effective cooling in high temperature si tuations. demand based switching (dbs) with enhanced intel speedstep allows trade-offs to be made between performance and power consumption. this may lower average power consumption (in conjunction with os support). [note: not all processors are capable of supporting thermal monitor 2 or enhanced intel speedstep technology. more deta ils on which processor fr equencies support this feature are provided in the 64-bit intel ? xeon? processor with 800 mhz system bus (1 mb and 2 mb l2 cache versions ) specification update . the 64-bit intel xeon processor with 2 mb l2 cache supports hyper-threading technology. this feature allows a single, physical processor to function as two logical processors. while some execution resources such as caches, execution units, and buses are shared, each logical processor has its own architecture state with its own set of general-purpose registers, control registers to provide increased system responsiveness in multitasking environments, and headroom for next generation multithreaded applications. more information on hyper-threading technology can be found at http://www.intel.com/technology/hyperthread. the 64-bit intel xeon processor with 2 mb l2 cache also includes the execute disable bit capability previously available in intel ? itanium ? processors. this feature, when combined with a supported operating system, allows memory to be ma rked as executable or non-executable. if code attempts to run in non-executable memory, the processor raises an error to the operating system. this feature can preven t some classes of viruses or wo rms that exploit buffer overrun vulnerabilities and can thus help improve th e overall security of the system. see the intel ? architecture software developer?s manual for more detailed information. other features within the intel netburst microa rchitecture include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, streaming simd extensions 2 (sse2) and streaming simd exte nsions 3 (sse3). advanced dynamic execution improves speculative execution and branch prediction internal to the processor. the advanced transfer cache is a 2 mb, on-die, level 2 (l2) cache with increas ed bandwidth. the floating point and multi-media units include 128-bit wide regist ers and a separate register for data movement. streaming simd2 (sse2) instructions provide hi ghly efficient double-precision floating point,
12 datasheet introduction simd integer, and memory management operations. in addition, sse3 instructions have been added to further extend the capabilities of intel processor technology. other processor enhancements include core frequency improve ments and microarchitec tural improvements. 64-bit intel xeon processors with 2 mb l2 cach e supports intel extended memory 64 technology (intel em64t) as an en hancement to intel's ia-32 architect ure. this enhancement allows the processor to execute operating systems and applications written to take advantage of the 64-bit extension technology. further details on intel extended memory 64 technology and its programming model can be found in the 64-bit intel ? extended memory 64 technology software developer's guide at http://developer.intel.com/technology/64bitextensions/ . 64-bit intel xeon pr ocessors with 2 mb l2 cache are intend ed for high perfor mance workstation and server systems with up to two processors on one system bus. the 64-bit intel xeon mv 3.20 ghz processor is a mid-voltage pr ocessor intended for volumetrical ly constrained platforms. the 64-bit intel xeon lv 3 ghz processor is a low-voltage, low-power processor intended for embedded and volumetrically constrained platforms. these processors are packaged in a 604-pin flip chip micro pin grid array (fc-mpga4) p ackage and use a surface mount zero insertion force (zif) socket (mpga604). 64-bit intel xeon processor with 2 mb l2 cache-based platforms implement independent power planes for each system bus agent. as a result, the proces sor core voltage (v cc ) and system bus termination voltage (v tt ) must connect to separate supplies. the processor core voltage utilizes power delivery guidelines denoted by vrm 10.1 and the associated load line (see voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 10.1 design guidelines for further details). implementation details can be obtained by referring to the applicable platform design guid elines. cost-reduced power deliv ery systems may be possible for mid-voltage (mv) and low-voltage (lv) processors. the 64-bit intel xeon processor with 2 mb l2 cache uses a scalable system bus protocol referred to as the ?system bus? in this document. the system bus utilizes a split-tran saction, deferred reply protocol. the system bus uses source-synchronous transfer (sst) of address and data to improve performance. the processor transfers data four ti mes per bus clock (4x data transfer rate, as in agp 4x). along with the 4x data bus, the addr ess bus can deliver addresses two times per bus clock and is referred to as a ?double-clocked? or the 2x address bus. in addition, the request phase completes in one clock cycle. work ing together, the 4x data bus and 2x address bus provide a data bus bandwidth of up to 6.4 gbytes/second (6400 mb ytes/second). finally, the system bus is also used to deliver interrupts. 1.1 terminology a ?#? symbol after a signal name refers to an active low signal, indicating a sign al is in the asserted state when driven to a low level. for example, when reset# is low, a reset has been requested. conversely, when nmi is high, a nonmaskable inte rrupt has occurred. in th e case of signals where table 1-1. features of the 64-bit intel ? xeon? processor with 2 mb l2 cache # of supported symmetric agents l2 advanced transfer cache front side bus frequency package 64-bit intel ? xeon? processor with 2 mb l2 cache 64-bit intel ? xeon? mv 3.20 ghz processor 64-bit intel ? xeon? lv 3 ghz processor 1 - 2 2 mb 800 mhz 604-pin fc- mpga4
datasheet 13 introduction the name does not imply an active state but describes part of a binary sequence (such as address or data ), the ?#? symbol implies that the signal is inve rted. for example, d[3:0] = ?hlhl? refers to a hex ?a?, and d[3:0]# = ?lhlh? also refers to a hex ?a? (h= high logic level, l= low logic level). ?front side bus? or ?system bus? refers to the interface between the proce ssor, system core logic (a.k.a. the chipset components), and other bus agents. the system bus is a multiprocessing interface to processors, memory, and i/o. for this document, ?front side bus? or ?system bus? are used as generic terms for the ?64-b it intel xeon processor with 2 mb l2 cache system bus?. commonly used terms are expl ained here for clarification: ? 64-bit intel xeon processo r with 2 mb l2 cache ? intel 64-bit microprocessor intended for dual processor servers and workstations. the 64- bit intel xeon processor with 2 mb l2 cache is based on intel?s 90 nanometer process and includes a larger 2 mb, on-die, level 2 (l2) cache. the processor uses the mp ga604 socket. for this document, ?processor? is used as the generic term for the ?64-bit intel xeon processor with 2 mb l2 cache?. ? 64-bit intel xeon mv 3.20 ghz processor ? mid-voltage (mv), low-power intel 64-bit microprocessor targeted for volumetrically cons trained platforms. unless otherwise noted, ?processor? and ?64-bit intel xeon processor wi th 2 mb l2 cache? are used as generic terms for the ?64-bit intel xeon mv 3.20 ghz processor?. ? 64-bit intel xeon lv 3 ghz processor ? low-voltage (lv), low-power intel 64-bit microprocessor targeted for embedded and volumetrically constrained platforms. unless otherwise noted, ?processor? and ?64-bit intel xeon processor with 2 mb l2 cache? are used as generic terms for the ?64-bit intel xeon lv 3 ghz processor?. ? central agent ? the central agent is the host bridge to the processor and is typically known as the chipset. ? demand based switching (dbs) with e nhanced intel speedstep technology ? demand based switching with enhanced intel speedstep technology is the next generation implementation of geyserville technology which extends power management capabilities of servers and workstations. ? enterprise voltage re gulator down (evrd) ? dc-dc converter integrated onto the system board that provide the co rrect voltage and curr ent for the processor based on the logic stat of the vid bits. ? flip chip micro pin grid array (fc-mpga4) package ? the processor package is a flip chip micro pin grid array (fc-mpga4), consisti ng of a processor core mounted on a pinned substrate with an integrated h eat spreader (ihs). this package technology employs a 1.27 mm [0.05 in.] pitch for the processor pins. ? front side bus (fsb) ? the electrical interface that connec ts the processor to the chipset. also referred to as the pr ocessor system bus or the system bus. all memory and i/o transactions as well as inte rrupt messages pass between the pr ocessor and the chipset over the fsb. ? functional operation ? refers to the normal operating conditions in which all processor specifications, including dc, ac, system bus, si gnal quality, mechani cal and thermal are satisfied. ? integrated heat spreader (ihs) ? a component of the processor package used to enhance the thermal performance of the package. component thermal solutions interface with the processor at the ihs surface. ? mpga604 socket ? the 64-bit intel xeon processor wi th 2 mb l2 cache mates with the baseboard through this surface mount, 604-pin, zero insertion force (zif) socket. see the mpga604 socket de sign guidelines for details regarding this socket.
14 datasheet introduction ? platform requirement bit ? bit 18 of the processor?s ia32_flex_brvid_sel register is the platform requirement bit (p rb) that indicates that the pr ocessor has specific platform requirements. ? processor core ? the processor?s execution engine. ? storage conditions ? refers to a non-operational state. the processor may be installed in a platform, in a tray, or loose. processors may be sealed in packaging or exposed to free air. under these conditions, processor pins should not be connected to any supply voltages, have any i/os biased or receive any clocks. ? symmetric agent ? a symmetric agent is a processor which shares the same i/o subsystem and memory array, and runs the same operatin g system as another processor in a system. systems using symmetric agents are known as symmetric mu ltiprocessor (smp) systems. 64- bit intel xeon processo rs with 2 mb l2 cache should only be used in smp systems which have two or fewer agents. ? thermal design power ? processor/chipset thermal solution should be designed to this target. it is the highest expect ed sustainable power while runn ing known power-intensive real applications. tdp is not the maximum power that the processor/ch ipset can dissipate. ? voltage regulator module (vrm) ? dc-dc converter built onto a module that interfaces with an appropriate card edge socket that supplies the correc t voltage and current to the processor. ? v cc ? the processor core power supply. ? v ss ? the processor ground. ? v tt ? the system bus termination voltage. 1.2 references material and concepts available in the following documents may be beneficial when reading this document: document intel order number 64-bit intel ? xeon ? processor with 800 mhz system bus (1 mb and 2 mb l2 cache versions) specification update 302402 64-bit intel ? xeon? processor with 2 mb l2 cache boundary scan descriptive language (bsdl) model (v2.0) and cell descriptor file (v2.0) http://developer.intel.com 64-bit intel ? xeon? processor with 2 mb l2 cache cooling solution mechanical models http://developer.intel.com 64-bit intel ? xeon? processor with 2 mb l2 cache cooling solution thermal models http://developer.intel.com 64-bit intel ? xeon? processor with 2 mb l2 cache mechanical models http://developer.intel.com 64-bit intel ? xeon? processor with 2 mb l2 cache thermal models http://developer.intel.com 64-bit intel ? xeon? processor with 2 mb l2 cache thermal/mechanical design guidelines 298348 ap-485, intel ? processor identification and cpuid instruction 241618 atx12v power supply design guidelines http://formfactors.org entry-level electronics-bay specifications: a server sy stem infrastructure (ssi) specification for entry pedestal servers and workstations http://www.ssiforum.org
datasheet 15 introduction note: contact your intel representative for the latest revision of documents without document numbers. 1.3 state of data the data contained within this do cument is subject to change. it is the most accurate information available by the publication date of this document. eps12v power supply design guide: a server system infrastructure (ssi) specification for entry chassis power supplies http://www.ssiforum.org ia-32 intel ? architecture optimization reference manual 248966 ia-32 intel ? architecture software developer's manual ? volume i: basic architecture ? volume 2a: instruction set reference, a-m ? volume 2b: instruction set reference, n-z ? volume 3: system programming guide 253665 253666 253667 253668 intel ? extended memory 64 technology software developer's manual, volume 1 intel ? extended memory 64 technology software developer's manual, volume 2 300834 300835 itp700 debug port design guide 249679 mpga604 socket design guidelines 254239 thin electronics bay specification (a server system infrastructure (ssi) specification for rack optimized servers) http://www.ssiforum.org voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 10.1 design guidelines 302732 document intel order number
16 datasheet introduction
datasheet 17 2 electrical specifications 2.1 power and ground pins for clean on-chip power distribution, the processor has 181 v cc (power) and 185 v ss (ground) inputs. all v cc pins must be connected to the processor power plane, while all v ss pins must be connected to the system gr ound plane. the processor v cc pins must be supplied with the voltage determined by the processor v oltage id entification (vid) pins. eleven signals are denoted as v tt , which provide termination for the front side bus and power to the i/o buffers. the platform must implement a separate supply for these pins, which meets the v tt specifications outlined in table 2-8 . 2.2 decoupling guidelines due to its large number of transistors and high internal clock speeds, the 64-bit intel xeon processor with 2 mb l2 cache is capable of generating large average current swings between low and full power states. this may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. larger bulk storage (c bulk ), such as electrolytic or aluminum -polymer capacitors, supply current du ring longer lasting changes in current demand by the component, such as coming out of an idle condition. similarly, they act as a storage well for current when en tering an idle condition from a running condition. care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in table 2-8 . failure to do so can result in timing violations or reduced lifetime of the component. 2.2.1 v cc decoupling regulator solutions need to prov ide bulk capacitance with a low ef fective series resistance (esr) and the baseboard designer must assure a low interconnect resistance from the voltage regulator (vrd or vrm pins) to the mpga604 socket. the pow er delivery solution must insure the voltage and current specifications are met (defined in table 2-8 ). 2.2.2 v tt decoupling decoupling must be provided on the baseboard. decoupling solutions must be sized to meet the expected load. to insure optimal performance, various factors asso ciated with the power delivery solution must be considered incl uding regulator type, power plan e and trace sizing , and component placement. a conservative decoupling solution w ould consist of a combination of low esr bulk capacitors and high frequency ceramic capacitors.
18 datasheet electrical specifications 2.2.3 front side bus agtl+ decoupling the 64-bit intel xeon processor with 2 mb l2 cache integrates signal term ination on the die, as well as part of the required high frequency decoupling capacitance on the processor package. however, additional high frequency capacitance must be added to the baseboard to properly decouple the return currents from the front side bus. bulk decoupling must also be provided by the baseboard for proper agtl+ bus operation. 2.3 front side bus clock (bclk[1:0]) and processor clocking bclk[1:0] directly controls the fr ont side bus interface speed as well as the core frequency of the processor. as in previous processor generations, the 64-bit intel xeon processor with 2 mb l2 cache core frequency is a multiple of the bclk[1: 0] frequency. the proce ssor bus ratio multiplier is set during manufacturing. the platform requirem ent bit (prb) is set for all 64-bit intel xeon processors with 2 mb l2 cache an d 64-bit intel xeon mv processo rs with 2 mb l2 cache, which means the default setting will be the minimum speed for the processor. software must override this setting to permit operation at the designated pr ocessor frequency. the prb will not be set for 64- bit intel xeon lv processors w ith 2 mb l2 cache. as a result, these processors will begin operation at their default maximum speed. it is possible to override this setting using software, permitting operation at a speed lower than the processors? tested frequency. the bclk[1:0] inputs directly control the opera ting speed of the front side bus interface. the processor core frequency is configured during re set by using values stored internally during manufacturing. the stored value sets the highest bus fraction at which the particular processor can operate. if lower speeds are desired, the appropriate ratio can be conf igured by setting bits [15:8] of the ia32_flex_brvid_sel msr. clock multiplying within the processor is provid ed by the internal phase locked loop (pll), which requires a constant frequency bclk[1:0] input, w ith exceptions for spread spectrum clocking. the 64-bit intel xeon processor with 2 mb l2 cache uses differential clocks. table 2-1 contains core frequency to front side bus multipliers and their corresponding core frequencies. note: individual processors operate only at or below the frequency marked on the package. 2.3.1 front side bus frequenc y select signals (bsel[1:0]) bsel[1:0] are open-drain outputs, which must be pulled up to v tt , and are used to select the front side bus frequency. please refer to table 2-11 for dc specifications. table 2-2 defines the possible combinations of the signals and the frequency associated with each combination. the frequency is table 2-1. core frequency to front side bus multiplier configuration core frequency to front side bus multiplier co re frequency with 200 mhz front side bus clock 1/14 2.80 ghz 1/15 3 ghz 1/16 3.20 ghz 1/17 3.40 ghz 1/18 3.60 ghz 1/19 3.80 ghz
datasheet 19 electrical specifications determined by the processor(s), chipset, and cloc k synthesizer. all front side bus agents must operate at the same core and front side bus frequ encies. individual processors will only operate at their specified front side bus clock frequency. 2.3.2 phase lock loop (pll) and filter v cca and v cciopll are power sources required by the pll cl ock generators on the processor. since these plls are analog in nature, they require quiet power supplies for minimum jitter. jitter is detrimental to the system: it degrades external i/o timings as well as internal core timings (i.e., maximum frequency). to prevent this degradation, these supplies must be low pass filtered from v tt . the ac low-pass requirements are as follows: ? < 0.2 db gain in pass band ? < 0.5 db attenuation in pass band < 1 hz ? > 34 db attenuation from 1 mhz to 66 mhz ? > 28 db attenuation from 66 mhz to core frequency the filter requirements are illustrated in figure 2-1 . table 2-2. bsel[1:0] frequency table bsel1 bsel0 bus clock frequency 00reserved 01reserved 1 0 200 mhz 11reserved figure 2-1. phase lock loop (pll) filter requirements 0 db -28 db -34 db 0.2 db forbidden zone -0.5 db forbidden zone 1 mhz 66 mhz f core f peak 1 hz dc p assband high frequency band
20 datasheet electrical specifications notes: 1. diagram not to scale. 2. no specifications for frequencies beyond f core (core frequency). 3. f peak , if existent, should be less than 0.05 mhz. 4. f core represents the maximum core frequ ency supported by the platform. 2.4 voltage identification (vid) the voltage identification (vid) specification for the 64-bit intel xeon processor with 2 mb l2 cache is defined by the voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 10.1 design guidelines . the voltage set by the vid signals is the maximum voltage allowed by the processor (please see section 2.11.2 for v cc overshoot specifica tions). vid signals are open drain outputs, which must be pulled up to v tt . please refer to table 2-11 for the dc specifications for these signals. a minimum voltage is provided in table 2-8 and changes with frequency. this allows processors running at a higher frequency to have a relaxed minimum voltage specification. the specifications have been set such that one voltage regulator can operate with all supported frequencies. individual processor vid values may be calibrate d during manufacturing such that two devices at the same core speed may have different default vid settings. this is reflected by the vid range values provided in table 2-8 . refer to the 64-bit intel ? xeon? processor with 800 mhz system bus (1 mb and 2 mb l2 cache versions) specification update for further details on specific valid core frequency and vid values of the processor. the processor uses six voltage id entification signals, vid[5:0], to support automatic selection of power supply voltages. table 2-3 specifies the voltage level corresponding to the state of vid[5:0]. a ?1? in this table refers to a high voltage level and a ?0? refers to a low voltage level. if the processor socket is empty (vid[5:0] = x11111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. see the voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 10.1 design guidelines for further details. the 64-bit intel xeon processor with 2 mb l2 cache provides the abili ty to operate while transitioning to an adjacent vid and its associated processor core voltage (v cc ). this will represent a dc shift in the load line. it should be noted that a low-to-high or high-to-low voltage state change may result in as many vid transitions as necessary to reach the target core voltage. transitions above the specified vid are not permitted. table 2-8 includes vid step sizes and dc shift ranges. minimum and maximum voltages must be maintained as shown in table 2-9 and figure 2-4 . the vrm or vrd used must be capable of regulating its output to the value defined by the new vid. dc specifications for dynami c vid transitions are included in table 2-8 and table 2-9 . please refer to the voltage regulator module (vrm) and enterprise voltage regulator-down (evrd) 10.1 design guidelines for further details. power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable.
datasheet 21 electrical specifications notes: 1. when this vid pattern is observed, the voltage regulator output should be disabled. 2. shading denotes the expected default vid range during normal ope ration for the 64-bit intel xeon processor with 2 mb l2 cache [1.2875 v -1.3875 v], 64-bit intel xeon mv 3.20 ghz processor [1.2125 v - 1.3875 v] and 64-bit intel xeon lv 3 ghz processor [1.0500 v - 1.2000 v]. please note this is subject to change. 3. shaded areas do not represent the entire range of vids that may be driven by the processo r. events causing dynamic vid transitions (see section 2.4 ) may result in a more broad range of vid values. table 2-3. voltage identification definition 2, 3 vid5 vid4 vid3 vid2 vid1 vid0 v cc_max vid5 vid4 vid3 vid2 vid1 vid0 v cc_max 0010100. 8375 0 1 1 0 1 0 1.2125 1010010. 8500 1 1 1 0 0 1 1.2250 0010010. 8625 0 1 1 0 0 1 1.2375 1010000. 8750 1 1 1 0 0 0 1.2500 0010000. 8875 0 1 1 0 0 0 1.2625 1001110. 9000 1 1 0 1 1 1 1.2750 0001110. 9125 0 1 0 1 1 1 1.2875 1001100. 9250 1 1 0 1 1 0 1.3000 0001100. 9375 0 1 0 1 1 0 1.3125 1001010. 9500 1 1 0 1 0 1 1.3250 0001010. 9625 0 1 0 1 0 1 1.3375 1001000. 9750 1 1 0 1 0 0 1.3500 0001000. 9875 0 1 0 1 0 0 1.3625 1000111. 0000 1 1 0 0 1 1 1.3750 0000111. 0125 0 1 0 0 1 1 1.3875 1000101. 0250 1100101. 4000 0000101. 0375 0100101. 4125 1 0 0 0 0 1 1.0500 1100011. 4250 0 0 0 0 0 1 1.0625 0100011. 4375 1 0 0 0 0 0 1.0750 1100001. 4500 0 0 0 0 0 0 1.0875 0100001. 4625 111111off 1 1011111. 4750 011111off 1 0011111. 4875 1 1 1 1 1 0 1.1000 1011101. 5000 0 1 1 1 1 0 1.1125 0011101. 5125 1 1 1 1 0 1 1.1250 1011011. 5250 0 1 1 1 0 1 1.1375 0011011. 5375 1 1 1 1 0 0 1.1500 1011001. 5500 0 1 1 1 0 0 1.1625 0011001. 5625 1 1 1 0 1 1 1.1750 1010111. 5750 0 1 1 0 1 1 1.1875 0010111. 5875 1 1 1 0 1 0 1.2000 1010101. 6000
22 datasheet electrical specifications 2.5 reserved or unused pins all reserved pins must remain unconnected. connection of these pins to v cc , v tt , v ss , or to any other signal (including each othe r) can result in comp onent malfunction or in compatibility with future processors. see section 5 for a pin listing of the processor and the location of all reserved pins. for reliable operation, al ways connect unused inputs or bidir ectional signals to an appropriate signal level. in a system level design, on-die termination has been included by the processor to allow end agents to be terminated within the processor silicon for most signals. in this context, end agent refers to the bus ag ent that resides on either end of th e daisy-chained front side bus interface while a middle agent is any bus agent in between the two end agents. for end agents, most unused agtl+ inputs should be left as no connects as agtl+ termination is provided on the processor silicon. however, see table 2-5 for details on agtl+ signals that do not include on-die termination. for middle agents, the on-die termination must be disabled, so the platform must ensure that unused agtl+ input signals which do not connect to end agents are connected to v tt via a pull-up resistor. unused active high inputs, s hould be connected through a resistor to ground (v ss ). unused outputs can be left unconnected, however this may interfere with some tap functions, complicate debug probing, and prevent boundary scan testing. a resistor must be used when tying bidirectional signals to power or ground. when tying any signal to power or ground, a resistor will also allow for system testability. resistor values should be within 20% of the impedance of the baseboard trace for front side bus signals. for unused agtl+ input or i/o signals, use pull-up resistors of the same value as the on-die termination resistors (r tt ). tap, asynchronous gtl+ inputs, and asynchronous gtl+ outputs do not include on-die termination. inputs and utilized outputs must be terminated on the baseboard. unused outputs may be terminated on the baseboard or left unconnected. note that leaving unused outputs unterminated may interfere with some tap functions, complicate debug probing, and prevent boundary scan testing. signal termination for these signal types is discussed in the itp700 debug port design guide (see section 1.2 ). all testhi[6:0] pins should be individually connected to v tt via a pull-up resistor which matches the nominal trace impeda nce. testhi[3:0] an d testhi[6:5] may be tied together and pulled up to v tt with a single resistor if desired. however, utilization of boundary scan test will not be functional if these pins are connected together. testhi4 must always be pulled up independently from the other testhi pins. for optimum noise margin, all pull-up resistor values used for testhi[6:0] pins should have a resistance value within 20 % of the impedance of the board transmission line traces . for example, if the nom inal trace impedance is 50 ? , then a value between 40 ? and 60 ? should be used. n/c (no connect) pins of the pro cessor are not utilized by the pro cessor. there is no connection from the pin to the die. these pins may perfor m functions in future processors intended for platforms using the 64-bit intel xeon processor with 2 mb l2 cache. 2.6 front side bus signal groups the front side bus signals have been combined into groups by buffer type. agtl+ input signals have differential input buffers, which use gtlref as a reference level. in this document, the term ?agtl+ input? refers to the agtl+ input group as well as the agtl+ i/o group when receiving. similarly, ?agtl+ output? refers to the agtl+ output group as well as the agtl+ i/o group when driving. agtl+ asynchronous outputs can become active anytime and include an active pmos pull-up transistor to assist during the fi rst clock of a low-to-high voltage transition.
datasheet 23 electrical specifications with the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. one set is for common clock signals whose timings are specified with respect to rising edge of bclk0 (ads#, hit#, hitm#, etc.) and the second set is for the source synchronous signals which are relative to their respec tive strobe lines (data and address) as well as rising edge of bclk0. asynchronous signals ar e still present (a20m#, ignne#, etc.) and can become active at any time during the clock cycle. table 2-4 identifies which signals are common clock, source synchronous and asynchronous. notes: 1. refer to section 4 for signal descriptions. 2. the 64-bit intel ? xeon? processor with 2 mb l2 cache only uses br0# and br1#. br2# and br3# must be terminated to v tt . for additional details regarding the br[3:0]# signals, see section 4 and section 7.1 . 3. the value of these pins during the active-to-inacti ve edge of reset# defines the processor configuration options. see section 7.1 for details. 4. these signals may be driven simult aneously by multiple agents (wired-or). table 2-5 outlines the signals which include on-die termination (r tt ) and lists signals which include additional on-die resistance (r l ). table 2-6 provides signal reference voltages. table 2-4. front side bus signal groups signal group type signals 1 agtl+ common clock input synchronous to bclk[1:0] bpri#, br[3:1]# 2,3 , defer#, reset#, rs[2:0]#, rsp#, trdy# agtl+ common clock i/o synchronous to bclk[1:0] ads#, ap[1:0]#, binit# 4 , bnr# 4 , bpm[5:0]#, br0# 2,3 , dbsy#, dp[3:0]#, drdy#, hit# 4 , hitm# 4 , lock#, mcerr# 4 agtl+ source synchronous i/o synchronous to assoc. strobe agtl+ strobe i/o synchronous to bclk[1:0] adstb[1:0]#, dstbp[3:0]#, dstbn[3:0]# agtl asynchronous output asynchronous ferr#/pbe#, ierr#, prochot# gtl+ asynchronous input asynchronous a20m#, forcepr#, ignne#, init# 3 , lint0/ intr, lint1/nmi, smi# 3 , slp#, stpclk# gtl+ asynchronous output asynchronous thermtrip# front side bus clock clock bclk1, bclk0 tap input synchronous to tck tck, tdi, tms, trst# tap output synchronous to tck tdo power/other power/other boot_select, bsel[1:0], comp[1:0], gtlref[3:0], odten, optimized/ compat#, pwrgood, reserved, sktocc#, slew_ctrl, smb_prt, test_bus, testhi[6:0], thermda, thermdc, v cc , v cca , v cciopll, v ccpll , vccsense, vid[5:0], v ss , v ssa , vsssense, v tt , vidpwrgd, vtten signals associated strobe req[4:0]#,a[16:3]# 3 adstb0# a[35:17]# 3 adstb1# d[15:0]#, dbi0# dstbp0#, dstbn0# d[31:16]#, dbi1# dstbp1#, dstbn1# d[47:32]#, dbi2# dstbp2#, dstbn2# d[63:48]#, dbi3# dstbp3#, dstbn3#
24 datasheet electrical specifications notes: 1. signals that do not have r tt , nor are actively driven to their high voltage level. 2. the termination for these signals is not r tt . the optimized/compat# and boot_select pins have a 500 - 5000 ? pull-up to v tt . notes: 1. these signals also have hysteresis added to the reference voltage. see table 2-13 for more information. 2.7 gtl+ asynchronous and agtl+ asynchronous signals the 64-bit intel xeon processor with 2 mb l2 cach e does not use cmos voltage levels on any signals that connect to the pr ocessor silicon. as a result, input signals such as a20m#, forcepr#, ignne#, init#, li nt0/intr, lint1/nmi, smi#, slp#, and stpclk# utilize gtl input buffers. legacy output thermtrip# u tilizes a gtl+ output bu ffers. all of these asynchronous gtl+ signals follow the same dc requirements as gtl+ signals, however the outputs are not driven high (during the logical 0- to-1 transition) by the processor. ferr#/pbe#, ierr#, and ignne# have now been defined as agtl+ asynchrnous signals as they include an active p-mos device. gtl+ asynchronous and agtl+ asynchronous signals do not have setup or hold time specifications in relation to bclk[1:0] . however, all of the gtl+ asynchronous and agtl+ asynchronous signals are required to be asserted/deasserted for at least six bclks in order for the processor to recognize them. see table 2-14 for the dc specifications for the asynchronous gtl+ signal groups. 2.8 test access port (tap) connection due to the voltage levels supported by other components in the test access port (tap) logic, it is recommended that the processor(s) be first in the tap chain and followed by any other components within the system. a translation buffer should be us ed to connect to the rest of the chain unless one table 2-5. signal description table signals with r tt a[35:3]#, ads#, adstb[1:0]#, ap[1:0]#, binit#, bnr#, boot_select 2 , bpri#, d[63:0]#, dbi[3:0]#, dbsy#, defer#, dp[3:0]#, drdy#, dstbn[3:0]#, dstbp[3:0]#, forcepr#, hit#, hitm#, lock#, mcerr#, optimized/compat# 2 , req[4:0]#, rs[2:0]#, rsp#, slew_ctrl, test_bus, trdy# signals with r l binit#, bnr#, hit#, hitm#, mcerr# table 2-6. signal reference voltages gtlref 0.5 * v tt a20m#, a[35:3]#, ads#, adstb[1:0]#, ap[1:0]#, binit#, bnr#, bpm[5:0]#, bpri#, br[3:0]#, d[63:0]#, dbi[3:0]#, dbsy#, defer#, dp[3:0]#, drdy#, dstbn[3:0]#, dstbp[3:0]#, forcepr#, hit#, hitm#, ignne#, init#, lint0/intr, lint1/ nmi, lock#, mcerr#, odten, reset#, req[4:0]#, rs[2:0]#, rsp#, slew_ctrl, slp#, smi#, stpclk#, trdy# boot_select, optimized/compat#, pwrgood 1 , tck 1 , tdi 1 , tms 1 , trst# 1 , vidpwrgd
datasheet 25 electrical specifications of the other components is capable of accepting an input of the appropriate voltage. similar considerations must be made for tck, tms, and trst#. two copies of each signal may be required with each driving a different voltage level. 2.9 mixing processors intel only supports and validates dual processor co nfigurations in which both processors operate with the same front side bus frequency, core fr equency, vid range, and have the same internal cache sizes. mixing components operating at differ ent internal clock frequencies is not supported and will not be validated by intel [note: proce ssors within a system must operate at the same frequency per bits [15:8] of the ia32_flex_brvid_sel msr; however this does not apply to frequency transitions initiated due to thermal events, enhanced intel speedstep technology transitions, or assertion of the forcepr# signal (see chapter 6 )]. not all operating systems can support dual processors with mixed frequencies. intel does not support or validate operation of processors with different cache si zes. mixing processors of differen t steppings but the same model (as per cpuid instruction) is supported. please see the 64-bit intel ? xeon? processor with 800 mhz system bus (1 mb and 2 mb l2 cache versions) specification update (see section 1.2 ) for the applicable mixed stepping table. details re garding the cpuid instruction are provided in the intel ? processor identification and the cpuid instruction application note. low-voltage (lv), mid-voltage (mv), and full power 64 -bit intel xeon processors with 2 mb l2 cache should not be mixed within a system. 2.10 absolute maximum and minimum ratings table 2-7 specifies absolute maximum and minimum ratings. within functional operation limits, functionality and long-term reliability can be expected. at conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long te rm reliability can be e xpected. if a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded de pending on exposure to conditions exceeding the functional operation condition limits. at conditions exceeding absolute maximum and mi nimum ratings, neither functionality nor long- term reliability can be expected. moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reli ability will be severely degraded. although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoi d high static voltage s or electric fields. table 2-7. absolute maximum and minimum ratings symbol parameter min max unit notes 1,2 v cc core voltage with respect to v ss -0.30 1.55 v v tt system bus termination voltage with respect to v ss -0.30 1.55 v t case processor case temperature see chapter 6 see chapter 6 c t storage storage temperature -40 85 c3,4
26 datasheet electrical specifications notes: 1. for functional operation, all proces sor electrical, signal quality, mechani cal and thermal specifications must be satisfied. 2. overshoot and undershoot voltage guidelines fo r input, output, and i/o signals are outlined in chapter 3 . excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. storage temperature is applicable to storage conditions only. in this scenar io, the processor must not receive a clock, and no pins can be connected to a voltage bias. storage within these limits will not affect the long- term reliability of the device. for functional operati on, please refer to the processor case temperature specifications. 4. this rating applies to the processor and does not include any tray or packaging. 2.11 processor dc specifications the processor dc specifications in this section are defined at th e processor core (pads) unless noted otherwise. see section 5.1 for the processor pin listings and chapter 4 for signal definitions. voltage and current specifi cations are detailed in table 2-8 . for platform power delivery planning refer to table 2-9 , which provides v cc static and transient toleran ces. this same information is presented graphically in figure 2-4 . bsel[1:0] and vid[5:0] si gnals are specified in table 2-11 . the dc specifications for the agtl+ signals are listed in table 2-12 . the dc specifications for the pwrgood input and tap signal group are listed in table 2-13 and the asynchronous gtl+ signal group is listed in table 2-14 . the vidpwrgd signal is detailed in table 2-15 . table 2-8 through table 2-15 list the dc specifications for th e processor and are valid only while meeting specifications for case temperature (t case as specified in chapter 6 ), clock frequency, and input voltages. care should be taken to read all notes associated with each parameter. ia32_flex_brvid_sel bit 18 is the platform re quirement bit (prb) that indicates that the processor has specific pl atform requirements. 2.11.1 flexible motherboard guidelines (fmb) the flexible motherboard (fmb) guidelines are estimates of the maximum values the 64-bit intel xeon processor with 2 mb l2 cache will have over certain time periods. the values are only estimates and actual specifications for future processors may differ. processors may or may not have specifications equal to the fmb value in the foreseeable future. system designers should meet the fmb values to ensure their systems will be compatible with future intel xeon processors.
datasheet 27 electrical specifications table 2-8. voltage and current specifications symbol parameter min typ max unit notes 1 vid range vid range for 64-bit intel ? xeon? processor with 2 mb l2 cache 1.2875 1.3875 v 2,3 vid range for 64-bit intel ? xeon? mv 3.20 ghz processor 1.2125 1.3875 v 2,3 vid range for 64-bit intel ? xeon? lv 3 ghz processor 1.0500 1.2000 v 2,3 v cc v cc for 64-bit intel xeon processors with 2 mb l2 cache with multiple vids (prb = 1) see table 2-9, figure 2-2 and figure 2-4 v 3,4,5,6,7 vid transition vid step size during a transition 12.5 mv 8 total allowable dc load line shift from vid steps 450 mv 9 v tt front side bus termination voltage (dc specification) 1.176 1.20 1.224 v 10 front side bus termination voltage (dc & ac specification) 1.140 1.20 1.260 v 10,11 i cc i cc for 64-bit intel xeon processor with 2 mb l2 cache and 64-bit intel xeon mv 3.20 ghz processor (prb = 1) 120 a 6,7 i cc for 64-bit intel xeon lv 3 ghz processor (prb = 0) 60 a 6,7 i tt front side bus end-agent v tt current 4.8 a 12 front side bus mid-agent v tt current 1.5 a 13 i cc_vcca i cc for pll power pins 120 ma 14 i cc_vcciopll i cc for pll power pins 100 ma 14 i cc_gtlref i cc for gtlref pins 200 a15 i sgnt i slp i cc stop grant for 64-bit intel xeon processor with 2 mb l2 cache and 64-bit intel xeon mv 3.20 ghz processor (prb = 1) 56 a 16 i cc stop grant for 64-bit intel xeon lv 3 ghz processor (prb = 0) 35.8 a 16 i tcc i cc tcc active i cc a17 i cc_tdc thermal design current for 64-bit intel xeon processor with 2 mb l2 cache and 64-bit intel xeon mv 3.20 ghz processor 105 a 18 thermal design current for 64-bit intel xeon lv 3 ghz processor 56 a 18
28 datasheet electrical specifications notes: 1. unless otherwise noted, all specificat ions in this table apply to all proces sors. these specifications are based on silicon characterization, however they ma y be updated as further data becomes available. 2. each processor is programmed with a maximum valid voltage identificati on (vid) values, which is set at manufacturing and can not be altered. individual maxi mum vid values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the vid range. please note this differs from the vid employed by the processor during a power management event (thermal monitor 2, enhanced intel speedstep ? technology, or enhanced halt power down state). 3. these voltages are targets only. a variable voltage s ource should exist on systems in the event that a different voltage is required. see section 2.4 for more information. 4. the voltage specification requirements are measured ac ross vias on the platform for the vccsense and vsssense pins close to the socket with a 100 mhz bandwidth oscilloscope , 1.5 pf maximum probe capacitance, and 1 m ? minimum impedance. the maximum length of ground wire on the probe should be less than 5 mm. ensure external noise from the system is not coupled in the scope probe. 5. refer to table 2-9 and corresponding figure 2-4 . the processor should not be subjected to any static v cc level that exceeds the v cc_max associated with any particular current. failure to adhere to this specification can shorten processor lifetime. 6. minimum v cc and maximum i cc are specified at the maximum processor case temperature (t case ) shown in table 6-1 . i cc_max is specified at the relative v cc_max point on the v cc load line. the processor is capable of drawing i cc_max for up to 10 ms. refer to figure 2-2 for further details on the average processor current draw over various time durations. 7. fmb is the flexible motherboard guideline. thes e guidelines are for estimation purposes only. see section 2.11.1 for further details on fmb guidelines. 8. this specification represents the v cc reduction due to each vid transition. see section 2.4 . 9. this specification refers to the potential total r eduction of the load line due to vid transitions below the specified vid. 10.v tt must be provided via a separate voltage source and must not be connected to v cc . this specification is measured at the pin. 11.baseboard bandwidth is limited to 20 mhz. 12.this specification refers to a single processor with r tt enabled. please note the end agent and middle agent may not require i tt (max) simultaneously. this parameter is based on design characterization and not tested. 13.this specification refers to a single processor with r tt disabled. please note the end agent and middle agent may not require i tt (max) simultaneously. 14.these specifications apply to the pl l power pins vcca, vcciopll, and vssa. see section 2.3.2 for details. these parameters are based on des ign characterization and are not tested. 15.this specification represents a total current for all gtlref pins. 16.the current specified is also for halt state. 17.the maximum instantaneous current the processor will draw while the ther mal control circuit is active as indicated by the assertion of the prochot# signal is the maximum i cc for the processor. 18.i cc_tdc (thermal design current) is the sustained (dc equival ent) current that the processor is capable of drawing indefinitely and should be used for the voltage regulator temperature assessment. the voltage regulator is responsible for monitoring its temperatur e and asserting the necessary signal to inform the processor of a thermal excursion. please see the applicable design guidelines fo r further details. the processor is capable of drawing icc_tdc indefinitely. refer to figure 2-2 for further details on the average processor craw over various time durations. this parameter is based on design characterization and is not tested.
datasheet 29 electrical specifications notes: 1. processor /voltage regulator thermal protection circui try should not trip for load currents greater than i cc_tdc . 2. not 100% tested. specified by design characterization. notes: 1. processor /voltage regulator thermal protection circui try should not trip for load currents greater than i cc_tdc . 2. not 100% tested. specified by design characterization. figure 2-2. 64-bit intel ? xeon? processor and 64-bit intel ? xeon? mv 3.20 ghz processor load current vs. time vrm 10.1 current 100 105 110 115 120 125 0.01 0.1 1 10 100 1000 time duration (s) sustained current (a) figure 2-3. 64-bit intel ? xeon? lv 3 ghz processor load current vs. time 54 56 58 60 62 0.01 0.1 1 10 100 1000 tim e duration (s) sustained current (a)
30 datasheet electrical specifications notes: 1. the v cc_min and v cc_max loadlines represent static and transient limits. please see section 2.11.2 for v cc overshoot specifications. 2. this table is intended to aid in reading discrete points on figure 2-4 . 3. the loadlines specify voltage limits at the die measured at the vccsense and vsssense pins. voltage regulation feedback for voltage regulator ci rcuits must be taken from processor v cc and v ss pins. refer to the enterprise voltage regulator down (evrd) 10.1 design guidelines for socket loadline guidelines and vr implementation. 4. the 64-bit intel xeon lv processor has a maximum i cc specification of 60 a. as a result, this processor will only use a portion of this table. table 2-9. v cc static and transient tolerance v cc_max v cc_typ v cc_min 0 vid - 0.000 vid - 0.020 vid - 0.040 5 vid - 0.006 vid - 0.026 vid - 0.046 10 vid - 0.013 vid - 0.033 vid - 0.052 15 vid - 0.019 vid - 0.039 vid - 0.059 20 vid - 0.025 vid - 0.045 vid - 0.065 25 vid - 0.031 vid - 0.051 vid - 0.071 30 vid - 0.038 vid - 0.058 vid - 0.077 35 vid - 0.044 vid - 0.064 vid - 0.084 40 vid - 0.050 vid - 0.070 vid - 0.090 45 vid - 0.056 vid - 0.076 vid - 0.096 50 vid - 0.063 vid - 0.083 vid - 0.103 55 vid - 0.069 vid - 0.089 vid - 0.109 60 vid - 0.075 vid - 0.095 vid - 0.115 65 vid - 0.081 vid - 0.101 vid - 0.121 70 vid - 0.087 vid - 0.108 vid - 0.128 75 vid - 0.094 vid - 0.114 vid - 0.134 80 vid - 0.100 vid - 0.120 vid - 0.140 85 vid - 0.106 vid - 0.126 vid - 0.146 90 vid - 0.113 vid - 0.133 vid - 0.153 95 vid - 0.119 vid - 0.139 vid - 0.159 100 vid - 0.125 vid - 0.145 vid - 0.165 105 vid - 0.131 vid - 0.151 vid - 0.171 110 vid - 0.138 vid - 0.158 vid - 0.178 voltage deviation from vid setting (v) 1,2,3,4 i cc
datasheet 31 electrical specifications notes: 1. the v cc_min and v cc_max loadlines represent static and transient limits. please see section 2.11.2 for v cc overshoot specifications. 2. the v cc_min and v cc_max loadlines are plots of the discrete point found in table 2-9 . 3. refer to table 2-8 for processor vid information. 4. the loadlines specify voltage limits at the die measured at the vccsense and vsssense pins. voltage regulation feedback for voltage regulator circ uits must be taken from processor v cc and v ss pins. refer to the enterprise voltage regulator down (evrd) 10.1 design guidelines for socket loadline guidelines and vr implementation. 5. the 64-bit intel xeon lv processor has a maximum i cc specification of 60 a. as a result, this processor will only use a portion of this table. 2.11.2 v cc overshoot specification the processor can tolerate short tr ansient overshoot events where v cc exceeds the vid voltage when transitioning from a high-to -low current load condition. th is overshoot cannot exceed vid + v os_max . (v os_max is the maximum allowable overshoot above vid). these specifications apply to the processor die voltage as measur ed across the vccsense and vsssense pins. figure 2-4. v cc static and transient tolerance vid - 0.000 vid - 0.020 vid - 0.040 vid - 0.060 vid - 0.080 vid - 0.100 vid - 0.120 vid - 0.140 vid - 0.160 vid - 0.180 vid - 0.200 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 icc [a] vcc [v] v cc typical v cc maximum v cc minimum table 2-10. v cc overshoot specifications symbol parameter min max units figure notes v os_max magnitude of v cc overshoot above vid 0.050 v 2-5 t os_max time duration of v cc overshoot above vid 25 s 2-5
32 datasheet electrical specifications notes: 1. v os is measured overshoot voltage. 2. t os is measured time duration above vid. 2.11.3 die voltage validation overshoot events from applicat ion testing on processor must meet the specifications in table 2-10 when measured across the vccsen se and vsssense pins. overshoot events that are < 10 ns in duration may be ignored. these measurement of pro cessor die level overshoot should be taken with a 100 mhz bandwidth limited oscilloscope. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. these parameters are based on design characterization and are not tested. 3. leakage to v ss with pin held at v tt . figure 2-5. v cc overshoot example waveform example overshoot waveform 0 5 10 15 20 25 time [us] voltage [v] vid - 0.000 vid + 0.050 v os t os t os : overshoot time above vid v os : overshoot above vid table 2-11. bsel[1:0] and vid[5:0] signal group dc specifications symbol parameter min typ max units notes 1 r on bsel[1:0] and vid[5:0] buffer on resistance n/a 60 ? 2 i ol maximum pin current n/a 8 ma 2 i lo output leakage current n/a 200 a2,3 r pull_up pull-up resistor 500 ? v tol voltage tolerance 0.95 * v tt v tt 1.05 * v tt v
datasheet 33 electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. the v tt represented in these specificat ions refers to instantaneous v tt . 3. v il is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 4. v ih is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 5. v ih and v oh may experience excursions above v tt . 6. refer to table 2-5 to determine which signals include addi tional on-die termi nation resistance (r l ). 7. leakage to v ss with pin held at v tt . 8. leakage to v tt with pin held at 300 mv. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. all outputs are open drain. 3. v hys represents the amount of hysteresis , nominally centered about 0.5 * v tt for all pwrgood and tap inputs. 4. the v tt represented in these specificat ions refers to instantaneous v tt . 5. pwrgood input and the tap signal group must meet system signal quality specification in chapter 2 . 6. the maximum output current is based on maximum current handling capability of the buffer and is not specified into the test load. table 2-12. agtl+ signal group dc specifications symbol parameter min max unit notes 1 v il input low voltage 0.0 gtlref - (0.10 * v tt )v 2,3 v ih input high voltage gtlref + (0.10 * v tt )v tt v 2,4,5 v oh output high voltage 0.90 * v tt v tt v2,5 i ol output low current n/a v tt / (0.50 * r tt_min + [r on_min || r l ]) ma 2,6 i li input leakage current n/a 200 a 7,8 i lo output leakage current n/a 200 a 7,8 r on buffer on resistance 7 11 ? table 2-13. pwrgood input and ta p signal group dc specifications symbol parameter min max unit notes 1,2,5 v hys input hysteresis 200 350 mv 3 v t+ input low to high threshold voltage 0.5 * (v tt + v hys_min ) 0.5 * (v tt + v hys_max )v 4 v t- input high to low threshold voltage 0.5 * (v tt - v hys_max ) 0.5 * (v tt - v hys_min )v 4 v oh output high voltage n/a v tt v4 i ol output low current 45 ma 6 i li input leakage current n/a 200 a i lo output leakage current n/a 200 a r on buffer on resistance 7 11 ?
34 datasheet electrical specifications notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. the v tt represented in these specifications refers to instantaneous v tt . 3. v il is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 4. v ih is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 5. v ih and v oh may experience excursions above v tt . 6. refer to table 2-5 to determine which signals in clude additional on-die termination resistance (r l ). 7. leakage to v ss with pin held at v tt . 8. leakage to v tt with pin held at 300 mv. table 2-14. gtl+ asynchronous and agtl+ asynchronous signal group dc specifications symbol parameter min max unit notes 1 v il input low voltage 0.0 gtlref - (0.10 * v tt )v2,3 v ih input high voltage gtlref + (0.10 * v tt )v tt v2,4,5 v oh output high voltage 0.90 * v tt v tt v2,5 i ol output low current n/a v tt / (0.50 * r tt_min + [r on_min || r l ]) ma 2,6 i li input leakage current n/a 200 a 7,8 i lo output leakage current n/a 200 a 7,8 r on buffer on resistance 7 11 ? table 2-15. vidpwrgd dc specifications symbol parameter min max unit notes 1 v il input low voltage 0.0 0.30 v v ih input high voltage 0.90 v tt v
datasheet 35 3 mechanical specifications the 64-bit intel xeon processor with 2 mb l2 ca che is packaged in flip chip micro pin grid array (fc-mpga4) package that interfaces to the baseboard via an mpga604 socket. the package consists of a processor core mounted on a substrate pin-carrier. an integrated heat spreader (ihs) is attach ed to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. figure 3-1 shows a sketch of the processor package components and how they are assembled together. refer to the mpga604 socket design guidelines for complete details on the mpga604 socket. the package components shown in figure 3-1 include the following: 1. integrated heat spreader (ihs) 2. processor die 3. substrate 4. pin side capacitors 5. package pin 6. die side capacitors note: this drawing is not to scale and is for reference only. the mpga604 socket is not shown. figure 3-1. processor package assembly sketch 1 3 5 4 6 2 1 3 5 4 6 2
36 datasheet mechanical specifications 3.1 package mechanical drawings the package mechanical drawings are shown in figure 3-2 and figure 3-3 . the drawings include dimensions necessary to design a thermal solution for the processor. these dimensions include: 1. package reference and tolerance dimensio ns (total height, length, width, etc.) 2. ihs parallelism and tilt 3. pin dimensions 4. top-side and back-side component keepout dimensions 5. reference datums all drawing dimensions are in mm [in.].
datasheet 37 mechanical specifications figure 3-2. processor package drawing (sheet 1 of 2)
38 datasheet mechanical specifications figure 3-3. processor package drawing (sheet 2 of 2)
datasheet 39 mechanical specifications 3.2 processor component keepout zones the processor may contain components on the substrate that define component keepout zone requirements. a thermal and mechanical solution design must not intrude into the required keepout zones. decoupling capacitors are typically mounted to either the topside or pin-side of the package substrate. see figure 3-3 for keepout zones. 3.3 package loading specifications table 3-1 provides dynamic and static load specifi cations for the processor package. these mechanical load limits should not be exceeded dur ing heatsink assembly, mechanical stress testing or standard drop and shipping conditions. the heatsink attach solutions must not include continuous stress onto the processor with the excep tion of a uniform load to maintain the heatsink- to-processor thermal interface. al so, any mechanical system or component testing should not exceed these limits. the processor package substrate should not be used as a mechanical reference or load-bearing surface for th ermal or mechanical solutions. notes: 1. these specifications apply to uni form compressive loading in a direction perpendicular to the ihs top surface. 2. this is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface. 3. these specifications are based on limited testing for design characteri zation. loading limits are for the package only and do not include the limits of the processor socket. 4. this specification applies for thermal ret ention solutions that allow baseboard deflection. 5. this specification applies either for thermal retention solutions that prevent baseboard deflection or for the intel enabled reference solution (cek). 6. dynamic loading is defined as an 11 ms duration av erage load superimposed on the static load requirement. 7. experimentally validated test condition used a heatsin k mass of 1 lbm (~0.45 kg) with 100 g acceleration measured at heatsink mass. the dynamic portion of th is specification in the product application can have flexibility in specific values, but the ultimate pr oduct of mass times acceleration should not exceed this validated dynamic load (1 lbm x 100 g = 100 lb). allo wable strain in the dynamic compressive load specification is in addition to the strain allowed in static loading. 8. transient loading is defined as a 2 second duration peak load superimposed on the static load requirement, representative of loads experienced by the package during heatsink installation. table 3-1. processor loading specifications parameter min max unit notes static compressive load 44 10 222 50 n lbf 1,2,3,4 44 10 288 65 n lbf 1,2,3,5 dynamic compressive load na na 222 n + 0.45 kg *100 g 50 lbf (static) + 1 lbm * 100 g n lbf 1,3,4,6,7 na na 288 n + 0.45 kg * 100 g 65 lbf (static) + 1 lbm * 100 g n lbf 1,3,5,6,7 transient na 445 100 n lbf 1,3,8
40 datasheet mechanical specifications 3.4 package handling guidelines table 3-2 includes a list of guidelines on a package handling in terms of recommended maximum loading on the processor ihs relative to a fixed substrate. these package handling loads may be experienced during heatsink removal. notes: 1. a shear load is defined as a load applied to the ih s in a direction parallel to the ihs top surface. 2. a tensile load is defined as a pul ling load applied to the ihs in a direction normal to the ihs surface. 3. a torque load is defined as a twisting load applied to th e ihs in an axis of rotation normal to the ihs top surface. 4. these guidelines are based on limited testing for des ign characterization and inci dental applications (one time only). 5. handling guidelines are for the package only and do not include the limits of the processor socket. 3.5 package insertion specifications the processor can be inserted and removed 15 times from an mpga604 socket, which meets the criteria outlined in the mpga604 socket design guidelines . 3.6 processor mass specifications the typical mass of the 64-bit in tel xeon processor with 2 mb l2 cache is 25 grams [0.88 oz.]. this mass [weight] includes all components which make up the entire processor product. 3.7 processor materials the processor is assembled from several componen ts. the basic material properties are described in table 3-3 . table 3-2. package handling guidelines parameter maximum recommended notes shear 356 n 80 lbf 1,4,5 tensile 156 n 35 lbf 2,4,5 torque 8 n-m 70 lbf-in 3,4,5 table 3-3. processor materials component material integrated heat spreader (ihs) nickel over copper substrate fiber-reinforced resin substrate pins gold over nickel
datasheet 41 mechanical specifications 3.8 processor markings figure 3-4 shows the topside markings and figure 3-5 shows the bottom-side markings on the processor. these diagrams are to aid in the identification of the processor. notes: 1. all characters will be in upper case. 2. drawing is not to scale. notes: 3. all characters will be in upper case. 4. drawing is not to scale. figure 3-4. processor top-side markings (example) processor name i(m ) ? ?04 2d matrix includes atpo and serial number (front end mark) pin 1 indicator atpo serial number processor name i(m ) ? ?04 2d matrix includes atpo and serial number (front end mark) pin 1 indicator atpo serial number figure 3-5. processor bottom-side markings (example) 4000dp/2mb/800/1.350v sl6ny costa rica c0096109-0021 speed / cache / bus / voltage s-spec country of assy fpo ? serial # (13 characters) pin field cavity with components text line1 text line2 text line3 pin 1 indicator 4000dp/2mb/800/1.350v sl6ny costa rica c0096109-0021 speed / cache / bus / voltage s-spec country of assy fpo ? serial # (13 characters) pin field cavity with components text line1 text line2 text line3 pin 1 indicator
42 datasheet mechanical specifications 3.9 processor pin-out coordinates figure 3-6 and figure 3-7 show the top and bottom view of the processor pin coordinates, respectively. the coordinates are referred to th roughout the document to identify processor pins. figure 3-6. processor pin-out coordinates, top view vcc/vss address data vcc/vss clocks common clock common clock async / jtag irwindale processor top view = signal = power = ground = reserved/no connect a c e g j l n r u w aa ac ae b d f h k m p t v y ab ad 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 1 = gtlref a c e g j l n r u w aa ac ae b d f h k m p t v y ab ad 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 (800 mhz) = v tt i i 64-bit intel? xeon? processor with 2 mb l2 cache (top view)
datasheet 43 mechanical specifications figure 3-7. processor pin-out coordinates, bottom view vcc/vss address data vcc/vss clocks common clock common clock async / jtag irwindale processor bottom view = signal = power = ground = reserved/no connect a c e g j l n r u w aa ac ae b d f h k m p t v y ab ad 3 5 7 9 11 13 15 17 19 21 23 25 27 29 1 31 = gtlref a c e g j l n r u w aa ac ae b d f h k m p t v y ab ad 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 (800 mhz) = v tt 64-bit intel? xeon? processor with 2 mb l2 cache (bottom view)
44 datasheet mechanical specifications
datasheet 45 4 signal definitions 4.1 signal definitions table 4-1. signal definitions (sheet 1 of 10) name type description notes a[35:3]# i/o a[35:3]# (address) define a 2 36 -byte physical memory address space. in sub-phase 1 of the address phase, these pins transmit the address of a transaction. in sub-phase 2, these pins transmit transaction type information. these signals must connec t the appropriate pins of all agents on the front side bus. a[35:3]# are protected by parity signals ap[1:0]#. a[35:3]# are source synchronous signals and are latched into the receiving buffers by adstb[1:0]#. on the active-to-inactive transition of reset#, the processors sample a subset of the a[35:3]# pins to deter mine their power-on configuration. see section 7.1 . 4 a20m# i if a20m# (address-20 mask) is assert ed, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap-around at the 1 mb boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. 3 ads# i/o ads# (address strobe) is asserted to indicate the validity of the transaction address on the a[35:3]# pins. all bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. this signal must c onnect the appropriate pins on all (800 mhz) front side bus agents. 4 adstb[1:0]# i/o address strobes are used to latch a[35:3]# and req[4:0]# on their rising and falling edge. strobes are associ ated with signals as shown below. 4 ap[1:0]# i/o ap[1:0]# (address parity) are driven by the request initiator along with ads#, a[35:3]#, and the transaction type on the req[4:0]# pins. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# should connect the appropriate pins of all system bus agent s. the following table defines the coverage model of these signals. 4 request signals subphase 1 subphase 2 a[35:24]# ap0# ap1# a[23:3]# ap1# ap0# req[4:0]# ap1# ap0# signals associated strobes req[4:0]#, a[16:3]# adstb0# a[35:17]# adstb1#
46 datasheet signal definitions bclk[1:0] i the differential bus clock pair bclk [1:0] determines the front side bus frequency. all processor front side bus agents must receive these signals to drive their outputs and latch their inputs. all external timing parameters are spec ified with respect to the rising edge of bclk0 crossing v cross . 4 binit# i/o binit# (bus initialization) may be observed and driven by all processor front side bus agents and if used, must connect the appropriate pins of all such agents. if the binit# driver is enabled during power on configuration, binit# is asserted to signal any bus condition that prevents reliable future information. if binit# observation is enabled during power-on configuration (see figure 7.1 ) and binit# is sampled asserted, symmetric agents reset their bus lock# activity and bus request ar bitration state machines. the bus agents do not reset their i/o queue (ioq) and transaction tracking state machines upon observation of binit# assertion. once the binit# assertion has been observed, the bus agents will re-arbitrate for the front side bus and attempt completion of their bus queue and ioq entries. if binit# observation is disabled duri ng power-on configuration, a central agent may handle an assertion of binit# as appropriate to the error handling architecture of the system. since multiple agents may drive this signal at the same time, binit# is a wired-or signal which must connect t he appropriate pins of all processor front side bus agents. in order to avoi d wired-or glitches associated with simultaneous edge transitions driven by multiple drivers, binit# is activated on specific clock edges and sampled on specific clock edges 4 bnr# i/o bnr# (block next request) is used to assert a bus stall by any bus agent who is unable to accept new bus tr ansactions. during a bus stall, the current bus owner cannot issue any new transactions. since multiple agents might need to request a bus stall at the same time, bnr# is a wired-or signal which mu st connect the appropriate pins of all processor front side bus agents. in or der to avoid wired-or glitches associated with simultaneous edge transiti ons driven by multiple drivers, bnr# is activated on specific cloc k edges and sampled on specific clock edges. 4 boot_ select i the boot_select input informs the processor whether the platform supports the 64-bit intel xeon processor with 2 mb l2 cache. the processor will not operate if this signal is low. this input has a weak pull-up to v tt . bpm[5:0]# i/o bpm[5:0]# (breakpoint monitor) ar e breakpoint and performance monitor signals. they are outputs from the proc essor which indicate the status of breakpoints and programmable counter s used for monitoring processor performance. bpm[5:0]# should connect the appropriate pins of all front side bus agents. bpm4# provides prdy# (probe ready) functionality for the tap port. prdy# is a processor output used by debug tools to determine processor debug readiness. bpm5# provides preq# (probe request) functionality for the tap port. preq# is used by debug tools to request debug operation of the processors. bpm[5:4]# must be bussed to all bus agents. please refer to the appropriate platform design guidelines for more detailed information. these signals do not have on-die termination and must be terminated at the end agent. 3 table 4-1. signal defi nitions (sheet 2 of 10) name type description notes
datasheet 47 signal definitions bpri# i bpri# (bus priority request) is used to arbitrate for ownership of the processor front side bus. it must c onnect the appropriate pins of all processor front side bus agents. observ ing bpri# active (as asserted by the priority agent) causes all other agen ts to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then releases the bus by deasserting bpri#. 4 br0# br[1:3]# 1 i/o i br[3:0]# (bus request) drive the breq[3:0]# signals in the system. the breq[3:0]# signals are interconnecte d in a rotating manner to individual processor pins. the tables below provide the rotating interconnect between the processor and bus signals for 2-way systems. during power-on configuration, the central agent must assert the br0# bus signal. all symmetric agents sample thei r br[3:0]# pins on the active-to- inactive transition of reset#. the pin which the agent samples asserted determines it?s agent id. these signals do not have on-die termination and must be terminated at the end agent. 1,4 bsel[1:0] o the bclk[1:0] frequency select signals bsel[1:0] are used to select the processor input clock frequency. table defines the possible combinations of the signals and the frequency associated with each combination. the required frequency is determined by the processors, chipset, and clock synthesizer. all front side bus agents must operate at the same frequency. the 64-bit intel xeon processor with 2 mb l2 cache currently operates at a 800 mhz front side bus frequency (200 mhz bclk[1:0] frequency). for more information about these pins, including termination recommendations, refer to the appropr iate platform design guideline. comp[1:0] i comp[1:0] must be terminated to v ss on the baseboard using precision resistors. these inputs configure the gt l+ drivers of the processor. refer to the appropriate platform design guidelines for implementation details. table 4-1. signal definitions (sheet 3 of 10) name type description notes br[1:0]# signals rotating interconnect, 2-way system br2# and br3# must not be utilized in 2-way platform designs. however, they must still be terminated. bus signal agent 0 pins agent 1 pins breq0# br0# br1# breq1# br1# br0#
48 datasheet signal definitions d[63:0]# i/o d[63:0]# (data) are the data signals. these signals provide a 64-bit data path between the processor front side bus agents, and must connect the appropriate pins on all such agents. the data driver asserts drdy# to indicate a valid data transfer. d[63:0]# are quad-pumped signals, and will thus be driven four times in a common clock period. d[63:0]# are latched off the falling edge of both dstbp[3:0]# and dstbn[3:0]#. each group of 16 data signals correspond to a pair of one dstbp# and one dstbn#. the following table shows the grouping of data signals to strobes and dbi#. furthermore, the dbi# pins determine the polarity of the data signals. each group of 16 data signals corresponds to one dbi# signal. when the dbi# signal is active, the corresponding data group is inverted and therefore sampled active high. 4 dbi[3:0]# i/o dbi[3:0]# are source synchronous and indi cate the polarity of the d[63:0]# signals. the dbi[3:0]# signals are ac tivated when the data on the data bus is inverted. if more than half the dat a bits, within a 16-bit group, would have been asserted electronically low, the bus agent may invert the data bus signals for that particular s ub-phase for that 16-bit group. 4 dbsy# i/o dbsy# (data bus busy) is asserted by the agent responsible for driving data on the processor front side bus to i ndicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate pins on all processor front side bus agents. 4 defer# i defer# is asserted by an agent to i ndicate that a transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addressed memory or i/o agent. this signal must connect the appropriate pins of all processor front side bus agents. 4 dp[3:0]# i/o dp[3:0]# (data parity) provide parity protection for the d[63:0]# signals. they are driven by the agent responsible for driving d[63:0]#, and must connect the appropriate pins of all processor front side bus agents. 4 drdy# i/o drdy# (data ready) is asserted by t he data driver on each data transfer, indicating valid data on the data bus . in a multi-common clock data transfer, drdy# may be deasserted to inse rt idle clocks. this signal must connect the appropriate pins of all processor front side bus agents. 4 table 4-1. signal defi nitions (sheet 4 of 10) name type description notes data group dstbn#/ dstbp# dbi# d[15:0]# 0 0 d[31:16]# 1 1 d[47:32]# 2 2 d[63:48]# 3 3 dbi[3:0] assignment to data bus bus signal data bus signals dbi0# d[15:0]# dbi1# d[31:16]# dbi2# d[47:32]# dbi3# d[63:48]#
datasheet 49 signal definitions dstbn[3:0]# i/o data strobe used to latch in d[63:0]#. 4 dstbp[3:0]# i/o data strobe used to latch in d[63:0]#. 4 ferr#/pbe# o ferr#/pbe# (floating-point error/pendi ng break event) is a multiplexed signal and its meaning is qualified by stpclk#. when stpclk# is not asserted, ferr#/pbe# indicates a float ing-point error and will be asserted when the processor detects an unmas ked floating-point error. when stpclk# is not asserted, ferr#/pbe# is similar to the error# signal on the intel 387 coprocessor, and is incl uded for compatibility with systems using ms-dos*-type floating-point error reporting. when stpclk# is asserted, an assertion of ferr#/pbe# indicates that the processor has a pending break event waiting for service. the assertion of ferr#/pbe# indicates that the processor should be returned to the normal state. for additional information on the pending br eak event functionality, including the identification of support of the f eature and enable/disable information, refer to vol. 3 of the ia-32 intel ? architecture software developer?s manual and the intel processor identification and the cpuid instruction application note. this signal does not have on-die termination and must be terminated at the end agent. 3 forcepr# i the forcepr# input can be used by the platform to force the processor to activate the thermal control circui t (tcc). the tcc will remain active until the system deasserts forcepr#. gtlref i gtlref determines the signal reference level for gtl+ input pins. gtlref is used by the gtl+ receivers to determine if a signal is a logical 0 or a logical 1. hit# hitm# i/o i/o hit# (snoop hit) and hitm# (hit m odified) convey transaction snoop operation results. any front side bus agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. since multiple agents may deliver snoop results at the same time, hit# and hitm# are wired-or signals which must connect the appropriate pins of all processor front side bus agents. in order to avoid wired-or glitches associated with simultaneous edge transit ions driven by multiple drivers, hit# and hitm# are activated on specific clock edges and sampled on specific clock edges. 4 table 4-1. signal definitions (sheet 5 of 10) name type description notes signals associated strobes d[15:0]#, dbi0# dstbn0# d[31:16]#, dbi1# dstbn1# d[47:32]#, dbi2# dstbn2# d[63:48]#, dbi3# dstbn3# signals associated strobes d[15:0]#, dbi0# dstbp0# d[31:16]#, dbi1# dstbp1# d[47:32]#, dbi2# dstbp2# d[63:48]#, dbi3# dstbp3#
50 datasheet signal definitions ierr# o ierr# (internal error) is asserted by a processor as the result of an internal error. assertion of ie rr# is usually accompanied by a shutdown transaction on the processo r front side bus. this transaction may optionally be converted to an exte rnal error signal (e.g., nmi) by system core logic. the processor will keep ierr# asserted until the assertion of reset#. this signal does not have on-die termination and must be terminated at the end agent. 3 ignne# i ignne# (ignore numeric error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. if ignne# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating- point instruction caused an error. ig nne# has no effect when the ne bit in control register 0 (cr0) is set. ignne# is an asynchronous signal. howeve r, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corres ponding i/o write bus transaction. 3 init# i init# (initialization), when asserted, resets integer registers inside all processors without affecting their inter nal caches or floating-point registers. each processor then begins execution at the power-on reset vector configured during power-on configurat ion. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous signal and must connect the appropriate pi ns of all processor front side bus agents. if init# is sampled active on the active to inactive transition of reset#, then the processor executes its built-in self-test (bist). 3 lint[1:0] i lint[1:0] (local apic interrupt) must connect the appropriate pins of all front side bus agents. when the apic fu nctionality is disabled, the lint0/ intr signal becomes intr, a maskable interrupt request signal, and lint1/nmi becomes nmi, a nonmaskable interrupt. intr and nmi are backward compatible with the signals of those names on the pentium ? processor. both si gnals are asynchronous. these signals must be software configured via bios programming of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. 3 lock# i/o lock# indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of all processor front side bus agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transac tion to the end of the last transaction. when the priority agent asserts bpri# to arbitrate for ownership of the processor front side bus, it will wait until it observes lock# deasserted. this enables symmetric agents to reta in ownership of the processor front side bus throughout the bus locked operation and ensure the atomicity of lock. 4 table 4-1. signal defi nitions (sheet 6 of 10) name type description notes
datasheet 51 signal definitions mcerr# i/o mcerr# (machine check error) is asserted to indicate an unrecoverable error without a bus protocol violation. it may be driven by all processor front side bus agents. mcerr# assertion conditions are configurable at a system level. assertion options are defined by the following options: ? enabled or disabled. ? asserted, if configured, for internal errors along with ierr#. ? asserted, if configured, by the request initiator of a bus transaction after it observes an error. ? asserted by any bus agent when it observes an error in a bus transaction. for more details regarding machine check architecture, refer to the ia-32 intel? architecture software developer?s manual, volume 3: system programming guide . since multiple agents may drive this signal at the same time, mcerr# is a wired-or signal which must connect the appropriate pins of all processor front side bus agents. in order to avoi d wired-or glitches associated with simultaneous edge transitions driven by multiple drivers, mcerr# is activated on specific clock edges and sampled on specific clock edges. odten i odten (on-die termination enable) should be connected to v tt to enable on-die termination for end bus agents. for middle bus agents, pull this signal down via a resistor to ground to disable on-die termination. whenever odten is high, on-die termin ation will be active, regardless of other states of the bus. optimized/ compat# i this is an input pin to the processor to determine if the processor is in an optimized platform or a compatible pl atform. this signal does includes a weak on-die pull-up to v tt . prochot# o prochot# (processor hot) will go active when the processor temperature monitoring sensor detects that the processor die temperature has reached its factory configured trip point. this indicates that the processor thermal control circuit (t cc) has been activated, if enabled. see section 6.2.4 for more details. pwrgood i pwrgood (power good) is an input. t he processor requires this signal to be a clean indication that all proc essor clocks and power supplies are stable and within their specifications. ?clean? implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. the signal must then tr ansition monotonically to a high state. pwrgood can be driven inactive at any time, but clocks and power must again be stable before a subsequent ri sing edge of pwrgood. it must also meet the minimum pulse width specification in table 2-14 , and be followed by a 1-10 ms reset# pulse. the pwrgood signal must be supplied to the processor; it is used to protect internal circuits against vo ltage sequencing issues. it should be driven high throughout boundary scan operation. 3 req[4:0]# i/o req[4:0]# (request command) must connect the appropriate pins of all processor front side bus agents. they are asserted by the current bus owner to define the currently active transaction type. these signals are source synchronous to adstb[1:0]#. refer to the ap[1:0]# signal description for details on pari ty checking of these signals. 4 table 4-1. signal definitions (sheet 7 of 10) name type description notes
52 datasheet signal definitions reset# i asserting the reset# signal resets al l processors to known states and invalidates their internal caches wit hout writing back any of their contents. for a power-on reset, reset# must stay active for at least 1 ms after v cc and bclk have reached their proper s pecifications. on observing active reset#, all front side bus agents will deassert their outputs within two clocks. reset# must not be kept asserted for more than 10 ms while pwrgood is asserted. a number of bus signals are sampled at the active-to-inactive transition of reset# for power-on configuration. these configuration options are described in the section 7.1 . this signal does not have on-die termination and must be terminated at the end agent. 4 rs[2:0]# i rs[2:0]# (response status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor front side bus agents. 4 rsp# i rsp# (response parity) is driven by the response agent (the agent responsible for completion of the curr ent transaction) during assertion of rs[2:0]#, the signals for which rsp# pr ovides parity protection. it must connect to the appropriate pins of all processor front side bus agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. while rs[2:0]# = 000, rsp# is also high, since this indica tes it is not being driven by any agent guaranteeing correct parity. 4 sktocc# o sktocc# (socket occupied) will be pulled to ground by the processor to indicate that the processor is pr esent. there is no connection to the processor silicon for this signal. slew_ctrl i the front side bus slew rate control input, slew_ctrl, is used to establish distinct edge rates for middle and end agents. slp# i slp# (sleep), when asserted in stop-grant state, causes processors to enter the sleep state. during sleep state, the processor stops providing internal clock signals to all units, leaving only the phase-lock loop (pll) still operating. processors in this state will not recognize snoops or interrupts. the processor will only re cognize the assertion of the reset# signal, deassertion of slp#, and removal of the bclk input while in sleep state. if slp# is deasserted, the processor exits sleep state and returns to stop-grant state, restarting its internal clock signals to the bus and processor core units. 3 smb_prt o the smbus present (smb_prt) pin is defined to inform the platform if the installed processor includes smbus components such as the integrated thermal sensor and the processor inform ation rom (pirom). this pin is tied to vss by the processor if these features are not present. platforms utilizing this pin should use a pull up resistor to the appropriate voltage level for the logic tied to this pin. because this pin does not connect to the processor silicon, any platform voltage and termination value is acceptable. smi# i smi# (system management interrupt) is asserted asynchronously by system logic. on acc epting a system management interrupt, processors save the current state and enter system management mode (smm). an smi acknowledge transaction is issued , and the processor begins program execution from the smm handler. if smi# is asserted during the deassertion of reset# the processor will tri- state its outputs. 3 table 4-1. signal defi nitions (sheet 8 of 10) name type description notes
datasheet 53 signal definitions stpclk# i stpclk# (stop clock), when asserted, causes processors to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing inter nal clock signals to all processor core units except the front side bus and api c units. the processor continues to snoop bus transactions and service inte rrupts while in stop-grant state. when stpclk# is deasserted, the processo r restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. 3 tck i tck (test clock) provides the clock input for the processor test bus (also known as the test access port). tdi i tdi (test data in) transfers serial test data into the processor. tdi provides the serial input needed for jt ag specification support. tdo o tdo (test data out) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. test_bus i must be connected to all other processor test_bus signals in the system. testhi[6:0] i all testhi inputs should be individually connected to v tt via a pull-up resistor which matches the trace impedance. testhi[3:0] and testhi[6:5] may all be tied together and pulled up to v tt with a single resistor if desired. however, util ization of boundary scan test will not be functional if these pins are connect ed together. testhi4 must always be pulled up independently from the other testhi pins. for optimum noise margin, all pull-up resistor values used for testhi[6:0] should have a resistance value within 20% of the impedance of the baseboard transmission line traces. for exam ple, if the trace impedance is 50 ? , than a value between 40 ? and 60 ? should be used. thermda other thermal diode anode. see section 6.2.8 . thermdc other thermal diode cathode. see section 6.2.8 . thermtrip# o assertion of thermtrip# (thermal trip) indicates the processor junction temperature has reached a temperature beyond which permanent silicon damage may occur. measurement of the temperature is accomplished through an internal thermal sensor. upon assertion of thermtrip#, the processor will shut off its internal cl ocks (thus halting program execution) in an attempt to reduce the processor junction temperature. to protect the processor its core voltage (v cc ) must be removed following the assertion of thermtrip#. driving of the thermtrip# signals is enabled within 10 ms of the assertion of pwrgood and is dis abled on de-assertion of pwrgood. once activated, thermtrip# remains latched until pwrgood is de- asserted. while the de-assertion of the pwrgood signal will de-assert thermtrip#, if the processor?s juncti on temperature remains at or above the trip level, thermtrip# will again be asserted within 10 ms of the assertion of pwrgood. 2 tms i tms (test mode select) is a jtag s pecification support signal used by debug tools. this signal does not have on-die termination and must be terminated at the end agent. trdy# i trdy# (target ready) is asserted by the ta rget to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate pins of all front side bus agents. trst# i trst# (test reset) resets the test access port (tap) logic. trst# must be driven low during power on reset. v cca i v cca provides isolated power for the analog portion of the internal processor core pll?s. refer to the appropriate platform design guidelines for complete implementation details. table 4-1. signal definitions (sheet 9 of 10) name type description notes
54 datasheet signal definitions notes: 1. the 64-bit intel ? xeon? processor with 2 mb l2 cache only supports br0# and br1#. however, platforms must terminate br2# and br3# to v tt . 2. for this pin on the 64-bit intel xeon processor wi th 2 mb l2 cache, the maximum number of symmetric agents is one. maximum number of central agents is zero. 3. for this pin on the 64-bit intel xeon processor wi th 2 mb l2 cache, the maximum number of symmetric agents is two. maximum number of central agents is zero. 4. for this pin on the 64-bit intel xeon processor wi th 2 mb l2 cache, the maximum number of symmetric agents is two. maximum number of central agents is one. v cciopll i v cciopll provides isolated power for digital portion of the internal processor core pll?s. refer to the appropriate platform design guidelines for complete implementation details. v ccpll i the on-die pll filter solution will not be implemented on this platform. the v ccpll input should be left unconnected. vccsense vsssense o vccsense and vsssense provide an isolated, low impedance connection to the processor core power and ground. they can be used to sense or measure power n ear the silicon with little noise. vid[5:0] o vid[5:0] (voltage id) pins are used to support automatic selection of power supply voltages (v cc ). these are open drain signals that are driven by the processor and must be pulled up through a resistor. conversely, the vr output must be disabled prior to the voltage supply for these pins becomes invalid. the vid pins are needed to s upport processor voltage specification variations. see ta b l e 2 - 3 for definitions of these pins. the vr must supply the voltage that is requested by these pins, or disable itself. vidpwrgd i the processor requires this input to determine that the supply voltage for bsel[1:0] and vid[5:0] is stable and within specification. v ssa i v ssa provides an isolated, internal ground for internal pll?s. do not connect directly to ground. this pin is to be connected to v cca and v cciopll through a discrete filter circuit. v tt p the front side bus termination voltage input pins. refer to ta b l e 2 - 8 for further details. vtten o the vtten can be used as an output enabl e for the vtt regulator in the event an incompatible processor is inserted into the platform. there is no connection to the processo r silicon for this signal and it must be pulled up through a resistor. refer to the appropr iate platform design guidelines for implementation details. table 4-1. signal defini tions (sheet 10 of 10) name type description notes
datasheet 55 5 pin listing 5.1 64-bit intel ? xeon? processor with 2 mb l2 cache pin assignments this section provides sorted pin lists in table 5-1 and table 5-2 . table 5-1 is a listing of all processor pins ordered alphabetically by pin name. table 5-2 is a listing of all processor pins ordered by pin number. 5.1.1 pin listing by pin name table 5-1. pin listing by pin name pin name pin no. signal buffer type direction a3# a22 source sync input/output a4# a20 source sync input/output a5# b18 source sync input/output a6# c18 source sync input/output a7# a19 source sync input/output a8# c17 source sync input/output a9# d17 source sync input/output a10# a13 source sync input/output a11# b16 source sync input/output a12# b14 source sync input/output a13# b13 source sync input/output a14# a12 source sync input/output a15# c15 source sync input/output a16# c14 source sync input/output a17# d16 source sync input/output a18# d15 source sync input/output a19# f15 source sync input/output a20# a10 source sync input/output a21# b10 source sync input/output a22# b11 source sync input/output a23# c12 source sync input/output a24# e14 source sync input/output a25# d13 source sync input/output a26# a9 source sync input/output a27# b8 source sync input/output a28# e13 source sync input/output a29# d12 source sync input/output a30# c11 source sync input/output a31# b7 source sync input/output a32# a6 source sync input/output a33# a7 source sync input/output a34# c9 source sync input/output a35# c8 source sync input/output a20m# f27 async gtl+ input ads# d19 common clk input/output adstb0# f17 source sync input/output adstb1# f14 source sync input/output ap0# e10 common clk input/output ap1# d9 common clk input/output bclk0 y4 sys bus clk input bclk1 w5 sys bus clk input binit# f11 common clk input/output bnr# f20 common clk input/output boot_select g7 power/other input bpm0# f6 common clk input/output bpm1# f8 common clk input/output bpm2# e7 common clk input/output bpm3# f5 common clk input/output bpm4# e8 common clk input/output bpm5# e4 common clk input/output bpri# d23 common clk input br0# d20 common clk input/output br1# f12 common clk input br2# 1 e11 common clk input br3# 1 d10 common clk input bsel0 aa3 power/other output table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction
pin listing 56 datasheet bsel1 ab3 power/other output comp0 ad16 power/other input comp1 e16 power/other input d0# y26 source sync input/output d1# aa27 source sync input/output d2# y24 source sync input/output d3# aa25 source sync input/output d4# ad27 source sync input/output d5# y23 source sync input/output d6# aa24 source sync input/output d7# ab26 source sync input/output d8# ab25 source sync input/output d9# ab23 source sync input/output d10# aa22 source sync input/output d11# aa21 source sync input/output d12# ab20 source sync input/output d13# ab22 source sync input/output d14# ab19 source sync input/output d15# aa19 source sync input/output d16# ae26 source sync input/output d17# ac26 source sync input/output d18# ad25 source sync input/output d19# ae25 source sync input/output d20# ac24 source sync input/output d21# ad24 source sync input/output d22# ae23 source sync input/output d23# ac23 source sync input/output d24# aa18 source sync input/output d25# ac20 source sync input/output d26# ac21 source sync input/output d27# ae22 source sync input/output d28# ae20 source sync input/output d29# ad21 source sync input/output d30# ad19 source sync input/output d31# ab17 source sync input/output d32# ab16 source sync input/output d33# aa16 source sync input/output d34# ac17 source sync input/output d35# ae13 source sync input/output d36# ad18 source sync input/output d37# ab15 source sync input/output table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction d38# ad13 source sync input/output d39# ad14 source sync input/output d40# ad11 source sync input/output d41# ac12 source sync input/output d42# ae10 source sync input/output d43# ac11 source sync input/output d44# ae9 source sync input/output d45# ad10 source sync input/output d46# ad8 source sync input/output d47# ac9 source sync input/output d48# aa13 source sync input/output d49# aa14 source sync input/output d50# ac14 source sync input/output d51# ab12 source sync input/output d52# ab13 source sync input/output d53# aa11 source sync input/output d54# aa10 source sync input/output d55# ab10 source sync input/output d56# ac8 source sync input/output d57# ad7 source sync input/output d58# ae7 source sync input/output d59# ac6 source sync input/output d60# ac5 source sync input/output d61# aa8 source sync input/output d62# y9 source sync input/output d63# ab6 source sync input/output dbsy# f18 common clk input/output defer# c23 common clk input dbi0# ac27 source sync input/output dbi1# ad22 source sync input/output dbi2# ae12 source sync input/output dbi3# ab9 source sync input/output dp0# ac18 common clk input/output dp1# ae19 common clk input/output dp2# ac15 common clk input/output dp3# ae17 common clk input/output drdy# e18 common clk input/output dstbn0# y21 source sync input/output dstbn1# y18 source sync input/output dstbn2# y15 source sync input/output dstbn3# y12 source sync input/output table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction
pin listing datasheet 57 dstbp0# y20 source sync input/output dstbp1# y17 source sync input/output dstbp2# y14 source sync input/output dstbp3# y11 source sync input/output ferr#/pbe# e27 async gtl+ output forcepr# a15 async gtl+ input gtlref w23 power/other input gtlref w9 power/other input gtlref f23 power/other input gtlref f9 power/other input hit# e22 common clk input/output hitm# a23 common clk input/output ierr# e5 async gtl+ output ignne# c26 async gtl+ input init# d6 async gtl+ input lint0/intr b24 async gtl+ input lint1/nmi g23 async gtl+ input lock# a17 common clk input/output mcerr# d7 common clk input/output n/c y29 n/c n/c n/c aa28 n/c n/c n/c aa29 n/c n/c n/c ab28 n/c n/c n/c ab29 n/c n/c n/c ac28 n/c n/c n/c ac29 n/c n/c n/c ad28 n/c n/c n/c ad29 n/c n/c n/c ae30 n/c n/c odten b5 power/other input optimized/ compat# c1 power/other input prochot# b25 async gtl+ output pwrgood ab7 async gtl+ input req0# b19 source sync input/output req1# b21 source sync input/output req2# c21 source sync input/output req3# c20 source sync input/output req4# b22 source sync input/output reserved a26 reserved reserved reserved d25 reserved reserved reserved w3 reserved reserved table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction reserved y3 reserved reserved reserved ac1 reserved reserved reserved ae15 reserved reserved reserved ae16 reserved reserved reserved ae28 reserved reserved reserved ae29 reserved reserved reset# y8 common clk input rs0# e21 common clk input rs1# d22 common clk input rs2# f21 common clk input rsp# c6 common clk input sktocc# a3 power/other output slp# ae6 async gtl+ input slew_ctrl ac30 power/other input smb_prt ae4 power/other output smi# c27 async gtl+ input stpclk# d4 async gtl+ input tck e24 tap input tdi c24 tap input tdo e25 tap output test_bus a16 power/other input testhi0 w6 power/other input testhi1 w7 power/other input testhi2 w8 power/other input testhi3 y6 power/other input testhi4 aa7 power/other input testhi5 ad5 power/other input testhi6 ae5 power/other input thermda y27 power/other output thermdc y28 power/other output thermtrip# f26 async gtl+ output tms a25 tap input trdy# e19 common clk input trst# f24 tap input vcc a2 power/other vcc a8 power/other vcc a14 power/other vcc a18 power/other vcc a24 power/other vcc a28 power/other vcc a30 power/other table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction
pin listing 58 datasheet vcc b6 power/other vcc b20 power/other vcc b26 power/other vcc b29 power/other vcc b31 power/other vcc c2 power/other vcc c4 power/other vcc c16 power/other vcc c22 power/other vcc c28 power/other vcc c30 power/other vcc d1 power/other vcc d8 power/other vcc d14 power/other vcc d18 power/other vcc d24 power/other vcc d29 power/other vcc d31 power/other vcc e2 power/other vcc e6 power/other vcc e20 power/other vcc e26 power/other vcc e28 power/other vcc e30 power/other vcc f1 power/other vcc f4 power/other vcc f16 power/other vcc f22 power/other vcc f29 power/other vcc f31 power/other vcc g2 power/other vcc g4 power/other vcc g6 power/other vcc g8 power/other vcc g24 power/other vcc g26 power/other vcc g28 power/other vcc g30 power/other vcc h1 power/other vcc h3 power/other vcc h5 power/other table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction vcc h7 power/other vcc h9 power/other vcc h23 power/other vcc h25 power/other vcc h27 power/other vcc h29 power/other vcc h31 power/other vcc j2 power/other vcc j4 power/other vcc j6 power/other vcc j8 power/other vcc j24 power/other vcc j26 power/other vcc j28 power/other vcc j30 power/other vcc k1 power/other vcc k3 power/other vcc k5 power/other vcc k7 power/other vcc k9 power/other vcc k23 power/other vcc k25 power/other vcc k27 power/other vcc k29 power/other vcc k31 power/other vcc l2 power/other vcc l4 power/other vcc l6 power/other vcc l8 power/other vcc l24 power/other vcc l26 power/other vcc l28 power/other vcc l30 power/other vcc m1 power/other vcc m3 power/other vcc m5 power/other vcc m7 power/other vcc m9 power/other vcc m23 power/other vcc m25 power/other vcc m27 power/other table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction
pin listing datasheet 59 vcc m29 power/other vcc m31 power/other vcc n1 power/other vcc n3 power/other vcc n5 power/other vcc n7 power/other vcc n9 power/other vcc n23 power/other vcc n25 power/other vcc n27 power/other vcc n29 power/other vcc n31 power/other vcc p2 power/other vcc p4 power/other vcc p6 power/other vcc p8 power/other vcc p24 power/other vcc p26 power/other vcc p28 power/other vcc p30 power/other vcc r1 power/other vcc r3 power/other vcc r5 power/other vcc r7 power/other vcc r9 power/other vcc r23 power/other vcc r25 power/other vcc r27 power/other vcc r29 power/other vcc r31 power/other vcc t2 power/other vcc t4 power/other vcc t6 power/other vcc t8 power/other vcc t24 power/other vcc t26 power/other vcc t28 power/other vcc t30 power/other vcc u1 power/other vcc u3 power/other vcc u5 power/other table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction vcc u7 power/other vcc u9 power/other vcc u23 power/other vcc u25 power/other vcc u27 power/other vcc u29 power/other vcc u31 power/other vcc v2 power/other vcc v4 power/other vcc v6 power/other vcc v8 power/other vcc v24 power/other vcc v26 power/other vcc v28 power/other vcc v30 power/other vcc w1 power/other vcc w25 power/other vcc w27 power/other vcc w29 power/other vcc w31 power/other vcc y2 power/other vcc y16 power/other vcc y22 power/other vcc y30 power/other vcc aa1 power/other vcc aa4 power/other vcc aa6 power/other vcc aa20 power/other vcc aa26 power/other vcc aa31 power/other vcc ab2 power/other vcc ab8 power/other vcc ab14 power/other vcc ab18 power/other vcc ab24 power/other vcc ab30 power/other vcc ac3 power/other vcc ac4 power/other vcc ac16 power/other vcc ac22 power/other vcc ac31 power/other table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction
pin listing 60 datasheet vcc ad2 power/other vcc ad6 power/other vcc ad20 power/other vcc ad26 power/other vcc ad30 power/other vcc ae3 power/other vcc ae8 power/other vcc ae14 power/other vcc ae18 power/other vcc ae24 power/other vcca ab4 power/other input vcciopll ad4 power/other input vccpll ad1 power/other input vccsense b27 power/other output vid0 f3 power/other output vid1 e3 power/other output vid2 d3 power/other output vid3 c3 power/other output vid4 b3 power/other output vid5 a1 power/other output vidpwrgd b1 power/other input vss a5 power/other vss a11 power/other vss a21 power/other vss a27 power/other vss a29 power/other vss a31 power/other vss b2 power/other vss b9 power/other vss b15 power/other vss b17 power/other vss b23 power/other vss b28 power/other vss b30 power/other vss c7 power/other vss c13 power/other vss c19 power/other vss c25 power/other vss c29 power/other vss c31 power/other vss d2 power/other table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction vss d5 power/other vss d11 power/other vss d21 power/other vss d27 power/other vss d28 power/other vss d30 power/other vss e9 power/other vss e15 power/other vss e17 power/other vss e23 power/other vss e29 power/other vss e31 power/other vss f2 power/other vss f7 power/other vss f13 power/other vss f19 power/other vss f25 power/other vss f28 power/other vss f30 power/other vss g1 power/other vss g3 power/other vss g5 power/other vss g9 power/other vss g25 power/other vss g27 power/other vss g29 power/other vss g31 power/other vss h2 power/other vss h4 power/other vss h6 power/other vss h8 power/other vss h24 power/other vss h26 power/other vss h28 power/other vss h30 power/other vss j1 power/other vss j3 power/other vss j5 power/other vss j7 power/other vss j9 power/other vss j23 power/other table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction
pin listing datasheet 61 vss j25 power/other vss j27 power/other vss j29 power/other vss j31 power/other vss k2 power/other vss k4 power/other vss k6 power/other vss k8 power/other vss k24 power/other vss k26 power/other vss k28 power/other vss k30 power/other vss l1 power/other vss l3 power/other vss l5 power/other vss l7 power/other vss l9 power/other vss l23 power/other vss l25 power/other vss l27 power/other vss l29 power/other vss l31 power/other vss m2 power/other vss m4 power/other vss m6 power/other vss m8 power/other vss m24 power/other vss m26 power/other vss m28 power/other vss m30 power/other vss n2 power/other vss n4 power/other vss n6 power/other vss n8 power/other vss n24 power/other vss n26 power/other vss n28 power/other vss n30 power/other vss p1 power/other vss p3 power/other vss p5 power/other table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction vss p7 power/other vss p9 power/other vss p23 power/other vss p25 power/other vss p27 power/other vss p29 power/other vss p31 power/other vss r2 power/other vss r4 power/other vss r6 power/other vss r8 power/other vss r24 power/other vss r26 power/other vss r28 power/other vss r30 power/other vss t1 power/other vss t3 power/other vss t5 power/other vss t7 power/other vss t9 power/other vss t23 power/other vss t25 power/other vss t27 power/other vss t29 power/other vss t31 power/other vss u2 power/other vss u4 power/other vss u6 power/other vss u8 power/other vss u24 power/other vss u26 power/other vss u28 power/other vss u30 power/other vss v1 power/other vss v3 power/other vss v5 power/other vss v7 power/other vss v9 power/other vss v23 power/other vss v25 power/other vss v27 power/other table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction
pin listing 62 datasheet notes: 1. in systems using the 64-bit in tel xeon processor with 2 mb l2 cache, the system designer must pull-up these signals to the processor v tt . vss v29 power/other vss v31 power/other vss w2 power/other vss w4 power/other vss w24 power/other vss w26 power/other vss w28 power/other vss w30 power/other vss y1 power/other vss y5 power/other vss y7 power/other vss y13 power/other vss y19 power/other vss y25 power/other vss y31 power/other vss aa2 power/other vss aa9 power/other vss aa15 power/other vss aa17 power/other vss aa23 power/other vss aa30 power/other vss ab1 power/other vss ab5 power/other vss ab11 power/other vss ab21 power/other vss ab27 power/other vss ab31 power/other vss ac2 power/other vss ac7 power/other vss ac13 power/other vss ac19 power/other vss ac25 power/other vss ad3 power/other vss ad9 power/other vss ad15 power/other vss ad17 power/other vss ad23 power/other vss ad31 power/other vss ae2 power/other vss ae11 power/other vss ae21 power/other table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction vss ae27 power/other vssa aa5 power/other input vsssense d26 power/other output vtt a4 power/other vtt b4 power/other vtt c5 power/other vtt b12 power/other vtt c10 power/other vtt e12 power/other vtt f10 power/other vtt y10 power/other vtt aa12 power/other vtt ac10 power/other vtt ad12 power/other vtten e1 power/other output table 5-1. pin listing by pin name (cont?d) pin name pin no. signal buffer type direction
pin listing datasheet 63 5.1.2 pin listing by pin number table 5-2. pin listing by pin number pin number pin name signal buffer type direction a1 vid5 power/other output a2 vcc power/other a3 sktocc# power/other output a4 vtt power/other a5 vss power/other a6 a32# source sync input/output a7 a33# source sync input/output a8 vcc power/other a9 a26# source sync input/output a10 a20# source sync input/output a11 vss power/other a12 a14# source sync input/output a13 a10# source sync input/output a14 vcc power/other a15 forcepr# async gtl+ input a16 test_bus power/other input a17 lock# common clk input/output a18 vcc power/other a19 a7# source sync input/output a20 a4# source sync input/output a21 vss power/other a22 a3# source sync input/output a23 hitm# common clk input/output a24 vcc power/other a25 tms tap input a26 reserved reserved reserved a27 vss power/other a28 vcc power/other a29 vss power/other a30 vcc power/other a31 vss power/other b1 vidpwrgd power/other input b2 vss power/other b3 vid4 power/other output b4 vtt power/other b5 otden power/other input b6 vcc power/other b7 a31# source sync input/output b8 a27# source sync input/output b9 vss power/other b10 a21# source sync input/output b11 a22# source sync input/output b12 vtt power/other b13 a13# source sync input/output b14 a12# source sync input/output b15 vss power/other b16 a11# source sync input/output b17 vss power/other b18 a5# source sync input/output b19 req0# source sync input/output b20 vcc power/other b21 req1# source sync input/output b22 req4# source sync input/output b23 vss power/other b24 lint0/intr async gtl+ input b25 prochot# power/other output b26 vcc power/other b27 vccsense power/other output b28 vss power/other b29 vcc power/other b30 vss power/other b31 vcc power/other c1 optimized/ compat# power/other input c2 vcc power/other c3 vid3 power/other output c4 vcc power/other c5 vtt power/other c6 rsp# common clk input c7 vss power/other c8 a35# source sync input/output c9 a34# source sync input/output c10 vtt power/other c11 a30# source sync input/output c12 a23# source sync input/output c13 vss power/other c14 a16# source sync input/output c15 a15# source sync input/output c16 vcc power/other c17 a8# source sync input/output table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction
pin listing 64 datasheet c18 a6# source sync input/output c19 vss power/other c20 req3# source sync input/output c21 req2# source sync input/output c22 vcc power/other c23 defer# common clk input c24 tdi tap input c25 vss power/other c26 ignne# async gtl+ input c27 smi# async gtl+ input c28 vcc power/other c29 vss power/other c30 vcc power/other c31 vss power/other d1 vcc power/other d2 vss power/other d3 vid2 power/other output d4 stpclk# async gtl+ input d5 vss power/other d6 init# async gtl+ input d7 mcerr# common clk input/output d8 vcc power/other d9 ap1# common clk input/output d10 br3# 1 common clk input d11 vss power/other d12 a29# source sync input/output d13 a25# source sync input/output d14 vcc power/other d15 a18# source sync input/output d16 a17# source sync input/output d17 a9# source sync input/output d18 vcc power/other d19 ads# common clk input/output d20 br0# common clk input/output d21 vss power/other d22 rs1# common clk input d23 bpri# common clk input d24 vcc power/other d25 reserved reserved reserved d26 vsssense power/other output d27 vss power/other d28 vss power/other table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction d29 vcc power/other d30 vss power/other d31 vcc power/other e1 vtten power/other output e2 vcc power/other e3 vid1 power/other output e4 bpm5# common clk input/output e5 ierr# async gtl+ output e6 vcc power/other e7 bpm2# common clk input/output e8 bpm4# common clk input/output e9 vss power/other e10 ap0# common clk input/output e11 br2# 1 common clk input e12 vtt power/other e13 a28# source sync input/output e14 a24# source sync input/output e15 vss power/other e16 comp1 power/other input e17 vss power/other e18 drdy# common clk input/output e19 trdy# common clk input e20 vcc power/other e21 rs0# common clk input e22 hit# common clk input/output e23 vss power/other e24 tck tap input e25 tdo tap output e26 vcc power/other e27 ferr#/pbe# async gtl+ output e28 vcc power/other e29 vss power/other e30 vcc power/other e31 vss power/other f1 vcc power/other f2 vss power/other f3 vid0 power/other output f4 vcc power/other f5 bpm3# common clk input/output f6 bpm0# common clk input/output f7 vss power/other f8 bpm1# common clk input/output table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction
pin listing datasheet 65 f9 gtlref power/other input f10 vtt power/other f11 binit# common clk input/output f12 br1# common clk input f13 vss power/other f14 adstb1# source sync input/output f15 a19# source sync input/output f16 vcc power/other f17 adstb0# source sync input/output f18 dbsy# common clk input/output f19 vss power/other f20 bnr# common clk input/output f21 rs2# common clk input f22 vcc power/other f23 gtlref power/other input f24 trst# tap input f25 vss power/other f26 thermtrip# async gtl+ output f27 a20m# async gtl+ input f28 vss power/other f29 vcc power/other f30 vss power/other f31 vcc power/other g1 vss power/other g2 vcc power/other g3 vss power/other g4 vcc power/other g5 vss power/other g6 vcc power/other g7 boot_select power/other input g8 vcc power/other g9 vss power/other g23 lint1/nmi async gtl+ input g24 vcc power/other g25 vss power/other g26 vcc power/other g27 vss power/other g28 vcc power/other g29 vss power/other g30 vcc power/other g31 vss power/other h1 vcc power/other table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction h2 vss power/other h3 vcc power/other h4 vss power/other h5 vcc power/other h6 vss power/other h7 vcc power/other h8 vss power/other h9 vcc power/other h23 vcc power/other h24 vss power/other h25 vcc power/other h26 vss power/other h27 vcc power/other h28 vss power/other h29 vcc power/other h30 vss power/other h31 vcc power/other j1 vss power/other j2 vcc power/other j3 vss power/other j4 vcc power/other j5 vss power/other j6 vcc power/other j7 vss power/other j8 vcc power/other j9 vss power/other j23 vss power/other j24 vcc power/other j25 vss power/other j26 vcc power/other j27 vss power/other j28 vcc power/other j29 vss power/other j30 vcc power/other j31 vss power/other k1 vcc power/other k2 vss power/other k3 vcc power/other k4 vss power/other k5 vcc power/other k6 vss power/other k7 vcc power/other table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction
pin listing 66 datasheet k8 vss power/other k9 vcc power/other k23 vcc power/other k24 vss power/other k25 vcc power/other k26 vss power/other k27 vcc power/other k28 vss power/other k29 vcc power/other k30 vss power/other k31 vcc power/other l1 vss power/other l2 vcc power/other l3 vss power/other l4 vcc power/other l5 vss power/other l6 vcc power/other l7 vss power/other l8 vcc power/other l9 vss power/other l23 vss power/other l24 vcc power/other l25 vss power/other l26 vcc power/other l27 vss power/other l28 vcc power/other l29 vss power/other l30 vcc power/other l31 vss power/other m1 vcc power/other m2 vss power/other m3 vcc power/other m4 vss power/other m5 vcc power/other m6 vss power/other m7 vcc power/other m8 vss power/other m9 vcc power/other m23 vcc power/other m24 vss power/other m25 vcc power/other m26 vss power/other table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction m27 vcc power/other m28 vss power/other m29 vcc power/other m30 vss power/other m31 vcc power/other n1 vcc power/other n2 vss power/other n3 vcc power/other n4 vss power/other n5 vcc power/other n6 vss power/other n7 vcc power/other n8 vss power/other n9 vcc power/other n23 vcc power/other n24 vss power/other n25 vcc power/other n26 vss power/other n27 vcc power/other n28 vss power/other n29 vcc power/other n30 vss power/other n31 vcc power/other p1 vss power/other p2 vcc power/other p3 vss power/other p4 vcc power/other p5 vss power/other p6 vcc power/other p7 vss power/other p8 vcc power/other p9 vss power/other p23 vss power/other p24 vcc power/other p25 vss power/other p26 vcc power/other p27 vss power/other p28 vcc power/other p29 vss power/other p30 vcc power/other p31 vss power/other r1 vcc power/other table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction
pin listing datasheet 67 r2 vss power/other r3 vcc power/other r4 vss power/other r5 vcc power/other r6 vss power/other r7 vcc power/other r8 vss power/other r9 vcc power/other r23 vcc power/other r24 vss power/other r25 vcc power/other r26 vss power/other r27 vcc power/other r28 vss power/other r29 vcc power/other r30 vss power/other r31 vcc power/other t1 vss power/other t2 vcc power/other t3 vss power/other t4 vcc power/other t5 vss power/other t6 vcc power/other t7 vss power/other t8 vcc power/other t9 vss power/other t23 vss power/other t24 vcc power/other t25 vss power/other t26 vcc power/other t27 vss power/other t28 vcc power/other t29 vss power/other t30 vcc power/other t31 vss power/other u1 vcc power/other u2 vss power/other u3 vcc power/other u4 vss power/other u5 vcc power/other u6 vss power/other u7 vcc power/other table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction u8 vss power/other u9 vcc power/other u23 vcc power/other u24 vss power/other u25 vcc power/other u26 vss power/other u27 vcc power/other u28 vss power/other u29 vcc power/other u30 vss power/other u31 vcc power/other v1 vss power/other v2 vcc power/other v3 vss power/other v4 vcc power/other v5 vss power/other v6 vcc power/other v7 vss power/other v8 vcc power/other v9 vss power/other v23 vss power/other v24 vcc power/other v25 vss power/other v26 vcc power/other v27 vss power/other v28 vcc power/other v29 vss power/other v30 vcc power/other v31 vss power/other w1 vcc power/other w2 vss power/other w3 reserved reserved reserved w4 vss power/other w5 bclk1 sys bus clk input w6 testhi0 power/other input w7 testhi1 power/other input w8 testhi2 power/other input w9 gtlref power/other input w23 gtlref power/other input w24 vss power/other w25 vcc power/other w26 vss power/other table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction
pin listing 68 datasheet w27 vcc power/other w28 vss power/other w29 vcc power/other w30 vss power/other w31 vcc power/other y1 vss power/other y2 vcc power/other y3 reserved reserved reserved y4 bclk0 sys bus clk input y5 vss power/other y6 testhi3 power/other input y7 vss power/other y8 reset# common clk input y9 d62# source sync input/output y10 vtt power/other y11 dstbp3# source sync input/output y12 dstbn3# source sync input/output y13 vss power/other y14 dstbp2# source sync input/output y15 dstbn2# source sync input/output y16 vcc power/other y17 dstbp1# source sync input/output y18 dstbn1# source sync input/output y19 vss power/other y20 dstbp0# source sync input/output y21 dstbn0# source sync input/output y22 vcc power/other y23 d5# source sync input/output y24 d2# source sync input/output y25 vss power/other y26 d0# source sync input/output y27 thermda power/other output y28 thermdc power/other output y29 n/c n/c n/c y30 vcc power/other y31 vss power/other aa1 vcc power/other aa2 vss power/other aa3 bsel0 power/other output aa4 vcc power/other aa5 vssa power/other input aa6 vcc power/other table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction aa7 testhi4 power/other input aa8 d61# source sync input/output aa9 vss power/other aa10 d54# source sync input/output aa11 d53# source sync input/output aa12 vtt power/other aa13 d48# source sync input/output aa14 d49# source sync input/output aa15 vss power/other aa16 d33# source sync input/output aa17 vss power/other aa18 d24# source sync input/output aa19 d15# source sync input/output aa20 vcc power/other aa21 d11# source sync input/output aa22 d10# source sync input/output aa23 vss power/other aa24 d6# source sync input/output aa25 d3# source sync input/output aa26 vcc power/other aa27 d1# source sync input/output aa28 n/c n/c n/c aa29 n/c n/c n/c aa30 vss power/other aa31 vcc power/other ab1 vss power/other ab2 vcc power/other ab3 bsel1 power/other output ab4 vcca power/other input ab5 vss power/other ab6 d63# source sync input/output ab7 pwrgood async gtl+ input ab8 vcc power/other ab9 dbi3# source sync input/output ab10 d55# source sync input/output ab11 vss power/other ab12 d51# source sync input/output ab13 d52# source sync input/output ab14 vcc power/other ab15 d37# source sync input/output ab16 d32# source sync input/output ab17 d31# source sync input/output table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction
pin listing datasheet 69 ab18 vcc power/other ab19 d14# source sync input/output ab20 d12# source sync input/output ab21 vss power/other ab22 d13# source sync input/output ab23 d9# source sync input/output ab24 vcc power/other ab25 d8# source sync input/output ab26 d7# source sync input/output ab27 vss power/other ab28 n/c n/c n/c ab29 n/c n/c n/c ab30 vcc power/other ab31 vss power/other ac1 reserved reserved reserved ac2 vss power/other ac3 vcc power/other ac4 vcc power/other ac5 d60# source sync input/output ac6 d59# source sync input/output ac7 vss power/other ac8 d56# source sync input/output ac9 d47# source sync input/output ac10 vtt power/other ac11 d43# source sync input/output ac12 d41# source sync input/output ac13 vss power/other ac14 d50# source sync input/output ac15 dp2# common clk input/output ac16 vcc power/other ac17 d34# source sync input/output ac18 dp0# common clk input/output ac19 vss power/other ac20 d25# source sync input/output ac21 d26# source sync input/output ac22 vcc power/other ac23 d23# source sync input/output ac24 d20# source sync input/output ac25 vss power/other ac26 d17# source sync input/output ac27 dbi0# source sync input/output ac28 n/c n/c n/c table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction ac29 n/c n/c n/c ac30 slew_ctrl power/other input ac31 vcc power/other ad1 vccpll power/other input ad2 vcc power/other ad3 vss power/other ad4 vcciopll power/other input ad5 testhi5 power/other input ad6 vcc power/other ad7 d57# source sync input/output ad8 d46# source sync input/output ad9 vss power/other ad10 d45# source sync input/output ad11 d40# source sync input/output ad12 vtt power/other ad13 d38# source sync input/output ad14 d39# source sync input/output ad15 vss power/other ad16 comp0 power/other input ad17 vss power/other ad18 d36# source sync input/output ad19 d30# source sync input/output ad20 vcc power/other ad21 d29# source sync input/output ad22 dbi1# source sync input/output ad23 vss power/other ad24 d21# source sync input/output ad25 d18# source sync input/output ad26 vcc power/other ad27 d4# source sync input/output ad28 n/c n/c n/c ad29 n/c n/c n/c ad30 vcc power/other ad31 vss power/other ae2 vss power/other ae3 vcc power/other ae4 smb_prt power/other output ae5 testhi6 power/other input ae6 slp# async gtl+ input ae7 d58# source sync input/output ae8 vcc power/other ae9 d44# source sync input/output table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction
pin listing 70 datasheet notes: 1. in systems using the 64-bit intel xeon processor with 2 mb l2 cache, the system designer must pull-up these signals to the processor v tt . ae10 d42# source sync input/output ae11 vss power/other ae12 dbi2# source sync input/output ae13 d35# source sync input/output ae14 vcc power/other ae15 reserved reserved reserved ae16 reserved reserved reserved ae17 dp3# common clk input/output ae18 vcc power/other ae19 dp1# common clk input/output ae20 d28# source sync input/output ae21 vss power/other ae22 d27# source sync input/output ae23 d22# source sync input/output ae24 vcc power/other ae25 d19# source sync input/output ae26 d16# source sync input/output ae27 vss power/other ae28 reserved reserved reserved ae29 reserved reserved reserved ae30 n/c n/c n/c table 5-2. pin listing by pin number (cont?d) pin number pin name signal buffer type direction
datasheet 71 6 thermal specifications 6.1 package thermal specifications the 64-bit intel xeon processor with 2 mb l2 cache requires a thermal solution to maintain temperatures within operating limits. any attemp t to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. as processor techno logy changes, thermal manageme nt becomes increasingly crucial when building computer systems. maintaining the proper thermal environment is key to reliable, long-term system operation. a complete solution includes both component and system level thermal management features. component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spread er (ihs). typical system level thermal solutions may consist of system fans combined with ducting and venting. for more information on designing a component level thermal solution, refer to the 64-bit intel ? xeon? processor with 2 mb l2 cach e thermal/mechanical design guidelines . note: the boxed processor will ship with a component thermal solution. refer to chapter 8 for details on the boxed processor. 6.1.1 thermal specifications to allow the optimal operation and long-term reliability of intel processor-based systems, the processor must remain within the minimum and maximum case temperature (t case ) specifications as defined by the applicable thermal profile (see figure 6-1 , table 6-2 and table 6-3 ). thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. for more details on thermal solution design, please refer to the appropriate processor ther mal/mechanical design guideline. the 64-bit intel xeon processor with 2 mb l2 cache uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control and assure processor reliability. selection of the appr opriate fan speed will be based on the temperature reported by the processor?s ther mal diode. if the diode temperature is greater than or equal to tcontrol (see section 6.2.7 ), then the processor case temperat ure must remain at or below the temperature as specified by the thermal profile (see figure 6-1 ). if the diode temperature is less than tcontrol, then the case temp erature is permitted to exceed th e thermal profile, but the diode temperature must remain at or below tcontrol. sy stems that implement fan speed control must be designed to take these conditions into account. syst ems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications. intel has developed two thermal profiles, either of which can be implemented with the 64-bit intel xeon processor with 2 mb l2 cach e. both ensure adherence to intel reliability requirements. thermal profile a is representative of a volume trically unconstrained thermal solution (i.e. industry enabled 2u heatsink). in this scenario, it is expected that the thermal control circuit (tcc) would only be activated for very brief periods of time when running the most power intensive applications. thermal profile b is indi cative of a constrained th ermal environment (i.e. 1u). because of the reduced cooling capability re presented by this thermal solution, the probability of tcc activation and performance loss is increased . additionally, utilization of a thermal solution that does not meet thermal profile b will viol ate the thermal specificatio ns and may result in
72 datasheet thermal specifications permanent damage to the processor. intel has de veloped these thermal profiles to allow oems to choose the thermal solution and environmental parameters that best suit their platform implementation. refer to the appropriate thermal /mechanical design guide for details on system thermal solution design, thermal profile s, and environmental considerations. the upper point of the thermal profile consists of the thermal design power (tdp) defined in table 6-1 and the associated t case value. it should be noted that the upper point associated with thermal profile b (x = tdp and y = t case_max_b @ tdp) represents a thermal solution design point. in actuality the processor case temperature will never reach this value due to tcc activation (see figure 6-1 ). the lower point of the thermal profile consists of x = p control_base and y = t case_max @ p control_base . pcontrol is defined as the processor power at which t case , calculated from the thermal profile, corresponds to th e lowest possible value of tcontrol. this point is associated with the tcontrol value (see section 6.2.7 ) however, because tcontrol represents a diode temperature, it is necessary to define the associated case temperature. this is t case_max @ p control_base . please see section 6.2.7 and the appropriate thermal/m echanical design guide for proper usage of the tcontrol specification. the case temperature is defined at the geometri c top center of the processor ihs. analysis indicates that real appl ications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. intel recommends that complete thermal solution designs target the thermal design power (tdp) indicated in table 6-1 , instead of the maximum processor power consumption. the thermal mo nitor feature is intended to he lp protect the processor in the event that an application exceeds the tdp recomm endation for a sustained time period. for more details on this feature, refer to section 6.2 . to ensure maximum flexibility for future requirements, systems should be designed to th e flexible motherboard (fmb) gu idelines, even if a processor with a lower thermal dissipation is currently planned. thermal monitor or thermal monitor 2 feature must be enabled for the proce ssor to remain within specification. notes: 1. these values are specified at v cc_max for all processor frequencies. systems must be designed to ensure the processor is not to be subjected to any static v cc and i cc combination wherein v cc exceeds v cc_max at specified i cc . please refer to the v cc static and transient tolerance specifications in chapter 2 . 2. listed frequencies are not necessari ly committed production frequencies. 3. maximum power is the maximum thermal power t hat can be dissipated by the processor through the integrated heat spreader (ihs). maximum power is measured at maximum t case . 4. thermal design power (tdp) should be used for proc essor/chipset thermal solution design targets. tdp is not the maximum power that the processor c an dissipate. tdp is measured at maximum t case . 5. these specifications are based on final silicon characterization. 6. power specifications are defined at all vids found in table 2-8 . the 64-bit intel ? xeon? processor with 2 mb l2 cache may be shipped under multiple vids listed for each frequency. 7. fmb, or flexible motherboard, guidelines provi de a design target for meeting all planned processor frequency requirements. fmb is a design target that is sequential in time. table 6-1. 64-bit intel ? xeon? processor with 2 mb l2 cache thermal specifications core frequency (ghz) maximum power (w) thermal design power (w) minimum t case (c) maximum t case (c) notes 2.80 ghz - fmb (prb = 1) 120 110 5 see figure 6-1 , ta b l e 6 - 2 or ta b l e 6 - 3 1,2,3,4,5,6,7
datasheet 73 thermal specifications notes: 1. thermal profile a is representative of a volume trically unconstrained plat form. please refer to table 6-2 for discrete points that constitute the thermal profile. 2. implementation of thermal profile a should result in virtually no tcc activation. fu rthermore, utilization of thermal solutions that do not meet processor thermal pr ofile a will result in increased probability of tcc activation and may incur measurable performance loss. (see section 6.2 for details on tcc activation). 3. thermal profile b is representative of a volu metrically constrained pl atform. please refer to table 6-3 for discrete points that constitute the thermal profile. 4. implementation of thermal profile b will result in increased probability of tcc activation and may incur measurable performance loss. furthermore, utilization of thermal solutions that do not meet thermal profile b do not meet the processor?s thermal specifications and may result in permanent damage to the processor. 5. refer to the 64-bit intel ? xeon? processor with 2 mb l2 cache thermal/mechanical design guidelines for system and environmental implementation details. figure 6-1. 64-bit intel ? xeon? processor with 2 mb l2 cache thermal profiles a and b (prb = 1) 0 10 20 30 40 50 60 70 80 90 0 102030405060708090100110120 pow e r [w] tcase [c] p control_base_b p control_base_a t case max_b @ tdp t case max_a @ tdp t case max @ p control_base thermal profile b y = 0.320 * x +43.4 thermal profile a y = 0.270 * x +43.1 t case_max_b is a thermal solution design point. in actuality, units will not exceed t case_max_a due to tcc activation. tdp 0 10 20 30 40 50 60 70 80 90 0 102030405060708090100110120 pow e r [w] tcase [c] p control_base_b p control_base_a t case max_b @ tdp t case max_a @ tdp t case max @ p control_base thermal profile b y = 0.320 * x +43.4 thermal profile a y = 0.270 * x +43.1 t case_max_b is a thermal solution design point. in actuality, units will not exceed t case_max_a due to tcc activation. tdp
74 datasheet thermal specifications table 6-2. 64-bit intel ? xeon? processor with 2 mb l2 cache thermal profile a (prb = 1) table 6-3. 64-bit intel ? xeon? processor with 2 mb l2 cache thermal profile b (prb = 1) power [w] t case_max [deg c] power [w] t case_max [deg c] p control _ base _ a = 27 50 68 61 28 51 70 62 30 51 72 63 32 52 74 63 34 52 76 64 36 53 78 64 38 53 80 65 40 54 82 65 42 54 84 66 44 55 86 66 46 56 88 67 48 56 90 67 50 57 92 68 52 57 94 68 54 58 96 69 56 58 98 70 58 59 100 70 60 59 102 71 62 60 104 71 64 60 106 72 64 60 108 72 66 61 110 73 power [w] t case_ma x [deg c] power [w] t case_max [deg c] p control _ base _ b = 22 50 66 65 24 51 68 65 26 52 70 66 28 52 72 66 30 53 74 67 32 54 76 68 34 54 78 68 36 55 80 69 38 56 82 70 40 56 84 70 42 57 86 71 44 57 88 72 46 58 90 72 48 59 92 73 50 59 94 73 52 60 96 74 54 61 98 75 56 61 100 75 58 62 102 76 60 63 104 77 62 63 106 77 64 64 108 78 110 79
datasheet 75 thermal specifications notes: 1. these values are specified at v cc_max for all processor frequencies. sy stems must be designed to ensure the processor is not to be subjected to any static v cc and i cc combination wherein v cc exceeds v cc_max at specified i cc . please refer to the v cc static and transient tole rance specifications in section 2 . 2. listed frequencies are not necessarily committed production frequencies. 3. maximum power is the maximum thermal power that can be dissipated by the processor through the integrated heat spreader (ihs). maximum power is measured at maximum t case . 4. thermal design power (tdp) should be used for processor/chipset thermal solution design targets. tdp is not the maximum power that the processor can dissipate. tdp is measured at maximum t case . 5. these specifications are ba sed on pre-silicon estimates. 6. power specifications are defined at all vids found in table 2-3 . the 64-bit intel ? xeon ? mv processor may be shipped under multiple vids listed for each frequency. notes: 1. thermal profile a is representative of a volume trically unconstrained plat form. please refer to table 6-5 for discrete points that constitute the thermal profile. 2. implementation of thermal profile a should result in virtually no tcc activation. fu rthermore, utilization of thermal solutions that do not meet processor thermal pr ofile a will result in increased probability of tcc activation and may incur measurable performance loss. (see section 6.2 for details on tcc activation). 3. thermal profile b is representative of a volu metrically constrained pl atform. please refer to table 6-6 for discrete points that constitute the thermal profile. 4. implementation of thermal profile b will result in increased probability of tcc activation and may incur measurable performance loss. furthermore, utilization of thermal solutions that do not meet thermal profile b do not meet the processor?s thermal specifications and may result in permanent damage to the processor. table 6-4. 64-bit intel ? xeon? mv 3.20 ghz processor thermal specifications core frequency (ghz) maximum power (w) thermal design power (w) minimum t case (c) maximum t case (c) notes 3.20 ghz (prb = 1) 97 90 5 see figure 6-2 , table 6-5 or table 6-6 1,2,3,4,5,6 figure 6-2. 64-bit intel ? xeon? mv 3.20 ghz processor thermal profiles a and b (prb = 1) 0 10 20 30 40 50 60 70 80 0 102030405060708090100 pow e r [w] tcase [c] p control_base_b p control_base_a t case max_b @ tdp t case max_a @ tdp t case max @ p control_base thermal profile b y = 0.320 * x +42.8 thermal profile a y = 0.270 * x +42.5 t case_max_b is a thermal solution design point. in actuality, units will not exceed t case_max_a due to tcc activation. tdp 0 10 20 30 40 50 60 70 80 0 102030405060708090100 pow e r [w] tcase [c] p control_base_b p control_base_a t case max_b @ tdp t case max_a @ tdp t case max @ p control_base thermal profile b y = 0.320 * x +42.8 thermal profile a y = 0.270 * x +42.5 t case_max_b is a thermal solution design point. in actuality, units will not exceed t case_max_a due to tcc activation. tdp
76 datasheet thermal specifications table 6-5. 64-bit intel ? xeon? mv 3.20 ghz processor thermal profile a (prb = 1) table 6-6. 64-bit intel ? xeon? mv 3.20 ghz processor thermal profile b (prb = 1) power [w] t case_max [deg c] power [w] t case_max [deg c] p control _ base _ a = 27 50 60 59 28 50 62 59 30 51 64 60 32 51 64 60 34 52 66 60 36 52 68 61 38 53 70 61 40 53 72 62 42 54 74 62 44 54 76 63 46 55 78 64 48 55 80 64 50 56 82 65 52 57 84 65 54 57 86 66 56 58 88 66 58 58 90 67 power [w] t case_max [deg c] power [w] t case_max [deg c] p control _ base _ b = 22 50 56 61 24 50 58 61 26 51 60 62 28 52 62 63 30 52 64 63 32 53 66 64 34 54 68 65 36 54 70 65 38 55 72 66 40 56 74 66 42 56 76 67 44 57 78 68 46 58 80 68 48 58 82 69 50 59 84 70 52 59 86 70 54 60 88 71 90 72
datasheet 77 thermal specifications notes: 1. these values are specified at v cc_max for all processor frequencies. sy stems must be designed to ensure the processor is not to be subjected to any static v cc and i cc combination wherein v cc exceeds v cc_max at specified i cc . please refer to the v cc static and transient tole rance specifications in section 2 . 2. listed frequencies are not necessarily committed production frequencies. 3. maximum power is the maximum thermal power that can be dissipated by the processor through the integrated heat spreader (ihs). maximum power is measured at maximum t case . 4. thermal design power (tdp) should be used for processor/chipset thermal solution design targets. tdp is not the maximum power that the processor can dissipate. tdp is measured at maximum t case . 5. these specifications are ba sed on pre-silicon estimates. 6. power specifications are def ined at all vids found in table 2-3 . the 64-bit intel ? xeon ? lv processor may be shipped under multiple vids listed for each frequency. notes: 1. please refer to table 6-8 for discrete points that constitute the thermal profile. 2. utilization of thermal solutions that do not meet t he thermal profile do not meet the processor?s thermal specifications and may result in permanent damage to the processor. table 6-7. 64-bit intel ? xeon? lv 3 ghz processor thermal specifications core frequency (ghz) maximum power (w) thermal design power (w) minimum t case (c) maximum t case (c) notes 3 ghz (prb = 1) 60 55 5 see figure 6-3 and table 6-8 1,2,3,4,5,6 figure 6-3. 64-bit intel ? xeon? lv processor thermal profiles a and b (prb = 0) 0 10 20 30 40 50 60 70 80 90 0 5 10 15 20 25 30 35 40 45 50 55 60 power [w] tcase [c] t case max @ tdp thermal profile y = 0.55 * x +55 tdp 0 10 20 30 40 50 60 70 80 90 0 5 10 15 20 25 30 35 40 45 50 55 60 power [w] tcase [c] t case max @ tdp thermal profile y = 0.55 * x +55 tdp
78 datasheet thermal specifications 6.1.2 thermal metrology the maximum case temperatures (t case ) are specified in table 6-2 , table 6-3 , table 6-5 , table 6-6 , and table 6-8 measured at the geometric top cente r of the processor integrated heat spreader (ihs). figure 6-4 illustrates the location where t case temperature measurements should be made. for detailed guidelines on temperat ure measurement metho dology, refer to the appropriate thermal/mech anical design guide. note: figure is not to scale and is for reference only. table 6-8. 64-bit intel ? xeon? lv 3 ghz processor thermal profile (prb = 0) power [w] t case _ max [deg c] pow er [w ] t case _ max [deg c] 055 3072 2 56 32 73 4 57 34 74 6 58 36 75 8 59 38 76 10 61 40 77 12 62 42 79 14 63 44 80 16 64 46 81 18 65 48 82 20 66 50 83 22 67 52 84 24 68 54 85 26 70 55 86 28 71 figure 6-4. case temperature (t case ) measurement location 21.25 mm [0.837 in. 21.25 mm [0.837 in. measure from edge of processor measure t case at this point. 42.5 mm fc-mpga4 package
datasheet 79 thermal specifications 6.2 processor thermal features 6.2.1 thermal monitor the thermal monitor feature help s control the processor temperat ure by activating the thermal control circuit (tcc) when the processor silic on reaches its maximum operating temperature. the tcc reduces processor power consumption as ne eded by modulating (starting and stopping) the internal processor core clocks. the thermal mo nitor (or thermal monitor 2) feature must be enabled for the processor to be operating within specifications. th e temperature at which thermal monitor activates the thermal contro l circuit is not user configurable and is not software visible. bus traffic is snooped in the normal manner, and in terrupt requests are latched (and serviced during the time that the clocks are on) while the tcc is active. when the thermal monitor is enabled, and a high temperature situation exis ts (i.e. tcc is active), the clocks will be modulated by alternately turnin g the clocks off and on at a duty cycle specific to the processor (typically 30 -50%). clocks will not be off for more than 3 microseconds when the tcc is active. cycle times are processor speed dependent and will decrease as processor core frequencies increase. a small am ount of hysteresis has been included to prevent rapid active/ inactive transitions of the tcc when the proce ssor temperature is near its maximum operating temperature. once the temperatur e has dropped below the maximu m operating temperature, and the hysteresis timer has expired, the tcc goes inactive and cl ock modulation ceases. with a thermal solution designed to meet thermal profile a, it is anticipated that the tcc would only be activated for very short periods of time when running the most power intensive applications. the processor performance impact du e to these brief periods of tcc activation is expected to be so minor that it would be immeasurable. a thermal solution that is designed to thermal profile b may cause a noticeable perfor mance loss due to increased tcc activation. thermal solutions that exceed thermal prof ile b will exceed the maximum temperature specification and affect the long-term reliability of the processor. in addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the tcc is active continuously. refer to the appr opriate thermal/mechanical design guide for information on designing a thermal solution. the duty cycle for the tcc, when activated by the thermal monito r, is factory configured and cannot be modified. the thermal monitor does not require any additional hardware, software drivers, or interrupt handling routines. 6.2.2 thermal monitor 2 the 64-bit intel xeon processor with 2 mb l2 cache also supports an additional power reduction capability known as thermal monitor 2. this mechanism provides an efficient means for limiting the processor temperature by re ducing the power consumption within the processor. the thermal monitor (or thermal monitor 2) feature must be enabled for the processor to be operating within specifications. note: not all intel xeon processors may be cap able of supporting thermal monitor 2. details on which processor frequencies support thermal monitor 2 are provided in the 64-bit intel ? xeon? processor with 800 mhz system bus (1 mb and 2 mb l2 cache versions) specification update . when thermal monitor 2 is enable d, and a high temperature situ ation is detected, the thermal control circuit (tcc) will be activated. the tcc causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the vid signals). this combination of reduced frequency and vid results in a reduction to the processor power consumption.
80 datasheet thermal specifications a processor enabled for thermal monitor 2 includes two opera ting points, each consisting of a specific operating frequency and voltage. the first operating point represents the normal operating condition for the processor. under this condition, the core-frequency-to-system-bus multiple utilized by the processor is that contained in the ia32_flex_brvid_sel msr and the vid is that specified in table 2-8 . these parameters represent normal system operation. the second operating point consists of both a lower operating frequency and voltage. when the tcc is activated, the processor automatically transitions to the new frequency. this transition occurs very rapidly (on the order of 5 s). during the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. edge-triggered interrupts will be latched and kept pending until the pro cessor resumes operation at the new frequency. once the new operating frequency is engaged, the processor will transiti on to the new core operating voltage by issuing a new vid code to the voltage regulator. the voltage regulator must support dynamic vid steps in order to support thermal monitor 2. during the voltage change, it will be necessary to transition through multiple vid codes to reach the target operating voltage. each step will be one vid table entry (see table 2-8 ). the processor continues to execute instructions during the voltage transition. oper ation at the lower voltage reduces the power consumption of the processor. a small amount of hysteresis has been included to prevent rapid active/inactive transitions of the tcc when the processor temper ature is near its maximum op erating temperature. once the temperature has dropped below the maximum operat ing temperature, and th e hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. transition of the vid code will occur first, in order to insure proper operation once the processor reaches its normal operating frequency. refer to figure 6-5 for an illustration of this ordering. the prochot# signal is asserted when a high temperature situation is detected, regardless of whether thermal monitor or thermal monitor 2 is enabled. if a processor has its thermal co ntrol circuit activated via a th ermal monitor 2 event, and an enhanced intel speedstep technology transition to a higher target frequency (through the applicable msr write) is attempted, the freque ncy transition will be delayed until the tcc is deactivated and the thermal mo nitor 2 event is complete. figure 6-5. demand based switching frequency and voltage ordering vcc temperature v nom frequency time f tm2 f max t tm2 v tm2 t(hysterisis) vcc temperature v nom frequency time f tm2 f max t tm2 v tm2 t(hysterisis)
datasheet 81 thermal specifications 6.2.3 on-demand mode the processor provides an auxiliar y mechanism that allows system software to force the processor to reduce its power consumption. this mechanism is referred to as ?on-demand? mode and is distinct from the thermal monitor and thermal monitor 2 features. on-demand mode is intended as a means to reduce system level power consumption. systems using the 64-bit intel xeon processor with 2 mb l2 cache must not re ly on software usage of this mechanism to limit the processor temperature. if bit 4 of the ia32_clock_modulation msr is written to a ?1?, the processor will immediately reduce its power consumption via modu lation (starting and stopping) of the internal core clock, independent of the processor temp erature. when using on -demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ia32_clock_modulation msr. in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off to 87.5% on/12.5% off in 12.5% increments. on-demand mode may be used in conjunction with the thermal monitor. if the system tries to enable on-demand mode at the same time the tcc is engaged, the factory conf igured duty cycle of th e tcc will override the duty cycle selected by the on-demand mode. 6.2.4 prochot# signal pin an external signal, prochot# (processor hot) is a sserted when the proce ssor die temperature has reached its factory configured trip point. if thermal monitor is en abled (note that thermal monitor must be enabled for the processor to be operating within specification), the tcc will be active when prochot# is asserted. the processor can be configured to generate an interrupt upon the assertion or de-assertion of prochot#. refer to the intel architecture software developer?s manual(s) for specific register and programming details. prochot# is designed to assert at or a few degrees higher than maximum t case (as specified by thermal profile a) when dissipating tdp power, and cannot be interpreted as an indication of processor case temperature. this temperature delta accounts for processor package, lifetime and manufacturing variations and attempts to ensure the thermal control circuit is not activated below maximum t case when dissipating tdp power. there is no defined or fixed correlation between the prochot# trip temperature, the case temperature or the ther mal diode temperature. thermal solutions must be designed to the processor specifications and cannot be adjusted based on experimental measurements of t case , prochot#, or tdiode on random processor samples. 6.2.5 forcepr# signal pin the forcepr# (force power reduction) input can be used by the platform to cause the processor to activate the tcc. if the thermal monitor is enabled, the tcc will be activated upon the assertion of the forcepr# signal. the tcc will remain active until the system deasserts forcepr#. forcepr# is an asynchronous input. forcepr# can be used to thermally protect other system components. to use the vr as an example, when the forcepr # pin is asserted, the tcc circuit in the processor will activate, reduc ing the current consumptio n of the processor and the corresponding temp erature of the vr. if should be noted that assertion of the forcepr # does not automatically assert prochot#. as mentioned previously, the prochot# signal is a sserted when a high te mperature situation is detected. a minimum pulse width of 500 s is recommend when the forcepr# is asserted by the system. sustained activation of the forcepr# pi n may cause noticeable platform performance degradation.
82 datasheet thermal specifications refer to the appropriate platform design guidelines for details on implementing the forcepr# signal feature. 6.2.6 thermtrip# signal pin regardless of whether or not thermal monitor or thermal monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (ref er to the thermtrip# definition in table 4-1 ). at this point, the system bus signal thermt rip# will go activ e and stay active as described in table 4-1 . thermtrip# activation is independent of pro cessor activity and does not generate any bus cycles. 6.2.7 t control and fan speed reduction tcontrol is a temperature specifi cation based on a temperature read ing from the thermal diode. the value for tcontrol will be calibra ted in manufacturing and config ured for each processor. the tcontrol temperature for a given proce ssor can be obtained by reading the ia32_temperature_target msr in the processor. the tcontrol value that is read from the ia32_temperature_target msr must be converted from hexadecimal to decimal and added to a base value. the base value is 50 c for the 64-bit intel xeon processor with 2 mb l2 cache. the value of tcontrol may vary from 0x00h to 0x1eh. systems that support the 64-bit intel xeon processor with 2 mb l2 cache must implement bios change s to detect which processor is present, and then select from the appropriate tcontrol_base value. when tdiode is above tcontrol, then t case must be at or below t case_max as defined by the thermal profile. (see figure 6-1 ; table 6-2 and table 6-3 ). otherwise, the processor temperature can be maintained at tcontrol. 6.2.8 thermal diode the processor incorporates an on -die thermal diode. a thermal sensor located on the system board may monitor the die temperature of the processor for thermal management/long term die temperature change purposes. table 6-9 and table 6-10 provide the diode parameter and interface specifications. this thermal diode is separate from the thermal monitor?s thermal sensor and cannot be used to predict the behavior of the thermal monitor. notes: 1. intel does not support or recommend operation of the thermal diode under reverse bias. 2. characterized at 75 c. 3. not 100% tested. specified by design characterization. 4. the ideality factor, n, represents the deviation fr om ideal diode behavior as exemplified by the diode equation: i fw = i s * (e qvd/nkt - 1) where i s = saturation current, q = electronic charge, vd = voltage across the diode, k = boltzmann constant, and t = absolute temperature (kelvin). table 6-9. thermal diode parameters symbol symbol min typ max unit notes i fw forward bias current 11 187 a1 n diode ideality factor 1.0083 1.011 1.0183 2,3,4 r t series resistance 3.242 3.33 3.594 ? 2,3,5
datasheet 83 thermal specifications 5. the series resistance, r t , is provided to allow for a more accurate measurement of the junction temperature. r t , as defined, includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket and external remote diode thermal sensor. r t can be used by remote diode thermal sensors with automatic series resistance canc ellation to calibrate out this error term. another application that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: t error = [r t * (n-1) * i fw_min ] / [nk/q *ln n] where t error = sensor temperature error, n =sensor current ratio, k = boltzmann constant, q= electronic charge. table 6-10. thermal diode interface pin name pin number pin description thermda y27 diode anode thermdc y28 diode cathode
84 datasheet thermal specifications
datasheet 85 7 features 7.1 power-on configuration options several configuration options can be configured by hardware. the processor samples its hardware configuration at reset, on the active-to-inactiv e transition of reset# . for specifics on these options, please refer to table 7-1 . the sampled information co nfigures the processor for subseque nt operation. th ese configuration options cannot be changed except by another reset. all resets reconfigure the processor, for reset purposes, the processor does not distinguish be tween a ?warm? reset and a ?power-on? reset. notes: 1. asserting this signal during reset# will select the corresponding option. 2. address pins not identified in this table as c onfiguration options should not be asserted during reset#. 3. the 64-bit intel ? xeon? processor with 2 mb l2 cache only uses the br0# and br1# signals. platforms must not utilize br2# and br3# signals. 7.2 clock control and low power states the processor allows the use of halt, stop gran t and sleep states to reduce power consumption by stopping the clock to internal sections of the pr ocessor, depending on each particular state. see figure 7-1 for a visual representation of the processor low power states. the 64-bit intel xeon processor with 2 mb l2 cache supports the enha nced halt power down state. refer to figure 7-1 and the following sections. note: not all intel xeon processors are capable of supporting the enhanced halt state. more details on which processor frequencies support the enhanced halt state are provided in the 64-bit intel ? xeon? processor with 800 mhz system bus (1 mb and 2 mb l2 cache versions) specification update . the stop grant state requires chipset and bi os support on multiprocessor systems. in a multiprocessor system, all the st pclk# signals are bussed togeth er, thus all processors are affected in unison. the hyper-threading technolo gy feature adds the conditions that all logical processors share the same stpclk# signal internal ly. when the stpclk# signal is asserted, the processor enters the stop gran t state, issuing a stop grant special bus cycle (sbc) for each processor or logical processor. the chipset needs to account for a variable number of processors table 7-1. power-on co nfiguration option pins configuration option pin notes output tri state smi# 1,2 execute bist (built-in self test) init# 1,2 in order queue de-pipelining (set ioq depth to 1) a7# 1,2 disable mcerr# observation a9# 1,2 disable binit# observation a10# 1,2 disable bus parking a15# 1,2 symmetric agent arbitration id br[3:0]# 1,2,3 disable hyper-threading technology a31# 1,2
86 datasheet features asserting the stop grant sbc on the bus before al lowing the processor to be transitioned into one of the lower processor power states. refer to the applicable chipset specification for more information. due to the inability of processors to recogn ize bus transactions dur ing the sleep state, multiprocessor systems are not allowed to simultane ously have one processor in sleep state and the other processors in normal or stop grant state. 7.2.1 normal state this is the normal operatin g state for the processor. 7.2.2 halt or enhanced halt power down states the enhanced halt power down st ate is configured and enabled via the bios. if the enhanced halt state is not enabled, the default power do wn state entered will be halt. refer to the sections below for details on halt and enhanced halt states. 7.2.2.1 halt power down state halt is a low power state entered when the pro cessor executes the halt or mwait instruction. when one of the logical processors executes the halt or mwait instruction, that logical processor is halted; however, the other processor continues normal operation. the processor will transition to the normal stat e upon the occurrence of smi#, bi nit#, init#, lint[1:0] (nmi, intr), or an interrupt delivered over the front side bus. reset# will cause the processor to immediately initialize itself. the return from a system management interrupt (s mi) handler can be to either normal mode or the halt power down state. see the ia-32 intel? architecture software developer's manual, volume 3: system programmer's guide for more information. the system can generate a stpclk# while the pro cessor is in the halt po wer down state. when the system deasserts the stpclk# interrupt, the processor will return execution to the halt state. while in halt power down state, the processor will process front side bus snoops and interrupts. 7.2.2.2 enhanced halt power down state enhanced halt state is a low power state entered when all logical proces sors have executed the halt or mwait instructions and enhanced hal t state has been enable d via the bios. when one of the logical processors executes the halt instruction, that logical processor is halted; however, the other processor continues normal operation. the enhanced halt state is generally a lower power state than the stop grant state. the processor will automatically transition to a lower core frequency and voltage operating point before entering the enhanced halt state. note th at the processor fsb frequency is not altered; only the internal core frequency is changed. when entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower vid. while in the enhanced halt state, th e processor will process bus snoops. the processor exits the enhanced halt state wh en a break event occurs. when the processor exists the enhanced halt state, it will first transition the vid to the original value and then change the bus ratio back to the original value.
datasheet 87 features 7.2.3 stop grant state when the stpclk# pin is asserted, the stop grant st ate of the processor is entered 20 bus clocks after the response phase of the processor-issued stop grant acknowledge special bus cycle. once the stpclk# pin has been asserted, it may only be deasserted once the processor is in the stop grant state. for the 64-bit intel xeon processor wi th 2 mb l2 cache, both logical processors must be in the stop grant state before the deassertion of stpclk#. since the agtl+ signal pins receive power from the front side bus, these pins should not be driven (allowing the level to return to v tt ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the front side bus should be driven to the inactive state. binit# will not be serviced while the processor is in stop grant state. the event will be latched and can be serviced by software upon exit from the stop grant state. reset# will cause the processor to immediately init ialize itself, but the processor will stay in stop grant state. a transition back to the normal state will occur with the de-assertion of the stpclk# signal. when re-entering the st op grant state from the sleep st ate, stpclk# should only be deasserted one or more bus clocks after the deassertion of slp#. figure 7-1. stop clock state machine enhanced halt or halt state bclk running snoops and interrupts allowed normal state normal execution enhanced halt snoop or halt snoop state bclk running service snoops to caches stop grant state bclk running snoops and interrupts allowed sleep state bclk running no snoops or interrupts allowed snoop event occurs snoop event serviced init#, binit#, intr, nmi, smi#, reset#, fsb interrupts stpclk# asserted stpclk# de-asserted s t p c l k # a s s e r t e d s t p c l k # d e - a s s e r t e d slp# asserted slp# de-asserted snoop event occurs snoop event serviced halt or mwait instruction and halt bus cycle generated stop grant snoop state bclk running service snoops to caches
88 datasheet features a transition to the grant snoop st ate will occur when the proce ssor detects a snoop on the front side bus (see section 7.2.4 ). a transition to the sleep state (see section 7.2.5 ) will occur with the assertion of the slp# signal. while in the stop grant state, smi#, init#, binit# and lint[1:0] will be latched by the processor, and only serviced when the processor returns to the no rmal state. only one occurrence of each event will be recognized upon return to the normal state. while in stop grant state, the processor will process snoops on the front side bus and it will latch interrupts delivered on the front side bus. the pbe# signal can be driven when the processor is in stop grant st ate. pbe# will be asserted if there is any pending interrupt latched within th e processor. pending interrupts that are blocked by the eflags.if bit being cl ear will still cause assertion of pb e#. assertion of pbe# indicates to system logic that it should return the processor to the normal state. 7.2.4 enhanced halt snoop or ha lt snoop state, stop grant snoop state the enhanced halt snoop state is used in conjunction with the enhanced halt state. if enhanced halt state is not enabled in the bios, the default snoop state entered will be the halt snoop state. refer to the sections below for details on halt snoop state, grant snoop state and enhanced halt snoop state. 7.2.4.1 halt snoop state, stop grant snoop state the processor will respond to snoop or interrupt transactions on the front side bus while in stop grant state or in halt power down state. during a snoop or interrupt transaction, the processor enters the halt/grant snoop state. the processor will stay in this state until the snoop on the front side bus has been serviced (whether by the proces sor or another agent on the front side bus) or the interrupt has been latched. after the snoop is servi ced or the interrupt is latched, the processor will return to the stop grant state or hal t power down state, as appropriate. 7.2.4.2 enhanced halt snoop state the enhanced halt snoop state is the default snoop state when the enhanced halt state is enabled via the bios. the processor will remain in the lower bus ratio and vid operating point of the enhanced halt state. while in the enhanced halt snoop state, snoops and interrupt transactions are handled the same way as in the halt snoop state. after the snoop is serviced or the interrupt is latched, the processor will return to the enhanced halt state. 7.2.5 sleep state the sleep state is a very low power state in whic h each processor maintains its context, maintains the phase-locked loop (pll), and has stopped most of internal clocks. the sleep state can only be entered from stop grant state. once in the stop gr ant state, the processor will enter the sleep state upon the assertion of the slp# signal. the sl p# pin has a minimum assertion of one bclk period. the slp# pin should only be asserted when the processor is in th e stop grant state. for 64- bit intel xeon processors with 2 mb l2 cache, the slp# pin may only be as serted when all logical processors are in the stop grant state. slp# a ssertions while the processors are not in the stop grant state are out of specification and may results in illegal operation.
datasheet 89 features snoop events that occur while in sleep state or during a transition into or out of sleep state will cause unpredictable behavior. in the sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the excep tion of slp# or reset#) are allowed on the front side bus while the processo r is in sleep state. an y transition on an input signal before the processor has returned to stop grant state will result in unpredictable behavior. if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# pin specification, then the processor will reset itself, ignoring the transition through stop grant state. if res et# is driven active while the processor is in the sleep state, the slp# and stpclk# signals should be deasserted immediat ely after reset# is asserted to ensure the processor correctly executes the reset sequence. when the processor is in sleep state, it will not respond to interrupts or snoop transactions. 7.3 demand based switching (dbs) with enhanced intel speedstep ? technology demand based switching (dbs) with enhanced intel speedstep ? technology enables the processor to switch between multiple frequency and voltage points, which may result in platform power savings. in order to support this technology, the system must support dynamic vid transitions. switching between voltage / fr equency states is software controlled. note: not all processors are capable of supporting enhanced intel speedstep technology. more details on which processor frequencies support this feature are provided in the 64-bit intel ? xeon? processor with 800 mhz system bus (1 mb and 2 mb l2 cache versions) specification update. enhanced intel speedstep technology is a technology that creates processor performance states (p- states). p-states are power cons umption and capability states with in the normal state. enhanced intel speedstep technology enables real-time dynamic switching between frequency and voltage points. it alters the performance of the processor by changing the bus to core frequency ratio and voltage. this allows the processor to run at different core frequenc ies and voltages to best serve the performance and power requirements of the processo r and system. note that the front side bus is not altered; only the internal core frequency is changed. in order to run at reduced power consumption, the voltage is altered in step with the bus ratio. the following are key features of enhanced intel speedstep technology: 1. multiple voltage / frequency operating points provide optimal performance at reduced power consumption. 2. voltage / frequency selection is software c ontrolled by writing to processor msr?s (model specific registers), thus el iminating chipset dependency. if the target frequency is higher than the current frequency, v cc is incremented in steps (+12.5 mv) by placing a new value on the vid signals. the phase lock loop (pll) then locks to the new frequency. note that the top frequency for the processor can not be exceeded. if the target frequency is lower th an the current frequenc y, the pll locks to the new frequency. the v cc is then decremented in step (-12.5 mv) by changing the target vid through the vid signals.
90 datasheet features
datasheet 91 8 boxed processor specifications 8.1 introduction intel boxed processors are intended for system integrators who build systems from components available through distribution channels. the 64-bit intel xeon processor with 2 mb l2 cache and 64-bit intel xeon lv 3 ghz processor will be offered as intel boxed processors. intel will offer boxed 64-bit intel xeon processo rs with 2 mb l2 cache and 64-bit intel xeon lv 3 ghz processors in three product configurati ons available for each processor frequency: 1u passive, 2u passive and 2u+ active. although the active thermal solution mech anically fits into a 2u keepout, additional design considerations may need to be addressed to provide sufficient airflow to the fan inlet. the active thermal solution is primarily designed to be used in a pedestal chassis where sufficient air inlet space is present and side directional airflow is not an issue. the 1u and 2u passive thermal solutions require the use of chassis ducting and ar e targeted for use in r ack mount servers. the retention solution used for these products is ca lled the common enabling kit, or cek. the cek base is compatible with all three thermal solutions. the active heatsink solution for the boxed 64-bit in tel xeon processor with 2 mb l2 cache will be a 4-pin pulse width modulated (pwm) t-diode co ntrolled solution. use of a 4-pin pwm t-diode controlled active thermal solution helps customers meet acoustic targets in pedestal platforms through the platform?s abi lity to directly control the active ther mal solution. it may be necessary to modify existing baseboard designs with 4-pin cp u fan headers and other required circuitry for pwm operation. if a 4-pin pwm t-diode controlled active thermal solution is connected to an older 3-pin cpu fan header, the thermal solution will revert back to a thermistor controlled mode. please see the section 8.3, ?electrical re quirements? on page 8-101 for more details. figure 8-1 through figure 8-3 are representations of the three heatsink solutions that will be offered as part of a boxed processor. figure 8-4 shows an exploded view of the boxed processor thermal solution and the other cek retention components. figure 8-1. 1u passive cek heatsink
92 datasheet boxed processor specifications 2u.tif figure 8-2. 2u passive cek heatsink figure 8-3. active cek heatsink (representation only)
datasheet 93 boxed processor specifications note: 1. the heatsink in this image is for reference only, and may not represent any of t he actual boxed processor heatsinks. 2. the screws, springs, and standoffs will be captive to the heatsink. this image shows all of the components in an exploded view. 3. it is intended that the cek spring will ship with the base board and be pre-attached prior to shipping. 8.2 mechanical specifications this section documents the mechanical specifications of the boxed processor. 8.2.1 boxed processor heatsink dimensions (cek) the boxed processor will be shipped with an una ttached thermal solution. clearance is required around the thermal solution to en sure unimpeded airflow for prop er cooling. the physical space requirements and dimensions for the boxed pr ocessor and assembled heatsink are shown in figure 8-5 through figure 8-9 . figure 8-10 through figure 8-11 are the mechanical drawings for the 4-pin server board fan header and 4-pin connector used for the active cek fan heatsink solution. figure 8-4. passive 64-bit intel ? xeon? processor with 2 mb l2 cache thermal solution (2u and larger) heat sink heat sink standoffs heat sink screw springs thermal interface material heat sink screws motherboard and processor chassis pan protective tape cek spring heat sink heat sink standoffs heat sink screw springs thermal interface material heat sink screws motherboard and processor chassis pan protective tape cek spring
94 datasheet boxed processor specifications figure 8-5. top-side board keepout zones (part 1)
datasheet 95 boxed processor specifications figure 8-6. top-side board keepout zones (part 2)
96 datasheet boxed processor specifications figure 8-7. bottom-side board keepout zones
datasheet 97 boxed processor specifications figure 8-8. board mounting hole keepout zones
98 datasheet boxed processor specifications figure 8-9. volumetric height keep-ins
datasheet 99 boxed processor specifications figure 8-10. 4-pin fan cable connector (for active cek heatsink)
100 datasheet boxed processor specifications figure 8-11. 4-pin base board fan header (for active cek heatsink)
datasheet 101 boxed processor specifications 8.2.2 boxed processor heatsink weight 8.2.2.1 thermal solution weight the 2u passive and 2u+ active heatsink solutions will not exceed a mass of 1050 grams. note that this is per processor, so a dual processor system will have up to 2100 grams total mass in the heatsinks. the 1u cek heat sink will not exceed a mass of 700 gr ams, for a total of 1400 grams in a dual processor system. this large mass will re quire a minimum chassis stiffness to be met in order to withstand force during shock and vibration. see section 3 for details on the processor weight. 8.2.3 boxed processor retent ion mechanism and heatsink support (cek) baseboards and chassis designed fo r use by a system integrator s hould include holes that are in proper alignment with each other to suppo rt the boxed processor. refer to the server system infrastructure specification (ssi-eeb 3.51) or see http://www.ssiforum.org for details on the hole locations. figure 8-4 illustrates the new common enabling kit (cek) retention solution. the cek is designed to extend air-cooling capability through th e use of larger heatsinks with minimal airflow blockage and bypass. cek retention mechanisms can allow the use of much heavier heatsink masses compared to legacy limits by using a load path directly attached to the chassis pan. the cek spring on the secondary side of the basebo ard provides the necessary compressive load for the thermal interface material. the ba seboard is intended to be isolat ed such that the dynamic loads from the heatsink are transferred to the chassis pan via the stiff screws and standoffs. the retention scheme reduces the risk of package pullout and solder joint failures. the baseboard mounting holes for the cek solution are the same location as the legacy server processor hole locations, as specifi ed by the ssi eeb 3.5. howeve r, the cek assembly requires larger diameter holes to compen sate for the cek spring embosses. the holes now need to be 10.2 mm [0.402 in.] in diameter. all components of the cek heatsink solution will be captive to the heatsink and will only require a phillips screwdriver to attach to the chassis pan. when installi ng the cek, the cek screws should be tightened until they will no longer turn easily. this should represent approximately 8 inch- pounds of torque. avoid applying more than 10 inch-pounds of torque; otherwise, damage may occur to retention mechanism components. for further details on the cek thermal solution, refer to the 64-bit intel ? xeon? processor with 2 mb l2 cache thermal/mechan ical design guidelines (see section 1.2 ). 8.3 electrical requirements 8.3.1 fan power supply (active cek) the 4-pin pwm/t-diode-controlled active thermal solution is being offered to help provide better control over pedestal chassis acoustics. this is ach ieved though more accura te measurement of processor die temperature through the processo r?s temperature diode (t-diode). fan rpm is modulated through the use of an asic located on the baseboard, that sends out a pwm control signal to the 4th pin of the connector labeled as control . this thermal solution requires a constant
102 datasheet boxed processor specifications +12 v supplied to pin 2 of the active thermal solution and does not support variable voltage control or 3-pin pwm control. see table 8-2 for details on the 3- and 4-pin active heatsink solution connectors. if the new 4-pin active fan heatsink solution is connected to an older 3-pin baseboard cpu fan header it will default back to a thermistor controlled mode, allowing compatibility with existing designs. when operating in thermistor controlled mode, fan rpm is automatically varied based on the t inlet temperature measured by a ther mistor located at the fan inlet. it may be necessary to change existing baseboard designs to support the new 4-pin active heatsink solution if pwm/t- diode control is desired. it may also be necessary to verify that the larger 4-pin fan c onnector will not interfere with other components installed on the baseboard. the fan power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. the fan power header id entification and locatio n must be documented in the suppliers platform documentation, or on the baseboard its elf. the baseboard fan power header should be positioned within 177.8 mm [7 in.] from the center of the processor socket. table 8-1. pwm fan frequency specificati ons for 4-pin active cek thermal solution description min frequency nominal frequency max frequency unit pwm control frequency range 21,000 25,000 28,000 hz table 8-2. fan specifications for 4-pin active cek thermal solution description min typ steady max steady max startup unit +12 v: 12 volt fan power supply 10.8 12 12 13.2 v ic: fan current draw n/a 1 1.25 1.5 a sense: sense frequency 2 2 2 2 pulses per fan revolution figure 8-12. fan cable connector pin out for 4-pin active cek thermal solution table 8-3. fan cable connector pin out for 4-pin active cek thermal solution pin number signal color 1 ground black 2 power: (+12 v) yellow 3 sense: 2 pulses per revolution green 4 control: 21 khz-28 khz blue
datasheet 103 boxed processor specifications this section describes the cooling requirements of the heatsink solution utilized by the boxed processor. 8.3.2 boxed processor cooling requirements as previously stated the boxed pr ocessor will be available in th ree product configurations. each configuration will require unique design cons iderations. meeting the processor?s temperature specifications is also the functi on of the thermal design of the entire system, and ultimately the responsibility of the system integrator. the pr ocessor temperature speci fications are found in section 6 of this document. 8.3.2.1 1u passive cek heat sink (1u form factor) in the 1u configuration it is assumed that a chassis duct will be implemented to provide 15 cfm of airflow to pass through the heatsink fins. the duct should be designed as precisely as possible and should not allow any air to bypass the heatsink (0? bypass) and a back pressure of 0.38 in. h 2 o. it is assumed that a 40 c t la is met. this requires a superior chassis design to limit the t rise at or below 5 c with an external ambi ent temperature of 35 c. following these guidelines will allow the designer to meet thermal profile b and confor m to the thermal requirem ents of the processor. 8.3.2.2 2u passive cek heatsink (2u and above form factor) once again a chassis duct is required for the 2u passive heatsink. in this configuration thermal profile a (see chapter 6 ) should be followed by supplying 22 cfm of airflow through the fins of the heatsink with a 0? or no duct bypass and a back pressure of 0.14 in. h 2 o. the t la temperature of 40 c should be met. this may require the use of superior design techniques to keep t rise at or below 5 c based on an ambient external temperature of 35 c. 8.3.2.3 2u+ active cek thermal so lution (2u+ and above pedestal) this thermal solution was designed to help pedest al chassis users to meet the thermal processor requirements without the use of chassis ducting. it may be necessary to implement some form of chassis air guide or air duct to meet the t la temperature of 40 c depending on the pedestal chassis layout. also, while the activ e thermal solution is designed to mechanically fit into a 2u chassis, it may require additional space at the top of the thermal solution to allow sufficient airflow into the heatsink fan. therefore, additional design criteria may need to be considered if this thermal solution is used in a 2u rack mount chassis, or in a chassis that has drive bay obstructions above the inlet to the fan heatsink. table 8-4. fan cable connector supplier and part number vendor 3-pin connector part number 4-pin connector part number amp* fan connector: 643815-3 header: 640456-3 n/a walden* molex* fan connector: 22-01-3037 header: 22-23-2031 fan connector: 47054-1000 header: 47053-1000 wieson* n/a fan connector: 2510c888-001 header: 2366c888-007 foxconn* n/a fan connector: n/a header: hf27040-m1
104 datasheet boxed processor specifications thermal profile a should be used to help dete rmine the thermal perfor mance of the platform. once again it is recommended that the ambient air temp erature outside of the ch assis be kept at or below 35 c. the air passing directly over the processor thermal solution should not be preheated by other system components. meeting the pr ocessor?s temperature specification is the responsibility of the system integrator. 8.4 boxed processor contents a direct chassis attach method must be used to avoid problems related to shock and vibration, due to the weight of the thermal solution required to cool the processor. the board must not bend beyond specification in order to avoid damage. the boxed processor contains the components necessary to solve both issues. the boxed pr ocessor will include the following items: ? 64-bit intel xeon processor with 2 mb l2 cache or 64-bit intel xeon lv 3 ghz processor ? unattached (active or pa ssive) thermal solution ? four screws, four springs, and four heatsink standoffs (all captive to the heatsink) ? thermal interface material (p re-applied on heatsink) ? installation manual ? intel inside ? logo the other items listed in figure 8-4 that are required to compete this solution will be shipped with either the chassis or boar ds. they are as follows: ? cek spring (supplied by baseboard vendors) ? heatsink standoffs (supplied by chassis vendors)
datasheet 105 9 debug tools specifications please refer to the itp700 debug port design guide for information regarding debug tool specifications. section 1.2 provides collateral details. 9.1 debug port system requirements the 64-bit intel xeon processor with 2 mb l2 cache debug port is the command and control interface for the in-target prob e (itp) debugger. the itp enab les run-time control of the processors for system debug. the debug port, which is connected to the front side bus, is a combination of the system, jtag and execution signals. there are several mechanical, electrical and functional constraints on the debug port that must be followed. the mechanical constraint requires the debug port connector to be installed in the system with adeq uate physical clearance. electrical constraints exist due to the mixed high and low speed signals of the debug port for the processor. while the jtag signals operate at a maximum of 75 mhz, the execution signals operate at the common clock front side bus frequency (200 mhz). the functional constraint requires the debug port to use the jtag system via a handshake and multiplexing scheme. in general, the information in this chapter may be used as a basis for including all run-control tools in 64-bit intel xeon processor with 2 mb l2 cach e-based system designs, including tools from vendors other than intel. note: the debug port and jtag signal chain must be designed into the processor board to utilize the itp for debug purposes. 9.2 target system implementation 9.2.1 system implementation specific connectivity and layou t guidelines for the debug port are provided in the itp700 debug port design guide . 9.3 logic analyzer interface (lai) intel is working with two logic an alyzer vendors to provide logic an alyzer interfaces (lais) for use in debugging 64-bit intel xeon processor with 2 mb l2 cache-based systems. tektronix* and agilent* should be contacted to obtain specific information about their logic analyzer interfaces. the following information is general in nature. specific information must be obtained from the logic analyzer vendor. due to the complexity of 64-bit intel xeon pro cessor with 2 mb l2 cach e-based multiprocessor systems, the lai is critical in providing the abil ity to probe and capture front side bus signals. there are two sets of considerations to keep in mind when designing a 64-bit intel xeon processor with 2 mb l2 cache-based system that can make use of an lai: mech anical and electrical.
106 datasheet debug tools specifications 9.3.1 mechanical considerations the lai is installed between the processor socket and the processor. the lai pins plug into the socket, while the processor pins pl ug into a socket on the lai. ca bling that is part of the lai egresses the system to allow an electrical conn ection between the processor and a logic analyzer. the maximum volume occupied by the lai, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. system designers must make sure that the keepout volume remains unobstructed inside the system. note that it is possible that the keepout volume re served for the lai may include differ erent requirements from the space normally occupied by the heatsink. if this is the case, th e logic analyzer vendor will provide a cooling solution as part of the lai. 9.3.2 electrical considerations the lai will also affect the electri cal performance of the front side bus, therefore it is critical to obtain electrical load mode ls from each of the logic analyzer ven dors to be able to run system level simulations to prove that their tool will work in the system. contact the lo gic analyzer vendor for electrical specifications and load mode ls for the lai solution they provide.

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