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user?s manual pd789166 pd789166y pd789166(a1) pd789167 pd789167y pd789167(a1) pd789176 pd789176y pd789176(a1) pd789177 pd789177y pd789177(a1) pd78f9177 pd78f9177y pd78f9177a(a1) pd78f9177a pd78f9177ay pd789166(a2) pd789166(a) pd789166y(a) pd789167(a2) pd789167(a) pd789167y(a) pd789176(a2) pd789176(a) pd789176y(a) pd789177(a2) pd789177(a) pd789177y(a) pd78f9177a(a) pd78f9177ay(a) pd789167, 789177, 789167y, 789177y subseries 8-bit single-chip microcontrollers printed in japan document no. u14186ej5v0ud00 (5th edition) date published june 2004 n cp(k) ? 2003
user?s manual u14186ej5v0ud 2 [memo]
user?s manual u14186ej5v0ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices fip and eeprom are trademarks of nec electronics corporation. windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. hp9000 series 700 and hp-ux are trad emarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc.
user?s manual u14186ej5v0ud 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. purchase of nec electronics i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. the information in this document is current as of march, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec ele ctronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, cust omers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
user?s manual u14186ej5v0ud 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
user?s manual u14186ej5v0ud 6 introduction readers this manual is intended for user engineer s who wish to understand the functions of the pd789167, 789177, 789167y, and 789177y subser ies in order to design and develop its application systems and programs. target products: ? pd789167 subseries: pd789166, 789167, 789166(a), 789167(a), 789166(a1), 789167(a1), 789166(a2), 789167(a2) ? pd789177 subseries: pd789176, 789177, 78f9177, 78f9177a, 789176(a), 789177(a), 78f9177a(a), 789176(a1), 789177(a1), 78f9177a(a1), 789176(a2), 789177(a2) ? pd789167y subseries: pd789166y, 789167y, 789166y(a), 789167y(a) ? pd789177y subseries: pd789176y, 789177y, 78f9177y, 78f9177ay, 789176y(a), 789177y(a), 78f9177ay(a) the pd789167, 789177, 789167y, and 789177y subseries is a generic term for all the target devices in this manual. the generic terms used in this manual indicate the following products. ?standard quality grade products?... pd789166, 789167, 789176, 789177, 78f9177, 78f9177a, 789166y, 789167y, 789176y, 789177y, 78f9177y, 78f9177ay ?(a) products?... pd789166(a), 789167(a), 789176(a), 789177(a), 78f9177a(a), 789166y(a), 789167y(a), 789176y(a), 789177y(a), 78f9177ay(a) ?(a1) products?... pd789166(a1), 789167(a1), 789176(a1), 789177(a1), 78f9177a(a1) ?(a2) products?... pd789166(a2), 789167(a2), 789176(a2), 789177(a2) ?mask rom versions?... pd789166, 789167, 789176, 789177, 789166y, 789167y, 789176y, 789177y, 789166(a), 789167(a), 789176(a), 789177(a), 789166y(a), 789167y(a), 789176y(a), 789177y(a), 789166(a1), 789167(a1), 789176(a1), 789177(a1), 789166(a2), 789167(a2), 789176(a2), 789177(a2) ?flash memory versions?... pd78f9177, 78f9177a, 78f9177a(a), 78f9177a(a1), 78f9177y, 78f9177ay, 78f9177ay(a) purpose this manual is intended to give users an understanding of the f unctions described in the organization below.
user?s manual u14186ej5v0ud 7 organization the pd789167, 789177, 789167y, 789177y subseries manual is divided into two parts: this manual and the instruction manual (common to the 78k/0s series). pd789167, 789177, 789167y, 789177y subseries user's manual (this manual) 78k/0s series instruction user's manual ? pin functions ? internal block functions ? interrupts ? other internal peripheral functions ? electrical specifications ? cpu function ? instruction set ? instruction description how to read this manual it is assumed that the readers of this manual have general knowledge of electric engineering, logic circuits, and microcontrollers. ? for users who use this doc ument as the manual for the pd789166(a), 789167(a), 789176(a), 789177(a), 789166y(a), 789167y (a), 789176y(a), 789177y(a), 789166(a1), 789167(a1), 789176(a1), 789177(a1), 789166(a2), 789167(a2), 789176(a2), 789177(a2), 78f9177a(a), 78f9177ay(a), and 78f9177a(a1) the only differences between standar d products and (a) products, (a1) products, and (a2) products are qua lity grades, power supply voltage, operating ambient temperat ure, minimum instruction execution time, and electrical specifications. (refer to 1.10 differences between standard quality grade products and (a) products, (a1) products, and (a2) products, and 2.10 differences between standard quality gr ade products and (a) products.) for (a) products, (a1) products, and (a2) products, read the part numbers indicated in chapters 3 to 22 in the following manner. pd789166 pd789166(a), 789166(a1), 789166(a2) pd789167 pd789167(a), 789167(a1), 789167(a2) pd789176 pd789176(a), 789176(a1), 789176(a2) pd789177 pd789177(a), 789177(a1), 789177(a2) pd789166y pd789166y(a) pd789167y pd789167y(a) pd789176y pd789176y(a) pd789177y pd789177y(a) pd78f9177a pd789177a(a), 78f9177a(a1) pd78f9177ay pd78f9177ay(a) ? to understand the overa ll functions of the pd789167, 789177, 789167y, and 789177y subseries read this manual in the order of the contents . ? how to read register formats the name of a bit whose number is enclosed with < > is reserved in the assembler and is defined as an sfr variable by the #pragma sfr directive in the c compiler. ? to learn the detailed functions of a register whose register name is known see appendix c register index .
user?s manual u14186ej5v0ud 8 ? to learn the details of the instru ction functions of the 78k/0s series refer to 78k/0s series instructions user's manual (u11047e) separately available. ? to know the electrical specifications of the pd789167, 789177, 789167y, and 789177y subseries refer to chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) , chapter 25 electrical specifications ( pd78916x(a1), 78917x(a1), 78916x(a2), 78917x(a2)) , chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f 9177a(a), 78f9177ay(a)) , chapter 28 electrical specifications ( pd78f9177, 78f9177ay) , and chapter 30 electrical specifications ( pd78f9177a(a1)) . caution the application examples in th is manual are created for ?standard? quality grade products for general el ectric equipment. when using the application examples in this manual for purposes which require ?special? quality grades, thoroughl y examine the quality grade of each part and circuit actually used.
user?s manual u14186ej5v0ud 9 differences between pd789167, 789177, 789167y, and 789177y subseries the pd789167, 789177, 789167y, and 789177y subseries differ in their package type, a/d converter resolution, and serial interface configuration. subseries item pd789167 pd789177 pd789167y pd789177y package ? 44-pin plastic lqfp ? 44-pin plastic lqfp ? 48-pin plastic tqfp ic2 pin not provided provided a/d converter resolution 8 bi ts 10 bits 8 bits 10 bits 3-wire serial i/o mode 1 channel serial interface configuration smb0 not provided 1 channel configuration of this manual this manual uses separate chapters to de scribe the functions t hat vary between the subseries. the chapters related to each subseries are listed below. for information about a certain subserie s, see only the chapters indicated by checkmarks in that subseries? column. chapter pd789167 subseries pd789177 subseries pd789167y subseries pd789177y subseries chapter 1 general ( pd789167 and 789177 subseries) ? ? chapter 2 general ( pd789167y and 789177y subseries) ? ? chapter 3 pin functions ( pd789167 and 789177 subseries ? ? chapter 4 pin functions ( pd789167y and 789177y subseries) ? ? chapter 5 cpu architecture chapter 6 port functions chapter 7 clock generator chapter 8 16-bit timer 90 chapter 9 8-bit timer/event counters 80 to 82 chapter 10 watch timer chapter 11 watchdog timer chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) ? ? chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) ? ? chapter 14 serial interface 20 chapter 15 smb0 ( pd789167y and 789177y subseries) ? ? chapter 16 multiplier chapter 17 interrupt functions chapter 18 standby function chapter 19 reset function chapter 20 flash memory version chapter 21 mask option chapter 22 instruction set
user?s manual u14186ej5v0ud 10 conventions data significance: higher digits on the left and lower digits on the right active low representation: (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... or b decimal ... hexadecimal ... h related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pd789167, 789177, 789167y, 789177y subseries user's manual this manual 78k/0s series instructions user's manual u11047e documents related to development tools (software) (user's manuals) document name document no. operation u16656e language u14877e ra78k0s assembler package structured assembly language u11623e operation u16654e cc78k0s c compiler language u14872e operation u16768e sm78k series ver. 2.52 system simulator external parts user open inte rface specifications u15802e id78k0s-ns ver. 2.52 integrated debugger operation u16584e pm plus ver. 5.10 u16569e caution the related docum ents listed above are subject to change wit hout notice. be sure to use the latest version of each document for designing.
user?s manual u14186ej5v0ud 11 documents related to development tools (hardware) (user?s manuals) document name document no. ie-78k0s-ns in-circuit emulator u13549e ie-78k0s-ns-a in-circuit emulator u15207e ie-789177-ns-em1 emulation board u14621e documents related to flash memory writing document name document no. pg-fp3 flash memory progr ammer user?s manual u13502e pg-fp4 flash memory progr ammer user?s manual u15260e other related documents document name document no. semiconductors selection guid e product & packages x13769x semiconductor device mount manual note quality grades on nec semiconductor device c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devi ces by electrostatic discharge (esd) c11892e note see the ?semiconductor device mount manual? webs ite (http://www.necel.com/pkg/en/mount/index.html) caution the related docum ents listed above are subject to change wit hout notice. be sure to use the latest version of each document for designing.
user?s manual u14186ej5v0ud 12 contents chapter 1 general ( pd789167 and 789177 subseries)............. .......................................19 1.1 expanded-specification products and conventiona l products ...........................................19 1.2 features ................................................................................................................... ...................20 1.3 applications............................................................................................................... .................20 1.4 ordering information ....................................................................................................... ..........21 1.5 quality grades............................................................................................................. ...............22 1.6 pin configuration (top view )............................................................................................... .....23 1.7 78k/0s series lineup....................................................................................................... ..........26 1.8 block diagram .............................................................................................................. ..............29 1.9 outline of functions ....................................................................................................... ...........30 1.10 differences between standard quality grade products and (a) products, (a1) products, and (a2) products ..........................................................................................32 chapter 2 general ( pd789167y and 789177y subseries) ........ .......................................33 2.1 expanded-specification products and conventiona l products ...........................................33 2.2 features ................................................................................................................... ...................34 2.3 applications............................................................................................................... .................34 2.4 ordering information ....................................................................................................... ..........35 2.5 quality grades............................................................................................................. ...............36 2.6 pin configuration (top view )............................................................................................... .....37 2.7 78k/0s series lineup....................................................................................................... ..........40 2.8 block diagram .............................................................................................................. ..............42 2.9 outline of function ........................................................................................................ ............43 2.10 differences between standard quality grade products and (a) products .........................45 chapter 3 pin functions ( pd789167 and 789177 subseries) ....... .................................46 3.1 pin function list .......................................................................................................... ..............46 3.2 description of pin functions ............................................................................................... .....48 3.2.1 p00 to p05 (por t 0)...................................................................................................... ................. 48 3.2.2 p10, p 11 (por t 1)........................................................................................................ .................. 48 3.2.3 p20 to p26 (por t 2)...................................................................................................... ................. 48 3.2.4 p30 to p33 (por t 3)...................................................................................................... ................. 49 3.2.5 p50 to p53 (por t 5)...................................................................................................... ................. 49 3.2.6 p60 to p67 (por t 6)...................................................................................................... ................. 50 3.2.7 reset .................................................................................................................... ..................... 50 3.2.8 x1 , x2................................................................................................................... ........................ 50 3.2.9 xt1, xt2 ................................................................................................................. ..................... 50 3.2.10 av dd .............................................................................................................................. .............. 50 3.2.11 av ss .............................................................................................................................. .............. 50 3.2.12 av ref .............................................................................................................................. ............. 50 3.2.13 v dd0 , v dd1 .............................................................................................................................. ...... 50 3.2.14 v ss0 , v ss1 .............................................................................................................................. ....... 50
user?s manual u14186ej5v0ud 13 3.2.15 v pp (flash memory versi on onl y) ................................................................................................... 50 3.2.16 ic0 (mask ro m versi on onl y)............................................................................................. .......... 51 3.2.17 ic3 .................................................................................................................... ........................... 51 3.3 pin i/o circuits and recommended connection of unused pins.........................................52 chapter 4 pin functions ( pd789167y and 789177y subseries)...... ..............................54 4.1 pin function list .......................................................................................................... ..............54 4.2 description of pin functions ............................................................................................... .....56 4.2.1 p00 to p05 (por t 0) ...................................................................................................... ................. 56 4.2.2 p10, p 11 (por t 1) ........................................................................................................ .................. 56 4.2.3 p20 to p26 (por t 2) ...................................................................................................... ................. 56 4.2.4 p30 to p33 (por t 3) ...................................................................................................... ................. 57 4.2.5 p50 to p53 (por t 5) ...................................................................................................... ................. 57 4.2.6 p60 to p67 (por t 6) ...................................................................................................... ................. 58 4.2.7 reset.................................................................................................................... ...................... 58 4.2.8 x1 , x2................................................................................................................... ........................ 58 4.2.9 xt1, xt2 ................................................................................................................. ..................... 58 4.2.10 av dd .............................................................................................................................. .............. 58 4.2.11 av ss .............................................................................................................................. ............... 58 4.2.12 av ref .............................................................................................................................. ............. 58 4.2.13 v dd0 , v dd1 .............................................................................................................................. ...... 58 4.2.14 v ss0 , v ss1 .............................................................................................................................. ....... 58 4.2.15 v pp (flash memory versi on onl y) ................................................................................................... 58 4.2.16 ic0 (mask ro m versi on onl y)............................................................................................. .......... 59 4.2.17 ic2 ..................................................................................................................... ........................... 59 4.3 pin i/o circuits and recommended connection of unused pins.........................................60 chapter 5 cpu architecture ....................................... .......................................................... .....62 5.1 memory space ............................................................................................................... .............62 5.1.1 internal progr am memory space ............................................................................................ ....... 65 5.1.2 internal data memory (i nternal high-speed ram) spac e............................................................... 66 5.1.3 special-function register (s fr) area..................................................................................... ........ 66 5.1.4 data memo ry addre ssing................................................................................................... ........... 66 5.2 processor registers ........................................................................................................ ..........69 5.2.1 control regist ers ........................................................................................................ ................... 69 5.2.2 general-pur pose regi sters ................................................................................................ ............ 72 5.2.3 special-functi on register s (sfr) ......................................................................................... .......... 73 5.3 instruction address addressing .................................. ........................................................... .76 5.3.1 relative addre ssing ...................................................................................................... ................ 76 5.3.2 immediat e addre ssing ..................................................................................................... ............. 77 5.3.3 table indi rect addr essing................................................................................................ .............. 78 5.3.4 register addre ssing ...................................................................................................... ................ 78 5.4 operand address addressing ....................................... .......................................................... .79 5.4.1 direct addressi ng........................................................................................................ .................. 79 5.4.2 short dire ct addre ssing.................................................................................................. ............... 80
user?s manual u14186ej5v0ud 14 5.4.3 special-function r egister (sfr ) addre ssing ............................................................................... ... 81 5.4.4 register addre ssing ...................................................................................................... ................ 82 5.4.5 register i ndirect addr essing ............................................................................................. ............ 83 5.4.6 based addressi ng ......................................................................................................... ................ 84 5.4.7 stack addressi ng ......................................................................................................... ................. 84 chapter 6 port functio ns ................................................................................................... ........85 6.1 port functions............................................................................................................. ...............85 6.2 port configuration ......................................................................................................... ............87 6.2.1 po rt 0................................................................................................................... ......................... 87 6.2.2 po rt 1................................................................................................................... ......................... 88 6.2.3 po rt 2................................................................................................................... ......................... 89 6.2.4 po rt 3................................................................................................................... ......................... 94 6.2.5 po rt 5................................................................................................................... ......................... 97 6.2.6 po rt 6................................................................................................................... ......................... 98 6.3 port function control registers . ........................................................................................... ..99 6.4 operation of port functions ................................................................................................ ...102 6.4.1 writing to i/o port ...................................................................................................... ................. 102 6.4.2 reading fr om i/o port .................................................................................................... ............. 102 6.4.3 arithmetic oper ation of i/o port......................................................................................... .......... 102 chapter 7 clock generator .................................................................................................. ..103 7.1 clock generator functions.................................................................................................. ...103 7.2 clock generator configuration .................................... .......................................................... 103 7.3 registers controlling clock generator ......................... ........................................................105 7.4 system clock oscillators ................................................................................................... .....108 7.4.1 main system clock osc illator ............................................................................................. .......... 108 7.4.2 subsystem cl ock osc illator............................................................................................... ........... 109 7.4.3 examples of incorre ct oscillato r connec tion.............................................................................. .. 110 7.4.4 sc aler ................................................................................................................... ...................... 111 7.4.5 when no subsystem clocks ar e us ed ........................................................................................ . 111 7.5 clock generator operatio n .................................................................................................. ...112 7.6 changing setting of system clock and cpu clock ... ..........................................................113 7.6.1 time required for switching between system clock and cpu cl ock ............................................ 113 7.6.2 switching between system clock and cp u cloc k........................................................................ 114 chapter 8 16-bit time r 90................................................................................................. ...........115 8.1 16-bit timer 90 functions .................................................................................................. .....115 8.2 16-bit timer 90 configuration.............................................................................................. ...116 8.3 registers controlling 16-bit timer 90............................ ........................................................11 9 8.4 operation of 16-bit timer 90............................................................................................... ....123 8.4.1 operation as timer in terrupt ............................................................................................. ........... 123 8.4.2 operation as time r out put ................................................................................................ ........... 125 8.4.3 captur e operat ion ........................................................................................................ ............... 126 8.4.4 16-bit timer counter 90 r eadout .......................................................................................... ......... 127
user?s manual u14186ej5v0ud 15 8.4.5 buzzer out put operat ion.................................................................................................. ............ 128 8.5 notes on 16-bit timer 90 ....................................................................................................... ..129 8.5.1 notes on usi ng 16-bit ti mer 90 ........................................................................................... ......... 129 8.5.2 restrictions on rewriting of 16-bit compare register 90............................................................... 131 chapter 9 8-bit timer/event counters 80 to 82 .............................................................133 9.1 functions of 8-bit timer/event counters 80 to 82 ..... ..........................................................133 9.2 configuration of 8-bit timer/e vent counters 80 to 82 ....................... ..................................135 9.3 8-bit timer/event counters 80 to 82 control regist ers.......................................................138 9.4 operation of 8-bit timer/event c ounters 80 to 82............................ ....................................142 9.4.1 operation as interval timer.............................................................................................. ............ 142 9.4.2 operation as ex ternal event count er...................................................................................... ..... 144 9.4.3 operation as square wave output .......................................................................................... ..... 145 9.4.4 pwm output operat ion ..................................................................................................... ........... 147 9.5 notes on using 8-bit timer/event counters 80 to 82......................... ..................................149 chapter 10 watch timer..................................................................................................... .........153 10.1 watch timer functions ..................................................................................................... ......153 10.2 watch timer configuration ...................................... ........................................................... ....154 10.3 watch timer control register ................................... ........................................................... ..155 10.4 watch timer operation..................................................................................................... .......156 10.4.1 operation as watch timer................................................................................................ ............ 156 10.4.2 operation as interval timer............................................................................................. ............. 156 chapter 11 watchdog timer ...................................... ............................................................ ...158 11.1 watchdog timer functions.................................................................................................. ...158 11.2 watchdog timer configuration .......... .................................................................................... 159 11.3 watchdog timer control registers.... ....................................................................................16 0 11.4 watchdog timer operation .................................................................................................. ...162 11.4.1 operation as watchdog timer ............................................................................................. ......... 162 11.4.2 operation as interval timer............................................................................................. ............. 163 chapter 12 8-bit a/d converter ( pd789167 and 789167y subseri es) .....................164 12.1 8-bit a/d converter functions..... ........................................................................................ ...164 12.2 8-bit a/d converter configuration ............................ ............................................................. 164 12.3 8-bit a/d converter control registers...................... .............................................................16 7 12.4 8-bit a/d converter operation ................................. ............................................................ ...169 12.4.1 basic operation of 8-bit a/d c onverte r .................................................................................. ...... 169 12.4.2 input voltage and conversion result ..................................................................................... ....... 170 12.4.3 operation mode of 8-bit a/d c onverter ................................................................................... .... 172 12.5 cautions related to 8-bit a/d converter ............... ................................................................173 chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) ...................177 13.1 10-bit a/d converter functions.......... .................................................................................. ..177 13.2 10-bit a/d converter configuration .......................... .............................................................1 77
user?s manual u14186ej5v0ud 16 13.3 10-bit a/d converter control registers ...................... ..........................................................180 13.4 10-bit a/d converter operation................................ ............................................................ ..182 13.4.1 basic operation of 10-bit a/d c onverte r ................................................................................. ..... 182 13.4.2 input voltage and conversion result ..................................................................................... ....... 183 13.4.3 operation mode of 10-bit a/d c onverte r .................................................................................. ... 185 13.5 cautions related to 10-bit a/d converter............... ..............................................................186 chapter 14 serial interface 20 ................................ ............................................................ ..190 14.1 functions of serial interface 20................................ .......................................................... ....190 14.2 configuration of serial inte rface 20 ...................................................................................... .190 14.3 control registers of serial interface 20 ................................................................................19 4 14.4 operation of serial interface 20............................. ............................................................. ....201 14.4.1 operati on stop mode ..................................................................................................... ............. 201 14.4.2 asynchronous serial interface (uar t) mode.............................................................................. 2 03 14.4.3 3-wire se rial i/o mode.................................................................................................. ............... 217 chapter 15 smb0 ( pd789167y and 789177y subseries)........ ...........................................227 15.1 smb0 functions ............................................................................................................ ...........227 15.2 smb0 configuration........................................................................................................ .........229 15.3 smb0 control registers .................................................................................................... ......231 15.4 smb0 definition and control methods .......................... ........................................................245 15.4.1 start conditi on......................................................................................................... .................... 245 15.4.2 a ddres s ................................................................................................................. ..................... 246 15.4.3 specification of transmission di rection................................................................................. ....... 246 15.4.4 acknowledge signal (a ck) ................................................................................................ ......... 247 15.4.5 stop conditi on.......................................................................................................... ................... 248 15.4.6 wait si gnal (w ait)...................................................................................................... ................ 249 15.4.7 smb0 interr upt (intsmb0)................................................................................................ ......... 251 15.4.8 interrupt request (intsmb0) gener ation timing and wa it cont rol ................................................ 272 15.4.9 matching addre ss detection method ....................................................................................... .... 274 15.4.10 error detecti on ........................................................................................................ .................... 274 15.4.11 extens ion c ode ......................................................................................................... .................. 274 15.4.12 arbi tration ............................................................................................................ ....................... 275 15.4.13 wakeup functi on........................................................................................................ ................. 276 15.4.14 communicati on reserv ation .............................................................................................. .......... 277 15.4.15 additional cautions.................................................................................................... .................. 279 15.4.16 communica tion operat ion................................................................................................ ........... 280 15.5 timing charts ............................................................................................................. ..............282 chapter 16 multiplier ....................................................................................................... ...........289 16.1 multiplier function ....................................................................................................... ............289 16.2 multiplier configuratio n.................................................................................................. .........289 16.3 multiplier control regist er ............................................................................................... .......291 16.4 multiplier operation ...................................................................................................... ...........292
user?s manual u14186ej5v0ud 17 chapter 17 interrupt functions .................................. ..........................................................2 93 17.1 interrupt function types.................................................................................................. .......293 17.2 interrupt sources and configuratio n .....................................................................................29 3 17.3 interrupt function control register s.....................................................................................2 96 17.4 interrupt processing operation ................................. ........................................................... ..301 17.4.1 non-maskable interrupt r equest acknowledgment operatio n ...................................................... 301 17.4.2 maskable interrupt reques t acknowledgment operatio n.............................................................. 303 17.4.3 multiple inte rrupt proc essing ........................................................................................... ............ 305 17.4.4 interrupt request hold.................................................................................................. ................ 307 chapter 18 standby function ..................................... ........................................................... ..308 18.1 standby function and configuration. ....................................................................................308 18.1.1 standby functi on ........................................................................................................ ................. 308 18.1.2 standby function control r egist er ....................................................................................... ......... 309 18.2 operation of standby function ................................. ............................................................ .310 18.2.1 halt mode ............................................................................................................... ................. 310 18.2.2 stop mode............................................................................................................... ................. 313 chapter 19 reset function .................................................................................................. .....316 chapter 20 flash memory version........................... .............................................................320 20.1 flash memory characteristics ................................... ........................................................... ..321 20.1.1 programmi ng envir onment ................................................................................................. ........ 321 20.1.2 communi cation mode...................................................................................................... ........... 322 20.1.3 on-board pi n proce ssing ................................................................................................. ........... 326 20.1.4 connection of adapter for flash writing ................................................................................. ...... 329 chapter 21 mask option..................................................................................................... .........337 chapter 22 instruction set ....................................... .......................................................... .....338 22.1 operation ................................................................................................................. .................338 22.1.1 operand identifiers and descripti on met hods............................................................................. . 338 22.1.2 description of ?operation? column ....................................................................................... ....... 339 22.1.3 description of ?flag? column ............................................................................................ ........... 339 22.2 operation list ............................................................................................................ ...............340 22.3 instructions listed by addressing type ................ ...............................................................345 chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a))...........................................................................................................348 chapter 24 characteristics curves ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a))...........................................................................................................367
user?s manual u14186ej5v0ud 18 chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)).......370 chapter 26 characteristics curves ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) ..........384 chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) ...............................................................................................................387 chapter 28 electrical specifications ( pd78f9177, 78f9177y) ......................................406 chapter 29 characteristics curves ( pd78f9177, 78f9177y)..........................................423 chapter 30 electrical specifications ( pd78f9177a(a1)) ...............................................424 chapter 31 package draw ings ................................................................................................. 439 chapter 32 recommended soldering conditions..... ........................................................441 appendix a development tools............................................................................................... 444 a.1 software package ........................................................................................................... .........446 a.2 language processing software ........................................ .....................................................44 6 a.3 control software ........................................................................................................... ...........447 a.4 flash memory writing tools ................................................................................................. ..447 a.5 debugging tools (hardwar e)................................................................................................. .448 a.6 debugging tools (software) ................................................................................................. ..449 appendix b notes on target system design ..................................................................450 appendix c register index ................................................................................................. .......454 c.1 register name index........................................................................................................ ........454 c.2 register symbol index ...................................................................................................... ......456 appendix d revision history ............................................................................................... .....458 d.1 major revisions in this edition............................................................................................ ..458 d.2 revision history up to previous edition ..................... ..........................................................459
user?s manual u14186ej5v0ud 19 chapter 1 general ( pd789167 and 789177 subseries) 1.1 expanded-specification products and conventional products the expanded-specification products and conventional products refer to the following products. expanded-specification produc t... products with a rank note 1 other than k ? mask rom versions for which orders were received after december 1, 2001 (except (a1) products and (a2) products note 2 ). ? pd78f9177a, 78f9177a(a) conventional product... products with rank note 1 k ? products other than the abov e expanded-specification products. notes 1. the rank is indicated by the 5th digit from the left in the lot number marked on the package. lot number 2. for the (a1) products and (a2) products, refer to 1.10 differences be tween standard quality grade products and (a) products, (a1) products, and (a2) products. expanded-specification products and conventional products differ in operat ing frequency ratings. the differences are shown in table 1-1. table 1-1. differences between expanded-sp ecification products and conventional products guaranteed operating s peed (operating frequency) power supply voltage (v dd ) conventional products expanded- specification products 4.5 to 5.5 v 5 mhz (0.4 s) 10 mhz (0.2 s) 3.0 to 5.5 v 5 mhz (0.4 s) 6 mhz (0.33 s) 2.7 to 5.5 v 5 mhz (0.4 s) 5 mhz (0.4 s) 1.8 to 5.5 v 1.25 mhz (1.6 s) 1.25 mhz (1.6 s) remark the values in parentheses indicate t he minimum instruction execution time. year code week code nec electronics control code ran k
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 20 1.2 features rom and ram capacity item product name program memory (rom) data memory (internal high-speed ram) pd789166, 789176, 789166(a), 789176(a), 789166(a1), 789176(a1), 789166(a2), 789176(a2) 16 kb pd789167, 789177, 789167(a), 789177(a), 789167(a1), 789177(a1), 789167(a2), 789177(a2) mask rom 24 kb pd78f9177, 78f9177a, 78f9177a(a), 78f9177a(a1) flash memory 24 kb 512 bytes minimum instruction execution time changeable from high-speed (0.2 s: main system clock 10.0 mhz operation note ) to ultra-low speed (122 s: subsystem clock 32.768 khz operation) i/o port: 31 serial interface: 1 channel 3-wire serial i/o mode/uart mode: 1 channel 8-bit resolution a/d converter: 8 channels ( pd789167 subseries) 10-bit resolution a/d converter: 8 channels ( pd789177 subseries) timer: 6 channels 16-bit timer: 1 channel 8-bit timer/event counter: 2 channels 8-bit timer: 1 channel watch timer: 1 channel watchdog timer: 1 channel vectored interrupt sources: 15 power supply voltage v dd = 1.8 to 5.5 v ( pd78916x, 78917x, 78916x(a), 78917x (a), 78f9177a, 78f9177a(a)) v dd = 4.5 to 5.5 v ( pd78916x(a1), 78917x(a1), 78916x(a2), 78917x(a2)) operating ambi ent temperature t a = ? 40 to 85 c ( pd78916x, 78917x, 78916x(a), 78917x (a), 78f9177a, 78f9177a(a)) t a = ? 40 to 110 c ( pd78916x(a1), 78917x(a1), 789177a(a1)) t a = ? 40 to 125 c ( pd78916x(a2), 78917x(a2)) note when v dd = 4.5 to 5.5 v and the product is an expanded-specification product 1.3 applications power windows, keyless entry, battery management units, side air bags, etc.
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 21 1.4 ordering information part number package internal rom pd789166gb- -8es 44-pin plastic lqfp (10 10) mask rom pd789166ga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd789167gb- -8es 44-pin plastic lqfp (10 10) mask rom pd789167ga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd789176gb- -8es 44-pin plastic lqfp (10 10) mask rom pd789176ga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd789177gb- -8es 44-pin plastic lqfp (10 10) mask rom pd789177ga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd789166gb(a)- -8es 44-pin plastic lqfp (10 10) mask rom pd789167gb(a)- -8es 44-pin plastic lqfp (10 10) mask rom pd789176gb(a)- -8es 44-pin plastic lqfp (10 10) mask rom pd789177gb(a)- -8es 44-pin plastic lqfp (10 10) mask rom pd789166gb(a1)- -8es 44-pin plastic lqfp (10 10) mask rom pd789167gb(a1)- -8es 44-pin plastic lqfp (10 10) mask rom pd789176gb(a1)- -8es 44-pin plastic lqfp (10 10) mask rom pd789177gb(a1)- -8es 44-pin plastic lqfp (10 10) mask rom pd789166gb(a2)- -8es 44-pin plastic lqfp (10 10) mask rom pd789167gb(a2)- -8es 44-pin plastic lqfp (10 10) mask rom pd789176gb(a2)- -8es 44-pin plastic lqfp (10 10) mask rom pd789177gb(a2)- -8es 44-pin plastic lqfp (10 10) mask rom pd78f9177gb-8es 44-pin plastic lqfp (10 10) flash memory pd78f9177agb-8es 44-pin plastic lqfp (10 10) flash memory pd78f9177aga-9eu 48-pin plastic tqfp (fine pitch) (7 7) flash memory pd78f9177agb(a)-8es 44-pin plastic lqfp (10 10) flash memory pd78f9177agb(a1)-8es 44-pin plastic lqfp (10 10) flash memory remark indicates rom code suffix.
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 22 1.5 quality grades part number package quality grade pd789166gb- -8es 44-pin plastic lqfp (10 10) standard pd789166ga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) standard pd789167gb- -8es 44-pin plastic lqfp (10 10) standard pd789167ga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) standard pd789176gb- -8es 44-pin plastic lqfp (10 10) standard pd789176ga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) standard pd789177gb- -8es 44-pin plastic lqfp (10 10) standard pd789177ga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) standard pd789166gb(a)- -8es 44-pin plastic lqfp (10 10) special pd789167gb(a)- -8es 44-pin plastic lqfp (10 10) special pd789176gb(a)- -8es 44-pin plastic lqfp (10 10) special pd789177gb(a)- -8es 44-pin plastic lqfp (10 10) special pd789166gb(a1)- -8es 44-pin plastic lqfp (10 10) special pd789167gb(a1)- -8es 44-pin plastic lqfp (10 10) special pd789176gb(a1)- -8es 44-pin plastic lqfp (10 10) special pd789177gb(a1)- -8es 44-pin plastic lqfp (10 10) special pd789166gb(a2)- -8es 44-pin plastic lqfp (10 10) special pd789167gb(a2)- -8es 44-pin plastic lqfp (10 10) special pd789176gb(a2)- -8es 44-pin plastic lqfp (10 10) special pd789177gb(a2)- -8es 44-pin plastic lqfp (10 10) special pd78f9177gb-8es 44-pin plastic lqfp (10 10) standard pd78f9177agb-8es 44-pin plastic lqfp (10 10) standard pd78f9177aga-9eu 48-pin plastic tqfp (fine pitch) (7 7) standard pd78f9177agb(a)-8es 44-pin plastic lqfp (10 10) special pd78f9177agb(a1)-8es 44-pin plastic lqfp (10 10) special remark indicates rom code suffix. please refer to quality grades on nec semiconduc tor devices (c11531e) published by nec electronics corporation to know the specific ation of the quality gr ade on the devices and its recommended applications.
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 23 1.6 pin configuration (top view) 44-pin plastic lqfp (10 10) pd789166gb- -8es pd789166gb(a1)- -8es pd789177gb-8es pd789167gb- -8es pd789167gb(a1)- -8es pd78f9177agb-8es pd789176gb- -8es pd789176gb(a1)- -8es pd78f9177agb(a)-8es pd789177gb- -8es pd789177gb(a1)- -8es pd78f9177agb(a1)-8es pd789166gb(a)- -8es pd789166gb(a2)- -8es pd789167gb(a)- -8es pd789167gb(a2)- -8es pd789176gb(a)- -8es pd789176gb(a2)- -8es pd789177gb(a)- -8es pd789177gb(a2)- -8es p60/ani0 p61/ani1 p62/ani2 p63/ani3 p64/ani4 p65/ani5 p66/ani6 p67/ani7 av ss p10 p11 33 32 31 30 29 28 27 26 25 24 23 p01 p00 p26/to80 p25/ti80/ss20 v dd0 v ss0 x1 x2 reset xt1 xt2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 av ref av dd p53 p52 p51 p50 p05 v ss1 p04 p03 p02 p30/intp0/ti81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 p20/sck20/asck20 v dd1 p21/so20/t x d20 p22/si20/r x d20 p23 p24 ic0 (v pp ) cautions 1. connect the ic0 (interna lly connected) pin directly to the v ss0 or v ss1 pin. 2. connect the av dd pin to the v dd0 pin. 3. connect the av ss pin to the v ss0 pin. remark pin connections in parenthes es are intended for the pd78f9177, 78f9177a, 78f9177a(a), and 78f9177a(a1).
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 24 48-pin plastic tqfp (fine pitch) (7 7) pd789166ga- -9eu pd789167ga- -9eu pd789176ga- -9eu pd789177ga- -9eu pd78f9177aga-9eu p60/ani0 p61/ani1 p62/ani2 p63/ani3 p64/ani4 p65/ani5 p66/ani6 p67/ani7 av ss p10 p11 ic3 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 p01 p00 p26/to80 p25/tl80/ss20 v dd0 ic3 v ss0 x1 x2 reset xt1 xt2 p30/intp0/tl81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 p20/sck20/asck20 v dd1 ic3 p21/so20/txd20 p22/sl20/rxd20 p23 p24 ic0 (v pp ) av ref av dd p53 p52 ic3 p51 p50 p05 v ss1 p04 p03 p02 cautions 1. connect the ic0 (interna lly connected) pin directly to the v ss0 or v ss1 pin. 2. leave the ic3 pin open. 3. connect the av dd pin to the v dd0 pin. 4. connect the av ss pin to the v ss0 pin. 5. the pin configuration of the 48-pin package for (a), (a1), and (a2) products is undefined. remark pin connections in parenthes es are intended for the pd78f9177a.
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 25 ani0 to ani7: analog input reset: reset asck20: asynchronous serial input rxd20: receive data av dd : analog power supply sck20: serial clock av ref : analog reference voltage si20: serial input av ss : analog ground so20: serial output bzo90: buzzer output ss20: chip select input cpt90: capture trigger input ti80, ti81: timer input ic0, ic3: internally connected to80 to to82, to90: timer output intp0 to intp3: interrupt from peripherals txd20: transmit data p00 to p05: port 0 v dd0 , v dd1 : power supply p10, p11: port 1 v pp : programming power supply p20 to p26: port 2 v ss0 , v ss1 : ground p30 to p33: port 3 x1, x2: crystal (main system clock) p50 to p53: port 5 xt1, xt 2: crystal (subsystem clock) p60 to p67: port 6
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 26 1.7 78k/0s series lineup the 78k/0s series products are shown below. t he subseries names are indicated in frames. 80-pin 52-pin 52-pin pd789327 pd789467 pd789446 pd789436 pd789426 pd789306 pd789316 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin pd789407a pd789456 80-pin pd789417a 80-pin 80-pin pd789479 pd789489 pd789881 64-pin 78k/0s series 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 pd789104a pd789114a 88-pin pd789830 pd789835 144-pin 42/44-pin 44-pin pd789074 30-pin 30-pin pd789088 pd789046 pd789026 44-pin pd789800 44-pin pd789842 52-pin pd789871 20-pin pd789860 pd789861 20-pin 30-pin pd789850a pd789052 20-pin pd789062 20-pin pd789862 30-pin pd789426 with enhanced a/d converter (10 bits) pd789446 with enhanced a/d converter (10 bits) sio, 8-bit a/d converter, and on-chip voltage booster type lcd (15 4) sio, 8-bit a/d converter, and on-chip voltage booster type lcd (5 4) rc oscillation version of the pd789306 sio and on-chip voltage booster type lcd (24 4) sio and resistance division type lcd (24 4) 8-bit a/d converter and on-chip voltage booster type lcd (23 4) small-scale package, general-purpose applications on-chip uart and capable of low voltage (1.8 v) operation pd789074 with added subsystem clock lcd drive inverter control on-chip inverter controller and uart usb on-chip bus controller keyless entry sio, 8-bit a/d converter, and resistance division type lcd (28 4) pd789407a with enhanced a/d converter (10 bits) small-scale package, general-purpose applications and a/d converter pd789167 with enhanced a/d converter (10 bits) pd789104a with enhanced timer pd789124a with enhanced a/d converter (10 bits) rc oscillation version of the pd789104a pd789104a with enhanced a/d converter (10 bits) pd789026 with added 8-bit a/d converter and multiplier on-chip poc and key return circuit on-chip can controller for pc keyboard, on-chip usb function rc oscillation version of the pd789860 vfd drive on-chip vfd controller (display output total: 25) sio, 10-bit a/d converter, and on-chip voltage booster type lcd (28 4) sio, 8-bit a/d converter, and resistance division type lcd (28 4) pd789177y pd789167y pd789026 with enhanced timer rc oscillation version of pd789052 pd789860 without eeprom tm , poc, and lvi uart and resistance division type lcd (26 4) pd789074 with enhanced timer and increased rom and ram capacity uart, 8-bit a/d converter, and dot lcd (display output total: 96) uart and dot lcd (40 16) meter control pd789860 with enhanced timer, added sio, and increased rom, ram capacity products under development products in mass production y subseries products support smb. pd789850a with enhanced timer and a/d pd789852 44-pin remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same.
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 27 series for lcd drive, general-purpose applications timer v dd function subseries name rom capacity 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks pd789046 16 kb 1 ch pd789026 4 kb to 16 kb 1 ch 34 pd789088 16 kb to 32 kb 3 ch pd789074 2 kb to 8 kb 1 ch 1 ch 1 ch (uart: 1 ch) 24 ? pd789062 rc oscillation version small-scale package, general- purpose applications pd789052 4 kb 2 ch ? ? 1 ch ? ? ? 14 1.8 v ? pd789177 ? 8 ch pd789167 16 kb to 24 kb 3 ch 1 ch 8 ch ? 31 ? pd789134a ? 4 ch pd789124a 4 ch ? rc oscillation version pd789114a ? 4 ch small-scale package, general- purpose applications and a/d converter pd789104a 2 kb to 8 kb 1 ch 1 ch ? 1 ch 4 ch ? 1 ch (uart: 1 ch) 20 1.8 v ? pd789835 24 kb to 60 kb 6 ch ? 3 ch 37 1.8 v note pd789830 24 kb 1 ch ? 1 ch (uart: 1 ch) 30 2.7 v dot lcd supported pd789489 32 kb ? 8 ch pd789479 24 kb to 32 kb 3 ch 8 ch ? 2 ch (uart: 1 ch) 45 pd789417a ? 7 ch pd789407a 12 kb to 24 kb 1 ch 7 ch ? 43 1.8 v pd789456 ? 6 ch pd789446 2 ch 6 ch ? 30 pd789436 ? 6 ch pd789426 12 kb to 16 kb 6 ch 1 ch (uart: 1 ch) 40 ? pd789316 rc oscillation version pd789306 8 kb to 16 kb 1 ch ? 2 ch (uart: 1 ch) 23 pd789467 1 ch ? 18 lcd drive pd789327 4 kb to 24 kb ? 1 ch ? ? 1 ch 21 ? note flash memory version: 3.0 v
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 28 series for assp timer v dd function subseries name rom capacity 8-bit 16-bit watch wdt 8-bit a/d 10-bit a/d serial interface i/o min. value remarks usb pd789800 8 kb 2 ch ? ? 1 ch ? ? 2 ch (usb: 1 ch) 31 4.0 v ? inverter control pd789842 8 kb to 16 kb 3 ch note 1 1 ch 1 ch 8 ch ? 1 ch (uart: 1 ch) 30 4.0 v ? pd789852 24 kb to 32 kb 3 ch ? 8 ch 3 ch (uart: 2 ch) 31 on-chip bus controller pd789850a 16 kb 1 ch 1 ch ? 1 ch 4 ch ? 2 ch (uart: 1 ch) 18 4.0 v ? pd789861 rc oscillation version, on-chip eeprom pd789860 4 kb 2 ch ? ? 14 keyless entry pd789862 16 kb 1 ch 2 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 22 1.8 v on-chip eeprom vfd drive pd789871 4 kb to 8 kb 3 ch ? 1 ch 1 ch ? ? 1 ch 33 2.7 v ? meter control pd789881 16 kb 2 ch 1 ch ? 1 ch ? ? 1 ch (uart: 1 ch) 28 2.7 v note 2 ? notes 1. 10-bit timer: 1 channel 2. flash memory version: 3.0 v
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 29 1.8 block diagram ram v dd0 v dd1 v ss0 v ss1 ic0 (v pp ) 78k/0s cpu core rom (flash memory) ti80/ss20/p25 8-bit timer/ event counter 80 p00 to p05 port 0 p10, p11 port 1 p20 to p26 port 2 p30 to p33 port 3 p50 to p53 port 5 p60 to p67 port 6 system control 8-bit timer 82 16-bit timer 90 watch timer watchdog timer sio20 to80/p26 8-bit timer/ event counter 81 ti81/intp0/cpt90/p30 to81/intp1/p31 cpt90/intp0/ti81/p30 to90/intp2/p32 bzo90/intp3/to82/p33 to82/intp3/bzo90/p33 sck20/asck20/p20 si20/r x d20/p22 so20/t x d20/p21 ss20/ti80/p25 multiplier ani0/p60 to ani7/p67 av dd av ss av ref a/d converter reset x1 x2 xt1 xt2 interrupt control intp0/ti81/cpt90/p30 intp1/to81/p31 intp2/to90/p32 intp3/to82/bzo90/p33 remarks 1. the size of the internal rom varies depending on the product. 2. pin connections in parenthes es are intended for the pd78f9177, 78f9177a, 78f9177a(a), and 78f9177a(a1).
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 30 1.9 outline of functions part number item pd789166, 789176, 789166(a), 789176(a), 789166(a1), 789176(a1), 789166(a2), 789176(a2) pd789167, 789177, 789167(a), 789177(a), 789167(a1), 789177(a1), 789167(a2), 789177(a2) pd78f9177, 78f9177a, 78f9177a(a), 78f9177a(a1) mask rom flash memory rom 16 kb 24 kb 24 kb internal memory high-speed ram 512 bytes minimum instruction execution time expanded-specificat ion products of pd78916x, 78917x, 78916x(a), 78917x(a), 78f9177a, 78f9177a(a) 0.2/0.8 s (operation with main system clock operating at 10.0 mhz, v dd = 4.5 to 5.5 v) ? 122 s (operation with subsystem clock operating at 32.768 khz) other than above products ? 0.4/1.6 s (operation with main system clock operating at 5.0 mhz) ? 122 s (operation with subsystem clock operating at 32.768 khz) general-purpose registers 8 bits 8 registers instruction set 16-bit operations bit manipulations (such as set, reset, and test) multiplier 8 bits 8 bits = 16 bits i/o ports total: 31 cmos input: 8 cmos i/o: 17 n-ch open-drain: 6 a/d converter 8-bit resolution 8 channels ( pd789167 subseries) 10-bit resolution 8 channels ( pd789177 subseries) serial interface switchable between 3-wi re serial i/o and uart modes: 1 channel timers 16-bit timer: 1 channel 8-bit timer/event counter: 2 channels 8-bit timer: 1 channel watch timer: 1 channel watchdog timer: 1 channel timer output four outputs buzzer output one output maskable internal: 10, external: 4 vectored interrupt sources non-maskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v ( pd78916x, 78917x, 78916x(a), 78917x(a), 78f9177, 78f9177a, 78f9177a(a) v dd = 4.5 to 5.5 v ( pd78916x(a1), 78917x(a1), 78916x(a2), 78917x(a2), 78f9177a(a1) operating ambient temperature t a = ? 40c to + 85c ( pd78916x, 78917x, 78916x(a), 78917x(a), 78f9177, 78f9177a, 78f9177a(a) t a = ? 40c to + 110c ( pd78916x(a1), 78917x(a1), 78f9177a(a1) t a = ? 40c to + 125c ( pd78916x(a2), 78917x(a2) package 44-pin plastic lqfp (10 10) 48-pin plastic tqfp (fine pitch) (7 7) note note pd789166, 789167, 789176, 789177, and 78f9177a only
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 31 the timers are outlined below. 16-bit timer 90 8-bit timer/event counter 80 8-bit timer/event counter 81 8-bit timer 82 watch timer watchdog timer interval timer ? 1 channel 1 channel 1 channel 1 c hannel note 1 1 channel note 2 operating mode external event counter ? 1 channel 1 channel ? ? ? timer output 1 output 1 output 1 output 1 output ? ? pwm output ? 1 output 1 output 1 output ? ? square-wave output ? 1 output 1 output 1 output ? ? buzzer output 1 output ? ? ? ? ? capture 1 input ? ? ? ? ? function interrupt sources 1 1 1 1 2 2 notes 1. the watch timer can perform both watch timer and in terval timer functions at the same time. 2. the watchdog timer provides a watchdog timer function and an interval timer function. use either of the functions.
chapter 1 general ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 32 1.10 differences between standard quality grad e products and (a) products, (a1) products, and (a2) products standard quality grade products, (a) products, (a1) products , and (a2) products indicate the following products respectively. standard quality grade products... pd789166, 789167, 789176, 789177, 78f9177, 78f9177a (a) products... pd789166(a), 789167(a), 789176(a), 789177(a), 78f9177a(a) (a1) products... pd789166(a1), 789167(a1), 789176(a1 ), 789177(a1), 78f9177a(a1) (a2) products... pd789166(a2), 789167(a2), 789176(a2), 789177(a2) table 1-2 shows the differences between the standard quality grade products and (a) products, (a1) products, and (a2) products. table 1-2. differences between st andard quality grade products and (a) products , (a1) products, and (a2) products part number item standard quality grade products (a) products (a1) pr oducts (a2) products quality grade standard special power supply voltage v dd = 1.8 to 5.5 v v dd = 4.5 to 5.5 v operating ambient temperature t a = ? 40 to 85 c t a = ? 40 to 110 c t a = ? 40 to 125 c minimum instruction execution time expanded-specific ation product note : 0.2 s (at 10.0 mhz operation) conventional product note : 0.4 s (at 5.0 mhz operation) 0.4 s (at 5.0 mhz operation) electrical specifications refer to t he electrical specifications chapters. note refer to 1.1 expanded-specificati on products and conventional products
user?s manual u14186ej5v0ud 33 chapter 2 general ( pd789167y and 789177y subseries) 2.1 expanded-specification products and conventional products the expanded-specification products and conventional products refer to the following products. expanded-specification produc t... products with a rank note other than k ? mask rom versions for which orders were received after december 1, 2001. ? pd78f9177ay, 78f9177ay(a) conventional product... products with rank note k ? products other than the abov e expanded-specification products. note the rank is indicated by the 5th digit from the left in the lot number marked on the package. lot number expanded-specification products and conventional products differ in operat ing frequency ratings. the differences are shown in table 2-1. table 2-1. differences between expanded-sp ecification products and conventional products guaranteed operating s peed (operating frequency) power supply voltage (v dd ) conventional products expanded- specification products 4.5 to 5.5 v 5 mhz (0.4 s) 10 mhz (0.2 s) 3.0 to 5.5 v 5 mhz (0.4 s) 6 mhz (0.33 s) 2.7 to 5.5 v 5 mhz (0.4 s) 5 mhz (0.4 s) 1.8 to 5.5 v 1.25 mhz (1.6 s) 1.25 mhz (1.6 s) remark the values in parentheses indicate t he minimum instruction execution time. year code week code nec electronics control code ran k
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 34 2.2 features rom and ram capacity item product name program memory (rom) data memory (internal high-speed ram) pd789166y, 789176y, 789166y(a), 789176y(a) 16 kb pd789167y, 789177y, 789167y(a), 789177y(a) mask rom 24 kb pd78f9177y, 78f9177ay, 78f9177ay( a) flash memory 24 kb 512 bytes minimum instruction execution time changeable from high-speed (0.2 s: main system clock 10.0 mhz operation note ) to ultra-low speed (122 s: subsystem clock 32.768 khz operation) i/o port: 31 serial interface: 2 channels 3-wire serial i/o mode/uart mode: 1 channel smb: 1 channel 8-bit resolution a/d converter: 8 channels ( pd789167y subseries) 10-bit resolution a/d converter: 8 channels ( pd789177y subseries) timer: 6 channels 16-bit timer: 1 channel 8-bit timer/event counter: 2 channels 8-bit timer: 1 channel watch timer: 1 channel watchdog timer: 1 channel vectored interrupt sources: 17 supply voltage: v dd = 1.8 to 5.5 v operating ambient temperature: t a = ?40 to +85 c note when v dd = 4.5 to 5.5 v and the product is an expanded-specif ication product. 2.3 applications power windows, keyless entry, battery management units, side air bags, etc.
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 35 2.4 ordering information part number package internal rom pd789166ygb- -8es 44-pin plastic lqfp (10 10) mask rom pd789166yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd789167ygb- -8es 44-pin plastic lqfp (10 10) mask rom pd789167yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd789176ygb- -8es 44-pin plastic lqfp (10 10) mask rom pd789176yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd789177ygb- -8es 44-pin plastic lqfp (10 10) mask rom pd789177yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd789166yga(a)- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd789167yga(a)- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd789176yga(a)- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd789177yga(a)- -9eu 48-pin plastic tqfp (fine pitch) (7 7) mask rom pd78f9177ygb-8es 44-pin plastic lqfp (10 10) flash memory pd78f9177yga-9eu 48-pin plastic tqfp (fine pitch) (7 7) flash memory pd78f9177aygb-8es 44-pin plastic lqfp (10 10) flash memory pd78f9177ayga-9eu 48-pin plastic tqfp (fine pitch) (7 7) flash memory pd78f9177aygb(a)-8es 44-pin plastic lqfp (10 10) flash memory pd78f9177ayga(a)-9eu 48-pin plastic tqfp (fine pitch) (7 7) flash memory remark indicates rom code suffix.
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 36 2.5 quality grades part number package quality grade pd789166ygb- -8es 44-pin plastic lqfp (10 10) standard pd789166yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) standard pd789167ygb- -8es 44-pin plastic lqfp (10 10) standard pd789167yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) standard pd789176ygb- -8es 44-pin plastic lqfp (10 10) standard pd789176yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) standard pd789177ygb- -8es 44-pin plastic lqfp (10 10) standard pd789177yga- -9eu 48-pin plastic tqfp (fine pitch) (7 7) standard pd789166yga(a)- -9eu 48-pin plastic tqfp (fine pitch) (7 7) special pd789167yga(a)- -9eu 48-pin plastic tqfp (fine pitch) (7 7) special pd789176yga(a)- -9eu 48-pin plastic tqfp (fine pitch) (7 7) special pd789177yga(a)- -9eu 48-pin plastic tqfp (fine pitch) (7 7) special pd78f9177ygb-8es 44-pin plastic lqfp (10 10) standard pd78f9177yga-9eu 48-pin plastic tqfp (fine pitch) (7 7) standard pd78f9177aygb-8es 44-pin plastic lqfp (10 10) standard pd78f9177ayga-9eu 48-pin plastic tqfp (fine pitch) (7 7) standard pd78f9177aygb(a)-8es 44-pin plastic lqfp (10 10) special pd78f9177ayga(a)-9eu 48-pin plastic tqfp (fine pitch) (7 7) special remark indicates rom code suffix. please refer to quality grades on nec semiconduc tor devices (c11531e) published by nec electronics corporation to know the specif ication of the quality grade on the device and its recommended applications.
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 37 2.6 pin configuration (top view) 44-pin plastic lqfp (10 10) pd789166ygb- -8es pd78f9177ygb-8es pd789167ygb- -8es pd78f9177aygb-8es pd789176ygb - -8es pd78f9177aygb(a)-8es pd789177ygb - -8es p60/ani0 p61/ani1 p62/ani2 p63/ani3 p64/ani4 p65/ani5 p66/ani6 p67/ani7 av ss p10 p11 33 32 31 30 29 28 27 26 25 24 23 p01 p00 p26/to80 p25/ti80/ss20 v dd0 v ss0 x1 x2 reset xt1 xt2 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 av ref av dd p53 p52 p51 p50 p05 v ss1 p04 p03 p02 p30/intp0/ti81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 p20/sck20/asck20 v dd1 p21/so20/t x d20 p22/si20/r x d20 p23/scl0 p24/sda0 ic0 (v pp ) cautions 1. connect the ic0 (interna lly connected) pin directly to the v ss0 or v ss1 pin. 2. connect the av dd pin to the v dd0 pin. 3. connect the av ss pin to the v ss0 pin. remark pin connections in parenthes es are intended for the pd78f9177y, 78f9177ay, and 78f9177ay(a).
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 38 48-pin plastic tqfp (fine pitch) (7 7) pd789166yga- -9eu pd789166yga(a)- -9eu pd78f9177yga-9eu pd789167yga- -9eu pd789167yga(a)- -9eu pd78f9177ayga-9eu pd789176yga- -9eu pd789176yga(a)- -9eu pd78f9177ayga(a)-9eu pd789177yga- -9eu pd789177yga(a)- -9eu p60/ani0 p61/ani1 p62/ani2 p63/ani3 p64/ani4 p65/ani5 p66/ani6 p67/ani7 av ss p10 p11 ic2 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 p01 p00 p26/to80 p25/tl80/ss20 v dd0 ic2 v ss0 x1 x2 reset xt1 xt2 p30/intp0/tl81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 p20/sck20/asck20 v dd1 ic2 p21/so20/txd20 p22/sl20/rxd20 p23/scl0 p24/sda0 ic0 (v pp ) av ref av dd p53 p52 ic0 p51 p50 p05 v ss1 p04 p03 p02 cautions 1. connect the ic0 (interna lly connected) pin directly to the v ss0 or v ss1 pin. 2. leave the ic2 pin open. 3. connect the av dd pin to the v dd0 pin. 4. connect the av ss pin to the v ss0 pin. remark pin connections in parenthes es are intended for the pd78f9177y, 78f9177ay, and 78f9177ay(a).
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 39 ani0 to ani7: analog input reset: reset asck20: asynchronous serial input rxd20: receive data av dd : analog power supply sck20: serial clock (for sio20) av ref : analog reference voltage scl0: serial clock (for smb0) av ss : analog ground sda0: serial data bzo90: buzzer output si20: serial input cpt90: capture trigger i nput so20: serial output ic0, ic2: internally connect ed ss20: chip select input intp0 to intp3: interrupt from peripherals ti80, ti81: timer input p00 to p05: port 0 to80 to to82, to90: timer output p10, p11: port 1 txd20: transmit data p20 to p26: port 2 v dd0 , v dd1 : power supply p30 to p33: port 3 v pp : programming power supply p50 to p53: port 5 v ss0 , v ss1 : ground p60 to p67: port 6 x1, x2: crystal (main system clock) xt1, xt2: crystal (subsystem clock)
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 40 2.7 78k/0s series lineup the 78k/0s series products are shown below. t he subseries names are indicated in frames. 80-pin 52-pin 52-pin pd789327 pd789467 pd789446 pd789436 pd789426 pd789306 pd789316 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin pd789407a pd789456 80-pin pd789417a 80-pin 80-pin pd789479 pd789489 pd789881 64-pin 78k/0s series 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin pd789124a pd789134a pd789177 pd789167 pd789104a pd789114a 88-pin pd789830 pd789835 144-pin 42/44-pin 44-pin pd789074 30-pin 30-pin pd789088 pd789046 pd789026 44-pin pd789800 44-pin pd789842 52-pin pd789871 20-pin pd789860 pd789861 20-pin 30-pin pd789850a pd789052 20-pin pd789062 20-pin pd789862 30-pin pd789426 with enhanced a/d converter (10 bits) pd789446 with enhanced a/d converter (10 bits) sio, 8-bit a/d converter, and on-chip voltage booster type lcd (15 4) sio, 8-bit a/d converter, and on-chip voltage booster type lcd (5 4) rc oscillation version of the pd789306 sio and on-chip voltage booster type lcd (24 4) sio and resistance division type lcd (24 4) 8-bit a/d converter and on-chip voltage booster type lcd (23 4) small-scale package, general-purpose applications on-chip uart and capable of low voltage (1.8 v) operation pd789074 with added subsystem clock lcd drive inverter control on-chip inverter controller and uart usb on-chip bus controller keyless entry sio, 8-bit a/d converter, and resistance division type lcd (28 4) pd789407a with enhanced a/d converter (10 bits) small-scale package, general-purpose applications and a/d converter pd789167 with enhanced a/d converter (10 bits) pd789104a with enhanced timer pd789124a with enhanced a/d converter (10 bits) rc oscillation version of the pd789104a pd789104a with enhanced a/d converter (10 bits) pd789026 with added 8-bit a/d converter and multiplier on-chip poc and key return circuit on-chip can controller for pc keyboard, on-chip usb function rc oscillation version of the pd789860 vfd drive on-chip vfd controller (display output total: 25) sio, 10-bit a/d converter, and on-chip voltage booster type lcd (28 4) sio, 8-bit a/d converter, and resistance division type lcd (28 4) pd789177y pd789167y pd789026 with enhanced timer rc oscillation version of pd789052 pd789860 without eeprom, poc, and lvi uart and resistance division type lcd (26 4) pd789074 with enhanced timer and increased rom and ram capacity uart, 8-bit a/d converter, and dot lcd (display output total: 96) uart and dot lcd (40 16) meter control pd789860 with enhanced timer, added sio, and increased rom, ram capacity products under development products in mass production y subseries products support smb. pd789850a with enhanced timer and a/d pd789852 44-pin remark vfd (vacuum fluorescent display) is referred to as fip tm (fluorescent indicator panel) in some documents, but the functions of the two are the same.
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 41 the functions of the y s ubseries are listed below. function subseries name rom capacity serial interface configuration i/o (pins) v dd min. value remark pd789177y small-scale package, general- purpose application + a/d converter pd789167y 16 kb to 24 kb 3-wire/uart: 1 ch smb: 1 ch 31 1.8 v ?
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 42 2.8 block diagram ram v dd0 v dd1 v ss0 v ss1 ic0 (v pp ) 78k/0s cpu core rom (flash memory) ti80/ss20/p25 8-bit timer/ event counter 80 p00 to p05 port 0 p10, p11 port 1 p20 to p26 port 2 p30 to p33 port 3 p50 to p53 port 5 p60 to p67 port 6 system control 8-bit timer 82 16-bit timer 90 watch timer watchdog timer sio20 to80/p26 8-bit timer/ event counter 81 ti81/intp0/cpt90/p30 to81/intp1/p31 cpt90/intp0/ti81/p30 to90/intp2/p32 bzo90/intp3/to82/p33 to82/intp3/bzo90/p33 sck20/asck20/p20 si20/r x d20/p22 so20/t x d20/p21 ss20/ti80/p25 multiplier ani0/p60 to ani7/p67 av dd av ss av ref a/d converter reset x1 x2 xt1 xt2 interrupt control intp0/ti81/cpt90/p30 intp1/to81/p31 intp2/to90/p32 intp3/to82/bzo90/p33 smb scl0/p23 sda0/p24 remarks 1. the size of the internal rom varies depending on the model. 2. pin connections in parenthes es are intended for the pd78f9177y, 78f9177ay, and 78f9177ay(a).
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 43 2.9 outline of function part number item pd789166y, 789176y 789166y(a), 789176y(a) pd789167y, 789177y 789167y(a), 789177y(a) pd78f9177y, 78f9177ay 78f9177ay(a) mask rom flash memory rom 16 kb 24 kb 24 kb internal memory high-speed ram 512 bytes minimum instruction execution time expanded-specificat ion products of pd78916xy, 78917xy, 78916x y(a), 78917xy(a), 78f9177ay, 78f9177ay(a) ? 0.2/0.8 s (operation with main system clock operating at 10.0 mhz, v dd = 4.5 to 5.5 v) ? 122 s (operation with subsystem clock operating at 32.768 khz) other than above products ? 0.4/1.6 s (operation with main system clock operating at 5.0 mhz) ? 122 s (operation with subsystem clock operating at 32.768 khz) general-purpose registers 8 bits 8 registers instruction set 16-bit operations bit manipulations (such as set, reset, and test) multiplier 8 bits 8 bits = 16 bits i/o ports total: 31 cmos input: 8 cmos i/o: 17 n-ch open-drain: 6 a/d converter 8-bit resolution 8 channels ( pd789167y subseries) 10-bit resolution 8 channels ( pd789177y subseries) serial interface switchable between 3-wi re serial i/o and uart modes: 1 channel smb (system management bus): 1 channel timers 16-bit timer: 1 channel 8-bit timer/event counter: 2 channels 8-bit timer: 1 channel watch timer: 1 channel watchdog timer: 1 channel timer output four outputs buzzer output one output maskable internal: 12, external: 4 vectored interrupt sources nonmaskable internal: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to + 85c package 44-pin plastic lqfp (10 10) note 48-pin plastic tqfp (fine pitch) (7 7) note pd789166y, 789167y, 789176y, 789177y, 78f9177y, 78f9177ay, and 78f9177ay(a) only
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 44 the timers are outlined below. 16-bit timer 90 8-bit timer/event counter 80 8-bit timer/event counter 81 8-bit timer 82 watch timer watchdog timer interval timer ? 1 channel 1 channel 1 channel 1 c hannel note 1 1 channel note 2 operating mode external event counter ? 1 channel 1 channel ? ? ? timer output 1 output 1 output 1 output 1 output ? ? pwm output ? 1 output 1 output 1 output ? ? square-wave output ? 1 output 1 output 1 output ? ? buzzer output 1 output ? ? ? ? ? capture 1 input ? ? ? ? ? function interrupt sources 1 1 1 1 2 2 notes 1. the watch timer can perform both watch timer and in terval timer functions at the same time. 2. the watchdog timer provides a watchdog timer function and an interval timer function. use either of the functions.
chapter 2 general ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 45 2.10 differences between standard qua lity grade products and (a) products standard quality grade products and (a) produc ts indicate the following products. standard quality grade products... pd789166y, 789167y, 789176y, 789177y, 78f9177y, 78f9177ay (a) products... pd789166y(a), 789167y(a), 789176y(a ), 789177y(a), 78f9177ay(a) table 2-2 shows the differences between t he standard quality grade pr oducts and (a) products table 2-2. differences between standard quality grade produc ts and (a) products part number item standard quality grade pr oducts (a) products quality grade standard special power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = ? 40 to 85 c minimum instruction execution time expanded-specific ation product note : 0.2 s (at 10.0 mhz operation) conventional product note : 0.4 s (at 5.0 mhz operation) electrical specifications refer to t he electrical specifications chapters. note refer to 2.1 expanded-specification pr oducts and con ventional products .
user?s manual u14186ej5v0ud 46 chapter 3 pin functions ( pd789167 and 789177 subseries) 3.1 pin function list (1) port pins pin name i/o function after reset alternate function p00 to p05 i/o port 0 6-bit i/o port i/o mode can be specif ied in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by means of pull- up resistor option register 0 (pu0). input ? p10, p11 i/o port 1 2-bit i/o port i/o mode can be specif ied in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by means of pull- up resistor option register 0 (pu0). input ? p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 ? p24 ? p25 ti80/ss20 p26 i/o port 2 7-bit i/o port i/o mode can be specif ied in 1-bit units. for p20 to p22, p25, and p26, an on-chip pull-up resistor can be specified by means of pu ll-up resistor option register b2 (pub2). only p23 and p24 can be used as n-ch open-drain i/o port pins. input to80 p30 intp0/ti81/cpt90 p31 intp1/to81 p32 intp2/to90 p33 i/o port 3 4-bit i/o port i/o mode can be specif ied in 1-bit units. an on-chip pull-up resistor can be specified by means of pull- up resistor option register b3 (pub3). input intp3/to82/bzo90 p50 to p53 i/o port 5 4-bit n-ch open-drain i/o port i/o mode can be specif ied in 1-bit units. for a mask rom version, an on-chip pull-up resistor can be specified by the mask option. input ? p60 to p67 input port 6 8-bit input-only port input ani0 to ani7
chapter 3 pin functions ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 47 (2) non-port pins pin name i/o function after reset alternate function intp0 p30/ti81/cpt90 intp1 p31/to81 intp2 p32/to90 intp3 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p33/to82/bzo90 si20 input serial data input to serial interface input p22/rxd20 so20 output serial data output from serial interface input p21/txd20 sck20 i/o serial clock i/o for se rial interface input p20/asck20 ss20 input chip select i nput to serial interface input p25/ti80 asck20 input serial clock i nput for asynchronous serial interface input p20/sck20 rxd20 input serial data input for asynch ronous serial interface input p22/si20 txd20 output serial data output for asyn chronous serial interface input p21/so20 ti80 input external count clock input to 8-bi t timer/event counter (tm80) input p25/ss20 ti81 input external count clock input to 8-bit ti mer/event counter (tm81) input p30/intp0/cpt90 to80 output 8-bit timer/event counter (tm80) output input p26 to81 output 8-bit timer/event counter (tm81) output input p31/intp1 to82 output 8-bit timer (tm82) output input p33/intp3/bzo90 to90 output 16-bit timer (tm90) output input p32/intp2 cpt90 input capture edge input input p30/intp0/ti81 bzo90 output buzzer output input p33/intp3/to82 ani0 to ani7 input a/d converter analog input input p60 to p67 av ref ? a/d converter reference voltage ? ? av ss ? a/d converter ground potential ? ? av dd ? a/d converter analog power supply ? ? x1 input ? ? x2 ? connecting crystal resonator for main system clock oscillation ? ? xt1 input ? ? xt2 ? connecting crystal resonator fo r subsystem clock oscillation ? ? reset input system reset input input ? v dd0 ? positive power supply ? ? v dd1 ? positive power supply (other than ports) ? ? v ss0 ? ground potential ? ? v ss1 ? ground potential (other than ports) ? ? ic0 ? internally connected. connect this pin directly to the v ss0 or v ss1 pin. ? ? ic3 ? internally connected. leave open. ? ? v pp ? this pin is used to set fl ash memory programming mode and applies a high voltage when a program is written or verified. ? ?
chapter 3 pin functions ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 48 3.2 description of pin functions 3.2.1 p00 to p05 (port 0) these pins constitute a 6-bit i/o port and can be set to i nput or output port mode in 1- bit units by using port mode register 0 (pm0). when these pins are used as an input port, an on-chip pull- up resistor can be used by setting pull- up resistor option register 0 (pu0). 3.2.2 p10, p11 (port 1) these pins constitute a 2-bit i/o port and can be set to i nput or output port mode in 1- bit units by using port mode register 1 (pm1). when these pins are used as an input port, an on-chip pull- up resistor can be used by setting pull- up resistor option register 0 (pu0). 3.2.3 p20 to p26 (port 2) these pins constitute a 7-bit i/o port. in addition, thes e pins provide a function to perform i/o to/from the timer and to i/o the data and clock of the serial interface. port 2 can be set to the following operation modes in 1-bit units. (1) port mode in port mode, p20 to p26 function as a 7-bit i/o port. po rt 2 can be set to input or output mode in 1-bit units by using port mode register 2 (pm2). for p20 to p22, p25, and p26, whether to use on-chip pull-up resistors can be specified in 1-bit units by us ing pull-up resistor option register b2 (pub2), regardless of the setting of port mode register 2 (pm2). p23 and p24 are n-ch open-drain i/o ports. (2) control mode in this mode, p20 to p26 function as the timer i/o, the data i/o and the clock i/o of the serial interface. (a) ti80 this is the external clock input pi n for 8-bit timer/event counter 80. (b) to80 this is the timer output pin of 8-bit timer/event counter 80. (c) si20, so20 these are the serial data i/o pins of the serial interface. (d) sck20 this is the serial clock i/o pin of the serial interface. (e) ss20 this is the chip select input pin of the serial interface. (f) rxd20, txd20 these are the serial data i/o pins of the asynchronous serial interface.
chapter 3 pin functions ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 49 (g) asck20 this is the serial clock input pin of the asynchronous serial interface. caution when using p20 to p26 as serial interf ace pins, the i/o mode and output latch must be set according to the function to be used. for details of the setting, see table 14-2 operating mode settings of serial interface 20. 3.2.4 p30 to p33 (port 3) these pins constitute a 4-bit i/o port. in addition, these pins function as the timer i/o and the external interrupt input. port 3 can be set to the following operation modes in 1-bit units. (1) port mode in port mode, p30 to p33 function as a 4-bit i/o port. po rt 3 can be set to input or output mode in 1-bit units by using port mode register 3 (pm3). whether to use the on-chip pull-up resistor can be specified in 1-bit units by using pull-up resistor opti on register b3 (pub3), regardless of the setting of port mode register 3 (pm3). (2) control mode in this mode, p30 to p33 function as t he timer i/o and the external interrupt input. (a) ti81 this is the external clock input pi n for 8-bit timer/event counter 81. (b) to90, to81, to82 these are the output pins of 16-bit timer 90, 8-bit timer/ev ent counter 81, and 8-bit timer 82. (c) cpt90 this is the capture edge input pin of 16-bit timer 90. (d) bzo90 this is the buzzer output pin of 16-bit timer 90. (e) intp0 to intp3 these are external interrupt input pins for wh ich the valid edge (rising edge, falling edge, and both the rising and falling edges) can be specified. 3.2.5 p50 to p53 (port 5) these pins constitute a 4-bit n-ch open-drain i/o port. port 5 can be set to input or output mode in 1-bit units by using port mode register 5 (pm5). for a mask rom version, whether a pull-up resistor is to be incorporated can be specified by a mask option.
chapter 3 pin functions ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 50 3.2.6 p60 to p67 (port 6) these pins constitute an 8-bit input-onl y port. they can function as a/d conv erter input pins as well as a general- purpose input port. (1) port mode in port mode, p60 to p67 function as an 8-bit input-only port. (2) control mode in control mode, p60 to p67 function as a/d converter analog inputs (ani0 to ani7). 3.2.7 reset a low-level active system reset signal is input to this pin. 3.2.8 x1, x2 these pins are used to connect a crystal re sonator for main system clock oscillation. to supply an external clock, input the clo ck to x1 and input the inverted signal to x2. 3.2.9 xt1, xt2 these pins are used to connect a crystal re sonator for subsystem clock oscillation. to supply an external clock, input the clock to xt1 and input the inverted signal to xt2. 3.2.10 av dd analog power supply pin of the a/ d converter. always use the sa me potential as that of the v dd0 pin even when the a/d converter is not used. 3.2.11 av ss this is a ground potential pin of t he a/d converter. always use the same potential as that of the v ss0 pin even when the a/d converter is not used. 3.2.12 av ref this is the a/d converter reference voltage input pin. when t he a/d converter is not used, connect this pin to v dd0 or v ss0 . 3.2.13 v dd0 , v dd1 v dd0 is a positive power supply pin for ports. v dd1 is a positive power supply pin for other than ports. 3.2.14 v ss0 , v ss1 v ss0 is a ground potential for ports pin. v ss1 is a ground potential pin for other than ports. 3.2.15 v pp (flash memory version only) high voltage application pin for flash memory pr ogramming mode setting and program write/verify. connect this pin in either of the following ways. ? independently connect to a 10 k ? pull-down resistor. ? by using a jumper on the board, c onnect directly to the dedicated flas h programmer in the programming mode or to v ss in the normal operation mode.
chapter 3 pin functions ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 51 3.2.16 ic0 (mask rom version only) the ic0 (internally connected) pin is used to set the pd789167 and 789177 subseries to test mode before shipment. in normal operation mode, directly connect this pin to the v ss0 or v ss1 pin with as short a wiring length as possible. if a potential difference is gener ated between the ic0 pin and v ss0 or v ss1 pin due to a long wiring length or external noise superimposed on the ic0 pin, the user program may not run correctly. ? directly connect the ic0 pin to the v ss0 or v ss1 pin. v ss0 , v ss1 ic0 keep short 3.2.17 ic3 the ic3 pin is internally connected. leave this pin open.
chapter 3 pin functions ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 52 3.3 pin i/o circuits and recomme nded connection of unused pins the i/o circuit type of each pin and recommended connec tion of unused pins are shown in table 3-1. for the i/o circuit configuration of each type, refer to figure 3-1 . table 3-1. types of i/o circuits for each pi n and recommended connecti on of unused pins pin name i/o circuit type i/o re commended connection of unused pins p00 to p05 p10, p11 5-h p20/sck20/asck20 p21/so20/txd20 p22/si20/rxd20 8-c input: independently connect to v dd0 , v dd1 v ss0 , or v ss1 via a resistor. output: leave open. p23 p24 13-x input: independently connect to v dd0 or v dd1 via a resistor. output: leave open. p25/ti80/ss20 p26/to80 input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 via a resistor. output: leave open. p30/intp0/ti81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 8-c input: independently connect to v ss0 or v ss1 via a resistor. output: leave open. p50 to p53 (mask rom version) 13-u p50 to p53 (flash memory version) 13-t i/o input: connect to v ss0 or v ss1 . output: leave open. p60/ani0 to p67/ani7 9-c input connect directly to v dd0 , v dd1 , v ss0 , or v ss1 . xt1 input connect directly to v ss0 or v ss1 . xt2 ? ? leave open. reset 2 input ? ic0 (mask rom version) connect directly to v ss0 or v ss1 . ic3 leave open. v pp (flash memory version) ? ? independently connect via a 10 k ? pull-down resistor, or connect directly to v ss0 or v ss1 .
chapter 3 pin functions ( pd789167 and 789177 subseries) user?s manual u14186ej5v0ud 53 figure 3-1. pin i/o circuits schmitt-triggered input with hysteresis characteristics type 2 in type 5-h pull-up enable data output disable input enable v dd0 p-ch v dd0 p-ch in/out n-ch type 13-u v ss0 v ss0 type 8-c pull-up enable data output disable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 type 13-t type 13-x output data output disable in/out v dd0 n-ch input buffer with intermediate withstanding voltage input enable pull-up resistor (mask option) v ss0 output data output disable in/out n-ch input buffer with intermediate withstanding voltage input enable v ss0 output data output disable in/out input buffer with 5 v withstanding voltage comparator n-ch type 9-c in comparator + ? v ref (threshold voltage) av ss p-ch n-ch input enable
user?s manual u14186ej5v0ud 54 chapter 4 pin functions ( pd789167y and 789177y subseries) 4.1 pin function list (1) port pins pin name i/o function after reset alternate function p00 to p05 i/o port 0 6-bit i/o port i/o mode can be specif ied in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by means of pull- up resistor option register 0 (pu0). input ? p10, p11 i/o port 1 2-bit i/o port i/o mode can be specif ied in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by means of pull- up resistor option register 0 (pu0). input ? p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 scl0 p24 sda0 p25 ti80/ss20 p26 i/o port 2 7-bit i/o port i/o mode can be specif ied in 1-bit units. for p20 to p22, p25, and p26, an on-chip pull-up resistor can be specified by means of pu ll-up resistor option register b2 (pub2). only p23 and p24 can be used as n-ch open-drain i/o port pins. input to80 p30 intp0/ti81/cpt90 p31 intp1/to81 p32 intp2/to90 p33 i/o port 3 4-bit i/o port i/o mode can be specif ied in 1-bit units. an on-chip pull-up resistor can be specified by means of pull- up resistor option register b3 (pub3). input intp3/to82/bzo90 p50 to p53 i/o port 5 4-bit n-ch open-drain i/o port i/o mode can be specif ied in 1-bit units. for a mask rom version, an on-chip pull-up resistor can be specified by the mask option. input ? p60 to p67 input port 6 8-bit input-only port input ani0 to ani7
chapter 4 pin functions ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 55 (2) non-port pins pin name i/o function after reset alternate function intp0 p30/ti81/cpt90 intp1 p31/to81 intp2 p32/to90 intp3 input external interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified input p33/to82/bzo90 si20 input serial data input to serial interface input p22/rxd20 so20 output serial data output from serial interface input p21/txd20 sck20 i/o serial clock i/o for se rial interface input p20/asck20 ss20 input chip select i nput to serial interface input p25/ti80 asck20 input serial clock i nput for asynchronous serial interface input p20/sck20 rxd20 input serial data input for asynch ronous serial interface input p22/si20 txd20 output serial data output for asyn chronous serial interface input p21/so20 scl0 i/o smb0 clock i/o input p23 sda0 i/o smb0 data i/o input p24 ti80 input external count clock input to 8-bi t timer/event counter (tm80) input p25/ss20 ti81 input external count clock input to 8-bit ti mer/event counter (tm81) input p30/intp0/cpt90 to80 output 8-bit timer/event counter (tm80) output input p26 to81 output 8-bit timer/event counter (tm81) output input p31/intp1 to82 output 8-bit timer (tm82) output input p33/intp3/bzo90 to90 output 16-bit timer (tm90) output input p32/intp2 cpt90 input capture edge input input p30/intp0/ti81 bzo90 output buzzer output input p33/intp3/to82 ani0 to ani7 input a/d converter analog input input p60 to p67 av ref ? a/d converter reference voltage ? ? av ss ? a/d converter ground potential ? ? av dd ? a/d converter analog power supply ? ? x1 input ? ? x2 ? connecting crystal resonator for main system clock oscillation ? ? xt1 input ? ? xt2 ? connecting crystal resonator fo r subsystem clock oscillation ? ? reset input system reset input input ? v dd0 ? positive power supply ? ? v dd1 ? positive power supply (other than ports) ? ? v ss0 ? ground potential ? ? v ss1 ? ground potential (other than ports) ? ? ic0 ? internally connected. connect this pin directly to the v ss0 or v ss1 pin. ? ? ic2 ? internally connected. leave this pin open. ? ? v pp ? this pin is used to set fl ash memory programming mode and applies a high voltage when a program is written or verified. ? ?
chapter 4 pin functions ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 56 4.2 description of pin functions 4.2.1 p00 to p05 (port 0) these pins constitute a 6-bit i/o port and can be set to i nput or output port mode in 1- bit units by using port mode register 0 (pm0). when these pins are used as an input port, an on-chip pull- up resistor can be used by setting pull- up resistor option register 0 (pu0). 4.2.2 p10, p11 (port 1) these pins constitute a 2-bit i/o port and can be set to i nput or output port mode in 1- bit units by using port mode register 1 (pm1). when these pins are used as an input port, an on-chip pull- up resistor can be used by setting pull- up resistor option register 0 (pu0). 4.2.3 p20 to p26 (port 2) these pins constitute a 7-bit i/o port. in addition, thes e pins provide a function to perform i/o to/from the timer and to i/o the data and clock of the serial interface. port 2 can be set to the following operation modes in 1-bit units. (1) port mode in port mode, p20 to p26 function as a 7-bit i/o port. po rt 2 can be set to input or output mode in 1-bit units by using port mode register 2 (pm2). for p20 to p22, p25, and p26, whether to use on-chip pull-up resistors can be specified in 1-bit units by us ing pull-up resistor option register b2 (pub2), regardless of the setting of port mode register 2 (pm2). p23 and p24 are n-ch open-drain i/o ports. (2) control mode in this mode, p20 to p26 function as the timer i/o, the data i/o and the clock i/o of the serial interface. (a) ti80 this is the external clock input pi n for 8-bit timer/event counter 80. (b) to80 this is the timer output pin of 8-bit timer/event counter 80. (c) si20, so20 these are the serial data i/o pins of the serial interface. (d) sck20 this is the serial clock i/o pin of the serial interface. (e) ss20 this is the chip select input pin of the serial interface. (f) rxd20, txd20 these are the serial data i/o pins of the asynchronous serial interface.
chapter 4 pin functions ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 57 (g) asck20 this is the serial clock input pin of the asynchronous serial interface. (h) scl0 this is the clock i/o pin of smb0. (i) sda0 this is the data i/o pin of smb0. caution when using p20 to p26 as serial interf ace pins, the i/o mode and output latch must be set according to the function to be used. for details of the setting, see table 14-2 operating mode setting of serial interface 20. 4.2.4 p30 to p33 (port 3) these pins constitute a 4-bit i/o port. in addition, these pins function as the timer i/o and the external interrupt input. port 3 can be set to the following operation modes in 1-bit units. (1) port mode in port mode, p30 to p33 function as a 4-bit i/o port. po rt 3 can be set to input or output mode in 1-bit units by using port mode register 3 (pm3). whether to use the on-chip pull-up resistor can be specified in 1-bit units by using pull-up resistor opti on register b3 (pub3), regardless of the setting of port mode register 3 (pm3). (2) control mode in this mode, p30 to p33 function as t he timer i/o and the external interrupt input. (a) ti81 this is the external clock input pi n for 8-bit timer/event counter 81. (b) to90, to81, to82 these are the output pins of 16-bit timer 90, 8-bit timer/ev ent counter 81, and 8-bit timer 82. (c) cpt90 this is the capture edge input pin of 16-bit timer 90. (d) bzo90 this is the buzzer output pin of 16-bit timer 90. (e) intp0 to intp3 these are external interrupt input pins for wh ich the valid edge (rising edge, falling edge, and both the rising and falling edges) can be specified. 4.2.5 p50 to p53 (port 5) these pins constitute a 4-bit n-ch open-drain i/o port. port 5 can be set to input or output mode in 1-bit units by using port mode register 5 (pm5). for a mask rom version, whether a pull-up resistor is to be incorporated can be specified by a mask option.
chapter 4 pin functions ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 58 4.2.6 p60 to p67 (port 6) these pins constitute an 8-bit input-onl y port. they can function as a/d conv erter input pins as well as a general- purpose input port. (1) port mode in port mode, p60 to p67 function as an 8-bit input-only port. (2) control mode in control mode, p60 to p67 function as a/d converter analog inputs (ani0 to ani7). 4.2.7 reset a low-level active system reset signal is input to this pin. 4.2.8 x1, x2 these pins are used to connect a crystal re sonator for main system clock oscillation. to supply an external clock, input the clo ck to x1 and input the inverted signal to x2. 4.2.9 xt1, xt2 these pins are used to connect a crystal re sonator for subsystem clock oscillation. to supply an external clock, input the clock to xt1 and input the inverted signal to xt2. 4.2.10 av dd analog power supply pin of the a/ d converter. always use the sa me potential as that of the v dd0 pin even when the a/d converter is not used. 4.2.11 av ss this is a ground potential pin of t he a/d converter. always use the same potential as that of the v ss0 pin even when the a/d converter is not used. 4.2.12 av ref this is the a/d converter reference voltage input pin. when t he a/d converter is not used, connect this pin to v dd0 or v ss0 . 4.2.13 v dd0 , v dd1 v dd0 is a positive power supply pin for ports. v dd1 is a positive power supply pin for other than ports. 4.2.14 v ss0 , v ss1 v ss0 is a ground potential pin for ports. v ss1 is a ground potential pin for other than ports. 4.2.15 v pp (flash memory version only) high voltage apply pin for flash memory progr amming mode setting and program write/verify. connect this pin in either of the following ways. ? independently connect to a 10 k ? pull-down resistor. ? by using a jumper on the board, c onnect directly to the dedicated flas h programmer in the programming mode or to v ss in the normal operation mode.
chapter 4 pin functions ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 59 4.2.16 ic0 (mask rom version only) the ic0 (internally connected) pin is used to set the pd789167y and 789177y subseries to test mode before shipment. in normal operation mode, directly connect this pin to the v ss0 or v ss1 pin with as short a wiring length as possible. if a potential difference is gener ated between the ic0 pin and v ss0 or v ss1 pin due to a long wiring length or external noise superimposed on the ic0 pin, the user program may not run correctly. ? directly connect the ic0 pin to the v ss0 or v ss1 pin. v ss0 , v ss1 ic0 keep short 4.2.17 ic2 the ic2 pin is internally c onnected. leave this pin open.
chapter 4 pin functions ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 60 4.3 pin i/o circuits and recomme nded connection of unused pins the i/o circuit type of each pin and recommended connec tion of unused pins are shown in table 4-1. for the i/o circuit configuration of each type, refer to figure 4-1 . table 4-1. types of i/o circuits for each pi n and recommended connecti on of unused pins pin name i/o circuit type i/o re commended connection of unused pins p00 to p05 p10, p11 5-h p20/sck20/asck20 p21/so20/txd20 p22/si20/rxd20 8-c input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 via a resistor. output: leave open. p23/scl0 p24/sda0 13-x input: independently connect to v dd0 or v dd1 via a resistor. output: leave open. p25/ti80/ss20 p26/to80 input: independently connect to v dd0 , v dd1 , v ss0 , or v ss1 via a resistor. output: leave open. p30/intp0/ti81/cpt90 p31/intp1/to81 p32/intp2/to90 p33/intp3/to82/bzo90 8-c input: independently connect to v ss0 or v ss1 via a resistor. output: leave open. p50 to p53 (mask rom version) 13-u p50 to p53 (flash memory version) 13-t i/o input: connect to v ss0 or v ss1 . output: leave open. p60/ani0 to p67/ani7 9-c input connect directly to v dd0 , v dd1 , v ss0 , or v ss1 . xt1 input connect directly to v ss0 or v ss1 . xt2 ? ? leave open. reset 2 input ? ic0 (mask rom version) connect directly to v ss0 or v ss1 . ic2 leave open. v pp (flash memory version) ? ? independently connect via a 10 k ? pull-down resistor, or connect directly to v ss0 or v ss1 .
chapter 4 pin functions ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 61 figure 4-1. pin i/o circuits schmitt-triggered input with hysteresis characteristics type 2 in type 5-h pull-up enable data output disable input enable v dd0 p-ch v dd0 p-ch in/out n-ch type 13-u v ss0 v ss0 type 8-c pull-up enable data output disable v dd0 p-ch v dd0 p-ch in/out n-ch v ss0 type 13-t type 13-x output data output disable in/out v dd0 n-ch input buffer with intermediate withstanding voltage input enable pull-up resistor (mask option) v ss0 output data output disable in/out n-ch input buffer with intermediate withstanding voltage input enable v ss0 output data output disable in/out input buffer with 5 v withstanding voltage comparator n-ch type 9-c in comparator + ? v ref (threshold voltage) av ss p-ch n-ch input enable
user?s manual u14186ej5v0ud 62 chapter 5 cpu architecture 5.1 memory space products in the pd789167, 789177, 789167y, and 789177y subseries can each access up to 64 kb of memory space. figures 5-1 through 5-3 show the memory maps. figure 5-1. memory map ( pd789166, pd789176, pd789166y, and pd789176y) special-function registers 256 8 bits internal high-speed ram 512 8 bits program memory space data memory space program area program area callt table area reserved vector table area internal rom 16,384 8 bits ffffh ff00h feffh fd00h fcffh 3fffh 0080h 007fh 0040h 003fh 0024h 0023h 0000h 0000h 4000h 3fffh
chapter 5 cpu architecture user?s manual u14186ej5v0ud 63 figure 5-2. memory map ( pd789167, pd789177, pd789167y, and pd789177y) special-function registers 256 8 bits internal high-speed ram 512 8 bits program memory space data memory space program area program area callt table area reserved vector table area internal rom 24,576 8 bits ffffh ff00h feffh fd00h fcffh 5fffh 0080h 007fh 0040h 003fh 0024h 0023h 0000h 0000h 6000h 5fffh
chapter 5 cpu architecture user?s manual u14186ej5v0ud 64 figure 5-3. memory map ( pd78f9177, pd78f9177y, pd78f9177a, and pd78f9177ay) special-function registers 256 8 bits internal high-speed ram 512 8 bits program memory space data memory space program area program area callt table area reserved vector table area internal flash memory 24,576 8 bits ffffh ff00h feffh fd00h fcffh 5fffh 0080h 007fh 0040h 003fh 0024h 0023h 0000h 0000h 6000h 5fffh
chapter 5 cpu architecture user?s manual u14186ej5v0ud 65 5.1.1 internal program memory space the internal program memory space stores programs and table data. this space is usually addressed by the program counter (pc). the pd789167, 789177, 789167y, and 789177y subseries provide the following internal rom (or flash memory) containing the following capacities. table 5-1. internal rom capacity internal rom part number structure capacity pd789166, pd789176, pd789166y, pd789176y 16,384 8 bits pd789167, pd789177, pd789167y, pd789177y mask rom 24,576 8 bits pd78f9177, pd78f9177y, pd78f9177a, pd 78f9177ay flash memory 24,576 8 bits the following areas are allocated to t he internal program memory space. (1) vector table area a 36-byte area of addresses 0000h to 0023h is reserved as a vector table area. this area stores program start addresses to be used when branching by reset input or interrupt request generation. of a 16-bit program address, the lower 8 bi ts are stored in an even address, and the higher 8 bits are stored in an odd address. table 5-2. vector table vector table address interrupt request vector table address interrupt request 0000h reset input 0014h intwti 0004h intwdt 0016h inttm80 0006h intp0 0018h inttm81 0008h intp1 001ah inttm82 000ah intp2 001ch inttm90 000ch intp3 001eh intsmb0 note 000eh intsr20/intcsi20 0020h intsmbov0 note 0010h intst20 0022h intad0 0012h intwt note for the pd789167y and 789177y subseries only (2) callt instruction table area the subroutine entry address of a 1-byte call instruction (callt ) can be stored in a 64-byte area of addresses 0040h to 007fh.
chapter 5 cpu architecture user?s manual u14186ej5v0ud 66 5.1.2 internal data memory (internal high-speed ram) space the pd789167, 789177, 789167y, and 789177y subseries provi de a 512-byte internal high-speed ram. the internal high-speed ram can also be used as a stack memory. 5.1.3 special-function register (sfr) area special-function registers (sfrs) of on-chip peripheral hardware are allo cated to an area of ff00h to ffffh (see table 5-3 ). 5.1.4 data memory addressing each of the pd789167, 789177, 789167y, 789177y subseries is pr ovided with a wide range of addressing modes to make memory manipulation as efficient as possible. a data memory area (fd00h to ffffh) can be accessed using a unique addressing mode according to its use, su ch as a special-function r egister (sfr). figures 5- 4 through 5-6 illustrate the data memory addressing modes. figure 5-4. data memory addressing modes ( pd789166, pd789176, pd789166y, and pd789176y) special-function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits internal rom 16,384 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing reserved ffffh ff20h ff1fh ff00h feffh fe20h fe1fh fd00h fcffh 4000h 3fffh 0000h
chapter 5 cpu architecture user?s manual u14186ej5v0ud 67 figure 5-5. data memory addressing modes ( pd789167, pd789177, pd789167y, and pd789177y) special-function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits internal rom 24,576 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing reserved ffffh ff20h ff1fh ff00h feffh fe20h fe1fh fd00h fcffh 6000h 5fffh 0000h
chapter 5 cpu architecture user?s manual u14186ej5v0ud 68 figure 5-6. data memory addressing modes ( pd78f9177, pd78f9177y, pd78f9177a, and pd78f9177ay) special-function registers (sfr) 256 8 bits internal high-speed ram 512 8 bits internal flash memory 24,576 8 bits direct addressing register indirect addressing based addressing sfr addressing short direct addressing reserved ffffh ff20h ff1fh ff00h feffh fe20h fe1fh fd00h fcffh 6000h 5fffh 0000h
chapter 5 cpu architecture user?s manual u14186ej5v0ud 69 5.2 processor registers the pd789167, 789177, 789167y, and 789177y subseries provide t he following on-chip processor registers. 5.2.1 control registers the control registers have special f unctions to control the program sequenc e statuses and stack memory. the control registers include a pr ogram counter, a program stat us word, and a stack pointer. (1) program counter (pc) the program counter is a 16-bit r egister which holds the address info rmation of the next program to be executed. in normal operation, the pc is automat ically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is execut ed, immediate data or r egister contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 5-7. program counter configuration (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents ar e automatically stacked upon interr upt request generation or push psw instruction execution and ar e automatically restored upon execution of the reti and pop psw instructions. reset input sets the psw to 02h. figure 5-8. program status word configuration 0 15 pc14 pc15 pc pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 70 ie z 0 ac 0 0 1 cy psw
chapter 5 cpu architecture user?s manual u14186ej5v0ud 70 (a) interrupt enable flag (ie) this flag controls interrupt request a cknowledgment operati ons of the cpu. when ie = 0, the interrupt disabled (d i) status is set. all interrupt requests except non-maskable interrupt are disabled. when ie = 1, the interrupt enabled (ei) status is set. interrupt reques t acknowledgment is controlled with an interrupt mask flag for various interrupt sources. this flag is reset to 0 upon di instruction executi on or interrupt acknowledgment and is set to 1 upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set to 1. it is reset to 0 in all other cases. (c) auxiliary carry flag (ac) if the operation result has a carry from bi t 3 or a borrow at bit 3, this flag is set to 1. it is reset to 0 in all other cases. (d) carry flag (cy) this flag stores an overflow or underfl ow that occurs upon add/subtract inst ruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution.
chapter 5 cpu architecture user?s manual u14186ej5v0ud 71 (3) stack pointer (sp) this is a 16-bit register used to hold the start address of the memory stack area. only the internal high- speed ram area can be set as the stack area. figure 5-9. stack pointer configuration the sp is decremented ahead of writing (saving) to the stack me mory and is incremented after reading (restoring) from the stack memory. each stack operation saves/restores dat a as shown in figures 5-10 and 5-11. caution since reset input makes sp contents undefine d, be sure to initialize the sp before using the stack. figure 5-10. data to be saved to stack memory interrupt psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp _ 2 sp _ 2 call, callt instructions push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 register pair higher figure 5-11. data to be restored from stack memory reti instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower ret instruction pop rp instruction sp pc7 to pc0 register pair higher sp + 1 sp sp + 2 sp sp + 1 sp sp + 2 sp sp + 1 sp + 2 sp sp + 3 0 15 sp14 sp15 sp sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0
chapter 5 cpu architecture user?s manual u14186ej5v0ud 72 5.2.2 general-purpose registers the general-purpose register s consist of eight 8-bit registers (x, a, c, b, e, d, l, and h). in addition that each register can be us ed as an 8-bit register, two 8-bit regi sters in pairs can be used as a 16-bit register (ax, bc, de, and hl). they can be described in terms of functional names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). figure 5-12. general-purpo se register configuration (a) absolute names r0 15 0 7 0 16-bit processing 8-bit processing rp3 rp2 rp1 rp0 r1 r2 r3 r4 r5 r6 r7 (b) functional names x 15 0 7 0 16-bit processing 8-bit processing hl de bc ax a c b e d l h
chapter 5 cpu architecture user?s manual u14186ej5v0ud 73 5.2.3 special-function registers (sfr) unlike a general-purpose register, each special-function register has a special function. they are allocated to the 256-byte area ff00h to ffffh. the special-function register s can be manipulated, like t he general-purpose registers, with operation, transfer, and bit manipulation instructions. manipulatable bit units (1 , 8, and 16) differ depending on the special-function register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describes a symbol reserved by the assembler for the 1- bit manipulation instructi on operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describes a symbol reserved by the assembler for the 8-bit manipulation instruct ion operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describes a symbol reserved by the assembler for the 16-bit manipulation instruct ion operand. when specifying an address, describe an even address. table 5-3 lists the special-function registers. the meanings of the sym bols in this table are as follows. ? symbol indicates the addresses of the implem ented special-function registers. t he symbols shown in this column are reserved words in the assembler, and have already been defi ned as sfr variables by t he #pragma sfr directive in the c compiler. therefor e, these symbols can be used as instructi on operands if an assembler or integrated debugger is used. ? r/w indicates whether the special-functi on register can be read or written. r/w: read/write r: read only w: write only ? bit units for manipulation indicates the bit units (1, 8, and 16) in which the special-function regi ster can be manipulated. ? after reset indicates the status of the special-function register w hen the reset signal is input.
chapter 5 cpu architecture user?s manual u14186ej5v0ud 74 table 5-3. special-function registers (1/2) bit units for manipulation address special-function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff00h port 0 p0 ? ff01h port 1 p1 ? ff02h port 2 p2 ? ff03h port 3 p3 ? ff05h port 5 p5 r/w ? ff06h port 6 p6 ? 00h ff10h mul0l ff11h 16-bit multiplication result storage register 0 mul0h mul0 ? ? notes 2, 3 ff14h ff15h a/d conversion result register 0 adcr0 r ? note 1 note 2 undefined ff16h cr90l ff17h 16-bit compare register 90 cr90h cr90 w ? ? notes 2, 3 ffffh ff18h tm90l ff19h 16-bit timer counter 90 tm90h tm90 ? ? notes 2, 3 0000h ff1ah tcp90l ff1bh 16-bit capture register 90 tcp90h tcp90 r ? ? notes 2, 3 undefined ff20h port mode register 0 pm0 ? ff21h port mode register 1 pm1 ? ff22h port mode register 2 pm2 ? ff23h port mode register 3 pm3 ? ff25h port mode register 5 pm5 ? ffh ff32h pull-up resistor option register b2 pub2 ? ff33h pull-up resistor option register b3 pub3 ? ff42h timer clock sele ction register 2 tcl2 ? ? ff48h 16-bit timer mode control register 90 tmc90 ? ff49h buzzer output control register 90 bzc90 ? ff4ah watch timer mode control register wtm r/w ? 00h ff50h 8-bit compare register 80 cr80 w ? ? undefined ff51h 8-bit timer counter 80 tm80 r ? ? ff53h 8-bit timer mode control register 80 tmc80 r/w ? 00h notes 1. when using this register with an 8-bit a/d converter ( pd789167 or 789167y subseries), the register can be accessed in 8-bit units. at this time, the address is ff15h. when using this register with a 10-bit a/d converter ( pd789177 or 789177y subseries), the register can be accessed only in 16-bit units. when the pd78f9177 or pd78f9177a, the flash memory counterpart of the pd789166 or pd789167, is used, the register c an be accessed in 8-bit units. however, only an object file assembled with the pd789166 or pd789167 can be used. the same is also true for the pd78f9177y or pd78f9177ay, the flash memo ry counterpart of the pd789166y or pd789167y. when the pd78f9177y or pd78f9177ay is used, the regi ster can be accessed in 8-bit units. however, only an object file assembled with the pd789166y and pd789167y can be used. 2. 16-bit access is allowed only with short direct addressing. 3. mul0, cr90, tm90, and tcp90 are designed only for 16- bit access. with direct addressing, however, they can also be accessed in 8-bit mode.
chapter 5 cpu architecture user?s manual u14186ej5v0ud 75 table 5-3. special-function registers (2/2) bit units for manipulation address special-function register (sfr) name symbol r/w 1 bit 8 bits 16 bits after reset ff54h 8-bit compare register 81 cr81 w ? ? undefined ff55h 8-bit timer counter 81 tm81 r ? ? ff57h 8-bit timer mode control register 81 tmc81 r/w ? 00h ff58h 8-bit compare register 82 cr82 w ? ? undefined ff59h 8-bit timer counter 82 tm82 r ? ? ff5bh 8-bit timer mode control register 82 tmc82 ? ff70h asynchronous serial interface mode register 20 asim20 r/w ? ff71h asynchronous serial interface status register 20 asis20 r ? ff72h serial operation mode register 20 csim20 ? ff73h baud rate generator control register 20 brgc20 r/w ? ? 00h transmission shift register 20 txs20 w ? ? ffh ff74h reception buffer register 20 rxb2 0 sio20 r ? ? undefined ff78h smb control register 0 note smbc0 r/w ? ff79h smb status register 0 note smbs0 r ? ff7ah smb clock selection register 0 note smbcl0 ? ff7bh smb slave address register 0 note smbsva0 ? 00h ff7ch smb mode register 0 note smbm0 ? 20h ff7dh smb input level setting register 0 note smbvi0 ? ff7eh smb shift register 0 note smb0 ? ff80h a/d converter mode register 0 adm0 ? ff84h a/d input selection register 0 ads0 r/w ? 00h ffd0h multiplication data register a0 mra0 ? ffd1h multiplication data register b0 mrb0 w ? undefined ffd2h multiplier control register 0 mulc0 ? ffe0h interrupt request flag register 0 if0 ? ffe1h interrupt request flag register 1 if1 ? 00h ffe4h interrupt mask flag register 0 mk0 ? ffe5h interrupt mask flag register 1 mk1 ? ffh ffech external interrupt mode register 0 intm0 ? ? ffedh external interrupt mode register 1 intm1 ? ? fff0h suboscillation mode register sckm ? fff2h subclock control register css ? fff7h pull-up resistor option register 0 pu0 ? fff9h watchdog timer mode register wdtm ? 00h fffah oscillation stabilization time selection register osts ? ? 04h fffbh processor clock control register pcc r/w ? 02h note for the pd789167y and 789177y subseries only
chapter 5 cpu architecture user?s manual u14186ej5v0ud 76 5.3 instruction address addressing an instruction address is determined by the program counter (p c) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an in struction to be fetched each time another instruction is ex ecuted. when a branch instruct ion is executed, the branch destination information is set to the pc and branched by the following addressing (f or details of each instruction, refer to 78k/0s series instruction user?s manual (u11047e) ). 5.3.1 relative addressing [function] the value obtained by adding 8-bit immedi ate data (displacement value: jdis p8) of an instruction code to the start address of the following instruction is transfe rred to the program counter (pc) and branched. the displacement value is treated as signed two?s complement data (?128 to +127) and bit 7 becomes a sign bit. in other words, the range of branch in relative addressing is between ?128 and +127 of the st art address of the following instruction. this function is carried out when the br $addr16 instruct ion or a conditional branch instruction is executed. [illustration] 15 0 pc 15 0 s 15 0 pc + 876 jdisp8 when s = 0, indicates all bits "0". ... pc is the start address of the next instruction of a br instruction. when s = 1, indicates all bits "1".
chapter 5 cpu architecture user?s manual u14186ej5v0ud 77 5.3.2 immediate addressing [function] immediate data in the instructi on word is transferred to the pr ogram counter (pc) and branched. this function is carried out when the call !addr 16 and br !addr16 instruct ions are executed. call !addr16 and br !addr16 instru ctions can be used to branch to all the memory spaces. [illustration] in case of call !addr16 and br !addr16 instructions 15 0 pc 87 70 call or br low addr. high addr.
chapter 5 cpu architecture user?s manual u14186ej5v0ud 78 5.3.3 table indirect addressing [function] table contents (branch destinat ion address) of the particular location to be addressed by the immediate data of an instruction code from bit 1 to bit 5 are trans ferred to the program c ounter (pc) and branched. table indirect addressing is carried out when the callt [addr5] inst ruction is executed. this instruction can be used to branch to all the memory spaces according to the address stored in the me mory table 40h to 7fh. [illustration] 15 1 15 0 pc 70 lower addr. higher addr. memory (table) effective address + 1 effective address 01 00000000 87 87 65 0 0 0 01 765 10 ta 4 ? 0 instruction code 5.3.4 register addressing [function] register pair (ax) contents to be spec ified with an instruction word are trans ferred to the program counter (pc) and branched. this function is carried out when t he br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87
chapter 5 cpu architecture user?s manual u14186ej5v0ud 79 5.4 operand address addressing the following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 direct addressing [function] the memory indicated by immediate data in an instruction word is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !fe00h; when setting !addr16 to fe00h instruction code 0 0 1 0 1 0 0 1 op code 0 0 0 0 0 0 0 0 00h 1 1 1 1 1 1 1 0 feh [illustration] 70 op code addr16 (lower) addr16 (higher) memory
chapter 5 cpu architecture user?s manual u14186ej5v0ud 80 5.4.2 short direct addressing [function] the memory to be manipulated in the fixed space is di rectly addressed with 8-bit dat a in an instruction word. the fixed space where this addressing is applied to is the 256-byte space fe20h to ff1fh. an internal high- speed ram and special-function registers (sfr) ar e mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area (ff00h to ff1fh) where short direct addressi ng is applied is a part of t he overall sfr area. in this area, ports which are frequently accessed in a program and a compare r egister of the timer counter are mapped, and these sfrs can be manipulated with a small num ber of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effe ctive address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. see [illustration] below. [operand format] identifier description saddr label or fe20h to ff1fh immediate data saddrp label or fe20h to ff1fh i mmediate data (even address only) [description example] mov fe90h, #50h; when setting saddr to fe90h and the immediate data to 50h instruction code 1 1 1 1 0 1 0 1 op code 1 0 0 1 0 0 0 0 90h (saddr-offset) 0 1 0 1 0 0 0 0 50h (immediate data) [illustration] 15 0 short direct memory effective address 1 111111 8 0 7 op code saddr-offset when 8-bit immediate data is 20h to ffh, = 0. when 8-bit immediate data is 00h to 1fh, = 1.
chapter 5 cpu architecture user?s manual u14186ej5v0ud 81 5.4.3 special-function register (sfr) addressing [function] the memory-mapped special-function regi sters (sfr) are addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 256-byte space ff00h to ffffh. however, the sfrs mapped at ff00h to ff1fh can also be accessed with short direct addressing. [operand format] identifier description sfr special-function register name [description example] mov pm0, a; when selecting pm0 for sfr instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [illustration] 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1
chapter 5 cpu architecture user?s manual u14186ej5v0ud 82 5.4.4 register addressing [function] the general-purpose register s are accessed as operands. the general- purpose register to be accessed is specified by the register s pecification code and functional nam e in the instruction code. register addressing is carried out when an instruction with the following operand forma t is executed. when an 8-bit register is specified, one of the eight registers is specified wit h 3 bits in the instruction code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl ?r? and ?rp? can be described with absolut e names (r0 to r7 and rp0 to rp3) as well as function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl). [description example] mov a, c; when selecting the c register for r instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 register specify code incw de; when selecting the de register pair for rp instruction code 1 0 0 0 1 0 0 0 register specify code
chapter 5 cpu architecture user?s manual u14186ej5v0ud 83 5.4.5 register indirect addressing [function] the memory is addressed with the contents of the r egister pair specified as an oper and. the register pair to be accessed is specified with t he register pair specify code in the instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [de], [hl] [description example] mov a, [de]; when selecting register pair [de] instruction code 0 0 1 0 1 0 1 1 [illustration] 15 0 8 d 7 e 0 7 7 0 a de the contents of addressed memory are transferred memory address specified by register pair de
chapter 5 cpu architecture user?s manual u14186ej5v0ud 84 5.4.6 based addressing [function] 8-bit immediate data is added to the cont ents of the base register, that is, t he hl register pair, and the sum is used to address the memory. addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description ? [hl+byte] [description example] mov a, [hl+10h]; when setting byte to 10h instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 5.4.7 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automat ically employed when the push, pop, subroutine call, and return instructions are executed or t he register is saved/reset upon generation of an interrupt request. stack addressing can be used to access t he internal high-speed ram area only. [description example] in the case of push de instruction code 1 0 1 0 1 0 1 0
user?s manual u14186ej5v0ud 85 chapter 6 port functions 6.1 port functions the pd789167, 789177, 789167y, and 789177y subserie s are provided with the ports shown in figure 6-1. these ports are used to enable several types of contro l. table 6-1 lists the functions of each port. these ports, while originally designed as digital i/o ports, have alternate functions, as summarized in 3.1 pin function list ( pd789167 and 789177 subseries) and 4.1 pin function list ( pd789167y and 789177y subseries). figure 6-1. port types p30 p33 p00 p05 port 3 port 0 p50 p53 port 5 p60 p67 port 6 p20 p26 port 2 p10 p11 port 1
chapter 6 port functions user?s manual u14186ej5v0ud 86 table 6-1. port functions pin name i/o function after reset alternate function p00 to p05 i/o port 0 6-bit i/o port i/o mode can be specif ied in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by means of pull- up resistor option register 0 (pu0). input ? p10, p11 i/o port 1 2-bit i/o port i/o mode can be specif ied in 1-bit units. when used as an input port, an on- chip pull-up resistor can be specified by means of pull- up resistor option register 0 (pu0). input ? p20 sck20/asck20 p21 so20/txd20 p22 si20/rxd20 p23 scl0 note p24 sda0 note p25 ti80/ss20 p26 i/o port 2 7-bit i/o port i/o mode can be specif ied in 1-bit units. for p20 to p22, p25, and p26, an on-chip pull-up resistor can be specified by means of pu ll-up resistor option register b2 (pub2). only p23 and p24 can be used as n-ch open-drain i/o port pins. input to80 p30 intp0/ti81/cpt90 p31 intp1/to81 p32 intp2/to90 p33 i/o port 3 4-bit i/o port i/o mode can be specif ied in 1-bit units. an on-chip pull-up resistor can be specified by means of pull- up resistor option register b3 (pub3). input intp3/to82/bzo90 p50 to p53 i/o port 5 4-bit n-ch open-drain i/o port i/o mode can be specif ied in 1-bit units. for a mask rom version, an on-chip pull-up resistor can be specified by a mask option. input ? p60 to p67 input port 6 8-bit input-only port input ani0 to ani7 note for the pd789167y and 789177y subseries only
chapter 6 port functions user?s manual u14186ej5v0ud 87 6.2 port configuration ports have the following har dware configuration. table 6-2. configuration of port parameter configuration control registers port mode registers (pmm: m = 0 to 3, 5) pull-up resistor option register 0 (pu0) pull-up resistor option registers b2, b3 (pub2, pub3) ports total: 31 (cmos i/o: 17, cmos input: 8, n-ch open-drain i/o: 6) pull-up resistors ? mask rom versions total: 21 (software control: 17, mask option control: 4) ? flash memory versions total: 17 (software control only) 6.2.1 port 0 this is a 6-bit i/o port with output latches. port 0 can be set to input or output mode in 1-bit units by using port mode register 0 (pm0). when the p00 to p05 pins are used as input port pins, on-chip pull-up resistors can be connected in 6-bit units by using pull- up resistor option register 0 (pu0). reset input sets port 0 to input mode. figure 6-2 shows a block diagram of port 0. figure 6-2. block di agram of p00 to p05 internal bus wr pu0 rd wr port wr pm pu00 output latch (p00 to p05) pm00 to pm05 v dd0 p-ch p00 to p05 selector pu0: pull-up resistor option register 0 pm: port mode register rd: port 0 read signal wr: port 0 write signal
chapter 6 port functions user?s manual u14186ej5v0ud 88 6.2.2 port 1 this is a 2-bit i/o port with output latches. port 1 can be se t to input or output mode in 1-bit units by using the port mode register 1 (pm1). when the p 10 and p11 pins are used as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull- up resistor option register 0 (pu0). reset input sets port 1 to input mode. figure 6-3 shows a block diagram of port 1. figure 6-3. block diagram of p10 and p11 internal bus wr pu0 rd wr port wr pm pu01 output latch (p10, p11) pm10, pm11 v dd0 p-ch p10, p11 selector pu0: pull-up resistor option register 0 pm: port mode register rd: port 1 read signal wr: port 1 write signal
chapter 6 port functions user?s manual u14186ej5v0ud 89 6.2.3 port 2 this is a 7-bit i/o port with output latches. port 2 can be set to input or output mode in 1-bit units by using port mode register 2 (pm2). for the p20 to p22, p25, and p26 pins, on-chip pu ll-up resistors can be connected in 1-bit units by using pull-up resistor option register b2 (pub2). the port is also used as a data i/o and clock i/o to and from the serial interface, and as the timer i/o. reset input sets port 2 to input mode. figures 6-4 through 6-8 show block diagrams of port 2. caution when using the pins of port 2 as the seria l interface, the i/o and output latches must be set according to the function to be used. for deta ils of the settings, see table 14-2 operating mode settings of serial interface 20. figure 6-4. block diagram of p20 internal bus v dd0 p-ch p20/asck20/ sck20 wr pub2 rd wr port wr pm pub20 alternate function output latch (p20) pm20 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 6 port functions user?s manual u14186ej5v0ud 90 figure 6-5. block diagram of p21 internal bus v dd0 p-ch p21/txd20/ so20 wr pub2 rd wr port wr pm pub21 output latch (p21) pm21 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 6 port functions user?s manual u14186ej5v0ud 91 figure 6-6. block diagram of p22 and p25 internal bus v dd0 p-ch p22/rxd20/si20 p25/ti80/ss20 wr pub2 rd wr port wr pm pub22, pub25 alternate function output latch (p22, p25) pm22, pm25 selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 6 port functions user?s manual u14186ej5v0ud 92 figure 6-7. block diagram of p23 and p24 + rd wr port wr pm internal bus alternate function note alternate function note selector output latch (p23, p24) pm23, pm24 n-ch comparator reference signal input switch signal p23/scl0 note p24/sda0 note pm: port mode register rd: port 2 read signal wr: port 2 write signal note this function is provided for the pd789167y and 789177y subseries only. for the pd789167 and 789177 subseries, p23 and p24 cannot be used as alternate-function pins.
chapter 6 port functions user?s manual u14186ej5v0ud 93 figure 6-8. block diagram of p26 internal bus v dd0 p-ch p26/to80 wr pub2 rd wr port wr pm pub26 output latch (p26) pm26 alternate function selector pub2: pull-up resistor option register b2 pm: port mode register rd: port 2 read signal wr: port 2 write signal
chapter 6 port functions user?s manual u14186ej5v0ud 94 6.2.4 port 3 this is a 4-bit i/o port with output latches. port 3 can be set to input or output mode in 1-bit units by using port mode register 3 (pm3). for the p30 to p33 pins, on-chip pull-up resistors can be connect ed in 1-bit units by using pull-up resistor option register b3 (pub3). the port is also used as an external interrupt input, capture input, timer output, and buzzer output. reset input sets port 3 to input mode. figures 6-9 through 6-11 show block diagrams of port 3. figure 6-9. block diagram of p30 internal bus v dd0 p-ch p30/intp0/ ti81/cpt90 wr pub3 rd wr port wr pm pub30 alternate function output latch (p30) pm30 selector pub3: pull-up resistor option register b3 pm: port mode register rd: port 3 read signal wr: port 3 write signal
chapter 6 port functions user?s manual u14186ej5v0ud 95 figure 6-10. block diagram of p31 and p32 internal bus v dd0 p-ch p31/intp1/to81 p32/intp2/to90 wr pub3 rd wr port wr pm pub31, pub32 alternate function output latch (p31, p32) pm31, pm32 selector alternate function pub3: pull-up resistor option register b3 pm: port mode register rd: port 3 read signal wr: port 3 write signal
chapter 6 port functions user?s manual u14186ej5v0ud 96 figure 6-11. block diagram of p33 internal bus v dd0 p-ch p33/intp3/ to82/bzo90 wr pub3 rd wr port wr pm pub33 alternate function output latch (p33) pm33 selector alternate function alternate function pub3: pull-up resistor option register b3 pm: port mode register rd: port 3 read signal wr: port 3 write signal
chapter 6 port functions user?s manual u14186ej5v0ud 97 6.2.5 port 5 this is a 4-bit n-ch open-drain i/o port with output latches. port 5 can be set to input or output mode in 1-bit units by using port mode register 5 (pm5). for a mask rom vers ion, whether a pull-up resistor is to be incorporated can be specified by the mask option. reset input sets port 5 to input mode. figure 6-12 shows a block diagram of port 5. figure 6-12. block di agram of p50 to p53 internal bus selector rd pm50 to pm53 p50 to p53 n-ch wr port output latch (p50 to p53) wr pm v dd0 mask option resistor mask rom version only. for flash memory version, a pull-up resistor is not incorporated. pm: port mode register rd: port 5 read signal wr: port 5 write signal caution when using port 5 of the pd78f9177 and 78f9177y as an input por t, be sure to observe the restrictions listed below. ? when v dd = 1.8 to 5.5 v use within the range of t a = 25 to 85 c ? when t a = ? 40 to 85 c use within the range of v dd = 2.7 to 5.5 v ? when t a = ? 40 to 85 c and v dd = 1.8 to 5.5 v issue three consecuti ve read instructions when reading port 5. if the above restrictions are not observed, the input value may be read incorrectly. note, however, that these restrictions do not apply when port 5 pins are used as output pins, or when the product is other than the pd78f9177 or 78f9177y.
chapter 6 port functions user?s manual u14186ej5v0ud 98 6.2.6 port 6 this is an 8-bit input port. the port is also used as an analog input to the a/d converter. figure 6-13 shows a block diagram of port 6. figure 6-13. block di agram of p60 to p67 internal bus v ref rd a/d converter p60/ani0 to p67/ani7 + ?
chapter 6 port functions user?s manual u14186ej5v0ud 99 6.3 port function control registers the following two types of register s are used to control the ports. port mode registers (pm0 to pm3, and pm5) pull-up resistor option registers (pu0, pub2, and pub3) (1) port mode registers (pm0 to pm3, and pm5) the port mode registers separately set eac h port bit to either input or output. each port mode register is set with a 1-bit or 8-bit memory manipulation instruction. reset input writes ffh into the port mode registers. when port pins are used for alternate functions, the corresponding port mode regist er and output latch must be set or reset as described in table 6-3. caution when port 3 is acting as an output port a nd its output level is changed, an interrupt request flag is set, because this port is also used as the input for an external interrupt. to use port 3 in output mode, therefore, the interr upt mask flag must be set to 1 in advance. figure 6-14. format of port mode register pmmn 0 output mode (output buffer on) input mode (output buffer off) 1 pmn pin i/o mode selection m = 0 : n = 0 to 5, m = 1 : n = 0, 1 m = 2 : n = 0 to 6, m = 3 : n = 0 to 3 m = 5 : n = 0 to 3 1 1 pm05 pm04 pm03 pm02 pm01 pm00 pm0 76 54 symbol address after reset r/w ff20h ffh r/w 3210 1 1 1 1 1 1 pm11 pm10 pm1 ff21h ffh r/w 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 ff22h ffh r/w 1 1 1 1 pm33 pm32 pm31 pm30 pm3 ff23h ffh r/w 1 1 1 1 pm53 pm52 pm51 pm50 pm5 ff25h ffh r/w
chapter 6 port functions user?s manual u14186ej5v0ud 100 table 6-3. port mode register and output latch settings for us ing alternate functions alternate function pin name name i/o pm p p25 ti80 input 1 p26 to80 output 0 0 intp0 input 1 ti81 input 1 p30 cpt90 input 1 intp1 input 1 p31 to81 output 0 0 intp2 input 1 p32 to90 output 0 0 intp3 input 1 to82 output 0 0 p33 bzo90 output 0 0 caution when using the pins of port 2 as the seria l interface, the i/o or output latch must be set according to the function to be used. for de tails of the settings, see table 14-2 operating mode settings of serial interface 20. remark : don?t care pm : port mode register p : port output latch (2) pull-up resistor option register 0 (pu0) pull-up resistor option register 0 (pu0 ) sets whether an on-chip pull-up resi stor on each port is used. on the port which is specified to use the on-chip pull-up resist or in pu0, the pull-up resi stor can be internally used only for the bits set to input mode. no on-chip pull- up resistors can be used for the bits set to output mode regardless of the setting of pu0. on-chip pull-up re sistors cannot be used even w hen the pins are used as the alternate-function output pins. pu0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears pu0 to 00h. figure 6-15. format of pull-up resistor option register 0 pu0m 0 1 pm on-chip pull-up resistor selection (m = 0, 1) on-chip pull-up resistor not used on-chip pull-up resistor used 0 0 0 0 0 0 pu01 pu00 pu0 76 54 symbol address after reset r/w fff7h 00h r/w 3 2 <1> <0> caution bits 2 to 7 must all be set to 0.
chapter 6 port functions user?s manual u14186ej5v0ud 101 (3) pull-up resistor option register s b2 and b3 (pub2 and pub3) these registers specify whet her an on-chip pull-up resistor is connect ed to each pin of ports 2 and 3. the pin specified by pub2 or pub3 is connected to on-chip pull-up resistor regardless of the setting of the port mode register. pub2 and pub3 are set with a 1-bit or 8-bit manipulation instruction. reset input clears this register to 00h. figure 6-16. format of pull-up resistor option register b2 pub2n 0 1 p2n on-chip pull-up resistor selection (n = 0 to 2, 5, 6) on-chip pull-up resistor not used on-chip pull-up resistor used 0 pub26 pub25 0 0 pub22 pub21 pub20 pub2 7 <6> <5> 4 symbol address after reset r/w ff32h 00h r/w 3 <2> <1> <0> caution bits 3, 4, and 7 must all be set to 0. figure 6-17. format of pull-up resistor option register b3 pub3n 0 1 p3n on-chip pull-up resistor selection (n = 0 to 3) on-chip pull-up resistor not used on-chip pull-up resistor used 0 0 0 0 pub33 pub32 pub31 pub30 pub3 76 54 symbol address after reset r/w ff33h 00h r/w <3> <2> <1> <0> caution bits 4 to 7 must all be set to 0.
chapter 6 port functions user?s manual u14186ej5v0ud 102 6.4 operation of port functions the operation of a port differs depending on whether the port is set to input or output mode, as described below. 6.4.1 writing to i/o port (1) in output mode a value can be written to the output la tch of a port by using a transfer inst ruction. the cont ents of the output latch can be output from the pins of the port. the data once written to t he output latch is retained until new dat a is written to the output latch. (2) in input mode a value can be written to the output latc h by using a transfer instruction. however, the status of the port pin is not changed because the out put buffer is off. the data once written to t he output latch is retained until new dat a is written to the output latch. caution a 1-bit memory manipulation instructi on is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of a port consisti ng both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined. 6.4.2 reading from i/o port (1) in output mode the contents of the out put latch can be read by using a transfer inst ruction. the content s of the output latch are not changed. (2) in input mode the status of a pin can be read by using a transfer instruction. the contents of the output latch are not changed. 6.4.3 arithmetic operation of i/o port (1) in output mode an arithmetic operation can be performed with the contents of the output latch. the re sult of the operation is written to the output latch. the contents of the out put latch are output from the port pins. the data once written to t he output latch is retained until new dat a is written to the output latch. (2) in input mode the contents of the output latch become undefined. however, the status of the pin is not changed because the output buffer is off. caution a 1-bit memory manipulation instructi on is executed to manipulate 1 bit of a port. however, this instruction accesses the port in 8-bit units. when this instruction is executed to manipulate a bit of a port consisti ng both of inputs and outputs, therefore, the contents of the output latch of the pin that is set to input mode and not subject to manipulation become undefined.
user?s manual u14186ej5v0ud 103 chapter 7 clock generator 7.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are used. ? main system clock oscillator this circuit oscillates at 1.0 to 10.0 mhz. oscilla tion can be stopped by executing the stop instruction or setting the processor clock control register (pcc). this circuit oscillates at 1.0 to 5.0 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). ? subsystem clock oscillator this circuit oscillates at 32.768 khz. oscillation can be stopped by setting the s uboscillation mode register (sckm). 7.2 clock generator configuration the clock generator consists of t he following items of hardware. table 7-1. configuration of clock generator item configuration control registers processor cl ock control register (pcc) suboscillation mode register (sckm) subclock control register (css) oscillator main system clock oscillator subsystem clock oscillator
chapter 7 clock generator user?s manual u14186ej5v0ud 104 figure 7-1. block diag ram of clock generator f xt f x prescaler f x 2 2 f xt 2 1/2 prescaler clock for peripheral hardware cpu clock (f cpu ) standby controller wait controller selector stop mcc pcc1 cls css0 internal bus suboscillation mode register (sckm) frc xt2 xt1 scc internal bus subclock control register (css) processor clock control register (pcc) subsystem clock oscillator x2 x1 main system clock oscillator watch timer
chapter 7 clock generator user?s manual u14186ej5v0ud 105 7.3 registers controlling clock generator the clock generator is controll ed by the following registers. ? processor clock control register (pcc) ? suboscillation mode register (sckm) ? subclock control register (css) (1) processor clock control register (pcc) pcc selects the cpu clock and the ratio of division. pcc is set with a 1-bit or 8-bit me mory manipulation instruction. reset input sets pcc to 02h. figure 7-2. format of processo r clock control register control of main system clock oscillator operation mcc 0 1 operation enabled operation disabled minimum instruction execution time: 2/f cpu cpu clock (f cpu ) selection note 1 css0 0 0 1 1 pcc1 0 1 0 1 at f x = 10.0 mhz note 2 or f xt = 32.768 khz operation at f x = 5.0 mhz or f xt = 32.768 khz operation f x f x /2 2 f xt /2 0.2 s 0.8 s 122 s 0.4 s 1.6 s 122 s mcc 0 0 0 0 0 pcc1 0 pcc 76 54 symbol address after reset r/w fffbh 02h r/w 3210 notes 1. the cpu clock is selected according to a combi nation of the pcc1 flag in the processor clock control register (pcc) and the css0 flag in the subclock control register (css). see 7.3 (3) subclock control register (css) . 2. expanded-specificati on products only. cautions 1. bits 0 and 2 to 6 must all be set to 0. 2. mcc can be set only when the subsystem clo ck has been selected as the cpu clock. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency
chapter 7 clock generator user?s manual u14186ej5v0ud 106 (2) suboscillation mode register (sckm) sckm specifies whether to use a feedback resistor for the subsystem clock, and c ontrols the oscillation of the clock. sckm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears sckm to 00h. figure 7-3. format of subo scillation mode register use of feedback resistor note frc 0 1 on-chip feedback resistor used on-chip feedback resistor not used control of subsystem clock oscillator operation scc 0 1 operation enabled operation disabled 0 0 0 0 0 0 frc scc sckm 76 54 symbol address after reset r/w fff0h 00h r/w 3210 note the feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid point of the supply voltage. only when the subclock is not used, the power consumption in stop mode can be further reduced by setting frc = 1. caution bits 2 to 7 must all be set to 0.
chapter 7 clock generator user?s manual u14186ej5v0ud 107 (3) subclock control register (css) css specifies whether the main system or subsystem clock oscillator is to be used. it also specifies how the cpu clock operates. css is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears css to 00h. figure 7-4. format of subclock control register cpu clock operation status cls 0 1 operation based on the (divided) main system clock operation based on the subsystem clock selection of main system or subsystem clock oscillator css0 0 1 (divided) output from the main system clock oscillator output form the subsystem clock oscillator 0 0 cls css0 0 0 0 0 css 76 54 symbol address after reset r/w fff2h 00h r/w note 3210 note bit 5 is read-only. caution bits 0 to 3, 6, and 7 must all be set to 0.
chapter 7 clock generator user?s manual u14186ej5v0ud 108 7.4 system clock oscillators 7.4.1 main system clock oscillator the main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 mhz typ.) connected across the x1 and x2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the x1 pin, and input the reversed signal to the x2 pin. figure 7-5 shows the external circuit of the main system clock oscillator. figure 7-5. external circuit of main system clock oscillator (a) crystal or ceramic osc illation (b) external clock v ss0 x1 x2 crystal or ceramic resonator external clock x1 x2 caution when using the main system or subsystem cl ock oscillator, wire in th e area enclosed by the broken lines in figures 7-5 and 7-6 as follows to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lin es. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss0 . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator.
chapter 7 clock generator user?s manual u14186ej5v0ud 109 7.4.2 subsystem clock oscillator the subsystem clock oscillator is oscillated by the cr ystal resonator (32.768 khz t yp.) connected across the xt1 and xt2 pins. an external clock can also be input to the circuit. in th is case, input the clock signal to the xt1 pin, and input the inverted signal to the xt2 pin. figure 7-6 shows the external circuit of the subsystem clock oscillator. figure 7-6. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock xt2 v ss0 xt1 32.768 khz crystal resonator external clock xt1 xt2 caution when using the main system or subsystem cl ock oscillator, wire in th e area enclosed by the broken lines in figures 7-5 and 7-6 as follows to avoid an adverse effect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. ? always make the ground point of the osc illator capacitor the same potential as v ss0 . do not ground the capacitor to a ground pattern through which a high current flows. ? do not fetch signals from the oscillator. the subsystem clock oscillator is designed as low-amplitude circuit for reducing current consumption. particular care is theref ore required with the wiring method when the subsystem clock is used.
chapter 7 clock generator user?s manual u14186ej5v0ud 110 7.4.3 examples of incorr ect oscillator connection figure 7-7 shows examples of incorrect oscillator connections. figure 7-7. examples of incorr ect oscillator connection (1/2) (a) wiring too long (b) crossed signal line v ss0 x1 x2 v ss0 x1 x2 portn (n = 0 to 3, 5, 6) (c) wiring near high alternating current (d) current flowing through ground line of oscillator (potential at points a, b, and c fluctuates) v ss0 x1 x2 high current v ss0 x1 ab c p mn v dd high current x2 remark when using the subsystem clo ck, read x1 and x2 as xt1 and xt 2, respectively, and connect a resistor to the xt2 pin in series.
chapter 7 clock generator user?s manual u14186ej5v0ud 111 figure 7-7. examples of incorr ect oscillator connection (2/2) (e) signals are fetche d (f) signal conductors of the main and subsystem clocks are parallel and near to each other v ss0 x1 x2 v ss0 x2 xt2 and x1 wiring in parallel x1 xt2 xt1 remark when using the subsystem clo ck, read x1 and x2 as xt1 and xt 2, respectively, and connect a resistor to the xt2 pin in series. caution if the x1 wire is in parallel with the xt2 wire, crosstalk noise may o ccur between the x1 and xt2, resulting in a malfunction. to avoid this, do not lay the x1 and xt2 wires in parallel. 7.4.4 scaler the scaler divides the main system clock oscillator output (f x ) and generates clocks. 7.4.5 when no subsyst em clocks are used if it is not necessary to use subsystem clocks for low power consumption operat ions and watch operations, connect the xt1 and xt2 pins as follows. xt1: connect to v ss0 or v ss1 xt2: open in this state, however, some current may leak via the internal feedback resist or of the subsystem clock oscillator when the main system clock stops. to minimize the leak age current, the internal feedback resistor can be removed by setting bit 1 (frc) of the suboscilla tion mode register (sckm). in this case, also connect the xt1 and xt2 pins as described above.
chapter 7 clock generator user?s manual u14186ej5v0ud 112 7.5 clock generator operation the clock generator generates the following clocks and controls operation modes of the cpu, such as standby mode. ? main system clock f x ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the operation of the clock gener ator is determined by the processor clo ck control register (pcc), suboscillation mode register (sckm), and subclock cont rol register (css), as follows. (a) the slow mode (0.8 s: at 10.0 mhz operation) of the main system clock is selected when the reset signal is generated (pcc = 02h). while a low level is input to the reset pin, oscillation of the main system clock is stopped. (b) three types of minimum instruction execution time (0.2 s and 0.8 s: main system clock (at 10.0 mhz operation), 122 s: subsystem clock (at 32.768 khz operati on)) can be selected by the pcc, sckm, and css settings. (c) two standby modes, stop and halt , can be used with the main system clock selected. in a system where no subsystem clock is used, setting bit 1 (frc) of sckm so that the built -in feedback resistor cannot be used reduces current drain during stop mode. in a system where a subsystem clock is used, setting the sckm bit 0 to 1 can cause the subsystem clock to stop oscillation. (d) css bit 4 (css0) can be used to select the subsystem clock so that a low cu rrent operation operation is used (122 s: at 32.768 khz operation). (e) with the subsystem clock selected, it is possible to cause the main system clock to stop oscillating by using bit 7 (mcc) of pcc. halt mode can be used, but stop mode cannot. (f) the clock for the peripheral hardw are is generated by dividing the frequency of the main system clock. the subsystem clock is supplied to 16-bit timer 90, 8-bit timer 82, and the watch timer only. so, even in standby mode, 16-bit timer 90, 8-bit timer 82, and the watch function can continue operati ng. the other hardware stops when the main system clock st ops, because it operates based on the main system clock (except for an external clock).
chapter 7 clock generator user?s manual u14186ej5v0ud 113 7.6 changing setting of s ystem clock and cpu clock 7.6.1 time required for switching between system clock and cpu clock the cpu clock can be selected by using bit 1 (pcc1) of the processor clock control register (pcc) and bit 4 (css0) of the subclock control register (css). actually, the specified clock is not selected immediately after the se tting of pcc has been changed, and the old clock is used for the duration of se veral instructions after that (see table 7-2 ). table 7-2. maximum time re quired for switching cpu clock set value before switching set value after switching css0 pcc1 css0 pcc1 css0 pcc1 css0 pcc1 0 0 0 1 1 0 4 clocks 2f x /f xt clocks (612 clocks)[306 clocks] 0 1 2 clocks f x /2f xt clocks (152 clocks)[76 clocks] 1 2 clocks 2 clocks remarks 1. two clocks are the minimum instruction execut ion time of the cpu clock before switching. 2. the values in paraentheses ( ) apply to operation at f x = 10.0 mhz or f xt = 32.768 khz. the values in brackets [ ] apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. 3. : don?t care
chapter 7 clock generator user?s manual u14186ej5v0ud 114 7.6.2 switching between system clock and cpu clock the following figure illustrates how t he cpu clock and system clock switch. figure 7-8. switching between system clock and cpu clock system clock cpu clock interrupt request signal reset v dd f x f x f xt f x slow operation fast operation subsystem clock operation fast operation wait (3.27 ms: at 10.0 mhz operaton, 6.55 ms: at 5.0 mhz operation) internal reset operation <1> the cpu is reset when the reset pin is made low on pow er application. the effect of resetting is released when the reset pin is later made high, and the main system clock starts osc illating. at this time, the time during which oscillation stabilizes (2 15 /f x ) is automatically secured. after that, the cpu starts inst ruction execution at the slow s peed of the main system clock (0.8 s: at 10.0 mhz operation). <2> after the time required for the v dd voltage to rise to the level at which the cpu can operate at the high speed has elapsed, bit 1 (pcc1) of the processor clo ck control register (pcc) and bit 4 (css0) of the subclock control register (css0) are rewritten so that the high speed oper ation can be selected. <3> when a drop of the v dd voltage is detected with an interrupt request signal, the clock is switched to the subsystem clock. (at this moment, the subsystem clock must be in the osc illation stabilized status.) <4> when a recover of the v dd voltage is detected with an in terrupt request signal, bit 7 (mcc) of pcc is set to 0 to make the main system clock start oscillating. a fter the time required for the oscillation to stabilize has elapsed, pcc1 and css0 are rewritten so t hat high-speed operation can be selected again. caution when the main system clock is stopped and the subsystem clock is operating, allow sufficient time for the oscillati on to stabilize by coding the pr ogram before switching again from the subsystem clock to the main system clock.
user?s manual u14186ej5v0ud 115 chapter 8 16-bit timer 90 8.1 16-bit timer 90 functions 16-bit timer 90 has the following functions. ? timer interrupt ? timer output ? buzzer output ? count value capture (1) timer interrupt an interrupt is generated when a count value and compare value matches. (2) timer output timer output can be controlled when a c ount value and compare value matches. (3) buzzer output buzzer output can be controlled by software. (4) count value capture the count value of 16-bit timer counter 90 (tm90) is latched into the capt ure register in synchronization with the capture trigger and retained.
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 116 8.2 16-bit timer 90 configuration 16-bit timer 90 consists of the following hardware. table 8-1. configuration of 16-bit timer 90 item configuration timer counter 16 bits 1 (tm90) registers compare register: 16 bits 1 (cr90) capture register: 16 bits 1 (tcp90) timer outputs 1 (to90) control registers 16-bit timer mode control register 90 (tmc90) buzzer output control register 90 (bzc90) port mode register 3 (pm3)
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 117 internal bus internal bus 16-bit timer mode control register 90 (tmc90) tof90 cpt900 cpt901 16-bit capture register 90 (tcp90) 16-bit counter read buffer 16-bit timer counter 90 (tm90) 16-bit compare register 90 (cr90) f x /2 2 f x /2 6 f x /2 7 f xt ctp90/intp0 /ti81/p30 toc90 tcl901 tcl900 toe90 f/f tod90 p32 output latch p33 output latch pm32 pm33 to90/intp2/ p32 inttm90 bzo90/intp3/ to82/p33 to82 output note match ovf buzzer output control register (bzc90) 3 bcs902 bcs901 bcs900 bzoe90 edge detector synchronization circuit f x write controller write controller f x /2 cpu clock selector selector selector note see figure 9-3 block diagram of 8-bit timer 82 . figure 8-1. block diagram of 16-bit timer 90
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 118 (1) 16-bit compare register 90 (cr90) the value specified in cr90 is compar ed with the count in 16-bit timer regi ster 90 (tm90). if they match, an interrupt request (inttm90) is issued by cr90. cr90 is set with an 8-bit or 16-bit memory manipulati on instruction. any value from 0000h to ffffh can be set. reset input sets cr90 to ffffh. cautions 1. cr90 is designed to be manipulated with a 16-bit memory manipulation instruction. it can also be manipulated with 8-bit memory manipulation instructions, however. when an 8-bit memory manipulation instruction is used to set cr90, it must be accessed using direct addressing. 2. to re-set cr90 during a count operation, it is necessary to disable interrupts in advance, using interrupt mask flag register 1 (mk1). it is also necessary to disable inversion of the timer output data, using 16-bi t timer mode control register 90 (tmc90). if the value in cr90 is rewritten in the inte rrupt-enabled state, an interrupt request may occur at the moment of rewrite. (2) 16-bit timer counter 90 (tm90) tm90 is used to count the number of pulses. the contents of tm90 are read with an 8-bit or 16-bit memory manipulation instruction. reset input clears tm90 to 0000h. cautions 1. the count becomes undefined when stop mode is released, because the count operation is performed during th e oscillation stabilization time. 2. tm90 is designed to be manipulated with a 16-bit memory manipulation instruction. it can also be manipulated with 8-bit memory manipulation instructions, however. when an 8-bit memory instruction is used to manipulate tm90, it must be accessed using direct addressing. 3. when an 8-bit memory ma nipulation instruction is used to manipulate tm90, the lower and higher bytes must be read as a pair, in this order. (3) 16-bit capture register 90 (tcp90) tcp90 captures the contents of tm90. it is set with an 8-bit or 16-bit memory manipulation instruction. reset input makes tcp90 undefined. caution tcp90 is designed to be manipulated with a 16-bit memory manipulation instruction. it can also be manipulated with 8-bit memory manipulation instructions, however. when an 8-bit memory manipulation instruction is u sed to manipulate tcp 90, it must be accessed using direct addressing. (4) 16-bit counter read buffer 90 this buffer is used to latch and hold the count for tm90.
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 119 8.3 registers controlling 16-bit timer 90 the following three register s control 16-bit timer 90. ? 16-bit timer mode control register 90 (tmc90) ? buzzer output control register 90 (bzc90) ? port mode register 3 (pm3) (1) 16-bit timer mode control register 90 (tmc90) 16-bit timer mode control register 90 (tmc90) controls the setting of t he count clock, c apture edge, etc. tmc90 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc90 to 00h.
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 120 figure 8-2. format of 16-bit timer mode control register 90 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 symbol address after reset r/w ff48h 00h r/w note 1 5 <6> 4321<0> 7 tof90 0 1 overflow flag control reset or cleared by software set when the 16-bit timer overflows cpt901 0 0 1 1 capture edge selection cpt900 0 1 0 1 capture operation disabled captured at the rising edge of the cpt90 pin captured at the falling edge of the cpt90 pin captured at both the rising and falling edges of the cpt90 pin toc90 0 1 timer output data inversion control inversion disabled inversion enabled toe90 0 1 16-bit timer counter 90 output control output disabled (port mode) output enabled tod90 0 1 timer output data timer output of 0 timer output of 1 16-bit time counter 90 count clock (fcl) section tcl901 0 0 1 1 tcl900 0 1 0 1 at f x = 10.0 mhz note 2 or f xt = 32.768 khz operation at f x = 5.0 mhz or f xt = 32.768 khz operation 2.5 mhz 156 khz 78.1 khz 32.768 khz f x /2 2 f x /2 6 f x /2 7 f xt 1.25 mhz 78.1 khz 39.1 khz notes 1. bit 7 is read-only. 2. expanded-specificati on products only. caution disable interrupts in advan ce by using the interrupt mask flag register (mk1) to change the data of tcl901 and tcl900. also, prevent th e timer output data fr om being inverted by setting toc90 to 1.
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 121 remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency (2) buzzer output control register 90 (bzc90) this register selects the buzzer frequency based on fcl selected with the count clo ck select bits (tcl901 and tcl900), and controls the out put of a square wave. bzc90 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears bzc90 to 00h. figure 8-3. format of buzzer output control register 90 bzoe90 buzzer port output control disable buzzer port output. enable buzzer port output. note 2 0 1 0 0 0 0 bcs902 bcs901 bcs900 bzoe90 bzc90 symbol address after reset r/w ff49h 00h r/w 6 754 bcs902 bcs901 bcs900 buzzer frequency selection 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 3 21 0 fcl/2 4 fcl/2 5 fcl/2 8 fcl/2 9 fcl/2 10 fcl/2 11 fcl/2 12 fcl/2 13 note 1 notes 1. bits 4 to 7 must all be set to 0. 2. when setting bzoe90 to 1, toe82 must be set to 0. (see figure 9-6 format of 8-bit timer mode control register 82 .) caution if the subclock is selected as the count clock (tcl901 = 1, tc l900 = 1: see figure 8-2 format of 16-bit timer mode control register 90), the subclock is not synchronized when buzzer port output is enabled. in this case, the capture function and tm90 read function are disabled. in addition, the count value of tm90 is undefined.
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 122 table 8-2. buzzer frequency of 16-bit timer 90 buzzer frequency at f x = 10.0 mhz note operation at f x = 5.0 mhz operation at f xt = 32.768 khz operation bcs902 bcs901 bcs900 fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 7 fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 7 fcl = f xt 0 0 0 156 khz 9.76 khz 4.88 khz 78.1 khz 4.88 khz 2.44 khz 2.05 khz 0 0 1 78.1 khz 4.88 khz 2.44 khz 39.1 khz 2.44 khz 1.22 khz 1.02 khz 0 1 0 9.76 khz 610 hz 305 hz 4.88 khz 305 hz 152 hz 128 hz 0 1 1 4.88 khz 305 hz 152 hz 2.44 khz 152 hz 76 hz 64 hz 1 0 0 2.44 khz 152 hz 76 hz 1.22 khz 76 hz 38 hz 32 hz 1 0 1 1.22 khz 76 hz 38 hz 610 hz 38 hz 19 hz 16 hz 1 1 0 610 hz 38 hz 19 hz 305 hz 19 hz 10 hz 8 hz 1 1 1 305 hz 19 hz 10 hz 153 hz 10 hz 5 hz 4 hz note expanded-specificati on products only. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency (3) port mode register 3 (pm3) pm3 is used to set each bit of port 3 to input or output. when the p32/intp2/to90 pin is used for timer output, reset the output latch of p32 and pm32 to 0; when the p33/intp3/to82/bzo90 pi n is used for buzzer output, note reset the output latch of p33 and pm33 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. note never output the to82 and bzo 90 signals at the same time. figure 8-4. format of port mode register 3 pm3n p3n pin i/o mode (n = 2 or 3) output mode (output buffer on) input mode (output buffer off) 0 1 1 1 1 1 pm33 pm32 pm31 pm30 pm3 symbol address after reset r/w ff23h ffh r/w 6 754 3 21 0
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 123 8.4 operation of 16-bit timer 90 8.4.1 operation as timer interrupt 16-bit timer 90 can generate interrupts repeatedly each time the free-running counter val ue reaches the value set to cr90. since this counter is not cleared and holds the count even after an inte rrupt is generated, the interval time is equal to one cycle of the count clock set in tcl901 and tcl900. to operate 16-bit timer 90 as a timer interrupt, the following settings are required. ? set count values in cr90 ? set 16-bit timer mode control register 90 (tmc90) as shown in figure 8-5. figure 8-5. settings of 16-bit timer mode cont rol register 90 for timer interrupt operation ? 0/1 0/1 0/1 0/1 0 0/1 0/1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 setting of count clock (see table 8-3 ) caution if both the cpt901 and cpt900 flags are set to 0, the capture edge is disabled. when the count value of 16-bit time r counter 90 (tm90) matches the va lue set in cr90, counting of tm90 continues and an interrupt request signal (inttm90) is generated. table 8-3 shows interval time, and figure 8-6 s hows timing of the timer interrupt operation. caution when rewriting the value in cr90 during a count operation, be sure to execute the following processing. <1> set interrupts to disabled (set tmmk90 (bit 4 of interrupt mask flag register 1 (mk1)) to 1). <2> disable inversion control of ti mer output data (set toc90 to 0) if the value in cr90 is rewritten in the interrup t-enabled state, an interr upt request may occur at the moment of rewrite.
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 124 table 8-3. interval time of 16-bit timer 90 tcl901 tcl900 count clock interval time at f x = 10.0 mhz note or f xt = 32.768 khz operation at f x = 5.0 mhz or f xt = 32.768 khz operation at f x = 10.0 mhz note or f xt = 32.768 khz operation at f x = 5.0 mhz or f xt = 32.768 khz operation 0 0 2 2 /f x 0.4 s 0.8 s 2 18 /f x 26.2 ms 52.4 ms 0 1 2 6 /f x 6.4 s 12.8 s 2 22 /f x 419 ms 839 ms 1 0 2 7 /f x 12.8 s 25.6 s 2 23 /f x 839 ms 1.68 s 1 1 1/f xt 30.5 s 2 16 /f xt 2.0 s note expanded-specification products only remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency figure 8-6. timing of timer interrupt operation cr90 inttm90 to90 tof90 nn n nn t 0000h n ffffh n 0000h 0001h 0001h count clock tm90 count value interrupt acknowledged interrupt acknowledged overflow flag set remark n = 0000h to ffffh
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 125 8.4.2 operation as timer output 16-bit timer 90 can invert the timer output repeatedly each time the free-running counter va lue reaches the value set to cr90. since this counter is not cleared and holds the count even after the timer output is inverted, the interval time is equal to one cycle of the count clock set in tcl901 and tcl900. to operate the 16-bit timer as a timer out put, the following settings are required. ? set p32 to output mode (pm32 = 0). ? reset the output latch of p32 to 0. ? set the count value in cr90. ? set 16-bit timer mode control register 90 (tmc90) as shown in figure 8-7. figure 8-7. settings of 16-bit timer mode c ontrol register 90 for timer output operation ? 0/1 0/1 0/1 1 0 0/1 1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 setting of count clock (see table 8-3 ) inverse enable of timer output data to90 output enable caution if both the cpt901 flag and cpt900 flag are set to 0, the capture edge is disabled. when the count value of 16-bit timer c ounter 90 (tm90) matches the value set in cr90, the output status of the to90/p32/intp2 pin is inverted. this enables timer out put. at that time, the tm90 count is continued and an interrupt request signal (inttm90) is generated. figure 8-8 shows the timing of timer output (see table 8-3 for the interval time of the 16-bit timer). figure 8-8. timer output timing nn n nn t 0000h n ffffh n 0000h 0001h 0001h count clock tm90 count value cr90 inttm90 to90 note tof90 interrupt acknowledged interrupt acknowledged overflow flag set note the to90 initial value becomes low level during output enable (toe90 = 1). remark n = 0000h to ffffh
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 126 8.4.3 capture operation the capture operation cons ists of latching the count value of 16-bit time r register 90 (tm90) in to a capture register in synchronization with a capture tri gger, and retaining the count value. set tmc90 as shown in figure 8-9 to allow t he 16-bit timer to start the capture operation. figure 8-9. settings of 16-bit timer mode control register 90 for capture operation ? 0/1 0/1 0/1 0/1 0 0/1 0/1 tod90 tof90 cpt901 cpt900 toc90 tcl901 tcl900 toe90 tmc90 count clock selection capture edge selection (see table 8-4 ) 16-bit capture register 90 (tcp90) st arts a capture operation after a cpt 90 capture trigger edge is detected, and latches and retains the count value of 16-bit timer regist er 90. tcp90 fetches the c ount value within 2 clocks and retains the count value until the next capture edge detection. table 8-4 and figure 8-10 shows the se ttings of the capture edge and captur e operation timing, respectively. table 8-4. settings of capture edge cpt901 cpt900 capture edge selection 0 0 capture operation prohibited 0 1 cpt90 pin rising edge 1 0 cpt90 pin falling edge 1 1 cpt90 pin both edges caution because tcp90 is rewritten when a capture tr igger edge is detected during tcp90 read, disable capture trigger edge det ection during tcp90 read. figure 8-10. capture operation timing (b oth edges of cpt90 pin are specified) count clock tm90 count read buffer tcp90 cpt90 0000h 0000h 0001h 0001h undefined n n n m 1 m m m capture start capture start capture edge detection capture edge detection
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 127 8.4.4 16-bit timer counter 90 readout the count value of 16-bit timer c ounter 90 (tm90) is read out with a 16-bit manipulation instruction. tm90 readout is performed via a counter read buffer. the counter read buffer latches the tm90 count value. the buffer operation is held pending at the cpu clock falling edge after the read signal of the tm90 lower byte rises and the count value is retained. the count er read buffer value in the retention st ate can be read out as the count value. cancellation of pending is performed at the cpu clock fa lling edge after the read signal of the tm90 higher byte falls. reset input clears tm90 to 0000h and tm90 starts freerunning. figure 8-11 shows the timing of 16-bit timer counter 90 readout. cautions 1. the count value after releasing th e stop mode becomes undefined because the count operation is executed during the oscillation stabilization time. 2. though tm90 is designed for a 16-bit transfer inst ruction, 8-bit transfer instruction can also be used. when using the 8-bit transfer instru ction, execute it using direct addressing. 3. when using the 8-bit transfer instruction, execute in the order from lower byte to higher byte in pairs. if only the lower byte is read , the pending state of the counter read buffer is not canceled, and if only the higher byte is read, an undefined c ount value is read. figure 8-11. 16-bit timer counter 90 readout timing cpu clock count clock tm90 count read buffer tm90 read signal 0000h 0000h 0001h 0001h n n n + 1 read signal latch prohibited period remark n = 0000h to ffffh
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 128 8.4.5 buzzer output operation the buzzer frequency is set using buzzer output control register 90 (bzc90) based on the count clock selected with tcl901 and tcl900 of tmc90 (source clock). a s quare wave of the set buzzer frequency is output. table 8-5 shows the buzzer frequency. set the 16-bit timer as follows to use it for buzzer output. ? set p33 to output mode (pm33 = 0). ? reset output latch of p33 to 0. ? set a count clock by using tcl901 and tcl900. ? set bzc90 as shown in figure 8-12. ? clear toe82 of 8-bit timer mode control register 82 (t mc82) to 0 to disable the output of 8-bit timer 82. figure 8-12. settings of buzzer output cont rol register 90 for buzzer output operation 0 0 0 0 0/1 0/1 0/1 1 bcs902 bcs901 bcs900 bzoe90 bzc90 setting of buzzer frequency (see table 8-5 ) enables buzzer output table 8-5. buzzer frequency of 16-bit timer 90 buzzer frequency at f x = 10.0 mhz note operation at f x = 5.0 mhz operation at f xt = 32.768 khz operation bcs902 bcs901 bcs900 fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 7 fcl = f x /2 2 fcl = f x /2 6 fcl = f x /2 7 fcl = f xt 0 0 0 156 khz 9.76 khz 4.88 khz 78.1 khz 4.88 khz 2.44 khz 2.05 khz 0 0 1 78.1 khz 4.88 khz 2.44 khz 39.1 khz 2.44 khz 1.22 khz 1.02 khz 0 1 0 9.76 khz 610 hz 305 hz 4.88 khz 305 hz 152 hz 128 hz 0 1 1 4.88 khz 305 hz 152 hz 2.44 khz 152 hz 76 hz 64 hz 1 0 0 2.44 khz 152 hz 76 hz 1.22 khz 76 hz 38 hz 32 hz 1 0 1 1.22 khz 76 hz 38 hz 610 hz 38 hz 19 hz 16 hz 1 1 0 610 hz 38 hz 19 hz 305 hz 19 hz 10 hz 8 hz 1 1 1 305 hz 19 hz 10 hz 153 hz 10 hz 5 hz 4 hz note expanded-specification products only remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 129 8.5 notes on 16-bit timer 90 8.5.1 notes on using 16-bit timer 90 usable functions differ according to the settings of the count clock selection, cpu clock operation, system clock oscillation status, and bzoe90 (bit 0 of bu zzer output control register 90 (bzc90)). refer to the following table. system clock count clock cpu clock main system clock subsystem clock bzoe90 capture tm90 read buzzer output timer output timer interrupt oscillating note 1 note 2 main stopped oscillating/stopped oscillating note 2 f x /2 2 , f x /2 6 , f x /2 7 sub stopped oscillating 1/0 0 oscillating 1 oscillating stopped 1/0 0 oscillating 1 main stopped (stop mode) stopped 1/0 0 oscillating 1 0 f xt sub stopped oscillating 1 notes 1. tm90 is enabled only when the cpu clock is in high-speed mode. 2. output is enabled when bzoe90 = 1. cautions 1. the capture function uses f x /2 for control (refer to figure 8- 1 block diagram of 16-bit timer 90). therefore, the capture function cannot be used when the ma in system clock is stopped. 2. the read function of tm90 uses the cpu clock for control (ref er to figure 8-1), and reads an undefined value when the cpu clock is slow er than the count cl ock (values are not guaranteed). when reading tm90, set the c ount clock to the same speed as the cpu clock (when the cpu clock is the main system clock, high-speed mode is set), or select a clock slower than the cpu clock. 3. when the subsystem clock is selected as the count cl ock and bzoe90 is set to 0, the subsystem clock selected as the tm90 count clock is one that has been synchronized with the main system clock (refer to figure 8-1). therefore, when the main system clock oscillation is stopped, the ti mer operation is stopped because the clock supplied to 16-bit timer 90 is stopped (timer inte rrupt is not generated). moreover, when the subsystem clock is selected as the count clock and bzoe90 is set to 1, the capture and tm90 read values are not gua ranteed because the sub system clock is not synchronized. therefore, be sure to set bzoe 90 to 0 when using the capture and tm90 read functions (when the subsystem clock is select ed as the count clock, buzzer output, and the capture and tm90 read functions ca nnot be used at the same time).
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 130 make the following settings to enable low-current cons umption when stopping the main system clock oscillation and releasing the halt mode. count clock: subsystem clock cpu clock: subsystem clock main system clock: oscillation stopped bzoe90: 1 (buzzer output enable) at this time, when the setting of p33, the buzzer output alternate function pi n, is ?pm33 = 0, p33 = 0?, a square wave of the buzzer frequency is output from p33. when making the above settings, perform either of the following. ? set p33 to input mode (pm33 = 1) ? if p33 cannot be set input mode, set the port latch value of p33 to 1 (p33 = 1) (in this case a high level is output from p33)
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 131 8.5.2 restrictions on rewriti ng of 16-bit compare register 90 (1) when rewriting the compare regi ster (cr90), be sure to disable interrupts (tmmk90 = 1), and disable inversion control of timer output (toc90 = 0) first. if cr90 is rewritten with interrupts enabled, an interrupt request may be generated at t he moment of rewrite. (2) the interval time may be double the intended time dependi ng on to the timing at whic h the compare register (cr90) is rewritten. likewise, the timer output waveform may be shorter or double the intended output. to avoid this, rewrite usi ng one of the following procedures. rewriting by 8-bit access <1> disable interrupts (tmmk90 = 1), and disable in version control of timer output (toc90 = 0) <2> rewrite the higher byte of cr90 (16 bits) first <3> next, rewrite the lower byte of cr90 (16 bits) <4> clear the interrupt request flag (tmif90) <5> after more than half the cycle of the count clock has passed from the start of the interrupt, enable timer interrupt and timer output inversion (when count clock = 64/fx, cpu clock = f x ) tm90_vct: set1 tmmk90; timer interrupt disable (6 clocks) clr1 tmc90.3; timer output inversion disable (6 clocks) mov a, #xxh; higher byte re write value setting (6 clocks) mov !0ff17h,a; cr90 higher byte rewriting (8 clocks) mov a, #yyh; lower byte re write value setting (6 clocks) mov !0ff16h,a; cr90 lower byte rewriting (8 clocks) clr1 tmif90; interrupt request flag clearing (6 clocks) clr1 tmmk90; timer interrupt enable (6 clocks) set1 tmc90.3; timer output inversion enable note this is because the inttm90 signal is set to the high level for a period of half the cycle of the count clock after an interrupt is generated, so the output will be inverted if toc90 is set to 1 during this period. more than 32 clocks in total note
chapter 8 16-bit timer 90 user?s manual u14186ej5v0ud 132 rewriting by 16-bit access <1> disable interrupt (tmmk90 = 1), and disable in version control of timer output (toc90 = 0) <2> rewrite cr90 (16 bits) <3> wait for more than one cycle of the count clock <4> clear the interrupt request flag (tmif90) <5> enable timer interrupt and timer output inversion (when count clock = 64/f x , cpu clock = f x ) tm90_vct: set1 tmmk90; timer interrupt disable clr1 tmc90.3; timer output inversion disable movw ax, #xxyyh; cr90 rewrite value setting movw cr90, ax; cr90 rewriting nop nop : nop nop clr1 tmif90; interrupt request flag clearing clr1 tmmk90; timer interrupt enable set1 tmc90.3; timer output inversion enable note wait for more than one cycle of the count clock a fter the cr90 rewriting inst ruction (movw cr90, ax) before clearing the interr upt request flag (tmif90). nop 32 (wait for 64/f x ) note
user?s manual u14186ej5v0ud 133 chapter 9 8-bit timer/event counters 80 to 82 9.1 functions of 8-bit timer/event counters 80 to 82 8-bit timer/event counters 80 and 81 and 8-bi t timer 82 have the following functions. ? interval timer (tm80, tm81, tm82) ? external event counter (tm80, tm81 only) ? square wave output (tm80, tm81, tm82) ? pwm output (tm80, tm81, tm82) (1) 8-bit interval timer when an 8-bit timer/event counter is us ed as an interval timer, it generates an interrupt at any time interval set in advance. table 9-1. interval time of 8-bit timer/event counter 80 minimum interval time maximum interval time resolution 1/f x (100 ns) [200 ns] 2 8 /f x (25.6 s) [51.2 s] 1/f x (100 ns) [200 ns] 2 3 /f x (0.8 s) [1.6 s] 2 11 /f x (204.8 s) [409.6 s] 2 3 /f x (0.8 s) [1.6 s] remarks 1. f x : main system clock oscillation frequency 2. the values in parentheses ( ) apply to operation at f x = 10.0 mhz (expanded- specification products only). 3. the values in brackets [ ] apply to operation at f x = 5.0 mhz. table 9-2. interval time of 8-bit timer/event counter 81 minimum interval time maximum interval time resolution 2 4 /f x (1.6 s) (3.2 s) 2 12 /f x (409.6 s) [819.2 s] 2 4 /f x (1.6 s) [3.2 s] 2 8 /f x (25.6 s) (51.2 s) 2 16 /f x (6.55 ms) [13.1 ms] 2 8 /f x (25.6 s) [51.2 s] remarks 1. f x : main system clock oscillation frequency 2. the values in parentheses ( ) apply to operation at f x = 10.0 mhz (expanded- specification products only). 3. the values in brackets [ ] apply to operation at f x = 5.0 mhz. table 9-3. interval time of 8-bit timer 82 minimum interval time maximum interval time resolution 2 5 /f x (3.2 s) [6.4 s] 2 13 /f x (0.82 ms) [1.64 ms] 2 5 /f x (3.2 s) [6.4 s] 2 7 /f x (12.8 s) [25.6 s] 2 15 /f x (3.27 ms) [6.55 ms] 2 7 /f x (12.8 s) [25.6 s] 1/f xt (30.5 s) [30.5 s] 2 8 /f xt (7.81 ms) [7.81 ms] 1/f xt (30.5 s) [30.5 s] remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the values in parentheses ( ) apply to operation at f x = 10.0 mhz or f xt = 32.768 khz (expanded-specification products only). 4. the values in brackets [ ] apply to operation at f x = 5.0 mhz or f xt = 32.768 khz.
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 134 (2) external event counter the number of pulses of an exter nally input signal can be counted. (3) square wave output a square wave of arbitrary frequency can be output. table 9-4. square wave output ra nge of 8-bit timer/event counter 80 minimum pulse width maximum pulse width resolution 1/f x (100 ns) [200 ns] 2 8 /f x (25.6 s) [51.2 s] 1/f x (100 ns) [200 ns] 2 3 /f x (0.8 s) [1.6 s] 2 11 /f x (204.8 s) [409.6 s] 2 3 /f x (0.8 s) [1.6 s] remarks 1. f x : main system clock oscillation frequency 2. the values in parentheses ( ) apply to operation at f x = 10.0 mhz. (expanded- specification products only) 3. the values in brackets [ ] apply to operation at f x = 5.0 mhz. table 9-5. square wave output range of 8-bit timer/event counter 81 minimum pulse width maximum pulse width resolution 2 4 /f x (1.6 s) [3.2 s] 2 12 /f x (409.6 s) [819.2 s] 2 4 /f x (1.6 s) [3.2 s] 2 8 /f x (25.6 s) [51.2 s] 2 16 /f x (6.55 ms) [13.1 ms] 2 8 /f x (25.6 s) [51.2 s] remarks 1. f x : main system clock oscillation frequency 2. the values in parentheses ( ) apply to operation at f x = 10.0 mhz. (expanded- specification products only) 3. the values in brackets [ ] apply to operation at f x = 5.0 mhz. table 9-6. square wave output range of 8-bit timer 82 minimum pulse width maximum pulse width resolution 2 5 /f x (3.2 s) [6.4 s] 2 13 /f x (819 s) [1.64 ms] 2 5 /f x (3.2 s) [6.4 s] 2 7 /f x (12.8 s) [25.6 s] 2 15 /f x (3.27 ms) [6.55 ms] 2 7 /f x (12.8 s) [25.6 s] 1/f xt (30.5 s) [30.5 s] 2 8 /f xt (7.81 ms) [7.81 ms] 1/f xt (30.5 s) [30.5 s] remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the values in parentheses ( ) apply to operation at f x = 10.0 mhz or f xt = 32.768 khz. (expanded-specification products only) 4. the values in brackets [ ] apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. (4) pwm output 8-bit resolution pwm output can be produced.
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 135 9.2 configuration of 8-bit timer/event counters 80 to 82 8-bit timer/event counters 80 to 82 c onsist of the following hardware. table 9-7. configuration of 8- bit timer/event counters 80 to 82 item configuration timer counter 8 bits 3 (tm80 to tm82) register compare register: 8 bits 3 (cr80 to cr82) timer outputs 3 (to80 to to82) control registers 8-bit timer mode contro l register 80 to 82 (tmc80 to tmc82) port mode register 2, 3 (pm2, pm3)
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 136 figure 9-1. block diagram of 8-bit timer/event counter 80 internal bus internal bus 8-bit compare register 80 (cr80) 8-bit timer counter 80 (tm80) match clear ovf r s inv q q tce80 pwme80 tcl801 tcl800 toe80 ti80/p25/ ss20 f x f x /2 3 8-bit timer mode control register 80 (tmc80) p26 output latch to80/p26 pm26 inttm80 selector figure 9-2. block diagram of 8-bit timer/event counter 81 internal bus internal bus 8-bit compare register 81 (cr81) 8-bit timer counter 81 (tm81) match clear ovf r s inv q q tce81 pwme81 tcl811 tcl810 toe81 ti81/cpt90/ p30/intp0 f x /2 8 f x /2 4 8-bit timer mode control register 81 (tmc81) p31 output latch to81/p31/ intp1 pm31 inttm81 selector
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 137 figure 9-3. block diag ram of 8-bit timer 82 internal bus internal bus 8-bit compare register 82 (cr82) 8-bit timer counter 82 (tm82) match clear ovf r s inv q q tce82 pwme82 tcl821 tcl820 toe82 f xt f x /2 7 f x /2 6 8-bit timer mode control register 82 (tmc82) p33 output latch to82/bzo90/ p33/intp3 pm33 inttm82 bzo90 output note selector note see figure 8-1 block diagra m of 16-bit time 90 . (1) 8-bit compare register 8n (cr8n) a value specified in cr8n is compar ed with the count in 8-bit timer count er 8n (tm8n). if they match, an interrupt request (inttm8n) is issued. cr8n is set with an 8-bit memory manipulation instru ction. any value from 00h to ffh can be set. reset input makes cr8n undefined. cautions 1. before rewriting cr8n, stop the timer operation once. if cr8n is rewritten in the timer operation-enabled state, a match interrupt re quest signal may occur at the moment of rewrite. 2. do not clear cr8n to 00h in pwm output m ode (when pwme8n = 1: bit 6 of 8-bit timer mode control register 8n (tmc8n)); othe rwise, pwm output may not be produced normally. remark n = 0 to 2 (2) 8-bit timer counter 8n (tm8n) tm8n is used to count the number of pulses. its contents are read with an 8-bit me mory manipulation instruction. reset input clears tm8n to 00h. remark n = 0 to 2
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 138 9.3 8-bit timer/event counters 80 to 82 control registers the following two types of registers are used to control the 8-bit timer/event counter. 8-bit timer mode control registers 80, 81, and 82 (tmc80, tmc81, and tmc82) port mode registers 2 and 3 (pm2 and pm3) (1) 8-bit timer mode control register 80 (tmc80) tmc80 determines whether to enable or disable 8-bit ti mer counter 80 (tm80), spec ifies the count clock for tm80, and controls the operation of the output controller of 8- bit timer/event counter 80. tmc80 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc80 to 00h. figure 9-4. format of 8-bit timer mode control register 80 tce80 0 1 tm80 operation control operation disabled (tm80 is cleared to 00h) operation enabled pwme80 0 1 pwm output selection timer counter operation mode pwm output operation mode toe80 0 1 8-bit timer/event counter 80 output control output disabled (port mode) output enabled 8-bit timer counter 80 count clock selection tcl801 0 0 1 1 tcl800 0 1 0 1 at f x = 10.0 mhz note operation at f x = 5.0 mhz operation f x f x /2 3 rising edge of ti80 falling edge of ti80 10.0 mhz 1.25 mhz 5.0 mhz 625 khz tce80 pwme80 0 0 0 tcl801 tcl800 toe80 tmc80 symbol address after reset r/w ff53h 00h r/w <6> <7> 5 4 3 21 <0> note expanded-specificati on products only. cautions 1. always stop the timer before setting tmc80. 2. for pwm mode operation, the inte rrupt mask flag (tmmk80) must be set. remarks f x : main system clock oscillation frequency
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 139 (2) 8-bit timer mode control register 81 (tmc81) tmc81 determines whether to enable or disable 8-bit ti mer counter 81 (tm81), spec ifies the count clock for tm81, and controls the operation of the output controller of 8- bit timer/event counter 81. tmc81 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc81 to 00h. figure 9-5. format of 8-bit timer mode control register 81 tce81 0 1 tm81 operation control operation disabled (tm81 is cleared to 00h) operation enabled pwme81 0 1 pwm output selection toe81 0 1 8-bit timer/event counter 81 output control output disabled (port mode) output enabled 8-bit timer counter 81 count clock selection tcl811 0 0 1 1 tcl810 0 1 0 1 at f x = 10.0 mhz note operation at f x = 5.0 mhz operation f x /2 4 f x /2 8 rising edge of ti81 falling edge of ti81 625 khz 39.1 khz 312 khz 19.5 khz tce81 pwme81 0 0 0 tcl811 tcl810 toe81 tmc81 symbol address after reset r/w ff57h 00h r/w <6> <7> 5 4 3 21 <0> note expanded-specificati on products only. cautions 1. always stop the timer before setting tmc81. 2. for pwm mode operation, the inte rrupt mask flag (tmmk81) must be set. remark f x : main system clock oscillation frequency
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 140 (3) 8-bit timer mode control register 82 (tmc82) tmc82 determines whether to enable or disable 8-bit ti mer counter 82 (tm82) and s pecifies the count clock for tm82. it also controls the operation of the output controller of 8-bit timer 82. tmc82 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears tmc82 to 00h. figure 9-6. format of 8-bit timer mode control register 82 tce82 0 1 tm82 operation control operation disabled (tm82 is cleared to 00h) operation enabled pwme82 0 1 pwm output selection timer counter operation mode pwm output operation mode toe82 0 1 8-bit timer 82 output control output disabled (port mode) output enabled note 2 8-bit time counter 82 count clock section tcl821 0 0 1 1 tcl820 0 1 0 1 at f x = 10.0 mhz note 1 or f xt = 32.768 khz operation at f x = 5.0 mhz or f xt = 32.768 khz operation f x /2 5 f x /2 7 f xt setting prohibited 312 khz 78.1 khz 32.768 khz 156 khz 39.1 khz tce82 pwme82 0 0 0 tcl821 tcl820 toe82 tmc82 symbol address after reset r/w ff5bh 00h r/w <6> <7> 5 4 3 21 <0> notes 1. expanded-specification products only. 2. when toe82 is set to 1, bzoe90 must be set to 0 (see figure 8-3 format of buzzer output control register 90 ). cautions 1. always stop the timer before setting tmc82. 2. for pwm mode operation, the inte rrupt mask flag (tmmk82) must be set. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 141 (4) port mode registers 2 and 3 (pm2 and pm3) pm2 and pm3 specify whether each bit of por t 2 and port 3 is used for input or output. to use the p26/to80 pin for timer output, the pm26 and p26 output latch must be reset to 0. to use the p31/to81/intp1 pin for timer output, t he pm31 and p31 output latch must be reset to 0. to use the p33/intp3/to82/bzo90 pi n for timer output, the pm33 and p33 out put latch must be reset to 0. pm2 and pm3 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input sets pm2 and pm3 to ffh. figure 9-7. format of port mode register 2 pm26 0 1 p26 pin i/o mode selection output mode (output buffer on) input mode (output buffer off) 1 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm2 76 54 symbol address after reset r/w ff22h ffh r/w 3210 figure 9-8. format of port mode register 3 pm31 0 1 p31 pin i/o mode selection output mode (output buffer on) input mode (output buffer off) 1 1 1 1 pm33 pm32 pm31 pm30 pm3 765 4 symbol address after reset r/w ff23h ffh r/w pm33 0 1 p33 pin i/o mode selection output mode (output buffer on) input mode (output buffer off) 32 10
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 142 9.4 operation of 8-bit timer/event counters 80 to 82 9.4.1 operation as interval timer the interval timer repeatedly generates an interrupt at time intervals specifi ed by the count value set in 8-bit compare register 8n (cr8n) in advance. to operate 8-bit timer/event counters 80 to 82 as an in terval timer, the following settings are required. <1> set 8-bit timer counter 8n (tm8n) to operation disabl e (by setting tce8n (bit 7 of 8-bit timer mode control register 8n (tmc8n)) to 0). <2> set the count clock of 8-bit timer/event counters 80 to 82 (see tables 9-8 to 9-10 ). <3> set a count value in cr8n. <4> set tm8n to operation enabled (tce8n = 1). when the count value of 8-bit timer counter 8n (tm8n) matches the value set in cr8n, tm8n is cleared to 00h and continues counting. at the same time, an interrupt request signal (inttm8n) is generated. tables 9-8 to 9-10 show interval time, and figure 9-9 shows the timing of interval timer operation. cautions 1. before rewriting cr8n, stop the timer operation once. if cr8n is rewritten in the timer operation-enabled state, a match interrupt re quest signal may occur at the moment of rewrite. 2. if the count clock setting and tm8n opera tion-enabled are set in tcm8n simultaneously using an 8-bit memory manipulation instruction, an error of more th an a clock in one cycle may occur after the timer start. therefo re, always follow the above procedure when operating the 8-bit timer/event c ounter as an interval timer. remark n = 0 to 2 table 9-8. interval time of 8-bit timer/event counter 80 tcl801 tcl800 minimum interval time ma ximum interval time resolution 0 0 1/f x (100 ns) [200 ns] 2 8 /f x (25.6 s) [51.2 s] 1/f x (100 ns) [200 ns] 0 1 2 3 /f x (0.8 s) [1.6 s] 2 11 /f x (204.8 s) [409.6 s] 2 3 /f x (0.8 s) [1.6 s] 1 0 ti80 input cycle 2 8 ti80 input cycle ti80 input edge cycle 1 1 ti80 input cycle 2 8 ti80 input cycle ti80 input edge cycle remarks 1. f x : main system clock oscillation frequency 2. the values in parentheses ( ) apply to operation at f x = 10.0 mhz. (expanded-s pecification products only) 3. the values in brackets [ ] apply to operation at f x = 5.0 mhz.
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 143 table 9-9. interval time of 8-bit timer/event counter 81 tcl811 tcl810 minimum interval time ma ximum interval time resolution 0 0 2 4 /f x (1.6 s) [3.2 s] 2 12 /f x (409.6 s) [819.2 s] 2 4 /f x (1.6 s) [3.2 s] 0 1 2 8 /f x (25.6 s) [51.2 s] 2 16 /f x (6.55 ms) [13.1 ms] 2 8 /f x (25.6 s) [51.2 s] 1 0 ti81 input cycle 2 8 ti81 input cycle ti81 input edge cycle 1 1 ti81 input cycle 2 8 ti81 input cycle ti81 input edge cycle remarks 1. f x : main system clock oscillation frequency 2. the values in parentheses ( ) apply to operation at f x = 10.0 mhz. (expanded-s pecification products only) 3. the values in brackets [ ] apply to operation at f x = 5.0 mhz. table 9-10. interval time of 8-bit timer 82 tcl821 tcl820 minimum interval time ma ximum interval time resolution 0 0 2 5 /f x (3.2 s) [6.4 s] 2 13 /f x (819 s) [1.64 ms] 2 5 /f x (3.2 s) [6.4 s] 0 1 2 7 /f x (12.8 s) [25.6 s] 2 15 /f x (3.27 ms) [6.55 ms] 2 7 /f x (12.8 s) [25.6 s] 1 0 1/f xt (30.5 s) [30.5 s] 2 8 /f xt (7.81 ms) [7.81 ms] 1/f xt (30.5 s) [30.5 s] 1 1 setting prohibited remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the values in parentheses ( ) apply to operation at f x = 10.0 mhz or f xt = 32.768 khz (expanded- specification products only). 4. the values in brackets [ ] apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. figure 9-9. interval timer operation timing clear clear interrupt acknowledged interrupt acknowledged count start interval time interval time interval time count clock tm8n count value cr8n tce8n inttm8n to8n n 01h 00h n 01h 00h n 00h 01h nn nn t remarks 1. interval time = (n + 1) t : n = 00h to ffh 2. n = 0 to 2
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 144 9.4.2 operation as external event counter note the external event counter counts the number of external clock pulses input to the ti80/p25/ss20 or ti81/p30/intp0/cpt90 pin by using 8-bit timer counters 80 or 81 (tm80 or tm81). to operate 8-bit timer/event counter 8n as an external event counter, the following settings are required. <1> set p25 or p30 to input mode (pm25 = 1, pm30 = 1). <2> set 8-bit timer register 8n (tm8n) to operation dis abled (by setting tce8n (bit 7 of 8-bit timer mode control register 8n (tmc8n)) to 0). <3> specify the rising/falling edges of ti8n (see tables 9-4 and 9-5 ). <4> set a count value in cr8n. <5> set tm8n to operation enabled (tce8n = 1). note only tm80 and tm81 have this function. each time the valid edge specified by bit 1 (tcl8n0) of tmc8n is input, the value tm8n is incremented. when the count value of tm8n matches the value set in cr8n, tm8n is cleared to 0 and continues counting. at the same time, an interrupt request signal (inttm8n) is generated. figure 9-10 shows the timing of the external ev ent counter operation (wit h rising edge specified). cautions 1. before rewriting cr8n, stop the timer operation once. if cr8n is rewritten in the timer operation-enabled state, a match interrupt re quest signal may occur at the moment of rewrite. 2. if the count clock setting and tm8n opera tion-enabled are set in tcm8n simultaneously using an 8-bit memory manipulation instruction, an error of more th an a clock in one cycle may occur after the timer start. therefo re, always follow the above procedure when operating the 8-bit timer/event count er as an external event counter. remark n = 0, 1 figure 9-10. external event counter oper ation timing (with rising edge specified) ti8n pin input tm8n count value cr8n tce8n inttm8n 00h 01h 02h 03h 04h 05h n 00h 01h 02h 03h n n 1 remarks 1. n = 00h to ffh 2. n = 0, 1
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 145 9.4.3 operation as square wave output the 8-bit timer/event counter can gener ate output square waves of an arbitrary frequency at intervals specified by the count value set in 8-bit compar e registers 8n (cr8n) in advance. to operate 8-bit timer/event count ers 8n for square wave output, the following settings are required. <1> set p26, p31, or p33 to output mode (pm26 = 0, pm31 = 0, pm33 = 0). <2> reset the output latches of p26, p31, or p33 to 0. <3> set 8-bit timer counter 8n (tm8n) to operation disabl e (by setting tce8n (bit 7 of 8-bit timer mode control register 8n (tmc8n)) to 1). <4> set the count clock of 8-bit ti mer/event counter 8n and set to8n to out put enable (toe8n (bit 0 of tmc8n) = 1). <5> set count value in cr8n. <6> set tm8n to operation enable (tce8n = 1). when the count value of tm8n matches the value set in cr8n, the to8n pin output will be inverted. through application of this mechanism, square waves of any fr equency can be output. as soon as a match occurs, tm8n will be cleared to 00h and resumes to count, generating an interrupt request signal (inttm8n). setting 0 for bit 7 (tce8n) of tmc8n clears the square-wave output to 0. tables 9-11 through 9-13 show square wave output range, and figure 9-11 s hows timing of square wave output. cautions 1. before rewriting cr8n, stop the timer operation once. if cr8n is rewritten in the timer operation-enabled state, a match interrupt re quest signal may occur at the moment of rewrite. 2. if the count clock setting and tm8n opera tion-enabled are set in tcm8n simultaneously using an 8-bit memory manipulation instruction, an error of more th an a clock in one cycle may occur after the timer start. therefo re, always follow the above procedure when operating the 8-bit timer/event c ounter for square wave output. remark n = 0 to 2 table 9-11. square wave output ra nge of 8-bit timer/event counter 80 tcl801 tcl800 minimum pulse width maximum pulse width resolution 0 0 1/f x (100 ns) [200 ns] 2 8 /f x (25.6 s) [51.2 s] 1/f x (100 ns) [200 ns] 0 1 2 3 /f x (0.8 s) [1.6 s] 2 11 /f x (204.8 s) [409.6 s] 2 3 /f x (0.8 s) [1.6 s] remarks 1. f x : main system clock oscillation frequency 2. the values in parentheses ( ) apply to operation at f x = 10.0 mhz. (expanded-s pecification products only) 3. the values in brackets [ ] apply to operation at f x = 5.0 mhz. table 9-12. square wave output ra nge of 8-bit timer/event counter 81 tcl811 tcl810 minimum pulse width maximum pulse width resolution 0 0 2 4 /f x (1.6 s) [3.2 s] 2 12 /f x (409.6 s) [819.2 s] 2 4 /f x (1.6 s) [3.2 s] 0 1 2 8 /f x (25.6 s) [51.2 s] 2 16 /f x (6.55 ms) [13.1 ms] 2 8 /f x (25.6 s) [51.2 s] remarks 1. f x : main system clock oscillation frequency 2. the values in parentheses ( ) apply to operation at f x = 10.0 mhz. (expanded-s pecification products only) 3. the values in brackets [ ] apply to operation at f x = 5.0 mhz.
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 146 table 9-13. square wave output range of 8-bit timer 82 tcl821 tcl820 minimum pulse width maximum pulse width resolution 0 0 2 5 /f x (3.2 s) [6.4 s] 2 13 /f x (819 s) [1.64 ms] 2 5 /f x (3.2 s) [6.4 s] 0 1 2 7 /f x (12.8 s) [25.6 s] 2 15 /f x (3.27 ms) [6.55 ms] 2 7 /f x (12.8 s) [25.6 s] 1 0 1/f xt (30.5 s) [30.5 s] 2 8 /f xt (7.81 ms) [7.81 ms] 1/f xt (30.5 s) [30.5 s] remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. the values in parentheses ( ) apply to operation at f x = 10.0 mhz or f xt = 32.768 khz. (expanded- specification products only) 4. the values in brackets [ ] apply to operation at f x = 5.0 mhz or f xt = 32.768 khz. figure 9-11. square wave output timing clear clear interrupt acknowledged interrupt acknowledged count start count clock tm8n count value cr8n tce8n inttm8n to8n note n 01h 00h n 01h 00h n 00h 01h nn nn note the initial value of to8n is low for output enable (toe8n = 1). remark n = 0 to 2
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 147 9.4.4 pwm output operation pwm output enables generation of an interr upt repeatedly at intervals specified by the count value set in 8-bit compare register 8n (cr8n) in advance. to use 8-bit timer/event counter 8n for pwm output, the following settings are required. <1> set p26, p31, or p33 to output mode (pm26 = 0, pm31 = 0, pm33 = 0). <2> reset the output latches of p26, p31, or p33 to 0. <3> set 8-bit timer counter 8n (tm8n) to operation disabl e (by setting tce8n (bit 7 of 8-bit timer mode control register 8n (tmc8n)) to 0). <4> set the count clock of 8-bit ti mer/event counter 8n, and set to8n to output enable (toe8n (b it 0 of tmc8n) = 1), and to pwm output mode (pwme8n = 1). <5> set a count value in cr8n. <6> set tm8n to operation enable (tce8n = 1). when the count value of tm8n matches the value set in cr8n, tm8n continues count ing, and an interrupt request signal (inttm8n) is generated. cautions 1. before rewriting cr8n, stop the timer. if cr8n is rewr itten in the timer operation-enabled state, a high-level signal may be output for the next cycle (256 count pulses) (for details, see 9.5 (3) timer operation after compare re gister is rewritten during pwm output). 2. if the count clock setting and tm8n opera tion-enabled are set in tcm8n simultaneously using an 8-bit memory manipulation instruction, an error of more th an a clock in one cycle may occur after the timer start. therefo re, always follow the above procedure when operating the 8-bit timer/event counter for pwm output. remark n = 0 to 2
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 148 figure 9-12. pwm output timing count clock tm8n cr8n tce8n inttm8n m = 01h to ffh ovf to8n note 00h 01h m m ffh 00h 01h 02h m m + 1 m + 2 ffh 00h 01h m note the initial value of to8n is low for output enable (toe8n = 1). caution do not set cr8n to 00h in pwm output m ode; otherwise, pwm may not be output normally. remark n = 0 to 2
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 149 9.5 notes on using 8-bit ti mer/event counters 80 to 82 (1) error on starting timer an error of up to 1.5 clocks is included in the ti me between when the timer is started and when a match signal is generated. this is because the rising edge is detected and the counter is increm ented if the timer is started while the selected clock is high (see figure 9-13 ). figure 9-13. case of error o ccurrence of up to 1.5 clocks 8-bit timer counter 8n (tm8n) count pulse clear signal selected clock tce8n delay a delay b selected clock tce8n clear signal count pulse tm8n counter value 00h 01h 02h 03h delay a delay b an error of up to 1.5 clocks occurs if the timer is started when the selected clock is high and delay a > delay b. remark n = 0 to 2
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 150 (2) count value if external clock input from ti8n pin is selected when the rising edge of the external clock signal input fr om the ti8n pin is selected as the count clock, the count value may start from 01h if the timer is enabled (tce8n = 0 1) while the ti8n pin is high. this is because the input signal of the ti 8n pin is internally anded with the tce8n signal. consequently, the counter is incremented becaus e the rising edge of the count clock is i nput to the timer immediately when the tce8n pin is set. depending on the delay timing, the c ount value is incremented by one if the rising edge is input after the counter is cleared. counting is not affected if the risi ng edge is input befor e the counter is cleared (the counter operates normally). by the same factor as the above, w hen the falling edge of the external clo ck signal input from the ti8n pin is selected as the count clock, the count value may start from 01h if the timer is enabled (tce8n = 0 1) while the ti8n pin is low. use the timer being aware that it has an error of one count, or take either of the following actions a or b. always start the timer while the ti8n pin is low if the rising edge is selected. always start the timer while the ti8n pi n is high if the falling edge is selected save the count value to a control regist er when the timer is start ed, sub the count value with the count value saved to the c ontrol register when reading the c ount value, and take the result of sub as the true count value. figure 9-14. counting operation if timer is started when ti8n is high (when the rising edge is selected) tce8n flag ti8n h rising edge detector counter clear increment
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 151 (3) setting of 8-bit compare register 8n 8-bit compare register 8n (cr8n) can be set to 00h. therefore, one pulse can be counted when an 8-bit timer/event c ounter operates as an event counter. figure 9-15. external event counter operation timing tl80, ti81 input cr80, cr81 00h tm80, tm81 count value 00h 00h 00h 00h interrupt request flag cautions 1. when cr8n is rewri tten to timer counter operation m ode (pwme8n (8-bit timer mode control register 8n (tmc8n)) = 0), be sure to stop the timer operation beforehand. if cr8n is rewritten in the timer operation-enab led state, a match interrupt request signal may occur at the moment of rewrite. 2. if cr8n is rewritten dur ing timer operation in the pwm operation mode (pwme8n = 1), pulses may not be generated for one cycle after the rewrite. 3. do not set cr8n to 00h in pwm operati on mode; otherwise, pwm may not be output normally. remark n = 0 to 2
chapter 9 8-bit timer/event counters 80 to 82 user?s manual u14186ej5v0ud 152 (4) timer operation after compare regi ster is rewritten during pwm output when 8-bit compare register 8n (cr8n) is rewritten during pwm output, if the new value is smaller than that of 8-bit timer/counter 8n (tm8n), a high-level signal may be output for t he next cycle (256 count pulses) after the cr8n value is rewritten. figure 9-16 shows t he timing at which the high-level signal is output. figure 9-16. operation timing after compare register is rewritten during pwm output count clock tm8n cr8n tce8n inttm8n m = 01h to ffh ovf to8n 00h 01h m m ffh 00h 01h 02h ffh 00h 01h 01h cr8n rewritten remark n = 0 to 2 (5) cautions when stop mode is set be sure to stop timer operations (tce8n = 0) before executing the stop instruction.
user?s manual u14186ej5v0ud 153 chapter 10 watch timer 10.1 watch timer functions the watch timer has the following functions. ? watch timer ? interval timer the watch and interval timers can be used at the same time. figure 10-1 is a block diagram of the watch timer. figure 10-1. block diagram of watch timer f x /2 7 f xt f w f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 clear 9-bit prescaler selector clear 5-bit counter intwt intwti wtm7 wtm6 wtm5 wtm4 wtm1 wtm0 watch timer mode control register (wtm) internal bus selector
chapter 10 watch timer user?s manual u14186ej5v0ud 154 (1) watch timer the 4.19 mhz main system clock or 32.768 khz subsyst em clock is used to issue an interrupt request (intwt) at 0.5-second intervals. caution when the main system clo ck is operating at 5.0 mhz, it ca nnot be used to generate a 0.5- second interval. in this case, the subsystem clock, which operates at 32.768 khz, should be used instead. (2) interval timer the interval timer is used to generate an interr upt request (intwti) at specified intervals. table 10-1. interval gene rated using interval timer interval at f x = 10.0 mhz note at f x = 5.0 mhz at f x = 4.19 mhz at f xt = 32.768 khz 2 4 1/f w 204 s 409 s 489 s 488 s 2 5 1/f w 409 s 819 s 978 s 977 s 2 6 1/f w 819 s 1.64 ms 1.96 ms 1.95 ms 2 7 1/f w 1.64 ms 3.28 ms 3.91 ms 3.91 ms 2 8 1/f w 3.28 ms 6.55 ms 7.82 ms 7.81 ms 2 9 1/f w 6.55 ms 13.1 ms 15.6 ms 15.6 ms note expanded-specificati on products only. remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 10.2 watch timer configuration the watch timer consists of the following hardware. table 10-2. watch timer configuration item configuration counter 5 bits 1 prescaler 9 bits 1 control register watch timer mode control register (wtm)
chapter 10 watch timer user?s manual u14186ej5v0ud 155 10.3 watch timer control register the watch timer mode control register (wt m) is used to control the watch timer. watch timer mode control register (wtm) wtm selects a count clock for the watch timer and specif ies whether to enable operation of the timer. it also specifies the prescaler interval and how the 5-bit counter is controlled. wtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wtm to 00h. figure 10-2. format of watch timer mode control register prescaler interval selection wtm6 0 0 0 0 1 1 2 4 /f w (488 s) 2 5 /f w (977 s) 2 6 /f w (1.95 ms) 2 7 /f w (3.91 ms) 2 8 /f w (7.81 ms) 2 9 /f w (15.6 ms) wtm5 0 0 1 1 0 0 wtm4 0 1 0 1 0 1 control of 5-bit counter operation wtm1 0 1 cleared after stop started watch timer operation wtm0 0 1 operation disabled (both prescaler and timer cleared) operation enabled other than above setting prohibited wtm7 wtm6 wtm5 wtm4 0 0 wtm1 wtm0 wtm 76 54 symbol address after reset r/w ff4ah 00h r/w 3210 watch timer count clock (f w ) section wtw7 0 1 at f x = 10.0 mhz note or f xt = 32.768 khz operation at f x = 5.0 mhz or f xt = 32.768 khz operation f x /2 7 f xt 78.2 khz 32.768 khz 39.1 khz note expanded-specificati on products only. remarks 1. f w : watch timer clock frequency (f x /2 7 or f xt ) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. the values in parentheses apply to operation at f w = 32.768 khz.
chapter 10 watch timer user?s manual u14186ej5v0ud 156 10.4 watch timer operation 10.4.1 operation as watch timer the main system clock (4.19 mhz) or subsystem clock (32.768 khz) is used to enable the watch timer to operate at 0.5-second intervals. the watch timer is used to generate an inte rrupt request at specified intervals. by setting bits 0 and 1 (wtm0 and wtm1) of the watch time r mode control register (wtm) to 1, the watch timer starts counting. by setting them to 0, the 5-bit counter is cleared and the watc h timer stops counting. only the watch timer can be started form zero seconds by clearing wtm1 to 0 when the interval timer and watch timer operate at the same time. in th is case, however, an error of up to 2 9 1/f w seconds may occur in the overflow (intwt) after the zero-second start of the watch time r because the 9-bit prescaler is not cleared to 0. 10.4.2 operation as interval timer the interval timer is used to repeatedl y generate an interrupt request at the inte rval specified by a count value set in advance. the interval can be selected by bits 4 to 6 (wtm4 to wtm6) of the watch timer m ode control register (wtm). table 10-3. interval gene rated using interval timer wtm6 wtm5 wtm4 interval at f x = 10.0 mhz note at f x = 5.0 mhz at f x = 4.19 mhz at f xt = 32.768 khz 0 0 0 2 4 1/f w 204 s 409 s 489 s 488 s 0 0 1 2 5 1/f w 409 s 819 s 978 s 977 s 0 1 0 2 6 1/f w 819 s 1.64 ms 1.96 ms 1.95 ms 0 1 1 2 7 1/f w 1.64 ms 3.28 ms 3.91 ms 3.91 ms 1 0 0 2 8 1/f w 3.27 ms 6.55 ms 7.82 ms 7.81 ms 1 0 1 2 9 1/f w 6.55 ms 13.1 ms 15.6 ms 15.6 ms other than above setting prohibited note expanded-specificati on products only. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. f w : watch timer clock frequency
chapter 10 watch timer user?s manual u14186ej5v0ud 157 figure 10-3. watch timer/inte rval timer operation timing 0h start overflow overflow 5-bit counter count clock f w /2 9 watch timer interrupt intwt interval timer interrupt intwti watch timer interrupt time (0.5 s) watch timer interrupt time (0.5 s) interval timer (t) t caution when operation of the wa tch timer and 5-bit counter opera tion is enabled by setting bit 0 (wtm0) of the watch timer mode control register (wtm) to 1, the interval until the first interrupt request (intwt) is generated after the register is set does not exactly match the watch timer interrupt time (0.5s). this is because there is a delay of one 9-bit prescaler output cycle until the 5-bit counter starts counting. subsequent ly, however, the intwt signa l is generated at the specified intervals. remarks 1. f w : watch timer clock frequency 2. the values in parentheses apply to operation at f w = 32.768 khz.
user?s manual u14186ej5v0ud 158 chapter 11 watchdog timer 11.1 watchdog timer functions the watchdog timer has the following functions. ? watchdog timer ? interval timer caution select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (wdtm). (1) watchdog timer the watchdog timer is used to detect inadvertent program loops. when an inadvertent loop is detected, a non-maskable interrupt or a reset signal can be generated. table 11-1. inadvertent loop de tection time of watchdog timer inadvertent loop detection time at f x = 10.0 mhz note at f x = 5.0 mhz 2 11 1/f x 205 s 410 s 2 13 1/f x 819 s 1.64 ms 2 15 1/f x 3.27 ms 6.55 ms 2 17 1/f x 13.1 ms 26.2 ms note expanded-specification products only. remark f x : main system clock oscillation frequency (2) interval timer the interval timer generates an interrupt at an arbitrary interval set in advance. table 11-2. interval time interval at f x = 10.0 mhz note at f x = 5.0 mhz 2 11 1/f x 205 s 410 s 2 13 1/f x 819 s 1.64 ms 2 15 1/f x 3.27 ms 6.55 ms 2 17 1/f x 13.1 ms 26.2 ms note expanded-specification products only. remark f x : main system clock oscillation frequency
chapter 11 watchdog timer user?s manual u14186ej5v0ud 159 11.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 11-3. configuration of watchdog timer item configuration control registers timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm) figure 11-1. block diagram of watchdog timer internal bus internal bus prescaler selector controller f x 2 6 f x 2 8 f x 2 10 3 7-bit counter tmif4 tmmk4 tcl22 tcl21 tcl20 timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm) clear wdtm4 run wdtm3 intwdt maskable interrupt request reset intwdt non-maskable interrupt request f x 2 4
chapter 11 watchdog timer user?s manual u14186ej5v0ud 160 11.3 watchdog timer control registers the following two types of registers ar e used to control the watchdog timer. timer clock selection register 2 (tcl2) watchdog timer mode register (wdtm) (1) timer clock selecti on register 2 (tcl2) this register sets the watchdog timer count clock. tcl2 is set with an 8-bit memory manipulation instruction. reset input clears tcl2 to 00h. figure 11-2. format of timer clock selection register 2 symbol 7 6 5 4 3 2 1 0 address address r/w tcl2 0 0 0 0 0 tcl22 tcl21 tcl20 ff42h 00h r/w tcl22 tcl21 tcl20 watchdog timer count clo ck selection interval at f x = 10.0 mhz note at f x = 5.0 mhz at f x = 10.0 mhz note at f x = 5.0 mhz 0 0 0 f x /2 4 625.0 khz 312.5 khz 2 11 /f x 205 s 410 s 0 1 0 f x /2 6 156.2 khz 78.1 khz 2 13 /f x 819 s 1.64 ms 1 0 0 f x /2 8 39.0 khz 19.5 khz 2 15 /f x 3.27 ms 6.55 ms 1 1 0 f x /2 10 9.76 khz 4.88 khz 2 17 /f x 13.1 ms 26.2 ms other than above setting prohibited note expanded-specification products only. remark f x : main system clock oscillation frequency
chapter 11 watchdog timer user?s manual u14186ej5v0ud 161 (2) watchdog timer mode register (wdtm) this register sets an operation mode of the watchdog timer, and enables /disables counting of the watchdog timer. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears wdtm to 00h. figure 11-3. format of watc hdog timer mode register run 0 1 watchdog timer operation selection note 1 stop counting clear counter and start counting wdtm4 watchdog timer operation mode selection note 2 wdtm3 0 1 1 0 1 1 operation stop interval timer mode (generates a maskable interrupt upon overflow occurrence) note 3 watchdog timer mode 1 (generates a non-maskable interrupt upon overflow occurrence) watchdog timer mode 2 (starts reset operation upon overflow occurrence.) 0 0 run 0 0 wdtm4 wdtm3 0 0 0 wdtm <7> 6 5 4 symbol address after reset r/w fff9h 00h r/w 3210 notes 1. once run has been set to 1, it cannot be cleared to 0 by software. ther efore, when counting is started, it cannot be stopped by any means other than reset input. 2. once wdtm3 and wdtm4 have been set to 1, they cannot be cleared to 0 by software. 3. the watchdog timer starts operations as an interval timer when run is set to 1. cautions 1. when the watchdog timer is cleared by setting run to 1, the actual overflow time is up to 0.8% shorter than the time set by timer clock selection register 2 (tcl2). 2. to set watchdog timer mode 1 or 2, set wdtm 4 to 1 after confirming that tmif4 (bit 0 of interrupt request flag register 0 (if0)) is set to 0. when watchdog timer mode 1 or 2 is selected with tmif4 set to 1, a non-m askable interrupt is generated upon the completion of rewriting wdtm4.
chapter 11 watchdog timer user?s manual u14186ej5v0ud 162 11.4 watchdog timer operation 11.4.1 operation as watchdog timer the watchdog timer detects an inadver tent program loop when bit 4 (w dtm4) of the watchdog timer mode register (wdtm) is set to 1. the count clock (inadvertent loop detection time interval) of the watc hdog timer can be selected by bits 0 to 2 (tcl20 to tcl22) of timer clock selection register 2 (tc l2). by setting bit 7 (run) of wdtm to 1, the watchdog timer is started. set run to 1 withi n the set inadvertent loop detection time interval after the watchdog timer has been started. by setting run to 1, t he watchdog timer can be cleared and start c ounting. if run is not set to 1, and the inadvertent loop detection time is exceeded, a system reset signal or a non-maskable interrupt is generated, depending on the value of bit 3 (wdtm3) of wdtm. the watchdog timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the watchdog timer before exec uting the stop instruction. cautions 1. the actual inadvertent loop detection time may be up to 0.8% shorter than the set time. 2. when the subsystem clock is selected as th e cpu clock, watchdog timer count operation is stopped. even when the main system clock continues oscilla ting in this case, the watchdog timer count operation is stopped. table 11-4. inadvertent loop det ection time of watchdog timer tcl22 tcl21 tcl20 inadvertent loop detection time at f x = 10.0 mhz note at f x = 5.0 mhz 0 0 0 2 11 1/f x 205 s 410 s 0 1 0 2 13 1/f x 819 s 1.64 ms 1 0 0 2 15 1/f x 3.27 ms 6.55 ms 1 1 0 2 17 1/f x 13.1 ms 26.2 ms note expanded-specification products only. remark f x : main system clock oscillation frequency
chapter 11 watchdog timer user?s manual u14186ej5v0ud 163 11.4.2 operation as interval timer when bits 4 and 3 (wdtm4, wdtm3) of the watchdog timer mode register (wdtm) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance. select a count clock (or interval) by setting bits 0 to 2 (t cl20 to tcl22) of timer clock selection register 2 (tcl2). the watchdog timer starts operation as an interval time r when the run bit (bit 7 of wdtm) is set to 1. in interval timer mode, the interrupt mask flag (tmmk 4) is valid, and a maskable interrupt (intwdt) can be generated. the priority of intwdt is set as the highest of all the maskable interrupts. the interval timer continues operation in halt mode, but stops in stop mode. therefore, first set run to 1 to clear the interval timer before ex ecuting the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (when watchdog timer mode is selected), interval timer mode is not set unless a reset signal is input. 2. the interval time may be up to 0.8% shorter than the set time when wdtm has just been set. table 11-5. interval time of interval timer tcl22 tcl21 tcl20 interval at f x = 10.0 mhz note at f x = 5.0 mhz 0 0 0 2 11 1/f x 205 s 410 s 0 1 0 2 13 1/f x 819 s 1.64 ms 1 0 0 2 15 1/f x 3.27 ms 6.55 ms 1 1 0 2 17 1/f x 13.1 ms 26.2 ms note expanded-specification products only. remark f x : main system clock oscillation frequency
user?s manual u14186ej5v0ud 164 chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) 12.1 8-bit a/d converter functions the 8-bit a/d converter is an 8-bit resolution converter that converts an analog input to a digital signal. this converter can control eight channels (ani0 to ani7) of analog inputs. a/d conversion can be star ted only by software. one of analog inputs ani0 to ani7 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued eac h time a/d conversion is completed. 12.2 8-bit a/d converter configuration the 8-bit a/d converter consis ts of the following hardware. table 12-1. configuration of 8-bit a/d converter item configuration analog input 8 channels (ani0 to ani7) registers successive approx imation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0)
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 165 figure 12-1. block diagra m of 8-bit a/d converter sample-and-hold circuit voltage comparator successive approximation register (sar) controller 3 a/d conversion result register 0 (adcr0) tap selector av ss intad0 a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0) internal bus av ss p-ch av ref av dd ani4/p64 ani5/p65 ani6/p66 ani7/p67 ani0/p60 ani1/p61 ani2/p62 ani3/p63 selector adcs0 fr02 fr01 fr00 ads02 ads01 ads00 (1) successive approximation register (sar) sar receives the result of comparing an analog i nput voltage and a voltage at the voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least signifi cant bit (lsb), that is, upon the completion of a/d conversion, sar sends its contents to a/ d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) adcr0 holds the result of a/d conv ersion. each time a/d conversion ends, the conversion result in the successive approximation register is loaded into adcr0, which is an 8-bit register. adcr0 can be read with an 8-bit memo ry manipulation instruction. reset input makes this register undefined. (3) sample-and-hold circuit the sample-and-hold circuit samples consecutive analog inputs from the input ci rcuit, one by one, and sends them to the voltage comparator. the sampled analog input voltage is held during a/d conversion.
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 166 (4) voltage comparator the voltage comparator compares an analog input with the volt age output by the series resistor string. (5) series resistor string the series resistor stri ng is configured between av ref and av ss . it generates the reference voltages against which analog inputs are compared. (6) ani0 to ani7 the ani0 to ani7 pins are the 8-channel analog input pins for the a/d converter. they are used to receive the analog signals for a/d conversion. caution do not supply the ani0 to ani7 pins with vo ltages that fall outside the rated range. if a voltage greater than or equal to av ref or less than av ss (even if within the absolute maximum ratings) is supplied to any of these pins, the conversion value for the corresponding channel will be undefi ned. furthermore, the con version values for the other channels may also be affected. (7) av ref this pin inputs the a/d c onverter reference voltage. it converts signals input to ani0 to ani7 into di gital signals according to the voltage applied between av ref and av ss . (8) av ss pin the av ss pin is a ground potential pin for t he a/d converter. this pin must be held at the same potential as the v ss0 pin, even while the a/d c onverter is not being used. (9) av dd pin the av dd pin is an analog power supply pin for the a/d conv erter. this pin must be held at the same potential as the v dd0 pin, even while the a/d c onverter is not being used.
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 167 12.3 8-bit a/d converter control registers the following two registers are used to control the 8-bit a/d converter. a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0) (1) a/d converter mode register 0 (adm0) adm0 specifies the conversion time for analog inputs. it also specifies whether to enable conversion. adm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears adm0 to 00h. figure 12-2. format of a/d converter mode register 0 symbol <7> 6 5 4 3 2 1 0 address after reset r/w adm0 adcs0 0 fr02 fr01 fr00 0 0 0 ff80h 00h r/w adcs0 a/d conversion control 0 conversion disabled 1 conversion enabled a/d conversion time selection note 1 fr02 fr01 fr00 at f x = 10.0 mhz operation note 2 at f x = 5.0 mhz operation 0 0 0 144/f x 14.4 s 28.8 s 0 0 1 120/f x 12.0 s 24.0 s 0 1 0 96/f x setting prohibited note 3 19.2 s 1 0 0 72/f x setting prohibited note 3 14.4 s 1 0 1 60/f x setting prohibited note 3 12.0 s note 4 1 1 0 48/f x setting prohibited note 3 other than above setting prohibited notes 1. set the a/d conversion time so that it satisfies the following ratings. 4.5 av ref av dd = v dd 5.5 v ?.. 12 s min. 2.7 av ref av dd = v dd < 4.5 v ?.. 14 s min. 1.8 av ref av dd = v dd < 2.7 v ?.. 28 s min. 2.7 av ref av dd = v dd 5.5 v ?.. 14 s min. 1.8 av ref av dd = v dd < 2.7 v ?.. 28 s min. 2. expanded-specificati on products only. 3. setting prohibited because the a/d conversi on time cannot satisfy the ratings in note 1 during operation under these f x conditions. 4. can only be set for expanded-specification products under the following conditions: 4.5 av ref av dd = v dd 5.5 v. other settings are prohibited. cautions 1. the result of conver sion performed immediately after bi t 7 (adcs0) is set is undefined. 2. the conversion result may be undefined a fter adcs0 has been clear ed to 0 (for details, see 12.5 (5) timing of undefine d a/d conversion result). remark f x : main system clock oscillation frequency
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 168 (2) a/d input selection register 0 (ads0) ads0 specifies the port used to input the analog voltage to be converted to a digital signal. ads0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears ads0 to 00h. figure 12-3. format of a/d input selection register 0 0 0 0 0 0 ads02 ads01 ads00 ads0 symbol address after reset r/w ff84h 00h r/w 76543210 analog input channel specification ads02 0 0 0 0 1 1 1 1 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ads01 0 0 1 1 0 0 1 1 ads00 0 1 0 1 0 1 0 1 caution bits 3 to 7 must all be set to 0.
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 169 12.4 8-bit a/d converter operation 12.4.1 basic operation of 8-bit a/d converter <1> select a channel for a/d conversion, usi ng a/d input selection register 0 (ads0). <2> the voltage supplied to the selected analog input c hannel is sampled using the sample and hold circuit. <3> after sampling continues for a certain period of ti me, the sample and hold circuit is put on hold to keep the input analog voltage until a/d conversion is completed. <4> bit 7 of the successive approximation register (sar) is set. the series resistor string tap voltage at the tap selector is set to half of av ref . <5> the series resistor string tap voltage is co mpared with the analog input voltage using the voltage comparator. if the analog input voltage is higher than half of av ref , the msb of sar is left set. if it is lower than half of av ref , the msb is reset. <6> bit 6 of sar is set automatically, and comparison sh ifts to the next stage. the next tap voltage of the series resistor string is selected according to bit 7, which reflects the previous comparison result, as follows: ? bit 7 = 1: three quarters of av ref ? bit 7 = 0: one quarter of av ref the tap voltage is compared with the analog input voltage. bit 6 is set or reset according to the result of comparison. ? analog input voltage tap voltage: bit 6 = 1 ? analog input voltage < tap voltage: bit 6 = 0 <7> comparison is repeated until bit 0 of sar is reached. <8> when comparison is completed for all of the 8 bits, a signi ficant digital result is left in sar. this value is sent to and latched in a/d conversion result register 0 (adcr0). at t he same time, it is possible to generate an a/d conversion end in terrupt request (intad0). cautions 1. the first a/d conver sion value immediately after a/d c onversion has been started may be undefined. 2. in standby mode, a/d c onverter operation is stopped.
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 170 figure 12-4. basic operati on of 8-bit a/d converter conversion time sampling time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcr0 intad0 80h c0h or 40h a/d conversion continues until bit 7 (adcs 0) of a/d converter mode register 0 (adm0) is reset to 0 by software. if an attempt is made to write to adm0 or a/d input se lection register 0 (ads0) during a/d conversion, the ongoing a/d conversion is canceled. in th is case, a/d conversion is restarted fr om the beginning, if adcs0 is set to 1. reset input makes a/d conversion re sult register 0 (adcr0) undefined. 12.4.2 input voltage and conversion result the relationships between the analog input voltage at the analog input pi ns (ani0 to ani7) and the a/d conversion result (a/d conversion result register 0 (adcr0)) are represented by: adcr0 = int ( 256 + 0.5) or (adcr0 ? 0.5) v in < (adcr0 + 0.5) int( ): function that returns t he integer part of a parenthesized value v in : analog input voltage av ref : voltage of av ref pin adcr0: value in a/d conversion result register 0 (adcr0) figure 12-5 shows the relationship between the anal og input voltage and the a/d conversion result. v in av ref av ref 256 av ref 256
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 171 figure 12-5. relationship between analog input voltage and a/d conversion result 255 254 253 3 2 1 0 a/d conversion result (adcr0) 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 input voltage/av ref
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 172 12.4.3 operation mode of 8-bit a/d converter the a/d converter is initially in select mode. in this mode, a/d input selecti on register 0 (ads0) is used to select an analog input channel from ani0 to ani7 for a/d conversion. a/d conversion can be started only by software; that is, by setting a/d converter mode register 0 (adm0). the a/d conversion result is saved to a/d conversion result register 0 (adcr0 ). at the same time, an interrupt request signal (intad0) is generated. ? software-started a/d conversion setting bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 1 triggers a/ d conversion for the voltage applied to the analog input pin specifi ed in a/d input selection register 0 (ads0). upon completion of a/d conversion, the conversion result is saved to a/d conversion result regist er 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. once a/d conversion is activated, and completed, another session of a/d conversion is started. a/d conversion is repeated until new data is written to adm0. if data where adcs0 is 1 is written to adm0 again during a/ d conversion, the ongoing sessi on of a/d conversion is discontinued, and a new session of a/d conversion begins for the new data. if data where adcs0 is 0 is written to adm0 again during a/d conversi on, a/d conversion is stopped immediately. figure 12-6. software-started a/d conversion rewriting adm0 adcs0 = 1 rewriting adm0 adcs0 = 1 adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion is discontinued; no conversion result is preserved. remarks 1. n = 0 to 7 2. m = 0 to 7
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 173 12.5 cautions related to 8-bit a/d converter (1) current consumpti on in standby mode in standby mode, the a/d converter st ops operating. setting bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 0 can reduce t he current consumption. figure 12-7 shows how to reduce the cu rrent consumption in standby mode. figure 12-7. how to reduce current consumption in standby mode av ref av ss p-ch series resistor string adcs0 (2) input range for ani0 to ani7 pins be sure to keep the input voltage at ani0 to ani7 wit hin its rating. if a voltage greater than or equal to av ref or less than or equal to av ss (even within the absolute maximum rati ngs) is input into a conversion channel, the conversion output of the channel becomes undefined, and the conversion output of the other channels may also be affected. (3) conflict <1> conflict between writing to a/d conversion result register 0 (a dcr0) at the end of conversion and reading from adcr0 using instruction reading from adcr0 takes precedence. after reading, the new conversion result is written to adcr0. <2> conflict between writing to adcr0 at the end of conversion and writing to a/d conv erter mode register 0 (adm0) or a/d input sele ction register 0 (ads0) writing to adm0 or ads0 takes precedence. adcr0 is not written to. no a/d conversion end interrupt request signal (intad0) is generated. (4) conversion result immediatel y after start of a/d conversion the first a/d conversion value immediately after a/d conversion has been started is undefined. poll the a/d conversion end interrupt request (intad0) and drop the first conversion result.
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 174 (5) timing of undefined a/d conversion result the a/d conversion value may become undefined if the timing of the comp letion of a/d conversion and that to stop the a/d conversion operation conflict. therefore, read the a/d conversion result while the a/d conversion operation is in progress. to read the a/d conversion result after the a/d conversion operation has been stopped, stop the a/d conversion operation before the next conversion operat ion is completed. figures 12-8 and 12-9 show the timing at wh ich the conversion result is read. figure 12-8. conversion result read timi ng (if conversion result is undefined) end of a/d conversion end of a/d conversion normal conversion result undefined value normal conversion result is read. a/d conversion stops. undefined value is read. adcr0 intad0 adcs0 figure 12-9. conversion result read ti ming (if conversion result is normal) normal conversion result end of a/d conversion normal conversion result is read. a/d conversion stops. adcr0 intad0 adcs0
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 175 (6) noise prevention to maintain a resolution of 8 bits, watch out for noise on the av ref and ani0 to ani7 pins. the higher the output impedance of the analog i nput source, the larger the effect fr om noise. to reduce noise, attach an external capacitor to the relevant pins as shown in figure 12-10. figure 12-10. analog input pin handling c = 100 to 1,000 pf if noise av ref or higher or av ss or lower is likely to enter the ani0 to ani7 pins, clamp the voltage at the pin by attaching a diode with a small v f (0.3 v or lower). v dd0 ani0 to ani7 av dd av ss v ss0 av ref reference voltage input (7) ani0 to ani7 the analog input pins (ani0 to ani7) are alternate-function pins. they are used also as port pins (p60 to p67). if any of ani0 to ani7 has been selected for a/d conversi on, do not execute input inst ructions for the ports. otherwise, the conversion re solution may become lower. if a digital pulse is applied to a pin adjacent to the analog input pins during a/d conversion, coupling noise may occur which prevents an a/d conversion result from being obtained as expec ted. avoid applying a digital pulse to pins adjacent to the analog input pins during a/d conversion. (8) input impedance of ani0 to ani7 pins this a/d converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs sampling. therefore at times other than sampli ng, only the leak current is output. during sampling, the current for charging the capacitor is also output, so t he input impedance fluctuat es and has no meaning. however, to ensure adequate sampling, it is reco mmended that the output im pedance of the analog input source be set to below 10 k ? , or a 100 pf capacitor be connected to the ani0 to ani7 pins (see figure 12- 10). (9) input impedance of the av ref pin a series resistor string of several 10 k ? is connected across the av ref and av ss pins. if the output impedance of the reference voltage source is high, th is high impedance is eventually connected in series with the series resistor string across the av ref and av ss pins, leading to a higher reference voltage error.
chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) user?s manual u14186ej5v0ud 176 (10) interrupt request flag (adif0) changing the content of a/d converter mode register 0 (adm0) does not clear the interrupt request flag (adif0). if the analog input pins are changed dur ing a/d conversion, t herefore, the a/d conv ersion result and the conversion end interrupt request flag may reflect the pr evious analog input immedi ately before writing to adm0 occurs. in this case, adif0 may already be set if it is read-accessed immediately after adm0 is write- accessed, even when a/d conversion has not been completed for the new analog input. in addition, when a/d conversion is rest arted, adif0 must be cleared beforehand. figure 12-11. a/d conversion end in terrupt request generation timing rewriting to adm0 (to begin conversion for anin) rewriting to adm0 (to begin conversion for anim) a/d conversion anin anin anim anim adif0 has been set, but conversion for anim has not been completed. adcr0 anin anin anim anim intad0 remarks 1. n = 0 to 7 2. m = 0 to 7 (11) av dd pin the av dd pin is used to supply power to the analog circuit. it is also used to supply power to the ani0 to ani7 input circuit. if your application is designed to be changed to backup power, the av dd pin must be supplied with the same voltage level as for the v dd0 pin, as shown in figure 12-12. figure 12-12. av dd pin handling main power source backup capacitor v dd0 av dd v ss0 av ss
user?s manual u14186ej5v0ud 177 chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) 13.1 10-bit a/d converter functions the 10-bit a/d converter is a 10-bit resolution converter that converts an analog input to a digital signal. this converter can control eight channels (ani0 to ani7) of analog inputs. a/d conversion can be star ted only by software. one of analog inputs ani0 to ani7 is selected for a/d conversion. a/d conversion is performed repeatedly, with an interrupt request (intad0) being issued eac h time a/d conversion is completed. 13.2 10-bit a/d converter configuration the 10-bit a/d converter consis ts of the following hardware. table 13-1. configuration of 10-bit a/d converter item configuration analog input 8 channels (ani0 to ani7) registers successive approx imation register (sar) a/d conversion result register 0 (adcr0) control registers a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0)
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 178 figure 13-1. block diagra m of 10-bit a/d converter sample-and-hold circuit voltage comparator successive approximation register (sar) controller 3 a/d conversion result register 0 (adcr0) tap selector av ss intad0 a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0) internal bus av ss p-ch av ref av dd ani4/p64 ani5/p65 ani6/p66 ani7/p67 ani0/p60 ani1/p61 ani2/p62 ani3/p63 selector adcs0 fr02 fr01 fr00 ads02 ads01 ads00 (1) successive approximation register (sar) sar receives the result of comparing an analog i nput voltage and a voltage at a voltage tap (comparison voltage), received from the series resistor string, starting from the most significant bit (msb). upon receiving all the bits, down to the least signifi cant bit (lsb), that is, upon the completion of a/d conversion, sar sends its contents to a/ d conversion result register 0 (adcr0). (2) a/d conversion result register 0 (adcr0) adcr0 is a 16-bit register that holds t he result of a/d conversion. the lower 6 bits are fixed to 0. each time a/d conversion ends, the conversion re sult in the successive approximati on register is loaded into adcr0. the results are stored in adcr0 from the most significant bit (msb). adcr0 can be read with a 16-bit memo ry manipulation instruction. reset input sets adcr0 to 0000h. adcr0 symbol ff15h 0 0 0 0 0 0 ff14h ff14h, ff15h address after reset 0000h r/w r caution when the pd78f9177, the flash memory counterpart of the pd789166 or pd789167, is used, the register can be accessed in 8-bit units. however, only an object file assembled with the pd789166 or pd789167 can be used. the sam e is also true for the pd78f9177y, the flash memory counterpart of the pd789166y or pd789167y. when the pd78f9177y is used, the regist er can be accessed in 8-bit uni ts. however, only an object file assembled with the pd789166y or pd789167y can be used.
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 179 (3) sample-and-hold circuit the sample-and-hold circuit samples consecutive analog inputs from the input ci rcuit, one by one, and sends them to the voltage comparator. the sampled analog input voltage is held during a/d conversion. (4) voltage comparator the voltage comparator compares an analog input with the volt age output by the series resistor string. (5) series resistor string the series resistor stri ng is configured between av ref and av ss . it generates the reference voltages against which analog inputs are compared. (6) ani0 to ani7 the ani0 to ani7 pins are the 8-channel analog input pins for the a/d converter. they are used to receive the analog signals for a/d conversion. caution do not supply the ani0 to ani7 pins with vo ltages that fall outside the rated range. if a voltage greater than or equal to av ref or less than or equal to av ss (even if within the absolute maximum ratings) is supplied to an y of these pins, the c onversion value for the corresponding channel will be undefi ned. furthermore, the con version values for the other channels may also be affected. (7) av ref pin this pin inputs the a/d c onverter reference voltage. it converts signals input to ani0 to ani7 into di gital signals according to the voltage applied between av ref and av ss . (8) av ss pin the av ss pin is a ground potential pin for t he a/d converter. this pin must be held at the same potential as the v ss0 pin, even while the a/d c onverter is not being used. (9) av dd pin the av dd pin is an analog power supply pin for the a/d conv erter. this pin must be held at the same potential as the v dd0 pin, even while the a/d c onverter is not being used.
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 180 13.3 10-bit a/d converter control registers the following two registers are used to control the 10-bit a/d converter. a/d converter mode register 0 (adm0) a/d input selection register 0 (ads0) (1) a/d converter mode register 0 (adm0) adm0 specifies the conversion time for analog inputs. it also specifies whether to enable conversion. adm0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears adm0 to 00h. figure 13-2. format of a/d converter mode register 0 symbol <7> 6 5 4 3 2 1 0 address after reset r/w adm0 adcs0 0 fr02 fr01 fr00 0 0 0 ff80h 00h r/w adcs0 a/d conversion control 0 conversion disabled 1 conversion enabled a/d conversion time selection note 1 fr02 fr01 fr00 at f x = 10.0 mhz operation note 2 at f x = 5.0 mhz operation 0 0 0 144/f x 14.4 s 28.8 s 0 0 1 120/f x 12.0 s 24.0 s 0 1 0 96/f x setting prohibited note 3 19.2 s 1 0 0 72/f x setting prohibited note 3 14.4 s 1 0 1 60/f x setting prohibited note 3 12.0 s note 4 1 1 0 48/f x setting prohibited note 3 other than above setting prohibited notes 1. set the a/d conversion time so that it satisfies the following ratings. 4.5 av ref av dd = v dd 5.5 v ?.. 12 s min. 2.7 av ref av dd = v dd < 4.5 v ?.. 14 s min. 1.8 av ref av dd = v dd < 2.7 v ?.. 28 s min. 2.7 av ref av dd = v dd 5.5 v ?.. 14 s min. 1.8 av ref av dd = v dd < 2.7 v ?.. 28 s min. 2. expanded-specificati on products only. 3. setting prohibited because the a/d conversi on time cannot satisfy the ratings in note 1 during operation under these f x conditions. 4. can only be set for expanded-specification products under the following conditions: 4.5 av ref av dd = v dd 5.5 v. other settings are prohibited. cautions 1. the result of conver sion performed immediately after bi t 7 (adcs0) is set is undefined. 2. the conversion result may be undefine d after adcs0 has been cleared to 0 (for details, see 13.5 (5) timing of unde fined a/d conversion result). remark f x : main system clock oscillation frequency
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 181 (2) a/d input selection register 0 (ads0) ads0 specifies the port used to input the analog voltage to be converted to a digital signal. ads0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears ads0 to 00h. figure 13-3. format of a/d input selection register 0 0 0 0 0 0 ads02 ads01 ads00 ads0 symbol address after reset r/w ff84h 00h r/w 76543210 analog input channel specification ads02 0 0 0 0 1 1 1 1 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ads01 0 0 1 1 0 0 1 1 ads00 0 1 0 1 0 1 0 1 caution bits 3 to 7 must all be set to 0.
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 182 13.4 10-bit a/d converter operation 13.4.1 basic operation of 10-bit a/d converter <1> select a channel for a/d conversion, usi ng a/d input selection register 0 (ads0). <2> the voltage supplied to the selected analog input c hannel is sampled using the sample and hold circuit. <3> after sampling continues for a certain period of ti me, the sample and hold circuit is put on hold to keep the input analog voltage until a/d conversion is completed. <4> bit 9 of the successive approximation register (sar) is set. the series resistor string tap voltage at the tap selector is set to half of av ref . <5> the series resistor string tap voltage is co mpared with the analog input voltage using the voltage comparator. if the analog input voltage is higher than half of av ref , the msb of sar is left set. if it is lower than half of av ref , the msb is reset. <6> bit 8 of sar is set automatically, and comparison sh ifts to the next stage. the next tap voltage of the series resistor string is selected according to bit 9, which reflects the previous comparison result, as follows: ? bit 9 = 1: three quarters of av ref ? bit 9 = 0: one quarter of av ref the tap voltage is compared with the analog input voltage. bit 8 is set or reset according to the result of comparison. ? analog input voltage tap voltage: bit 8 = 1 ? analog input voltage < tap voltage: bit 8 = 0 <7> comparison is repeated until bit 0 of sar is reached. <8> when comparison is completed for all of the 10 bits, a signi ficant digital result is le ft in sar. this value is sent to and latched in a/d conversion result register 0 (adcr0). at t he same time, it is possible to generate an a/d conversion end in terrupt request (intad0). cautions 1. the first a/d conver sion value immediately after a/d c onversion has been started may be undefined. 2. in standby mode, a/d c onverter operation is stopped.
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 183 figure 13-4. basic operati on of 10-bit a/d converter conversion time sampling time sampling a/d conversion undefined conversion result conversion result a/d converter operation sar adcr0 intad0 200h 300h or 100h a/d conversion continues until bit 7 (adcs 0) of a/d converter mode register 0 (adm0) is reset to 0 by software. if an attempt is made to write to adm0 or a/d input se lection register 0 (ads0) during a/d conversion, the ongoing a/d conversion is canceled. in th is case, a/d conversion is restarted fr om the beginning, if adcs0 is set to 1. reset input makes a/d conversion re sult register 0 (adcr0) undefined. 13.4.2 input voltage and conversion result the relationships between the analog input voltage at the analog input pi ns (ani0 to ani7) and the a/d conversion result (a/d conversion result register 0 (adcr0)) are represented by: adcr0 = int ( 1,024 + 0.5) or (adcr0 ? 0.5) v in < (adcr0 + 0.5) int( ): function that returns t he integer part of a parenthesized value v in : analog input voltage av ref : voltage of av ref pin adcr0: value in a/d conversion result register 0 (adcr0) figure 13-5 shows the relationship between the anal og input voltage and the a/d conversion result. v in av ref av ref 1,024 av ref 1,024
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 184 figure 13-5. relationship between analog input voltage and a/d conversion result 1,023 1,022 1,021 3 2 1 0 a/d conversion result (adcr0) 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 input voltage/av dd
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 185 13.4.3 operation mode of 10-bit a/d converter the a/d converter is initially in select mode. in this mode, a/d input selecti on register 0 (ads0) is used to select an analog input channel from ani0 to ani7 for a/d conversion. a/d conversion can be started only by software; that is, by setting a/d converter mode register 0 (adm0). the a/d conversion result is saved to a/d conversion result register 0 (adcr0 ). at the same time, an interrupt request signal (intad0) is generated. ? software-started a/d conversion setting bit 7 (adcs0) of a/d converter mode register 0 (adm0) to 1 triggers a/ d conversion for the voltage applied to the analog input pin specifi ed in a/d input selection register 0 (ads0). upon completion of a/d conversion, the conversion result is saved to a/d conversion result regist er 0 (adcr0). at the same time, an interrupt request signal (intad0) is generated. once a/d conversion is activated, and completed, another session of a/d conversion is started. a/d conversion is repeated until new data is written to adm0. if data where adcs0 is 1 is written to adm0 again during a/ d conversion, the ongoing sessi on of a/d conversion is discontinued, and a new session of a/d conversion begins for the new data. if data where adcs0 is 0 is written to adm0 again during a/d conversi on, a/d conversion is stopped immediately. figure 13-6. software-started a/d conversion rewriting adm0 adcs0 = 1 rewriting adm0 adcs0 = 1 adcs0 = 0 a/d conversion adcr0 intad0 anin anin anin anim anim stop anin anin anim conversion is discontinued; no conversion result is preserved. remarks 1. n = 0 to 7 2. m = 0 to 7
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 186 13.5 cautions related to 10-bit a/d converter (1) current consumpti on in standby mode in standby mode, the a/d converter stops operating. stopping conversion (bit 7 (adcs0) of a/d converter mode register 0 (adm0) = 0) can reduce the current consumption. figure 13-7 shows how to reduce t he current drain in standby mode. figure 13-7. how to reduce current consumption in standby mode av ref av ss p-ch series resistor string adcs0 (2) input range for ani0 to ani7 pins be sure to keep the input voltage at ani0 to ani7 wit hin its rating. if a voltage greater than or equal to av ref or less than or equal to av ss (even within the absolute maximum rati ng) is input into a conversion channel, the conversion output of the channel becomes undefined, and the conversion output of the other channels may also be affected. (3) conflict <1> conflict between writing to a/d conversion result register 0 (a dcr0) at the end of conversion and reading from adcr0 using instruction reading from adcr0 takes precedence. after reading, the new conversion result is written to adcr0. <2> conflict between writing to adcr0 at the end of conversion and writing to a/d conv erter mode register 0 (adm0) or a/d input sele ction register 0 (ads0) writing to adm0 or ads0 takes precedence. adcr0 is not written to. no a/d conversion end interrupt request signal (intad0) is generated. (4) conversion result immediatel y after start of a/d conversion the first a/d conversion value immediately after a/d conversion has been started is undefined. poll the a/d conversion end interrupt request (intad0) and drop the first conversion result.
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 187 (5) timing of undefined a/d conversion result the a/d conversion value may become undefined if the timing of the comp letion of a/d conversion and that to stop the a/d conversion operation conflict. therefore, read the a/d conversion result while the a/d conversion operation is in progress. to read the a/d conversion result after the a/d conversion operation has been stopped, stop the a/d conversion operation before the next conversion operat ion is completed. figures 13-8 and 13-9 show the timing at wh ich the conversion result is read. figure 13-8. conversion result read timi ng (if conversion result is undefined) end of a/d conversion end of a/d conversion normal conversion result undefined value normal conversion result is read. a/d conversion stops. undefined value is read. adcr0 intad0 adcs0 figure 13-9. conversion result read ti ming (if conversion result is normal) normal conversion result end of a/d conversion normal conversion result is read. a/d conversion stops. adcr0 intad0 adcs0
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 188 (6) noise prevention to maintain a resolution of 10 bits, watch out for noise on the av ref and ani0 to ani7 pins. the higher the output impedance of the analog i nput source, the larger the effect fr om noise. to reduce noise, attach an external capacitor to the relevant pins as shown in figure 13-10. figure 13-10. analog input pin handling c = 100 to 1,000 pf if noise av ref or higher or av ss or lower is likely to enter the ani0 to ani7 pin, clamp the voltage at the pin by attaching a diode with a small v f (0.3 v or lower). v dd0 ani0 to ani7 av dd av ss v ss0 av ref reference voltage input (7) ani0 to ani7 the analog input pins (ani0 to ani7) are alternate-function pins. they are used also as port pins (p60 to p67). if any of ani0 to ani7 has been selected for a/d conversi on, do not execute input inst ructions for the ports. otherwise, the conversion re solution may become lower. if a digital pulse is applied to a pin adjacent to the analog input pins during a/d conversion, coupling noise may occur which prevents an a/d conversion result from being obtained as expec ted. avoid applying a digital pulse to pins adjacent to the analog input pins during a/d conversion. (8) input impedance of ani0 to ani7 pins this a/d converter charges the internal sampling capacitor for about 1/10 of the conversion time, and performs sampling. therefore at times other than sampli ng, only the leak current is output. during sampling, the current for charging the capacitor is also output, so t he input impedance fluctuat es and has no meaning. however, to ensure adequate sampling, it is reco mmended that the output im pedance of the analog input source be set to below 10 k ? , or a 100 pf capacitor be connected to the ani0 to ani7 pins (see figure 13- 10). (9) input impedance of the av ref pin a series resistor string of several 10 k ? is connected across the av ref and av ss pins. if the output impedance of the reference voltage source is high, th is high impedance is eventually connected in series with the series resistor string across the av ref and av ss pins, leading to a higher reference voltage error.
chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) user?s manual u14186ej5v0ud 189 (10) interrupt request flag (adif0) changing the content of a/d converter mode register 0 (adm0) does not clear the interrupt request flag (adif0). if the analog input pins are changed dur ing a/d conversion, t herefore, the a/d conv ersion result and the conversion end interrupt request flag may reflect the pr evious analog input immedi ately before writing to adm0 occurs. in this case, adif0 may already be set if it is read-accessed immediately after adm0 is write- accessed, even when a/d conversion has not been completed for the new analog input. in addition, when a/d conversion is rest arted, adif0 must be cleared beforehand. figure 13-11. a/d conversion end in terrupt request generation timing a/d conversion adcr0 intad0 rewriting to adm0 (to begin conversion for anin) rewriting to adm0 (to begin conversion for anim) adif0 has been set, but conversion for anim has not been completed. anin anin anim anim anin anin anim anim remarks 1. n = 0 to 7 2. m = 0 to 7 (11) av dd pin the av dd pin is used to supply power to the analog circuit. it is also used to supply power to the ani0 to ani7 input circuit. if your application is designed to be changed to backup power, the av dd pin must be supplied with the same voltage level as for the v dd0 pin, as shown in figure 13-12. figure 13-12. av dd pin treatment main power supply backup capacitor v dd0 av dd v ss0 av ss
user?s manual u14186ej5v0ud 190 chapter 14 serial interface 20 14.1 functions of serial interface 20 serial interface 20 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not performed. power consumption is minimized in this mode. (2) asynchronous serial interface (uart) mode this mode is used to send and receive the one byte of data that follows a start bit. it supports full-duplex communication. serial interface 20 contains an uart-dedicated baud rate generator, enabling communication over a wide range of baud rates. it is also possible to define baud ra tes by dividing the frequency of the clock input to the asck20 pin. (3) 3-wire serial i/o mode (swit chable between msb-first a nd lsb-first transmission) this mode is used to transmit 8-bit data, using three lines: a serial clock (sck20) line and two serial data lines (si20 and so20). as it supports simultaneous transmissi on and reception, 3-wire serial i/o mode requires less processing time for data transmission than asynchr onous serial interface mode. because, in 3-wire serial i/o mode, it is possible to select whether 8-bit dat a transmission begins with the msb or lsb, serial interface 20 can be connected to any device regardless of whether that device is designed for msb-first or lsb-first transmission. 3-wire serial i/o mode is useful for connecting peri pheral i/o circuits and display controllers having conventional synchronous serial interfaces, such as those of the 75xl, 78k, and 17k series devices. 14.2 configuration of serial interface 20 serial interface 20 consists of the following hardware. table 14-1. configuration of serial interface 20 item configuration registers transmission shi ft register 20 (txs20) reception shift register 20 (rxs20) reception buffer register 20 (rxb20) control registers serial operati on mode register 20 (csim20) asynchronous serial interfac e mode register 20 (asim20) asynchronous serial interface st atus register 20 (asis20) baud rate generator control register 20 (brgc20) port mode register 2 (pm2) port 2 (p2)
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 191 internal bus reception buffer register 20 (rxb20) switching of the first bit asynchronous serial interface status register 20 (asis20) serial operation mode register 20 (csim20) reception shift register 20 (rxs20) csie20 sse20 dap20 dir20 csck20 ckp20 pe20 fe20 ove20 txe20 rxe20 ps201 ps200 cl20 sl20 asynchronous serial interface mode register 20 (asim20) transmission shift register 20 (txs20) transmission shift clock selector csie20 dap20 data phase control reception shift clock si20/p22/ rxd20 so20/p21/ txd20 4 parity detection stop bit detection reception data counter parity operation stop bit addition transmission data counter sl20, cl20, ps200, ps201 reception enabled reception clock detection clock start bit detection csie20 csck20 sck20/p20/ asck20 ss20/p25/ ti80 clock phase control reception detected internal clock output external clock input transmission and reception clock control baud rate generator note 4 tps203 tps202 tps201 tps200 csie20 csck20 f x /2 to f x /2 8 baud rate generator control register 20 (brgc20) intst20 intsr20/intcsi20 internal bus figure 14-1. block diagram of serial interface 20 note see figure 14-2 for the configuration of the baud rate generator. port mode register (pm21) output latch (p21)
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 192 reception detection clock transmission shift clock reception shift clock reception detected txe20 rxe20 csie20 selector selector selector 1/2 1/2 transmission clock counter reception clock counter 4 f x /2 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 2 sck20/asck20/p20 tps203 tps202 tps201 tps200 baud rate generator control register 20 (brgc20) internal bus figure 14-2. block diagram of baud rate generator 20
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 193 (1) transmission shift register 20 (txs20) txs20 is a register in which trans mission data is prepared. the transmi ssion data is output from txs20 bit serially. when the data length is seven bits, bits 0 to 6 of t he data in txs20 will be transmissi on data. writing data to txs20 triggers transmission. txs20 can be written with an 8-bit memory m anipulation instruction, but cannot be read. reset input sets txs20 to ffh. caution do not write to txs20 during transmission. txs20 and reception buffer register 20 (rxb 20) are mapped at the same address, so any attempt to read from txs20 results in a value being read from rxb20. (2) reception shift register 20 (rxs20) rxs20 is a register in which serial data, received at the rxd 20 pin, is converted to parallel data. once one entire byte has been received, rxs20 feeds the reception data to recept ion buffer register 20 (rxb20). rxs20 cannot be manipulated di rectly by a program. (3) reception buffer register 20 (rxb20) rxb20 holds reception data. a new reception data is transferred from re ception shift register 20 (rxs20) every 1-byte data reception. when the data length is seven bits, the reception data is sent to bits 0 to 6 of rxb20, in which the msb is always fixed to 0. rxb20 can be read with an 8-bit memory manipul ation instruction, but cannot be written. reset input makes rxb20 undefined. caution rxb20 and transmission shift register 20 (txs20) are mapped at the same address, so any attempt to write to rxb20 results in a value being written to txs20. (4) transmission controller the transmission controller controls transmission. for ex ample, it adds start, parity, and stop bits to the data in transmission shift register 20 (txs20), according to the setting of asynchronous serial interface mode register 20 (asim20). (5) reception controller the reception controller controls re ception according to the setting of asynchronous serial interface mode register 20 (asim20). it also checks for errors, such as parity errors, during recepti on. if an error is detected, asynchronous serial interface status register 20 (asis20) is set accord ing to the status of the error.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 194 14.3 control registers of serial interface 20 serial interface 20 is controll ed by the following registers. ? serial operation mode register 20 (csim20) ? asynchronous serial interfac e mode register 20 (asim20) ? asynchronous serial interface status register 20 (asis20) ? baud rate generator contro l register 20 (brgc20) ? port mode register 2 (pm2) ? port 2 (p2) (1) serial operation mode register 20 (csim20) csim20 is used to make the settings related to 3-wire serial i/o mode. csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. figure 14-3. format of serial operation mode register 20 csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection output at the falling edge of sck20. output at the rising edge of sck20. ss20-pin selection function of ss20/p25 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is active-low , and sck20 is high level in the idle state. clock is active-high , and sck20 is low level in the idle state. cautions 1. bits 4 and 5 must be set to 0. 2. csim20 must be cleared to 00h, if uart mode is selected. 3. switch operating modes after halt ing the serial transmit/receive operation. 4. when the external input cl ock is selected in 3-wire seria l i/o mode, set input mode by setting bit 0 of port mode register 2 (pm2) to 1.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 195 (2) asynchronous serial interface mode register 20 (asim20) asim20 is used to make the settings related to the asynchronous serial interface mode. asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. figure 14-4. format of asynchronous serial interface mode register 20 txe20 0 1 transmit operation control txe20 rxe20 ps201 ps200 cl20 sl20 00 asim20 symbol address after reset r/w ff70h 00h r/w <7><6>543210 transmit operation stop transmit operation enable rxe20 0 1 receive operation control receive operation stop receive operation enable ps201 0 0 1 1 parity bit specification ps200 0 1 0 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity cl20 0 1 transmit data character length specification 7 bits 8 bits sl20 0 1 transmit data stop bit length 1 bit 2 bits cautions 1. bits 0 and 1 must be set to 0. 2. if 3-wire serial i/o mode is select ed, asim20 must be cleared to 00h. 3. switch operating modes after ha lting serial transmit/receive operation.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 196 table 14-2. operating mode settings of serial interface 20 (1) operation stop mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 0 0 0 note 1 note 1 note 1 note 1 note 1 note 1 ? ? p22 p21 p20 other than above setting prohibited (2) 3-wire serial i/o mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 0 1 external clock sck20 input 1 0 1 0 1 msb internal clock sck20 output 0 1 external clock sck20 input 0 0 1 1 1 note 2 note 2 0 1 0 1 lsb internal clock si20 note 2 so20 (cmos output) sck20 output other than above setting prohibited (3) asynchronous serial interface mode asim20 csim20 txe20 rxe20 csie20 dir20 csck20 pm22 p22 pm21 p21 pm20 p20 first bit shift clock p22/si20/ rxd20 pin function p21/so20/ txd20 pin function p20/sck20/ asck20 pin function 1 external clock asck20 input 1 0 0 0 0 note 1 note 1 0 1 note 1 note 1 internal clock p22 txd20 (cmos output) p20 1 external clock asck20 input 0 1 0 0 0 1 note 1 note 1 note 1 note 1 internal clock p21 p20 1 external clock asck20 input 1 1 0 0 0 1 0 1 note 1 note 1 lsb internal clock rxd20 txd20 (cmos output) p20 other than above setting prohibited notes 1. these pins can be used for port functions. 2. when only transmission is used, this pin can be used as p22 (cmos i/o). remark : don?t care.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 197 (3) asynchronous serial interface status register 20 (asis20) asis20 indicates the type of a recepti on error, if an error occurs while asynchronous serial interface mode is set. asis20 is set with a 1-bit or 8-bit memory manipulation instruction. the contents of asis 20 are undefined in 3-wire serial i/o mode. reset input clears asis20 to 00h. figure 14-5. format of asynchronous se rial interface status register 20 pe20 0 1 parity error flag 00000 pe20 fe20 ove20 asis20 symbol address after reset r/w ff71h 00h r 76543210 no parity error has occurred. a parity error has occurred (when the transmit parity and receive parity do not match). fe20 0 1 flaming error flag no framing error has occurred. a framing error has occurred (when stop bit is not detected). note 1 ove20 0 1 overrun error flag no overrun error has occurred. an overrun error has occurred. note 2 (when the next receive operation is completed before the data is read from reception buffer register 20) notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asim 20), the stop bit detection at rec eption is performed with 1 bit. 2. be sure to read reception buffer register 20 (r xb20) when an overrun error occurs. if not, every time the data is received an overrun error occurs.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 198 (4) baud rate generator cont rol register 20 (brgc20) brgc20 is used to specify the serial clock for serial interface 20. brgc20 is set with an 8-bit memo ry manipulation instruction. reset input clears brgc20 to 00h. figure 14-6. format of baud rate generator control register 20 symbol 7 6 5 4 3 2 1 0 address after reset r/w brgc20 tps203 tps202 tps201 tps200 0 0 0 0 ff73h 00h r/w 3-bit counter source clock selection tps203 tps202 tps201 tps200 at f x = 10.0 mhz operation note 1 at fx = 5.0 mhz operation n 0 0 0 0 f x /2 5.00 mhz 2.50 mhz 1 0 0 0 1 f x /2 2 2.50 mhz 1.25 mhz 2 0 0 1 0 f x /2 3 1.25 mhz 625 khz 3 0 0 1 1 f x /2 4 625 khz 313 khz 4 0 1 0 0 f x /2 5 313 khz 156 khz 5 0 1 0 1 f x /2 6 156 khz 78.1 khz 6 0 1 1 0 f x /2 7 78.1 khz 39.1 khz 7 0 1 1 1 f x /2 8 39.1 khz 19.5 khz 8 1 0 0 0 external clock input to the asck20 pin note 2 ? other than above setting prohibited notes 1. expanded-specificati on products only. 2. an external clock can be used only in uart mode. cautions 1. when writing to brgc00 is perfo rmed during a communication operation, the output of baud rate generator is disr upted and communications cannot be performed normally. be sure not to write to brgc 00 during communication operations. 2. be sure not to select n = 1 in uart mode when f x > 2.5 mhz because the baud rate will exceed the rated range. 3. be sure not to select n = 2 in uart mode when f x > 5.0 mhz because the baud rate will exceed the rated range. 4. be sure not to select n = 1 in 3-wire serial i/o mode when f x > 5.0 mhz because the serial clock specification will be exceeded. 5. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the se ttings of tps200 to tps203 (1 n 8)
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 199 the baud rate transmit/receive clock to be generated is ei ther a signal scaled from the system clock, or a signal scaled from the clock input to the asck20 pin. (a) generation of baud ra te transmit/receive clo ck from system clock the transmit/receive clock is generated by scaling t he system clock. the baud rate of a clock generated from the system clock is estimated by using the following expression. [baud rate] = [bps] f x : main system clock oscillation frequency n: values in figure 14-6, determined by the values of tps200 to tps203 (2 n 8) table 14-3. example of relationship between system clock and baud rate at f x = 10.0 mhz note at f x = 5.0 mhz at f x = 4.9152 mhz baud rate (bps) n brgc20 set value error (%) n brgc20 set value error (%) n brgc20 set value error (%) 1,200 ? ? 8 70h 8 70h 2,400 8 70h 7 60h 7 60h 4,800 7 60h 6 50h 6 50h 9,600 6 50h 5 40h 5 40h 19,200 5 40h 4 30h 4 30h 38,400 4 30h 3 20h 3 20h 76,800 3 20h 1.73 2 10h 1.73 2 10h 0 note expanded-specification products only. cautions 1. be sure not to select n = 1 during operation at f x > 2.5 mhz because the baud rate will exceed the rated range. 2. be sure not to select n = 2 during operation at f x > 5.0 mhz because the baud rate will exceed the rated range. f x 2 n + 1 8
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 200 (b) generation of baud rate tr ansmit/receive clock from externa l clock input to asck20 pin the transmit/receive clock is generat ed by scaling the clock input from the asck20 pin. the baud rate of a clock generated from the clo ck input to the asck20 pin is ca lculated by using the following expression. [baud rate] = [bps] f asck : frequency of clock input to the asck20 pin table 14-4. relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 (c) generation of 3-wire serial i/o m ode serial clock from system clock the serial clock is generated by scaling the system cl ock. the serial clock frequency is calculated by using the following expression. brgc20 does not have to be set when the serial clock is input to the sck20 pin externally. serial clock frequency = [hz] f x : system clock oscillation frequency n: value determined by settings of tps200 to tps203 in fig. 14-6. f asck 16 f x 2 n+1
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 201 14.4 operation of serial interface 20 serial interface 20 provides the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode 14.4.1 operation stop mode in operation stop mode, serial transfer is not executed; theref ore, the power consumpt ion can be reduced. the p20/sck20/asck20, p21/so20/tx d20, and p22/si20/rxd20 pins can be used as normal i/o ports. (1) register setting operation stop mode is set by serial operation mode register 20 (csim20) and asynchronous serial interface mode register 20 (asim20). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 operation control in 3-wire serial i/o mode operation disabled operation enabled csie20 sse20 0 0 dap20 dir20 csck20 ckp20 csim20 <7> 6 5 4 symbol address after reset r/w ff72h 00h r/w 3210 caution bits 4 and 5 must be set to 0.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 202 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control transmit operation stopped transmit operation enabled receive operation stopped receive operation enabled rxe20 0 1 receive operation control txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 caution bits 0 and 1 must be set to 0.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 203 14.4.2 asynchronous serial interface (uart) mode in this mode, the one-byte data followi ng the start bit is transmitted/receiv ed and thus full-duplex communication is possible. this device incorporates an uart- dedicated baud rate generator that enabl es communications at the desired baud rate from many options. in addition, the baud rate can also be defined by dividing the clock input to the asck20 pin. the uart-dedicated baud rate generator also can output t he 31.25 kbps baud rate that complies with the midi standard. (1) register setting uart mode is set by serial operat ion mode register 20 (csim20), a synchronous serial interface mode register 20 (asim20), asynchronous serial interface st atus register 20 (asis20) , baud rate generator control register 20 (brgc20), port mode r egister 2 (pm2), and port 2 (p2).
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 204 (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. set csim20 to 00h when uart mode is selected. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 00 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>6543210 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20. outputs at the rising edge of sck20. ss20-pin selection function of ss20/p25 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is active-low, and sck20 is high level in the idle state. clock is active-high, and sck20 is low level in the idle state. cautions 1. bits 4 and 5 must be set to 0. 2. csim20 must be cleared to 00h, if uart mode is selected. 3. switch operating modes after ha lting serial transmit/receive operation.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 205 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control transmit operation stop transmit operation enable receive operation stop receive operation enable rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 cautions 1. bits 0 and 1 must be set to 0. 2. switch operating modes after halt ing the serial transmit/receive operation.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 206 (c) asynchronous serial interface status register 20 (asis20) asis20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asis20 to 00h. pe20 0 1 parity error flag parity error not generated parity error generated (when the parity of transmit data does not match) framing error not generated framing error generated (when stop bit is not detected) note 1 overrun error not generated overrun error generated note 2 (when the next receive operation is completed before data is read from reception buffer register 20) fe20 0 1 0 1 framing error flag overrun error flag ove20 0 0 0 0 0 pe20 fe20 ove20 asis20 76 54 symbol address after reset r/w ff71h 00h r 3210 notes 1. even when the stop bit length is set to 2 bits by setting bit 2 (sl20) of asynchronous serial interface mode register 20 (asi m20), the stop bit detection at reception is performed with 1 bit. 2. be sure to read reception buffer register 20 (rxb20) when an overrun error occurs. if not, every time the data is receiv ed an overrun error is generated.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 207 (d) baud rate generator cont rol register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. symbol 7 6 5 4 3 2 1 0 address after reset r/w brgc20 tps203 tps202 tps201 tps200 0 0 0 0 ff73h 00h r/w tps203 tps202 tps201 tps200 3-bit c ounter source clock selection n at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 0 0 0 0 f x /2 5.00 mhz 2.50 mhz 1 0 0 0 1 f x /2 2 2.50 mhz 1.25 mhz 2 0 0 1 0 f x /2 3 1.25 mhz 625 khz 3 0 0 1 1 f x /2 4 625 khz 313 khz 4 0 1 0 0 f x /2 5 313 khz 156 khz 5 0 1 0 1 f x /2 6 156 khz 78.1 khz 6 0 1 1 0 f x /2 7 78.1 khz 39.1 khz 7 0 1 1 1 f x /2 8 39.1 khz 19.5 khz 8 1 0 0 0 external clock input to the asck20 pin ? other than above setting prohibited note expanded-specification products only. cautions 1. when writing to brgc20 is performed during a communication operation, the output of the baud rate generator is disrupted and communications cannot be performed normally. be sure not to write to brgc20 during a communication operation. 2. be sure not to select n = 1 during operation at f x > 2.5 mhz because the baud rate will exceed the rated range. 3. be sure not to select n = 2 during operation at f x > 5.0 mhz because the baud rate will exceed the rated range. 4. when the external input clock is selected, set port mode register 2 (pm2) to input mode. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the settings of tps200 to tps203 (1 n 8)
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 208 the baud rate transmit/receive clock to be generated is either a signal scaled from the system clock, or a signal scaled from the clock input to the asck20 pin. (i) generation of baud rate transm it/receive clock from system clock the transmit/receive clock is generated by scaling the system clock. the baud rate of a clock generated from the system clock is estimat ed by using the following expression. [baud rate] = [bps] f x : main system clock oscillation frequency n: values in the above table determined by the settings of tps200 to tps203 (2 n 8) table 14-5. example of relationship between system clock and baud rate at f x = 10.0 mhz note at f x = 5.0 mhz at f x = 4.9152 mhz baud rate (bps) n brgc20 set value error (%) n brgc20 set value error (%) n brgc20 set value error (%) 1,200 ? ? 8 70h 8 70h 2,400 8 70h 7 60h 7 60h 4,800 7 60h 6 50h 6 50h 9,600 6 50h 5 40h 5 40h 19,200 5 40h 4 30h 4 30h 38,400 4 30h 3 20h 3 20h 76,800 3 20h 1.73 2 10h 1.73 2 10h 0 note expanded-specificati on products only. cautions 1. be sure not to select n = 1 during operation at f x > 2.5 mhz because the baud rate will exceed the rated range. 2. be sure not to select n = 2 during operation at f x > 5.0 mhz because the baud rate will exceed the rated range. f x 2 n + 1 8
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 209 (ii) generation of baud rate tr ansmit/receive clock from externa l clock input to asck20 pin the transmit/receive clock is generated by scaling the clock input from t he asck20 pin. the baud rate of a clock generated from the clock input to the asck20 pin is estimated by using the following expression. [baud rate] = [bps] f asck : frequency of clock input to asck20 pin table 14-6. relationship between asck20 pin input frequency and baud rate (when brgc20 is set to 80h) baud rate (bps) asck20 pin input frequency (khz) 75 1.2 150 2.4 300 4.8 600 9.6 1,200 19.2 2,400 38.4 4,800 76.8 9,600 153.6 19,200 307.2 31,250 500.0 38,400 614.4 f asck 16
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 210 (2) communication operation (a) data format the transmit/receive data format is as shown in figur e 14-7. one data frame c onsists of a start bit, character bits, parity bit, and stop bit(s). the specification of character bit length in one data frame, parity select ion, and specificat ion of stop bit length is carried out with asynchronous seri al interface mode register 20 (asim20). figure 14-7. asynchronous serial interface transmit/receive data format d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame ? start bits ................... 1 bit ? character bits............ 7 bits/8 bits ? parity bits .................. ev en parity/odd parity/ 0 parity/no parity ? stop bit(s) ................. 1 bit/2 bits when 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (b it 7) is ignored, and in reception t he most significant bit (bit 7) is always ?0?. the serial transfer rate is selected by baud rate generator control register 20 (brgc20). if a serial data receive error is generated, the re ceive error contents can be determined by reading the status of asynchronous serial inte rface status register 20 (asis20).
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 211 (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receivi ng side. with even parit y and odd parity, a one-bit (odd number) error can be detected. with 0 par ity and no parity, an erro r cannot be detected. (i) even parity ? at transmission the parity bit is determined so t hat the number of bits with a va lue of ?1? in the transmit data including the parity bit is even. the parity bit value should be as follows. the number of bits with a value of ?1 ? is an odd number in transmit data: 1 the number of bits with a value of ?1 ? is an even number in transmit data: 0 ? at reception the number of bits with a value of ?1? in the receive data including parity bit is counted, and if the number is odd, a parity error is generated. (ii) odd parity ? at transmission conversely to even parity, the parit y bit is determined so that the num ber of bits with a value of ?1? in the transmit data including parity bit is odd. the parity bit value should be as follows. the number of bits with a value of ?1 ? is an odd number in transmit data: 0 the number of bits with a value of ?1 ? is an even number in transmit data: 1 ? at reception the number of bits with a value of ?1? in the receive data including parity bit is counted, and if the number is even, a parity error is generated. (iii) 0 parity when transmitting, the parity bit is set to ?0? irrespective of the transmit data. at reception, a parity bit check is not perform ed. therefore, a parit y error is not generated, irrespective of whether the parity bit is set to ?0? or ?1?. (iv) no parity a parity bit is not added to the trans mit data. at reception, data is received assuming that there is no parity bit. since there is no parit y bit, a parity error is not generated.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 212 (c) transmission a transmit operation is started by writing transmit data to transmission shift register 20 (txs20). the start bit, parity bit, and stop bi t(s) are added automatically. when the transmit operation starts, the data in txs20 is shifted out, and when txs20 is empty, a transmission completion interr upt (intst20) is generated. figure 14-8. asynchronous serial interf ace transmission completion interrupt timing (a) stop bit length: 1 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 (b) stop bit length: 2 stop parity d7 d6 d2 d1 d0 start txd20 (output) intst20 caution do not rewrite asynchronous serial in terface mode register 20 (asim20) during a transmit operation. if the asim20 regist er is rewritten to during transmission, subsequent transmission may not be perf ormed (the normal state is restored by reset input). it is possible to determine whether transm ission is in progress by software by using a transmission completion interrupt (intst20) or the interrupt request flag (stif20) set by intst20.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 213 (d) reception when bit 6 (rxe20) of asynchronous serial interface mode register 20 (asim20) is set to 1, a receive operation is enabled and sampling of t he rxd20 pin input is performed. rxd20 pin input sampling is performed using t he serial clock specified by brgc20. when the rxd20 pin input becomes lo w, the 3-bit counter starts count ing, and at the time when half the time determined by the specified baud rate has passed, the data sampling start timing signal is output. if the rxd20 pin input sampled again as a result of this st art timing signal is low, it is identified as a start bit, the 3-bit counter is initializ ed and starts counting, and data sampli ng is performed. when character data, a parity bit, and one stop bit ar e detected after the start bit, re ception of one frame of data ends. when one frame of data has been receiv ed, the receive data in the shi ft register is transferred to reception buffer register 20 (rxb20), and a recept ion completion interrupt (intsr20) is generated. if an error is generated, the receive data in which t he error was generated is still transferred to rxb20, and intsr20 is generated. if the rxe20 bit is reset to 0 during the receive oper ation, the receive operati on is stopped immediately. in this case, the contents of rxb20 and asynchronous serial interface status register 20 (asis20) are not changed, and intsr 20 is not generated. figure 14-9. asynchronous serial inte rface reception completion interrupt timing stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 caution be sure to read recepti on buffer register 20 (rxb20) even if a receive error occurs. if rxb20 is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 214 (e) receive errors the following three errors may occur during a receiv e operation: a parity e rror, framing error, and overrun error. after data reception, an error flag is se t in asynchronous serial interface status register 20 (asis20). receive error caus es are shown in table 14-7. it is possible to determine what kind of error o ccurred during reception by reading the contents of asis20 in the reception error interrupt servicing (see figures 14-9 and 14-10 ). the contents of asis20 are reset to 0 by reading reception buffer regi ster 20 (rxb20) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). table 14-7. receive error causes receive errors cause parity error transmission-time parity and reception data parity do not match framing error stop bit not detected overrun error reception of next data is completed bef ore data is read from reception buffer register figure 14-10. receive error timing (a) parity error occurred stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 (b) framing error or overrun error occurred stop parity d7 d6 d2 d1 d0 start rxd20 (input) intsr20 cautions 1. the contents of the asis20 regist er are reset to 0 by reading reception buffer register 20 (rxb20) or receiving the next data. to ascertain the error contents, read asis20 before reading rxb20. 2. be sure to read reception buffer re gister 20 (rxb20) even if a receive error occurred. if rxb20 is not read, an ove rrun error will occur when the next data is received, and the receive error st ate will continue indefinitely.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 215 (f) reading receive data when the reception completion inte rrupt (intsr20) occurs, receiv e data can be read by reading the value of reception buffer register 20 (rxb20). to read the receive data stored in reception buffer register 20 (rxb20), read while reception is enabled (rxe20 = 1). remark however, if it is necessary to read receiv e data after reception has stopped (rxe20 = 0), read using either of the following methods. (a) read after setting rxe20 = 0 after waiti ng for one cycle or more of the source clock selected by brgc20. (b) read after bit 2 (dir20) of serial operat ion mode register 20 (csim20) is set (1). program example of (a) (brgc20 = 00h (source clock = fx/2)) intrex: ; nop ;2 clocks clr1 rxe20 ;reception stopped mov a, rxb20 ;read receive data program example of (b) intrxe: ; set1 csim20.2 ;dir20 flag is set to lsb first clr1 rxe20 ;reception stopped mov a, rxb20 ;read receive data
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 216 (3) cautions rela ted to uart mode (a) when bit 7 (txe20) of asynchronous serial inte rface mode register 20 ( asim20) is cleared during transmission, be sure to set transmission shift regist er 20 (txs20) to ffh, then set txe20 to 1 before executing the next transmission. (b) when bit 6 (rxe20) of asynchronous serial inte rface mode register 20 ( asim20) is cleared during reception, reception buffer regist er 20 (rxb20) and the reception comp letion interrupt (intsr20) are as follows. parity rxd20 pin rxb20 intsr20 <3> <1> <2> when rxe20 is set to 0 at the time indicated by <1> , rxb20 holds the previous data and intsr20 is not generated. when rxe20 is set to 0 at the time indicated by <2> , rxb20 renews the data and intsr20 is not generated. when rxe20 is set to 0 at the time indicated by <3> , rxb20 renews the data and intsr20 is generated.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 217 14.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional synchronous se rial interface, such as the 75xl se ries, 78k series, 17k series, etc. communication is performed using three lines: the serial clock (sck20), serial output (so20), and serial input (si20). (1) register setting 3-wire serial i/o mode settings are performed usi ng serial operation mode register 20 (csim20), asynchronous serial interface mode register 20 (asim 20), baud rate generator contro l register 20 (brgc20), port mode register 2 (pm2), and port 2 (p2). (a) serial operation mode register 20 (csim20) csim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears csim20 to 00h. csie20 0 1 3-wire serial i/o mode operation control csie20 sse20 0 0 dap20 dir20 csck20 ckp20 csim20 symbol address after reset r/w ff72h 00h r/w <7>654321 0 operation disabled operation enabled dir20 0 1 first-bit specification msb lsb csck20 0 1 3-wire serial i/o mode clock selection external clock input to the sck20 pin output of the dedicated baud rate generator sse20 0 1 not used used dap20 0 1 3-wire serial i/o mode data phase selection outputs at the falling edge of sck20. outputs at the rising edge of sck20. ss20-pin selection function of ss20/p25 pin port function 0 1 communication status communication enabled communication enabled communication disabled ckp20 0 1 3-wire serial i/o mode clock phase selection clock is active-low , and sck20 is at high level in the idle state. clock is active-high , and sck20 is at low level in the idle state. cautions 1. bits 4 and 5 must be set to 0. 2. switch operating modes after halt ing the serial transmit/receive operation. 3. when the external input clock is selected in 3-wire serial i/o mode, set input mode by setting bit 0 of port mode register 2 (pm2) to 1.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 218 (b) asynchronous serial interface mode register 20 (asim20) asim20 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears asim20 to 00h. txe20 0 1 transmit operation control transmit operation stop transmit operation enable receive operation stop receive operation enable rxe20 0 1 0 1 0 0 0 1 0 1 1 1 no parity always add 0 parity at transmission. parity check is not performed at reception (no parity error is generated). odd parity even parity receive operation control ps201 parity bit specification ps200 cl20 0 1 sl20 character length specification 7 bits 8 bits 1 bit 2 bits transmit data stop bit length specification txe20 rxe20 ps201 ps200 cl20 sl20 0 0 asim20 <7> <6> 5 4 symbol address after reset r/w ff70h 00h r/w 3210 cautions 1. bits 0 and 1 must be set to 0. 2. asim20 must be cleared to 00h if 3-wire serial i/o mode is selected. 3. switch operating modes after ha lting serial transmit/receive operation.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 219 (c) baud rate generator cont rol register 20 (brgc20) brgc20 is set with an 8-bit memory manipulation instruction. reset input clears brgc20 to 00h. symbol 7 6 5 4 3 2 1 0 address after reset r/w brgc20 tps203 tps202 tps201 tps200 0 0 0 0 ff73h 00h r/w tps203 tps202 tps201 tps200 3-bit c ounter source clock selection n at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 0 0 0 0 f x /2 5.00 mhz 2.50 mhz 1 0 0 0 1 f x /2 2 2.50 mhz 1.25 mhz 2 0 0 1 0 f x /2 3 1.25 mhz 625 khz 3 0 0 1 1 f x /2 4 625 khz 313 khz 4 0 1 0 0 f x /2 5 313 khz 156 khz 5 0 1 0 1 f x /2 6 156 khz 78.1 khz 6 0 1 1 0 f x /2 7 78.1 khz 39.1 khz 7 0 1 1 1 f x /2 8 39.1 khz 19.5 khz 8 other than above setting prohibited note expanded-specification products only. cautions 1. when writing to brgc20 is pe rformed during a communication operation, the baud rate generator output is disrupted a nd communications cannot be performed normally. be sure not to write to brgc20 during a communication operation. 2. if f x > 5.0 mhz in the 3-wire serial i/o mode, this setting is prohibited because n = 1 exceeds the rated range of the serial clock. remarks 1. f x : main system clock oscillation frequency 2. n: values determined by the se ttings of tps200 to tps203 (1 n 8) if the internal clock is used as the serial clock fo r 3-wire serial i/o mode, set the tps200 to tps203 bits to set the frequency of the serial clock. to obtai n the frequency to be set, use the following expression. when an external clock is used, setting brgc20 is not necessary. serial clock frequency = [hz] f x : main system clock oscillation frequency n: values in the above table determined by the settings of tps200 to tps203 (1 n 8) f x 2 n + 1
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 220 (2) communication operation in 3-wire serial i/o mode, data transmission/recept ion is performed in 8-bit units. data is transmitted/received bit by bit in syn chronization with the serial clock. transmission shift register (txs20/sio20) and recept ion shift register (rxs20) shift operations are performed in synchronization with the fall of the serial clock (sck20). then transmit data is held in the so20 latch and output from the so20 pin. also, receive data input to the si 20 pin is latched in the reception buffer register (rxb20/sio20) on the rise of sck20. at the end of an 8-bit transfer, the operation of txs20/ sio20 and rxs20 stops automatically, and the interrupt request signal (i ntcsi20) is generated. figure 14-11. 3-wire serial i/o mode timing (1/7) (i) master operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 note si20 sio20 write intcsi20 note the value of the last bit previously output is output.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 221 figure 14-11. 3-wire serial i/o mode timing (2/7) (ii) slave operation timing (when dap20 = 0, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 note so20 sio20 write intcsi20 note the value of the last bit previously output is output. (iii) slave operation (when dap20 = 0, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 note 1 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 222 figure 14-11. 3-wire serial i/o mode timing (3/7) (iv) master operation (when dap20 = 0, ckp20 = 1, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20 (v) slave operation (when dap20 = 0, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first rising edge of sck20. ma ke sure that the master outputs the first bit before the first rising of sck20.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 223 figure 14-11. 3-wire serial i/o mode timing (4/7) (vi) slave operation (when dap20 = 0, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first rising edge of sck20. make sure that the master outputs the first bit before the first rising of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state. (vii) master operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 do7 do6 do5 do4 do3 do2 do1 do0 di7 di6 di5 di4 di3 di2 di1 di0 sck20 so20 si20 sio20 write intcsi20
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 224 figure 14-11. 3-wire serial i/o mode timing (5/7) (viii) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 sck20 si20 so20 sio20 write intcsi20 sio20 write (master) note note the data of si20 is loaded at the first falling edge of sck20. ma ke sure that the master outputs the first bit before the first falling of sck20. (ix) slave operation (when dap20 = 1, ckp20 = 0, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 note 2 sck20 si20 hi-z hi-z so20 sio20 write ss20 intcsi20 do0 sio20 write (master) note 1 notes 1. the data of si20 is loaded at the first falling edge of sck20. make sure that the master outputs the first bit before the first falling of sck20. 2. so20 is high until ss20 rises after completion of do0 output. when ss20 is high, so20 is in a high-impedance state.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 225 figure 14-11. 3-wire serial i/o mode timing (6/7) (x) master operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 do7 note do6 do5 do4 do3 do2 do1 di7 di6 di5 di4 di3 di2 di1 sck20 so20 si20 sio20 write intcsi20 di0 do0 note the value of the last bit previously output is output. (xi) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 0) 12345678 di7 di6 di5 di4 di3 di2 di1 sck20 si20 so20 sio20 write intcsi20 do7 note do6 do5 do4 do3 do2 do1 do0 di0 note the value of the last bit previously output is output.
chapter 14 serial interface 20 user?s manual u14186ej5v0ud 226 figure 14-11. 3-wire serial i/o mode timing (7/7) (xii) slave operation (when dap20 = 1, ckp20 = 1, sse20 = 1) 12345678 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 note 2 sck20 si20 note 1 so20 hi-z hi-z ss20 sio20 write intcsi20 notes 1. the value of the last bit previously output is output. 2. do0 is output until ss20 rises. when ss20 is high, so20 is in a high-impedance state. (3) transfer start serial transfer is started by setting transfer data to the transmission shift regist er (txs20/sio20) when the following two conditions are satisfied. ? serial operation mode register 20 (csim20) bit 7 (csie20) = 1 ? internal serial clock is stopped or sck 20 is high after 8-bit serial transfer. caution if csie20 is set to 1 after data is wr itten to txs20/sio20, tr ansfer does not start. a termination of 8-bit transfer stops the serial tr ansfer automatically and generat es the interrupt request signal (intcsi20).
user?s manual u14186ej5v0ud 227 chapter 15 smb0 ( pd789167y and 789177y subseries) 15.1 smb0 functions smb0 (system management bus) has t he following two types of modes. ? operation stop mode ? smb mode (supporting multiple masters) (a) operation stop mode this mode is used when serial transfer is not performed. power consumption is minimized in this mode. (b) smb mode (supporting multiple masters) this mode is used for performing 8-bit data transmission to several devices, using a serial clock (scl0) line and a serial data bus (sda0) line. in this mode, which conforms to the smb format, st art conditions, data, and stop conditions can be output on the serial data bus during transmissi on. moreover, these data can be aut omatically detec ted by hardware during reception. in smb0, scl0 and sda0 are open-drain outputs, and therefor e a pull-up resistor is required for the serial clock line and serial data bus line. i 2 c (inter ic) bus standard mode or high-speed mode can be specifi ed by software in smb mode. figure 15-1 shows the block diagram of smb0.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 228 smb control register 0 (smbc0) acknowledge detector start condition detector stop condition detector serial clock counter wakeup generator interrupt request signal generator prescaler smb clock selection register 0 (smbcl0) internal bus cld0 dad0 smc0 dfc0 cl01 cl00 smbe0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 internal bus figure 15-1. block diagram of smb0 tos02 tos01 tos00 svin0 lvl01 lvl00 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 + e + e f x /2 f x serial clock controller serial clock wait controller sclctl0 awtim0 scl0/ p23 sda0/ p24 n-ch open-drain output n-ch open-drain output selector selector smb slave address register 0 (smbsva0) smb shift register 0 (smb0) d q data hold time collector timeout count & controller scl ctl0 awtim0 stie0 toen0 tocl00 intsmbov0 intsmb0 tocl01 f x /2 6 f x /2 7 f x /2 8 f xt noise eliminator noise eliminator reference generator smb status register 0 (smbs0) smb mode register 0 (smbm0) smb input level setting register 0 (smbvi0) cl00, cl01 acknowledge detector exc0
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 229 15.2 smb0 configuration smb0 consists of the following hardware. table 15-1. configuration of smb0 item configuration registers smb shift register 0 (smb0) smb slave address register 0 (smbsva0) control registers smb control register 0 (smbc0) smb status register 0 (smbs0) smb clock selection register 0 (smbcl0) smb mode register 0 (smbm0) smb input level setting register 0 (smbvi0) port mode register 2 (pm2) port 2 (p2) (1) smb shift register 0 (smb0) smb0 is a register that converts 8- bit serial data to 8-bit parallel data, and vice-versa. smb0 is used both for transmitting and receiving data. write and read operations for smb0 contro l actual send and receive operations. smb0 is manipulated with an 8-bit me mory manipulation instruction. reset input clears smb0 to 00h. (2) smb slave address register 0 (smbsva0) this register is used to set a local address when used as a slave. smbsva0 is manipulated with an 8-bit me mory manipulation instruction. reset input clears smbsva0 to 00h. (3) so latch the so latch is a latch that hol ds the sda0 pin output level. (4) wakeup controller this circuit generates an interrupt request when the address value set in smb slave address register 0 (smbsva0) and the received address match, or when an extension code is received. (5) clock selector selects the sampling clock to be used. (6) serial clock counter counts the serial clock output/input during send/receive operations, to c heck if 8-bit data has been sent or received.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 230 (7) interrupt request signal generator controls the generation of interrupt request signals. smb interrupts are generated with the following two triggers. ? 8th clock or 9th clock of serial clock (set with wtim0 bit note ) ? generation of interrupt request at detection of stop condition (set with bit spie0 note ) note wtim0 bit: smb control register 0 (smbc0) bit 3 spie0 bit: smb control register 0 (smbc0) bit 4 (8) serial clock controller in master mode, generates the clock to be output to the scl0 pin from the sampling clock. (9) serial clock wait controller controls the wait timing. (10) acknowledge output circuit, stop condition detector, start conditi on detector, acknowledge detector perform output and detecti on of control signals. (11) data hold time corrector generates the data hold time from t he falling edge of the serial clock.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 231 15.3 smb0 control registers the following five registers are used to control smb0. ? smb control register 0 (smbc0) ? smb status register 0 (smbs0) ? smb clock selection register 0 (smbcl0) ? smb mode register 0 (smbm0) ? smb input level setting register 0 (smbvi0) the following registers are also used. ? smb shift register 0 (smb0) ? smb slave address register 0 (smbsva0) (1) smb control register 0 (smbc0) this register sets smb operation enable/disable, the wait timing, and other smb operations. smbc0 is manipulated with a 1-bit or 8-bi t memory manipulation instruction. reset input clears smbc0 to 00h. caution set port mode register 2 (pm2 ) as follows in smb mode. reset the output latch to 0. ? set p23 (scl0) in output mode (pm23 = 0). ? set p24 (sda0) in output mode (pm24 = 0).
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 232 figure 15-2. format of smb control register 0 (1/4) smbe0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 smbc0 symbol address after reset r/w ff78h 00h r/w <6> <5> <4> <3> <2> <1> smbe0 0 1 clear conditions (smbe0 = 0) ? cleared with instruction ? cleared by reset input set conditions (smbe0 = 1) ? set with instruction smb operation note 1 operation disabled. presets smb status register 0 (smbs0). internal operation also disabled. operation enabled <7> <0> lrel0 0 1 the standby status continues until the following communication participation conditions are met. ? startup as master after detection of stop condition ? matching addresses or extension code reception after start condition clear conditions (lrel0 = 0) note 2 ? automatically cleared after execution ? cleared by reset input set conditions (lrel0 = 1) ? set with instruction escape from transmission normal operation escape from the current transmission and enter the standby status. automatically cleared after execution. this bit is used when extension codes not relevant to the local station are received. the scl0 and sda0 lines enter the high impedance status. the following flags are cleared. ? std0 ? stt0 ? spt0 ? ackd0 ? trc0 ? coi0 ? exc0 ? msts0 wrel0 0 1 clear conditions (wrel0 = 0) note 2 ? automatically cleared after execution ? cleared by reset input set conditions (wrel0 = 1) ? set with instruction wait cancel do not cancel wait. cancel wait. automatically cleared after wait cancellation. spie0 0 1 clear conditions (spie0 = 0) note 2 ? cleared with instruction ? cleared by reset input set conditions (spie0 = 1) ? set with instruction interrupt request generation at stop condition detection disabled enabled notes 1. before setting smbe0 to 1, fix the value of smb clock selection register 0 (smbcl0). to change the communication clock, clear smbe0 to 0 first before rewriting smbcl0. 2. this flag?s signals are made invalid by setting smbe0 = 0.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 233 figure 15-2. format of smb control register 0 (2/4) wtim0 0 1 the setting of this bit becomes invalid during address transmission, and becomes effective at the end of transmission. during operation as master, a wait is inserted at the falling edge of the 9th clock during address transmission. a slave that receives a local address enters the wait status at the falling edge of the 8th or 9th clock according to the setting of awtim0. a slave that receives an extension code enters the wait status at the falling edge of the 8th clock. clear conditions (wtim0 = 0) note ? cleared with instruction ? cleared by reset input set conditions (wtim0 = 1) ? set with instruction wait and interrupt request generation control generate interrupt request at falling edge of 8th clock. in case of master: wait with clock output at low level after 8 clocks have been output. in case of slave: wait master with clock set to low level after 8 clocks have been input. generate interrupt request at falling edge of 9th clock. in case of master: wait with clock at low level after 9 clocks have been output. in case of slave: wait master with clock set to low level after 9 clocks have been input. acke0 0 1 clear conditions (acke0 = 0) note ? cleared with instruction ? cleared by reset input set conditions (acke0 = 1) ? set with instruction acknowledge control acknowledge disabled acknowledge enabled. sda0 line set to low level during 9 clocks. however, invalid during address transmission, and valid when exc0 = 1. smbe0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 smbc0 symbol address after reset r/w ff78h 00h r/w <6> <5> <4> <3> <2> <1> <7> <0> note this flag?s signals are made invalid by setting smbe0 = 0.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 234 figure 15-2. format of smb control register 0 (3/4) cautions regarding set timing ? master receive operation: setting during transmission is prohibited. set acke0 = 0; can be set only after end of receive operation has been reported to slave. ? master transmit operation: note that start condition may not be generated normally during ack period. ? setting at the same time as spt0 is prohibited. ? after setting stt0, resetting is prohibited if the clear conditions have not been met. stt0 0 1 clear conditions (stt0 = 0) note ? cleared with instruction ? cleared upon defeat in arbitration ? cleared after generation of start condition by master ? cleared when lrel0 = 1 ? cleared when smbe0 = 0 ? cleared by reset input set conditions (stt0 = 1) ? set with instruction start condition trigger do not generate start condition. when bus is released (stop status): generate start conditions (activation as master). change sda0 line from high level to low level and generate start condition. then secure rated time and sets scl0 to low level. when not participating on bus: functions as start condition reservation flag. when set, automatically generate start condition after bus is released. smbe0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 smbc0 symbol address after reset r/w ff78h 00h r/w <6> <5> <4> <3> <2> <1> <7> <0> note this flag?s signals are made invalid by setting smbe0 = 0.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 235 figure 15-2. format of smb control register 0 (4/4) cautions regarding set timing ? master receive operation: setting during transmission is prohibited. set acke0 = 0; can be set only after end of receive operation has been notified to slave. ? master send operation: note that stop condition may not be generated normally during ack period. ? setting at the same time as stt0 is prohibited. ? set spt0 only during operation as master. note 1 ? after setting spt0, resetting is prohibited if the clear conditions have not been met. ? note that when wtim0 = 0, if spt0 is set during the wait period after 8-clock output, a stop condition is generated during the high-level period of the 9th clock following wait release. if it is necessary to output a 9th clock, change the setting of wtim0 from 0 to 1 during the wait period following 8-clock output, and set spt0 during the wait period following the 9th clock output. spt0 0 1 clear conditions (spt0 = 0) note 2 ? cleared with instruction ? cleared upon defeat in arbitration ? cleared automatically after detection of stop condition ? cleared when lrel0 = 1 ? cleared when smbe0 = 0 ? cleared by reset input set conditions (spt0 = 1) ? set with instruction stop condition trigger do not generate stop condition. generate stop condition (end transmission as master). after setting sda0 line to low level, set scl0 line to high level, or maintain scl0 line at high level. then, secure rated time, change sda0 line from low level to high level, and generate stop condition. smbe0 lrel0 wrel0 spie0 wtim0 acke0 stt0 spt0 smbc0 symbol address after reset r/w ff78h 00h r/w <6> <5> <4> <3> <2> <1> <7> <0> notes 1. set spt0 only during operation as master. however, for master operation by the time a stop condition is detected for the first time following operati on enable, spt0 must be se t once to generate a stop condition. 2. this flag?s signals are made invalid by setting smbe0 = 0. caution while smb status register 0 (smbs0) bit 3 (t rc0) = 1, when wrel0 is set at the 9th clock and wait is released, trc0 is cleared and th e sda0 line is set to high impedance. remarks 1. std0: smb status register 0 (smbs0) bit 1 ackd0: smb status register 0 (smbs0) bit 2 trc0: smb status register 0 (smbs0) bit 3 coi0: smb status register 0 (smbs0) bit 4 exc0: smb status register 0 (smbs0) bit 5 msts0: smb status register 0 (smbs0) bit 7 2. bits 0 and 1 (spt0, stt0) are 0 if read after data setting.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 236 (2) smb status register 0 (smbs0) this register indicates the smb status. smbs0 is manipulated with a 1-bit or 8-bit memory manipul ation instruction. smbs0 is a read-only register. reset input clears smbs0 to 00h. figure 15-3. format of smb status register 0 (1/3) msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 smbs0 symbol address after reset r/w ff79h 00h r msts0 0 1 clear conditions (msts0 = 0) ? cleared upon detection of stop condition ? cleared when ald0 = 1 ? cleared when lrel0 = 1 ? cleared when smbe0 changes from 1 to 0 ? cleared by reset input set conditions (msts0 = 1) ? set during generation of start condition master status slave status or communication wait status master transmission status exc0 0 1 clear conditions (exc0 = 0) ? cleared upon detection of start condition ? cleared upon detection of stop condition ? cleared when lrel0 = 1 ? cleared when smbe0 changes from 1 to 0 ? cleared by reset input extension code receive detection do not receive extension code. receive extension code. ald0 0 1 clear conditions (ald0 = 0) ? automatically cleared after reading smbs0 note ? cleared when smbe0 changes from 1 to 0 ? cleared by reset input set conditions (ald0 = 1) ? set upon defeat in arbitration arbitration defeat detection no arbitration, or won in arbitration. defeated in arbitration. msts0 cleared. set conditions (exc0 = 1) ? set when high 4 bits of received address are 0000 or 1111 (set at rising edge of 8th clock) <6> <5> <4> <3> <2> <1> <7> <0> note the bit is also cleared when a bit manipulation instruction is executed for any other bit smbs0.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 237 figure 15-3. format of smb status register 0 (2/3) coi0 0 1 clear conditions (coi0 = 0) ? cleared upon detection of start condition ? cleared upon detection of stop condition ? cleared when lrel0 = 1 ? cleared when smbe0 changes from 1 to 0 ? cleared by reset input set conditions (coi0 = 1) ? set when received address matches local address (sva0) (set at rising edge of 8th clock) matching address detection address does not match. address matches. ackd0 0 1 clear conditions (ackd0 = 0) ? cleared upon detection of stop condition ? cleared at rising edge of 1st clock of following byte ? cleared when lrel0 = 1 ? cleared when smbe0 changes from 1 to 0 ? cleared by reset input acknowledge output do not detect acknowledge. detect acknowledge. trc0 0 1 clear conditions (trc0 = 0) ? cleared upon detection of stop condition ? cleared when lrel0 = 1 ? cleared smbe0 changes from 1 to 0 ? cleared when wrel0 = 1 note ? cleared when ald0 changes from 0 to 1 ? cleared by reset input in case of master: ? when "1" is output to 1st byte lsb (transmission direction specification bit) in case of slave: ? upon detection of start condition in case of non-participation in communication receive/send status detection receive status (when not in send status). sets sda0 line to high impedance. send status. sets so that so latch value can be output to sda0 line (valid from falling edge of 9th clock of 1st byte). set conditions (trc0 = 1) in case of master: ? upon generation of start condition in case of slave: ? when "1" is input to 1st byte lsb (transmission direction specification bit) set conditions (ackd0 = 1) ? set when sda0 line is low level at rising edge of 9th clock of scl0 msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 smbs0 symbol address after reset r/w ff79h 00h r <6> <5> <4> <3> <2> <1> <7> <0> note when bit 3 (trc0) of smb status register 0 (sm bs0) is set to 1, bit 5 (wrel0) of smb control register 0 (smbc0) is set during the ninth clock and wait is canceled, after which trc0 is cleared and the sda0 line is set to high impedance.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 238 figure 15-3. format of smb status register 0 (3/3) std0 0 1 clear conditions (std0 = 0) ? cleared upon detection of stop condition ? cleared at rising edge of 1st clock of byte following address transmission ? cleared when lrel0 = 1 ? cleared when smbe0 changes from 1 to 0 ? cleared by reset input set conditions (std0 = 1) ? set upon detection of start condition start condition detection do not detect start condition. detect start condition. indicates that address transmission is in progress. spd0 0 1 clear conditions (spd0 = 0) ? cleared at rising edge of 1st clock of address transfer byte following detection of start condition after this bit has been set ? cleared when smbe0 changes from 1 to 0 ? cleared by reset input stop condition detection do not detect stop condition. detect stop condition. transmission by master is completed and bus is released. set conditions (spd0 = 1) ? set upon detection of stop condition msts0 ald0 exc0 coi0 trc0 ackd0 std0 spd0 smbs0 symbol address after reset r/w ff79h 00h r <6> <5> <4> <3> <2> <1> <7> <0> remark lrel0: smb control register 0 (smbc0) bit 6 smbe0: smb control register 0 (smbc0) bit 7
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 239 (3) smb clock selection register 0 (smbcl0) this register sets the smb transmission clock. smbcl0 is manipulated with a 1-bit or 8- bit memory manipulation instruction. reset input clears smbcl0 to 00h. table 15-2 shows the smb communication clocks. figure 15-4. format of smb clo ck selection register 0 (1/2) 0 0 cld0 dad0 smc0 dfc0 cl01 cl00 smbcl0 symbol address after reset r/w ff7ah 00h r/w note 1 6 <5> <4> 3 2 1 cld0 0 1 clear conditions (cld0 = 0) ? cleared when scl0 line is low level ? cleared when smbe0 = 0 ? cleared by reset input set conditions (cld0 = 1) ? set when scl0 line is high level scl0 line level detection (valid only when smbe0 = 1) detect that scl0 line is low level. detect that scl0 line is high level. 7 0 dad0 0 1 clear conditions (dad0 = 0) ? cleared when sda0 line is low level ? cleared when smbe0 = 0 ? cleared by reset input set conditions (dad0 = 1) ? set when sda0 line is high level sda0 line level detection (valid only when smbe0 = 1) detect that sda0 line is low level. detect that sda0 line is high level. smc0 0 1 clear conditions (smc0 = 0) ? cleared with instruction ? cleared by reset input set conditions (smc0 = 1) ? set with instruction operating mode switching iic standard mode or smb mode operation iic high-speed mode dfc0 0 1 digital filter operation control note 2 digital filter off digital filter on notes 1. bits 4 and 5 are read-only. 2. the digital filter can be used in high-speed mode. when used in hi gh-speed mode, the digital filter provides a slower response. caution bits 6 and 7 must be set to 0.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 240 figure 15-4. format of smb clo ck selection register 0 (2/2) cl01 0 0 1 1 cl00 0 1 0 1 communication clock f x /44 f x /86 f x /172 setting prohibited smb/iic standard mode (smc0 = 0) iic high-speed mode (smc0 = 1) f x /24 f x /48 0 0 cld0 dad0 smc0 dfc0 cl01 cl00 smbcl0 symbol address after reset r/w ff7ah 00h r/w note 6 <5> <4> 3 2 1 7 0 note bits 4 and 5 are read-only. caution to change the communication clock, stop ope rations (smbe0 = 0) fi rst before rewriting smbcl0. remark f x : main system clock oscillation frequency table 15-2. smb0 communication clock communication clock smc0 cl01 cl00 at f x = 10.0 mhz operation note 1 at f x = 5.0 mhz operation digital filter input delay 0 0 0 227.2 khz note 2 113.6 khz note 2 250 ns 0 0 1 116.2 khz note 2 58.13 khz 250 ns 0 1 0 58.13 khz 29.06 khz 500 ns 1 0 0 416.6 khz note 3 208.3 khz 250 ns 1 0 1 416.6 khz note 3 208.3 khz 250 ns 1 1 0 208.3 khz 104.1 khz 500 ns other than above setting prohibited notes 1. expanded-specification products only. 2. since the smb/iic standard mode st andards specify a range of 10 to 100 khz, this communication clock falls outside the specifications. 3. since the standards of the iic high-speed mode specify a range of 0 to 400 khz, this communication clock falls outside the specifications.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 241 (4) smb mode register 0 (smbm0) smbm0 is used to specify scl0 leve l control and interrupt control. smbm0 is manipulated with a 1-bit or 8- bit memory manipulation instruction. reset input sets smbm0 to 20h. figure 15-5. format of smb mode register 0 (1/2) sclctl0 scl level control note 1 scl0 is held low. 0 0 0 sclctl0 awtim0 stie0 toen0 tocl01 tocl00 smbm0 symbol address after reset r/w ff7ch 20h r/w 6 7 <5> <4> <3> <2> awtim0 at the slave, an interrupt request is generated on the falling edge of the 9th clock period when an address match (coi0 = 1) is found during address data reception. the clock is pulled low to cause the master to wait. 0 1 0 when scl0 is high, scl0 is held low after waiting until scl0 is made low. normal operation 1 stie0 start condition interrupt enable start condition interrupt generation is disabled. 0 normal operation 1 wait and interrupt control when an address match is found notes 2, 3 at the slave, an interrupt request is generated on the falling edge of the 8th clock period when an address match (coi0 = 1) is found during address data reception. the clock is pulled low to cause the master to wait. 1 toen0 time out count enable bit note 4 the time out count is cleared to 0, then count operation is disabled. 0 1 time out count operation is enabled. notes 1. if scl0 is made low by sclctl0, the wa it state cannot be released by wrel0. 2. when an extension code is received (exc0 = 1), a wait state is forcibly set in the 8th clock period. 3. during address transfer, the master waits in the 9th clock period. 4. an interrupt (intsmbov0) is gener ated when the time out counter ov erflows. the hardware does not reset the smb operation. ensure that smb oper ation is reset by software after intsmbov0 generation. caution bits 6 and 7 must be set to 0.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 242 figure 15-5. format of smb mode register 0 (2/2) tocl00 tocl01 time out clock f to selection bits f x /2 6 0 1 0 1 0 0 1 1 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f xt (32.768 khz) 0 0 sclctl0 awtim0 stie0 toen0 tocl01 tocl00 smbm0 symbol address after reset r/w ff7ch 20h r/w 6 7 <5> <4> <3> <2> 1 0 remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 243 (5) smb input level setting register 0 (smbvi0) smbvi0 is manipulated with a 1-bit or 8- bit memory manipulation instruction. reset input clears smbvi0 to 00h. figure 15-6. format of smb input level setting register 0 symbol 7 6 5 4 3 2 1 0 address after reset r/w smbvi0 0 tos02 tos01 tos00 svin0 0 lvl01 lvl00 ff7dh 00h r/w time out time selection bits tos02 tos01 tos00 at f x = 10.0 mhz operation note 1 at f x = 5.0 mhz operation at f xt = 32.768 khz operation f to = f x /2 6 f to = f x /2 7 f to = f x /2 8 f to = f x /2 6 f to = f x /2 7 f to = f x /2 8 f to = f xt 0 0 0 1024/f to 6.55 ms 13.1 ms 26.2 ms 13.1 ms 26.2 ms 52.4 ms 31.2 ms 0 0 1 896/f to 5.73 ms 11.4 ms 22.9 ms 11.4 ms 22.9 ms 45.8 ms 27.3 ms 0 1 0 768/f to 4.91 ms 9.83 ms 19.6 ms 9.83 ms 19.6 ms 39.3 ms 23.4 ms 0 1 1 640/f to 4.09 ms 8.19 ms 16.3 ms 8.19 ms 16.3 ms 32.7 ms 19.5 ms 1 0 0 512/f to 3.27 ms 6.55 ms 13.1 ms 6.55 ms 13.1 ms 26.2 ms 15.6 ms 1 0 1 384/f to 2.45 ms 4.91 ms 9.83 ms 4.91 ms 9.83 ms 19.6 ms 11.7 ms 1 1 0 256/f to 1.63 ms 3.27 ms 6.55 ms 3.27 ms 6.55 ms 13.1 ms 7.81 ms 1 1 1 128/f to 819 s 1.63 ms 3.27 ms 1.63 ms 3.27 ms 6.55 ms 3.90 ms svin0 input level selection bit 0 same input level as the ordinary hysteresis 1 the voltage set with lvl01 and lvl00i is used as the scl0 and sda0 input level threshold lvl01 lvl00 input level selection bits note 2 0 0 the input level is 0.1875 v dd . 0 1 the input level is 0.25 v dd . 1 0 the input level is 0.375 v dd . 1 1 the input level is 0.5 v dd . notes 1. expanded-specification products only. 2. set an input level from 0.75 to 1.25 v. caution bits 2 and 7 must be set to 0. remarks 1. f x : main system clock oscillation frequency 2. f xt : subsystem clock oscillation frequency 3. f to : clock selected using bits 0 and 1 (tocl00, tocl01) of smb mode register 0 (smbm0)
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 244 (6) smb shift register 0 (smb0) this register is used to perform serial transmit/recei ve (shift operation) in synchronization with the serial clock. read/write operations can be performed in 8-bit units, but do not wr ite data to smb0 during transmission. smb0 symbol address after reset r/w ff7eh 00h r/w 654 3 21 7 0 (7) smb slave address register 0 (smbsva0) this register stores the smb slave address. it can be read/written in 8-bit units, but bit 0 is fixed to 0. smbsva0 symbol address after reset r/w ff7bh 00h r/w 6543 2 1 7 0 0
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 245 15.4 smb0 definition and control methods the smb0 serial data transmission format and the m eanings of the signals used are described below. the transmission timing of the start condi tion, data, and stop condition output to the serial dat a bus of the smb0 is shown in figure 15-7. figure 15-7. smb0 serial data transmission timing 1 to 7 scl0 8 9 1 to 7 8 9 1 to 7 8 9 address start condition sda0 r/w ack data ack data ack stop condition the start condition, slave address, and st op condition are output by the master. sda0 of only the start condition and stop condition can be changed when scl0 is high. the acknowledge signal (ack) can be out put by either the master or slave (the slave outputs ack when an address is transferred. the receiver of the data outputs ack when 8-bit data is transferred). the master continuously outputs the serial clock (scl0). however, it is possible to prolong the low-level period of the scl0 and insert a wait in the case of the slave. 15.4.1 start condition a start condition is generated when the sd a0 pin changes from high level to low level while the scl0 pin is high level (serial clock is not output). t he start condition of the scl0 and sda0 pins is output at the start of serial transmission from the master to the sl ave. the slave incorporates hardwar e that detects the start condition. figure 15-8. start condition h scl0 sda0 the start condition is output when smb c ontrol register 0 (smbc0) bit 1 (stt0) is set to 1 in the stop condition detection status (std0: smb st atus register 0 (smbs0) bit 1 = 1). mor eover, when the start c ondition is detected, smbs0 bit 1 (std0) is set to 1, and when bit 3 (sti e0) of smbm0 is set to 1, intsmb0 is generated.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 246 15.4.2 address the 7-bit data following the start c ondition is defined as an address. an address consists of 7 bits of dat a output to select a particular slave among several slaves connected to the master via the bus line. theref ore, slaves on the bus line must each have a different address. slaves detect start conditions via har dware and check if the 7-bit data matc hes the value of smb slave address register 0 (smbsva0). if the 7-bit data and the smbsva0 value match, that slave is selected, and communication between the master and that slave is performed until the master issues a start condition or a stop condition. figure 15-9. address note address 1 a6 scl0 sda0 intsmb0 a5 a4 a3 a2 a1 a0 r/w 23456789 note if other than a local address or extension code is re ceived during slave operation, intsmb0 is not issued. addresses are written and output to smb shift register 0 (smb0) as 8 bits consisting of the slave address and the transmission direction (see 15.4.3 ). moreover, received addresses are written to smb0. slave addresses are allocated to the high 7 bits of smb0. 15.4.3 specification of transmission direction the master sends a 1-bit data following the 7-bit address to specify the transmission direction. when this transmission direction bit is 0, the master sends data to the slave. when this bit is 1, the slave sends data to the master. figure 15-10. specification of transmission direction note transmission direction specification 1 a6 scl0 sda0 intsmb0 a5 a4 a3 a2 a1 a0 r/w 23456789 ? ? ? note if other than a local address or extension code is re ceived during slave operation, intsmb0 is not issued.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 247 15.4.4 acknowledge signal (ack) the acknowledge signal (ack) is used to confirm recepti on of serial data on the transmitting and receiving sides. on the receiving side, an acknowledge signal is returned eac h time 8 bits of data are received. on the sending side, an acknowledge signal is normally received following trans mission of 8 bits of data. however, when the master is receiving, no acknowledge signal is output after the final data has been received. the transmitting side detects whether an acknowledge signal is returned following transmi ssion of 8 bits of data. if an acknowledge signal is returned, processing is continued assu ming that the data was successfully re ceived. if no acknowledge signal is returned by the slave, the master outputs a stop condition or a restart c ondition, and stops transmission. an acknowledge signal is not returned for the following two reasons. <1> reception was not performed normally. <2> the final data was received. if the receiving side sets the sda0 line to low level at the 9th clock, the ackno wledge signal becomes active (normal reception response). when smb control register 0 (smbc0) bit 2 (acke0) = 1, the acknowledge signal automatic generation enable state is entered. smb status register 0 (smbs0) bit 3 (trc0) is set by t he 8th bit following the 7-bit address. however, when the trc0 bit value is 0, receive status is selected, therefore set acke0 to 1. during a slave receive operation (trc0 = 0), if the slave side receives several bytes and does not require subsequent data, acke0 can be set to 0 so that t he master does not start the next transmission. in the same way, if, during a master receive operati on (trc0 = 0), subsequent data is not required and you want to output a restart condition or a stop condition, set acke0 to 0 so that no ack signal is output. this must be done so that the data?s msb is not output to the sda0 line during the slave transmission operation (transmission stop). figure 15-11. acknowledge signal 1 a6 scl0 sda0 a5 a4 a3 a2 a1 a0 r/w 23456789 ack when a slave receives a local address, it automatically output s an acknowledge signal in synchronization with the falling edge of the 8th clock of scl0, r egardless of the value of acke0. if a slave receives other than a local address, no acknowledge signal is output. the acknowledge signal output method during data reception depends on the wa it timing setting, as follows. ? 8-clock wait: acknowledge signal is output when the va lue of acke0 becomes 1 bef ore wait cancellation is performed. ? 9-clock wait: acknowledge signal is automatically output in synchronizati on with the falling edge of the 8th clock of scl0 by setting acke0 to 1 beforehand.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 248 15.4.5 stop condition when the sda0 pin changes from low level to high level wh ile the scl0 pin is at high level, a stop condition is generated. a stop condition is the signal that is out put when serial transfer from the master to a slave is completed. slaves incorporate hardware for the detection of stop conditions. figure 15-12. stop condition h scl0 sda0 a stop condition is generated when bit 0 ( spt0) of smb control register 0 (s mbc0) is set to 1. if, when a stop condition is detected, bit 0 (spd0) of smb status register 0 (smbs0) and bi t 4 (spie0) of smbc0 are set to 1, intsmb0 is generated.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 249 15.4.6 wait signal (wait) a wait signal (wait) indicates to the ot her party that the master or slave is getting ready (wait status) to send or receive data. a wait status is notified by making t he scl0 pin low level. when the wait st atus of both the ma ster and slave is canceled, the next transmission starts. figure 15-13. wait signal (1/2) (1) when master = 9-clo ck wait, slave = 8-clock wait (master: send, slave: receive, acke0 = 1) smb0 scl0 6789 1 smb0 data write (wait canceled) 23 6 d2 d1 d0 ack d7 d6 d5 78 9 123 wait after 9th clock output return master to hi-z but slave waits (low level) smb0 scl0 scl0 sda0 acke0 h smb0 ffh, or wrel0 1 wait after 8th clock output master slave transmission line
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 250 figure 15-13. wait signal (2/2) (2) master, slave = 9-clock wait (master: send, slave: receive, acke0 = 1) smb0 scl0 6789 1 smb0 data write (wait canceled) 23 6 d2 d1 d0 ack output according to previously set acke0 d7 d6 d5 789 123 both master and slave wait after 9th clock output smb0 scl0 scl0 sda0 acke0 h smb0 ffh, or wrel0 1 master slave transmission line remark acke0: smb control register 0 (smbc0) bit 2 wrel0: smb control register 0 (smbc0) bit 5 waits are automatically generated by setting bit 3 (w tim0) of smb control register 0 (smbc0). normally, the receive side cancels the wa it status when smbc0 bit 5 (wrel0) = 1 or smb shift register (smb0) ffh write, and the transmit side cancels the wa it status when data is written to smb0. in the case of the master, wait status can be canceled by the following methods. ? setting smbc0 bit 1 (stt0) to 1 ? setting smbc0 bit 0 (spt0) to 1
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 251 15.4.7 smb0 interrupt (intsmb0) the following section shows the values of smb status register 0 (smbs0 ) using the intsmb0 interrupt request generation timing and intsmb0 interrupt timing. caution the case when awtim0 = 0 is described here. (1) master operation (a) start ? address ? data ? data ? stop (normal send/receive) <1> when wtim0 = 0 <2> when wtim0 = 1 1 2 3 5 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 4 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 1000 000b 3: smbs0 = 1000 000b 4: smbs0 = 1000 00b 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1 2 3 4 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 1000 100b 3: smbs0 = 1000 00b 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 252 (b) start ? address ? data ? start ? address ? data ? stop (restart) <1> when wtim0 = 0 <2> when wtim0 = 1 1 2 3 4 6 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 5 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 1000 000b 3: smbs0 = 1000 110b 4: smbs0 = 1000 000b 5: smbs0 = 1000 00b 6: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 1 2 3 4 5 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 1000 00b 3: smbs0 = 1000 110b 4: smbs0 = 1000 00b 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 253 (c) start ? code ? data ? data ? stop (extension code transmission) <1> when wtim0 = 0 <2> when wtim0 = 1 1 2 3 5 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 4 0 0: smbs0 = 10001010b 1: smbs0 = 1010 10b 2: smbs0 = 1010 000b 3: smbs0 = 1010 000b 4: smbs0 = 1010 00b 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 1 2 3 4 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 0 0: smbs0 = 10001010b 1: smbs0 = 0010 110b 2: smbs0 = 0010 100b 3: smbs0 = 0010 00b 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 254 (2) slave operation (during slave addr ess data reception (matching sva0)) (a) start ? address ? data ? data ? stop <1> when wtim0 = 0 <2> when wtim0 = 1 1 2 3 4 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 0 0: smbs0 = 00000010b 1: smbs0 = 0001 110b 2: smbs0 = 0001 000b 3: smbs0 = 0001 000b 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 1 2 3 4 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 0 0: smbs0 = 00000010b 1: smbs0 = 0001 110b 2: smbs0 = 0001 100b 3: smbs0 = 0001 00b 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 255 (b) start ? address ? data ? start ? address ? data ? stop <1> when wtim0 = 0 (matching sva0 after restart) <2> when wtim0 = 1 (matching sva0 after restart) 1 2 3 4 5 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 0 0: smbs0 = 00000010b 1: smbs0 = 0001 110b 2: smbs0 = 0001 000b 3: smbs0 = 0001 110b 4: smbs0 = 0001 000b 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 1 2 3 4 5 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 0 0: smbs0 = 00000010b 1: smbs0 = 0001 110b 2: smbs0 = 0001 00b 3: smbs0 = 0001 110b 4: smbs0 = 0001 00b 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 256 (c) start ? address ? data ? start ? code ? data ? stop <1> when wtim0 = 0 (extension code reception after restart) <2> when wtim0 = 1 (extension code reception after restart) 1 2 3 4 5 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 0 0: smbs0 = 00000010b 1: smbs0 = 0001 110b 2: smbs0 = 0001 000b 3: smbs0 = 0010 010b 4: smbs0 = 0010 000b 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 1 2 3 4 6 5 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 0 0: smbs0 = 00000010b 1: smbs0 = 0001 110b 2: smbs0 = 0001 00b 3: smbs0 = 0010 010b 4: smbs0 = 00100110b 5: smbs0 = 0010 00b 6: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 257 (d) start ? address ? data ? start ? address ? data ? stop <1> when wtim0 = 0 (unmatching addr ess (except extension code) after restart) <2> when wtim0 = 1 (unmatching addr ess (except extension code) after restart) 1 2 3 4 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 0 0: smbs0 = 00000010b 1: smbs0 = 0001 110b 2: smbs0 = 0001 000b 3: smbs0 = 0000 10b 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 1 2 3 4 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 0 0: smbs0 = 00000010b 1: smbs0 = 0001 110b 2: smbs0 = 0001 00b 3: smbs0 = 0000 10b 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 258 (3) slave operation (during extension code reception) (a) start ? code ? data ? data ? stop <1> when wtim0 = 0 <2> when wtim0 = 1 2 3 4 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1 0 0: smbs0 = 00000010b 1: smbs0 = 0010 010b 2: smbs0 = 0010 000b 3: smbs0 = 0010 000b 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 5 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1 2 3 4 0 0: smbs0 = 00000010b 1: smbs0 = 0010 010b 2: smbs0 = 0010 110b 3: smbs0 = 0010 00b 4: smbs0 = 0010 00b 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 259 (b) start ? code ? data ? start ? address ? data ? stop <1> when wtim0 = 0 (matching sva0 after restart) <2> when wtim0 = 1 (matching sva0 after restart) 2 4 5 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 3 1 0 0: smbs0 = 00000010b 1: smbs0 = 0010 010b 2: smbs0 = 0010 000b 3: smbs0 = 0001 110b 4: smbs0 = 0001 000b 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 3 4 5 6 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 2 1 0 0: smbs0 = 00000010b 1: smbs0 = 0010 010b 2: smbs0 = 0010 110b 3: smbs0 = 0010 00b 4: smbs0 = 0001 110b 5: smbs0 = 0001 00b 6: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 260 (c) start ? code ? data ? start ? code ? data ? stop <1> when wtim0 = 0 (extension code reception after restart) <2> when wtim0 = 1 (extension code reception after restart) 2 4 5 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 3 1 0 0: smbs0 = 00000010b 1: smbs0 = 0010 010b 2: smbs0 = 0010 000b 3: smbs0 = 0010 010b 4: smbs0 = 0010 000b 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 3 5 6 7 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 4 2 1 0 0: smbs0 = 00000010b 1: smbs0 = 0010 010b 2: smbs0 = 0010 110b 3: smbs0 = 0010 00b 4: smbs0 = 0010 010b 5: smbs0 = 0010 110b 6: smbs0 = 0010 00b 7: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 261 (d) start ? code ? data ? start ? address ? data ? stop <1> when wtim0 = 0 (unmatching a ddress (except extension code) after restart) <2> when wtim0 = 1 (unmatching addr ess (except extension code) after restart) (4) non-participation in communication (a) start ? code ? data ? data ? stop 1 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 0 0: smbs0 = 00000010b 1: smbs0 = 00000001b remark generate only when stie0 = 1 generate only when spie0 = 1 2 4 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 3 1 0 0: smbs0 = 00000010b 1: smbs0 = 0010 010b 2: smbs0 = 0010 000b 3: smbs0 = 00000 10b 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 3 4 5 rw ak ad6 to ad0 ak d7 to d0 st rw ak ad6 to ad0 sp ak d7 to d0 st 2 1 0 0: smbs0 = 00000010b 1: smbs0 = 0010 010b 2: smbs0 = 0010 110b 3: smbs0 = 0010 00b 4: smbs0 = 00000 10b 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 262 (5) arbitration defeat operation (ope ration as slave after arbitration defeat) (a) in case of arbitration defeat during slave address data transmission <1> when wtim0 = 0 <2> when wtim0 = 1 4 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1 2 3 0 0: smbs0 = 10001010b 1: smbs0 = 0101 110b (example: read ald0 during interrupt processing) 2: smbs0 = 0001 000b 3: smbs0 = 0001 000b 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 4 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 1 2 3 0 0: smbs0 = 10001010b 1: smbs0 = 0101 110b (example: read ald0 during interrupt processing) 2: smbs0 = 0001 100b 3: smbs0 = 0001 00b 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 263 (b) in case of arbitration defeat during extension code transmission <1> when wtim0 = 0 <2> when wtim0 = 1 1 2 3 4 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 0 0: smbs0 = 10001010b 1: smbs0 = 0110 010b (example: read ald0 during interrupt processing) 2: smbs0 = 0010 000b 3: smbs0 = 0010 000b 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 1 2 3 5 4 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 0 0: smbs0 = 10001010b 1: smbs0 = 0110 010b (example: read ald0 during interrupt processing) 2: smbs0 = 0010 110b 3: smbs0 = 0010 100b 4: smbs0 = 0010 00b 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 264 (6) arbitration defeat operation (non-pa rticipation after arbitration defeat) (a) in case of arbitration defeat during slave address data transmission (b) in case of arbitration defeat during extension code transmission 1 2 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 0 0: smbs0 = 10001010b 1: smbs0 = 01000110b (example: read ald0 during interrupt processing) 2: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 1 2 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 0 0: smbs0 = 10001010b 1: smbs0 = 0110 010b (example: read ald0 during interrupt processing, lrel0 = 1 set by software) 2: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 265 (c) in case of arbitration de feat during data transmission <1> when wtim0 = 0 <2> when wtim0 = 1 1 2 3 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 0 0: smbs0 = 10001010b 1: smbs0 = 10001110b 2: smbs0 = 01000000b (example: read ald0 during interrupt processing) 3: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 1 2 3 rw ak ad6 to ad0 ak sp d7 to d0 ak d7 to d0 st 0 0: smbs0 = 10001010b 1: smbs0 = 10001110b 2: smbs0 = 01000100b (example: read ald0 during interrupt processing) 3: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 266 (d) in case of defeat by restar t condition during data transmission <1> other than extension code (example: matching sva0) <2> extension code 1 2 3 rw ak ad6 to ad0 d7 to dn st rw ak ad6 to ad0 sp ak d7 to d0 st 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 01000110b (example: read ald0 during interrupt processing) 3: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care dn = d6 to d0 1 2 3 rw ak ad6 to ad0 d7 to dn st rw ak ad6 to ad0 sp ak d7 to d0 st 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 0110 010b (example: read ald0 during interrupt processing, smbc0: lrel0 = 1 set by software) 3: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care dn = d6 to d0
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 267 (e) in case of defeat by stop condition during data transmission 1 2 rw ak ad6 to ad0 d7 to dn st sp 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 01000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care dn = d6 to d0
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 268 (f) in case of arbitration defeat by data low l evel while attempting to ge nerate restart condition <1> when wtim0 = 0 <2> when wtim0 = 1 1 2 4 stt0 = 1 5 rw ak ad6 to ad0 d7 to d0 st ak sp ak d7 to d0 ak d7 to d0 3 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 1000 000b 3: smbs0 = 1000 00b 4: smbs0 = 10000000b (example: read ald0 during interrupt processing) 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 1 2 3 stt0 = 1 4 rw ak ad6 to ad0 d7 to d0 st ak sp ak d7 to d0 ak d7 to d0 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 1000 00b 3: smbs0 = 01000100b (example: read ald0 during interrupt processing) 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 269 (g) in case of arbitration defeat by stop conditi on while attempting to ge nerate restart condition <1> when wtim0 = 0 <2> when wtim0 = 1 stt0 = 1 1 2 4 rw ak ad6 to ad0 d7 to d0 st sp ak 3 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 1000 000b 3: smbs0 = 1000 00b 4: smbs0 = 01000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care stt0 = 1 1 2 3 rw ak ad6 to ad0 d7 to d0 st sp ak 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 1000 00b 3: smbs0 = 01000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 270 (h) in case of arbitration defeat by data low level while attempting to generate a stop condition <1> when wtim0 = 0 <2> when wtim0 = 1 1 2 4 spt0 = 1 5 rw ak ad6 to ad0 d7 to d0 st ak sp ak d7 to d0 ak d7 to d0 3 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 1000 000b 3: smbs0 = 1000 00b 4: smbs0 = 01000000b (example: read ald0 during interrupt processing) 5: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care 1 2 3 spt0 = 1 4 rw ak ad6 to ad0 d7 to d0 st ak sp ak d7 to d0 ak d7 to d0 0 0: smbs0 = 10001010b 1: smbs0 = 1000 110b 2: smbs0 = 1000 00b 3: smbs0 = 01000000b (example: read ald0 during interrupt processing) 4: smbs0 = 00000001b remark generate only when stie0 = 1 always generate generate only when spie0 = 1 don't care
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 271 (7) slave operation (after st op mode is released) (a) start ? address ? data ? data ? stop <1> when wtim0 = 0 rw ak ad6-ad0 ak sp d7-d0 ak d7-d0 st oscillation stabilization time 1: smbs0 = 0001x010b 2: smbs0 = 0001x000b 3: smbs0 = 0001x000b remark always generate don't care 1 2 3 <2> when wtim0 = 1 rw ak ad6-ad0 ak sp d7-d0 ak d7-d0 st oscillation stabilization time 1: smbs0 = 0001x010b 2: smbs0 = 0001x100b 3: smbs0 = 0001xx00b remark always generate don't care 1 2 3 cautions 1. be sure to set stie0 = spi e0 = 0 when releasing stop mode upon address match. in this case however, the time out count operation or stop operation cannot be controlled, because an interr upt is not generated even if a start or stop condition is output by another device duri ng stop mode operation. 2. when releasing stop mode, th e timeout count operation cannot be performed in the period from the star t condition to oscillation stabilization, because an interrupt is not generated when a start condition is generated.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 272 15.4.8 interrupt request (intsmb0) generation timing a nd wait control intsmb0 generation and wait control c an be performed at the timing indicat ed in table 15-3 by setting bit 3 (wtim0) of smb control register 0 (smbc0). table 15-3. intsmb0 genera tion timing and wait control during slave operation during master operation wtim0 awtim0 address data receive data transmit a ddress data receive data transmit 0 9 notes 1, 2 0 1 8 notes 1, 2 8 note 2 8 note 2 9 8 8 0 9 notes 1, 2 1 1 8 notes 1, 2 9 note 2 9 note 2 9 9 9 notes 1. intsmb0 and wait signals are generated by a slave at the falling edge of the 8th or 9th clock according to the setting of awtim0 only when matching with the address of the smb slave address register (smbsva0) occurs. moreover, at this time, an ack signal is output regar dless of the setting of bit 2 (acke0) of smbc0. a slave that receives an extensi on code generates intsmb0 at the falling edge of the 8th clock. 2. if the address received does not match the address set in smb slave address register 0 (smbsva0), the slave does not generate intsmb0 and wait signals. remark figures listed in table 15-3 above indicate the number of serial cl ocks. interrupt requests and wait control are synchronized with the falling edge of the serial clock. (1) during address transmission/reception ? during slave operation: interrupt and wait timing is set based on the conditions described in notes 1 and 2 above regardless of the wtim0 bit setting. ? during master operation: interr upt and wait signals are generated at the falling edge of the 9th clock regardless of the wtim0 bit setting. (2) during data reception ? during master/slave operation: interrupt and wait timing is set by the wtim0 bit. (3) during data transmission ? during master/slave operation: interrupt and wait timing is set by the wtim0 bit. (4) wait cancellation method waits can be canceled by one of the following four methods. ? setting smb control register 0 (smbc0) bit 5 (wrel0) to 1 ? performing smb shift register 0 (smb0) write operation ? setting a start condition (by setting smbc0 bit 1 (stt0) to 1) ? setting a stop condition (by setting smbc0 bit 0 (spt0) to 1) when 8-clock wait is selected (wtim0 = 0), the ack output level must be determi ned before the wa it status is released.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 273 (5) stop condition detection an intsmb0 signal is output when a stop c ondition is detected (only when spie0 = 1). (6) start condition detection an intsmb0 signal is output when a start c ondition is detected (only when stie0 = 1).
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 274 15.4.9 matching address detection method in smb mode, a particular slave device can be select ed by sending that slave address to the master. the detection of matching addresses is performed automatically by hardware. if a local address has been set in smb slave address register 0 (smbsva0), and the slave address sent from the master matches the address set in smbsva0, or if the extension code is receiv ed, an intsmb0 interrupt request is generated. 15.4.10 error detection in smb mode, because the status of t he serial data bus (sda0) during transmission is also input to smb shift register 0 (smb0), transmission errors can be detected by comparing the sm b0 data before transmission start and at transmission end. if the two data do not match, a tr ansmission error is considered to have occurred. 15.4.11 extension code (1) an extension code is considered to have been receiv ed when the high four bits of the receive address are 0000 or 1111, and in this case the extension code re ceive flag (exc0) is set and an interrupt request (intsmb0) is generated at the fa lling edge of the 8th clock. the local address stored in smb slave addre ss register 0 (smbsva0) is not affected. (2) when 111110 is set to smbsva0 and 111110 0 is transferred from the master during transfer of a 10-bit address, the following occurs. however, intsmb0 is generated at the falling edge of the 8th clock. ? matching high 4 bits: exc0 = 1 note ? matching 7-bit data: coi0 = 1 note note exc0: smb status register 0 (smbs0) bit 5 coi0: smb status register 0 (smbs0) bit 4 (3) because the processing after an interrupt request is generated differs depending on t he data that follows the extension code, it is performed by so ftware. for instance, if operation as a slave is not desired following the reception of an extension code, set lrel0 to 1, in which case the fo llowing communication standby status is entered. table 15-4. extensi on code bit definition slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 cbus address 0000 010 address reserved for different bus format 1111 0 10-bit slave address specification addresses reserved for system management bus are described below. slave address description 0001 000 smb host 0001 100 response address for smb alert 1010 001 default address of smb device 1001 0 free address
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 275 15.4.12 arbitration if several masters output a start c ondition simultaneously (when stt0 is set to 1 before std0 is set to 1 note ), master communication is performed while adjusting the clo ck until data differs. this operation is referred to as arbitration. a master defeated in arbitration sets t he arbitration defeat flag (ald0) of smb status register 0 (smbs0), and sets the scl0 and sda0 lines to hi-z to release the bus. arbitration defeat is detect ed by software when ald0 = 1 at the next interrupt request generation timing (8th or 9th clock, stop conditi on detection, etc.). for the interrupt generation timing, see 15.4.7 smb0 interrupt (intsmb0) . note std0: smb status register 0 (smbs0) bit 1 stt0: smb control register 0 (smbc0) bit 1 figure 15-14. arbitration timing examples scl0 sda0 scl0 sda0 scl0 sda0 hi-z hi-z master 1 arbitration defeat master 1 master 2 transmission line
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 276 table 15-5. status at arbitration and interrupt request generation timing status at arbitration inte rrupt request generation timing address transmission in progress read/write information following address transmission extension code transmission in progress read/write information followi ng extension code transmission data transmission in progress ack transmission in progress following data transmission data transmission in progress, restart condition detection falling edge of 8th or 9th clock following byte transmission note 1 data transmission in progress, stop condition det ection during stop condition output (spie0 = 1) note 2 attempt to output restart condition was made, but data was low level falling edge of 8th or 9th clock following byte transfer note 1 attempt to output restart condition was made, but stop condition was detected during stop condition output (spie0 = 1) note 2 attempt to output stop condition was made, but data was low level attempt to output restart condition was made, but scl0 was low level falling edge of 8th or 9th clock following byte transfer note 1 notes 1. if wtim0 (bit 3 of smb control register 0 (smb c0) = 1, an interrupt reques t is generated at the falling edge of the 9th clock. during reception of an extension code slave address when wtim0 = 0, an interrupt request is generated at t he falling edge of the 8th clock. 2. if there is a possibility of arbitration o ccurring, set spie0 to 1 for master operation. remark spie0: smb control register 0 (smbc0) bit 4 15.4.13 wakeup function the smb0 slave function generates an interrupt request (intsmb0) when a local address and extension code are received. this interrupt enables re lease of stop mode and halt mode. when the address does not match, no unnecessary interr upt request is generated, a llowing greater processing efficiency. when a start condition is detected, t he wakeup standby status is entered. because even a master (when a start condition is output) may become a slave if defeated in arbitration, the wakeup standby status is entered while address transmission is performed. however, when a stop condition is det ected, interrupt request enable/dis able is determined by setting bit 4 (spie0) of smb control register 0 (smb c0) regardless of the wakeup function.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 277 15.4.14 communication reservation if, during non-participation on the bus, t he next master communication is desir ed, a start condition can be made to be sent at bus release by performing communication reservat ion. non-participation on t he bus includes the following two statuses. ? when unit neither master nor slave during bus arbitration ? when extension code is received and unit does not operate as slave (releas ed bus with smb control register 0 (smbc0) bit 6 (lrel0) = 1, without returning ack). when bit 1 (stt0) of smbc0 is set during non-parti cipation on the bus, a st art condition is generated automatically after the bus is releas ed (following detection of stop condition) , and the wait status is entered. when bus release is detected (detecti on of stop condition), address transmissi on as master is started through a smb shift register 0 (smb0) write operation. at this time, set smbc0 bit 4 (spie0). when stt0 is set, whether operation as a start condition or operation as communicati on reservation is selected depends on the bus status. ? if bus is rel eased .................................... start condition generation ? if bus is not released (standby st atus).... communication reservation the method to detect which operation is selected by stt0 is to set stt0, and reconfirm the stt0 bit after the wait time elapses. secure the wait time by software as shown in table 15-6. the wait time is set by bit 3 (smc0) of smb clock selection register 0 (smbcl0). table 15-6. wait time smc0 wait time 0 46 clocks 1 16 clocks
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 278 the communication reservation timing is shown in figure 15-15. figure 15-15. communication reservation timing program processing hardware processing scl0 1 2 3 4 5 6 1 2 3 4 5 6 789 sda0 commu- nication reservation stt0 = 1 smb0 write std0 setting spd0, intsmb0 setting output of master that occupied bus smb0: smb shift register 0 stt0: smb control register 0 (smbc0) bit 1 std0: smb status register 0 (smbs0) bit 1 spd0: smb status register 0 (smbs0) bit 0 communication reservations are received at the following ti ming. after bit 1 (std0) of smb status register 0 (smbs0) becomes 1, communication reservation is done by setting bit 1 (stt0) of smb control register 0 (smbc0) to ?1? before detection of a stop condition. figure 15-16. communication reservation reception timing scl0 sda0 std0 spd0 standby state
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 279 figure 15-17 shows the communica tion reservation procedure. figure 15-17. communication reservation procedure di set1 stt0 definition of communication reservation release of communication reservation mov smb0, # h ei wait stt0 = 1? ; set stt0 flag (communication reservation) ; define that communication reservation is in progress (define user flag in any ram, and set) ; clear user flag ; smb0 write operation ; secure wait time by software (see table 15-6 ) ; check stt0 flag ye s (communication reservation) note no (generate start condition) note during the communication reservati on operation, execute writ ing to smb shift register 0 (smb0) using a stop condition interrupt. 15.4.15 additional cautions if, after reset, master communication is attempted from a status where no st op condition is detected (bus is not released), a stop condition must be generated and the bus released before per forming master communication. in the case of multiple masters, master communication cannot be performed while the bus is not released (stop condition not detected). a stop condition is generated in the following sequence. <1> setting of smb clock selection register 0 (smbcl0) <2> setting of smb control register 0 (smbc0) bit 7 (smbe0) <3> setting of smbc0 bit 0 (spt0)
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 280 15.4.16 communication operation (1) master operation the master operation sequenc e is illustrated below. figure 15-18. master operation sequence smbcl0 h selection of transmission clock smb0 write start of transmission smbc0 h smbe0 = spie0 = wtim0 = 1 stt0 = 1 intsmb0 = 1? intsmb0 = 1? smb0 write start of transmission generation of stop condition (there is no slave with matching address) intsmb0 = 1? ackd0 = 1? ackd0 = 1? trc0 = 1? start ye s no ye s no ye s no ye s no ye s no yes (send) no (receive) no ye s no ; end of address transmission ; detection of stop condition data processing smbc0 h wtim0 = 0 acke0 = 1 wrel0 = 1 start of reception intsmb0 = 1? transmission end? data processing acke0 = 0 generation of restart condition or stop condition
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 281 (2) slave operation the slave operation sequenc e is illustrated below. figure 15-19. slave operation sequence smbc0 h smbe0 = 1 intsmb0 = 1? exc0 = 1? intsmb0 = 1? ackd0 = 1? coi0 = 1? trc0 = 1? start ye s no no ye s ye s no ye s no ye s no ye s no no ye s no data processing smbc0 h wtim0 = 0 acke0 = 1 wrel0 = 1 start of transmission intsmb0 = 1? transmission end? data processing acke0 = 0 detection of start condition or stop condition participate in communication? ye s no wtim0 = 1 smb0 write start of transmission lrel0 = 1
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 282 15.5 timing charts in smb mode, a master can select for communicati on a slave device from among many such devices by outputting an address to the serial bus. after the slave address, the master s ends the trc0 bit (bit 3 of smb stat us register 0 (smbs0)) indicating the data transmission direction and starts the serial communication with the slave. the timing charts for data transmission are shown in figures 15-20 and 15-21. the shift operation of smb shift register 0 (smb0) is performed in synchronizati on with the falling edge of the serial clock (scl0), send data is transmitted to the so0 latch and output msb first from the sda0 pin. data input to the sda0 pin at t he rising edge of scl0 is read by smb0.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 283 figure 15-20. master slave communication example (when 9-clock wait is selected for both master and slave) (1/3) (1) start condition ? address smb0 address smb0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intsmb0 trc0 scl0 sda0 smb0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intiic trc0 h h l h h h l l l l receive send 1 a6 start condition a5 a4 a3 a2 a1 a0 w d7 note 4 smb0 ffh note 4 (when exc0 = 1) d6 d5 d4 ack 23456789 1234 smb0 data master device processing slave device processing transmission line note 1 note 3 note 2 note 1 note 1 notes 1. an interrupt signal is output only when stie0 = 1. 2. an interrupt signal is output only when exc0 = 1. 3. an interrupt signal is output only when spie0 = 1. 4. perform slave wait cancellation by either changing smb0 ffh, or setting wrel0.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 284 figure 15-20. master slave communication example (when 9-clock wait is selected for both master and slave) (2/3) (2) data note perform slave wait cancellation by either changing smb0 ffh, or setting wrel0. smb0 data smb0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intsmb0 trc0 smb0 ackd0 scl0 sda0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intsmb0 trc0 h h h l l l l l h h l l l l l l h send receive note note smb0 data master device processing slave device processing transmission line 1 9 d0 8 d7 d6 d5 d4 d3 d2 d1 d0 d7 smb0 ffh note smb0 ffh note d6 d5 23456789 123
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 285 figure 15-20. master slave communication example (when 9-clock wait is selected for both master and slave) (3/3) (3) stop condition smb0 data smb0 ffh note 1 note 1 note 1 smb0 ffh note 1 smb0 address smb0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intsmb0 trc0 scl0 sda0 smb0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intsmb0 trc0 h h h h h l l l l receive send 12 1 a6 stop condition start condition d0 d1 d2 d3 d4 d5 d6 d7 a5 2 3456789 l master device processing slave device processing transmission line note 2 note 3 note 2 note 3 notes 1. perform slave wait cancellation by either changing smb0 ffh, or setting wrel0. 2. an interrupt signal is output only when spie0 = 1. 3. an interrupt signal is output only when stie0 = 1.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 286 figure 15-21. slave master communication example (when 9-clock wait is selected for both master and slave) (1/3) (1) start condition ? address smb0 address smb0 ffh note 2 smb0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intsmb0 trc0 scl0 sda0 smb0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intsmb0 trc0 l h h l l l l note 2 h h 1 a6 a5 a4 a3 a2 d6 d7 d5 d4 d3 d2 a1 a0 r smb0 data start condition 23456 123456 789 master device processing slave device processing transmission line note 1 note 1 notes 1. only when stie0 = 1. 2. perform slave wait cancellation by either changing smb0 ffh, or setting wrel0.
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 287 figure 15-21. slave master communication example (when 9-clock wait is selected for both master and slave) (2/3) (2) data note perform slave wait cancellation by either changing smb0 ffh, or setting wrel0. smb0 ffh note smb0 ffh note smb0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intsmb0 trc0 scl0 sda0 smb0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intsmb0 trc0 l l h h h l l l l l h h l l l l h send note receive note 1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ack d7 d6 d5 ack smb0 data smb0 data 23 1 2 3 456789 89 master device processing slave device processing transmission line
chapter 15 smb0 ( pd789167y and 789177y subseries) user?s manual u14186ej5v0ud 288 figure 15-21. slave master communication example (when 9-clock wait is selected for both master and slave) (3/3) (3) stop condition smb0 address smb0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intsmb0 trc0 scl0 sda0 smb0 ackd0 std0 spd0 wtim0 acke0 msts0 stt0 spt0 wrel0 intsmb0 trc0 h h h h l l l note 1 1 d7 a6 a5 d6 d5 d4 d3 d2 d1 d0 n-ack smb0 ffh note 1 smbc0 data stop condition start condition 2 12 3456789 master device processing slave device processing transmission line note 2 note 3 note 2 note 3 notes 1. perform slave wait cancellation by either changing smb0 ffh, or setting wrel0. 2. an interrupt signal is output only when spie0 = 1. 3. an interrupt signal is output only when stie0 = 1.
user?s manual u14186ej5v0ud 289 chapter 16 multiplier 16.1 multiplier function the multiplier has the following function. ? calculation of 8 bits 8 bits = 16 bits 16.2 multiplier configuration (1) 16-bit multiplication result storage register 0 (mul0) this register stores the 16-bi t result of multiplication. this register holds the result of mult iplication after 16 cpu clocks have elapsed. mul0 is set with a 16-bit memory manipulation instruction. reset input makes this register undefined. caution mul0 is designed to be manipulated with a 16-bit memory ma nipulation instruction. it can also be manipulated with 8-bit memory manipul ation instructions, however. when an 8-bit memory manipulation instruction is used to manipulate mul0, it must be accessed using direct addressing. (2) multiplication data regist ers a and b (mra0 and mrb0) these are 8-bit multiplicat ion data storage registers. the multiplier multiplies the values of mra0 and mrb0. mra0 and mrb0 are set with a 1-bit or 8- bit memory manipulation instruction. reset input makes thes e registers undefined. figure 16-1 shows a block diagram of the multiplier.
chapter 16 multiplier user?s manual u14186ej5v0ud 290 figure 16-1. block diagram of multiplier internal bus selector counter value 3 cpu clock start clear counter output 16-bit adder 16-bit multiplication result storage register 0 (master) (mul0) 16-bit multiplication result storage register 0 (slave) multiplication data register a (mra0) multiplication data register b (mrb0) internal bus 3-bit counter mulst0 reset multiplier control register 0 (mulc0)
chapter 16 multiplier user?s manual u14186ej5v0ud 291 16.3 multiplier control register the multiplier is controlled by the following register. ? multiplier control register 0 (mulc0) mulc0 indicates the operating stat us of the multiplier, as well as controls the multiplier. mulc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input clears this register to 00h. figure 16-2. format of multiplier control register 0 mulst0 0 1 multiplier operation start control bit stops operation after resetting counter to 0. enables operation operation stops operation in progress operating status of multiplier 00 0 0 0 0 0 mulst0 mulc0 7 654 32 10 symbol address after reset r/w ffd2h 00h r/w caution bits 1 to 7 must all be set to 0.
chapter 16 multiplier user?s manual u14186ej5v0ud 292 16.4 multiplier operation the multiplier of the pd789167, 789177, 789167y, and 789177y subseries can execute calculation of 8 bits 8 bits = 16 bits. figure 16-3 shows the operation timing of the multiplier where mra0 is set to aah and mrb0 is set to d3h. <1> counting is started by setting mulst0. <2> the data generated by the selector is added to the data of mul0 at each cpu clock, and the counter value is incremented by one. <3> if mulst0 is cleared when the counter value is 111b, the operation is stopped. at this time, mul0 holds the data. <4> while mulst0 is low, the counter and slave are cleared. figure 16-3. multiplier operation timing (example of aah d3h) aa d3 000b 00aa 0000 001b 010b 011b 100b 101b 110b 111b 000b 0154 0000 0000 0aa0 0000 2a80 5500 00aa 00aa 01fe 01fe 01fe 0c9e 0c9e 371e 8c1e 00aa 01fe 01fe 01fe 0c9e 0c9e 371e 0000 cpu clock mra0 mrb0 mulst0 counter selector output mul0 (master) (slave)
user?s manual u14186ej5v0ud 293 chapter 17 interrupt functions 17.1 interrupt function types the following two types of in terrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. a standby release signal is generated. the non-maskable interrupt has one inte rrupt source the watchdog timer. (2) maskable interrupt these interrupts undergo mask control. if two or more interrupts are si multaneously generated, each interrupt has a predetermined priori ty as shown in table 17-1. a standby release signal is generated. for the pd789167 and 789177 subseries, maskable interrupts have four external interrupt sources and ten internal interrupts sources. for the pd789167y and 789177y subseries, ma skable interrupts have four external interrupt sources of and 12 internal interrupt sources. 17.2 interrupt sources and configuration there are a total of 15 non-maskable and maskable interrupt sources for the pd789167 and 789177 subseries, and a total of 17 non-maskable and maskable interrupt sources for the pd789167y and 789177y subseries (see table 17-1 ).
chapter 17 interrupt functions user?s manual u14186ej5v0ud 294 table 17-1. interrupt sources interrupt source interrupt type priority note 1 name trigger internal/external vector table address basic configuration type note 2 non-maskable interrupt ? intwdt watchdog timer overflow (when watchdog timer mode 1 is selected) (a) 0 intwdt watchdog timer overflow (when interval timer mode is selected) internal 0004h (b) 1 intp0 0006h 2 intp1 0008h 3 intp2 000ah 4 intp3 pin input edge detection external 000ch (c) intsr20 end of uart reception on serial interface 20 5 intcsi20 end of three-wire sio transfer reception on serial interface 20 000eh 6 intst20 end of uart transmission on serial interface 20 0010h 7 intwt watch timer interrupt 0012h 8 intwti interval timer interrupt 0014h 9 inttm80 generation of match signal for 8-bit timer/event counter 80 0016h 10 inttm81 generation of match signal for 8-bit timer/event counter 81 0018h 11 inttm82 generation of match signal for 8-bit timer 82 001ah 12 inttm90 generation of match signal for 16-bit timer 90 001ch 13 intsmb0 note 3 smb interrupt 001eh 14 note 3 intsmbov0 smb timeout interrupt 0020h maskable interrupt 15 intad0 a/d conversion completion signal internal 0022h (b) notes 1. the priority regulates which ma skable interrupt is higher when two or more maskable interrupts are generated simultaneously. zero signifies t he highest priority, and 15 is the lowest. 2. basic configuration types (a), (b), and (c) correspond to (a), (b), and (c) in figure 17-1, respectively. 3. for the pd789167y and 789177y subseries only
chapter 17 interrupt functions user?s manual u14186ej5v0ud 295 figure 17-1. basic configuration of interrupt function (a) internal non-maskable interrupt internal bus interrupt request vector table address generator standby release signal (b) internal maskable interrupt mk if ie internal bus interrupt request vector table address generator standby release signal (c) external maskable interrupt mk if ie internal bus external interrupt mode register (intm0, intm1) interrupt request edge detector vector table address generator standby release signal if: interrupt request flag ie: interrupt enable flag mk: interrupt mask flag
chapter 17 interrupt functions user?s manual u14186ej5v0ud 296 17.3 interrupt function control registers the interrupt functions are contro lled by the following registers. interrupt request flag registers 0 and 1 (if0 and if1) interrupt mask flag registers 0 and 1 (mk0 and mk1) external interrupt mode regi sters 0 and 1 (intm0 and intm1) program status word (psw) table 17-2 lists interrupt requests, the correspondi ng interrupt request flags, and interrupt mask flags. table 17-2. interrupt request signals and corresponding flags interrupt request signal interrupt request flag interrupt mask flag intwdt intp0 intp1 intp2 intp3 intsr20/intcsi20 intst20 intwt intwti inttm80 inttm81 inttm82 inttm90 intsmb0 note intsmbov0 note intad0 tmif4 pif0 pif1 pif2 pif3 srif20 stif20 wtif wtiif tmif80 tmif81 tmif82 tmif90 smbif0 note smbovif0 note adif0 tmmk4 pmk0 pmk1 pmk2 pmk3 srmk20 stmk20 wtmk wtimk tmmk80 tmmk81 tmmk82 tmmk90 smbmk0 note smbovmk0 note admk0 note for the pd789167y and 789177y subseries only
chapter 17 interrupt functions user?s manual u14186ej5v0ud 297 (1) interrupt request flag registers (if0 and if1) an interrupt request flag is set to 1 when the corres ponding interrupt request is i ssued, or when the related instruction is executed. it is cleared to 0 when t he interrupt request is acknowledged, when a reset signal is input, or when a related instruction is executed. if0 and if1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input clears if0 and if1 to 00h. figure 17-2. format of interrupt request flag register adif0 smbovif0 smbif0tmif90 tmif82 tmif81 tmif80 wtiif if1 ffe1h 00h r/w if 0 1 interrupt request flag no interrupt request signal has been issued. an interrupt request signal has been issued; an interrupt request has been made. <6> <7> <5> <4> <3> <2> <1> <0> wtif stif20srif20 pif3 pif2 pif1 pif0 tmif4 if0 symbol address after reset r/w ffe0h 00h r/w <6> <7> <5> <4> <3> <2> <1> <0> note note note this flag is provided for the pd789167y and 789177y subseries only. for the pd789167 and 789177 subseries, the flag must be set to 0. cautions 1. the tmif4 flag can be read- and write-accessed only when the watchdog timer is being used as an interval ti mer. it must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. 2. when port 3 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. to use port 3 in output mode, therefore, the interrupt mask flag must be set to 1 in advance. 3. when an interrupt is acknowledged, the in terrupt routine is ente red after the interrupt request flag has been automatically cleared.
chapter 17 interrupt functions user?s manual u14186ej5v0ud 298 (2) interrupt mask flag registers (mk0 and mk1) the interrupt mask flags are used to enable and disable the corresponding maskable interrupts. mk0 and mk1 are set with a 1-bit or 8-bi t memory manipulation instruction. reset input sets mk0 and mk1 to ffh. figure 17-3. format of interrupt mask flag register admk0 smbovmk0 smbmk0 tmmk90 tmmk82 tmmk81 tmmk80 wtimk mk1 ffe5h ffh r/w mk 0 1 interrupt handling control enable interrupt handling. disable interrupt handling. <6> <7> <5> <4> <3> <2> <1> <0> wtmk srmk20 stmk20 pmk3 pmk2 pmk1 pmk0 tmmk4 mk0 symbol address after reset r/w ffe4h ffh r/w <6> <7> <5> <4> <3> <2> <1> <0> note note note this flag is provided for the pd789167y and 789177y subseries only. for the pd789167 and 789177 subseries, the flag must be set to 1. cautions 1. when the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read tmmk4 flag results in an undefined value being detected. 2. when port 3 is being used as an output port, and its output level is changed, an interrupt request flag is set, because this port is also used as an external interrupt input. to use port 3 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
chapter 17 interrupt functions user?s manual u14186ej5v0ud 299 (3) external interrupt m ode register 0 (intm0) intm0 is used to specify the valid edge for intp0 to intp2. intm0 is set with an 8-bit memo ry manipulation instruction. reset input clears intm0 to 00h. figure 17-4. format of external interrupt mode register 0 es21 es20 es11 es10 es01 es00 0 0 intm0 76543210 es11 0 0 1 1 intp1 valid edge selection es10 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es21 0 0 1 1 intp2 valid edge selection es20 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges es01 0 0 1 1 intp0 valid edge selection es00 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges symbol address after reset r/w ffech 00h r/w cautions 1. bits 0 and 1 must be set to 0. 2. before setting intm0, set the corr esponding interrupt mask flag register ( mk ) to 1 to disable interrupts. to enable interrupts, clear the corresponding interrupt request flag ( if ) to 0, then clear the corresponding interrupt mask flag register ( mk to 0).
chapter 17 interrupt functions user?s manual u14186ej5v0ud 300 (4) external interrupt m ode register 1 (intm1) intm1 is used to specify the valid edge for intp3. intm1 is set with an 8-bit memo ry manipulation instruction. reset input clears intm1 to 00h. figure 17-5. format of external interrupt mode register 1 00 0 0 es31 0 0 es30 intm1 7 654 32 10 es31 0 0 1 1 intp3 valid edge selection es30 0 1 0 1 falling edge rising edge setting prohibited both rising and falling edges symbol address after reset r/w ffedh 00h r/w cautions 1. bits 2 to 7 must be set to 0. 2. before setting intm1, set pm k3 to 1 to disable interrupts. to enable interrupts, clear pif3 to 0, then clear pmk3 to 0. (5) program status word (psw) the program status word is used to hold the instruction execution resu lt and the current status of the interrupt requests. the ie flag, used to enable and di sable maskable interrupts, is mapped to the psw. the psw can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and dedicated instructions (ei and di). when a vector interrupt is ack nowledged, the psw is automatically saved to a stack, and the ie flag is reset to 0. reset input sets psw to 02h. figure 17-6. program status word configuration ie z 0 ac 0 0 1 cy psw symbol after reset 02h 76543210 ie 0 1 disable enable whether to enable/disable interrupt acknowledgment used in the execution of ordinary instructions
chapter 17 interrupt functions user?s manual u14186ej5v0ud 301 17.4 interrupt processing operation 17.4.1 non-maskable interrupt request acknowledgment operation a non-maskable interrupt request is unconditionally ackno wledged even when interrupts are disabled. it is not subject to interrupt priority control and takes precedence over all other interrupts. when a non-maskable interrupt request is acknowledged, the psw and pc are sa ved to the stack in that order, the ie flag is reset to 0, the content s of the vector table are loaded to t he pc, and then program execution branches. figure 17-7 shows the flowchart from non-maskable inte rrupt request generation to acknowledgment. figure 17-8 shows the timing of non-maskable interrupt request a cknowledgment. figure 17-9 shows the acknowledgment operation if multiple non-mask able interrupts are generated. caution during non-maskable interrupt service progr am execution, do not input another non-maskable interrupt request; if it is input, the service pr ogram will be interrupted and the new interrupt request will be acknowledged.
chapter 17 interrupt functions user?s manual u14186ej5v0ud 302 figure 17-7. flowchart from non-maskable in terrupt request genera tion to acknowledgment start wdtm4 = 1 (watchdog timer mode is selected) interval timer no wdt overflows no yes reset processing no yes yes interrupt request is generated interrupt servicing is started wdtm3 = 0 (non-maskable interrupt is selected) wdtm: watchdog timer mode register wdt: watchdog timer figure 17-8. timing of non-maskable interrupt request acknowledgment instruction instruction save psw and pc, and jump to interrupt processing interrupt processing program cpu processing tmif4 figure 17-9. acknowledgment n on-maskable interrupt request second interrupt servicing first interrupt servicing nmi request (second) nmi request (first) main routine
chapter 17 interrupt functions user?s manual u14186ej5v0ud 303 17.4.2 maskable interrupt re quest acknowledgment operation a maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. a vect ored interrupt request is a cknowledged in the interrupt enabled status (when the ie flag is set to 1). the time required to start the inte rrupt servicing after a maskable inte rrupt request has been generated is shown in table 17-3. see figures 17-11 and 17-12 for the inte rrupt request acknowledging timing. table 17-3. time from generation of maskable interrupt request to processing minimum time maximum time note 9 clocks 19 clocks note the wait time is maximum when an interrupt request is generated immedi ately before the bt and bf instruction. remark 1 clock: (f cpu : cpu clock) when two or more maskable interrupt requests are generat ed at the same time, they are acknowledged starting from the interrupt request assigned the highest priority. a pending interrupt is acknowledged when the stat us where it can be acknowledged is set. figure 17-10 shows the algorithm of acknowledging interrupt requests. when a maskable interrupt request is a cknowledged, the contents of the psw and pc are saved to the stack in that order, the ie flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the pc, and execution branches. to return from interrupt proce ssing, use the reti instruction. 1 f cpu
chapter 17 interrupt functions user?s manual u14186ej5v0ud 304 figure 17-10. interrupt request acknowledgment processing algorithm start if = 1 ? mk = 0 ? ie = 1 ? vectored interrupt servicing yes (interrupt request generated) yes yes no no no interrupt request pending interrupt request pending if: interrupt request flag mk: interrupt mask flag ie: flag to control maskable interrupt reques t acknowledgment (1 = enabled, 0 = disabled)
chapter 17 interrupt functions user?s manual u14186ej5v0ud 305 figure 17-11. interrupt request ackno wledgment timing (example of mov a,r) clock cpu interrupt mov a,r save psw and pc, and jump to interrupt servicing 8 clocks interrupt servicing program if an interrupt request flag ( if) is set before instruction clock n (n = 4 to 10) under execution becomes n ? 1, the interrupt is acknowledged after the inst ruction under execution?s completed. figure 17-11 shows an example of the interrupt request acknowledgment timing for an 8-bit data trans fer instruction mov a,r. since this instruction is executed in 4 clocks, if an interrupt o ccurs within 3 clocks after the executi on starts, the interrupt acknowledgment processing is performed after the mo v a,r instruction is completed. figure 17-12. interrupt request acknowledgment timing (when interrupt request fl ag is generated at last clock during in struction execution) save psw and pc, and jump to interrupt servicing 8 clocks interrupt servicing program clock cpu interrupt nop mov a,r if an interrupt request flag ( if) is set at the last clock of the in struction, the inte rrupt acknowledgment processing starts after the next instruction is exec uted. figure 17-12 shows an example of the interrupt acknowledgment timing for an interrupt reques t flag that is set at the second clo ck of nop (2-clock instruction). in this case, the mov a,r instruction a fter the nop instruction is executed, and then the interrupt acknowledgment processing is performed. caution interrupt requests are reserved while interrupt re quest flag register 0 or 1 (if0 or if1) or the interrupt mask flag register 0 or 1 (mk0 or mk1) is being accessed. 17.4.3 multiple interrupt processing multiple interrupt processing in wh ich another interrupt is acknowledged wh ile an interrupt is being serviced can be processed by priority. when two or more interrupt s are generated at once, interr upt servicing is performed according to the priority assigned to each interrupt request in advance (see table 17-1 ).
chapter 17 interrupt functions user?s manual u14186ej5v0ud 306 figure 17-13. example of multiple interrupts example 1. multiple interrupt is acknowledged intyy ei main processing ei intyy servicing intxx servicing reti ie = 0 intxx reti ie = 0 during interrupt intxx servicing, interrupt request int yy is acknowledged, and multiple interrupts are generated. an ei instruction is issued before each interrupt request acknowledgment, and the interrupt request acknowledgment enabled state is set. example 2. multiple interrupts are not generated because interrupts are not enabled intyy ei main processing reti intyy servicing intxx servicing ie = 0 intxx reti intyy is held pending ie = 0 because interrupts are not enabled in interrupt intxx serv icing (the ei instruction was not issued), interrupt request intyy is not acknowledged, and multiple interr upts are not generated. the intyy request is held pending and acknowledged after intxx servicing is performed. ie = 0: interrupt request acknowledgment disabled
chapter 17 interrupt functions user?s manual u14186ej5v0ud 307 17.4.4 interrupt request hold some instructions may hold the a cknowledgment of an instruction reques t pending until the completion of the execution of the next instruction even if the interrupt request (maskabl e interrupt, non-maskable interrupt, and external interrupt) is generated during t he execution. the following shows such instructions (interrupt request hold instructions). ? manipulation instruction for interrupt request flag registers 0 and 1 (if0 and if1) ? manipulation instruction for interrupt mask flag registers 0 and 1 (mk0 and mk1)
user?s manual u14186ej5v0ud 308 chapter 18 standby function 18.1 standby function and configuration 18.1.1 standby function the standby function is to used reduce the power consum ption of the system and can be effected in the following two modes. (1) halt mode this mode is set when the halt instru ction is executed. ha lt mode stops the operati on clock of the cpu. the system clock oscillator continues oscillating. th is mode does not reduce the current consumption as much as the stop mode, but is useful for resumi ng processing immediately when an interrupt request is generated, or for intermittent operations. (2) stop mode this mode is set when the stop instruction is ex ecuted. stop mode stops the main system clock oscillator and stops the entire system. the current consumpti on of the cpu can be s ubstantially reduced in this mode. the low voltage (v dd = 1.8 v min.) of the data memory can be reta ined. therefore, this mode is useful for retaining the contents of the data memory at an extremely low current consumption. stop mode can be released by an interrupt request, so this mode can be used for intermittent operations. however, some time is required until the system clock oscillator stabilizes after stop mode has been released. if processing must be resumed immediately by using an interrupt request, therefore, use the halt mode. in both modes, the previous contents of the registers, flags, and data memo ry before setting standby mode are all retained. in addition, the statuses of the output latches of the i/o ports and output buffers are also retained. caution to set stop mode, be sure to stop the opera tions of the peripheral ha rdware, and then execute the stop instruction.
chapter 18 standby function user?s manual u14186ej5v0ud 309 18.1.2 standby function control register the wait time after stop mode is released upon interrupt request until the oscillation st abilizes is controlled with the oscillation stabilization time selection register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, the o scillation stabilization time after reset input is 2 15 /f x , instead of 2 17 /f x . figure 18-1. format of oscillation st abilization time selection register symbol 7 6 5 4 3 2 1 0 address after reset r/w osts 0 0 0 0 0 osts2 osts1 osts0 fffah 04h r/w osts2 osts1 osts0 oscillation stabilization time selection at f x = 10.0 mhz operation note at f x = 5.0 mhz operation 0 0 0 2 12 /f x 409 s 819 s 0 1 0 2 15 /f x 3.27 ms 6.55 ms 1 0 0 2 17 /f x 13.1 ms 26.2 ms other than above setting prohibited note expanded-specification products only. caution the wait time after st op mode is released does not incl ude the time from stop mode release to clock oscillation star t (?a? in the figure below), regardless of release by reset input or by inte rrupt generation. stop mode release x1 pin voltage waveform a remark f x : main system clock oscillation frequency
chapter 18 standby function user?s manual u14186ej5v0ud 310 18.2 operation of standby function 18.2.1 halt mode (1) halt mode halt mode is set by execut ing the halt instruction. the operation status in halt mode is shown in the following table. table 18-1. operation statuses in halt mode halt mode operation status while main system clock is operating halt mode operation status while subsystem clock is operating item while subsystem clock is operating while subsystem clock is not operating while main system clock is operating while main system clock is not operating main system clock generator main system clock oscillation enabled does not operate cpu operation disabled port (output latch) remains in the state existing before the selection of halt mode 16-bit timer (tm90) oper ation enabled operation enabled note 1 operation enabled operation enabled note 2 8-bit timer/event counter (tm80) operation enabled operation enabled note 3 8-bit timer/event counter (tm81) operation enabled operation enabled note 4 8-bit timer (tm82) oper ation enabled operation enabled note 1 operation enabled operation enabled note 5 watch timer operation enabled operation enabled note 1 operation enabled operation enabled note 5 watchdog timer operation enabled operation disabled serial interface 20 operation enabled operation enabled note 6 smb0 operation enabled operation enabled note 7 a/d converter operation disabled multiplier operation disabled external interrupt operation enabled note 8 notes 1. operation is enabled when the ma in system clock is selected. 2. operation is enabled when the subsystem clock is selected and when buzzer output is enabled (for details, see 8.5 notes on 16-bit timer 90 ). 3. operation is enabled only when ti80 is selected as the count clock. 4. operation is enabled only when ti81 is selected as the count clock. 5. operation is enabled when the s ubsystem clock is selected. 6. operation is enabled in both 3-wire serial i/o and uart modes while an external clock is being used. 7. an interrupt can be generated when addre sses match during the slave operation. 8. maskable interrupt that is not masked
chapter 18 standby function user?s manual u14186ej5v0ud 311 (2) releasing halt mode halt mode can be released by t he following three sources. (a) releasing by unmasked interrupt request halt mode is released by an unmask ed interrupt request. in this case, if the interrupt request is enabled to be acknowledged, vectored interrupt servici ng is performed. if inte rrupts are disabled, the instruction at the next address is executed. figure 18-2. releasing halt mode by interrupt halt instruction standby release signal wait wait halt mode operating mode operating mode clock oscillation remarks 1. the broken lines indicate the case where the interrupt request t hat has released standby mode is acknowledged. 2. the wait time is as follows: ? when vectored interrupt servici ng is performed: 9 to 10 clocks ? when vectored interrupt servicing is not performed: 1 to 2 clocks (b) releasing by non-maskable interrupt request halt mode is released regardless of whether interrupts are enabled or disabled, and vectored interrupt servicing is performed.
chapter 18 standby function user?s manual u14186ej5v0ud 312 (c) releasing by reset input when halt mode is released by t he reset signal, execution branches to the reset vector address in the same manner as the ordinary reset operat ion, and program execut ion is started. figure 18-3. releasing halt mode by reset input halt instruction reset signal wait (2 15 /f x ) note reset period halt mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation note 3.27 ms (at f x = 10.0 mhz operation), 6.55 ms (at f x = 5.0 mhz operation) table 18-2. operation after release of halt mode releasing source mk ie operation 0 0 executes next address instruction 0 1 executes interrupt servicing maskable interrupt request 1 retains halt mode non-maskable interrupt request ? executes interrupt servicing reset input ? ? reset processing : don?t care
chapter 18 standby function user?s manual u14186ej5v0ud 313 18.2.2 stop mode (1) setting and operation st atus of stop mode stop mode is set by execut ing the stop instruction. caution because standby mode can be released by an interrupt request si gnal, standby mode is released as soon as it is set if there is an in terrupt source whose interrupt request flag is set and interrupt mask flag is reset. when st op mode is set, therefore, halt mode is set immediately after the stop in struction has been executed, the wait time set by the oscillation stabilization time selection register (osts) elapses, and then operation mode is set. the operation status in stop mode is shown in the following table. table 18-3. operation statuses in stop mode stop mode operation status while main system clock is operating item while subsystem clock is operating while subsystem clock is not operating main system clock generator main system clock oscillation stopped cpu operation disabled port (output latch) remains in the state existing before the selection of stop mode 16-bit timer (tm90) operation enabled note 1 operation disabled 8-bit timer/event counter (tm80) operation enabled note 2 8-bit timer/event counter (tm81) operation enabled note 3 8-bit timer (tm82) operation enabled note 4 operation disabled watch timer operation enabled note 4 operation disabled watchdog timer operation disabled serial interface 20 operation enabled note 5 smb0 operation enabled note 6 a/d converter operation disabled multiplier operation disabled external interrupt operation enabled note 7 notes 1. operation is enabled when the subsystem clo ck is selected and when buzzer output is enabled. 2. operation is enabled only when ti80 is selected as the count clock. 3. operation is enabled only when ti81 is selected as the count clock. 4. operation is enabled when the s ubsystem clock is selected. 5. operation is enabled in both 3-wire serial i/o and uart modes while an external clock is being used. 6. an interrupt can be generated when addre sses match during the slave operation. 7. maskable interrupt that is not masked
chapter 18 standby function user?s manual u14186ej5v0ud 314 (2) releasing stop mode stop mode can be released by the following two sources. (a) releasing by unmasked interrupt request stop mode can be released by an unmasked interrupt r equest. in this case, if the interrupt is enabled to be acknowledged, vectored interrupt servicing is performed, after t he oscillation stabilization time has elapsed. if the interrupt acknowledgment is disabled, the instruction at the next address is executed. figure 18-4. releasing stop mode by interrupt stop instruction standby release signal wait (set time by osts) stop mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation remark the broken lines indicate the case where the interrupt request t hat has released standby mode is acknowledged.
chapter 18 standby function user?s manual u14186ej5v0ud 315 (b) releasing by reset input when stop mode is released by the reset signal, the reset oper ation is performed after the oscillation stabilization time has elapsed. figure 18-5. releasing stop mode by reset input stop instruction reset signal wait (2 15 /f x ) note stop mode operating mode oscillation stabilization wait status clock operating mode oscillation stop oscillation oscillation reset period note 3.27 ms (at f x = 10.0 mhz operation), 6.55 ms (at f x = 5.0 mhz operation) table 18-4. operation after release of stop mode releasing source mk ie operation 0 0 executes next address instruction 0 1 executes interrupt servicing maskable interrupt request 1 retains stop mode reset input ? ? reset processing : don?t care
user?s manual u14186ej5v0ud 316 chapter 19 reset function the following two operations are av ailable to generate reset signals. (1) external reset input via reset pin (2) internal reset by program loop time detected by watchdog timer external and internal reset have no functional differences. in both cases, program exec ution starts at the address at 0000h and 0001h by reset signal input. when a low level is input to the r eset pin or the watchdog timer overflow s, a reset is applied and each hardware is set to the status shown in tabl e 19-1. each pin is high impedance dur ing reset input or during oscillation stabilization time just after reset release. when a high level is input to the reset pin, the reset is released and progr am execution is started after the oscillation stabilization time has elapsed. the reset applied by the watchdog time r overflow is automatically released after reset, and program execution is started afte r the oscillation stabilization time has elapsed (see figures 19-2 through 19-4 ). cautions 1. for an external reset, input a low level for 10 s or more to the reset pin. 2. when stop mode is released by reset, the st op mode contents are he ld during reset input. however, the port pins become high impedance. figure 19-1. block diagram of reset function reset interrupt function count clock reset controller watchdog timer over- flow reset signal stop
chapter 19 reset function user?s manual u14186ej5v0ud 317 figure 19-2. reset timing by reset input x1 reset internal reset signal port pin normal operation reset period (oscillation stops) oscillation stabilization time wait normal operation (reset processing) delay delay hi-z figure 19-3. reset timing by overflow in watchdog timer x1 internal reset signal port pin overflow in watchdog timer normal operation reset period (oscillation continues) oscillation stabilization time wait normal operation (reset processing) hi-z figure 19-4. reset timing by reset input in stop mode x1 reset internal reset signal port pin hi-z delay delay stop instruction execution normal operation stop status (oscillation stops) reset period (oscillation stops) oscillation stabilization time wait normal operation (reset processing)
chapter 19 reset function user?s manual u14186ej5v0ud 318 table 19-1. state of hardware after reset (1/2) hardware state after reset program counter (pc) note 1 loaded with the contents of the reset vector table (0000h, 0001h) stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 ram general-purpose register undefined note 2 ports (p0 to p3, p5, p6) (output latch) 00h port mode registers (pm0 to pm3, pm5) ffh pull-up resistor option registers (pu0, pub2, pub3) 00h processor clock control register (pcc) 02h suboscillation mode register (sckm) 00h subclock control register (css) 00h oscillation stabilization time selection register (osts) 04h timer counter (tm90) 0000h compare register (cr90) ffffh capture register (tcp90) undefined mode control register (tmc90) 00h 16-bit timer 90 buzzer output control register (bzc90) 00h timer counters (tm80 to tm82) 00h compare registers (cr80 to cr82) undefined 8-bit timer/event counters 80 to 82 mode control registers (tmc80 to tmc82) 00h watch timer mode control register (wtm) 00h timer clock selection register (tcl2) 00h watchdog timer mode register (wdtm) 00h mode register (adm0) 00h a/d input selection register (ads0) 00h a/d converter a/d conversion result register (adcr0) undefined mode register (csim20) 00h asynchronous serial interface mode register (asim20) 00h asynchronous serial interface st atus register (asis20) 00h baud rate generator control register (brgc20) 00h transmission shift register (txs20) ffh serial interface 20 reception buffer register (rxb20) undefined notes 1. while a reset signal is being input, and during the osc illation stabilization period, the contents of the pc will be undefined, while the remainder of the har dware will be the same as after the reset. 2. in standby mode, the ram enter s the hold state after a reset.
chapter 19 reset function user?s manual u14186ej5v0ud 319 table 19-1. state of hardware after reset (2/2) hardware state after reset control register (smbc0) 00h status register (smbs0) 00h clock selection register (smbcl0) 00h slave address register (smbsva0) 00h mode register (smbm0) 20h input level setting register (smbvi0) 00h smb0 shift register (smb0) 00h 16-bit multiplication result storage register (mul0) undefined multiplication data registers (mra0, mrb0) undefined multiplier multiplier control register (mulc0) 00h request flag registers (if0, if1) 00h mask flag registers (mk0, mk1) ffh interrupts external interrupt mode registers (intm0, intm1) 00h
user?s manual u14186ej5v0ud 320 chapter 20 flash memory version the pd78f9177, pd78f9177a, pd78f9177a(a), and pd78f9177a(a1) are flash me mory versions of the pd789177 subseries. the pd78f9177y, pd78f9177ay, and pd78f9177ay(a) are flash memory versions of the pd789177y subseries. the pd78f9177, pd78f9177a, pd78f9177a(a), and pd78f9177a(a1) replace the internal rom of the pd789167 and 789177 subseries with flash memory, while the pd78f9177y, pd78f9177ay, and pd78f9177ay(a) replace the internal rom of the pd789167y and 789177y subseries with flash memory. the differences between the flash memory and mask rom versions are shown in table 20-1. table 20-1. differences between fl ash memory and mask rom versions flash memory mask rom item pd78f9177a pd78f9177ay pd78f9177a(a) pd78f9177ay(a) pd78f9177ay(a1) pd78f9177 pd78f9177y pd789166 pd789166y pd789166(a) pd789166y(a) pd789166(a1) pd789166(a2) pd789167 pd789167y pd789167(a) pd789167y(a) pd789167(a1) pd789167(a2) pd789176 pd789176y pd789176(a) pd789176y(a) pd789176(a1) pd789176(a2) pd789177 pd789177y pd789177(a) pd789177y(a) pd789177(a1) pd789177(a2) rom structure flash memory mask rom rom capacity 24 kb 16 kb 24 kb 16 kb 24 kb internal memory high- speed ram 512 bytes minimum instruction execution time 0.2 s (at 10 mhz operation) 0.4 s (at 5 mhz operation) expanded-specificati on products: 0.2 s (at 10 mhz operation) (a1) products, (a2) products, and conventional products: 0.4 s (at 5 mhz operation) a/d converter resolution 10 bits 8 bits 10 bits specification of on-chip pull-up resistors for p50 to p53 by mask option disabled enabled v pp pin provided not provided electrical specifications refer to the electrical specifications chapters. cautions 1. there are differences in the amount of noise immunity and noise radi ation between the flash memory and mask rom versions. when pre-pr oducing an application set with the flash memory version and then mass producing it wit h the mask rom version, be sure to conduct sufficient evaluations on the comme rcial samples (cs) (not engineering sample, es) of the mask rom version. 2. when using a/d conversion result regi ster 0 (adcr0) with an 8-bit a/d converter ( pd789167 and 789167y subseries), manipulate with an 8-bit memory manipulation instruction; when using it with a 10-bit a/d converter ( pd789177 and 789177y subseries), use a 16-bit memory mani pulation instruction.
chapter 20 flash memory version user?s manual u14186ej5v0ud 321 when the flash memory version of the pd789167 or 789167y subseries, is used, however, adcr0 can be manipulated with an 8-bit memory manipulation instruction. in this case, use an object file assembled with the pd789167 or 789167y subseries. 20.1 flash memory characteristics flash memory programming is performed by connecting a dedicated flash programmer (flashpro iii (part no. fl- pr3, pg-fp3) or flashpro iv (part no. fl-pr4, pg-fp4)) to the target system with the pd78f9177, pd78f9177y, pd78f9177a, and pd78f9177ay mounted on the target system (on-board). a flash memory program adapter (fa adapter), which is a target board used exclus ively for programming, is also provided. remark fl-pr3, fl-pr4, and the program adapter are the pr oducts made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191). programming using flash memory has the following advantages. ? software can be modified after the microcontro ller is solder-mounted on the target system. ? distinguishing software facilities lo w-quantity, varied model production ? easy data adjustment when starting mass production 20.1.1 programming environment the following shows the environment required for pd78f9177, pd78f9177y, pd78f9177a, and pd78f9177ay flash memory programming. when flashpro iii or flashpro iv is used as a dedicated fl ash programmer, a host machine is required to control the dedicated flash programmer. comm unication between the host machine and flash programmer is performed via rs-232c/usb (rev. 1.1). for details, refer to the manual for flashpro iii or flashpro iv. remark usb is supported by flashpro iv only. figure 20-1. environment for wr iting program to flash memory host machine rs-232c usb dedicated flash programmer pd78f9177 v pp v dd v ss reset 3-wire serial i/o or uart or pseudo 3-wire mode pd78f9177y pd78f9177a pd78f9177ay
chapter 20 flash memory version user?s manual u14186ej5v0ud 322 20.1.2 communication mode use the communication mode shown in table 20-2 to perform communication between the dedicated flash programmer and pd78f9177, pd78f9177y, pd78f9177a, and pd78f9177ay. table 20-2. communication mode list type setting note 1 cpu clock notes 2, 3 communication mode comm port sio clock in flashpro on target board multiple rate pins used number of v pp pulses sio ch-0 (3-wired, sync.) si20/rxd20/p22 so20/txd20/p21 sck20/asck20/ p20 0 3-wire serial i/o (sio3) sio ch-1 (3-wired, sync.) note 8 100 hz to 1.25 mhz note 3 1, 2, 4, 5, 6, 8, 10 mhz note 4 1 to 10 mhz 1.0 p02 p01 p00 1 note 8 smb note 5 i2c ch-0 10 to 100 khz 1, 2, 4, 5, 6, 8, 10 mhz note 4 1 to 10 mhz 1.0 scl0/p23 sda0/p24 4 uart uart ch-0 (async.) 4,800 to 76,800 bps notes 3, 6 5, 10 mhz note 7 4.91, 5, 10 mhz 1.0 rxd20/si20/p22 txd20/so20/p21 8 pseudo 3-wire note 9 port a (pseudo 3-wire) 100 hz to 1 khz 1, 2, 4, 5 mhz 1 to 5 mhz 1.0 p02 p01 p00 12 note 9 notes 1. selection items for type settings on the dedicated flash programmer (flashpro iii or flashpro iv). 2. setting a frequency 5 mhz or higher for the pd78f9177 and pd78f9177y is prohibited. 3. the possible setting range differs depending on the voltage. for details, refer to chapters related to the electrical specifications chapters. 4. only 2, 4, 8 mhz in flashpro iii. 5. for the pd78f9177y and pd78f9177ay only. set slave address to 10h. 6. because signal wave slew also affects uart communication, in addition to the baud rate error, thoroughly evaluate the slew and baud rate error. 7. available only in flashpro iv. when using flashpro iii, be sure to select the clock of the resonator on the board. uart cannot be used with the clock supplied by flashpro iii. 8. in the pd78f9177a and pd78f9177ay only. 9. in the pd78f9177 and pd78f9177y only. serial transfer is performed by controlling the ports by software. figure 20-2. communication mode selection format 10 v v ss v dd v pp v dd v ss reset 12 n v pp pulses
chapter 20 flash memory version user?s manual u14186ej5v0ud 323 figure 20-3. example of connection with dedicated flash programmer (1/2) (a) 3-wire serial i/o (sio-ch0) vpp1 vdd reset sck so si gnd v pp v dd0, v dd1 , av dd reset dedicated flash programmer pd78f9177, 78f9177y, 78f9177a, 78f9177ay sck20 si20 so20 v ss0 , v ss1 , av ss clk note x1 (b) 3-wire serial i/o (sio-ch 1) or pseudo 3-wire mode reset sck so si gnd v pp v dd0 , v dd1 , av dd reset p00 (serial clock) p02 (serial input) p01 (serial output) v ss0 , v ss1 , av ss x1 vpp1 vdd clk note pd78f9177, 78f9177y, 78f9177a, 78f9177ay dedicated flash programmer (c) smb reset so si gnd v pp v dd0 , v dd1 , av dd reset scl0 sda0 v ss0 , v ss1 , av ss pd78f9177y, 78f9177ay x1 vpp1 vdd clk note dedicated flash programmer note connect this pin when the system clock is supplied from the dedicated flash progra mmer. if a resonator is already connected to the x1 pin, t he clk pin does not need to be connected. caution the v dd pin, if already connected to the power suppl y, must be connected to the vdd pin of the dedicated flash programmer. before us ing the power supply connected to the v dd pin, supply voltage before starting programming.
chapter 20 flash memory version user?s manual u14186ej5v0ud 324 figure 20-3. example of connection with dedicated flash programmer (2/2) (d) uart dedicated flash programmer vpp1 vdd reset so si clk notes 1, 2 gnd v pp v dd0 ,v dd1 , av dd reset r x d20 t x d20 x1 v ss0 ,v ss1 , av ss pd78f9177, 78f9177y, 78f9177a, 78f9177ay notes 1. connect this pin when the system clock is supp lied from the dedicated flash programmer. if a resonator is already connected to the x1 pi n, the clk pin does not need to be connected. 2. when using uart with flashpro iii, t he clock of the resonator connect ed to the x1 pin must be used, so connection to the clk pin is not necessary. caution the v dd pin, if already connected to the power suppl y, must be connected to the vdd pin of the dedicated flash programmer. before usi ng the power supply connected to the v dd pin, supply voltage before starting programming.
chapter 20 flash memory version user?s manual u14186ej5v0ud 325 if flashpro iii or flashpro iv is used as a dedicated fl ash programmer, the followi ng signals are generated for the pd78f9177, pd78f9177y, pd78f9177a, and pd78f9177ay. for details, refer to the manual of flashpro iii or flashpro iv. table 20-3. pin connection list signal name i/o pin function pin name 3-wire serial i/o (sio-ch0) 3-wire serial i/o (sio-ch1) note 1 smb note 2 uart pseudo 3-wire note 3 vpp1 output write voltage v pp vpp2 ? ? ? vdd i/o v dd voltage generation/ voltage monitoring v dd0 /v dd1 /av dd note 4 note 4 note 4 note 4 note 4 gnd ? ground v ss0 /v ss1 /av ss clk output clock output x1 { { { { { reset output reset signal reset si input receive signal so20/p01/ sda0/txd20 so output transmit signal si20/p02/scl0 /rxd20 sck output transfer clock sck20/p00 hs input handshake signal ? notes 1. in the pd78f9177a and pd78f9177ay only 2. in the pd78f9177y and pd78f9177ay only 3. in the pd78f9177 and pd78f9177y only 4. v dd voltage must be supplied befor e programming is started. remark : pin must be connected. { : if the signal is supplied on the target board, pin does not need to be connected. : pin does not need to be connected.
chapter 20 flash memory version user?s manual u14186ej5v0ud 326 20.1.3 on-board pin processing when performing programming on the tar get system, provide a connector on t he target system to connect the dedicated flash programmer. an on-board function that allows switching between normal operation m ode and flash memory programming mode may be required in some cases. in normal operation mode, input 0 v to the v pp pin. in flash memory progra mming mode, a write voltage of 10.0 v (typ.) is supplied to the vpp pin, so perform one of the following (1) or (2). (1) connect a pull-down resistor (rv pp = 10 k ? ) to the v pp pin. (2) use the jumper on t he board to switch the v pp pin input to either the wr iter or directly to gnd. a v pp pin connection example is shown below. figure 20-4. v pp pin connection example v pp pd78f9177, 78f9177y, 78f9177a, 78f9177ay pull-down resistor (rv pp ) connection pin of dedicated flash programmer the following shows the pins us ed by the serial interface. serial interface pins used sio-ch0 si20, so20, sck20 3-wire serial i/o sio-ch1 note 1 p00, p01, p02 smb note 2 scl0, sda0 uart rxd20, txd20 pseudo 3-wire note 3 p00, p01, p02 notes 1. in the pd78f9177a and pd78f9177ay only 2. in the pd78f9177y and pd78f9177ay only 3. in the pd78f9177 and pd78f9177y only when connecting the dedicated flash programmer to a serial interface pin that is connected to another device on- board, signal conflict or abnormal operation of the other device may occur. care must therefore be taken with such connections.
chapter 20 flash memory version user?s manual u14186ej5v0ud 327 (1) signal conflict if the dedicated flash programmer (output ) is connected to a serial interfac e pin (input) that is connected to another device (output), a signal conflict occurs. to prevent this , isolate the connection with the other device or set the other device to the output high impedance status. figure 20-5. signal conflict (input pin of serial interface) input pin signal conflict connection pin of dedicated flash programmer other device output pin pd78f9177, 78f9177y, 78f9177a, 78f9177ay in the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device. (2) abnormal operation of other device if the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input ), a signal is output to the dev ice, and this may cause an abnormal operation. to prevent this abnormal operation, isolate the c onnection with the other devic e or set so that the input signals to the ot her device are ignored. figure 20-6. abnormal operation of other device pin connection pin of dedicated flash programmer connection pin of dedicated flash programmer other device input pin pin other device input pin if the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device. pd78f9177, 78f9177y, 78f9177a, 78f9177ay pd78f9177, 78f9177y, 78f9177a, 78f9177ay if the signal output by the pd78f9177, 78f9177y, 78f9177a, and 78f9177ay affects another device in the flash memory programming mode, isolate the signals of the other device.
chapter 20 flash memory version user?s manual u14186ej5v0ud 328 if the reset signal of the dedicated flash programmer is connected to the reset pi n connected to the reset signal generator on-board, a signal conflict occurs. to prevent this, is olate the connection with the reset signal generator. if the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed. therefore, do not input reset signal s from other than the dedicated flash programmer. figure 20-7. signal conflict (reset pin) reset connection pin of dedicated flash programmer reset signal generator signal conflict output pin the signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the flash memory programming mode, so isolate the signal of the reset signal generator. pd78f9177, 78f9177y, 78f9177a, 78f9177ay when the pd78f9177, pd78f9177y, pd78f9177a, and pd78f9177ay enter the flash memory programming mode, all the pins other than those that communicate in fl ash memory programmer are in the same status as immediately after reset. if the external device does not recogni ze initial statuses such as the output high impedance st atus, therefore, connect the external device to v dd0 , v dd1 , v ss0 , or v ss1 via a resistor. when using the on-board clock, connect x1, x2, xt1, and xt2 as required in t he normal operation mode. when using the clock output of the flas h programmer, connect it directly to x1, disconnecting the main oscillator on-board, and leave the x2 pin open. the subclock conforms to the me thod in the normal operation mode. to use the power output from t he flash programmer, connect the v dd0 and v dd1 pins to vdd of the flash programmer, and the v ss0 and v ss1 pins to gnd of the flash programmer. to use the on-board power supply, ma ke connections that accord with t he normal operation mode. however, because the voltage is monitored by t he flash programmer, be sure to c onnect vdd of the flash programmer. supply the same power as in the normal operat ion mode to the other power supply pins (av dd , av ref , and av ss ).
chapter 20 flash memory version user?s manual u14186ej5v0ud 329 20.1.4 connection of adapter for flash writing the following figures show the exam ples of recommended connection when the adapter for flash writing is used. figure 20-8. wiring example for flash writing adap ter in 3-wire serial i/o mode (sio-ch0) (1/2) (a) 44-pin plastic lqfp (10 10) 44 43 42 41 40 39 38 13 12 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 25 37 24 pd78f9177 pd78f9177y pd78f9177a pd78f9177ay gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd
chapter 20 flash memory version user?s manual u14186ej5v0ud 330 figure 20-8. wiring example for flash writing adap ter in 3-wire serial i/o mode (sio-ch0) (2/2) (b) 48-pin plastic tqfp (fine pitch) (7 7) 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 12 25 37 24 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface v dd (2.7 to 5.5 v) gnd pd78f9177a pd78f9177y pd78f9177ay
chapter 20 flash memory version user?s manual u14186ej5v0ud 331 figure 20-9. wiring example for flash writ ing adapter in 3-wire serial i/o mode (sio-ch1) or pseudo 3-wire mode (1/2) (a) 44-pin plastic lqfp (10 10) 44 43 42 41 40 39 38 13 12 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 25 37 24 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd pd78f9177 pd78f9177y pd78f9177a pd78f9177ay
chapter 20 flash memory version user?s manual u14186ej5v0ud 332 figure 20-9. wiring example for flash writ ing adapter in 3-wire serial i/o mode (sio-ch1) or pseudo 3-wire mode (2/2) (b) 48-pin plastic tqfp (fine pitch) (7 7) 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 12 25 37 24 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface v dd (2.7 to 5.5 v) gnd pd78f9177a pd78f9177y pd78f9177ay
chapter 20 flash memory version user?s manual u14186ej5v0ud 333 figure 20-10. wiring example for flash writing adapter in smb mode (1/2) (a) 44-pin plastic lqfp (10 10) 44 43 42 41 40 39 38 13 12 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 25 37 24 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd pd78f9177y pd78f9177ay
chapter 20 flash memory version user?s manual u14186ej5v0ud 334 figure 20-10. wiring example for flash writing adapter in smb mode (2/2) (b) 48-pin plastic tqfp (fine pitch) (7 7) 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 12 25 37 24 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface v dd (2.7 to 5.5 v) gnd pd78f9177y pd78f9177ay
chapter 20 flash memory version user?s manual u14186ej5v0ud 335 figure 20-11. wiring example for flash writing adapter in uart mode (1/2) (a) 44-pin plastic lqfp (10 10) 44 43 42 41 40 39 38 13 12 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 25 37 24 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface vdd (2.7 to 5.5 v) gnd pd78f9177 pd78f9177y pd78f9177a pd78f9177ay
chapter 20 flash memory version user?s manual u14186ej5v0ud 336 figure 20-11. wiring example for flash writing adapter in uart mode (2/2) (b) 48-pin plastic tqfp (fine pitch) (7 7) 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 36 35 34 33 32 31 30 29 28 27 26 12 25 37 24 gnd vdd vdd2 (lvdd) si so sck clkout reset vpp reserve/hs writer interface v dd (2.7 to 5.5 v) gnd pd78f9177a pd78f9177y pd78f9177ay
user?s manual u14186ej5v0ud 337 chapter 21 mask option table 21-1. selection of mask option for pins pin mask option p50 to p53 whether a pull-up resistor is to be incorporated can be spec ified in 1-bit units. for p50 to p53 (port 5), whether a pull-up resistor is to be incorporated can be specif ied by a mask option. the mask option is specified in 1-bit units. caution the flash memory versi ons do not provide a mask option pull-up resistor incorporation function.
user?s manual u14186ej5v0ud 338 chapter 22 instruction set this chapter lists the instruction set of the pd789167, 789177, 789167y, and 789177y subser ies. for details of the operation and machine language (instruction code) of each instruction, refer to 78k/0s series instruction user?s manual (u11047e) . 22.1 operation 22.1.1 operand identifier s and description methods operands are described in ?operand? colu mn of each instruction in accordanc e with the description method of the instruction operand identifier (refer to the assembler specif ications for details). w hen there are two or more description methods, select one of them. uppercase letters the and symbols, #, !, $, and [ ] are keywords and must be described as they are. each symbol has the following meaning. ? #: immediate dat a specification ? !: absolute address specification ? $: relative address specification ? [ ]: indirect address specification in the case of immediate data, descr ibe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $ and [ ] symbols. for operand register identifiers, r and rp , either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 22-1. operand identifi ers and description methods identifier description method r rp sfr x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7) ax (rp0), bc (rp1), de (rp2), hl (rp3) special-function register symbol saddr saddrp fe20h to ff1fh immediate data or labels fe20h to ff1fh immediate data or labels (even addresses only) addr16 addr5 0000h to ffffh immediate data or labels (only ev en addresses for 16-bit data transfer instructions) 0040h to 007fh immediate data or labels (even addresses only) word byte bit 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label remark see table 5-3 special-function registers for symbols of special-function registers.
chapter 22 instruction set user?s manual u14186ej5v0ud 339 22.1.2 description of ?operation? column a: a register; 8-bit accumulator x: x register b: b register c: c register d: d register e: e register h: h register l: l register ax: ax register pair; 16-bit accumulator bc: bc register pair de: de register pair hl: hl register pair pc: program counter sp: stack pointer psw: program status word cy: carry flag ac: auxiliary carry flag z: zero flag ie: interrupt request enable flag ( ): memory contents indicated by addre ss or register contents in parenthesis h , l : higher 8 bits and lower 8 bits of 16-bit register : logical product (and) : logical sum (or) : exclusive logical sum (exclusive or) ? : inverted data addr16: 16-bit immediate data or label jdisp8: signed 8-bit data (displacement value) 22.1.3 description of ?flag? column (blank): unchanged 0: cleared to 0 1: set to 1 : set/cleared according to the result r: previously saved value is stored
chapter 22 instruction set user?s manual u14186ej5v0ud 340 22.2 operation list flag mnemonic operands bytes clocks operation z ac cy r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte 3 6 sfr byte a, r note 1 2 4 a r r, a note 1 2 4 r a a, saddr 2 4 a (saddr) saddr, a 2 4 (saddr) a a, sfr 2 4 a sfr sfr, a 2 4 sfr a a, !addr16 3 8 a (addr16) !addr16, a 3 8 (addr16) a psw, #byte 3 6 psw byte a, psw 2 4 a psw psw, a 2 4 psw a a, [de] 1 6 a (de) [de], a 1 6 (de) a a, [hl] 1 6 a (hl) [hl], a 1 6 (hl) a a, [hl + byte] 2 6 a (hl + byte) mov [hl + byte], a 2 6 (hl + byte) a a, x 1 4 a ? x a, r note 2 2 6 a ? r a, saddr 2 6 a ? (saddr) a, sfr 2 6 a ? sfr a, [de] 1 8 a ? (de) a, [hl] 1 8 a ? (hl) xch a, [hl + byte] 2 8 a ? (hl + byte) notes 1. except r = a. 2. except r = a, x. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 22 instruction set user?s manual u14186ej5v0ud 341 flag mnemonic operands bytes clocks operation z ac cy rp, #word 3 6 rp word ax, saddrp 2 6 ax (saddrp) saddrp, ax 2 8 (saddrp) ax ax, rp note 1 4 ax rp movw rp, ax note 1 4 rp ax xchw ax, rp note 1 8 ax ? rp a, #byte 2 4 a, cy a + byte saddr, #byte 3 6 (saddr), cy (saddr) + byte a, r 2 4 a, cy a + r a, saddr 2 4 a, cy a + (saddr) a, !addr16 3 8 a, cy a + (addr16) a, [hl] 1 6 a, cy a + (hl) add a, [hl + byte] 2 6 a, cy a + (hl + byte) a, #byte 2 4 a, cy a + byte + cy saddr, #byte 3 6 (saddr), cy (saddr) + byte + cy a, r 2 4 a, cy a + r + cy a, saddr 2 4 a, cy a + (saddr) + cy a, !addr16 3 8 a, cy a + (addr16) + cy a, [hl] 1 6 a, cy a + (hl) + cy addc a, [hl + byte] 2 6 a, cy a + (hl + byte) + cy a, #byte 2 4 a, cy a ? byte saddr, #byte 3 6 (saddr), cy (saddr) ? byte a, r 2 4 a, cy a ? r a, saddr 2 4 a, cy a ? (saddr) a, !addr16 3 8 a, cy a ? (addr16) a, [hl] 1 6 a, cy a ? (hl) sub a, [hl + byte] 2 6 a, cy a ? (hl + byte) note only when rp = bc, de, or hl. remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 22 instruction set user?s manual u14186ej5v0ud 342 flag mnemonic operands bytes clocks operation z ac cy a, #byte 2 4 a, cy a ? byte ? cy saddr, #byte 3 6 (saddr), cy (saddr) ? byte ? cy a, r 2 4 a, cy a ? r ? cy a, saddr 2 4 a, cy a ? (saddr) ? cy a, !addr16 3 8 a, cy a ? (addr16) ? cy a, [hl] 1 6 a, cy a ? (hl) ? cy subc a, [hl + byte] 2 6 a, cy a ? (hl + byte) ? cy a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) and a, [hl + byte] 2 6 a a (hl + byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) or a, [hl + byte] 2 6 a a (hl + byte) a, #byte 2 4 a a byte saddr, #byte 3 6 (saddr) (saddr) byte a, r 2 4 a a r a, saddr 2 4 a a (saddr) a, !addr16 3 8 a a (addr16) a, [hl] 1 6 a a (hl) xor a, [hl + byte] 2 6 a a (hl + byte) remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 22 instruction set user?s manual u14186ej5v0ud 343 flag mnemonic operands bytes clocks operation z ac cy a, #byte 2 4 a ? byte saddr, #byte 3 6 (saddr) ? byte a, r 2 4 a ? r a, saddr 2 4 a ? (saddr) a, !addr16 3 8 a ? (addr16) a, [hl] 1 6 a ? (hl) cmp a, [hl + byte] 2 6 a ? (hl + byte) addw ax, #word 3 6 ax, cy ax + word subw ax, #word 3 6 ax, cy ax ? word cmpw ax, #word 3 6 ax ? word r 2 4 r r + 1 inc saddr 2 4 (saddr) (saddr) + 1 r 2 4 r r ? 1 dec saddr 2 4 (saddr) (saddr) ? 1 incw rp 1 4 rp rp + 1 decw rp 1 4 rp rp ? 1 ror a, 1 1 2 (cy, a 7 a 0 , a m ? 1 a m ) 1 rol a, 1 1 2 (cy, a 0 a 7 , a m+1 a m ) 1 rorc a, 1 1 2 (cy a 0 , a 7 cy, a m ? 1 a m ) 1 rolc a, 1 1 2 (cy a 7 , a 0 cy, a m+1 a m ) 1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 a.bit 2 4 a.bit 1 psw.bit 3 6 psw.bit 1 set1 [hl].bit 2 10 (hl).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 a.bit 2 4 a.bit 0 psw.bit 3 6 psw.bit 0 clr1 [hl].bit 2 10 (hl).bit 0 set1 cy 1 2 cy 1 1 clr1 cy 1 2 cy 0 0 not1 cy 1 2 cy cy remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 22 instruction set user?s manual u14186ej5v0ud 344 flag mnemonic operands bytes clocks operation z ac cy call !addr16 3 6 (sp ? 1) (pc + 3) h , (sp ? 2) (pc + 3) l , pc addr16, sp sp ? 2 callt [addr5] 1 8 (sp ? 1) (pc + 1) h , (sp ? 2) (pc + 1) l , pc h (00000000, addr5 + 1), pc l (00000000, addr5), sp sp ? 2 ret 1 6 pc h (sp + 1), pc l (sp), sp sp + 2 reti 1 8 pc h (sp + 1), pc l (sp), psw (sp + 2), sp sp + 3 r r r psw 1 2 (sp ? 1) psw, sp sp ? 1 push rp 1 4 (sp ? 1) rp h , (sp ? 2) rp l , sp sp ? 2 psw 1 4 psw (sp), sp sp + 1 r r r pop rp 1 6 rp h (sp + 1), rp l (sp), sp sp + 2 sp, ax 2 8 sp ax movw ax, sp 2 6 ax sp !addr16 3 6 pc addr16 $addr16 2 6 pc pc + 2 + jdisp8 br ax 1 6 pc h a, pc l x bc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 1 bnc $saddr16 2 6 pc pc + 2 + jdisp8 if cy = 0 bz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 1 bnz $saddr16 2 6 pc pc + 2 + jdisp8 if z = 0 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 1 bt psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 1 saddr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 pc pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 pc pc + 3 + jdisp8 if a.bit = 0 bf psw.bit, $addr16 4 10 pc pc + 4 + jdisp8 if psw.bit = 0 b, $addr16 2 6 b b ? 1, then pc pc + 2 + jdisp8 if b 0 c, $addr16 2 6 c c ? 1, then pc pc + 2 + jdisp8 if c 0 dbnz saddr, $addr16 3 8 (saddr) (saddr) ? 1, then pc pc + 3 + jdisp8 if (saddr) 0 nop 1 2 no operation ei 3 6 ie 1 (enable interrupt) di 3 6 ie 0 (disable interrupt) halt 1 2 set halt mode stop 1 2 set stop mode remark one instruction clock cycle is one cpu clock cycle (f cpu ) selected by the processor clock control register (pcc).
chapter 22 instruction set user?s manual u14186ej5v0ud 345 22.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, inc, dec, ror, rol, rorc, rolc, push, pop, dbnz 2nd operand 1st operand #byte a r sfr saddr ! addr16 psw [de] [hl] [hl + byte] $addr16 1 none a add addc sub subc and or xor cmp mov note xch note add addc sub subc and or xor cmp mov xch mov xch add addc sub subc and or xor cmp mov add addc sub subc and or xor cmp mov mov xch mov xch add addc sub subc and or xor cmp mov xch add addc sub subc and or xor cmp ror rol rorc rolc r mov mov inc dec b, c dbnz sfr mov mov saddr mov add addc sub subc and or xor cmp mov dbnz inc dec !addr16 mov psw mov mov push pop [de] mov [hl] mov [hl + byte] mov note except r = a.
chapter 22 instruction set user?s manual u14186ej5v0ud 346 (2) 16-bit instructions movw, xchw, addw, subw, cmpw , push, pop, incw, decw 2nd operand 1st operand #word ax rp note saddrp sp none ax addw subw cmpw movw xchw movw movw rp movw movw note incw decw push pop saddrp movw sp movw note only when rp = bc, de, or hl. (3) bit manipulation instructions set1, clr1, not1, bt, bf 2nd operand 1st operand $addr16 none a.bit bt bf set1 clr1 sfr.bit bt bf set1 clr1 saddr.bit bt bf set1 clr1 psw.bit bt bf set1 clr1 [hl].bit set1 clr1 cy set1 clr1 not1
chapter 22 instruction set user?s manual u14186ej5v0ud 347 (4) call instructions/branch instructions call, callt, br, bc, bnc, bz, bnz, dbnz 2nd operand 1st operand ax !addr16 [addr5] $addr16 basic instructions br call br callt br bc bnc bz bnz compound instructions dbnz (5) other instructions ret, reti, nop, ei, di, halt, stop
user?s manual u14186ej5v0ud 348 chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) remark the values listed in this chapter are for expanded-specification products. absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v av dd v supply voltage av ref av dd ? 0.3 v v dd av dd + 0.3 v av ref av dd + 0.3 v av ref v dd + 0.3 v ? 0.3 to +6.5 v v i1 pins other than p50 to p53, p23, p24 ? 0.3 to v dd + 0.3 v v i2 p23, p24 ? 0.3 to +5.5 v n-ch open drain ? 0.3 to +13 v input voltage v i3 p50 to p53 on-chip pull-up resistor ? 0.3 to v dd + 0.3 v output voltage v o ? 0.3 to v dd + 0.3 v per pin ? 10 ma total for all pins pd78916x, 78917x, 78916xy, 78917xy ? 30 ma per pin ? 7 ma output current, high i oh total for all pins pd78916x(a), 78917x(a), 78916xy(a), 78917xy(a) ? 22 ma per pin 30 ma total for all pins pd78916x, 78917x, 78916xy, 78917xy 160 ma per pin 10 ma output current, low i ol total for all pins pd78916x(a), 78917x(a), 78916xy(a), 78917xy(a) 120 ma operating ambient temperature t a ? 40 to +85 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, a nd therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 349 main system clock osc illator characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit v dd = 4.5 to 5.5 v 1.0 10.0 mhz v dd = 3.0 to 5.5 v 1.0 6.0 mhz oscillation frequency (f x ) note 1 v dd = 1.8 to 5.5 v 1.0 5.0 mhz ceramic resonator oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms v dd = 4.5 to 5.5 v 1.0 10.0 mhz v dd = 3.0 to 5.5 v 1.0 6.0 mhz oscillation frequency (f x ) note 1 v dd = 1.8 to 5.5 v 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 ms v dd = 4.5 to 5.5 v 1.0 10.0 mhz v dd = 3.0 to 5.5 v 1.0 6.0 mhz x1 input frequency (f x ) note 1 v dd = 1.8 to 5.5 v 1.0 5.0 mhz v dd = 4.5 to 5.5 v 45 500 ns v dd = 3.0 to 5.5 v 75 500 ns x1 input high-/low-level width (t xh , t xl ) v dd = 1.8 to 5.5 v 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator that stabilizes oscillation within the oscillation wait time. cautions 1. when using the main system clock osc illator, wire as follows in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss0 . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and th e device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. x2 x1 v ss0 c2 c1 x2 x1 v ss0 c2 c1 x1 x2 x1 x2 open
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 350 recommended oscillator constant ( pd78916x, 17x, 16xy, and 17xy) ceramic resonator (t a = ?40 to +85c) recommended circuit constant (pf) oscillation voltage range (v dd ) manufacturer part number frequency (mhz) c1 c2 min. max. remarks csbla1m00j58-b0 csbfb1m00j58-r1 1.000 150 150 2.2 5.5 without on-chip capacitor cstcc2m00g56-r0 cstls2m00g56-b0 2.000 cstcr4m00g53-r0 cstls4m00g53-b0 4.000 cstcr4m19g53-r0 cstls4m19g53-b0 4.195 cstcr4m91g53-r0 cstls4m91g53-b0 4.915 cstcr5m00g53-r0 cstls5m00g53-b0 5.000 cstcr6m00g53-r0 cstls6m00g53-b0 6.000 cstce8m00g52-r0 cstls8m00g53-b0 8.000 cstce8m38g52-r0 cstls8m38g53-b0 8.388 cstce10m0g52-r0 1.8 5.5 murata mfg. co., ltd. (standard type) cstls10m0g53-b0 10.000 ? ? 1.9 5.5 with on-chip capacitor murata mfg. co., ltd. (low-voltage drive type) cstls10m0g53093- b0 10.000 ? ? 1.8 5.5 with on-chip capacitor caution the oscillator constant is a reference value based on evaluati on in specific environments by the resonator manufacturer. if th e oscillator characteri stics need to be optimized in the actual application, request the resona tor manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the internal operation conditions of the pd78916x, 17x, 16xy, and 17xy within the specifications of the dc and ac characteristics.
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 351 recommended oscillator constant ( pd78916x(a), 17x(a), 16xy(a), and 17xy(a)) ceramic resonator (t a = ?40 to +85c) recommended circuit constant (pf) oscillation voltage range (v dd ) manufacturer part number frequency (mhz) c1 c2 min. max. remarks cstcc2m00g56a-r0 2.000 cstcr4m00g53a-r0 4.000 cstcr4m19g53a-r0 4.195 cstcr4m91g53a-r0 4.915 cstcr5m00g53a-r0 5.000 cstcr6m00g53a-r0 6.000 cstce8m00g52a-r0 8.000 cstce8m38g52a-r0 8.388 murata mfg. co., ltd. cstce10m0g52a-r0 10.000 ? ? 1.8 5.5 on-chip capacitor caution the oscillator constant is a reference value based on evaluati on in specific environments by the resonator manufacturer. if th e oscillator characteri stics need to be optimized in the actual application, request the resona tor manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the intern al operation conditions of the pd78916x(a), 17x(a), 16xy(a), and 17xy(a) within the specifications of the dc and ac characteristics.
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 352 subsystem clock oscillator characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz v dd = 4.5 to 5.5 v 1.2 2 s crystal resonator xt2 xt1 v ss0 c4 c3 r oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 input high-/low-level width (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator that stabilizes oscillation within the oscillation wait time. cautions 1. when using the subsyst em clock oscillator, wire as follo ws in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss0 . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is mo re prone to malfunction due to noise than the ma in system clock oscillator. particular care is therefore required with the wir ing method when the subsystem clock is used. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. xt1 xt2
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 353 dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (1/3) parameter symbol conditions min. typ. max. unit per pin ? 1 ma total for all pins pd78916x, 78917x, 78916xy, 78917xy ? 15 ma per pin ? 1 ma output current , high i oh total for all pins pd78916x(a), 78917x(a), 78916xy(a), 78917xy(a) ? 11 ma per pin 10 ma total for all pins pd78916x, 78917x, 78916xy, 78917xy 80 ma per pin 3 ma output current, low i ol total for all pins pd78916x(a), 78917x(a), 78916xy(a), 78917xy(a) 60 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 p00 to p05, p10, p11, p60 to p67 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v n-ch open drain v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih2 p50 to p53 on-chip pull- up resistor v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p20 to p26, p30 to p33 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 p00 to p05, p10, p11, p60 to p67 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset, p20 to p26, p30 to p33 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v 0 0.1 v v dd = 4.5 to 5.5 v, i oh = ? 1 ma v dd ? 1.0 v output voltage, high v oh pins other than p23, p24, p50 to p53 v dd = 1.8 to 5.5 v, i oh = ? 100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78916x, 78917x, 78916xy, 78917xy) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78916x(a), 78917x(a), 78916xy(a), 78917xy(a)) 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78916x, 78917x, 78916xy, 78917xy) 1.0 v v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78916x(a), 78917x(a), 78916xy(a), 78917xy(a)) 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 354 dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (2/3) parameter symbol conditions min. typ. max. unit i lih1 pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 3 a i lih2 v i = v dd x1, x2, xt1, xt2 20 a input current leakage, high i lih3 v i = 12 v note 1 p50 to p53 (n-ch open drain) 20 a i lil1 pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 ? 3 a i lil2 x1, x2, xt1, xt2 ? 20 a input current leakage, low i lil3 v i = 0 v p50 to p53 (n-ch open drain) ? 3 note 2 a output current leakage, high i loh v o = v dd 3 a output current leakage, low i lol v o = 0 v ? 3 a software pull-up resistor r 1 v i = 0 v, for pins other than p23, p24, and p50 to p53 50 100 200 k ? mask option pull- up resistor r 2 v i = 0 v, p50 to p53 15 30 60 k ? notes 1. when pull-up resistors are not connected to p50 to p53 (specified by the mask option). 2. a low-level input leakage current of ? 60 a (max.) flows only during th e 1-cycle time after a read instruction is executed to p50 to p53 when on-chip pull-up resistors are not connected to p50 to p53 (specified by the mask option) and p50 to p53 are set to input mode. at times other than this, a ? 3 a (max.) current flows. remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 355 dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (3/3) parameter symbol conditions min. typ. max. unit 10.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 4 3.2 8.0 ma 6.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 4 2.0 4.7 ma v dd = 5.0 v 10% note 4 1.8 4.0 ma v dd = 3.0 v 10% note 5 0.6 1.2 ma i dd1 note 1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.35 0.7 ma 10.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 4 1.5 3.0 ma 6.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 4 0.9 1.8 ma v dd = 5.0 v 10% note 4 0.75 1.5 ma v dd = 3.0 v 10% note 5 0.4 0.8 ma i dd2 note 1 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.25 0.5 ma v dd = 5.0 v 10% 25 90 a v dd = 3.0 v 10% 7.0 50 a i dd3 note 1 32.768 khz crystal oscillation operating mode note 3 (c3 = c4 = 22 pf, r = 220 k ? ) v dd = 2.0 v 10% 3.5 30 a v dd = 5.0 v 10% 16 75 a v dd = 3.0 v 10% 4.5 35 a i dd4 note 1 32.768 khz crystal oscillatio n halt mode note 3 (c3 = c4 = 22 pf, r = 220 k ? ) v dd = 2.0 v 10% 2.3 18 a v dd = 5.0 v 10% 0.1 10 a v dd = 3.0 v 10% 0.05 5.0 a i dd5 note 1 32.768 khz crystal stop stop mode v dd = 2.0 v 10% 0.05 3.0 a 10.0 mhz crystal oscillation a/d operating mode v dd = 5.0 v 10% note 4 4.0 10.0 ma 6.0 mhz crystal oscillation a/d operating mode v dd = 5.0 v 10% note 4 2.8 6.7 ma v dd = 5.0 v 10% note 4 2.6 6.0 ma v dd = 3.0 v 10% note 5 1.4 3.2 ma power supply current i dd6 note 2 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 1.15 2.7 ma notes 1. the av ref on (adcs0 (bit 7 of adm0; a/d converter mode register 0) = 1), av dd , and the port current (including the current flowing through the inte rnal pull-up resistors) are not included. 2. the av ref on (adcs0 =1) and port current (including the current flowing through the internal pull-up resistors) are not included. refer to the a/d conv erter characteristics for the current flowing through av ref . 3. when the main system clock is stopped. 4. during high-speed mode operation (when the processor clock control register (pcc) is set to 00h.) 5. during low-speed mode operation (when pcc is set to 02h) remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 356 ac characteristics (1) basic operation (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 4.5 to 5.5 v 0.2 8 s v dd = 3.0 to 5.5 v 0.33 8 s v dd = 2.7 to 5.5 v 0.4 8 s operation based on the main system clock v dd = 1.8 to 5.5 v 1.6 8 s cycle time (minimum instruction execution time) t cy operation based on the s ubsystem clock 114 122 125 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 and ti81 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz v dd = 2.7 to 5.5 v 0.1 s ti80 and ti81 input high-/low-level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s interrupt input high- /low-level width t inth , t intl intp0 to intp3 10 s reset input low- level width t rsl 10 s cpt90 input high- /low-level width t cph , t cpl 10 s t cy vs. v dd (main system clock) 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] supply voltage v dd [v] operation guaranteed range
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 357 (2) serial interface sio20 (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck20...internal clock) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (b) 3-wire serial i/o mode (sck20...external clock) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3500 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (when using ss20, to ss20 ) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (when using ss20, from ss20 ) t kds2 v dd = 1.8 to 5.5 v 800 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 358 (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3500 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise time, fall time t r , t f 1 s
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 359 (3) serial interface smb0 (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) ( pd78916xy, 78917xy, 78916xy(a), 78917xy(a) only) (a) dc characteristics parameter symbol conditions min. typ. max. unit input voltage, high v ih scl0, sda0 (at hysteresis) 0.8v dd v dd v input voltage, low v il scl0, sda0 (at hysteresis) 0 0.2v dd v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol scl0, sda0 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v input current leakage, high i lih scl0, sda0 v i = v dd 3 a input current leakage, low i lil scl0, sda0 v i = 0 v ? 3 a (b) dc characteristics (when using comparator) parameter symbol conditions min. typ. max. unit input range v sda , v scl v dd = 1.8 to 5.5 v 0 5.5 v 4.5 v dd 5.5 v 0.72v ismb v ismb 1.28v ismb v 3.3 v dd < 4.5 v 0.78v ismb v ismb 1.22v ismb v 2.7 v dd < 3.3 v 0.75v ismb v ismb 1.25v ismb v transfer level v isda , v iscl 1.8 v dd < 2.7 v 0.90v ismb v ismb 1.45v ismb v lvl01, lvl00 = 0, 1 0.25 v dd v lvl01, lvl00 = 1, 0 0.375 v dd v input level threshold value note v ismb lvl01, lvl00 = 1, 1 0.5 v dd v note v ismb is an input level threshold value selected by bits lvl00 and lvl01 (bits 0 and 1 of smb input level setting register 0 (smbvi0)). according to the smb standard (v1.1), the maximum value of low-level input voltage is 0.8 v, and the minimum value of high-level input voltage, 2.1 v. to satisfy these conditions, set lvl01 and lvl00 as follows. ? when v dd = 1.8 to 3.3 v: lvl01, lvl00 = 1, 1 (0.5 v dd ) ? when v dd = 3.3 to 4.5 v: lvl0 1, lvl00 = 1, 0 (0.375 v dd ) ? when v dd = 4.5 to 5.5 v: lvl0 1, lvl00 = 0, 1 (0.25 v dd ) ?lvl01, lvl00 = 0, 0? is not possible since this setting does not satisfy the smb standard (v1.1).
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 360 (c) ac characteristics smb mode standard mode i 2 c bus high-speed mode i 2 c bus parameter symbol min. max. min. max. min. max. unit scl0 clock frequency f clk 10 100 0 100 0 400 khz bus free time (between stop and start condition) t buf 4.7 ? 4.7 ? 1.3 ? s hold time note 1 t hd:sta 4.0 ? 4.0 ? 0.6 ? s start/restart condition setup time t su:sta 4.7 ? 4.7 ? 0.6 ? s stop condition setup time t su:sto 4.0 ? 4.0 ? 0.6 ? s when using cbus- compatible master ? ? 5 ? ? ? s data hold time when using smb/iic bus t hd:dat 300 ? 0 note 2 ? 0 note 2 900 note 3 ns data setup time t su:dat 250 ? 250 ? 100 note 4 ? ns scl0 clock low-level width t low 4.7 ? 4.7 ? 1.3 ? s scl0 clock high-level width t high 4.0 50 4.0 ? 0.6 ? s scl0 and sda0 signal fall time t f ? 300 ? 300 ? 300 ns scl0 and sda0 signal rise time t r ? 1000 ? 1000 ? 300 ns spike pulse width controlled by input filter t sp ? ? ? ? 0 50 ns timeout t timeout 25 35 ? ? ? ? ms total extended time of scl0 clock low-level period (slave) t low:sext ? 25 ? ? ? ? ms total extended time of cumulative clock low-level period (master) t low:mext ? 10 ? ? ? ? ms capacitive load per each bus line cb ? ? ? 400 ? 400 pf notes 1. in the start condition, the first clock pulse is generated after this hold time. 2. to fill in the undefined area of the scl0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the sda0 signal (which is v ihmin . of the scl0 signal). 3. if the device does not extend the scl0 signal low hold time (t low ), only maximum data hold time t hd:dat needs to be fulfilled. 4. the high-speed mode i 2 c bus is available in the smb mode and the standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. ? if the device extends the sc l0 signal low state hold time t su:dat 250 ns ? if the device extends the sc l0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax. + t su:dat = 1000 + 250 = 1250 ns by the smb mode or the standard mode i 2 c bus specification).
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 361 ac timing measurement points (excluding x1 and xt1 inputs) 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd point of measurement clock timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) ti timing 1/f ti t til t tih ti80, ti81
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 362 interrupt input timing intp0 to intp3 t intl t inth reset input timing reset t rsl cpt90 input timing cpt90 t cpl t cph
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 363 serial transfer timing 3-wire serial i/o mode: t kcym t klm t khm sck20 t sikm t ksim t ksom input data output data si20 so20 remark m = 1, 2 3-wire serial i/o mode (when using ss20): t kas2 so20 ss20 output data t kds2 uart mode (external clock input): t kcy3 t kl3 t kh3 asck20 t r t f
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 364 smb mode: t r t low t f t high t hd:sta stop condition start condition restart condition stop condition t buf t su:dat t su:sta t hd:sta t sp t su:sto t hd:dat scl0 sda0 8-bit a/d converter characteristics ( pd78916x, 78916xy, 78916x(a), 78916xy(a)) (t a = ? 40 to +85 c, 1.8 av ref av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit 2.7 av ref av dd 5.5 v 0.4 0.6 %fsr overall error note 1.8 av ref av dd 5.5 v 0.8 1.2 %fsr 4.5 av ref av dd 5.5 v 12 100 s 2.7 av ref av dd 5.5 v 14 100 s conversion time t conv 1.8 av ref av dd 5.5 v 28 100 s analog input voltage v ian 0 av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r adref 20 40 k ? note excludes quantization error ( 0.2%fsr). remark fsr: full scale range
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 365 10-bit a/d converter characteristics ( pd78917x, 78917xy, 78917x(a), 78917xy(a)) (t a = ? 40 to +85 c, 1.8 av ref av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.5 v av ref av dd 5.5 v 0.2 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.4 0.6 %fsr overall error note 1.8 v av ref av dd 5.5 v 0.8 1.2 %fsr 4.5 v av ref av dd 5.5 v 12 100 s 2.7 v av ref av dd 5.5 v 14 100 s conversion time t conv 1.8 v av ref av dd 5.5 v 28 100 s 4.5 v av ref av dd 5.5 v 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.6 %fsr zero-scale error note 1.8 v av ref av dd 5.5 v 1.2 %fsr 4.5 v av ref av dd 5.5 v 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.6 %fsr full-scale error note 1.8 v av ref av dd 5.5 v 1.2 %fsr 4.5 v av ref av dd 5.5 v 2.5 lsb 2.7 v av ref av dd 5.5 v 4.5 lsb integral linearity error note inl 1.8 v av ref av dd 5.5 v 8.5 lsb 4.5 v av ref av dd 5.5 v 1.5 lsb 2.7 v av ref av dd 5.5 v 2.0 lsb differential linearity error note dnl 1.8 v av ref av dd 5.5 v 3.5 lsb analog input voltage v ian 0 av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r adref 20 40 k ? note excludes quantization error ( 0.05%fsr). remark fsr: full scale range
chapter 23 electrical specifications ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 366 data memory stop mode low power supply voltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization time is the time t he cpu operation is stopped to prevent unstable operation when oscillation starts. 2. by using bits 0 to 2 (osts0 to osts2) of the osc illation stabilization time selection register (osts), 2 12 /f x , 2 15 /f x , or 2 17 /f x can be selected. remark f x : main system clock oscillation frequency data retention timing (sto p mode release by reset) v dd stop mode stop instruction execution internal reset operation data retention mode halt mode operating mode t srel t wait v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd t srel t wait v dddr stop mode stop instruction execution standby release signal (interrupt request) data retention mode halt mode operating mode
user?s manual u14186ej5v0ud 367 chapter 24 characteristics curves ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) 10.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 (t a = 25 ? c) i dd vs. v dd (f x = 5.0 mhz, f xt = 32.768 khz) supply voltage v dd (v) supply current i dd (ma) x1 x2 22 pf xt1 xt2 33 pf 220 k ? v ss 22 pf 33 pf v ss main system clock operating mode (pcc1 = 0, css0 = 0) main system clock operating mode (pcc1 = 1, css0 = 0) main system clock operation halt mode (pcc1 = 0, css0 = 0) main system clock operation halt mode (pcc1 = 1, css0 = 0) subsystem clock operating mode (css0 = 1, mcc = 1) crystal resonator 5.0 mhz crystal resonator 32.768 khz subsystem clock operation halt mode (css0 = 1, mcc = 1)
chapter 24 characteristics curves ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 368 10.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 x1 x2 22 pf xt1 xt2 33 pf v ss 22 pf 33 pf v ss i dd vs. v dd (f x = 4.19 mhz, f xt = 32.768 khz) supply voltage v dd (v) supply current i dd (ma) main system clock operating mode (pcc1 = 0, css0 = 0) main system clock operating mode (pcc1 = 1, css0 = 0) main system clock operation halt mode (pcc1 = 0, css0 = 0) main system clock operation halt mode (pcc1 = 1, css0 = 0) subsystem clock operating mode (css0 = 1, mcc = 1) crystal resonator 4.19 mhz crystal resonator 32.768 khz subsystem clock operation halt mode (css0 = 1, mcc = 1) (t a = 25 ? c) 220 k ?
chapter 24 characteristics curves ( pd78916x, 17x, 16xy, 17xy, 16x(a), 17x(a), 16xy(a), 17xy(a)) user?s manual u14186ej5v0ud 369 10.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 012345678 x1 x2 100 pf xt1 xt2 33 pf v ss 100 pf 33 pf v ss i dd vs. v dd (f x = 1.0 mhz, f xt = 32.768 khz) supply voltage v dd (v) supply current i dd (ma) main system clock operating mode (pcc1 = 0, css0 = 0) main system clock operating mode (pcc1 = 1, css0 = 0) main system clock operation halt mode (pcc1 = 0, css0 = 0) main system clock operation halt mode (pcc1 = 1, css0 = 0) subsystem clock operating mode (css0 = 1, mcc = 1) crystal resonator 1.0 mhz crystal resonator 32.768 khz subsystem clock operation halt mode (css0 = 1, mcc = 1) (t a = 25 ? c) 220 k ?
370 user?s manual u14186ej5v0ud chapter 25 electrical specifications ( pd78916x(a1), 17x(a1) , 16x(a2), 17x(a2)) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v av dd v supply voltage av ref av dd ? 0.3 v v dd av dd + 0.3 v av ref av dd + 0.3 v av ref v dd + 0.3 v ? 0.3 to +6.5 v v i1 pins other than p50 to p53, p23, p24 ? 0.3 to v dd + 0.3 v v i2 p23, p24 ? 0.3 to +5.5 v n-ch open drain ? 0.3 to +13 v input voltage v i3 p50 to p53 on-chip pull-up resistor ? 0.3 to v dd + 0.3 v output voltage v o ? 0.3 to v dd + 0.3 v per pin ? 4 ma total for all pins pd78916x(a1), 78917x(a1) ? 14 ma per pin ? 2 ma output current, high i oh total for all pins pd78916x(a2), 78917x(a2) ? 6 ma per pin 5 ma total for all pins pd78916x(a1), 78917x(a1) 80 ma per pin 2 ma output current, low i ol total for all pins pd78916x(a2), 78917x(a2) 40 ma pd78916x(a1), 78917x(a1) ? 40 to +110 c operating ambient temperature t a pd78916x(a2), 78917x(a2) ? 40 to +125 c storage temperature t stg ? 65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, a nd therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 371 main system clock osc illator characteristics (v dd = 4.5 to 5.5 v, t a = ? 40 to +110 c ( pd78916x(a1), 78917x(a1)), = ? 40 to +125 c ( pd78916x(a2), 78917x(a2))) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz ceramic resonator oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 1.0 5.0 mhz external clock x1 input high-/low-level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator that stabilizes oscillation within the oscillation wait time. cautions 1. when using the main system clock osc illator, wire as follows in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss0 . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and th e device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 3. for ceramic resonator, use the part number for which the resonator manufacturer guarantees operation under th e following conditions. pd78916x(a1), 78917x(a1): t a = 110 c pd78916x(a2), 78917x(a2): t a = 125 c remark for the resonator selection and oscillator constant, us ers are requested to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. x1 x2 x1 x2 open c1 x1 x2 c2 v ss0
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 372 subsystem clock oscillator characteristics (v dd = 4.5 to 5.5 v, t a = ? 40 to +110 c ( pd78916x(a1), 78917x(a1)), = ? 40 to +125 c ( pd78916x(a2), 78917x(a2))) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz crystal resonator c4 c3 r v ss0 xt1 xt2 oscillation stabilization time note 2 1.2 2 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 input high-/low-level width (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator that stabilizes oscillation within the oscillation wait time. cautions 1. when using the subsyst em clock oscillator, wire as follo ws in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss0 . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is mo re prone to malfunction due to noise than the ma in system clock oscillator. particular care is therefore required with the wir ing method when the subsystem clock is used. remark for the resonator selection and oscillator constant, us ers are requested to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. xt1 xt2
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 373 dc characteristics (v dd = 4.5 to 5.5 v, t a = ? 40 to +110 c ( pd78916x(a1), 78917x(a1)), = ? 40 to +125 c ( pd78916x(a2), 78917x(a2))) (1/3) parameter symbol conditions min. typ. max. unit per pin ? 1 ma total for all pins pd78916x(a1), 78917x(a1) ? 7 ma per pin ? 1 ma output current , high i oh total for all pins pd78916x(a2), 78917x(a2) ? 3 ma per pin 1.6 ma total for all pins pd78916x(a1), 78917x(a1) 40 ma per pin 1.6 ma output current, low i ol total for all pins pd78916x(a2), 78917x(a2) 20 ma v ih1 p00 to p05, p10, p11, p60 to p67 0.7v dd v dd v n-ch open drain 0.7v dd 10 v v ih2 p50 to p53 on-chip pull-up resistor 0.7v dd v dd v v ih3 reset, p20 to p26, p30 to p33 0.8v dd v dd v input voltage, high v ih4 x1, x2, xt1, xt2 v dd ? 0.1 v dd v v il1 p00 to p05, p10, p11, p60 to p67 0 0.3v dd v v il2 p50 to p53 0 0.3v dd v v il3 reset, p20 to p26, p30 to p33 0 0.2v dd v input voltage, low v il4 x1, x2, xt1, xt2 0 0.1 v i oh = ? 1 ma v dd ? 2.0 v output voltage, high v oh pins other than p23, p24, p50 to p53 i oh = ? 100 a v dd ? 1.0 v i ol = 1.6 ma 2.0 v v ol1 pins other than p50 to p53 i ol = 400 a 1.0 v output voltage, low v ol2 p50 to p53 i ol = 1.6 ma 1.0 v remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 374 dc characteristics (v dd = 4.5 to 5.5 v, t a = ? 40 to +110 c ( pd78916x(a1), 78917x(a1)), = ? 40 to +125 c ( pd78916x(a2), 78917x(a2))) (2/3) parameter symbol conditions min. typ. max. unit i lih1 pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 10 a i lih2 v i = v dd x1, x2, xt1, xt2 20 a input leakage current, high i lih3 v i = 10 v note1 p50 to p53 (n-ch open drain) 80 a i lil1 v i = 0 v pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 ? 10 a i lil2 x1, x2, xt1, xt2 ? 20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) ? 10 note 2 a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ? 10 a software pull-up resistor r 1 v i = 0 v, for pins other than p23, p24, and p50 to p53 50 100 300 k ? pd78916x(a1), 78917x(a1) 15 30 100 k ? mask option pull- up resistor r 2 v i = 0 v, p50 to p53 pd78916x(a2), 78917x(a2) 10 30 100 k ? notes 1. when pull-up resistors are not connected to p50 to p53 (specified by mask option). 2. a low-level input leakage current of ? 60 a (max.) flows only during th e 1-cycle time after a read instruction is executed to p50 to p53 when on-chip pull-up resistors are not connected to p50 to p53 (specified by mask option) and p50 to p53 are set to input mode. at times other than this, a ? 10 a (max.) current flows. remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 375 dc characteristics (v dd = 4.5 to 5.5 v, t a = ? 40 to +110 c ( pd78916x(a1), 78917x(a1)), = ? 40 to +125 c ( pd78916x(a2), 78917x(a2))) (3/3) parameter symbol conditions min. typ. max. unit i dd1 note 1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 5.0 v 10% note 4 2.0 8.0 ma i dd2 note 1 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 5.0 v 10% note 4 1.0 5.0 ma i dd3 note 1 32.768 khz crystal oscillation operating mode note 3 (c3 = c4 = 22 pf, r = 220 k ? ) v dd = 5.0 v 10% 30 1200 a i dd4 note 1 32.768 khz crystal oscillation halt mode note 3 (c3 = c4 = 22 pf, r = 220 k ? ) v dd = 5.0 v 10% 25 1100 a i dd5 note 1 32.768 khz crystal stop stop mode v dd = 5.0 v 10% 0.1 1000 a power supply current i dd6 note 2 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) v dd = 5.0 v 10% note 4 3.0 10.0 ma notes 1. the av ref on (adcs0 (bit 7 of adm0; a/d converter mode register 0) = 1), av dd , and port current (including the current flowing through the inte rnal pull-up resistors) is not included. 2. the av ref on (adcs0 =1) and port current (including the current flowing through the internal pull-up resistors) is not included. refer to the a/d conv erter characteristics for the current flowing through av ref . 3. when the main system clock is stopped. 4. during high-speed mode operation (when the processor clock control register (pcc) is set to 00h.) remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 376 ac characteristics (1) basic operation (v dd = 4.5 to 5.5 v, t a = ? 40 to +110 c ( pd78916x(a1), 78917x(a1)), = ? 40 to +125 c ( pd78916x(a2), 78917x(a2))) parameter symbol conditions min. typ. max. unit operation based on the main system clock 0.4 8 s cycle time (minimum instruction execution time) t cy operation based on the s ubsystem clock 114 122 125 s ti80 and ti81 input frequency f ti 0 4 mhz ti80 and ti81 input high-/low-level width t tih , t til 0.1 s interrupt input high- /low-level width t inth , t intl intp0 to intp3 10 s reset input low- level width t rsl 10 s cpt90 input high- /low-level width t cph , t cpl 10 s t cy vs. v dd (main system clock) supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] operation guaranteed range
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 377 (2) serial interface 20 (v dd = 4.5 to 5.5 v, t a = ? 40 to +110 c ( pd78916x(a1), 78917x(a1)), = ? 40 to +125 c ( pd78916x(a2), 78917x(a2))) (a) 3-wire serial i/o mode (sck20...internal clock) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy1 800 ns sck20 high-/low- level width t kh1 , t kl1 t kcy1 /2 ? 50 ns si20 setup time (to sck20 ) t sik1 150 ns si20 hold time (from sck20 ) t ksi1 400 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note 0 250 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (b) 3-wire serial i/o mode (sck20...external clock) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy2 900 ns sck20 high-/low- level width t kh2 , t kl2 400 ns si20 setup time (to sck20 ) t sik2 100 ns si20 hold time (from sck20 ) t ksi2 400 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note 0 300 ns so20 setup time (when using ss20, to ss20 ) t kas2 120 ns so20 disable time (when using ss20, from ss20 ) t kds2 240 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 78125 bps
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 378 (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck20 cycle time t kcy3 900 ns asck20 high-/low- level width t kh3 , t kl3 400 ns transfer rate 39063 bps asck20 rise time, fall time t r , t f 1 s
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 379 ac timing measurement points (excluding x1 and xt1 inputs) 0.8v dd 0.2v dd point of measurement 0.8v dd 0.2v dd clock timing ti timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) 1/f ti t til t tih ti80, ti81
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 380 interrupt input timing reset input timing reset t rsl cpt90 input timing cpt90 t cpl t cph intp0 to intp3 t intl t inth
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 381 serial transfer timing 3-wire serial i/o mode: remark m = 1, 2 3-wire serial i/o mode (when using ss20): uart mode (external clock input): sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 asck20 t r t f t kl3 t kcy3 t kh3 t kas2 so20 ss20 output data t kds2
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 382 8-bit a/d converter characteristics ( pd78916x(a1), 78916x(a2)) (t a = ? 40 to +110 c ( pd78916x(a1)), ? 40 to +125 c ( pd78916x(a2)) 4.5 av ref av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 8 8 bit overall error note 0.4 1.0 %fsr conversion time t conv 14 28 s analog input voltage v ian 0 av ref v reference voltage av ref 4.5 av dd v resistance between av ref and av ss r adref 20 40 k ? note excludes quantization error ( 0.2%fsr). remark fsr: full scale range 10-bit a/d converter characteristics ( pd78917x(a1), 78917x(a2)) (t a = ? 40 to +110 c ( pd78917x(a1)), ? 40 to +125 c ( pd78917x(a2)) 4.5 av ref av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 0.2 0.6 %fsr conversion time t conv 14 28 s zero-scale error note 0.6 %fsr full-scale error note 0.6 %fsr integral linearity error note inl 4.5 lsb differential linearity error note dnl 2.0 lsb analog input voltage v ian 0 av ref v reference voltage av ref 4.5 av dd v resistance between av ref and av ss r adref 20 40 k ? note excludes quantization error ( 0.05%fsr). remark fsr: full scale range
chapter 25 electrical specifications ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 383 data memory stop mode low power suppl y voltage data retention characteristics (t a = ? 40 to +110 c ( pd78916x(a1), 78917x(a1)), = ? 40 to +125 c ( pd78916x(a2), 78917x(a2))) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 4.5 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization time is the time t he cpu operation is stopped to prevent unstable operation when oscillation starts. 2. 2 12 /f x , 2 15 /f x , or 2 17 /f x can be selected by using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select ion register (osts). remark f x : main system clock oscillation frequency data retention timing (sto p mode release by reset) t wait stop instruction execution stop mode operating mode halt mode reset internal reset operation data retention mode v dddr v dd t srel data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd stop mode halt mode t srel v dddr t wait operating mode data retention mode stop instruction execution standby release signal (interrupt request)
384 user?s manual u14186ej5v0ud chapter 26 characteristics curves ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) 10.0 i dd vs. v dd (fx = 5.0 mhz, f xt = 32.768 khz) 1.0 0.5 0.1 0.05 0.01 0.005 0.001 01234 supply voltage v dd (v) supply current i dd (ma) 5678 (t a = 25 c) subsystem clock operation halt mode (css0 = 1, mcc = 1) subsystem clock operating mode (css0 = 1, mcc = 1) main system clock operating mode (pcc1 = 0, css0 = 0) main system clock operating mode (pcc1 = 1, css0 = 0) main system clock operation halt mode (pcc1 = 1, css0 = 0) main system clock operation halt mode (pcc1 = 0, css0 = 0) 33 pf 220 k ? v ss 22 pf 33 pf v ss 22 pf crystal resonator 5.0 mhz crystal resonator 32.768 khz x1 x2 xt1 xt2
chapter 26 characteristics curves ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 385 10.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 01234 supply voltage v dd (v) supply voltage i dd (ma) 5678 (t a = 25 c) main system clock operating mode (pcc1 = 0, css0 = 0) subsystem clock operation halt mode (css0 = 1, mcc = 1) subsystem clock operating mode (css0 = 1, mcc = 1) main system clock operation halt mode (pcc1 = 1, css0 = 0) main system clock operation halt mode (pcc1 = 0, css0 = 0) main system clock operating mode (pcc1 = 1, css0 = 0) x1 x2 xt1 xt2 33 pf 220 k ? v ss 22 pf 33 pf v ss 22 pf crystal resonator 4.19 mhz crystal resonator 32.768 khz i dd vs. v dd (fx = 4.19 mhz, f xt = 32.768 khz)
chapter 26 characteristics curves ( pd78916x(a1), 17x(a1), 16x(a2), 17x(a2)) user?s manual u14186ej5v0ud 386 10.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 01234 supply voltage v dd (v) supply current i dd (ma) 5678 (t a = 25 c) subsystem clock operation halt mode (css0 = 1, mcc = 1) subsystem clock operating mode (css0 = 1, mcc = 1) main system clock operating mode (pcc1 = 1, css0 = 0) main system clock operation halt mode (pcc1 = 1, css0 = 0) x1 x2 xt1 xt2 33 pf 220 k ? v ss 100 pf 33 pf v ss 100 pf main system clock operation halt mode (pcc1 = 0, css0 = 0) main system clock operating mode (pcc1 = 0, css0 = 0) crystal resonator 1.0 mhz crystal resonator 32.768 khz i dd vs. v dd (fx = 1.0 mhz, f xt = 32.768 khz)
user?s manual u14186ej5v0ud 387 chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v av dd v av ref av dd ? 0.3 v v dd av dd + 0.3 v av ref av dd + 0.3 v av ref v dd + 0.3 v ? 0.3 to +6.5 v supply voltage v pp note ? 0.3 to +10.5 v v i1 pins other than p50 to p53, p23, p24 ? 0.3 to v dd + 0.3 v v i2 p23, p24 ? 0.3 to +5.5 v input voltage v i3 p50 to p53 ? 0.3 to +13 v output voltage v o ? 0.3 to v dd + 0.3 v per pin ? 10 ma output current, high i oh total for all pins pd78f9177a, pd78f9177ay ? 30 ma per pin ? 7 ma total for all pins pd78f9177a(a), pd78f9177ay(a) ? 22 ma per pin 30 ma output current, low i ol total for all pins pd78f9177a, pd78f9177ay 160 ma per pin 10 ma total for all pins pd78f9177a(a), pd78f9177ay(a) 120 ma in normal operation mode ? 40 to +85 c operating ambient temperature t a during flash memory programming +10 to +40 c storage temperature t stg ? 40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (1.8 v) of the operating voltage range (see a in the figure below). when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.8 v) of the operating voltage range of v dd (see b in the figure below). caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, a nd therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins. 1.8 v v dd 0 v 0 v v pp 1.8 v a b
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 388 main system clock osc illator characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit v dd = 4.5 to 5.5 v 1.0 10.0 mhz v dd = 3.0 to 5.5 v 1.0 6.0 mhz oscillation frequency (f x ) note 1 v dd = 1.8 to 5.5 v 1.0 5.0 mhz ceramic resonator c1 x1 x2 c2 v ss0 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms v dd = 4.5 to 5.5 v 1.0 10.0 mhz v dd = 3.0 to 5.5 v 1.0 6.0 mhz oscillation frequency (f x ) note 1 v dd = 1.8 to 5.5 v 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator c1 x1 x2 c2 v ss0 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 ms v dd = 4.5 to 5.5 v 1.0 10.0 mhz v dd = 3.0 to 5.5 v 1.0 6.0 mhz x1 input frequency (f x ) note 1 v dd = 1.8 to 5.5 v 1.0 5.0 mhz v dd = 4.5 to 5.5 v 45 500 ns v dd = 3.0 to 5.5 v 75 500 ns x1 input high-/low-level width (t xh , t xl ) v dd = 1.8 to 5.5 v 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator that stabilizes oscillation within the oscillation wait time. cautions 1. when using the main system clock osc illator, wire as follows in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss0 . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and th e device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to th e main system clock. x1 x2 x1 x2 open
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 389 recommended oscillator constant ( pd78f9177a and 78f9177ay) ceramic resonator (t a = ?40 to +85c) recommended circuit constant (pf) oscillation voltage range (v dd ) manufacturer part number frequency (mhz) c1 c2 min. max. remarks csbla1m00j58-b0 csbfb1m00j58-r1 1.000 150 150 2.4 5.5 without on-chip capacitor cstcc2m00g56-r0 cstls2m00g56-b0 2.000 cstcr4m00g53-r0 1.8 5.5 cstls4m00g53-b0 4.000 1.9 5.5 cstcr4m19g53-r0 1.8 5.5 cstls4m19g53-b0 4.195 cstcr4m91g53-r0 1.9 5.5 cstls4m91g53-b0 4.915 2.1 5.5 cstcr5m00g53-r0 1.9 5.5 cstls5m00g53-b0 5.000 2.1 5.5 cstcr6m00g53-r0 1.9 5.5 cstls6m00g53-b0 6.000 2.1 5.5 cstce8m00g52-r0 1.8 5.5 cstls8m00g53-b0 8.000 2.0 5.5 cstce8m38g52-r0 1.8 5.5 cstls8m38g53-b0 8.388 cstce10m0g52-r0 2.0 5.5 murata mfg. co., ltd. (standard type) cstls10m0g53-b0 10.000 ? ? 2.2 5.5 with on-chip capacitor cstls4m00g53093-b0 4.000 cstls4m19g53093-b0 4.195 cstcr4m91g53093-r0 cstls4m91g53u-b0 4.915 cstcr5m00g53093-r0 cstls5m00g53u-b0 5.000 cstcr6m00g53093-r0 cstls6m00g53u-b0 6.000 cstls8m00g53u-b0 8.000 cstls8m38g53u-b0 8.388 murata mfg. co., ltd. (low-voltage drive type) cstls10m0g53u-b0 10.000 ? ? 1.8 5.5 with on-chip capacitor caution the oscillator constant is a reference value based on evaluati on in specific environments by the resonator manufacturer. if th e oscillator characteri stics need to be optimized in the actual application, request the resona tor manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the intern al operation conditions of the pd78f9177a and 78f9177ay within the specifications of the dc and ac characteristics.
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 390 recommended oscillator constant ( pd78f9177a(a) and 78f9177ay(a)) ceramic resonator (t a = ?40 to +85c) recommended circuit constant (pf) oscillation voltage range (v dd ) manufacturer part number frequency (mhz) c1 c2 min. max. remarks cstcc2m00g56a-r0 2.000 cstcr4m00g53a-r0 4.000 cstcr4m19g53a-r0 4.195 1.8 5.5 cstcr4m91g53a-r0 4.915 cstcr5m00g53a-r0 5.000 cstcr6m00g53a-r0 6.000 1.9 5.5 cstce8m00g52a-r0 8.000 cstce8m38g52a-r0 8.388 1.8 5.5 murata mfg. co., ltd. (standard type) cstce10m0g52a-r0 10.000 ? ? 2.0 5.5 with on-chip capacitor cstcr4m91g53a093-r0 4.915 cstcr5m00g53a093-r0 5.000 murata mfg. co., ltd. (low-voltage drive type) cstcr6m00g53a093-r0 6.000 ? ? 1.8 5.5 with on-chip capacitor caution the oscillator constant is a reference value based on evaluati on in specific environments by the resonator manufacturer. if th e oscillator characteri stics need to be optimized in the actual application, request the resona tor manufacturer for evaluation on the implementation circuit. note that the oscillation voltage and oscillation frequency merely indicate the characteristics of the oscillator. use the intern al operation conditions of the pd78f9177a(a) and 78f9177ay(a) within the specifications of the dc and ac characteristics.
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 391 subsystem clock oscillator characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz v dd = 4.5 to 5.5 v 1.2 2 s crystal resonator c4 c3 r v ss0 xt1 xt2 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 input high-/low-level width (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator that stabilizes oscillation within the oscillation stabilization wait time. cautions 1. when using the subsyst em clock oscillator, wire as follo ws in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss0 . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is mo re prone to malfunction due to noise than the ma in system clock oscillator. particular care is therefore required with the wir ing method when the subsystem clock is used. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. xt1 xt2
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 392 dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin ? 1 ma total for all pins pd78f9177a, pd78f9177ay ? 15 ma per pin ? 1 ma output current , high i oh total for all pins pd78f9177a(a), pd78f9177ay(a) ? 11 ma per pin 10 ma total for all pins pd78f9177a, pd78f9177ay 80 ma per pin 3 ma output current, low i ol total for all pins pd78f9177a(a), pd78f9177ay(a) 60 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 p00 to p05, p10, p11,p60 to p67 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v v ih2 p50 to p53 v dd = 1.8 to 5.5 v 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p20 to p26, p30 to p33 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 p00 to p05, p10, p11, p60 to p67 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset,p20 to p26, p30 to p33 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v 0 0.1 v v dd = 4.5 to 5.5 v, i oh = ? 1 ma v dd ? 1.0 v output voltage, high v oh pins other than p23, p24, p50 to p53 v dd = 1.8 to 5.5 v, i oh = ? 100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78f9177a, pd78f9177ay) v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78f9177(a), pd78f9177ay(a)) 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma ( pd78f9177a, pd78f9177ay) v dd = 4.5 to 5.5 v, i ol = 3 ma ( pd78f9177(a), pd78f9177ay(a)) 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v i lih1 pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 3 a i lih2 v i = v dd x1, x2, xt1, xt2 20 a input leakage current, high i lih3 v i = 12 v p50 to p53 (n-ch open drain) 20 a i lil1 pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 ? 3 a i lil2 x1, x2, xt1, xt2 ? 20 a input leakage current, low i lil3 v i = 0 v p50 to p53 (n-ch open drain) ? 3 note a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ? 3 a software pull-up resistor r 1 v i = 0 v, for pins other than p23, p24, and p50 to p53 50 100 200 k ? note a low-level input leakage current of ? 60 a (max.) flows only during the 1-cycle time after a read instruction is executed to p50 to p53 and p50 to p53 are set to input mode. at times other than this, ? 3 a (max.) current flows. remark unless otherwise specified, the characteristics of al ternate-function pins are the same as those of port pins.
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 393 dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit 10.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 4 10.0 20.0 ma 6.0 mhz crystal oscillation operating mode v dd = 5.0 v 10% note 4 6.0 12.0 ma v dd = 5.0 v 10% note 4 5.0 10.0 ma v dd = 3.0 v 10% note 5 1.2 2.5 ma i dd1 note 1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 1.0 2.0 ma 10.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 4 1.2 6.0 ma 6.0 mhz crystal oscillation halt mode v dd = 5.0 v 10% note 4 0.9 2.8 ma v dd = 5.0 v 10% note 4 0.8 2.5 ma v dd = 3.0 v 10% note 5 0.4 2.0 ma i dd2 note 1 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.25 1.5 ma v dd = 5.0 v 10% 100 320 a v dd = 3.0 v 10% 80 240 a i dd3 note 1 32.768 khz crystal oscillation operating mode note 3 (c3 = c4 = 22 pf, r = 220 k ? ) v dd = 2.0 v 10% 65 210 a v dd = 5.0 v 10% 18 120 a v dd = 3.0 v 10% 5.0 50 a i dd4 note 1 32.768 khz crystal oscillation halt mode note 3 (c3 = c4 = 22 pf, r = 220 k ? ) v dd = 2.0 v 10% 2.5 30 a v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a i dd5 note 1 32.768 khz crystal stop stop mode v dd = 2.0 v 10% 0.05 10 a 10.0 mhz crystal oscillation a/d operating mode v dd = 5.0 v 10% note 4 10.8 22.0 ma 6.0 mhz crystal oscillation a/d operating mode v dd = 5.0 v 10% note 4 6.8 14.0 ma v dd = 5.0 v 10% note 4 5.8 12.0 ma v dd = 3.0 v 10% note 5 2.0 4.5 ma power supply current i dd6 note 2 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 1.8 4.0 ma notes 1. the av ref on (adcs0 (bit 7 of adm0; a/d converter mode register 0) = 1), av dd , and the port current (including the current flowing through the inte rnal pull-up resistors) are not included. 2. the av ref on (adcs0 =1) and port current (including the current flowing through the internal pull-up resistors) are not included. refer to the a/d conv erter characteristics for the current flowing through av ref . 3. when the main system clock is stopped. 4. during high-speed mode operation (when the processor clock control register (pcc) is set to 00h.) 5. during low-speed mode operation (when pcc is set to 02h) remark unless otherwise specified, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 394 ac characteristics (1) basic operation (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 4.5 to 5.5 v 0.2 8 s v dd = 3.0 to 5.5 v 0.333 8 s v dd = 2.7 to 5.5 v 0.4 8 s operation based on the main system clock v dd = 1.8 to 5.5 v 1.6 8 s cycle time (minimum instruction execution time) t cy operation based on the s ubsystem clock 114 122 125 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 and ti81 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz v dd = 2.7 to 5.5 v 0.1 s ti80 and ti81 input high-/low-level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s interrupt input high- /low-level width t inth , t intl intp0 to intp3 10 s reset input low- level width t rsl 10 s cpt90 input high- /low-level width t cph , t cpl 10 s t cy vs. v dd (main system clock) 123456 0.1 0.4 1.0 10 60 supply voltage v dd [v] cycle time t cy [ s] operation guaranteed range
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 395 (2) serial interface sio20 (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck20...internal clock) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (b) 3-wire serial i/o mode (sck20...external clock) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3500 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (when using ss20, to ss20 ) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (when using ss20, from ss20 ) t kds2 v dd = 1.8 to 5.5 v 800 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 396 (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3500 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise time, fall time t r , t f 1 s
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 397 (3) serial interface smb0 (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) ( pd78f9177ay, 78f9177ay(a) only) (a) dc characteristics parameter symbol conditions min. typ. max. unit input voltage, high v ih scl0, sda0 (at hysteresis) 0.8v dd v dd v input voltage, low v il scl0, sda0 (at hysteresis) 0 0.2v dd v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol scl0, sda0 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v input leakage current, high i lih scl0, sda0 v i = v dd 3 a input leakage current, low i lil scl0, sda0 v i = 0 v ? 3 a (b) dc characteristics (when using comparator) parameter symbol conditions min. typ. max. unit input range v sda , v scl v dd = 1.8 to 5.5 v 0 5.5 v 4.5 v dd 5.5 v 0.72v ismb v ismb 1.28v ismb v 3.3 v dd < 4.5 v 0.78v ismb v ismb 1.22v ismb v 2.7 v dd < 3.3 v 0.75v ismb v ismb 1.25v ismb v transfer level v isda , v iscl 1.8 v dd < 2.7 v 0.90v ismb v ismb 1.45v ismb v lvl01, lvl00 = 0, 1 0.25 v dd v lvl01, lvl00 = 1, 0 0.375 v dd v input level threshold value note v ismb lvl01, lvl00 = 1, 1 0.5 v dd v note v ismb is an input level threshold value selected by bits lvl00 and lvl01 (bits 0 and 1 of smb input level setting register 0 (smbvi0)). according to the smb standard (v1.1), the maximum value of low-level input voltage is 0.8 v, and the minimum value of high-level input voltage, 2.1 v. to satisfy these conditions, set lvl01 and lvl00 as follows; ? when v dd = 1.8 to 3.3 v: lvl01, lvl00 = 1, 1 (0.5 v dd ) ? when v dd = 3.3 to 4.5 v: lvl0 1, lvl00 = 1, 0 (0.375 v dd ) ? when v dd = 4.5 to 5.5 v: lvl0 1, lvl00 = 0, 1 (0.25 v dd ) ?lvl01, lvl00 = 0, 0? is not available since th is setting does not satisfy the smb standard (v1.1).
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 398 (c) ac characteristics smb mode standard mode i 2 c bus high-speed mode i 2 c bus parameter symbol min. max. min. max. min. max. unit scl0 clock frequency f clk 10 100 0 100 0 400 khz bus free time (between stop and start condition) t buf 4.7 ? 4.7 ? 1.3 ? s hold time note 1 t hd:sta 4.0 ? 4.0 ? 0.6 ? s start/restart condition setup time t su:sta 4.7 ? 4.7 ? 0.6 ? s stop condition setup time t su:sto 4.0 ? 4.0 ? 0.6 ? s when using cbus- compatible master ? ? 5 ? ? ? s data hold time when using smb/iic bus t hd:dat 300 ? 0 note 2 ? 0 note 2 900 note 3 ns data setup time t su:dat 250 ? 250 ? 100 note 4 ? ns scl0 clock low-level width t low 4.7 ? 4.7 ? 1.3 ? s scl0 clock high-level width t high 4.0 50 4.0 ? 0.6 ? s scl0 and sda0 signal fall time t f ? 300 ? 300 ? 300 ns scl0 and sda0 signal rise time t r ? 1000 ? 1000 ? 300 ns spike pulse width controlled by input filter t sp ? ? ? ? 0 50 ns timeout t timeout 25 35 ? ? ? ? ms total extended time of scl0 clock low-level period (slave) t low:sext ? 25 ? ? ? ? ms total extended time of cumulative clock low-level period (master) t low:mext ? 10 ? ? ? ? ms capacitive load per each bus line cb ? ? ? 400 ? 400 pf notes 1. in the start condition, the first clock pulse is generated after this hold time. 2. to fill in the undefined area of the scl0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the sda0 signal (which is v ihmin . of the scl0 signal). 3. if the device does not extend the scl0 signal low hold time (t low ), only maximum data hold time t hd:dat needs to be fulfilled. 4. the high-speed mode i 2 c bus is available in the smb mode and the standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. ? if the device extends the scl0 signal low state hold time t su:dat 250 ns ? if the device extends the scl0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax. + t su:dat = 1000 + 250 = 1250 ns by the smb mode or the standard mode i 2 c bus specification).
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 399 ac timing measurement points (excluding x1 and xt1 inputs) clock timing ti timing 0.8 v dd 0.2 v dd point of measurement 0.8 v dd 0.2 v dd 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) 1/f ti t til t tih ti80, ti81
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 400 interrupt input timing reset input timing reset t rsl cpt90 input timing cpt90 t cpl t cph intp0 to intp3 t intl t inth
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 401 serial transfer timing 3-wire serial i/o mode: remark m = 1, 2 3-wire serial i/o mode (when using ss20): uart mode (external clock input): sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 asck20 t r t f t kl3 t kcy3 t kh3 t kas2 so20 ss20 output data t kds2
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 402 smb mode: t r t low t f t high t hd:sta stop condition start condition restart condition stop condition t buf t su:dat t su:sta t hd:sta t sp t su:sto t hd:dat scl0 sda0
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 403 10-bit a/d converter characteristics (t a = ? 40 to +85 c, 1.8 av ref av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.5 v av ref av dd 5.5 v 0.2 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.4 0.6 %fsr overall error note 1.8 v av ref av dd 5.5 v 0.8 1.2 %fsr 4.5 v av ref av dd 5.5 v 12 100 s 2.7 v av ref av dd 5.5 v 14 100 s conversion time t conv 1.8 v av ref av dd 5.5 v 28 100 s 4.5 v av ref av dd 5.5 v 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.6 %fsr zero-scale error note 1.8 v av ref av dd 5.5 v 1.2 %fsr 4.5 v av ref av dd 5.5 v 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.6 %fsr full-scale error note 1.8 v av ref av dd 5.5 v 1.2 %fsr 4.5 v av ref av dd 5.5 v 2.5 lsb 2.7 v av ref av dd 5.5 v 4.5 lsb integral linearity error note inl 1.8 v av ref av dd 5.5 v 8.5 lsb 4.5 v av ref av dd 5.5 v 1.5 lsb 2.7 v av ref av dd 5.5 v 2.0 lsb differential linearity error note dnl 1.8 v av ref av dd 5.5 v 3.5 lsb analog input voltage v ian 0 av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r adref 20 40 k ? note excludes quantization error ( 0.05%fsr). remark fsr: full scale range
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 404 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit write current (v dd pin) note 1 i ddw when v pp supply voltage = v pp1 (5.0 mhz operation) 23 ma write current (v pp pin) i ppw when v pp supply voltage = v pp1 20 ma erase current (v dd pin) note 1 i dde when v pp supply voltage = v pp1 (5.0 mhz operation) 23 ma erase current (v pp pin) i ppe when v pp supply voltage = v pp1 100 ma unit erase time note 2 t er 0.2 0.2 0.2 s total erase time t era 20 s write count note 3 erase/write is regarded as 1 cycle 20 20 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v notes 1. the current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and av dd current are not included. 2. the prewrite time before erasure and the erase verify time (writeback time) is not included. 3. when a product is first written after shipment, ?erase write? is taken as one rewrite. data memory stop mode low power supply voltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization time is the time the cpu operation is st opped to prevent unstable operation when oscillation starts. 2. by using bits 0 to 2 (osts0 to osts2) of the o scillation stabilization time selection register (osts), 2 12 /f x , 2 15 /f x , or 2 17 /f x can be selected. remark f x : main system clock oscillation frequency
chapter 27 electrical specifications ( pd78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a)) user?s manual u14186ej5v0ud 405 data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14186ej5v0ud 406 chapter 28 electrical specifications ( pd78f9177, 78f9177y) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v av dd v av ref av dd ? 0.3 v v dd av dd + 0.3 v av ref av dd + 0.3 v av ref v dd + 0.3 v ? 0.3 to +6.5 v supply voltage v pp note ? 0.3 to +10.5 v v i1 pins other than p50 to p53, p23, p24 ? 0.3 to v dd + 0.3 v v i2 p23, p24 ? 0.3 to +5.5 v input voltage v i3 p50 to p53 ? 0.3 to +13 v output voltage v o ? 0.3 to v dd + 0.3 v per pin ? 10 ma output current, high i oh total for all pins ? 30 ma per pin 30 ma output current, low i ol total for all pins 160 ma in normal operation mode ? 40 to +85 c operating ambient temperature t a during flash memory programming +10 to +40 c storage temperature t stg ? 40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (1.8 v) of the operating voltage range (see a in the figure below). when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (1.8 v) of the operating voltage range of v dd (see b in the figure below). 1.8 v v dd 0 v 0 v v pp 1.8 v a b caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, a nd therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 407 main system clock osc illator characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz ceramic resonator c1 x1 x2 c2 v ss0 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms oscillation frequency (f x ) note 1 1.0 5.0 mhz v dd = 4.5 to 5.5 v 10 ms crystal resonator c1 x1 x2 c2 v ss0 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 30 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 v dd = 2.7 to 5.5 v 1.0 5.0 mhz external clock x1 input high-/low-level width (t xh , t xl ) v dd = 2.7 to 5.5 v 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator that stabilizes oscillation within the oscillation wait time. cautions 1. when using the main system clock osc illator, wire as follows in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss0 . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and th e device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. x1 x2 x1 x2 open
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 408 subsystem clock oscillator characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz v dd = 4.5 to 5.5 v 1.2 2 s crystal resonator c4 c3 r v ss0 xt1 xt2 oscillation stabilization time note 2 v dd = 1.8 to 5.5 v 10 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 input high-/low-level width (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator that stabilizes oscillation within the oscillation stabilization wait time. cautions 1. when using the subsyst em clock oscillator, wire as follo ws in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss0 . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is mo re prone to malfunction due to noise than the ma in system clock oscillator. particular care is therefore required with the wir ing method when the subsystem clock is used. remark for the resonator selection and oscillator constan t, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. xt1 xt2
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 409 dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (1/2) parameter symbol conditions min. typ. max. unit per pin ? 1 ma output current , high i oh total for all pins ? 15 ma per pin 10 ma output current, low i ol total for all pins 80 ma v dd = 2.7 to 5.5 v 0.7v dd v dd v v ih1 p00 to p05, p10, p11,p60 to p67 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 2.7 to 5.5 v 0.7v dd 12 v v ih2 p50 to p53 v dd = 1.8 to 5.5 v, t a = 25 to +85 c 0.9v dd 12 v v dd = 2.7 to 5.5 v 0.8v dd v dd v v ih3 reset, p20 to p26, p30 to p33 v dd = 1.8 to 5.5 v 0.9v dd v dd v v dd = 4.5 to 5.5 v v dd ? 0.5 v dd v input voltage, high v ih4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v v dd ? 0.1 v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il1 p00 to p05, p10, p11, p60 to p67 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.3v dd v v il2 p50 to p53 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 2.7 to 5.5 v 0 0.2v dd v v il3 reset,p20 to p26, p30 to p33 v dd = 1.8 to 5.5 v 0 0.1v dd v v dd = 4.5 to 5.5 v 0 0.4 v input voltage, low v il4 x1, x2, xt1, xt2 v dd = 1.8 to 5.5 v 0 0.1 v v dd = 4.5 to 5.5 v, i oh = ? 1 ma v dd ? 1.0 v output voltage, high v oh pins other than p23, p24, p50 to p53 v dd = 1.8 to 5.5 v, i oh = ? 100 a v dd ? 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v v ol1 pins other than p50 to p53 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol2 p50 to p53 v dd = 1.8 to 5.5 v, i ol = 1.6 ma 0.4 v i lih1 pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 3 a i lih2 v i = v dd x1, x2, xt1, xt2 20 a input leakage current, high i lih3 v i = 12 v p50 to p53 (n-ch open drain) 20 a i lil1 pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 ? 3 a i lil2 x1, x2, xt1, xt2 ? 20 a input leakage current, low i lil3 v i = 0 v p50 to p53 (n-ch open drain) ? 3 note a output leakage current, high i loh v o = v dd 3 a output leakage current, low i lol v o = 0 v ? 3 a software pull-up resistor r 1 v i = 0 v, for pins other than p23, p24, and p50 to p53 50 100 200 k ? note a low-level input leakage current of ? 60 a (max.) flows only during the 1-cycle time after a read instruction is executed to p50 to p53 and p50 to p53 are set to input mode. at times other than this, a ? 3 a (max.) current flows. remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 410 dc characteristics (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (2/2) parameter symbol conditions min. typ. max. unit v dd = 5.0 v 10% note 4 5.0 15.0 ma v dd = 3.0 v 10% note 5 2.0 5.0 ma i dd1 note 1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 1.5 3.0 ma v dd = 5.0 v 10% note 4 2.0 6.0 ma v dd = 3.0 v 10% note 5 1.0 2.5 ma i dd2 note 1 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 0.75 1.5 ma v dd = 5.0 v 10% 250 750 a v dd = 3.0 v 10% 200 600 a i dd3 note 1 32.768 khz crystal oscillation operating mode note 3 (c3 = c4 = 22 pf, r = 220 k ? ) v dd = 2.0 v 10% 150 450 a v dd = 5.0 v 10% 50 150 a v dd = 3.0 v 10% 30 90 a i dd4 note 1 32.768 khz crystal oscillation halt mode note 3 (c3 = c4 = 22 pf, r = 220 k ? ) v dd = 2.0 v 10% 20 60 a v dd = 5.0 v 10% 0.1 30 a v dd = 3.0 v 10% 0.05 10 a i dd5 note 1 32.768 khz crystal stop stop mode v dd = 2.0 v 10% 0.05 10 a v dd = 5.0 v 10% note 4 6.0 17.0 ma v dd = 3.0 v 10% note 5 3.0 7.0 ma power supply current i dd6 note 2 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) v dd = 2.0 v 10% note 5 2.5 5.0 ma notes 1. the av ref on (adcs0 (bit 7 of adm0; a/d converter mode register 0) = 1), av dd , and the port current (including the current flowing through the inte rnal pull-up resistors) are not included. 2. the av ref on (adcs0 =1) and port current (including the current flowing through the internal pull-up resistors) are not included. refer to the a/d conv erter characteristics for the current flowing through av ref . 3. when the main system clock is stopped. 4. during high-speed mode operation (when the processor clock control register (pcc) is set to 00h.) 5. during low-speed mode operation (when pcc is set to 02h) remark unless otherwise specified, the characteristics of alte rnate-function pins are t he same as those of port pins.
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 411 ac characteristics (1) basic operation (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 0.4 8 s operation based on the main system clock v dd = 1.8 to 5.5 v 1.6 8 s cycle time (minimum instruction execution time) t cy operation based on the s ubsystem clock 114 122 125 s v dd = 2.7 to 5.5 v 0 4 mhz ti80 and ti81 input frequency f ti v dd = 1.8 to 5.5 v 0 275 khz v dd = 2.7 to 5.5 v 0.1 s ti80 and ti81 input high-/low-level width t tih , t til v dd = 1.8 to 5.5 v 1.8 s interrupt input high- /low-level width t inth , t intl intp0 to intp3 10 s reset input low- level width t rsl 10 s cpt90 input high- /low-level width t cph , t cpl 10 s t cy vs. v dd (main system clock) supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] guaranteed operation range
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 412 (2) serial interface sio20 (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) (a) 3-wire serial i/o mode (sck20...internal clock) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 800 ns sck20 cycle time t kcy1 v dd = 1.8 to 5.5 v 3200 ns v dd = 2.7 to 5.5 v t kcy1 /2 ? 50 ns sck20 high-/low- level width t kh1 , t kl1 v dd = 1.8 to 5.5 v t kcy1 /2 ? 150 ns v dd = 2.7 to 5.5 v 150 ns si20 setup time (to sck20 ) t sik1 v dd = 1.8 to 5.5 v 500 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi1 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 250 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (b) 3-wire serial i/o mode (sck20...external clock) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns sck20 cycle time t kcy2 v dd = 1.8 to 5.5 v 3500 ns v dd = 2.7 to 5.5 v 400 ns sck20 high-/low- level width t kh2 , t kl2 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 100 ns si20 setup time (to sck20 ) t sik2 v dd = 1.8 to 5.5 v 150 ns v dd = 2.7 to 5.5 v 400 ns si20 hold time (from sck20 ) t ksi2 v dd = 1.8 to 5.5 v 600 ns v dd = 2.7 to 5.5 v 0 300 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note v dd = 1.8 to 5.5 v 0 1000 ns v dd = 2.7 to 5.5 v 120 ns so20 setup time (when using ss20, to ss20 ) t kas2 v dd = 1.8 to 5.5 v 400 ns v dd = 2.7 to 5.5 v 240 ns so20 disable time (when using ss20, from ss20 ) t kds2 v dd = 1.8 to 5.5 v 800 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 78125 bps transfer rate v dd = 1.8 to 5.5 v 19531 bps
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 413 (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit v dd = 2.7 to 5.5 v 900 ns asck20 cycle time t kcy3 v dd = 1.8 to 5.5 v 3500 ns v dd = 2.7 to 5.5 v 400 ns asck20 high-/low- level width t kh3 , t kl3 v dd = 1.8 to 5.5 v 1600 ns v dd = 2.7 to 5.5 v 39063 bps transfer rate v dd = 1.8 to 5.5 v 9766 bps asck20 rise time, fall time t r , t f 1 s
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 414 (3) serial interface smb0 (t a = ? 40 to +85 c, v dd = 1.8 to 5.5 v) ( pd78f9177y only) (a) dc characteristics parameter symbol conditions min. typ. max. unit input voltage, high v ih scl0, sda0 (at hysteresis) 0.8v dd v dd v input voltage, low v il scl0, sda0 (at hysteresis) 0 0.2v dd v v dd = 4.5 to 5.5 v, i ol = 10 ma 1.0 v output voltage, low v ol scl0, sda0 v dd = 1.8 to 5.5 v, i ol = 400 a 0.5 v input leakage current, high i lih scl0, sda0 v i = v dd 3 a input leakage current, low i lil scl0, sda0 v i = 0 v ? 3 a (b) dc characteristics (when using comparator) parameter symbol conditions min. typ. max. unit input range v sda , v scl v dd = 1.8 to 5.5 v 0 5.5 v 4.5 v dd 5.5 v 0.72v ismb v ismb 1.28v ismb v 3.3 v dd < 4.5 v 0.78v ismb v ismb 1.22v ismb v 2.7 v dd < 3.3 v 0.75v ismb v ismb 1.25v ismb v transfer level v isda , v iscl 1.8 v dd < 2.7 v 0.90v ismb v ismb 1.45v ismb v lvl01, lvl00 = 0, 1 0.25 v dd v lvl01, lvl00 = 1, 0 0. 375 v dd v input level threshold value note v ismb lvl01, lvl00 = 1, 1 0.5 v dd v note v ismb is an input level threshold value selected by bits lvl00 and lvl01 (bits 0 and 1 of smb input level setting register 0 (smbvi0)). according to the smb standard (v1.1), the maximum value of low-level input voltage is 0.8 v, and the minimum value of high-level input voltage, 2.1 v. to satisfy these conditions, set lvl01 and lvl00 as follows; ? when v dd = 1.8 to 3.3 v: lvl01, lvl00 = 1, 1 (0.5 v dd ) ? when v dd = 3.3 to 4.5 v: lvl0 1, lvl00 = 1, 0 (0.375 v dd ) ? when v dd = 4.5 to 5.5 v: lvl0 1, lvl00 = 0, 1 (0.25 v dd ) ?lvl01, lvl00 = 0, 0? is not available since th is setting does not satisfy the smb standard (v1.1).
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 415 (c) ac characteristics smb mode standard mode i 2 c bus high-speed mode i 2 c bus parameter symbol min. max. min. max. min. max. unit scl0 clock frequency f clk 10 100 0 100 0 400 khz bus free time (between stop and start condition) t buf 4.7 ? 4.7 ? 1.3 ? s hold time note 1 t hd:sta 4.0 ? 4.0 ? 0.6 ? s start/restart condition setup time t su:sta 4.7 ? 4.7 ? 0.6 ? s stop condition setup time t su:sto 4.0 ? 4.0 ? 0.6 ? s when using cbus- compatible master ? ? 5 ? ? ? s data hold time when using smb/iic bus t hd:dat 300 ? 0 note 2 ? 0 note 2 900 note 3 ns data setup time t su:dat 250 ? 250 ? 100 note 4 ? ns scl0 clock low-level width t low 4.7 ? 4.7 ? 1.3 ? s scl0 clock high-level width t high 4.0 50 4.0 ? 0.6 ? s scl0 and sda0 signal fall time t f ? 300 ? 300 ? 300 ns scl0 and sda0 signal rise time t r ? 1000 ? 1000 ? 300 ns spike pulse width controlled by input filter t sp ? ? ? ? 0 50 ns timeout t timeout 25 35 ? ? ? ? ms total extended time of scl0 clock low-level period (slave) t low:sext ? 25 ? ? ? ? ms total extended time of cumulative clock low-level period (master) t low:mext ? 10 ? ? ? ? ms capacitive load per each bus line cb ? ? ? 400 ? 400 pf notes 1. in the start condition, the first clock pulse is generated after this hold time. 2. to fill in the undefined area of the scl0 falling edge, it is necessary for the device to internally provide at least 300 ns of hold time for the sda0 signal (which is v ihmin . of the scl0 signal). 3. if the device does not extend the scl0 signal low hold time (t low ), only maximum data hold time t hd:dat needs to be fulfilled. 4. the high-speed mode i 2 c bus is available in the smb mode and the standard mode i 2 c bus system. at this time, the conditions described below must be satisfied. ? if the device extends the scl0 signal low state hold time t su:dat 250 ns ? if the device extends the scl0 signal low state hold time be sure to transmit the next data bit to the sda0 line before the scl0 line is released (t rmax. + t su:dat = 1000 + 250 = 1250 ns by the sm b mode or the standard mode i 2 c bus specification).
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 416 ac timing measurement points (excluding x1 and xt1 inputs) clock timing ti timing 0.8 v dd 0.2 v dd point of measurement 0.8 v dd 0.2 v dd 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) 1/f ti t til t tih ti80, ti81
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 417 interrupt input timing reset input timing reset t rsl cpt90 input timing cpt90 t cpl t cph intp0 to intp3 t intl t inth
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 418 serial transfer timing 3-wire serial i/o mode: remark m = 1, 2 3-wire serial i/o mode (when using ss20): uart mode (external clock input): sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 asck20 t r t f t kl3 t kcy3 t kh3 t kas2 so20 ss20 output data t kds2
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 419 smb mode: t r t low t f t high t hd:sta stop condition start condition restart condition stop condition t buf t su:dat t su:sta t hd:sta t sp t su:sto t hd:dat scl0 sda0
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 420 10-bit a/d converter characteristics (t a = ? 40 to +85 c, 1.8 av ref av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit 4.5 v av ref av dd 5.5 v 0.2 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.4 0.6 %fsr overall error note 1.8 v av ref av dd 5.5 v 0.8 1.2 %fsr 4.5 v av ref av dd 5.5 v 14 100 s 2.7 v av ref av dd 5.5 v 14 100 s conversion time t conv 1.8 v av ref av dd 5.5 v 28 100 s 4.5 v av ref av dd 5.5 v 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.6 %fsr zero-scale error note 1.8 v av ref av dd 5.5 v 1.2 %fsr 4.5 v av ref av dd 5.5 v 0.4 %fsr 2.7 v av ref av dd 5.5 v 0.6 %fsr full-scale error note 1.8 v av ref av dd 5.5 v 1.2 %fsr 4.5 v av ref av dd 5.5 v 2.5 lsb 2.7 v av ref av dd 5.5 v 4.5 lsb integral linearity error note inl 1.8 v av ref av dd 5.5 v 8.5 lsb 4.5 v av ref av dd 5.5 v 1.5 lsb 2.7 v av ref av dd 5.5 v 2.0 lsb differential linearity error note dnl 1.8 v av ref av dd 5.5 v 3.5 lsb analog input voltage v ian 0 av ref v reference voltage av ref 1.8 av dd v resistance between av ref and av ss r adref 20 40 k ? note excludes quantization error ( 0.05%fsr). remark fsr: full scale range
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 421 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 1.8 to 5.5 v) parameter symbol conditions min. typ. max. unit write current (v dd pin) note 1 i ddw when v pp supply voltage = v pp1 (5.0 mhz operation) 18 ma write current (v pp pin) i ppw when v pp supply voltage = v pp1 7.5 ma erase current (v dd pin) note 1 i dde when v pp supply voltage = v pp1 (5.0 mhz operation) 18 ma erase current (v pp pin) i ppe when v pp supply voltage = v pp1 100 ma unit erase time note 2 t er 0.5 1 1 s total erase time t era 20 s write count note 3 erase/write is regarded as 1 cycle 20 20 20 times v pp0 in normal operation 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v notes 1. the current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and av dd current are not included. 2. the prewrite time before erasure and the erase verify time (writeback time) is not included. 3. when a product is first written after shipment, ?erase write? is taken as one rewrite. data memory stop mode low power supply voltage data retention characteristics (t a = ? 40 to +85 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 1.8 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization time is the time the cpu operation is st opped to prevent unstable operation when oscillation starts. 2. by using bits 0 to 2 (osts0 to osts2) of the o scillation stabilization time selection register (osts), 2 12 /f x , 2 15 /f x , or 2 17 /f x can be selected. remark f x : main system clock oscillation frequency
chapter 28 electrical specifications ( pd78f9177, 78f9177y) user?s manual u14186ej5v0ud 422 data retention timing (sto p mode release by reset) v dd data retention mode stop mode halt mode internal reset operation operating mode t srel t wait stop instruction execution v dddr reset data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd data retention mode stop mode halt mode operating mode t srel t wait stop instruction execution v dddr standby release signal (interrupt request)
user?s manual u14186ej5v0ud 423 chapter 29 characteristics curves ( pd78f9177, 78f9177y) 10.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 01234 supply voltage v dd (v) 5678 x1 x2 22 pf xt1 xt2 33 pf 220 k ? v ss 22 pf 33 pf v ss supply current i dd (ma) crystal resonator 5.0 mhz crystal resonator 32.768 khz subsystem clock operation halt mode (css0 = 1, mcc = 1) subsystem clock operating mode (css0 = 1, mcc = 1) main system clock operation halt mode (pcc1 = 1, css0 = 0) main system clock operation halt mode (pcc1 = 0, css0 = 0) main system clock operating mode (pcc1 = 1, css0 = 0) main system clock operating mode (pcc1 = 0, css0 = 0) (t a = 25 c) i dd vs. v dd (f x = 5.0 mhz, f xt = 32.768 khz)
user?s manual u14186ej5v0ud 424 chapter 30 electrical specifications ( pd78f9177a(a1)) absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit v dd v av dd v av ref av dd ? 0.3 v v dd av dd + 0.3 v av ref av dd + 0.3 v av ref v dd + 0.3 v ? 0.3 to +6.5 v supply voltage v pp note ? 0.3 to +10.5 v v i1 pins other than p50 to p53, p23, p24 ? 0.3 to v dd + 0.3 v v i2 p23, p24 ? 0.3 to +5.5 v input voltage v i3 p50 to p53 ? 0.3 to +13 v output voltage v o ? 0.3 to v dd + 0.3 v per pin ? 4 ma output current, high i oh total for all pins ? 14 ma per pin 5 ma output current, low i ol total for all pins 80 ma in normal operation mode ? 40 to +105 c operating ambient temperature t a during flash memory programming 10 to 40 c storage temperature t stg ? 40 to +125 c note make sure that the following conditions of the v pp voltage application timing are satisfied when the flash memory is written. ? when supply voltage rises v pp must exceed v dd 10 s or more after v dd has reached the lower-limit va lue (4.5 v) of the operating voltage range (see a in the figure below). when supply voltage drops v dd must be lowered 10 s or more after v pp falls below the lower-limit value (4.5 v) of the operating voltage range of v dd (see b in the figure below). caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the ab solute maximum ratings are rate d values at which the product is on the verge of suffering physical damage, a nd therefore the product must be used under conditions that ensure that the abso lute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins. 4.5 v v dd 0 v 0 v v pp 4.5 v a b
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 425 main system clock osc illator characteristics (v dd = 4.5 to 5.5 v, t a = ? 40 to +105 c) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f x ) note 1 v dd = oscillation voltage range 1.0 5.0 mhz ceramic resonator c1 x1 x2 c2 v ss0 oscillation stabilization time note 2 after v dd reaches oscillation voltage range min. 4 ms x1 input frequency (f x ) note 1 1.0 5.0 mhz x1 input high-/low-level width (t xh , t xl ) 85 500 ns x1 input frequency (f x ) note 1 1.0 5.0 mhz external clock x1 input high-/low-level width (t xh , t xl ) 85 500 ns notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator that stabilizes oscillation within the oscillation wait time. cautions 1. when using the main system clock osc illator, wire as follows in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss0 . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. when the main system clock is stopped and th e device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 3. for ceramic resonator, use the part number for which the resonator manufacturer guarantees operation under the condition of t a = 105 c. remark for the resonator selection and oscillator constant, us ers are requested to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. x1 x2 x1 x2 open
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 426 subsystem clock oscillator characteristics (v dd = 4.5 to 5.5 v, t a = ? 40 to +105 c) resonator recommended circuit parameter conditions min. typ. max. unit oscillation frequency (f xt ) note 1 32 32.768 35 khz crystal resonator c4 c3 r v ss0 xt1 xt2 oscillation stabilization time note 2 1.2 2 s xt1 input frequency (f xt ) note 1 32 35 khz external clock xt1 input high-/low-level width (t xth , t xtl ) 14.3 15.6 s notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. use a resonator that stabilizes oscillation within the oscillation wait time. cautions 1. when using the subsyst em clock oscillator, wire as follo ws in the area enclosed by the broken lines in the above fi gures to avoid an adverse eff ect from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with the other signal lines. ? do not route the wiring near a signal line th rough which a high fluctuating current flows. ? always make the ground point of the osci llator capacitor the same potential as v ss0 . ? do not ground the capacitor to a ground pa ttern through which a high current flows. ? do not fetch signals from the oscillator. 2. the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is mo re prone to malfunction due to noise than the ma in system clock oscillator. particular care is therefore required with the wir ing method when the subsystem clock is used. remark for the resonator selection and oscillator constant, us ers are requested to either evaluate the oscillation themselves or apply to the resonat or manufacturer for evaluation. xt1 xt2
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 427 dc characteristics (v dd = 4.5 to 5.5 v, t a = ? 40 to +105 c) (1/3) parameter symbol conditions min. typ. max. unit per pin ? 1 ma output current , high i oh total for all pins ? 7 ma per pin 1.6 ma output current, low i ol total for all pins 40 ma v ih1 p00 to p05, p10, p11, p60 to p67 0.7v dd v dd v v ih2 p50 to p53 0.7v dd 10 v v ih3 reset, p20 to p26, p30 to p33 0.8v dd v dd v input voltage, high v ih4 x1, x2, xt1, xt2 v dd ? 0.1 v dd v v il1 p00 to p05, p10, p11, p60 to p67 0 0.3v dd v v il2 p50 to p53 0 0.3v dd v v il3 reset, p20 to p26, p30 to p33 0 0.2v dd v input voltage, low v il4 x1, x2, xt1, xt2 0 0.1 v i oh = ? 1 ma v dd ? 2.0 v output voltage, high v oh pins other than p23, p24, p50 to p53 i oh = ? 100 a v dd ? 1.0 v i ol = 1.6 ma 2.0 v v ol1 pins other than p50 to p53 i ol = 400 a 1.0 v output voltage, low v ol2 p50 to p53 i ol = 1.6 ma 1.0 v remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 428 dc characteristics (v dd = 4.5 to 5.5 v, t a = ? 40 to +105 c) (2/3) parameter symbol conditions min. typ. max. unit i lih1 pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 10 a i lih2 v i = v dd x1, x2, xt1, xt2 20 a input leakage current, high i lih3 v i = 10 v p50 to p53 (n-ch open drain) 80 a i lil1 v i = 0 v pins other than p50 to p53 (n-ch open drain), x1, x2, xt1, and xt2 ? 10 a i lil2 x1, x2, xt1, xt2 ? 20 a input leakage current, low i lil3 p50 to p53 (n-ch open drain) ? 10 note a output leakage current, high i loh v o = v dd 10 a output leakage current, low i lol v o = 0 v ? 10 a software pull-up resistor r 1 v i = 0 v, for pins other than p23, p24, and p50 to p53 50 100 300 k ? note a low-level input leakage current of ? 60 a (max.) flows only during the 1-cycle time after a read instruction is executed to p50 to p53 when p50 to p5 3 are set to input mode. at times other than this, a ? 10 a (max.) current flows. remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 429 dc characteristics (v dd = 4.5 to 5.5 v, t a = ? 40 to +105 c) (3/3) parameter symbol conditions min. typ. max. unit i dd1 note 1 5.0 mhz crystal oscillation operating mode (c1 = c2 = 22 pf) v dd = 5.0 v 10% note 4 7.5 20.0 ma i dd2 note 1 5.0 mhz crystal oscillation halt mode (c1 = c2 = 22 pf) v dd = 5.0 v 10% note 4 3.0 6.0 ma i dd3 note 1 32.768 khz crystal oscillation operating mode note 3 (c3 = c4 = 22 pf, r = 220 k ? ) v dd = 5.0 v 10% 30 3000 a i dd4 note 1 32.768 khz crystal oscillation halt mode note 3 (c3 = c4 = 22 pf, r = 220 k ? ) v dd = 5.0 v 10% 25 2500 a i dd5 note 1 32.768 khz crystal stop stop mode v dd = 5.0 v 10% 1.0 1000 a power supply current i dd6 note 2 5.0 mhz crystal oscillation a/d operating mode (c1 = c2 = 22 pf) v dd = 5.0 v 10% note 4 8.7 22.3 ma notes 1. the av ref on (adcs0 (bit 7 of adm0; a/d converter mode register 0) = 1), av dd , and port current (including the current flowing through the inte rnal pull-up resistors) is not included. 2. the av ref on (adcs0 =1) and port current (including the current flowing through the internal pull-up resistors) is not included. refer to the a/d conv erter characteristics for the current flowing through av ref . 3. when the main system clock is stopped. 4. during high-speed mode operation (when the processor clock control register (pcc) is set to 00h.) remark unless otherwise specified, the characteristics of al ternate-function pins are t he same as those of port pins.
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 430 ac characteristics (1) basic operation (v dd = 4.5 to 5.5 v, t a = ? 40 to +105 c) parameter symbol conditions min. typ. max. unit operation based on the main system clock 0.4 8 s cycle time (minimum instruction execution time) t cy operation based on the s ubsystem clock 114 122 125 s ti80 and ti81 input frequency f ti 0 4 mhz ti80 and ti81 input high-/low-level width t tih , t til 0.1 s interrupt input high- /low-level width t inth , t intl intp0 to intp3 10 s reset input low- level width t rsl 10 s cpt90 input high- /low-level width t cph , t cpl 10 s t cy vs. v dd (main system clock) supply voltage v dd [v] 123456 0.1 0.4 1.0 10 60 cycle time t cy [ s] operation guaranteed range
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 431 (2) serial interface 20 (v dd = 4.5 to 5.5 v, t a = ? 40 to +105 c) (a) 3-wire serial i/o mode (sck20...internal clock) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy1 800 ns sck20 high-/low- level width t kh1 , t kl1 t kcy1 /2 ? 50 ns si20 setup time (to sck20 ) t sik1 150 ns si20 hold time (from sck20 ) t ksi1 400 ns so20 output delay time from sck20 t kso1 r = 1 k ? , c = 100 pf note 0 250 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (b) 3-wire serial i/o mode (sck20...external clock) parameter symbol conditions min. typ. max. unit sck20 cycle time t kcy2 900 ns sck20 high-/low- level width t kh2 , t kl2 400 ns si20 setup time (to sck20 ) t sik2 100 ns si20 hold time (from sck20 ) t ksi2 400 ns so20 output delay time from sck20 t kso2 r = 1 k ? , c = 100 pf note 0 300 ns so20 setup time (when using ss20, to ss20 ) t kas2 120 ns so20 disable time (when using ss20, from ss20 ) t kds2 240 ns note r and c are the load resistance and l oad capacitance of the so20 output line. (c) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 78125 bps
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 432 (d) uart mode (external clock input) parameter symbol conditions min. typ. max. unit asck20 cycle time t kcy3 900 ns asck20 high-/low- level width t kh3 , t kl3 400 ns transfer rate 39063 bps asck20 rise time, fall time t r , t f 1 s
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 433 ac timing measurement points (excluding x1 and xt1 inputs) 0.8v dd 0.2v dd point of measurement 0.8v dd 0.2v dd clock timing ti timing 1/f x t xl t xh x1 input v ih4 (min.) v il4 (max.) 1/f xt t xtl t xth xt1 input v ih4 (min.) v il4 (max.) 1/f ti t til t tih ti80, ti81
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 434 interrupt input timing reset input timing reset t rsl cpt90 input timing cpt90 t cpl t cph intp0 to intp3 t intl t inth
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 435 serial transfer timing 3-wire serial i/o mode: remark m = 1, 2 3-wire serial i/o mode (when using ss20): uart mode (external clock input): sck20 t klm t kcym t khm si20 input data t ksim t sikm output data t ksom so20 asck20 t r t f t kl3 t kcy3 t kh3 t kas2 so20 ss20 output data t kds2
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 436 10-bit a/d converter characteristics (t a = ? 40 to +105 c, 4.5 av ref av dd = v dd 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 0.2 0.6 %fsr conversion time t conv 14 28 s zero-scale error note 0.6 %fsr full-scale error note 0.6 %fsr integral linearity error note inl 4.5 lsb differential linearity error note dnl 2.0 lsb analog input voltage v ian 0 av ref v reference voltage av ref 4.5 av dd v resistance between av ref and av ss r adref 20 40 k ? note excludes quantization error ( 0.05%fsr). remark fsr: full scale range
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 437 flash memory write/erase characteristics (t a = 10 to 40 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit write current (v dd pin) note 1 i ddw when v pp supply voltage = v pp1 (5.0 mhz operation) 23 ma write current (v pp pin) i ppw when v pp supply voltage = v pp1 20 ma erase current note 1 (v dd pin) i dde when v pp supply voltage = v pp1 (5.0 mhz operation) 23 ma erase current (v pp pin) i ppe when v pp supply voltage = v pp1 100 ma unit erase time note 2 t er 0.2 0.2 0.2 s total erase time t era 20 s write count note 3 erase/write is regarded as 1 cycle 20 20 20 times v pp0 in normal operation mode 0 0.2v dd v v pp supply voltage v pp1 during flash memory programming 9.7 10.0 10.3 v notes 1. the current flowing to the ports (including the current flowing through an on-chip pull-up resistor) and av dd current are not included. 2. the prewrite time before erasure and the erase verify time (writeback time) are not included. 3. when a product is first written after shipment, ?erase write? is taken as one rewrite.
chapter 30 electrical specifications ( pd78f9177a(a1)) user?s manual u14186ej5v0ud 438 data memory stop mode low power supply voltage data retention characteristics (t a = ? 40 to +105 c) parameter symbol conditions min. typ. max. unit data retention power supply voltage v dddr 4.5 5.5 v release signal set time t srel 0 s release by reset 2 15 /f x s oscillation stabilization wait time note 1 t wait release by interrupt request note 2 s notes 1. the oscillation stabilization time is the time t he cpu operation is stopped to prevent unstable operation when oscillation starts. 2. 2 12 /f x , 2 15 /f x , or 2 17 /f x can be selected by using bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select ion register (osts). remark f x : main system clock oscillation frequency data retention timing (sto p mode release by reset) t wait stop instruction execution stop mode operating mode halt mode reset internal reset operation data retention mode v dddr v dd t srel data retention timing (standby release signal: stop mode re lease by interrupt signal) v dd stop mode halt mode t srel v dddr t wait operating mode data retention mode stop instruction execution standby release signal (interrupt request)
user?s manual u14186ej5v0ud 439 chapter 31 package drawings 33 34 22 44 1 12 11 23 44 pin plastic lqfp (10x10) item millimeters n q 0.1 0.05 0.10 s44gb-80-8es-2 j i h n a 12.0 0.2 b 10.0 0.2 c 10.0 0.2 d 12.0 0.2 f g h 1.0 0.37 1.0 i j k 0.8 (t.p.) 1.0 0.2 0.20 l 0.5 m 0.17 s t u 1.6 max. 0.25 (t.p.) 0.6 0.15 r3 + 0.08 ? 0.07 + 0.03 ? 0.06 + 4 ? 3 detail of lead end f g k m m p 1.4 0.05 note s s a b cd u r s p q l t each lead centerline is located within 0.20 mm of its true position (t.p.) at maximum material condition.
chapter 31 package drawings user?s manual u14186ej5v0ud 440 s s n j detail of lead end r k m l p i s q g f m h 48-pin plastic tqfp (fine pitch) (7x7) note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 9.0 0.2 7.0 0.2 0.5 (t.p.) 0.75 j 9.0 0.2 k c 7.0 0.2 i 0.10 1.0 0.2 l 0.5 0.2 f 0.75 n p q 0.10 1.0 0.1 0.1 0.05 s48ga-50-9eu-2 s 1.27 max. h 0.22 + 0.05 ? 0.04 m 0.145 + 0.055 ? 0.045 r3 + 7 ? 3 36 37 24 48 1 13 12 25 cd a b
user?s manual u14186ej5v0ud 441 chapter 32 recommended soldering conditions the pd789167, 789177, 789167y, and 789177y subseries s hould be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than thos e recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (h ttp://www.necel.com/pkg/en/mount/index.html). table 32-1. surface mounting type soldering cond itions (1/3) pd789166gb- -8es: 44-pin plastic lqfp (10 10) pd789167gb- -8es: 44-pin plastic lqfp (10 10) pd789176gb- -8es: 44-pin plastic lqfp (10 10) pd789177gb- -8es: 44-pin plastic lqfp (10 10) pd789166ygb- -8es: 44-pin plastic lqfp (10 10) pd789167ygb- -8es: 44-pin plastic lqfp (10 10) pd789176ygb- -8es: 44-pin plastic lqfp (10 10) pd789177ygb- -8es: 44-pin plastic lqfp (10 10) pd789166gb(a)- -8es: 44-pin plastic lqfp (10 10) pd789167gb(a)- -8es: 44-pin plastic lqfp (10 10) pd789176gb(a)- -8es: 44-pin plastic lqfp (10 10) pd789177gb(a)- -8es: 44-pin plastic lqfp (10 10) pd789166gb(a1)- -8es: 44-pin plastic lqfp (10 10) pd789167gb(a1)- -8es: 44-pin plastic lqfp (10 10) pd789176gb(a1)- -8es: 44-pin plastic lqfp (10 10) pd789177gb(a1)- -8es: 44-pin plastic lqfp (10 10) pd789166gb(a2)- -8es: 44-pin plastic lqfp (10 10) pd789167gb(a2)- -8es: 44-pin plastic lqfp (10 10) pd789176gb(a2)- -8es: 44-pin plastic lqfp (10 10) pd789177gb(a2)- -8es: 44-pin plastic lqfp (10 10) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less ir35-00-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less vp15-00-2 wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, preheating temperature: 120 c max. (package surface temperature) ws60-00-1 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? caution do not use different soldering methods together ( except for partial heating).
chapter 32 recommended soldering conditions user?s manual u14186ej5v0ud 442 table 32-1. surface mounting type soldering cond itions (2/3) pd78f9177gb-8es: 44-pin plastic lqfp (10 10) pd78f9177ygb-8es: 44-pin plastic lqfp (10 10) pd78f9177agb-8es: 44-pin plastic lqfp (10 10) pd78f9177aygb-8es: 44-pin plastic lqfp (10 10) pd78f9177agb(a)-8es: 44-pin plastic lqfp (10 10) pd78f9177aygb(a)-8es: 44-pin plastic lqfp (10 10) pd78f9177agb(a1)-8es: 44-pin plastic lqfp (10 10) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235c, time: 30 seconds max. (at 210c or higher), count: twice or less, number of days: 3 note (after that, prebaking is necessary at 125c for 10 hours) ir35-103-2 vps package peak temperature: 215c, time: 40 seconds max. (at 200c or higher), count: twice or less, number of days: 3 note (after that, prebaking is necessary at 125c for 10 hours) vp15-103-2 wave soldering solder bath temperature: 260c max., time: 10 seconds max., count: once, preheating temperature: 120c max. (package surface temperature), number of days: 3 note (after that, prebaking is necessary at 125c for 10 hours) ws60-103-1 partial heating pin temperature: 300c max., time: 3 seconds max. (per pin row) ? note the number of days for storage at 25c, 65% rh max after the dry pack has been opened. caution do not use different soldering methods together ( except for partial heating).
chapter 32 recommended soldering conditions user?s manual u14186ej5v0ud 443 table 32-1. surface mounting type soldering cond itions (3/3) pd789166ga- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd789167ga- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd789176ga- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd789177ga- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd789166yga- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd789167yga- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd789176yga- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd789177yga- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd789166yga(a)- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd789167yga(a)- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd789176yga(a)- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd789177yga(a)- -9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd78f9177yga-9eu: 48-pin plast ic tqfp (fine pitch) (7 7) pd78f9177aga-9eu: 48-pin plast ic tqfp (fine pitch) (7 7) pd78f9177ayga-9eu: 48-pin plastic tqfp (fine pitch) (7 7) pd78f9177ayga(a)-9eu: 48-pin pl astic tqfp (fine pitch) (7 7) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: twice or less, number of days: 3 note (after that, prebaking is necessary at 125 c for 10 hours) ir35-103-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: twice or less, number of days: 3 note (after that, prebaking is necessary at 125 c for 10 hours) vp15-103-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note the number of days for storage at 25 c, 65% rh max after the dry pack has been opened. caution do not use different soldering methods together ( except for partial heating).
444 user?s manual u14186ej5v0ud appendix a development tools the following development tools are avail able for development of systems using the pd789167, 789177, 789167y, and 789177y subseries. figure a- 1 shows the development tools. ? support to pc98-nx series unless specified otherwise, the pr oducts supported by ibm pc/at? co mpatibles can be used in pc98-nx series. when using the pc98-nx series, refer to the explanation of ibm pc/at compatibles. ? windows tm unless specified otherwise, ?windows? i ndicates the following operating systems. ? windows 3.1 ? windows 95 ? windows 98 ? windows 2000 ? windows nt tm ver. 4.0 ? windows xp
appendix a development tools user?s manual u14186ej5v0ud 445 figure a-1. development tools notes 1. the c library source file is not included in the software package. 2. the project manager is included in the assembler package. the project manager is used only in the windows environment. language processing software assembler package c compiler package device file c library source file note 1 debugging software integrated debugger system simulator host machine (pc or ews) interface adapter in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system flash programmer flash memory writing adapter flash memory power supply unit software package control software project manager (windows version only) note 2 software package flash memory writing environment
appendix a development tools user?s manual u14186ej5v0ud 446 a.1 software package software tools for development of the 78k/0 s series are combined in this package. the following tools are included. ra78k0s, cc78k0s, id78k0s-ns, sm78k0s, and device files sp78k0s software package part number: s sp78k0s remark in the part number differs depending on the os used s sp78k0s host machine os supply medium ab17 japanese windows cd-rom bb17 pc-9800 series, ibm pc/at compatible english windows a.2 language processing software program that converts program written in mnemonic into obj ect codes that can be executed by a microcontroller. in addition, automatic functions to generate a symbol table and optimize branch instructions are also provided. used in combination with a device file (df789178) (sold separately). the assembler package is a dos-based app lication but may be used in the windows environment by using the proj ect manager of windows (included in the assembler package). ra78k0s assembler package part number: s ra78k0s program that converts program written in c language into objec t codes that can be executed by a microcontroller. used in combination with an assembler package (ra78k0s) and device file (df789178) (both sold separately). the c compiler package is a dos-based app lication but may be used in the windows environment by using the proj ect manager of windows (included in the assembler package). cc78k0s c compiler package part number: s cc78k0s file containing the informat ion inherent to the device. used in combination with the ra78k0s, cc 78k0s, id78k0s-ns, and sm78k0s (all sold separately). df789178 note 1 device file part number: s df789178 source file of functions for generating an obj ect library included in the c compiler package. necessary for changing the object library incl uded in the c compiler package according to the customer?s specifications. since this is a source file , its working environment does not depend on any particular operating system. cc78k0s-l note 2 c library source file part number: s cc78k0s-l notes 1. df789178 is a common file t hat can be used with the ra78k 0s, cc78k0s, id78k0s-ns, and sm78k0s. 2. cc78k0s-l is not included in the software package (sp78k0s).
appendix a development tools user?s manual u14186ej5v0ud 447 remark in the part number differs depending on the hos t machine and operating system to be used. s ra78k0s s cc78k0s host machine os supply medium ab13 japanese windows 3.5" 2hd fd bb13 english windows ab17 japanese windows bb17 pc-9800 series, ibm pc/at compatible english windows cd-rom 3p17 hp9000 series 700 tm hp-ux tm (rel. 10.10) 3k17 sparcstation tm sunos tm (rel. 4.1.4), solaris tm (rel. 2.5.1) s df789178 s cc78k0s-l host machine os supply medium ab13 japanese windows 3.5" 2hd fd bb13 pc-9800 series, ibm pc/at compatible english windows 3p16 hp9000 series 700 hp-ux (rel. 10.10) dat 3k13 3.5" 2hd fd 3k15 sparcstation sunos (rel. 4.1.4), solaris (rel. 2.5.1) 1/4-inch cgmt a.3 control software project manager control software created for efficient development of the user program in the windows environment. user program dev elopment operations such as editor startup, build, and debugger startup can be performed from the project manager. the project manager is included in the assembler package (ra78k0s). the project manager is used onl y in the windows environment. a.4 flash memory writing tools flashpro iii (fl-pr3, pg-fp3) flashpro iv (fl-pr4, pg-fp4) flash programmer dedicated flash programmer for microcont rollers incorporating flash memory fa-44gb-8es fa-48ga flash memory writing adapter adapter for writing to flash memory and connected to flashpro iii or flashpro iv. ? fa-44gb-8es: for 44-pin plastic lqfp (gb-8es type) ? fa-48ga: for 48-pin pl astic tqfp (ga-9eu type) remark the fl-pr3, fl-pr4, fa-44gb-8es, and fa-48ga ar e products made by naito densei machida mfg. co., ltd. (tel +81-45-475-4191).
appendix a development tools user?s manual u14186ej5v0ud 448 a.5 debugging tools (hardware) ie-78k0s-ns in-circuit emulator in-circuit emulator for debugging hardware and software of an application system using the 78k/0s series. supports the integrated debugger (i d78k0s-ns). used in combination with an ac adapter, emulation probe, and interface adapter for connecting the host machine. ie-78k0s-ns-a in-circuit emulator the ie-78k0s-ns-a provides a co verage function in addition to t he ie-78k0s-ns functions, thus enhancing the debug functions, including the tracer and timer functions. ie-70000-mc-ps-b ac adapter adapter for supplying power from an ac 100 to 240 v outlet. ie-70000-98-if-c interface adapter adapter necessary when using a pc-9800 series pc (except notebook type) as the host machine (c bus supported) ie-70000-cd-if-a pc card interface pc card and interface cable necessary when us ing a notebook pc as the host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter interface adapter necessary when using an ibm pc /at compatible as the host machine (isa bus supported) ie-70000-pci-if-a interface adapter adapter necessary when using a personal computer incorporating a pci bus as the host machine ie-789177-ns-em1 emulation board board for emulating the peripheral hardware inherent to the device. used in combination with an in-circuit emulator. np-44gb-tq np-h44gb-tq emulation probe probe to connect the in-circuit emulator and target system. used in combination with the tgb-044sap. tgb-044sap conversion adapter conversion socket to connect the np-44gb-tq , np-h44gb-tq and a target system board on which a 44-pin plastic lqfp (gb-8es type) can be mounted. np-48ga emulation probe cable to connect the in-circuit emulator and target system. used in combination with the tga-048sdp. tga-048sdp conversion adapter conversion adapter to connect t he np-48ga and a target system board on which a 48-pin plastic tqfp (fine pitch) (ga- 9eu type) can be mounted remarks 1. the np-44gb-tq and np-h44gb-tq are products made by naito d ensei machida mfg. co., ltd. (tel +81-45-475-4191). 2. the tgb-044sap and tga-048sdp are products made by tokyo eletech corporation. for further information, c ontact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672)
appendix a development tools user?s manual u14186ej5v0ud 449 a.6 debugging tools (software) this debugger supports the in-cir cuit emulators ie-78k0s-ns and ie-78k0s-ns-a for the 78k/0s series. the id78k0s-n s is windows-based software. it has improved c-compatible debuggi ng functions and can display the results of tracing with the source program using an integrating wi ndow function that associates the source program, disassemble display, and memo ry display with the trace result. used in combination with a device file (df789178) (sold separately). id78k0s-ns integrated debugger part number: s id78k0s-ns this is a system simulator for the 78k/0s series. the sm78k0s is windows-based software. it can be used to debug the target system at c source level or assembler level while simulating the operation of the target system on the host machine. using sm78k0s, the logic and performance of the application can be verified independently of hardware development. therefore, t he development efficiency can be enhanced and the software quality can be improved. used in combination with a device f ile (df789178) (sold separately). sm78k0s system simulator part number: s sm78k0s file containing the informat ion inherent to the device. used in combination with the ra78k0s, cc 78k0s, id78k0s-ns, and sm78k0s (all sold separately). df789178 note device file part number: s df789178 note df789178 is a common file that can be used with the ra78k0s, cc 78k0s, id78k0s-ns, and sm78k0s. remark in the part number differs depending on the oper ating system and supply medium to be used. s id78k0s-ns s sm78k0s host machine os supply medium ab13 japanese windows bb13 english windows 3.5" 2hd fd ab17 japanese windows bb17 pc-9800 series ibm pc/at compatible english windows cd-rom
user?s manual u14186ej5v0ud 450 appendix b notes on target system design the following shows the conditions when connecting the emulation probe to the conversion connector or conversion socket. follow the configuration below and c onsider the shape of parts to be mounted on the target system when designing a system. figure b-1. distance between in-circuit emulator and conversion socket (np-44gb-tq) 170 mm note in-circuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789177-ns-em1 conversion adapter: tgb-044sap target system cn1 emulation probe np-44gb-tq np-h44gb-tq note distance when np-44gb-tq is used. when np -h44gb-tq is used, the distance is 370 mm. remarks 1. np-44gb-tq and np-h44gb-tq are products of naito densei machida mfg. co., ltd. 2. tgb-044sap is a product of tokyo eletech corporation.
appendix b notes on target system design user?s manual u14186ej5v0ud 451 figure b-2. connection condition of target system (np-h44gb-tq) extension probe np-h44gb-tq emulation board ie-789177-ns-em1 23 mm 10 mm 40 mm 34 mm target system 11 mm conversion adapter tgb-044sap remarks 1. np-h44gb-tq is a product of nait o densei machida mfg. co., ltd. 2. tgb-044sap is a product of tokyo eletech corporation.
appendix b notes on target system design user?s manual u14186ej5v0ud 452 figure b-3. distance between in-circuit emulator and conversion socket (np-48ga) 170 mm incircuit emulator ie-78k0s-ns or ie-78k0s-ns-a emulation board ie-789177-ns-em1 conversion adapter: tga-048sdp target system cn1 emulation probe np-48ga remarks 1. np-48ga is a product of naito d ensei machida mfg. co., ltd. 2. tga-048sdp is a product of tokyo eletech corporation.
appendix b notes on target system design user?s manual u14186ej5v0ud 453 figure b-4. connection condition of target system (np-48ga) extension probe np-48ga emulation board ie-789177-ns-em1 23 mm 10 mm 40 mm 34 mm target system 11 mm conversion adapter tga-048sdp remarks 1. np-48ga is a product of naito d ensei machida mfg. co., ltd. 2. tga-048sdp is a product of tokyo eletech corporation.
user?s manual u14186ej5v0ud 454 appendix c register index c.1 register name index 16-bit capture regi ster 90 (tcp90) ............................................................................................. ..........................118 16-bit compare regi ster 90 (cr90) .............................................................................................. .........................118 16-bit multiplication result storage regist er 0 (mul0) ......................................................................... ..................289 16-bit timer count er 90 (t m90) ................................................................................................. ............................118 16-bit timer mode contro l register 90 (tmc 90) .................................................................................. ...................119 8-bit compare registers 80, 81, 82 (cr80, cr81, cr82) .......................................................................... ...........137 8-bit timer counter 80, 81, 82 (tm80, tm81, tm82) .............................................................................. ...............137 8-bit timer mode contro l register 80 (tmc 80) ................................................................................... ....................138 8-bit timer mode contro l register 81 (tmc 81) ................................................................................... ....................139 8-bit timer mode contro l register 82 (tmc 82) ................................................................................... ....................140 [a] a/d conversion result register 0 (adcr0 ) ....................................................................................... .............165, 178 a/d converter mode r egister 0 (adm0) ........................................................................................... .............167, 180 a/d input selection register 0 (ads 0) .......................................................................................... .................168, 181 asynchronous serial interface mode register 20 (asi m20)........................................................... 195, 202, 205 , 218 asynchronous serial interface status register 20 (asi s20)...................................................................... .....197, 206 [b] baud rate generator control register 20 (brgc 20) .............................................................................. 1 98, 207, 219 buzzer output control register 90 (bzc 90) ...................................................................................... .....................121 [e] external interrupt mode register 0 (intm0) ..................................................................................... .....................299 external interrupt mode register 1 (intm1) ..................................................................................... .....................300 [i] interrupt mask flag regist ers 0, 1 (mk 0, mk1) .................................................................................. ....................298 interrupt request flag regi sters 0, 1 (if0, if1) ............................................................................... ........................297 [m] multiplication data register s a0, b0 (mr a0, mrb0) .............................................................................. ...............289 multiplier control r egister 0 (mulc 0) .......................................................................................... ..........................291 [o] oscillation stabilization time selection regi ster (osts) ....................................................................... .................309 [p] port 0 (p0) ................................................................................................................... .........................................87 port 1 (p1) ................................................................................................................... .........................................88 port 2 (p2) ................................................................................................................... .........................................89
appendix c register index user?s manual u14186ej5v0ud 455 port 3 (p3) ................................................................................................................... .........................................94 port 5 (p5) ................................................................................................................... .........................................97 port 6 (p6) ................................................................................................................... .........................................98 port mode regist er 0 (p m0) ..................................................................................................... ...............................99 port mode regist er 1 (p m1) ..................................................................................................... .........................88, 99 port mode regist er 2 (p m2) ..................................................................................................... .................89, 99, 141 port mode regist er 3 (p m3) ..................................................................................................... ...............99, 122, 141 port mode regist er 5 (p m5) ..................................................................................................... ...............................99 processor clock cont rol regist er (pcc)......................................................................................... ........................105 pull-up resistor option register 0 (pu0)....................................................................................... ..........................100 pull-up resistor option regist ers b2, b3 (p ub2, pu b3) .......................................................................... ..............101 [r] reception buffer r egister 20 (rxb20)........................................................................................... ........................193 reception shift r egister 20 (rxs20) ............................................................................................ .........................193 [s] serial operation mode regi ster 20 (csi m20) ................................................................................ 194, 201, 204, 217 smb clock selection r egister 0 (smbc l0) ........................................................................................ ....................239 smb control regist er 0 (s mbc0) ................................................................................................. .........................231 smb input level setting register 0 (smbvi0).................................................................................... .....................243 smb mode register 0 (smbm0).................................................................................................... ........................241 smb shift regist er 0 (s mb0) .................................................................................................... .....................229, 244 smb slave address regi ster 0 (s mbsva0)......................................................................................... ..........229, 244 smb status regist er 0 (s mbs0).................................................................................................. ..........................236 subclock control register (css)................................................................................................ ............................107 suboscillation mode r egister (sckm) ............................................................................................ .......................106 [t] timer clock selection register 2 (tc l2) ........................................................................................ ........................160 transmission shift r egister 20 (txs20) ......................................................................................... .......................193 [w] watch timer mode contro l register (wtm)........................................................................................ ....................155 watchdog timer mode r egister (wdtm) ............................................................................................ ...................161
appendix c register index user?s manual u14186ej5v0ud 456 c.2 register symbol index [a] adcr0: a/d conversion result regi ster 0...................................................................................... ..........165, 178 adm0: a/d converte r mode regi ster 0 .......................................................................................... ........167, 180 ads0: a/d input se lection regi ster 0 ......................................................................................... ...........168, 181 asim20: asynchronous serial interf ace mode register 20 ....................................................... 195, 202, 205, 2 18 asis20: asynchronous serial interface status regist er 20 ..................................................................... .197, 206 [b] brgc20: baud rate generator control regi ster 20 ............................................................................ 19 8, 207, 219 bzc90: buzzer output control regi ster 90 ..................................................................................... .................121 [c] cr80: 8-bit com pare regist er 80 .............................................................................................. ....................137 cr81: 8-bit com pare regist er 81 .............................................................................................. ....................137 cr82: 8-bit com pare regist er 82 .............................................................................................. ....................137 cr90: 16-bit com pare regist er 90 ............................................................................................. ...................118 csim20: serial operati on mode register 20 ............................................................................. 194, 20 1, 204, 217 css: subclock control r egister............................................................................................... ....................107 [i] if0: interrupt r equest flag regi ster 0....................................................................................... ..................297 if1: interrupt r equest flag regi ster 1....................................................................................... ..................297 intm0: external inte rrupt mode r egister 0.................................................................................... .................299 intm1: external inte rrupt mode r egister 1..................................................................................... ................300 [m] mk0: interrupt ma sk flag regi ster 0 .......................................................................................... ..................298 mk1: interrupt ma sk flag regi ster 1 .......................................................................................... ..................298 mra0: multiplicati on data regi ster a0........................................................................................ ...................289 mrb0: multiplicati on data regi ster b0........................................................................................ ...................289 mul0: 16-bit multiplication result storage register 0........................................................................ .............289 mulc0: multiplier control regi ster 0......................................................................................... .......................291 [o] osts: oscillation stabilizati on time select ion regi ster ...................................................................... ............309 [p] p0: port 0 ................................................................................................................... ...............................87 p1: port 1 .................................................................................................................... ..............................88 p2: port 2 .................................................................................................................... ..............................89 p3: port 3 ................................................................................................................... ...............................94 p5: port 5 ................................................................................................................... ...............................97 p6: port 6 ................................................................................................................... ...............................98 pcc: processor cl ock control regist er........................................................................................ ................105 pm0: port m ode regist er 0 .................................................................................................... .......................99 pm1: port m ode regist er 1 .................................................................................................... .................88, 99
appendix c register index user?s manual u14186ej5v0ud 457 pm2: port m ode regist er 2 .................................................................................................... .........89, 99, 141 pm3: port m ode regist er 3 .................................................................................................... .......99, 132, 141 pm5: port m ode regist er 5 .................................................................................................... .......................99 pu0: pull-up resistor option regi ster 0 ...................................................................................... .................100 pub2: pull-up resistor option regi ster b2 .................................................................................... .................101 pub3: pull-up resistor option regi ster b3 .................................................................................... .................101 [r] rxb20: reception buffer regi ster 20.......................................................................................... ....................193 rxs20: reception shift regi ster 20 ........................................................................................... .....................193 [s] sckm: suboscilla tion mode r egist er ........................................................................................... ..................106 smb0: smb shi ft regist er 0................................................................................................... ................229, 244 smbc0: smb cont rol regist er 0 ................................................................................................ ......................231 smbcl0: smb clock se lection regi ster 0 ....................................................................................... ...................239 smbm0: smb m ode regist er 0 ................................................................................................... .....................241 smbs0: smb stat us regist er 0................................................................................................. .......................236 smbsva0: smb slave addr ess regist er 0 ......................................................................................... ..........229, 244 smbvi0: smb input le vel setting r egister 0................................................................................... ...................243 [t] tcl2: timer clock se lection regi ster 2....................................................................................... ..................160 tcp90: 16-bit c apture regi ster 90 ............................................................................................ ......................118 tm80: 8-bit ti mer count er 80 ................................................................................................. .......................137 tm81: 8-bit ti mer count er 81 ................................................................................................. .......................137 tm82: 8-bit ti mer count er 82 ................................................................................................. .......................137 tm90: 16-bit ti mer count er 90 ................................................................................................ ......................118 tmc80: 8-bit timer m ode control r egister 80 .................................................................................. ................138 tmc81: 8-bit timer m ode control r egister 81 .................................................................................. ................139 tmc82: 8-bit timer m ode control r egister 82 .................................................................................. ................140 tmc90: 16-bit timer m ode control r egister 90 ................................................................................. ...............119 txs20: transmission shift regi ster 20 ........................................................................................ ...................193 [w] wdtm: watchdog time r mode r egist er ............................................................................................ ..............161 wtm: watch timer mode control regist er ....................................................................................... .............155
user?s manual u14186ej5v0ud 458 appendix d revision history d.1 major revisions in this edition page description throughout addition of 48-pin plas tic tqfp (fine pitch) (7 7) to pd789167, 789177 subseries pd789166ga- -9eu, pd789167ga- -9eu, pd789176ga- -9eu, pd789177ga- -9eu, pd78f9177aga-9eu p. 47 p. 51 p. 52 chapter 3 pin functions ( pd789167 and 789177 subseries) addition of description on ic3 to 3.1 (2) non-port pins addition of 3.2.17 ic3 addition of description on ic3 to table 3-1 types of i/o circuits for each pin and recommended connection of unused pins the mark shows major revised points.
appendix d revision history user?s manual u14186ej5v0ud 459 d.2 revision history up to previous edition revisions up to the previous edition are shown below. the ?applied to? column indicates the chapter in each edition to which the revision was applied. (1/3) edition revision from previous edition applied to: addition of description of pd789166y, pd789167y, pd789176y, and pd789177y change of status of pd789166, pd789167, pd789176, and pd789177 from ?under development? to ?developed? throughout addition of description of smb0 specia l function registers to table 5-3 special function registers chapter 5 cpu architecture modification of figure 6-5 block diagram of p21 chapter 6 port functions addition of 8.5 notes on using 16- bit timer chapter 8 16-bit timer addition of 15 smb0 ( pd789167y and 789177y subseries) chapter 15 smb0 ( pd789167y and 789177y subseries) addition of description of smb0 interrupt to 17 interrupt functions chapter 17 interrupt functions addition of figure 20-3 flashpro iii connection in smb mode addition of setting with smb mode in table 20-4 setting with pg-fp3 chapter 20 pd78f9177 and pd78f9177y second edition addition of development tools for pd789166y, pd789167y, pd789176y, and pd789177y appendix a development tools addition of pd789166(a), 789167(a), 789176(a), 789177(a), 789166y(a), 789167y(a), 789176y(a), 789177y(a), 789166(a1), 789167(a1), 789176(a1), 789177(a1), 789166(a2), 789167(a2), 789176(a2), 789177(a2), 78f9177a, 78f9177ay, 78f9177a(a), 78f9177ay(a), and 78f9177a(a1) addition of description on expanded- specification pr oducts (10 mhz) throughout addition of description on generic terms used in this manual change of related documents introduction addition of 1.1 expanded-specif ication products and conventional products addition of 1.10 differenc es between standard quality grade products and (a) products, (a1) products, and (a2) products chapter 1 general ( pd789167 and 789177 subseries) addition of 2.1 expanded-specif ication products and conventional products addition of 2.10 differenc es between standard quality grade products and (a) products chapter 2 general ( pd789167y and 789177y subseries) modification of v pp pin connection in 3.2.15 v pp (flash memory version only) and table 3-1 types of i/o circuits for each pin and recommended connection of unused pins chapter 3 pin functions ( pd789167 and 789177 subseries) addition of note to figure 7-3 format of suboscillation mode register chapter 7 clock generator third edition modification of description in 8. 4.1 operation as timer interrupt modification of description in 8.4.2 operation as timer output chapter 8 16-bit timer 90
appendix d revision history user?s manual u14186ej5v0ud 460 (2/3) edition revision from previous edition applied to: addition of 9.5 (4) cautions when set to stop mode addition of 9.5 (5) start ti ming of external event counter chapter 9 8-bit timer/event counters 80 to 82 addition of 12.5 (8) input impedance of ani0 to ani7 pins chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) modification of description in 13.2 (2 ) a/d conversion result register 0 (adcr0) modification of figure 13-4 basi c operation of 10-bit a/d converter addition of 13.5 (8) input impedance of ani0 to ani7 pins chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) modification of figure 14-1 blo ck diagram of serial interface 20 modification of description on pe 20 flag in figure 14-5 format of asynchronous serial interface status register 20 addition of 14.4.2 (2) (f) reading receive data chapter 14 serial interface 20 overall revision of description on flash me mory programming chapter 20 flash memory version addition of electrical specifications chapter 23, 25, 27, 29, and 31 electrical specifications addition of characteristics curves chapter 24, 26, 28, 30, and 32 characteristics curves addition of package drawings chapter 33 package drawings addition of recommended soldering conditions chapter 34 recommended soldering conditions third edition overall revision of description on development tools deletion of embedded software appendix a development tools change of related documents introduction ? deletion of smb from block diagram in 1.8 chapter 1 general ( pd789167 and 789177 subseries) ? deletion of p60 to p67 from table 6-3 port mode register and output latch settings for using alternate functions chapter 6 port functions ? modification of figures 8-6 timi ng of timer interrupt operation and 8- 8 timer output timing chapter 8 16-bit timer 90 ? change of description of cautions in 9.5 notes on using 8-bit timer/event counters 80 to 82 chapter 9 8-bit timer/event counters 80 to 82 ? modification of notes in figure 12-2 format of a/d converter mode register 0 chapter 12 8-bit a/d converter ( pd789167 and 789167y subseries) ? modification of notes in figure 13-2 format of a/d converter mode register 0 chapter 13 10-bit a/d converter ( pd789177 and 789177y subseries) fourth edition ? modification of figure 14-1 blo ck diagram of serial interface 20 ? modification of description of cauti ons in figure 14-6 format of baud rate generator control register 20 ? addition of 14.3 (4) (c) generation of serial clock from system clock input to 3-wire serial i/o mode chapter 14 serial interface 20
appendix d revision history user?s manual u14186ej5v0ud 461 (3/3) edition revision from previous edition applied to: ? addition of description of smbm0 to 15.4.1 start condition ? addition of description of 15.4.7 (7) slave operation (after stop mode is released) ? modification of table 15-3 intsmb0 generation timing and wait control ? addition of 15.4.8 (6) start condition detection ? addition and modificati on of description of notes in figure 15-20 master slave communication example (when 9-clock wait is selected for both master and slave) and figure 15-21. slave master communication example (when 9-clock wait is selected for both master and slave) chapter 15 smb0 ( pd789167y and 789177y subseries) ? addition of caution in figure 17-2 format of interrupt request flag register chapter 17 interrupt functions ? modification of table 20-2 communication mode list and table 20- 3 pin connection list ? addition of description of pseudo 3-wire mode to figure 20-3 example of connection with dedicated flash programme r and figure 20-9 wiring example for flash writing adapter in 3-wire serial i/o mode (sio-ch1) or pseudo 3-wire mode chapter 20 flash memory version ? modification of electr ical specifications ch apters 23, 25, 27, 28, 30 electrical specifications fourth edition ? addition of chapter appendix b notes on target system design

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