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rev.1.00 oct 27, 2008 page 1 of 128 rej03b0266-0100 description the 3804 group (spec.l) is the 8-bit microcomputer based on the 740 family core technology. the 3804 group (spec.l) is designed for household products, office automation equipment, and controlling systems that require analog signal processi ng, including the a/d converter and d/a converters. features ? basic machine-language instructions ................. ........... ..... 71 ? minimum instruction execution time .......................... 0.24 s (at 16.8 mhz osci llation frequency) ? memory size rom (flash memory) ............................................ 60 k bytes ram ........... ........... ........... ........... ........... ............ ... 2048 bytes ? programmable input/output ports ....................................... 56 ? software pull-up resistors ............................................ built-in ? interrupts 21 sources, 16 vectors............................................................... (external 8, internal 12, software 1) ? timers ...................................................................... 16-bit 1 8-bit 4 (with 8-bit prescaler) ? serial interface ......... 8-bit 2 (uart or clock-synchronized) 8-bit 1 (clock-synchronized) ? pwm ....................................... 8-bit 1 (with 8-bit prescaler) ? a/d converter ........ ........... ........... .......... 10-bit 16 channels (8-bit reading enabled) ? d/a converter .......... ........... ............ ........... 8-bi t 2 channels ? watchdog timer ....................................................... 16-bit 1 ? multi-master i 2 c-bus interface.............................. 1 channel ? led direct drive port............................................................. 8 ? clock generating circuit ............................. built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) ? power source voltage [in high-speed mode] at 16.8 mhz oscillation frequency .................... 4.5 to 5.5 v at 12.5 mhz oscillation frequency .................... 4.0 to 5.5 v at 8.4 mhz oscillation frequency ...................... 2.7 to 5.5 v [in middle-speed mode] at 16.8 mhz oscillation frequency .................... 4.5 to 5.5 v at 12.5 mhz oscillation frequency .................... 2.7 to 5.5 v [in low-speed mode] at 32 khz oscillation fre quency......................... 2.7 to 5.5 v ? power dissipation in high-speed mode ........................................ 27.5 mw (typ.) (at 16.8 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode . ............ ........... ........... ..... 1200 w (typ.) (at 32 khz oscillation frequency, at 3 v power source voltage) ? operating temperature range ............................. ? 20 to 85 c ? packages sp............ ...prdp0064ba-a (64p4b) (64-pin 750 mil sdip) hp ......plqp0064kb-a (64p6q-a ) (64-pin 10 10 mm lqfp) kp ......plqp0064ga-a (64p6u-a) (64-pin 14 14 mm lqfp) wg ........ptlg0064ja-a (64f 0g) (64-pin 6 6 mm flga) ? power source voltage ................................ v cc = 2.7 to 5.5 v ? program/erase voltage ............................. v cc = 2.7 to 5.5 v ? programming method ............. .. programming in unit of byte ? erasing method ............ ........... ........... ........... .... block erasing ? program/erase control by software command ? number of times for programming/erasing ...................... 100 application camera, household a ppliance, consumer electronics, etc. 3804 group (spec.l) single-chip 8-bit cmos microcomputer rej03b0266-0100 rev.1.00 oct 27, 2008
rev.1.00 oct 27, 2008 page 2 of 128 rej03b0266-0100 3804 group (spec.l) fig. 1 pin configuration (top view) plqp 0064kb-a (64p6q-a)/plqp0064ga-a (64p6u-a) fig. 2 pin configuration (top view) (prdp0064ba-a (64p4b)) 48 p2 0 (led 0 ) M38049FFLHP/kp 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p3 5 /t x d 3 p3 4 /r x d 3 p3 1 /da 2 p3 0 /da 1 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p3 7 /s rdy3 p3 6 /s clk3 p3 3 /scl p3 2 /sda v ss x out x in p4 2 /int 1 reset cnv ss p4 0 /int 40 /x cout p4 1 /int 00 /x cin p2 7 (led 7 ) p2 2 (led 2 ) p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) p2 1 (led 1 ) p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p6 2 /an 2 p4 7 /s rdy1 /cntr 2 p5 3 /s rdy2 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 6 p1 4 p1 5 p1 7 package code : plqp0064kb-a (64p6q-a)/plqp0064ga-a (64p6u-a) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 3 /s rdy2 p5 2 /s clk2 p5 1 /s out2 p4 7 /s rdy1 / cntr 2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p4 2 /int 1 cnv ss v ss reset p4 1 /int 00 /x cin p4 0 /int 40 /x cout x in x out p5 0 /s in2 p3 0 /da 1 p3 1 /da 2 p3 2 /sda p3 3 /scl p3 4 /r x d 3 p3 5 /t x d 3 p3 6 / s clk3 p3 7 / s rdy3 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 / int 41 p1 1 / int 01 p1 3 p1 4 p1 5 p1 6 p1 7 p2 0 (led 0 ) p2 1 (led 1 ) p2 2 (led 2 ) p1 2 p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) m38049fflsp package code : prdp0064ba-a (64p4b) p2 7 (led 7 )
rev.1.00 oct 27, 2008 page 3 of 128 rej03b0266-0100 3804 group (spec.l) fig. 3 pin configuration (top view) (ptlg0064ja-a (64f0g)) 3 2 1 8 7 6 5 4 p6 1 /an 1 p6 0 /an 0 p5 5 /cntr 1 p5 2 /s clk2 p5 0 /s in2 p4 4 /r x d 1 p4 3 /int 2 cnv ss p6 5 /an 5 p6 4 /an 4 p5 6 /pwm p5 3 /s rdy2 p5 1 /s out2 p4 6 /s clk1 p4 2 /int 1 reset p6 7 /an 7 p6 6 /an 6 p5 7 /int 3 p5 4 /cntr 0 p4 7 /s rdy1 /cntr 2 p4 5 /t x d 1 p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 0 /da 1 p3 1 /da 2 p3 2 /sda p3 7 /s rdy3 p1 7 p1 4 p1 5 p1 6 p3 3 /scl p3 4 /r x d 3 p0 0 /an 8 p0 5 /an 13 p1 2 p1 3 p2 6 (led 6 )p2 7 (led 7 ) p3 5 /t x d 3 p0 1 /an 9 p0 3 /an 11 p0 6 /an 14 p1 1 /int 01 p2 5 (led 5 )p2 3 (led 3 )p2 4 (led 4 ) p3 6 /s clk3 p0 2 /an 10 p0 4 /an 12 p0 7 /an 15 p1 0 /int 41 p2 0 (led 0 )p2 1 (led 1 )p2 2 (led 2 ) p6 2 /an 2 p6 3 /an 3 v ref av ss v cc v ss x in x out abcdefgh 3 2 1 8 7 6 5 4 abcdefgh package (top view) 50 46 44 41 40 32 31 30 51 47 45 42 39 27 29 28 53 52 48 43 38 37 26 25 56 55 54 49 33 36 35 34 1 64 58 59 57 24 22 23 60 61 4 7 12 14 21 20 62 63 5 8 10 13 17 19 2 3 6 9 11 15 16 18 pin configuration (top view) package code : ptlg0064ja-a (64f0g) note : the numbers in circles corresponds wi th the number on the packages hp/kp. m38049 fflwg
rev.1.00 oct 27, 2008 page 4 of 128 rej03b0266-0100 3804 group (spec.l) table 1 performance overview parameter function number of basic instructions 71 minimum instruction execution time 0.24 s (oscillation frequency 16.8 mhz) oscillation frequency oscillation frequency 16.8 mhz (maximum) memory sizes rom 60 kbytes ram 2048 bytes i/o port p0-p6 56 pins software pull-up resistors built-in interrupt 21 sources, 16 vectors (8 external, 12 internal, 1 software) timer 8-bit 4 (with 8-bit prescaler), 16-bit 1 serial interface 8-bit 2 (uart or cloc k-synchronized) 8-bit 1 (clock-synchronized) pwm 8-bit 1 (with 8-bit prescaler) a/d converter 10-bit 16 channels (8-bit reading enabled) d/a converter 8-bit 2 channels watchdog timer 16-bit 1 multi-master i 2 c-bus interface 1 channel led direct drive port 8 (average current: 15 ma, peak current: 30 ma, total current: 90 ma) clock generating circuits built-in 2 circuits (connect to external ceramic resona tor or quartz-crystal oscillator) power source voltage in high-speed mode at 16.8 mhz 4.5 to 5.5 v at 12.5 mhz 4.0 to 5.5 v at 8.4 mhz 2.7 to 5.5 v in middle-speed mode at 16.8 mhz 4.5 to 5.5 v at 12.5 mhz 2.7 to 5.5 v in low-speed mode at 32 mhz 2.7 to 5.5 v power dissipation in high-speed mode typ. 27.5 mw (vcc = 5.0 v, f(x in ) = 16.8 mhz, ta = 25 c) in low-speed mode typ. 1200 w (vcc = 3.0 v, f(x in ) = stop, f(x cin ) = 32 khz, ta = 25 c) operating temperature range -20 to 85 c device structure cmos silicon gate package 64-pin plastic molded sdip/lqfp/flga
rev.1.00 oct 27, 2008 page 5 of 128 rej03b0266-0100 3804 group (spec.l) fig. 4 functional block diagram i 2 c prescaler x (8) timer 1 (8) prescaler 12 (8) timer x (8) timer 2 (8) reset 27 26 cnv ss cntr 0 reset input p1 (8) 41 43 45 47 42 44 46 48 i/o port p1 prescaler y (8) timer y (8) cntr 1 p2 (8) 33 35 37 39 34 36 38 40 i/o port p2 (led drive) p0 (8) 49 50 51 52 53 54 55 56 i/o port p0 d/a converter 1 (8) r a m r o m a x y s pc l pc h ps c p u v ss 32 v cc 1 d/a converter 2 (8) 0 p5 (8) 13 17 14 16 18 15 clock generating circuit x in x out main clock input main clock output functional block diagram (package: prdp0064ba-a (64p4b)) 30 31 a/d converter (10) v ref pwm (8) 2 3 av ss x cin x cout sub-clock input sub-clock output 28 29 data bus timer z (16) cntr 2 p6 (8) 46810 57911 i/o port p6 19 12 i/o port p5 int 3 si/o2 (8) si/o1 (8) p4 (8) 21 25 22 24 28 23 29 20 i/o port p4 int 00 int 1 int 2 int 40 p3 (8) 58 62 59 61 63 60 64 57 i/o port p3 si/o3 (8) int 01 int 41
rev.1.00 oct 27, 2008 page 6 of 128 rej03b0266-0100 3804 group (spec.l) pin description table 2 pin description pin name functions function except a port function v cc , v ss power source ? apply voltage of 2.7 v ? 5.5 v to v cc , and 0 v to v ss . cnv ss cnv ss input ? this pin controls the operation mode of the chip. ? normally connected to v ss . v ref reference voltage ? reference voltage input pin for a/d and d/a converters. av ss analog power source ? analog power source input pin for a/d and d/a converters. ? connect to v ss . reset reset input ? reset i nput pin for active ?l?. x in main clock input ? input and output pi ns for the clock generating circuit. ? connect a ceramic resonator or quar tz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ? when an external clock is used, co nnect the clock source to the x in pin and leave the x out pin open. x out main clock output p0 0 /an 8 ? p0 7 /an 15 i/o port p0 ? 8-bit cmos i/o port. ? i/o direction register allo ws each pin to be individually programmed as either input or output. ? cmos compatible input level. ? cmos 3-state output structure. ? pull-up control is enabled in a bit unit. ?p2 0 ? p2 7 (8 bits) are enabled to output large current for led drive. ? a/d converter input pin p1 0 /int 41 p1 1 /int 01 i/o port p1 ? interrupt input pin p1 2 ? p1 7 p2 0 (led 0 )- p2 7 (led 7 ) i/o port p2 p3 0 /da 1 p3 1 / da 2 i/o port p3 ? 8-bit cmos i/o port. ? i/o direction register allo ws each pin to be individually programmed as either input or output. ? cmos compatible input level. ?p3 2 to p3 3 can be switched between cmos compatible input level or smbus input level in the i 2 c-bus interface function. ?p3 0 , p3 1 , p3 4 ? p3 7 are cmos 3-state output structure. ?p3 2 , p3 3 are n-channel open-drain output structure. ? pull-up control of p3 0 , p3 1 , p3 4 ? p3 7 is enabled in a bit unit. ? d/a converter input pin p3 2 /sda p3 3 /scl ?i 2 c-bus interface function pins p3 4 /r x d 3 p3 5 /t x d 3 p3 6 /s clk3 p3 7 /s rdy3 ? serial i/o3 function pin p4 0 /int 40 / x cout p4 1 /int 00 / x cin i/o port p4 ? 8-bit cmos i/o port. ? i/o direction register allo ws each pin to be individually programmed as either input or output. ? cmos compatible input level. ? cmos 3-state output structure. ? pull-up control is enabled in a bit unit. ? interrupt input pin ? sub-clock generating i/o pin (resonator connected) p4 2 /int 1 p4 3 /int 2 ? interrupt input pin p4 4 /r x d 1 p4 5 /t x d 1 p4 6 /s clk1 ? serial i/o1 function pin p4 7 /s rdy1 /cntr 2 ? serial i/o1, timer z function pin p5 0 /s in2 p5 1 /s out2 p5 2 /s clk2 p5 3 /s rdy2 i/o port p5 ? serial i/o2 function pin p5 4 /cntr 0 ? timer x function pin p5 5 /cntr 1 ? timer y function pin p5 6 /pwm ? pwm output pin p5 7 /int 3 ? interrupt input pin p6 0 /an 0 ? p6 7 /an 7 i/o port p6 ? a/d converter input pin
rev.1.00 oct 27, 2008 page 7 of 128 rej03b0266-0100 3804 group (spec.l) part numbering fig. 5 part numbering m3804 9 f f sp product name package code sp : prdp0064ba-a (64p4b) hp : plqp0064kb-a (64p6q-a) kp : plqp0064ga-a (64p6u-a) wg : ptlg0064ja-a (64f0g) rom/prom size 1: 4096 bytes 2: 8192 bytes 3: 12288 bytes 4: 16384 bytes 5: 20480 bytes 6: 24576 bytes 7: 28672 bytes 8: 32768 bytes memory type f: flash memory version ram size 0: 192 bytes 1: 256 bytes 2: 384 bytes 3: 512 bytes 4: 640 bytes -: standard l: minner spec. change product 9: 36864 bytes a: 40960 bytes b: 45056 bytes c: 49152 bytes d: 53248 bytes e: 57344 bytes f: 61440 bytes 5: 768 bytes 6: 896 bytes 7: 1024 bytes 8: 1536 bytes 9: 2048 bytes l
rev.1.00 oct 27, 2008 page 8 of 128 rej03b0266-0100 3804 group (spec.l) group expansion renesas plans to expand the 3804 group (spec.l) as follows. memory size ? flash memory size .....................................................60 kbytes ? ram size ............ ........... ........... ........... ......... ........... 2048 bytes packages ? prdp0064ba-a (64p4b) ........................................... 64-pin shrink plastic-molded sdip ? plqp0064kb-a (64p6q-a) ...........................................0.5 mm-pitch plastic molded lqfp ? plqp0064ga-a (64p6u-a) ...........................................0.8 mm-pitch plastic molded lqfp ? ptlg0064ja-a (64f0g) ........................................0.65 mm-pitch plastic molded flga fig. 6 memory expansion plan note: 1. rom size includes the id code area. table 3 support products part no. rom size (bytes) ram size (bytes) package remarks m38049fflsp 57344+4096 (note) 2048 prdp0064ba-a (64p4b) v cc = 2.7 to 5.5 v M38049FFLHP plqp0064kb-a (64p6q-a) m38049fflkp plqp0064ga-a (64p6u-a) m38049fflwg ptlg0064ja-a (64f0g) memory expansion plan 512 12 k 16 k 20 k 24 k 28 k 32 k 384 768 640 8 k 1024 896 1280 1152 1408 2048 1536 rom size (bytes) ram size (bytes) 4032 3072 48 k 60 k m38049ffl
rev.1.00 oct 27, 2008 page 9 of 128 rej03b0266-0100 3804 group (spec.l) functional description central processing unit (cpu) the 3804 group (spec.l) uses the standard 740 family instruction set. refer to the 740 family software manual for details on the instruction set. machine-resident 740 family in structions are as follows: the fst and slw instructions cannot be used. the stp, wit, mul, and div instructions can be used. [accumulator (a)] the accumulator is an 8-bit regist er. data operations such as data transfer, etc. are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit re gister. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit regi ster used during subroutine calls and interrupts. this register indi cates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. th e high-order 8 bits of the stack address are determined by the st ack page selection bit. if the stack page selection bit is ?0?, the high-order 8 bits becomes ?00 16 ?. if the stack page selection bi t is ?1?, the high-order 8 bits becomes ?01 16 ?. the operations of pushing register contents onto the stack and popping them from the stack are shown in figure 8. store registers other than those described in figure 7 with program when the user needs them during interrupts or subroutine calls (see table 4). [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 7 740 family cpu register structure processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag b7 b0 b15 program counter stack pointer index register y index register x accumulator a x y s pc l pc h c z i d b t v n b7 b0 b7 b0 b7 b0 b7 b0 b7 b0
rev.1.00 oct 27, 2008 page 10 of 128 rej03b0266-0100 3804 group (spec.l) fig. 8 register push and pop at interrupt generation and subroutine call interrupt request (1) m(s) (pc h ) (s) (s) ? 1 m(s) (pc l ) ( s ) ( s ) ? 1 ..... execute rts subroutine (s) (s) + 1 (pc l ) m(s) (s) (s) + 1 (pc h ) m(s) m(s) (pc h ) (s) (s) ? 1 m(s) (pc l ) (s) (s) ? 1 m(s) (ps) (s) (s) ? 1 interrupt service routine (s) (s) + 1 (ps) m(s) (s) (s) + 1 (pc l ) m(s) (s) (s) + 1 (pc h ) m(s) execute jsr ..... execute rti push return address on stack push contents of processor status register on stack i flag is set from ?0? to ?1? fetch the jump vector pop contents of processor status register from stack pop return address from stack pop return address from stack push return address on stack note 1 : condition for acceptance of an interrupt interrupt enable flag is ?1? interrupt disable flag is ?0? on-going routine table 4 push and pop instructions of accumulator or processor status register push instruction to stack p op instruction from stack accumulator pha pla processor status register php plp
rev.1.00 oct 27, 2008 page 11 of 128 rej03b0266-0100 3804 group (spec.l) [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 fl ags which decide mcu operation. branch operations can be perf ormed by testing the carry (c) flag, zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the resu lt of an immediate arithmetic operation or a data transfer is ?0 ?, and cleared if the result is anything other than ?0?. bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is ?1?. bit 3: decimal mode flag (d) the d flag determines whether additions and s ubtractions are executed in binary or decimal. binary arithmetic is executed when this flag is ?0?; decimal arithmetic is executed when it is ?1?. decimal correction is automati c in decimal mode. only the adc and sbc instructions can execute decimal arithmetic. bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always ?0?. when the brk instruction is used to generate an interrupt, the processor status register is pushed onto th e stack with the break flag set to ?1?. bit 5: index x mode flag (t) when the t flag is ?0?, arithmetic operations are performed between accumulator and memory . when the t flag is ?1?, direct arithmetic operations a nd direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to ? 128. when the bit instructio n is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 5 set and clear instructions of each bit of processor status register c flag z flag i flag d flag b flag t flag v flag n flag set instruction sec ? sei sed ? set ?? clear instruction clc ? cli cld ? clt clv ?
rev.1.00 oct 27, 2008 page 12 of 128 rej03b0266-0100 3804 group (spec.l) [cpu mode register (cpum)] 003b 16 the cpu mode register contains th e stack page sele ction bit, the internal system clock control bits, etc. the cpu mode register is allocated at address 003b 16 . fig. 9 structure of cpu mode register cpu mode register (cpum: address 003b 16 ) b7 b0 stack page selection bit 0 : 0 page 1 : 1 page processor mode bits b1 b0 0 0 : single-chip mode 01: 1 0 : not available 11: main clock division ratio selection bits b7 b6 00: = f(x in )/2 (high-speed mode) 01: = f(x in )/8 (middle-speed mode) 10: = f(x cin )/2 (low-speed mode) 1 1 : not available fix this bit to ?1?. 1 port x c switch bit 0 : i/o port function (stop oscillating) 1:x cin -x cout oscillating function main clock (x in -x out ) stop bit 0 : oscillating 1 : stopped
rev.1.00 oct 27, 2008 page 13 of 128 rej03b0266-0100 3804 group (spec.l) misrg (1) bit 0 of address 0010 16 : oscillation stabilizing time set after stp instruction released bit when the mcu stops the clock os cillation by the stp instruction and the stp instruction has been released by an external interrupt source, usually, the fixed values of timer 1 and prescaler 12 (timer 1 = 01 16 , prescaler 12 = ff 16 ) are automatically reloaded in orde r for the oscillation to stabilize. the user can inhibit the automati c setting by settin g ?1? to bit 0 of misrg (address 0010 16 ). however, by setting this bit to ?1?, the previous values, set just before the stp instruction was executed, will remain in timer 1 and prescaler 12. therefore, you wi ll need to set an appropriate value to each register, in ac cordance with the oscillation stabilizing time, before exec uting the stp instruction. figure 10 shows the structure of misrg. (2) bits 1, 2, 3 of address 0010 16 : middle-speed mode automatic swit ch function in order to switch the clock mode of an mcu which has a sub- clock, the following pr ocedure is necessary: set cpu mode register (003b 16 ) --> start main clock oscillation --> wait for oscillation stabilizat ion --> switch to middle-speed mode (or high-speed mode). however, the 3804 group (spec.l) has the built-in function which automatically switches from low to middle-speed mode by program. ? middle-speed mode automatic switch by program the middle-speed mode can also be automatically switched by program while operating in lo w-speed mode. by setting the middle-speed automatic switch start bit (bit 3) of misrg (address 0010 16 ) to ?1? in the condit ion that the middle-speed mode automatic switch set bit is ?1? while operating in low- speed mode, the mcu will automatically switch to middle-speed mode. in this case, the oscillation stabilizing time of the main clock can be selected by the mi ddle-speed automatic switch wait time set bit (bit 2) of misrg (address 0010 16 ). fig. 10 structure of misrg misrg (misrg: address 0010 16 ) b7 b0 oscillation stabilizing time set after stp instruction released bit 0 : automatically set ?01 16 ? to timer 1, ?ff 16 ? to prescaler 12 1 : automatically set disabled middle-speed mode automatic switch set bit 0 : not set automatically 1 : automatic switching enabled (1) middle-speed mode automatic switch wait time set bit 0 : 4.5 to 5.5 machine cycles 1 : 6.5 to 7.5 machine cycles middle-speed mode automatic switch start bit (depending on program) 0 : invalid 1 : automatic switch start (1) not used (return ?0? when read) (do not write ?1? to this bit) note 1 : when automatic switch to middle-speed mode from low-speed mode occurs, the values of cpu mode register (3b 16 ) change.
rev.1.00 oct 27, 2008 page 14 of 128 rej03b0266-0100 3804 group (spec.l) memory ? special function register (sfr) area the special function register area in the zero page contains control registers such as i/o ports and timers. ? ram the ram is used for data st orage and for stack area of subroutine calls and interrupts. ?rom the rom area can program/erase. ? interrupt vector area the interrupt vector area contai ns reset and interrupt vectors. ? zero page access to this area with only 2 bytes is possible in the zero page addressing mode. ? special page access to this area with only 2 bytes is possible in the special page addressing mode. since the contents of ram are undefi ned at reset, be sure to set an initial value before use. fig. 11 memory map diagram ram area ram size (bytes) address xxxx 16 192 256 384 512 640 768 896 1024 1536 2048 00ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 rom area rom size (bytes) address yyyy 16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 f000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 ram rom 0100 16 0000 16 0040 16 0ff0 16 ff00 16 ffdc 16 fffe 16 ffff 16 xxxx 16 yyyy 16 sfr area interrupt vector area zero page special page reserved rom area not used 0fff 16 sfr area not used reserved rom area (rom code protect) reserved rom area (id code) ffdb 16 ffd4 16
rev.1.00 oct 27, 2008 page 15 of 128 rej03b0266-0100 3804 group (spec.l) fig. 12 memory map of special function register (sfr) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) timer 12, x count source selection register (t12xcss) timer y, z count source selection register (tyzcss) misrg i 2 c data shift register (s0) i 2 c special mode status register (s3) i 2 c status register (s1) i 2 c control register (s1d) i 2 c clock control register (s2) i 2 c start/stop condition control register (s2d) i 2 c special mode control register (s3d) transmit/receive buffer register 1 (tb1/rb1) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart1 control register (uart1con) baud rate generator (brg1) serial i/o2 control register (sio2con) watchdog timer control register (wdtcon) serial i/o2 register (sio2) prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) timer z low-order (tzl) timer z high-order (tzh) timer z mode register (tzm) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) baud rate generator 3 (brg3) transmit/receive buffer register 3 (tb3/rb3) serial i/o3 status register (sio3sts) serial i/o3 control register (sio3con) uart3 control register (uart3con) ad/da control register (adcon) ad conversion register 1 (ad1) da1 conversion register (da1) da2 conversion register (da2) ad conversion register 2 (ad2) interrupt source selection register (intsel) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) note 1 : do not write any data to t hese addresses, because these are reserved area. 0fe0 16 0fe1 16 0fe2 16 0fe3 16 0fe4 16 0fe5 16 0fe6 16 0fe7 16 0fe8 16 0fe9 16 0fea 16 0feb 16 0fec 16 0fed 16 0fee 16 0fef 16 0ff0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 0ff6 16 0ff7 16 0ff8 16 0ff9 16 flash memory control register 0 (fmcr0) flash memory control register 1 (fmcr1) flash memory control register 2 (fmcr2) reserved (1) reserved (1) reserved (1) reserved (1) reserved (1) reserved (1) reserved (1) reserved (1) reserved (1) reserved (1) reserved (1) reserved (1) reserved (1) port p0 pull-up control register (pull0) port p1 pull-up control register (pull1) port p2 pull-up control register (pull2) port p3 pull-up control register (pull3) port p4 pull-up control register (pull4) port p5 pull-up control register (pull5) port p6 pull-up control register (pull6) i 2 c slave address register 0 (s0d0) i 2 c slave address register 1 (s0d1) i 2 c slave address register 2 (s0d2)
rev.1.00 oct 27, 2008 page 16 of 128 rej03b0266-0100 3804 group (spec.l) i/o ports the i/o ports have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, and each pin can be set to be input port or output port. when ?0? is written to the bit corresponding to a pin, that pin becomes an input pin. when ?1? is written to that bit, that pin becomes an output pin. if data is read from a pin which is set to output, the value of the port output latch is read, not the va lue of the pin it self. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. by setting the port p0 pull-up control register (address 0ff0 16 ) to the port p6 pull-up control register (address 0ff6 16 ) ports can control pull-up with a program. however, the contents of these registers do not affect ports programmed as the output ports. notes: 1. refer to the applicable sections how to us e double-function ports as function i/o ports. 2. make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a current will flow from v cc to v ss through the input-stage gate. table 6 i/o port function pin name input/ output i/o structure non-port function related sfrs ref. no. p0 0 /an 8 ? p0 7 /an 15 port p0 input/output, individual bits cmos compatible input level cmos 3-state output a/d converter input ad/da control register (1) p1 0 /int 41 p1 1 /int 01 port p1 external interrupt input interrupt edge selection register (2) p1 2 ? p1 7 (3) p2 0 (led 0 ) ? p2 7 (led 7 ) port p2 p3 0 /da 1 p3 1 /da 2 port p3 d/a converter output ad/da control register (4) p3 2 /sda p3 3 /scl cmos compatible input level n-channel open-drain output cmos/smbus input level (when selecting i 2 c-bus interface function) i 2 c-bus interface function i/o i 2 c control register (5) p3 4 /r x d 3 p3 5 /t x d 3 p3 6 /s clk3 p3 7 /s rdy3 cmos compatible input level cmos 3-state output serial i/o3 function i/o serial i/o3 control register uart3 control register (6) (7) (8) (9) p4 0 /int 40 / x cout p4 1 /int 00 / x cin port p4 external interrupt input sub-clock generating circuit interrupt edge selection register cpu mode register (10) (11) p4 2 /int 1 p4 3 /int 2 external interrupt input interrupt edge selection register (2) p4 4 /r x d 1 p4 5 /t x d 1 p4 6 /s clk1 serial i/o1 function i/o serial i/o1 control register uart1 control register (6) (7) (8) p4 7 /s rdy1 /cntr 2 serial i/o1 function i/o timer z function i/o serial i/o1 control register timer z mode register (12) p5 0 /s in2 p5 1 /s out2 p5 2 /s clk2 p5 3 /s rdy2 port p5 serial i/o2 function i/o serial i/o2 control register (13) (14) (15) (16) p5 4 /cntr 0 p5 5 /cntr 1 timer x, y function i/o timer xy mode register (17) p5 6 /pwm pwm output pwm control register (18) p5 7 /int 3 external interrupt input interrupt edge selection register (2) p6 0 /an 0 ? p6 7 /an 7 port p6 a/d converter input ad/da control register (1)
rev.1.00 oct 27, 2008 page 17 of 128 rej03b0266-0100 3804 group (spec.l) fig. 13 port block diagram (1) i 2 c-bus interface enable bit sda output scl output sda input scl input (5) ports p3 2 , p3 3 (7) ports p3 5 , p4 5 (4) ports p3 0 , p3 1 data bus a/d converter input (1) ports p0 , p6 (6) ports p3 4 , p4 4 serial i/o enable bit (2) ports p1 0 , p1 1 , p4 2 , p4 3 , p5 7 (3) ports p1 2 to p1 7 , p2 serial i/o output p-channel output disable bit (8) ports p3 6 , p4 6 pull-up control bit pull-up control bit port latch direction register pull-up control bit data bus port latch direction register data bus port latch direction register analog input pin selection bit data bus interrupt input pull-up control bit port latch direction register data bus pull-up control bit port latch direction register data bus d/a converter output pull-up control bit port latch direction register da 1 output enable bit (p3 0 ) da 2 output enable bit (p3 1 ) serial i/o input receive enable bit serial i/o enable bit transmit enable bit serial i/o mode selection bit serial i/o clock output serial i/o external clock input serial i/o enable bit pull-up control bit data bus port latch direction register serial i/o synchronous clock selection bit serial i/o enable bit data bus port latch direction register
rev.1.00 oct 27, 2008 page 18 of 128 rej03b0266-0100 3804 group (spec.l) fig. 14 port block diagram (2) (13) port p5 0 (12) port p4 7 (9) port p3 7 (14) port p5 1 (10) port p4 0 (11) port p4 1 int 40 interrupt input serial i/o3 mode selection bit serial i/o3 ready output serial i/o3 enable bit pull-up control bit data bus port latch direction register s rdy3 output enable bit port x c switch bit pull-up control bit data bus port latch direction register port x c switch bit int 00 interrupt input port x c switch bit pull-up control bit data bus port latch direction register sub-clock generating circuit input timer output cntr 2 interrupt input pull-up control bit data bus port latch direction register serial i/o2 output pull-up control bit data bus port latch direction register serial i/o2 transm it completion signal serial i/o2 port selection bit pull-up control bit data bus port latch direction register serial i/o2 input serial i/o1 mode selection bit serial i/o1 enable bit s rdy1 output enable bit bit 2 bit 1 bit 0 timer z operating mode bits serial i/o1 ready output p-channel output disable bit port x c switch bit
rev.1.00 oct 27, 2008 page 19 of 128 rej03b0266-0100 3804 group (spec.l) fig. 15 port block diagram (3) (18) port p5 6 (15) port p5 2 (16) port p5 3 (17) ports p5 4 , p5 5 cntr interrupt input pull-up control bit data bus port latch direction register pwm output pwm function enable bit pull-up control bit data bus port latch direction register serial i/o2 clock output pull-up control bit data bus port latch direction register serial i/o2 port selection bit serial i/o2 synchronous clock selection bit serial i/o2 external clock input serial i/o2 ready output pull-up control bit data bus port latch direction register s rdy2 output enable bit pulse output mode timer output
rev.1.00 oct 27, 2008 page 20 of 128 rej03b0266-0100 3804 group (spec.l) fig. 16 structure of port pull-up control register (1) b7 b0 port p0 pull-up control register (pull0: address 0ff0 16 ) p0 0 pull-up control bit 0: no pull-up 1: pull-up p0 1 pull-up control bit 0: no pull-up 1: pull-up p0 2 pull-up control bit 0: no pull-up 1: pull-up p0 3 pull-up control bit 0: no pull-up 1: pull-up p0 4 pull-up control bit 0: no pull-up 1: pull-up p0 5 pull-up control bit 0: no pull-up 1: pull-up p0 6 pull-up control bit 0: no pull-up 1: pull-up p0 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 port p1 pull-up control register (pull1: address 0ff1 16 ) p1 0 pull-up control bit 0: no pull-up 1: pull-up p1 1 pull-up control bit 0: no pull-up 1: pull-up p1 2 pull-up control bit 0: no pull-up 1: pull-up p1 3 pull-up control bit 0: no pull-up 1: pull-up p1 4 pull-up control bit 0: no pull-up 1: pull-up p1 5 pull-up control bit 0: no pull-up 1: pull-up p1 6 pull-up control bit 0: no pull-up 1: pull-up p1 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected.
rev.1.00 oct 27, 2008 page 21 of 128 rej03b0266-0100 3804 group (spec.l) fig. 17 structure of port pull-up control register (2) b7 b0 port p2 pull-up control register (pull2: address 0ff2 16 ) p2 0 pull-up control bit 0: no pull-up 1: pull-up p2 1 pull-up control bit 0: no pull-up 1: pull-up p2 2 pull-up control bit 0: no pull-up 1: pull-up p2 3 pull-up control bit 0: no pull-up 1: pull-up p2 4 pull-up control bit 0: no pull-up 1: pull-up p2 5 pull-up control bit 0: no pull-up 1: pull-up p2 6 pull-up control bit 0: no pull-up 1: pull-up p2 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 port p3 pull-up control register (pull3: address 0ff3 16 ) p3 0 pull-up control bit 0: no pull-up 1: pull-up p3 1 pull-up control bit 0: no pull-up 1: pull-up not used (return ?0? when read) p3 4 pull-up control bit 0: no pull-up 1: pull-up p3 5 pull-up control bit 0: no pull-up 1: pull-up p3 6 pull-up control bit 0: no pull-up 1: pull-up p3 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected.
rev.1.00 oct 27, 2008 page 22 of 128 rej03b0266-0100 3804 group (spec.l) fig. 18 structure of port pull-up control register (3) b7 b0 port p4 pull-up control register (pull4: address 0ff4 16 ) p4 0 pull-up control bit 0: no pull-up 1: pull-up p4 1 pull-up control bit 0: no pull-up 1: pull-up p4 2 pull-up control bit 0: no pull-up 1: pull-up p4 3 pull-up control bit 0: no pull-up 1: pull-up p4 4 pull-up control bit 0: no pull-up 1: pull-up p4 5 pull-up control bit 0: no pull-up 1: pull-up p4 6 pull-up control bit 0: no pull-up 1: pull-up p4 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected. b7 b0 port p5 pull-up control register (pull5: address 0ff5 16 ) p5 0 pull-up control bit 0: no pull-up 1: pull-up p5 1 pull-up control bit 0: no pull-up 1: pull-up p5 2 pull-up control bit 0: no pull-up 1: pull-up p5 3 pull-up control bit 0: no pull-up 1: pull-up p5 4 pull-up control bit 0: no pull-up 1: pull-up p5 5 pull-up control bit 0: no pull-up 1: pull-up p5 6 pull-up control bit 0: no pull-up 1: pull-up p5 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port direction register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected.
rev.1.00 oct 27, 2008 page 23 of 128 rej03b0266-0100 3804 group (spec.l) fig. 19 structure of port pull-up control register (4) b7 b0 port p6 pull-up control register (pull6: address 0ff6 16 ) p6 0 pull-up control bit 0: no pull-up 1: pull-up p6 1 pull-up control bit 0: no pull-up 1: pull-up p6 2 pull-up control bit 0: no pull-up 1: pull-up p6 3 pull-up control bit 0: no pull-up 1: pull-up p6 4 pull-up control bit 0: no pull-up 1: pull-up p6 5 pull-up control bit 0: no pull-up 1: pull-up p6 6 pull-up control bit 0: no pull-up 1: pull-up p6 7 pull-up control bit 0: no pull-up 1: pull-up note : pull-up control is valid when the corresponding bit of the port directi on register is ?0? (input). when that bit is ?1? (output), pull-up cannot be set to the port of which pull-up is selected.
rev.1.00 oct 27, 2008 page 24 of 128 rej03b0266-0100 3804 group (spec.l) termination of unused pins ? termination of common pins i/o ports: select an input port or an output port and follow each processing method. in addition, it is recommended that related registers be overwritten periodically to prevent malfunctions, etc. output ports: open. input ports: if the input level become unstable, through current flow to an input circuit, and the power supply current may increase. especially, when expe cting low consumption current (at stp or wit instruction execution etc.), pull-up or pull-down input ports to prevent through current (built-in resistor can be used). we recommend processing unused pins through a resistor which can secure i oh ( avg ) or i ol ( avg ). because, when an i/o port or a pin which have an output function is selected as an input port, it may operate as an output port by incorrect operation etc. table 7 termination of unused pins pins termination p0, p1, p2, p3, p4, p5, p6 ? set to the input mode and connect each to v cc or v ss through a resistor of 1 k to 10 k . ? set to the output mode and open at ?l? or ?h? output state. v ref connect to v cc or v ss (gnd). av ss connect to v cc or v ss (gnd). x out open (only when using external clock)
rev.1.00 oct 27, 2008 page 25 of 128 rej03b0266-0100 3804 group (spec.l) interrupts the 3804 group (spec.l) interrupts are vector interrupts with a fixed priority scheme, and ge nerated by 16 sources among 24 sources: 10 external, 13 internal, and 1 software. the interrupt sources, vector addresses (1) , and interrupt priority are shown in table 8. each interrupt except the brk instruction interrupt has the interrupt request bit and the interr upt enable bit. these bits and the interrupt disable flag (i flag) control the acceptance of interrupt requests. figu re 20 shows an interrupt control diagram. an interrupt requests is accept ed when all of the following conditions are satisfied: ? interrupt disable flag.................................?0? ? interrupt request bit...................................?1? ? interrupt enable bit....................................?1? though the interrupt priority is determined by hardware, priority processing can be performed by software using the above bits and flag. notes: 1. vector addresses contain interrupt jump destination addresses. 2. reset function in the same way as an interrupt with the highest priority. table 8 interrupt vector addresses and priority interrupt source priority vector addresses (1) interrupt request generating conditions remarks high low reset (2) 1fffd 16 fffc 16 at reset non-maskable int 0 2fffb 16 fffa 16 at detection of either rising or falling edge of int 0 input external interrupt (active edge selectable) timer z at timer z underflow int 1 3 fff9 16 fff8 16 at detection of either rising or falling edge of int 1 input external interrupt (active edge selectable) serial i/o1 reception 4 fff7 16 fff6 16 at completion of serial i/o1 data reception valid when serial i/o1 is selected serial i/o1 transmission 5 fff5 16 fff4 16 at completion of serial i/o1 transmission shift or when transmission buffer is empty valid when serial i/o1 is selected scl, sda at detection of either rising or falling edge of scl or sda external interrupt (active edge selectable) timer x 6 fff3 16 fff2 16 at timer x underflow timer y 7 fff1 16 fff0 16 at timer y underflow timer 1 8 ffef 16 ffee 16 at timer 1 underflow stp release timer underflow timer 2 9 ffed 16 ffec 16 at timer 2 underflow cntr 0 10 ffeb 16 ffea 16 at detection of either rising or falling edge of cntr 0 input external interrupt (active edge selectable) scl, sda at detection of either rising or falling edge of scl or sda external interrupt (active edge selectable) cntr 1 11 ffe9 16 ffe8 16 at detection of either rising or falling edge of cntr 1 input external interrupt (active edge selectable) serial i/o3 reception at completion of serial i/o3 data reception valid when serial i/o3 is selected serial i/o2 12 ffe7 16 ffe6 16 at completion of serial i/o2 data transmission or reception valid when serial i/o2 is selected timer z at timer z underflow int 2 13 ffe5 16 ffe4 16 at detection of either rising or falling edge of int 2 input external interrupt (active edge selectable) i 2 c at completion of data transfer int 3 14 ffe3 16 ffe2 16 at detection of either rising or falling edge of int 3 input external interrupt (active edge selectable) int 4 15 ffe1 16 ffe0 16 at detection of either rising or falling edge of int 4 input external interrupt (active edge selectable) cntr 2 at detection of either rising or falling edge of cntr 2 input external interrupt (active edge selectable) a/d conversion 16 ffdf 16 ffde 16 at completion of a/d conversion serial i/o3 transmission at completion of serial i/o3 transmission shift or when transmission buffer is empty valid when serial i/o3 is selected brk instruction 17 ffdd 16 ffdc 16 at brk instruction execution non-maskable software interrupt
rev.1.00 oct 27, 2008 page 26 of 128 rej03b0266-0100 3804 group (spec.l) fig. 20 interrupt control diagram ? interrupt disable flag the interrupt disable flag is as signed to bit 2 of the processor status register. this flag contro ls the acceptance of all interrupt requests except for the brk instruction. when this flag is set to ?1?, the acceptance of interrupt requests is disabled. when it is set to ?0?, acceptance of interrupt requests is enabled. this flag is set to ?1? with the set instruction and set to ?0? with the cli instruction. when an interrupt request is accepted, the contents of the processor status register are pu shed onto the stack while the interrupt disable flag remains set to ?0?. subsequently, this flag is automatically set to ?1? and multiple interrupts are disabled. to use multiple interrupts, set this flag to ?0? with the cli instruction within the inte rrupt processing routine. the contents of the processor stat us register are popped off the stack with the rti instruction. ? interrupt request bits once an interrupt request is generate d, the corresponding interrupt request bit is set to ?1? and remains ?1? until the request is accepted. when the request is accepted, this bit is automatically set to ?0?. each interrupt request bit can be set to ?0?, but cannot be set to ?1?, by software. ? interrupt enable bits the interrupt enable bits control the acceptance of the corresponding interrupt requests. wh en an interrupt enable bit is set to ?0?, the acceptance of th e corresponding interrupt request is disabled. if an interrupt reque st occurs in this condition, the corresponding interrupt request bit is set to ?1?, but the interrupt request is not accepted. when an in terrupt enable bit is set to ?1?, acceptance of the corresponding interrupt request is enabled. each interrupt enable bit can be set to ?0? or ?1? by software. the interrupt enable bit for an unused interrupt should be set to ?0?. ? interrupt source selection any of the following combinati ons can be selected by the interrupt source selection register (0039 16 ). 1. int0 or timer z 2. serial i/o1 transm ission or scl, sda 3. cntr 0 or scl, sda 4. cntr 1 or serial i/ o3 reception 5. serial i/o2 or timer z 6. int 2 or i 2 c 7. int 4 or cntr 2 8. a/d conversion or seri al i/o3 transmission ? external interrupt pin selection for external interrupts int 0 and int 4 , the int 0 , int 4 interrupt switch bit in the interrupt edge se lection register (b it 6 of address 003a 16 ) can be used to select int 00 and int 40 pin input or int 01 and int 41 pin input. interrupt disable flag (i) interrupt request interrupt request bit interrupt enable bit brk instruction reset
rev.1.00 oct 27, 2008 page 27 of 128 rej03b0266-0100 3804 group (spec.l) fig. 21 structure of interrupt-related registers interrupt edge selection register (intedge : address 003a 16 ) int 0 interrupt edge selection bit int 1 interrupt edge selection bit not used (returns ?0? when read) int 2 interrupt edge selection bit int 3 interrupt edge selection bit int 4 interrupt edge selection bit int 0 , int 4 interrupt switch bit 0 : int 00 , int 40 interrupt 1 : int 01 , int 41 interrupt not used (returns ?0? when read) 0 : falling edge active 1 : rising edge active interrupt request register 1 (ireq1 : address 003c 16 ) int 0 /timer z interrupt request bit int 1 interrupt request bit serial i/o1 receive interrupt request bit serial i/o1 transmit/scl,sda interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit interrupt request register 2 (ireq2 : address 003d 16 ) cntr 0 /scl,sda interrupt request bit cntr 1 /serial i/o3 receive interrupt request bit serial i/o2/timer z interrupt request bit int 2 /i 2 c interrupt request bit int 3 interrupt request bit int 4 /cntr 2 interrupt request bit ad converter/serial i/o3 transmit interrupt request bit not used (returns ?0? when read) interrupt control register 1 (icon1 : address 003e 16 ) int 0 /timer z interrupt enable bit int 1 interrupt enable bit serial i/o1 receive interrupt enable bit serial i/o1 transmit/scl,sda interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit interrupt control register 2 (icon2 : address 003f 16 ) b7 b0 b7 b0 b7 b0 b7 b0 0 : falling edge active 1 : rising edge active cntr 0 /scl,sda interrupt enable bit cntr 1 /serial i/o3 receive interrupt enable bit serial i/o2/timer z interrupt enable bit int 2 /i 2 c interrupt enable bit int 3 interrupt enable bit int 4 /cntr 2 interrupt enable bit ad converter/serial i/o3 transmit interrupt enable bit not used (returns ?0? when read) (do not write ?1?.) b7 b0 interrupt source selection register (intsel : address 0039 16 ) int 0 /timer z interrupt source selection bit 0 : int 0 interrupt 1 : timer z interrupt serial i/o2/timer z interrupt source selection bit 0 : serial i/o2 interrupt 1 : timer z interrupt serial i/o1 transmit/scl, sda interrupt source selection bit 0 : serial i/o1 transmit interrupt 1 : scl, sda interrupt cntr 0 /scl, sda interrupt source selection bit 0 : cntr 0 interrupt 1 : scl, sda interrupt int 4 /cntr 2 interrupt source selection bit 0 : int 4 interrupt 1 : cntr 2 interrupt int 2 /i 2 c interrupt source selection bit 0 : int 2 interrupt 1 : i 2 c interrupt cntr 1 /serial i/o3 receive interrupt source selection bit 0 : cntr 1 interrupt 1 : serial i/o3 receive interrupt ad converter/serial i/o3 transmit interrupt source selection bit 0 : a/d converter interrupt 1 : serial i/o3 transmit interrupt (do not write ?1? to these bits simultaneously.) b7 b0 (do not write ?1? to these bits simultaneously.) 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : interrupts disabled 1 : interrupts enabled 0 : interrupts disabled 1 : interrupts enabled
rev.1.00 oct 27, 2008 page 28 of 128 rej03b0266-0100 3804 group (spec.l) ? interrupt request generati on, acceptance, and handling interrupts have the following three phases. (i) interrupt request generation an interrupt request is gene rated by an interrupt source (external interrupt signal input, timer underflow, etc.) and the corresponding request bit is set to ?1?. (ii) interrupt request acceptance based on the interrupt acceptance timing in each instruction cycle, the interrupt control circuit determines acceptance conditions (interrupt request b it, interrupt enable bit, and interrupt disable flag) and in terrupt priority levels for accepting interrupt requests. when two or more interrupt requests are generated simultan eously, the highest priority interrupt is accepted. the valu e of interrupt request bit for an unaccepted interrupt remains the same and acceptance is determined at the next inte rrupt acceptance timing point. (iii) handling of accept ed interrupt request the accepted interrupt request is processed. figure 22 shows the time up to execution in the interrupt processing routine, and figure 23 shows the interrupt sequence. figure 24 shows the timing of interrupt request generation, interrupt request bi t, and interrupt re quest acceptance. ? interrupt handling execution when interrupt handlin g is executed, the following operations are performed automatically. (1) once the currently executing instruction is completed, an interrupt request is accepted. (2) the contents of the program counters and the processor status register at this point are pushed onto the stack area in order from 1 to 3. 1. high-order bits of program counter (pch) 2. low-order bits of program counter (pcl) 3. processor status register (ps) (3) concurrently with the push operation, the jump address of the corresponding interrupt (the start address of the interrupt processing routine) is transferred from the interrupt vector to the program counter. (4) the interrupt reque st bit for the corresponding interrupt is set to ?0?. also, the interrupt disable flag is set to ?1? and multiple interrupts are disabled. (5) the interrupt routine is executed. (6) when the rti instruction is executed, the contents of the registers pushed onto the stack area are popped off in the order from 3 to 1. then, the routine that was before running interrupt processing resumes. as described above, it is necess ary to set the stack pointer and the jump address in the vect or area corresponding to each interrupt to execute the interrupt processing routine. the interrupt request bit may be set to ?1? in the following cases. ? when setting the external interrupt active edge related registers: interrupt edge selection register (address 003a 16) timer xy mode register (address 0023 16 ) timer z mode register (address 002a 16 ) i 2 c start/stop condition control register (address 0016 16 ) ? when switching the interrupt so urces of an interrupt vector address where two or more in terrupt sources are assigned related registers: interrupt source selection register (address 0039 16 ) if it is not necessary to generate an interrupt synchronized with these settings, take the following sequence. (1) set the corresponding enable bit to ?0? (disabled). (2) set the interrupt edge select ion bit (the acti ve edge switch bit) or the interrupt source bit. (3) set the corresponding interrupt request bit to ?0? after one or more instructions have been executed. (4) set the corresponding interrupt enable bit to ?1? (enabled). fig. 22 time up to execution in interrupt routine fig. 23 interrupt sequence 7 cycles interrupt request generated interrupt request acceptance interrupt routine starts interrupt sequence * 0 to 16 cycles 7 to 23 cycles * when executing div instruction main routine stack push and vector fetch interrupt handling routine sync rd wr push onto stack vector fetch address bus data bus execute interrupt routine pc s,sps s-1,sps s-2,sps b l b h a l ,a h not used pc h pc l ps a l a h sync : cpu operation code fetch cycle (this is an internal signal that cannot be observed from the external unit.) bl, bh: vector address of each interrupt al, ah: jump destination address of each interrupt sps : ?00 16 ? or ?01 16 ? ([sps] is a page selected by the stack page selection bit of cpu mode register.)
rev.1.00 oct 27, 2008 page 29 of 128 rej03b0266-0100 3804 group (spec.l) fig. 24 timing of interrupt request generation, interrupt request bit, and interrupt acceptance t1 (1) the interrupt request bit for an interrupt request generated during period 1 is set to ?1? at timing point ir1. (2) the interrupt request bit fo r an interrupt request generated during period 2 is set to ?1? at timing point ir1 or ir2. the timing point at which the bit is set to ?1? varies depending on conditions. when two or more interrupt requests are generated during the period 2, each requ est bit may be set to ?1? at timing point ir1 or ir2 separately. t1 t2 t3 : interrupt acceptance timing points ir1 ir2 : timings points at which the interrupt request bit is set to ?1?. note : period 2 indicates the last cycle during one instruction cycle. ir1 t2 sync ir2 t3 12 internal clock instruction cycle push onto stack vector fetch instruction cycle
rev.1.00 oct 27, 2008 page 30 of 128 rej03b0266-0100 3804 group (spec.l) timers ? 8-bit timers the 3804 group (spec.l) has four 8-bit timers: timer 1, timer 2, timer x, and timer y. the timer 1 and timer 2 use one prescaler in common, and the timer x and timer y use each prescaler. those are 8-bit prescalers. each of the timers and prescalers has a timer latch or a prescaler latch. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are down-counters. when the timer reaches ?00 16 ?, an underflow occurs at the next coun t pulse and the co ntents of the corresponding timer latch are reloaded into the timer and the count is continued. when th e timer underflows, the interrupt request bit corresponding to th at timer is set to ?1?. ? timer divider the divider count source is swit ched by the main clock division ratio selection bits of cpu mode register (bits 7 and 6 at address 003b 16 ). when these bits are ?00? (high-speed mode) or ?01? (middle-speed mode), x in is selected. when these bits are ?10? (low-speed mode), x cin is selected. ? prescaler 12 the prescaler 12 counts the output of the timer divider. the count source is select ed by the timer 12, x c ount source selection register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024 of f(x in ) or f(x cin ). ? timer 1 and timer 2 the timer 1 and timer 2 counts the output of prescaler 12 and periodically set the in terrupt request bit. ? prescaler x and prescaler y the prescaler x and prescaler y count the output of the timer divider or f(x cin ). the count source is selected by the timer 12, x count source selectio n register (address 000e 16 ) and the timer y, z count source selection register (address 000f 16 ) among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/12 8, 1/256, 1/512, and 1/1024 of f(x in ) or f(x cin ); and f(x cin ). ? timer x and timer y the timer x and timer y can each select one of four operating modes by setting the timer xy mode regi ster (address 0023 16 ). (1) timer mode ? mode selection this mode can be selected by setting ?00? to the timer x operating mode bits (bits 1 a nd 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). ? explanation of operation the timer count operati on is started by setting ?0? to the timer x count stop bit (bit 3) and the timer y count stop bit (bit 7) of the timer xy mode register (address 0023 16 ). when the timer reaches ?00 16 ?, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the count is continued. (2) pulse output mode ? mode selection this mode can be selected by setting ?01? to the timer x operating mode bits (bits 1 a nd 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). ? explanation of operation the operation is the same as the timer mode?s. moreover the pulse which is inverted each time the timer underflows is output from cntr 0 /cntr 1 pin. regardless of the timer counting or not the output of cntr 0 /cntr 1 pin is initialized to the level of specified by their active edge sw itch bits when writing to the timer. when the cntr 0 active edge switch bit (bit 2) and the cntr 1 active edge switch bit (bit 6) of the timer xy mode register (address 0023 16 ) is ?0?, the output starts with ?h? level. when it is ?1?, the output starts with ?l? level. switching the cntr 0 or cntr 1 active edge switch bit will reverse the output level of the corresponding cntr 0 or cntr 1 pin. ? precautions set the double-function port of cntr 0 /cntr 1 pin and port p5 4 /p5 5 to output in this mode. (3) event counter mode ? mode selection this mode can be selected by setting ?10? to the timer x operating mode bits (bits 1 a nd 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). ? explanation of operation the operation is the same as the timer mode?s except that the timer counts signals input from the cntr 0 or cntr 1 pin. the valid edge for the count operation depends on the cntr 0 active edge switch bit (bit 2) or the cntr 1 active edge sw itch bit (bit 6) of the timer xy mode register (address 0023 16 ). when it is ?0?, the rising edge is valid. when it is ?1?, the falling edge is valid. ? precautions set the double-function port of cntr 0 /cntr 1 pin and port p5 4 /p5 5 to input in this mode.
rev.1.00 oct 27, 2008 page 31 of 128 rej03b0266-0100 3804 group (spec.l) (4) pulse width measurement mode ? mode selection this mode can be selected by setting ?11? to the timer x operating mode bits (bits 1 a nd 0) and the timer y operating mode bits (bits 5 and 4) of the timer xy mode register (address 0023 16 ). ? explanation of operation when the cntr 0 active edge switch b it (bit 2) or the cntr 1 active edge switch bit (bit 6) of the timer xy mode register (address 0023 16 ) is ?1?, the timer counts during the term of one falling edge of cntr 0 /cntr 1 pin input until the next rising edge of input (?l? term). when it is ?0?, the timer counts during the term of one rising edge input until the next falling edge input (?h? term). ? precautions set the double-function port of cntr 0 /cntr 1 pin and port p5 4 /p5 5 to input in this mode. the count operation can be stopped by setting ?1? to the timer x count stop bit (bit 3) and the timer y count stop bit (bit 7) of the timer xy mode register (address 0023 16 ). the interrupt request bit is set to ?1? each time the timer underflows. ? precautions when sw itching count source when switching the count source by the timer 12, x and y count source selection bits, the value of timer count is altered in inconsiderable amount owing to ge nerating of thin pulses on the count input signals. therefore, select the timer count source before setting the value to the prescaler and the timer.
rev.1.00 oct 27, 2008 page 32 of 128 rej03b0266-0100 3804 group (spec.l) fig. 25 block diagram of timer x, timer y, timer 1, and timer 2 q q ?1? ?0? p5 4 /cntr 0 q q p5 5 /cntr 1 ?0? ?1? r r ?1? ?0? ?0? ?1? t t prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) to timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode to cntr 0 interrupt request bit pulse output mode port p5 4 latch port p5 4 direction register cntr 0 active edge switch bit timer x latch write pulse pulse output mode timer mode pulse output mode prescaler y latch (8) prescaler y (8) timer y latch (8) timer y (8) to timer y interrupt request bit toggle flip-flop timer y count stop bit to cntr 1 interrupt request bit pulse output mode port p5 5 latch port p5 5 direction register cntr 1 active edge switch bit timer y latch write pulse pulse output mode timer mode pulse output mode prescaler 12 latch (8) prescaler 12 (8) timer 1 latch (8) timer 1 (8) timer 2 latch (8) timer 2 (8) to timer 2 interrupt request bit to timer 1 interrupt request bit cntr 0 active edge switch bit cntr 1 active edge switch bit pulse width measurement mode event counter mode clock for timer 12 data bus data bus data bus clock for timer 12 x in (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) divider clock for timer y count source selection bit main clock division ratio selection bits ?00? ?01? ?10? x cin clock for timer x f(x cin ) count source selection bit f(x cin ) clock for timer y
rev.1.00 oct 27, 2008 page 33 of 128 rej03b0266-0100 3804 group (spec.l) fig. 26 structure of timer xy mode register b7 timer xy mode register (tm : address 0023 16 ) timer x operating mode bits b1 b0 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode cntr 0 active edge switch bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode timer x count stop bit 0: count start 1: count stop timer y operating mode bits b5 b4 0 0: timer mode 0 1: pulse output mode 1 0: event counter mode 1 1: pulse width measurement mode cntr 1 active edge switch bit 0: interrupt at falling edge count at rising edge in event counter mode 1: interrupt at rising edge count at falling edge in event counter mode timer y count stop bit 0: count start 1: count stop b0
rev.1.00 oct 27, 2008 page 34 of 128 rej03b0266-0100 3804 group (spec.l) fig. 27 structure of timer 12, x and timer y, z count source selection registers b7 b0 timer 12, x count source selection register (t12xcss : address 000e 16 ) timer 12 count sour ce selection bits b3 b2 b1 b0 0 000:f(x in )/2 or f(x cin )/2 0 001:f(x in )/4 or f(x cin )/4 0 010: f(x in )/8 or f(x cin )/8 0 011: f(x in )/16 or f(x cin )/16 0 100: f(x in )/32 or f(x cin )/32 0 101: f(x in )/64 or f(x cin )/64 0 110: f(x in )/128 or f(x cin )/128 0 111: f(x in )/256 or f(x cin )/256 1 000: f(x in )/512 or f(x cin )/512 1 001: f(x in )/1024 or f(x cin )/1024 1 0 1 0 : 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : 1 1 1 1 : not used timer x count sour ce selection bits b7 b6 b5 b4 0 000:f(x in )/2 or f(x cin )/2 0 001:f(x in )/4 or f(x cin )/4 0 010: f(x in )/8 or f(x cin )/8 0 011: f(x in )/16 or f(x cin )/16 0 100: f(x in )/32 or f(x cin )/32 0 101: f(x in )/64 or f(x cin )/64 0 110: f(x in )/128 or f(x cin )/128 0 111: f(x in )/256 or f(x cin )/256 1 000: f(x in )/512 or f(x cin )/512 1 001: f(x in )/1024 or f(x cin )/1024 1 010: f(x cin ) 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : 1 1 1 1 : not used b7 b0 timer y, z count source selection register (tyzcss : address 000f 16 ) timer y count sour ce selection bits b3 b2 b1 b0 0 000:f(x in )/2 or f(x cin )/2 0 001:f(x in )/4 or f(x cin )/4 0 010: f(x in )/8 or f(x cin )/8 0 011: f(x in )/16 or f(x cin )/16 0 100: f(x in )/32 or f(x cin )/32 0 101: f(x in )/64 or f(x cin )/64 0 110: f(x in )/128 or f(x cin )/128 0 111: f(x in )/256 or f(x cin )/256 1 000: f(x in )/512 or f(x cin )/512 1 001: f(x in )/1024 or f(x cin )/1024 1 010: f(x cin ) timer z count sour ce selection bits b7 b6 b5 b4 0 000:f(x in )/2 or f(x cin )/2 0 001:f(x in )/4 or f(x cin )/4 0 010: f(x in )/8 or f(x cin )/8 0 011: f(x in )/16 or f(x cin )/16 0 100: f(x in )/32 or f(x cin )/32 0 101: f(x in )/64 or f(x cin )/64 0 110: f(x in )/128 or f(x cin )/128 0 111: f(x in )/256 or f(x cin )/256 1 000: f(x in )/512 or f(x cin )/512 1 001: f(x in )/1024 or f(x cin )/1024 1 010: f(x cin ) 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : 1 1 1 1 : not used 1 0 1 1 : 1 1 0 0 : 1 1 0 1 : 1 1 1 0 : 1 1 1 1 : not used
rev.1.00 oct 27, 2008 page 35 of 128 rej03b0266-0100 3804 group (spec.l) ? 16-bit timer the timer z is a 16-bit timer. when the timer reaches ?0000 16 ?, an underflow occurs at th e next count pulse and the corresponding timer latc h is reloaded into the timer and the count is continued. when the timer unde rflows, the interr upt request bit corresponding to the timer z is set to ?1?. when reading/writing to the timer z, perform reading/writing to both the high-order byte and th e low-order byte. when reading the timer z, read from the high-ord er byte first, followed by the low-order byte. do not perform the writing to the timer z between read operation of the hi gh-order byte and read operation of the low-order byte. when writing to the timer z, write to the low-order byte first, followed by the high-order byte. do not perform the reading to the timer z between write operation of the low-order byte and write opera tion of the high-order byte. the timer z can select the co unt source by the timer z count source selection bits of timer y, z count source selection register (bits 7 to 4 at address 000f 16 ). timer z can select one of seve n operating modes by setting the timer z mode register (address 002a 16 ). (1) timer mode ? mode selection this mode can be selected by setting ?000? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. ? interrupt when an underflow occurs, the int 0 /timer z interrupt request bit (bit 0) of the interrupt re quest register 1 (address 003c 16 ) is set to ?1?. ? explanation of operation during timer stop, usually write data to a latch and a timer at the same time to set the timer value. the timer count operation is starte d by setting ?0? to the timer z count stop bit (bit 6) of the timer z mode register (address 002a 16 ). when the timer reaches ?0000 16 ?, an underflow occurs at the next count pulse and the contents of timer latch are reloaded into the timer and the c ount is continued. when writing data to the timer during operation, the data is written only into the latch. then the new latch value is reloaded into the timer at the next underflow. (2) event counter mode ? mode selection this mode can be selected by setting ?000? to the timer z operating mode bits (bits 2 to 0) and setting ?1? to the timer/event counter mode switch bit (bit 7) of the timer z mode register (address 002a 16 ). the valid edge for the count operation depends on the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ). when it is ?0?, the rising edge is valid. when it is ?1?, the falling edge is valid. ? interrupt the interrupt at an underflow is the same as the timer mode?s. ? explanation of operation the operation is the same as the timer mode?s. set the double-function port of cntr 2 pin and port p4 7 to input in this mode. figure 30 shows the timing chart of the timer/event counter mode. (3) pulse output mode ? mode selection this mode can be selected by setting ?001? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. ? interrupt the interrupt at an underflow is the same as the timer mode?s. ? explanation of operation the operation is the same as the timer mode?s. moreover the pulse which is inverted each time the timer underflows is output from cntr 2 pin. when the cntr 2 active edge switch bit (bit 5) of the timer z mode re gister (address 002a 16 ) is ?0?, the output starts with ?h? level. when it is ?1?, the output starts with ?l? level. ? precautions the double-function port of cntr 2 pin and port p4 7 is automatically set to the timer pulse output port in this mode. the output from cntr 2 pin is initialized to the level depending on cntr 2 active edge switch bit by writing to the timer. when the value of the cntr 2 active edge switch bit is changed, the output level of cntr 2 pin is inverted. figure 31 shows the timing char t of the pulse output mode.
rev.1.00 oct 27, 2008 page 36 of 128 rej03b0266-0100 3804 group (spec.l) (4) pulse period measurement mode ? mode selection this mode can be selected by setting ?010? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. ? interrupt the interrupt at an underflow is the same as the timer mode?s. when the pulse period meas urement is completed, the int 4 /cntr 2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003d 16 ) is set to ?1?. ? explanation of operation the cycle of the pulse which is input from the cntr 2 pin is measured. when the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ) is ?0?, the timer counts during the term from one falling edge of cntr 2 pin input to the next falling edge. when it is ?1 ?, the timer counts during the term from one rising e dge input to the next rising edge input. when the valid edge of meas urement completion/start is detected, the 1?s complement of the timer value is written to the timer latch and ?ffff 16 ? is set to the timer. furthermore when the timer unde rflows, the timer z interrupt request occurs and ?ffff 16 ? is set to the timer. when reading the timer z, the value of the timer latch (measured value) is read. the measured value is retained until the next measurement completion. ? precautions set the double-function port of cntr 2 pin and port p4 7 to input in this mode. a read-out of timer value is impossible in this mode. the timer can be written to only during timer stop (no measurement of pulse period). since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operation during measurement. ?ffff 16 ? is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. figure 32 shows the timing chart of the pulse period measurement mode. (5) pulse width measurement mode ? mode selection this mode can be selected by setting ?011? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. ? interrupt the interrupt at an underflow is the same as the timer mode?s. when the pulse widths measurement is completed, the int 4 /cntr 2 interrupt request bit (bit 5) of the interrupt request register 2 (address 003d 16 ) is set to ?1?. ? explanation of operation the pulse width which is input from the cntr 2 pin is measured. when the cntr 2 active edge switch bit (bit 5) of the timer z mode register (address 002a 16 ) is ?0?, the timer counts during the term from one rising edge input to the next falling edge input (?h? term). when it is ?1?, th e timer counts during the term from one falling edge of cntr 2 pin input to the next rising edge of input (?l? term). when the valid edge of measurement completion is detected, the 1?s complement of the timer value is written to the timer latch. when the valid edge of meas urement completion/start is detected, ?ffff 16 ? is set to the timer. when the timer z underflows, the timer z interrupt occurs and ?ffff 16 ? is set to the timer z. when reading the timer z, the value of the timer latch (measure d value) is read. the measured value is retained until the next measurement completion. ? precautions set the double-function port of cntr 2 pin and port p4 7 to input in this mode. a read-out of timer value is impossible in this mode. the timer can be written to only during timer stop (no measurement of pulse widths). since the timer latch in this mode is specialized for the read-out of measured values, do not pe rform any write operation during measurement. ?ffff 16 ? is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. consequently, the timer value at start of pulse width measurement depends on the timer value just before measurement start. figure 33 shows the timing chart of the pulse width measurement mode.
rev.1.00 oct 27, 2008 page 37 of 128 rej03b0266-0100 3804 group (spec.l) (6) programmable waveform generating mode ? mode selection this mode can be selected by setting ?100? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. in low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x cin ); or f(x cin ) can be selected as the count source. ? interrupt the interrupt at an underflow is the same as the timer mode?s. ? explanation of operation the operation is the same as the timer mode?s. moreover the timer outputs the data set in the output level latch (bit 4) of the timer z mode register (address 002a 16 ) from the cntr 2 pin each time the timer underflows. changing the value of the output level latch and the timer latch after an underflow makes it pos sible to output an optional waveform from the cntr 2 pin. ? precautions the double-function port of cntr 2 pin and port p4 7 is automatically set to the programmable waveform generating port in this mode. figure 34 shows the timing chart of the programmable waveform generating mode. (7) programmable one-shot generating mode ? mode selection this mode can be selected by setting ?101? to the timer z operating mode bits (bits 2 to 0) and setting ?0? to the timer/event counter mode switch bit (b7) of the timer z mode register (address 002a 16 ). ? count source selection in high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512 or 1/1024 of f(x in ); or f(x cin ) can be selected as the count source. ? interrupt the interrupt at an underflow is the same as the timer mode?s. the trigger to generate one-shot pulse can be selected by the int 1 active edge selection bit (bit 1) of the interrupt edge selection register (address 003a 16 ). when it is ?0?, the falling edge active is selected; when it is ?1?, the rising edge active is selected. when the valid edge of the int 1 pin is detected, the int 1 interrupt request bit (bit 1) of the interrupt request register 1 (address 003c 16 ) is set to ?1?. ? explanation of operation 1. ?h? one-shot pulse; bit 5 of timer z mode register = ?0? the output level of the cntr 2 pin is initialized to ?l? at mode selection. when trigge r generation (input signal to int 1 pin) is detected, ?h? is output from the cntr 2 pin. when an underflow occurs, ?l ? is output. the ?h? one-shot pulse width is set by the setting value to the timer z register low-order and high-order. when trigger generating is detected during timer count st op, although ?h? is output from the cntr 2 pin, ?h? output stat e continues because an underflow does not occur. 2. ?l? one-shot pulse; bit 5 of timer z mode register = ?1? the output level of the cntr 2 pin is initialized to ?h? at mode selection. when trigge r generation (input signal to int 1 pin) is detected, ?l? is output from the cntr 2 pin. when an underflow occurs, ?h? is output. the ?l? one-shot pulse width is set by the setting value to the timer z low- order and high-order. when tr igger generating is detected during timer count stop, although ?l? is output from the cntr 2 pin, ?l? output state c ontinues because an under- flow does not occur. ? precautions set the double-function port of int 1 pin and port p4 2 to input in this mode. the double-function port of cntr 2 pin and port p4 7 is automatically set to the progr ammable one-shot generating port in this mode. this mode cannot be used in low-speed mode. if the value of the cntr 2 active edge swit ch bit is changed during one-shot generating enable d or generating one-shot pulse, then the output level from cntr 2 pin changes. figure 35 shows the timing chart of the programmable one-shot generating mode.
rev.1.00 oct 27, 2008 page 38 of 128 rej03b0266-0100 3804 group (spec.l) ? timer z write control which write control can be selected by the timer z write control bit (bit 3) of the timer z mode register (address 002a 16 ), writing data to both the latch and the timer at the same time or writing data only to the latch. when the operation ?writing data on ly to the latch? is selected, the value is set to the timer latch by writing data to the address of timer z and the timer is updated at next underflow. after reset release, the operation ?w riting data to both th e latch and the timer at the same time? is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer z. in the case of writing data only to the latch, if writing data to the latch and an underflow are perform ed almost at the same time, the timer value may become undefined. ? timer z read control a read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. in the other modes, a read-out of timer value is possible regardless of count operating or stopped. however, a read-out of time r latch value is impossible. ? switch of interrupt active edge of cntr 2 and int 1 each interrupt active edge de pends on setting of the cntr 2 active edge switch bit and the int 1 active edge selection bit. ? switch of count source when switching the count sour ce by the timer z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. therefore, select the timer count source before setting the value to the prescaler and the timer. ? usage of cntr 2 pin as normal i/o port p4 7 to use the cntr 2 pin as normal i/o port p4 7 , set timer z operating mode bits (b2, b1, b0) of timer z mode register (address 002a 16 ) to ?000?. fig. 28 block diagram of timer z p4 7 /s rdy2 / cntr 2 ?001? x in output level latch programmable one-shot generating mode cntr 2 active edge switch bit programmable one-shot generating mode data bus to timer z interrupt request bit to int 1 interrupt request bit programmable waveform generating mode pulse output mode cntr 2 active edge switch bit pulse output mode timer z operating mode bits port p4 7 direction register port p4 7 latch pulse period measurement mode pulse width measurement mode timer z count stop bit count source selection bit (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) divider clock for timer z cntr 2 active edge switch bit d q t ?1? timer/event counter mode switch bit ?0? ?1? ?1? ?0? p4 2 /int 1 programmable one-shot generating circuit t q s q ?100? ?101? to cntr 2 interrupt request bit ?0? f(x cin ) edge detection circuit ?1? ?0? timer z low-order latch timer z low-order timer z high-order latch timer z high-order x cin
rev.1.00 oct 27, 2008 page 39 of 128 rej03b0266-0100 3804 group (spec.l) fig. 29 structure of timer z mode register b7 b0 timer z mode register (tzm : address 002a 16 ) timer z operating mode bits b2 b1 b0 0 0 0 : timer/event counter mode 0 0 1 : pulse output mode 0 1 0 : pulse period measurement mode 0 1 1 : pulse width measurement mode 1 0 0 : programmable waveform generating mode 1 0 1 : programmable one-shot generating mode 1 1 0 : not available 1 1 1 : not available timer z write control bit 0 : writing data to both latch and timer simultaneously 1 : writing data only to latch output level latch 0 : ?l? output 1 : ?h? output cntr 2 active edge switch bit 0 : ? event counter mode: count at rising edge ? pulse output mode: start outputting ?h? ? pulse period measurement mode: measurement between two falling edges ? pulse width measurement mode: measurement of ?h? term ? programmable one-shot generating mode: after start outputting ?l?, ?h? one-shot pulse generated ? interrupt at falling edge 1 : ? event counter mode: count at falling edge ? pulse output mode: start outputting ?l? ? pulse period measurement mode: measurement between two rising edges ? pulse width measurement mode: measurement of ?l? term ? programmable one-shot generating mode: after start outputting ?h?, ?l? one-shot pulse generated ? interrupt at rising edge timer z count stop bit 0 : count start 1 : count stop timer/event counter mode switch bit (1) 0 : timer mode 1 : event counter mode note 1 : when selecting the modes except the timer/ event counter mode, set ?0? to this bit.
rev.1.00 oct 27, 2008 page 40 of 128 rej03b0266-0100 3804 group (spec.l) fig. 30 timing chart of timer/event counter mode fig. 31 timing chart of pulse output mode ffff 16 0000 16 tl tr tr tr tl : value set to timer latch tr : timer interrupt request tr tr tr tr waveform output from cntr 2 pin cntr 2 cntr 2 ffff 16 0000 16 tl tl : value set to timer latch tr : timer interrupt request cntr 2 : cntr 2 interrupt request (cntr 2 active edge switch bit = ?0?; falling edge active)
rev.1.00 oct 27, 2008 page 41 of 128 rej03b0266-0100 3804 group (spec.l) fig. 32 timing chart of pulse period measurement mode (measuring term between two rising edges) fig. 33 timing chart of pulse width measurement mode (measuring ?l? term) t3 tr tr t2 t1 t2 t3 cntr 2 of rising edge active tr : timer interrupt request cntr 2 : cntr 2 interrupt request signal input from cntr 2 pin cntr 2 ffff 16 0000 16 cntr 2 cntr 2 cntr 2 ffff 16 ffff 16 + t1 t3 tr t2 t1 t1 t3 cntr 2 interrupt of rising edge active; measurement of ?l? width tr : timer interrupt request cntr 2 : cntr 2 interrupt request signal input from cntr 2 pin cntr 2 ffff 16 0000 16 cntr 2 cntr 2 ffff 16 + t2
rev.1.00 oct 27, 2008 page 42 of 128 rej03b0266-0100 3804 group (spec.l) fig. 34 timing chart of programmable waveform generating mode fig. 35 timing chart of programmable one-shot generating mode (?h? one-shot pulse generating) signal output from cntr 2 pin ffff 16 0000 16 t3 t2 t1 t2 t3 l l t1 tr tr tr tr cntr 2 cntr 2 l : timer initial value tr : timer interrupt request cntr 2 : cntr 2 interrupt request (cntr 2 active edge switch bit = ?0?; falling edge active) l tr tr tr l l signal input from int 1 pin ffff 16 l cntr 2 cntr 2 l : one-shot pulse width tr : timer interrupt request cntr 2 : cntr 2 interrupt request (cntr 2 active edge switch bit = ?0?; falling edge active) signal output from cntr 2 pin
rev.1.00 oct 27, 2008 page 43 of 128 rej03b0266-0100 3804 group (spec.l) serial interface ? serial i/o1 serial i/o1 can be used as either clock synchronous or asynchronous (uart) serial i/ o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6 of address 001a 16 ) to ?1?. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. fig. 36 block diagram of clock synchronous serial i/o1 fig. 37 operation of clock synchronous serial i/o1 serial i/o1 control register receive buffer register 1 receive shift register 1 clock control circuit 1/4 baud rate generator 1 f(x in ) 1/4 clock control circuit falling-edge detector transmit buffer register 1 transmit shift register 1 serial i/o1 status register f/f address 0018 16 receive buffer full flag (rbf) receive interrupt request (ri) shift clock serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) address 001c 16 brg count source selection bit address 0018 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0019 16 address 001a 16 data bus data bus p4 6 /s clk1 p4 4 /r x d 1 p4 5 /t x d 1 p4 7 /s rdy1 (f(x cin ) in low-speed mode) d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output t x d 1 serial input r x d 1 write pulse to receive/transmit buffer register 1 (address 0018 16 ) overrun error (oe) detection notes 1 : as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transm it shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control regi ster. 2 : if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the t x d pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ?1?. receive enable signal s rdy1
rev.1.00 oct 27, 2008 page 44 of 128 rej03b0266-0100 3804 group (spec.l) (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode sele ction bit (b6) of the serial i/o1 control register to ?0?. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift re gisters each have a buffer, but the two buffers have the same address in a memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next characte r is being received. fig. 38 block diagram of uart serial i/o1 fig. 39 operation of uart serial i/o1 f(x in ) 1/4 oe pe fe 1/16 1/16 data bus data bus receive buffer register 1 address 0018 16 receive shift register 1 receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator frequency division ratio 1/(n+1) address 001c 16 st/sp/pa generator transmit buffer register 1 transmit shift register 1 address 0018 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0019 16 st detector sp detector uart1 control register address 001b 16 character length selection bit address 001a 16 brg count source selection bit transmit interrupt source selection bit serial i/o1 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o1 status register serial i/o1 control register p4 6 /s clk1 p4 4 /r x d 1 p4 5 /t x d 1 (f(x cin ) in low-speed mode) tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 tbe=1 tsc=1* st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal serial output t x d 1 receive buffer read signal serial input r x d 1 generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) notes 1: error flag detection occurs at the same time that the rbf flag becomes ?1? (at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes ?1?, can be selected to occur depending on the settin g of the transmit interrupt source selection bit (tic) of the se rial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes ?1?. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changi ng to tsc=0. st d 0 d 1 sp d 0 d 1 st sp
rev.1.00 oct 27, 2008 page 45 of 128 rej03b0266-0100 3804 group (spec.l) [transmit buffer register 1/receive buffer register 1 (tb1/rb1)] 0018 16 the transmit buffer register 1 and the receive buffer register 1 are located at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is ?0?. [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to ?0? when the receive buffer register is read. if there is an error, it is detect ed at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. a write to the serial i/o1 status register clea rs all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing ?0? to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to ?0? at reset, but if the transmit enable bit (bit 4) of the serial i/o1 control register has been set to ?1?, the transmit shift completion flag (bit 2) and the transmit buffe r empty flag (bit 0) become ?1?. [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register c onsists of eight control bits for the serial i/ o1 function. [uart1 control register (uart1con)] 001b 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchro nous serial i/o is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the p4 5 /t x d 1 pin. [baud rate generator 1 (brg1)] 001c 16 the baud rate generator determin es the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
rev.1.00 oct 27, 2008 page 46 of 128 rej03b0266-0100 3804 group (spec.l) fig. 40 structure of serial i/o1 control registers b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns ?1? when read) uart1 control register (uart1con : address 001b 16 ) character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p4 5 /t x d 1 p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return ?1? when read) brg count source selection bit (css) 0: f(x in ) (f(x cin ) in low-speed mode) 1: f(x in )/4 (f(x cin )/4 in low-speed mode) serial i/o1 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o1 is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o1 is selected, external clock input divided by 16 when uart is selected. s rdy1 output enable bit (srdy) 0: p4 7 pin operates as normal i/o pin 1: p4 7 pin operates as s rdy1 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o1 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o1 enable bit (sioe) 0: serial i/o1 disabled (pins p4 4 to p4 7 operate as normal i/o pins) 1: serial i/o1 enabled (pins p4 4 to p4 7 operate as serial i/o1 pins) serial i/o1 control register (sio1con : address 001a 16 ) serial i/o1 status register (sio1sts : address 0019 16 ) b0 b7 b0 b7 b0
rev.1.00 oct 27, 2008 page 47 of 128 rej03b0266-0100 3804 group (spec.l) 1. notes when selecting cl ock synchronous serial i/o 1.1 stop of transmission operation ?note clear the serial i/o1 enable b it and the transmit enable bit to ?0? (serial i/o and transmit disabled). ?reason since transmission is not stoppe d and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to ?0? (serial i/o disabled), the internal transmission is running (in this case, since pins t x d 1 , r x d 1 , s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to ?1? at this time, the data during internally shifting is output to the t x d 1 pin and an operation failure occurs. 1.2 stop of receive operation ?note clear the receive enable bit to ?0? (receive disabled), or clear the serial i/o1 enable bit to ?0? (serial i/o disabled). 1.3 stop of transmit/receive operation ? note clear both the transmit enable bit and receive enable bit to ?0? (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial i/o mode, any one of data transmission and reception cannot be stopped.) ?reason in the clock synchronous serial i/o mode, the same clock is used for transmission and recept ion. if any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also operates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to ?0? (transmit disabled). also, th e transmission circuit is not initialized by clearing the serial i/o1 enable bit to ?0? (serial i/o disabled) (refer to 1.1). 2. notes when selecting cl ock asynchronous serial i/o 2.1 stop of transmission operation ?note clear the transmit enable bit to ?0? (transmit disabled). the transmission operation does not stop by clearing the serial i/o1 enable bit to ?0?. ?reason since transmission is not stoppe d and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to ?0? (serial i/o disabled), the internal transmission is running (in this case, since pins t x d 1 , r x d 1 , s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to ?1? at this time, the data during internally shifting is output to the t x d 1 pin and an operation failure occurs. 2.2 stop of receive operation ?note clear the receive enable bit to ?0? (receive disabled). 2.3 stop of transmit/receive operation ? note 1 (only transmission operation is stopped) clear the transmit enable bit to ?0? (transmit disabled). the transmission operation does not stop by clearing the serial i/o1 enable bit to ?0?. ?reason since transmission is not stoppe d and the transmission circuit is not initialized even if only the serial i/o1 enable bit is cleared to ?0? (serial i/o disabled), the internal transmission is running (in this case, since pins t x d 1 , r x d 1 , s clk1 , and s rdy1 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o1 enable bit is set to ?1? at this time, the data during internally shifting is output to the t x d 1 pin and an operation failure occurs. ? note 2 (only receive operation is stopped) clear the receive enable bit to ?0? (receive disabled).
rev.1.00 oct 27, 2008 page 48 of 128 rej03b0266-0100 3804 group (spec.l) 3. s rdy1 output of reception side ?note when signals are output from the s rdy1 pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy1 output enable bit, and the transmit enable bit to ?1? (transmit enabled). 4. setting serial i/o1 control register again ?note set the serial i/o1 control register again after the transmission and the reception circuits ar e reset by clearing both the transmit enable bit and the receive enable bit to ?0?. 5.data transmission control with referring to transmit shift register completion flag ? note after the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from ?1? to ?0? with a delay of 0.5 to 1.5 shift clocks. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. transmission control when external clock is selected ?note when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to ?1? at ?h? of the s clk1 input level. also, write data to the transmit buffer register at ?h? of the s clk1 input level. 7. transmit interrupt request when transmit enable bit is set ?note when using the transmit in terrupt, take the following sequence. 1. set the serial i/o1 transmit interrupt enable bit to ?0? (dis- abled). 2. set the transmit enable bit to ?1?. 3. set the serial i/o1 transmit interrupt request bit to ?0? after 1 or more instruction has executed. 4. set the serial i/o1 transmit interrupt enable bit to ?1? (enabled). ?reason when the transmit enable bit is set to ?1?, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to ?1?. therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. clear both the transmit enable bit (te) and the receive enable bit (re) to ?0? set the bits 0 to 3 and bit 6 of the serial i/o1 control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to ?1? can be set with the ldm instruction at the same time
rev.1.00 oct 27, 2008 page 49 of 128 rej03b0266-0100 3804 group (spec.l) ? serial i/o2 the serial i/o2 function can be used only for clock synchronous serial i/o. for clock synchronous serial i/ o2, the transmitter and the receiver must use the same clock. if the internal clock is used, transfer is started by a write signal to the serial i/o2 register (address 001f 16 ). [serial i/o2 control register (sio2con)] 001d 16 the serial i/o2 control register contains eight bits which control various serial i/o2 functions. fig. 41 structure of seri al i/o2 control register fig. 42 block diagram of serial i/o2 serial i/o2 control register (sio2con : address 001d 16 ) b7 internal synchronous clock selection bits b2 b1 b0 000:f(x in )/8 (f(x cin )/8 in low-speed mode) 001:f(x in )/16 (f(x cin )/16 in low-speed mode) 010:f(x in )/32 (f(x cin )/32 in low-speed mode) 011:f(x in )/64 (f(x cin )/64 in low-speed mode) 110:f(x in )/128 f(x cin )/128 in low-speed mode) 111:f(x in )/256 (f(x cin )/256 in low-speed mode) serial i/o2 port selection bit 0: i/o port 1: s out2 , s clk2 signal output s rdy2 output enable bit 0: i/o port 1: s rdy2 signal output transfer direction selection bit 0: lsb first 1: msb first serial i/o2 synchronous clock selection bit 0: external clock 1: internal clock p5 1 /s out2 p-channel output disable bit 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) b0 f(x in ) serial i/o counter 2 (3) serial i/o2 register (8) synchronization circuit ?1? ?0? ?0? ?1? ?0? ?1? s clk2 ?0? ?1? divider 1/8 1/16 1/32 1/64 1/128 1/256 data bus serial i/o2 interrupt request serial i/o2 port selection bit serial i/o2 port selection bit serial i/o2 synchronous clock selection bit s rdy2 output enable bit external clock internal synchronous clock selection bits p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p5 2 latch p5 1 latch p5 3 latch p5 3 /s rdy2 (f(x cin ) in low-speed mode) s rdy2 address 001f 16
rev.1.00 oct 27, 2008 page 50 of 128 rej03b0266-0100 3804 group (spec.l) fig. 43 timing of serial i/o2 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 transfer clock (1) serial i/o2 output s out2 serial i/o2 input s in2 receive enable signal s rdy2 serial i/o2 register write signal (2) serial i/o2 interrupt request bit set notes 1 : when the internal clock is selected as the transfer clock, the divide ratio of f(x in ), or (f(x cin ) in low-speed mode, can be selected by setting bits 0 to 2 of the serial i/o2 control register. 2 : when the internal clock is selected as the transfer clock, the s out2 pin goes to high impedance after transfer completion.
rev.1.00 oct 27, 2008 page 51 of 128 rej03b0266-0100 3804 group (spec.l) ? serial i/o3 serial i/o3 can be used as either clock synchronous or asynchronous (uart) serial i/o3. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o3 mode can be selected by setting the serial i/o3 mode selection bit of the serial i/o3 control register (bit 6 of address 0032 16 ) to ?1?. for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the transmit/receive buffer register. fig. 44 block diagram of clock synchronous serial i/o3 fig. 45 operation of clock synchronous serial i/o3 serial i/o3 control register receive buffer register 3 receive shift register 3 clock control circuit 1/4 baud rate generator 3 f(x in ) 1/4 clock control circuit falling-edge detector transmit buffer register 3 transmit shift register 3 serial i/o3 status register f/f address 0030 16 receive buffer full flag (rbf) receive interrupt request (ri) shift clock serial i/o3 synchronous clock selection bit frequency division ratio 1/(n+1) address 002f 16 brg count source selection bit address 0030 16 shift clock transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) transmit interrupt source selection bit address 0031 16 address 0032 16 data bus data bus p3 6 /s clk3 p3 4 /r x d 3 p3 5 /t x d 3 p3 7 /s rdy3 (f(x cin ) in low-speed mode) d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output t x d 3 serial input r x d 3 write pulse to receive/transmit buffer register (address 0030 16 ) overrun error (oe) detection notes 1 : as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transm it shift operation has ended (tsc=1), by setting the transmit interrupt source selection bi t (tic) of the serial i/o3 control regi ster. 2 : if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is outpu t continuously from the t x d pin. 3 : the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ?1?. receive enable signal s rdy3
rev.1.00 oct 27, 2008 page 52 of 128 rej03b0266-0100 3804 group (spec.l) (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o3 mode sele ction bit (b6) of the serial i/o3 control register to ?0?. eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift re gisters each have a buffer, but the two buffers have the same address in a memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next characte r is being received. fig. 46 block diagram of uart serial i/o3 fig. 47 operation of uart serial i/o3 f(x in ) 1/4 oe pe fe 1/16 1/16 data bus data bus receive buffer register 3 address 0030 16 receive shift register 3 receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator 3 frequency division ratio 1/(n+1) address 002f 16 st/sp/pa generator transmit buffer register 3 transmit shift register 3 address 0030 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 0031 16 st detector sp detector uart3 control register address 0033 16 character length selection bit address 0032 16 brg count source selection bit transmit interrupt source selection bit serial i/o3 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o3 status register serial i/o3 control register p3 6 /s clk3 p3 4 /r x d 3 p3 5 /t x d 3 (f(x cin ) in low-speed mode) tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 tbe=1 tsc=1* st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer write signal serial output t x d 3 receive buffer read signal serial input r x d 3 * generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) notes 1 : error flag detection occurs at the same time that the rbf flag becomes ?1? (at 1st stop bit, during reception). 2 : as the transmit interrupt (ti), when either the tbe or tsc flag becomes ?1?, can be selected to occur depending on the setting of the transmit interrupt source selection bit (tic) of the serial i/o3 control register. 3 : the receive interrupt (ri) is set when the rbf flag becomes ?1?. 4 : after data is written to the transmit buffer when tsc=1, 0. 5 to 1.5 cycles of the data shift cycle are necessary until changin g to tsc=0. st d 0 d 1 sp d 0 d 1 st sp
rev.1.00 oct 27, 2008 page 53 of 128 rej03b0266-0100 3804 group (spec.l) [transmit buffer register 3/receive buffer register 3 (tb3/rb3)] 0030 16 the transmit buffer register 3 and the receive buffer register 3 are located at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is ?0?. [serial i/o3 status register (sio3sts)] 0031 16 the read-only serial i/o3 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o3 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to ?0? when the receive buffer register is read. if there is an error, it is detect ed at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. a write to the serial i/o3 status register clea rs all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing ?0? to the serial i/o3 enable bit sioe (bit 7 of the serial i/o3 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o3 status register are initialized to ?0? at reset, but if the transmit enable bit (bit 4) of the serial i/o3 control register has been set to ?1?, the transmit shift completion flag (bit 2) and the transmit buffe r empty flag (bit 0) become ?1?. [serial i/o3 control register (sio3con)] 0032 16 the serial i/o3 control register c onsists of eight control bits for the serial i/ o3 function. [uart3 control register (uart3con)] 0033 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchro nous serial i/o is selected and set the data format of an data transfer, and one bit (bit 4) which is always valid and sets the output structure of the p3 5 /t x d 3 pin. [baud rate generator 3 (brg3)] 002f 16 the baud rate generator determin es the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
rev.1.00 oct 27, 2008 page 54 of 128 rej03b0266-0100 3804 group (spec.l) fig. 48 structure of serial i/o3 control registers b7 transmit buffer empty flag (tbe) 0: buffer full 1: buffer empty receive buffer full flag (rbf) 0: buffer empty 1: buffer full transmit shift completion flag (tsc) 0: transmit shift in progress 1: transmit shift completed overrun error flag (oe) 0: no error 1: overrun error parity error flag (pe) 0: no error 1: parity error framing error flag (fe) 0: no error 1: framing error summing error flag (se) 0: (oe) u (pe) u (fe)=0 1: (oe) u (pe) u (fe)=1 not used (returns ?1? when read) uart3 control register (uart3con : address 0033 16 ) character length selection bit (chas) 0: 8 bits 1: 7 bits parity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity stop bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p3 5 /t x d 3 p-channel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not used (return ?1? when read) brg count source selection bit (css) 0: f(x in ) (f(x cin ) in low-speed mode) 1: f(x in )/4 (f(x cin )/4 in low-speed mode) serial i/o3 synchronous clock selection bit (scs) 0: brg output divided by 4 when clock synchronous serial i/o3 is selected, brg output divided by 16 when uart is selected. 1: external clock input when clock synchronous serial i/o3 is selected, external clock input divided by 16 when uart is selected. s rdy3 output enable bit (srdy) 0: p3 7 pin operates as normal i/o pin 1: p3 7 pin operates as s rdy3 output pin transmit interrupt source selection bit (tic) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed transmit enable bit (te) 0: transmit disabled 1: transmit enabled receive enable bit (re) 0: receive disabled 1: receive enabled serial i/o3 mode selection bit (siom) 0: clock asynchronous (uart) serial i/o 1: clock synchronous serial i/o serial i/o3 enable bit (sioe) 0: serial i/o3 disabled (pins p3 4 to p3 7 operate as normal i/o pins) 1: serial i/o3 enabled (pins p3 4 to p3 7 operate as serial i/o3 pins) serial i/o3 control register (sio3con : address 0032 16 ) serial i/o3 status register (sio3sts : address 0031 16 ) b0 b7 b0 b7 b0
rev.1.00 oct 27, 2008 page 55 of 128 rej03b0266-0100 3804 group (spec.l) 1. notes when selecting cl ock synchronous serial i/o 1.1 stop of transmission operation ?note clear the serial i/o3 enable b it and the transmit enable bit to ?0? (serial i/o and transmit disabled). ?reason since transmission is not stoppe d and the transmission circuit is not initialized even if only the serial i/o3 enable bit is cleared to ?0? (serial i/o disabled), the internal transmission is running (in this case, since pins t x d 3 , r x d 3 , s clk3 , and s rdy3 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o3 enable bit is set to ?1? at this time, the data during internally shifting is output to the t x d 3 pin and an operation failure occurs. 1.2 stop of receive operation ?note clear the receive enable bit to ?0? (receive disabled), or clear the serial i/o3 enable bit to ?0? (serial i/o disabled). 1.3 stop of transmit/receive operation ? note clear both the transmit enable bit and receive enable bit to ?0? (transmit and receive disabled). (when data is transmitted and received in the clock synchronous serial i/o mode, any one of data transmission and reception cannot be stopped.) ?reason in the clock synchronous serial i/o mode, the same clock is used for transmission and recept ion. if any one of transmission and reception is disabled, a bit error occurs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also operates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to ?0? (transmit disabled). also, th e transmission circuit is not initialized by clearing the serial i/o3 enable bit to ?0? (serial i/o disabled) (refer to 1.1). 2. notes when selecting cl ock asynchronous serial i/o 2.1 stop of transmission operation ?note clear the transmit enable bit to ?0? (transmit disabled). the transmission operation does not stop by clearing the serial i/o3 enable bit to ?0?. ?reason since transmission is not stoppe d and the transmission circuit is not initialized even if only the serial i/o3 enable bit is cleared to ?0? (serial i/o disabled), the internal transmission is running (in this case, since pins t x d 3 , r x d 3 , s clk3 , and s rdy3 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o3 enable bit is set to ?1? at this time, the data during internally shifting is output to the t x d 3 pin and an operation failure occurs. 2.2 stop of receive operation ?note clear the receive enable bit to ?0? (receive disabled). 2.3 stop of transmit/receive operation ? note 1 (only transmission operation is stopped) clear the transmit enable bit to ?0? (transmit disabled). the transmission operation does not stop by clearing the serial i/o3 enable bit to ?0?. ?reason since transmission is not stoppe d and the transmission circuit is not initialized even if only the serial i/o3 enable bit is cleared to ?0? (serial i/o disabled), the internal transmission is running (in this case, since pins t x d 3 , r x d 3 , s clk3 , and s rdy3 function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/o3 enable bit is set to ?1? at this time, the data during internally shifting is output to the t x d 3 pin and an operation failure occurs. ? note 2 (only receive operation is stopped) clear the receive enable bit to ?0? (receive disabled).
rev.1.00 oct 27, 2008 page 56 of 128 rej03b0266-0100 3804 group (spec.l) 3. s rdy3 output of reception side ?note when signals are output from the s rdy3 pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy3 output enable bit, and the transmit enable bit to ?1? (transmit enabled). 4. setting serial i/o3 control register again ?note set the serial i/o3 control register again after the transmission and the reception circuits ar e reset by clearing both the transmit enable bit and the receive enable bit to ?0?. 5.data transmission control with referring to transmit shift register completion flag ?note after the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from ?1? to ?0? with a delay of 0.5 to 1.5 shift clocks. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. transmission control when external clock is selected ?note when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to ?1? at ?h? of the s clk3 input level. also, write data to the transmit buffer register at ?h? of the s clk input level. 7. transmit interrupt request when transmit enable bit is set ?note when using the transmit in terrupt, take the following sequence. 1. set the serial i/o3 transmit interrupt enable bit to ?0? (dis- abled). 2. set the transmit enable bit to ?1?. 3. set the serial i/o3 transmit interrupt request bit to ?0? after 1 or more instruction has executed. 4. set the serial i/o3 transmit interrupt enable bit to ?1? (enabled). ?reason when the transmit enable bit is set to ?1?, the transmit buffer empty flag and the transmit shift register shift completion flag are also set to ?1?. therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. clear both the transmit enable bit (te) and the receive enable bit (re) to ?0? set the bits 0 to 3 and bit 6 of the serial i/o3 control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to ?1? can be set with the ldm instruction at the same time
rev.1.00 oct 27, 2008 page 57 of 128 rej03b0266-0100 3804 group (spec.l) pwm (pwm: pulse width modulation) the 3804 group (spec.l) has pwm functions with an 8-bit resolution, based on a signal that is the clock input x in or that clock input divided by 2 or the clock input x cin or that clock input divided by 2 in low-speed mode. ? data setting the pwm output pin also functions as port p5 6 . set the pwm period by the pwm prescaler, an d set the ?h? term of output pulse by the pwm register. if the value in the pwm prescaler is n and the value in the pwm register is m (where n = 0 to 255 and m = 0 to 255): pwm period = 255 (n+1) / f(x in ) = 31.875 (n+1) s (when f(x in ) = 8 mhz, count source selection bit = ?0?) output pulse ?h? term = pwm period m / 255 = 0.125 (n+1) m s (when f(x in ) = 8 mhz, count source selection bit = ?0?) ? pwm operation when bit 0 (pwm enable bit) of the pwm control register is set to ?1?, operation starts by initializing the pwm output circuit, and pulses are output starting at an ?h?. if the pwm register or pwm pr escaler is updated during pwm output, the pulses will change in the cycle after the one in which the change was made. fig. 49 timing of pwm period fig. 50 block diagram of pwm function 31.875 m (n+1) 255 s t = [31.875 (n+1)] s pwm output m : contents of pwm register n : contents of pwm prescaler t : pwm period (when f(x in ) = 8 mhz, count source selection bit = ?0?) data bus count source selection bit ?0? ?1? pwm prescaler pre-latch pwm register pre-latch pwm prescaler latch pwm register latch transfer control circuit pwm register 1/2 x in (x cin at low- speed mode) port p5 6 latch pwm function enable bit port p5 6 pwm prescaler
rev.1.00 oct 27, 2008 page 58 of 128 rej03b0266-0100 3804 group (spec.l) fig. 51 structure of pwm control register fig. 52 pwm output timing when pwm register or pwm prescaler is changed the pwm starts after the pwm function enable bit is se t to enable and ?l? level is output from the pwm pin. the length of this ?l? leve l output is as follows: (count source selection bit = 0, where n is the value set in the prescaler) (count source selection bit = 1, where n is the value set in the prescaler) b7 b0 pwm control register (pwmcon: address 002b 16 ) pwm function enable bit 0 : pwm disabled 1 : pwm enabled count source selection bit 0: f(x in ) (f(x cin ) at low-speed mode) 1: f(x in )/2 (f(x cin )/2 at low-speed mode) not used (return ?0? when read) pwm output t t t2 b c pwm register write signal pwm prescaler write signal (changes ?h? term from ?a? to ? b?.) (changes pwm period from ?t? to ?t2?.) b t c t2 = when the contents of the pwm register or pwm prescaler have changed, the pwm output will chan ge from the next peri od after the change. a n1 + 2 fx in () ----------------------- sec n1 + fx in () --------------- - sec
rev.1.00 oct 27, 2008 page 59 of 128 rej03b0266-0100 3804 group (spec.l) a/d converter (successive approximation type) [ad conversion register 1, 2 (ad1, ad2)] 0035 16 , 0038 16 the ad conversion register is a read-only register that stores the result of an a/d conversion. when reading this register during an a/d conversion, the previous conversion result is read. bit 7 of the ad conversion regi ster 2 is the conversion mode selection bit. when this bit is set to ?0?, the a/d converter becomes the 10-bit a/d mode. when this bit is set to ?1?, that becomes the 8-bit a/d mode. the conversion result of the 8-bit a/d mode is stored in the ad c onversion register 1. as for 10-bit a/d mode, not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the ad conv ersion registers 1, 2 after a/d conversion is completed (in figure 54). as for 10-bit a/d mode, the 8-bit reading inclined to msb is performed when reading the ad co nverter register 1 after a/d conversion is started; and when the ad converter register 1 is read after reading the ad converter register 2, the 8-bit reading inclined to lsb is performed. [ad/da control regi ster (adcon)] 0034 16 the ad/da control register controls the a/d conversion process. bits 0 to 2 and bit 4 se lect a specific analog input pin. bit 3 signals the completion of an a/d conversion. the value of this bit remains at ?0? during an a/d conversion, and changes to ?1? when an a/d conversion ends. writing ?0? to this bit starts the a/d conversion. ? comparison voltage generator the comparison voltage generato r divides the voltage between av ss and v ref into 1024, and that outputs the comparison voltage in the 10-bit a/d mode (256 division in 8-bit a/d mode). the a/d converter successive ly compares the comparison voltage vref in each mode, dividing the v ref voltage (see below), with the input voltage. ? 10-bit a/d mode (10-bit reading) vref = n (n = 0 ? 1023) ? 10-bit a/d mode (8-bit reading) vref = n (n = 0 ? 255) ? 8-bit a/d mode vref = (n ? 0.5) (n = 1 ? 255) =0 (n = 0) ? channel selector the channel selector se lects one of ports p6 7 /an 7 to p6 0 /an 0 or p0 7 /an 15 to p0 0 /an 8 , and inputs the voltage to the comparator. ? comparator and control circuit the comparator and control circ uit compares an analog input voltage with the comparison voltage , and then stores the result in the ad conversion registers 1, 2. when an a/d conversion is completed, the control circuit sets the ad conve rsion completion bit and the ad interrupt request bit to ?1?. note that because the comparator consists of a capacitor coupling, set f(x in) to 500 khz or more during an a/d conversion. fig. 53 structure of ad/da control register fig. 54 structure of 10-bit a/d mode reading v ref 1024 ------------- v ref 256 ------------- v ref 256 ------------- ad/da control register (adcon : address 0034 16 ) analog input pin selection bits 1 0 0 0: p6 0 /an 0or p0 0 /an 8 0 0 1: p6 1 /an 1or p0 1 /an 9 0 1 0: p6 2 /an 2or p0 2 /an 10 0 1 1: p6 3 /an 3or p0 3 /an 11 1 0 0: p6 4 /an 4or p0 4 /an 12 1 0 1: p6 5 /an 5or p0 5 /an 13 1 1 0: p6 6 /an 6or p0 6 /an 14 1 1 1: p6 7 /an 7or p0 7 /an 15 ad conversion completion bit 0: conversion in progress 1: conversion completed analog input pin selection bit 2 0: an 0 to an 7 side 1: an 8 to an 15 side not used (returns ?0? when read) da 1 output enable bit 0: da 1 output disabled 1: da 1 output enabled da 2 output enable bit 0: da 2 output disabled 1: da 2 output enabled b7 b0 b2 b1 b0 10-bit reading (read address 0038 16 before 0035 16 ) ad conversion register 2 (ad2: address 0038 16 ) ad conversion register 1 (ad1: address 0035 16 ) note : bits 2 to 6 of address 0038 16 become ?0? at reading. 8-bit reading (read only address 0035 16 ) ad conversion register 1 (ad1: address 0035 16 ) b9 b7 b0 b8 b7 b6 b5 b4 b3 b2 b7 b0 b9 b8 b7 b7 b0 b6 b5 b4 b3 b2 b1 b0 0
rev.1.00 oct 27, 2008 page 60 of 128 rej03b0266-0100 3804 group (spec.l) fig. 55 block diagram of a/d converter c h a n n e l s e l e c t o r a/d control circuit ad conversion register 1 resistor ladder v ref av ss comparator a/d converter interrupt request 10 p6 0 /an 0 p6 1 /an 1 p6 2 /an 2 p6 3 /an 3 p6 4 /an 4 p6 5 /an 5 p6 6 /an 6 p6 7 /an 7 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 b7 b0 4 data bus ad/da control register (address 0034 16 ) ad conversion register 2 (address 0038 16 ) (address 0035 16 )
rev.1.00 oct 27, 2008 page 61 of 128 rej03b0266-0100 3804 group (spec.l) d/a converter the 3804 group (spec.l) has two internal d/a converters (da 1 and da 2 ) with 8-bit resolution. the d/a conversion is performed by setting the value in each da conversion register. the resu lt of d/a conversion is output from the da 1 or da 2 pin by setting the da output enable bit to ?1?. when using the d/a converter, th e corresponding port direction register bit (p3 0 /da 1 or p3 1 /da 2 ) must be set to ?0? (input status). the output analog voltage v is determined by the value n (decimal notation) in the da c onversion register as follows: v = v ref n/256 (n = 0 to 255) where v ref is the reference voltage. at reset, the da conversion re gisters are cleared to ?00 16 ?, and the da output enable bits ar e cleared to ?0?, and the p3 0 /da 1 and p3 1 /da 2 pins become high impedance. the da output does not have buffers. accordingly, connect an external buffer when driving a low-impedance load. fig. 56 block diagram of d/a converter fig. 57 equivalent connection circuit of d/a converter (da1) da 1 conversion register (8) da 1 output enable bit p3 0 /da 1 data bus r-2r resistor ladder da 2 conversion register (8) da 2 output enable bit p3 1 /da 2 r-2r resistor ladder da 1 output enable bit av ss v ref r 2r r r r r r r 2r 2r 2r 2r 2r 2r 2r 2r lsb ?1? ?0? msb da 1 conversion register p3 0 /da 1 ?0? ?1?
rev.1.00 oct 27, 2008 page 62 of 128 rej03b0266-0100 3804 group (spec.l) watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away ). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. ? watchdog timer initial value watchdog timer l is set to ?ff 16 ? and watchdog timer h is set to ?ff 16 ? by writing to the watchdog time r control regi ster (address 001e 16 ) or at a reset. any write instruction that causes a write signal can be used, such as the sta, ldm, clb, etc. data can only be written to bits 6 and 7 of the watchdog timer control register. regardless of the value wr itten to bits 0 to 5, the above- mentioned value will be set to each timer. bit 6 can be written only once after releasing reset. after rewriting it is disable to write any data to this bit. ? watchdog timer operations the watchdog timer stops at rese t and starts to count down by writing to the watchdog timer control register (address 001e 16 ). an internal reset occurs at an underflow of the watchdog timer h. the reset is released after waiting for a reset release time and the program is processed from the reset vector address. accordingly, programming is usually performed so that writing to the watchdog timer control register may be started before an underflow. if writing to the watchdog timer control register is not performed once, the watchdog timer does not function. ? bit 6 of watchdog timer control register ? when bit 6 of the watchdog timer control register is ?0?, the mcu enters the stop mode by ex ecution of stp instruction. just after releasing the stop mode, the watchdog timer restarts counting (note.) . when executing the wit instruction, the watchdog timer does not stop. ? when bit 6 is ?1?, execution of stp instruction causes an internal reset. when this bit is set to ?1? once, it cannot be rewritten to ?0? by program. bit 6 is ?0? at reset. the following shows the period between the write execution to the watchdog timer control register and the underflow of watchdog timer h. bit 7 of the watchdog timer control register is ?0?: when x cin = 32.768 khz; 32 s when x in = 16 mhz; 65.536 ms bit 7 of the watchdog timer control register is ?1?: when x cin = 32.768 khz; 125 ms when x in = 16 mhz; 256 s note. the watchdog timer continues to count even during the wait time set by timer 1 and timer 2 to rele ase the stop state and in the wait mode. accordingly, write to the wa tchdog timer control register to not underflow the watch dog timer in this time. fig. 58 block diagram of watchdog timer fig. 59 structure of watchdog timer control register x in data bus x cin ?10? ?00? ?01? main clock division ratio selection bits (1) ?0? ?1? 1/16 watchdog timer h count source selection bit reset circuit stp instruction function selection bit watchdog timer h (8) ?ff 16 ? is set when watchdog timer control register is written to. internal reset watchdog timer l (8) ?ff 16 ? is set when watchdog timer control register is written to. note 1 : any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. stp instruction reset b7 watchdog timer h (for read-out of high-order 6 bit) stp instruction function selection bit 0: entering stop mode by execution of stp instruction 1: internal reset by execution of stp instruction watchdog timer h count source selection bit 0: watchdog timer l underflow 1: f(x in )/16 or f(x cin )/16 watchdog timer control register (wdtcon : address 001e 16 ) b0
rev.1.00 oct 27, 2008 page 63 of 128 rej03b0266-0100 3804 group (spec.l) multi-master i 2 c-bus interface the 3804 group (spec. l) has the multi-master i 2 c-bus interface. the multi-master i 2 c-bus interface is a serial communications circuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchronous func tions, is useful for the multi- master serial communications. figure 60 shows a block diagram of the multi-master i 2 c-bus interface and table 9 lists the multi-master i 2 c-bus interface functions. this multi-master i 2 c-bus interface consists of the i 2 c slave address registers 0 to 2, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register, the i 2 c start/stop condition control register, the i 2 c special mode control register, the i 2 c special mode status register, and other control circuits. when using the multi-master i 2 c-bus interface, set 1 mhz or more to the internal clock . system clock = f(x in )/2 (high-speed mode) = f(x in )/8 (middle-speed mode) note: 1. we are not responsible for any third party?s infringement of patent rights or other rights attributable to the use of the control function (bit 6 of the i 2 c control register at address 002e 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, and sda2). fig. 60 block diagram of multi-master i 2 c-bus interface *: purchase of renesas technology corporation?s i 2 c components conveys a license under the philips i 2 c patent rights to use these components an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. table 9 multi-master i 2 c-bus interface functions item function format in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode communication mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception scl clock frequency 16.1 khz to 400 khz (at = 4 mhz) i 2 c slave address registers 0 to 2 b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw serial data (sda) address comparator b7 i 2 c data shift register b0 interrupt generating circuit system clock ( ) b7 mst trx bb pin al aas ad0 lrb b0 s1 noise elimination circuit data control circuit al circuit bb circuit clock control circuit noise elimination circuit b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 clock division s 0 s2 s0d0-2 sis sip ssc4 ssc3 ssc2 ssc1 ssc0 b7 b0 tiss tsel 10bit sad als bc2 bc1 bc0 s1d bit counter es0 i 2 c clock control register i 2 c status register internal data bus interrupt generating circuit interrupt request signal (scl, sda, irq) interrupt request signal (i 2 cirq) b7 b0 spcf s3 pin2 aas2 aas1 aas0 b7 b0 spcfl s3d pin2 hd pin2 in hslad acki con i 2 c special mode control register i 2 c special mode status register serial clock (scl) s2d i 2 c start/stop condition control register i 2 c control register
rev.1.00 oct 27, 2008 page 64 of 128 rej03b0266-0100 3804 group (spec.l) [i 2 c data shift register (s0)] 0011 16 the i 2 c data shift register (s0: address 0011 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchr onization with the scl, and each time one-bit data is output, the data of this register are shifted by one bit to the left. when data is received, it is input to this register from bit 0 in synchroni zation with the scl, and each time one-bit data is input, the data of this register are shifted by one bit to the left. the minimum 2 cycles of the internal clock are required from the rising of the scl until input to this register. the i 2 c data shift register is in a write enable status only when the i 2 c-bus interface enable bit (es0 bit) of the i 2 c control register (s1d: address 0014 16 ) is ?1?. the bit counter is reset by a write instruction to the i 2 c data shift register. when both the es0 bit and the mst bit of the i 2 c status register (s1: address 0013 16 ) are ?1?, the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift register is always enabled re gardless of the es0 bit value. [i 2 c slave address registers 0 to 2 (s0d0 to s0d2)] 0ff7 16 to 0ff9 16 the i 2 c slave address registers 0 to 2 (s0d0 to s0d2: addresses 0ff7 16 to 0ff9 16 ) consists of a 7-bit slave address and a read/ write bit. in the addressing mode, th e slave address written in this register is compared with th e address data to be received immediately after the start condition is detected. ? bit 0: read/w rite bit (rwb) this is not used in the 7-bit addressing mode. in the 10-bit addressing mode, set rwb to ?0? because the first address data to be received is compared with the contents (sad6 to sad0 + rwb) of the i 2 c slave address registers 0 to 2. when 2-byte address data matc h slave address, a 7-bit slave address which is received after restart condition has detected and r/w data can be matched by setting ?1? to rwb with software. the rwb is cleared to ?0? automatically when the stop condition is detected. ? bits 1 to 7: slave address (sad0-sad6) these bits store slave addresses. regardless of the 7-bit addressing mode or the 10-bit a ddressing mode, the address data transmitted from the master is compared with these bits? contents. fig. 61 structure of i 2 c slave address registers 0 to 2 i 2 c slave address register 0 (s0d0: address 0ff7 16 ) i 2 c slave address register 1 (s0d1: address 0ff8 16 ) i 2 c slave address register 2 (s0d2: address 0ff9 16 ) read/write bit slave address sad6 sad5 sad4 sad3 sad2 sad1 sad0 rwb b0 b7
rev.1.00 oct 27, 2008 page 65 of 128 rej03b0266-0100 3804 group (spec.l) [i 2 c clock control register (s2)] 0015 16 the i 2 c clock control register (s2: address 0015 16 ) is used to set ack control, scl mode and scl frequency. ? bits 0 to 4: scl frequency control bits (ccr0-ccr4) these bits control the scl frequency. refer to table 10. ? bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. wh en this bit is set to ?0?, the standard clock mode is selected. when the bit is set to ?1?, the high-speed clock mode is selected. when connecting the bus of the high-speed mode i 2 c bus standard (maximum 400 kbits/s), use 8 mhz or more oscillation frequency f(x in ) in the high-speed mode (2 division clock). ? bit 6: ack bit (ack bit) this bit sets the sda status wh en an ack clock* is generated. when this bit is set to ?0?, the ack return mode is selected and sda goes to ?l? at the occurrence of an ack clock. when the bit is set to ?1?, the ack non-return mode is selected. the sda is held in the ?h? status at the occurrence of an ack clock. however, when the slave address agree with the address data in the reception of address data at ack bit = ?0?, the sda is automatically made ?l? (ack is returned). if there is a disagreement between the slave a ddress and the address data, the sda is automatically made ?h? (ack is not returned). * ack clock: clock for acknowledgment ? bit 7: ack clock bit (ack) this bit specifies the mode of acknowledgment which is an acknowledgment response of data tran sfer. when this bit is set to ?0?, the no ack clock mode is selected. in this case, no ack clock occurs after data transmissi on. when the bit is set to ?1?, the ack clock mode is selected and the master generates an ack clock each completion of each 1-byte data transfer. the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (makes sda ?h?) and receives the ack bit generated by the data receiving device. note. do not write data into the i 2 c clock control register during trans- fer. if data is written during transfer, the i 2 c clock generator is reset, so that data canno t be transferred normally. fig. 62 structure of i 2 c clock control register notes: 1. duty of scl output is 50 %. the duty becomes 35 to 45 % only when the high-speed clock mode is selected and ccr value = 5 (400 khz, at = 4 mhz). ?h? duration of the clock fluctuates from -4 to +2 mach ine cycles in t he standard clock mode, and fluctuates from -2 to +2 machine cycles in the high-speed clock mode. in the case of negative fluctuation, the frequency does not increase because ?l? duration is extended instead of ?h? duration reduction. these are values when scl synchronization by the synchronous function is not performed. ccr value is the decimal notation value of the scl frequency control bits ccr4 to ccr0. 2. each value of scl frequen cy exceeds the limit at = 4 mhz or more. when using these setting value, use of 4 mhz or less. 3. the data formula of scl frequency is described below: /(8 ccr value) standard clock mode /(4 ccr value) high-speed clock mode (ccr value 5) /(2 ccr value) high-speed clock mode (ccr value = 5) do not set 0 to 2 as ccr value regardless of frequency. set 100 khz (max.) in the standard clock mode and 400 khz (max.) in the high-speed clock mode to the scl frequency by setting the scl frequency control bits ccr4 to ccr0. table 10 set values of i 2 c clock control register and scl frequency setting value of ccr4-ccr0 scl frequency (at = 4 mkz, unit: khz) (note 1) ccr4 ccr3 ccr2 ccr1 ccr0 standard clock mode high-speed clock mode 00000setting disabledsetting disabled 00001setting disabledsetting disabled 00010setting disabledsetting disabled 00011 ? (note 2) 333 00100 ? (note 2) 250 00101 100 400 (note 3) 00110 83.3 166 : : : : : : : : : : 500/ccr value (note 3) 1000/ccr value (note 3) 11101 17.2 34.5 11110 16.6 33.3 11111 16.1 32.3 b7 b0 ack ack bit fast mode ccr4 ccr3 ccr2 ccr1 ccr0 (s2: address 0015 16 ) i 2 c clock control register scl frequency control bits refer to table 10. scl mode specification bit 0: standard clock mode 1: high-speed clock mode ack bit 0: ack is returned 1: ack is not returned ack clock bit 0: no ack clock 1: ack clock
rev.1.00 oct 27, 2008 page 66 of 128 rej03b0266-0100 3804 group (spec.l) [i 2 c control register (s1d)] 0014 16 the i 2 c control register (s1d: address 0014 16 ) controls data communication format. ? bits 0 to 2: bit counter (bc0-bc2) these bits decide the number of bits for the next 1-byte data to be transmitted. the i 2 c interrupt request signa l occurs immediately after the number of count specifie d with these bits (ack clock is added to the number of count wh en ack clock is selected by ack clock bit (bit 7 of s2, address 0015 16 ) have been transferred, and bc0 to bc2 are returned to ?000 2 ?. also when a start condition is received, these bits become ?000 2 ? and the address data is alwa ys transmitted and received in 8 bits. ? bit 3: i 2 c interface enable bit (es0) this bit enables to use the multi-master i 2 c-bus interface. when this bit is set to ?0?, the use disable status is provided, so that the sda and the scl become high-impedance. when the bit is set to ?1?, use of the interface is enabled. when es0 = ?0?, the following is performed. ? pin = ?1?, bb = ?0? and al = ?0? are set (which are bits of the i 2 c status register, s1, at address 0013 16 ). ? writing data to the i 2 c data shift register (s0: address 0011 16 ) is disabled. ? bit 4: data format selection bit (als) this bit decides whether or no t to recognize slave addresses. when this bit is set to ?0?, the addressing format is selected, so that address data is recognized. when a match is found between a slave address and address data as a result of comparison or when a general call (refer to ?i 2 c status register?, bit 1) is received, transfer processing can be performed . when this bit is set to ?1?, the free data format is selected, so that slave addresses are not recognized. ? bit 5: addressing format selection bit (10bit sad) this bit selects a slave addre ss specification format. when this bit is set to ?0?, the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c slave address registers 0 to 2 are compared with address data. when this bit is set to ?1?, the 10-bit addressing format is selected, and all the bits of the i 2 c slave address registers 0 to 2 are compared with address data. ? bit 7: i 2 c-bus interface pin input level selection bit (tiss) this bit selects the input level of the scl and sda pins of the multi-master i 2 c-bus interface. fig. 63 structure of i 2 c clock control register tiss als es0 bc2 bc1 bc0 10bit sad i 2 c control register (s1d: address 0014 16 ) bit counter (number of transmit/receive bits) b2 b1 b0 000:8 001:7 010:6 011:5 100:4 101:3 110:2 111:1 i 2 c-bus interface enable bit 0: disabled 1: enabled data format selection bit 0: addressing format 1: free data format addressing format selection bit 0: 7-bit addressing format 1: 10-bit addressing format not used (return ?0? when read) i 2 c-bus interface pin input level selection bit 0: smbus input 1: cmos input b7 b0
rev.1.00 oct 27, 2008 page 67 of 128 rej03b0266-0100 3804 group (spec.l) [i 2 c status register (s1)] 0013 16 the i 2 c status register (s1: address 0013 16 ) controls the i 2 c- bus interface status. the low-order 4 bits are read-only bits and the high-order 4 bits can be read out and written to. set ?0000 2 ? to the low-order 4 bits, because these bits become the reserved bits at writing. ? bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmati on. if ack is returned when an ack clock occurs, the lrb bit is set to ?0?. if ack is not returned, this bit is set to ?1?. except in the ack mode, the last bit value of received data is input. the state of this bit is changed from ?1? to ?0? by executing a write instruction to the i 2 c data shift register (s0: address 0011 16 ). ? bit 1: general call detecting flag (ad0) when the als bit is ?0?, this bit is set to ?1? when a general call* whose address data is all ?0? is received in the slave mode. by a general call of the master device, every slave device receives control data after the general call. the ad0 bit is set to ?0? by detecting the stop co ndition or start condition, or reset. * general call: the master transmits the general call address ?00 16 ? to all slaves. ? bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data when the als bit is ?0?. (1) in the slave receive mode, wh en the 7-bit addressing format is selected, this bit is set to ?1? in one of the following conditions: ? the address data immediat ely after occurrence of a start condition agrees with the slave address stored in the high-order 7 bits of the i 2 c slave address register. ? a general call is received. (2) in the slave receive mode, when the 10-bit addressing format is selected, this bit is set to ?1? with the following condition: ? when the address data is compared with the i 2 c slave address register (8 bits c onsisting of slave address and rwb bit), the first bytes agree. (3) this bit is set to?0? by executing a write instruction to the i 2 c data shift register (s0: address 0011 16 ) when es0 is set to ?1? or reset. ? bit 3: arbitration lost* detecting flag (al) in the master transmission mode, when the sda is made ?l? by any other device, arbitration is j udged to have been lost, so that this bit is set to ?1?. at the sa me time, the trx bit is set to ?0?, so that immediately after tran smission of the byte whose arbitration was lost is completed, the mst bit is set to ?0?. the arbitration lost can be detected only in the master transmission mode. when arbitration is lost during slave address transmission, the trx bit is set to ?0? and the reception mode is set. consequently, it becomes possible to detect the agreement of its own slave address and address data transmitted by another master device. the al bit is set to ?0? in one of the following conditions: ? executing a write instruction to the i 2 c data shift register (s0: address 0011 16 ) ? when the es0 bit is ?0? ?at reset * arbitration lost: the status in which communication as a master is disabled. ? bit 4: scl pin low hold bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the pin bit ch anges from ?1? to ?0?. at the same time, an interrupt request signal occurs to the cpu. the pin bit is set to ?0? in synchronization with a falling of the last clock (including the ack clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling of the pin bit. when the pin bit is ?0?, the scl is kept in the ?0? state and clock generation is disabled. figure 65 shows an interrupt request signal generating timing chart. the pin bit is set to ?1? in one of the foll owing conditions: ? executing a write instruction to the i 2 c data shift register (s0: address 0011 16 ). (this is the only condition which the prohibition of the internal cloc k is released and data can be communicated except for the start condition detection.) ? when the es0 bit is ?0? ?at reset ? when writing ?1? to the pin bit by software the pin bit is set to ?0? in one of the foll owing conditions: ? immediately after completion of 1-byte data transmission (including when arbitration lost is detected) ? immediately after completi on of 1-byte data reception ? in the slave reception mode, wi th als = ?0? and immediately after completion of slave address agreement or general call address reception ? in the slave reception mode, wi th als = ?1? and immediately after completion of a ddress data reception ? bit 5: bus busy flag (bb) this bit indicates the status of use of the bus system. when this bit is set to ?0?, this bus system is not busy and a start condition can be generated. the bb flag is set/reset by the scl, sda pins input signal re gardless of master/slave . this flag is set to ?1? by detecting the start c ondition, and is set to ?0? by detecting the stop condition. th e condition of these detecting is set by the start/stop condition setting bits (ssc4-ssc0) of the i 2 c start/stop condition contro l register (s2d: address 0016 16 ). when the es0 bit of the i 2 c control register (bit 3 of s1d, address 0014 16 ) is ?0? or reset, the bb flag is set to ?0?. for the writing function to the bb flag, refer to the sections ?start condition generating method? and ?stop condition generating method? described later.
rev.1.00 oct 27, 2008 page 68 of 128 rej03b0266-0100 3804 group (spec.l) ? bit 6: communication mode specification bit (transfer direction specifi cation bit: trx) this bit decides a direction of transfer for data communication. when this bit is ?0?, the recepti on mode is selected and the data of a transmitting device is received. when the bit is ?1?, the transmission mode is selected and address data and control data are output onto the sda in synchronization with the clock generated on the scl. this bit is set/reset by software and hardware. about set/reset by hardware is described below. this bit is set to ?1? by hardware when all the following conditions are satisfied: ? when als is ?0? ? in the slave reception mode or the slave transmission mode ? when the r/w bit reception is ?1? ? this bit is set to ?0? in one of the following conditions: ? when arbitration lost is detected. ? when a stop condition is detected. ? when writing ?1? to this bit by software is invalid by the start condition duplication pr eventing function (note). ? with mst = ?0? and when a start condition is detected. ? with mst = ?0? and when ac k non-return is detected. ?at reset ? bit 7: communication mode specification bit (master/ slave specification bit: mst) this bit is used for master/slave specification for data communication. when this bit is ?0?, the slave is specified, so that a start condition and a stop condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. when this bit is ?1?, the master is specified and a start condition and a stop condition are generated. additionally, the clocks required for data communicati on are generated on the scl. this bit is set to ?0? in one of the following conditions. ? immediately after completion of the byte which has lost arbitration when arbitration lost is detected ? when a stop condition is detected. ? writing ?1? to this bit by software is invalid by the start condition duplicati on preventing function (note). ?at reset note. start condition duplication preventing function the mst, trx, and bb bits is set to ?1? at the same time after confirming that the bb flag is ?0? in the procedure of a start condition occurrence. however, when a start condition by another master device occurs and the bb flag is set to ?1? imme- diately after the contents of the bb flag is confirmed, the start condition duplication preventing fu nction makes the writing to the mst and trx bits invalid. the duplication preventing function becomes valid from the rising of the bb flag to reception comple- tion of slave address. fig. 64 structure of i 2 c status register fig. 65 interrupt request signal generating timing mst b7 b0 trx bb pin al aas ad 0 lrb i 2 c status register (s1: address 0013 16 ) last receive bit (note) 0: last bit = ?0? 1: last bit = ?1? general call detecting flag (note) 0: no general call detected 1: general call detected slave address comparison flag (note) 0: address disagreement 1: address agreement arbitration lost detecting flag (note) 0: not detected 1: detected scl pin low hold bit 0: scl pin low hold 1: scl pin low release bus busy flag 0: bus free 1: bus busy communication mode specification bits 0 0 : slave receive mode 0 1 : slave transmit mode 1 0 : master receive mode 1 1 : master transmit mode note: these bits and flags can be read out, but cannot be written. write ?0? to these bits at writing. scl pin i 2 cirq
rev.1.00 oct 27, 2008 page 69 of 128 rej03b0266-0100 3804 group (spec.l) start condition generating method when writing ?1? to the mst, trx, and bb bits of the i 2 c status register (s1: address 0013 16 ) at the same time after writing the slave address to the i 2 c data shift register (s0: address 0011 16 ) with the condition in which the es0 bit of the i 2 c control register (s1d: address 0014 16 ) is ?1? and the bb flag is ?0?, a start condition occurs. after that, the bit counter becomes ?000 2 ? and an scl for 1 byte is output. the start condition generating timing is di fferent in the standard clock mode and the high-speed clock mode. refer to figure 66, the start condition generating timing diagram, and table 11, the start condition gene rating timing table. fig. 66 start condition generating timing diagram note: 1. absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. stop condition generating method when the es0 bit of the i 2 c control register (s1d: address 0014 16 ) is ?1?, write ?1? to the mst and trx bits, and write ?0? to the bb bit of the i 2 c status register (s1: address 0013 16 ) simultaneously. then a stop condition occurs. the stop condition generating timing is di fferent in the standard clock mode and the high-speed clock mode. refer to figure 67, the stop condition genera ting timing diagram, and table 12, the stop condition gene rating timing table. fig. 67 stop condition generating timing diagram note: 1. absolute time at = 4 mhz. the value in parentheses denotes the number of cycles. table 11 start condition generating timing table item standard clock mode high-speed clock mode setup time 5.0 s (20 cycles) 2.5 s (10 cycles) hold time 5.0 s (20 cycles) 2.5 s (10 cycles) i 2 c status register write signal scl sda hold time setup time table 12 stop condition generating timing table item standard clock mode high-speed clock mode setup time 5.0 s (20 cycles) 3.0 s (12 cycles) hold time 4.5 s (18 cycles) 2.5 s (10 cycles) scl sda i 2 c status register write signal hold time setup time
rev.1.00 oct 27, 2008 page 70 of 128 rej03b0266-0100 3804 group (spec.l) start/stop condition detecting operation the start/stop condition detec tion operations are shown in figures 68, 69, and table 13. th e start/stop condition is set by the start/stop condition set bit. the start/stop condition can be detected only when the input signal of the scl and sda pins satisfy three conditions: scl release time, setup time, and hold time (see table 13). the bb flag is set to ?1? by detecting the start condition and is reset to ?0? by dete cting the stop condition. the bb flag set/reset timing is different in the standard clock mode and the high-speed clock m ode. refer to table 13, the bb flag set/reset time. note. when a stop condition is detect ed in the slave mode (mst = 0), an interrupt request signal ?i 2 cirq? occurs to the cpu. note: 1. unit : cycle number of system clock ssc value is the decimal notation value of the start/stop condition set bits ssc4 to ssc0. do not set ?0? or an odd number to ssc value. the value in parentheses is an example when the i 2 c start/stop condition control register is set to ?18 16 ? at = 4 mhz. fig. 68 start/stop condition detecting timing diagram fig. 69 stop condition detecting timing diagram table 13 start condition/stop condition detecting conditions standard clock mode high-speed clock mode scl release time ssc value + 1 cycle (6.25 s) 4 cycle (1.0 s) setup time ssc value + 1 cycle < 4 s (3.125 s) 2 2 cycle (0.5 s) hold time ssc value + 1 cycle < 4 s (3.125 s) 2 2 cycle (0.5 s) bb flag set/ reset time ssc value ? 1 + 2 cycles (3.375 s) 2 3.5 cycle (0.875 s) bb flag scl sda scl release time bb flag reset time hold time setup time scl sda bb flag scl release time bb flag reset time hold time setup time
rev.1.00 oct 27, 2008 page 71 of 128 rej03b0266-0100 3804 group (spec.l) [i 2 c start/stop condition control register (s2d)] 0016 16 the i 2 c start/stop condition contro l register (s2d: address 0016 16 ) controls start/stop condition detection. ? bits 0 to 4: start/stop condition set bits (ssc4-ssc0) scl release time, setup time, and hold time change the detection condition by value of the main cl ock divide ratio selection bit and the oscillation frequency f(x in ) because these time are measured by the internal system clock. accordingly, set the proper value to the start/st op condition set bits (ssc4 to ssc0) in considered of the system clock frequency. refer to table 13. do not set ?00000 2 ? or an odd number to the start/stop condition set bits (ssc4 to ssc0). refer to table 14, the recommended set value to start/stop condition set bits (ssc4-ssc0) for each oscillation frequency. ? bit 5: scl/sda interrupt pin polarity selection bit (sip) an interrupt can occur when dete cting the falling or rising edge of the scl or sda pin. this bit selects the polarity of the scl or sda pin interrupt pin. fig. 70 structure of i 2 c start/stop condition control register ? bit 6: scl/sda interrupt pin selection bit (sis) this bit selects the pin of whic h interrupt becomes valid between the scl pin and the sda pin. note. when changing the setting of th e scl/sda interrupt pin polarity selection bit, the scl/sda interrupt pin selection bit, or the i 2 c- bus interface enable bit es0, th e scl/sda interrupt request bit may be set. when selecting the scl/sda interrupt source, dis- able the interrupt before the scl/ sda interrupt pin polarity selec- tion bit, the scl/sda interrupt pin selection bit, or the i 2 c-bus interface enable bit es0 is set. reset the request bit to ?0? after setting these bits, and enable the interrupt. note: 1. do not set an odd number to the start/stop condition set bits (ssc4 to ssc0) and ?00000 2 ?. sis sip ssc4 ssc3 ssc2 ssc1 ssc0 i 2 c start/stop condition control register (s2d: address 0016 16 ) start/stop condition set bits scl/sda interrupt pin polarity selection bit 0: falling edge active 1: rising edge active scl/sda interrupt pin selection bit 0: sda valid 1: scl valid b7 b0 not used (fix this bit to ?0?.) table 14 recommended set value to start/stop condition set bits (ssc4-ssc0) for e ach oscillation frequency oscillation frequency f(x in )(mhz) main clock divide ratio internal clock (mhz) start/stop condition control register scl release time ( s) setup time ( s) hold time ( s) 824 xxx11010 6.75 s (27 cycles) 3.5 s (14 cycles) 3.25 s (13 cycles) xxx11000 6.25 s (25 cycles) 3.25 s (13 cycles) 3.0 s (12 cycles) 8 8 1 xxx00100 5.0 s (5 cycles) 3.0 s (3 cycles) 2.0 s (2 cycles) 422 xxx01100 6.5 s (13 cycles) 3.5 s (7 cycles) 3.0 s (6 cycles) xxx01010 5.5 s (11 cycles) 3.0 s (6 cycles) 2.5 s (5 cycles) 2 2 1 xxx00100 5.0 s (5 cycles) 3.0 s (3 cycles) 2.0 s (2 cycles)
rev.1.00 oct 27, 2008 page 72 of 128 rej03b0266-0100 3804 group (spec.l) [i 2 c special mode status register (s3)] 0012 16 the i 2 c special mode status register (s3: address 0012 16 ) consists of the flags indicating i 2 c operating state in the i 2 c special mode, which is set by the i 2 c special mode control register (s3d: address 0017 16 ). the stop condition flag is va lid in all ope rating modes. ? bit 0: slave address 0 comparison flag (aas0) bit 1: slave address 1 comparison flag (aas1) bit 2: slave address 2 comparison flag (aas2) these flags indicate a comparison result of address data. these flags are valid only when the slave address control bit (mslad) is ?1?. in the 7-bit addressing format of the slave reception mode, the respective slave address i (i = 0, 1, 2) comparison flags corresponding to the i 2 c slave address registers 0 to 2 are set to ?1? when an address data immediat ely after an occurrence of a start condition agrees with the high-order 7-bit slave address stored in the i 2 c slave address registers 0 to 2 (addresses 0ff7 16 to 0ff9 16 ). in the 10-bit addressing format of the slave mode, the respective slave address i (i = 0, 1, 2) co mparison flags corresponding to the i 2 c slave address registers are set to ?1? when an address data is compared with the 8 bits consistin g of the slave address stored in the i 2 c slave address registers 0 to 2 and the rwb bit, and the first byte agrees. these flags are initialized to ?0? at reset, when the slave address control bit (mslad) is ?0?, or when writing data to the i 2 c data shift register (s0: address 0011 16 ). ? bit 5: scl pin low hold 2 flag (pin2) when the ack interrupt contro l bit (ackicon) and the ack clock bit (ack) are ?1?, this flag is set to ?0? in synchronization with the falling of the data?s last scl clock, just before the ack clock. the scl pin is simultaneously held low, and the i 2 c interrupt reque st occurs. this flag is initialized to ?1? at reset, when the ack interrupt control bit (ackicon) is ?0?, or when writing ?1? to the scl pin low hold 2 flag set bit (pin2in). the scl pin is held low when either the scl pin low hold bit (pin) or the scl pin low hold 2 flag (pin2) becomes ?0?. the low hold state of the scl pin is released when both the scl pin low hold bit (pin) and the scl pin low hold 2 flag (pin2) are ?1?. ? bit 7: stop condition flag (spcf) this flag is set to ?1? when a stop condition occurs. this flag is initialized to ?0? at reset, when the i 2 c-bus interface enable bit (es0) is ?0?, or when writing ?1? to the stop condition flag clear bit (spfcl). fig. 71 structure of i 2 c special mode status register i 2 c special mode status register (s3: address 0012 16 ) b7 b0 slave address 0 comparison flag 0: address disagreement 1: address agreement slave address 1 comparison flag 0: address disagreement 1: address agreement slave address 2 comparison flag 0: address disagreement 1: address agreement not used (return ?0? when read) not used (undefined when read) scl pin low hold 2 flag 0: scl pin low hold 1: scl pin low release (note) not used (return ?0? when read) stop condition flag 0: no detection 1: detection note: in order that the low hold state of the scl pin may release, it is necessary that the scl pin low hold 2 flag and the scl pin low hold bit (pin) are ?1? simultaneously. spcf pin2 aas2 aas1 aas0
rev.1.00 oct 27, 2008 page 73 of 128 rej03b0266-0100 3804 group (spec.l) [i 2 c special mode control register (s3d)] 0017 16 the i 2 c special mode control register (s3d: address 0017 16 ) controls special functi ons such as occurrence timing of reception interrupt request and extending slave address comparison to 3 bytes. ? bit 1: ack interrupt control bit (ackicon) this bit controls the timing of i 2 c interrupt request occurrence at completion of data receiving du e to master reception or slave reception. when this bit is ?0?, the scl pin low hold bit (pin) is set to ?0? in synchronization with the fa lling of the last scl clock, including the ack clock. the scl pin is simultaneously held low, and the i 2 c interrupt request occurs. when this bit is ?1? and the ack clock bit (ack) is ?1?, the scl pin low hold 2 flag (pin2) is set to ?0? in synchronization with the falling of the data?s last scl clock, just before the ack clock. the scl pin is simultaneously held low, and the i 2 c interrupt request occurs again. the ack bit can be changed after the contents of data are c onfirmed by using this function. ? bit 2: i 2 c slave address control bit (mslad) this bit controls a slave address. when this bit is ?0?, only the i 2 c slave address register 0 (address 0ff7 16 ) becomes valid as a slave address and a read/write bit. when this bit is ?1?, all of the i 2 c slave address registers 0 to 2 (addresses 0ff7 16 to 0ff9 16 ) become valid as a slave address and a read/write bit. in this ca se, when an address data agrees with any one of the i 2 c slave address registers 0 to 2, the slave address comparison flag (aas ) is set to ?1? and the i 2 c slave address comparison flag corresponding to the agreed i 2 c slave address registers 0 to 2 is also set to ?1?. ? bit 5: scl pin low hold 2 flag set bit (pin2in) writing ?1? to this bit initializes the scl pin low hold 2 flag (pin2) to ?1?. when writing ?0?, nothing is generated. ? bit 6: scl pin low hold set bit (pin2hd) when the scl pin low hold bit (pin) becomes ?0?, the scl pin is held low. however, the scl pin low hold bit (pin) cannot be set to ?0? by software. the sc l pin low hold set bit (pin2hd) is used to, hold the scl pin in the low state by software. when writing ?1? to this bit, the sc l pin low hold 2 flag (pin2) becomes ?0?, and the scl pin is held low. when writing ?0?, nothing occurs. ? bit 7: stop condition flag clear bit (spfcl) writing ?1? to this bit initiali zes the stop condition flag (spcf) to ?0?. when writing ?0?, nothing is generated. fig. 72 structure of i 2 c special mode control register i 2 c special mode control register (s3d: address 0017 16 ) b7 b0 not used (fix this bit to ?0?.) ack interrupt control bit 0: at communication completion 1: at falling of ack clock and communication completion slave address control bit 0: one-byte slave address compare mode 1: three-byte slave address compare mode not used (return ?0? when read) not used (fix this bit to ?0?.) scl pin low hold 2 flag set bit (notes 1, 2) writing ?1? to this bit initializes the scl pin low hold 2 flag to ?1?. scl pin low hold set bit (notes 1, 2) when writing ?1? to this bit, the scl pin low hold 2 flag becomes ?0? and the scl pin is held low. stop condition flag clear bit (note 2) writing ?1? to this bit initializes the stop condition flag to ?0?. spfcl pin2in mslad acki con pin2hd notes 1: do not write ?1? to these bits simultaneously. 2: return ?0? when read
rev.1.00 oct 27, 2008 page 74 of 128 rej03b0266-0100 3804 group (spec.l) address data communication there are two address data communication formats, namely, 7- bit addressing format and 10-bit addressing format. the respective address communicati on formats are described below. ? 7-bit addressing format to adapt the 7-bit ad dressing format, set the 10bit sad bit of the i 2 c control register (s1d: address 0014 16 ) to ?0?. the first 7- bit address data transmitted from the master is compared with the high-order 7-bit slave ad dress stored in the i 2 c slave address register. at the time of this comparison, address comparison of the rwb bit of the i 2 c slave address regist er is not performed. for the data transmission form at when the 7-bit addressing format is selected, refer to figure 73, (1) and (2). ? 10-bit addressing format to adapt the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (s1d: address 0014 16 ) to ?1?. an address comparison is performed between the first-byte address data transmitted from the master and th e 8-bit slave address stored in the i 2 c slave address register. at the time of this comparison, an address comparison between the rwb bit of the i 2 c slave address register and the r/w bit which is the last bit of the address data transmitted from th e master is made. in the 10-bit addressing mode, the rwb bit which is the last bit of the address data not only specifies the di rection of communication for control data, but also is proc essed as an address data bit. when the first-byte address data agree with the slave address, the aas bit of the i 2 c status register (s1: address 0013 16 ) is set to ?1?. after the second-byte addres s data is stored into the i 2 c data shift register (s0: address 0011 16 ), perform an address comparison between the second-byte data and the slave address by software. when the address data of the 2 bytes agree with the slave address, set the rwb bit of the i 2 c slave address register to ?1? by software. this processing can make the 7-bit slave address and r/w data agree, which are received after a restart condition is detected, with the value of the i 2 c slave address register. for the data tr ansmission format when the 10- bit addressing format is selected , refer to figure 73, (3) and (4) . fig. 73 address data communication format 7 bits 1 to 8 bits (1) a master-transmitter transmits data to a slave-receiver ?0? (2) a master-receiver receives data from a slave-transmitter (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address ?1? (4) a master-receiver receives data from a slave-transmitter with a 10-bit address 1 to 8 bits 7 bits 7 bits 7 bits 1 to 8 bits 8 bits 8 bits 7 bits 1 to 8 bits 1 to 8 bits 1 to 8 bits 1 to 8 bits 1 to 8 bits : master to slave : slave to master s: start condition p: stop condition a: ack bit r/w: read/write bit sr: restart condition ?1? ?0? ?0? s slave address r/w data a/a data aa p s slave address r/w data a data aa p s r/w slave address 1st 7 bits data a/a data aa p a r/w data a data aa p s r/w a a sr slave address 1st 7 bits slave address 2nd bytes slave address 2nd bytes slave address 1st 7 bits
rev.1.00 oct 27, 2008 page 75 of 128 rej03b0266-0100 3804 group (spec.l) example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz and in the ack return mode is shown below. (1) set a slave address in th e high-order 7 bits of the i 2 c slave address register and ?0? into the rwb bit. (2) set the ack return mode and scl = 100 khz by setting ?85 16 ? in the i 2 c clock control regist er (s2: address 0015 16 ). (3) set ?00 16 ? in the i 2 c status register (s1: address 0013 16 ) so that transmission/reception mode can become initializing condition. (4) set a communication enab le status by setting ?08 16 ? in the i 2 c control register (s1d: address 0014 16 ). (5) confirm the bus free condition by the bb flag of the i 2 c status register (s1: address 0013 16 ). (6) set the address data of the de stination of transmission in the high-order 7 bits of the i 2 c data shift register (s0: address 0011 16 ) and set ?0? in the least significant bit. (7) set ?f0 16 ? in the i 2 c status register (s1: address 0013 16 ) to generate a start condition. at this time, an scl for 1 byte and an ack clock automatically occur. (8) set transmit data in the i 2 c data shift register (s0: address 0011 16 ). at this time, an scl and an ack clock automatically occur. (9) when transmitting control data of more than 1 byte, repeat step (8). (10) set ?d0 16 ? in the i 2 c status register (s1: address 0013 16 ) to generate a stop condition if ack is not returned from slave reception side or transmission ends. example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, in the ack non-return mode and using the addressing fo rmat is shown below. (1) set a slave address in th e high-order 7 bits of the i 2 c slave address register and ?0? in the rwb bit. (2) set the no ack clock mode and scl = 400 khz by setting ?25 16 ? in the i 2 c clock control register (s2: address 0015 16 ). (3) set ?00 16 ? in the i 2 c status register (s1: address 0013 16 ) so that transmission/reception mode can become initializing condition. (4) set a communication enab le status by setting ?08 16 ? in the i 2 c control register (s1d: address 0014 16 ). (5) when a start condition is received, an address comparison is performed. (6) ? when all transmitted addresses are ?0? (general call): ad0 of the i 2 c status register (s1: address 0013 16 ) is set to ?1? and an interrupt request signal occurs. ? when the transmitted addresse s agree with the address set in (1): aas of the i 2 c status register (s1: address 0013 16 ) is set to ?1? and an interrupt request signal occurs. ? in the cases other than the above ad0 and aas of the i 2 c status register (s1: address 0013 16 ) are set to ?0? and no interrupt request signal occurs. (7) set dummy data in the i 2 c data shift register (s0: address 0011 16 ). (8) when receiving control data of more than 1 byte, repeat step (7). (9) when a stop condition is detected, the communication ends.
rev.1.00 oct 27, 2008 page 76 of 128 rej03b0266-0100 3804 group (spec.l) precautions when using multi-master i 2 c bus inter- face (1) read-modify-write instruction the precautions when the read-m odify-write instruction such as seb, clb etc. is executed for each register of the multi-master i 2 c-bus interface are described below. ?i 2 c data shift register (s0: address 0011 16 ) when executing the read-modif y-write instruction for this register during transfer, data may become a value not intended. ?i 2 c slave address registers 0 to 2 (s0d0 to s0d2: addresses 0ff7 16 to0ff9 16 ) when the read-modify-write inst ruction is executed for this register at detecting the stop condition, data may become a value not intended. it is becau se h/w changes the read/write bit (rwb) at the above timing. ?i 2 c status register (s1: address 0013 16 ) do not execute the read-modif y-write instruction for this register because all bits of th is register are changed by h/w. ?i 2 c control register (s1d: address 0014 16 ) when the read-modify-write inst ruction is executed for this register at detecting the star t condition or at completing the byte transfer, data may become a value not intended. because h/w changes the bit counter ( bc0-bc2) at the above timing. ?i 2 c clock control register (s2: address 0015 16 ) the read-modify-write instruct ion can be executed for this register. ?i 2 c start/stop condition contro l register (s2d: address 0016 16 ) the read-modify-write instruct ion can be executed for this register. (2) start condition generating procedure using multi-master 1. procedure example (the nece ssary conditions of the gener- ating procedure are describe d as the following 2 to 5. : lda ? (taking out of slave address value) sei (interrupt disabled) bbs 5, s1, busbusy (bb flag confirming and branch process) busfree: sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of start condition generating) cli (interrupt enabled) : busbusy: cli (interrupt enabled) : 2. use ?branch on bit set? of ?bbs 5, s1, -? for the bb flag confirming and branch process. 3. use ?sta $12, stx $12? or ?sty $12? of the zero page addressing instruction for writ ing the slave address value to the i 2 c data shift register. 4. execute the branch instruction of above 2 and the store instruction of above 3 conti nuously shown the above proce- dure example. 5. disable interrupts during the following three process steps: ? bb flag confirming ? writing of slave address value ? trigger of start condition generating when the condition of the bb flag is bus busy, enable interrupts immediately. (3) restart condition generating procedure 1. procedure example (the nece ssary conditions of the gener- ating procedure are describe d as the following 2 to 4.) execute the following procedure when the pin bit is ?0? : ldm #$00, s1 (select slave receive mode) lda ? (taking out of slave address value) sei (interrupt disabled) sta s0 (writing of slave address value) ldm #$f0, s1 (trigger of restart condition generating) cli (interrupt enabled) : 2. select the slave receive mode when the pin bit is ?0?. do not write ?1? to the pin bit. neither ?0? nor ?1? is specified for the writing to the bb bit. the trx bit becomes ?0? and the sda pin is released. 3. the scl pin is released by writing the slave address value to the i 2 c data shift register. 4. disable interrupts during the following two process steps: ? writing of slave address value ? trigger of restart condition generating (4) writing to i 2 c status register do not execute an instruction to set the pin bit to ?1? from ?0? and an instruction to set the ms t and trx bits to ?0? from ?1? simultaneously. it is because it may enter the state that the scl pin is released and the sda pi n is released after about one machine cycle. do not execute an instruction to set the mst and trx bits to ?0? from ?1? simu ltaneously when the pin bit is ?1?. it is because it may become the same as above. (5) process of after stop condition generating do not write data in the i 2 c data shift register s0 and the i 2 c status register s1 until the bus busy flag bb becomes ?0? after generating the stop condition in th e master mode. it is because the stop condition waveform mi ght not be normally generated. reading to the above register s does not have the problem.
rev.1.00 oct 27, 2008 page 77 of 128 rej03b0266-0100 3804 group (spec.l) reset circuit to reset the microcomputer, reset pin should be held at an ?l? level for 16 cycles or more of x in . then the reset pin is returned to an ?h? level (the power source voltage should be between 2.7 v and 5.5 v, and th e oscillation should be stable), reset is released. after the reset is completed, the program starts from the address contained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). input to the reset pin in the following procedure. ? when power source is stabilized (1) input ?l? level to reset pin. (2) input ?l? level for 16 cycles or more to x in pin. (3) input ?h? level to reset pin. ? at power-on (1) input ?l? level to reset pin. (2) increase the power source voltage to 2.7 v. (3) wait for td(p-r) until intern al power source has stabilized. (4) input ?l? level for 16 cycles or more to x in pin. (5) input ?h? level to reset pin. fig. 74 reset circuit example fig. 75 reset sequence v cc reset v cc reset power source voltage detection circuit example at v cc = 5 v 0 v 0 v v cc reset 0.2v cc or less 0 v 0 v v cc reset td(p-r)+x in 16 cycles or more 5 v 5 v 2.7 v 2.7 v td(p-r)+x in 16 cycles or more reset internal reset data address sync x in ? ? ? ? fffc fffd ad h , l ? ? ? ?ad l ad h notes 1: the frequency relation of f(x in ) and f( ) is f(x in ) = 8 ? f( ). 2: the question marks (?) indicate an undefined state that depends on the previous state. reset address from the vector table. x in : 10.5 to 18.5 clock cycles
rev.1.00 oct 27, 2008 page 78 of 128 rej03b0266-0100 3804 group (spec.l) fig. 76 internal status at reset 0 1 0 1 1 0 0 0 x 0 0 0 1 0 0 0 x 0 x 0 x 0 x 0 x 0 x 1 x 0 x 0 00 16 00 16 00 16 ff 16 01 16 ff 16 00 16 00 16 ff 16 ff 16 ff 16 ff 16 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x 1 0 x 1 x 0 x 1 x 0 x 1 x 0 x 1 x 0 x 1 x 1 x 1 x 1 x 0 x 1 x 0 x 00 16 00 16 00 16 fffc 16 contents fffd 16 contents x xx1x x x x note : x: not fixed. since the initial values for other than above mentioned registers and ram contents are indefinite at reset, they must be set. port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) timer 12, x count source selection register (t12xcss) timer y, z count source selection register (tyzcss) misrg i 2 c data shift register (s0) i 2 c special mode status register (s3) i 2 c status register (s1) i 2 c control register (s1d) i 2 c clock control register (s2) i 2 c start/stop condition control register (s2d) i 2 c special mode control register (s3d) transmit/receive buffer register 1 (tb1/rb1) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart1 control register (uart1con) baud rate generator 1 (brg1) serial i/o2 control register (sio2con) watchdog timer control register (wdtcon) serial i/o2 register (sio2) prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer xy mode register (tm) prescaler x (prex) timer x (tx) prescaler y (prey) timer y (ty) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) register contents address 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 timer z (low-order) (tzl) timer z (high-order) (tzh) timer z mode register (tzm) pwm control register (pwmcon) pwm prescaler (prepwm) pwm register (pwm) baud rate generator 3 (brg3) transmit/receive buffer register 3 (tb3/rb3) serial i/o3 status register (sio3sts) serial i/o3 control register (sio3con) uart3 control register (uart3con) ad/da control register (adcon) ad conversion register 1 (ad1) da1 conversion register (da1) da2 conversion register (da2) ad conversion register 2 (ad2) interrupt source selection register (intsel) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 1 (icon1) interrupt control register 2 (icon2) flash memory control register 0 (fmcr0) flash memory control register 1 (fmcr1) flash memory control register 2 (fmcr2) port p0 pull-up control register (pull0) port p1 pull-up control register (pull1) port p2 pull-up control register (pull2) port p3 pull-up control register (pull3) port p4 pull-up control register (pull4) port p5 pull-up control register (pull5) port p6 pull-up control register (pull6) i 2 c slave address register 0 (s0d0) i 2 c slave address register 1 (s0d1) i 2 c slave address register 2 (s0d2) processor status register program counter (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) (59) (60) (61) (62) (63) (64) (65) (66) (67) (68) (69) (70) (71) (72) (73) (74) (75) (76) (77) (78) 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0fe0 16 0fe1 16 0fe2 16 0ff0 16 0ff1 16 0ff2 16 0ff3 16 0ff4 16 0ff5 16 0ff6 16 0ff7 16 0ff8 16 0ff9 16 (ps) (pc h ) (pc l ) register contents address 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 00 16 00 16 ff 16 00 16 00 16 00 16 00 16 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 x 0 x 0 0 0 x x x x x 0 0 0 0 0 x x x x x 1 0 1 0 0 x x x x x 0 0 0 0 0 x x x x x 0 x 0 0 0 x x x x x 0 0 0 1 0 x x x x x 1 0 0 1 0 x x x x x 0 0 0 1 1 x x x x 00 16 00 16 00 16 00 16 00 16 00 16 00 16 1 0000 0 0 0 0 0000 0 1 0 1 0010 0 1 0 00 16
rev.1.00 oct 27, 2008 page 79 of 128 rej03b0266-0100 3804 group (spec.l) clock generating circuit the 3804 group (spec.l) has two built-in oscillation circuits: main clock x in -x out oscillation circuit and sub clock x cin - x cout oscillation circuit. an oscill ation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer?s recommended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip.(an exte rnal feed-back resistor may be needed depending on conditions.) however, an external feed- back resistor is needed between x cin and x cout . immediately after power on, only the x in oscillation circuit starts oscilla ting, and x cin and x cout pins function as i/o ports. ? frequency control (1) middle-speed mode the internal clock is the frequency of x in divided by 8. after reset is released, this mode is selected. (2) high-speed mode the internal clock is half the frequency of x in . (3) low-speed mode the internal clock is half the frequency of x cin . (4) low power dissipation mode the low power consumption ope ration can be realized by stopping the main clock x in in low-speed mode. to stop the main clock, set bit 5 of the cpu mode register to ?1?. when the main clock x in is restarted (by setting the main clock stop bit to ?0?), set sufficient time for oscillation to stabilize. the sub-clock x cin -x cout oscillating circuit can not directly input clocks that are generated externally. accordingly, make sure to cause an external resonator to oscillate. oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at an ?h? level, and x in and x cin oscillators stop. when the oscillation stabilizing time set after stp instruction released bit (bit 0 of address 0010 16 ) is ?0?, the prescaler 12 is set to ?ff 16 ? and timer 1 is set to ?01 16 ?. when the oscillation stabilizing time set after stp instruction released bit is ?1?, set the sufficient time for oscillation of used oscillator to stabilize since nothing is set to the prescaler 12 and timer 1. after stp instruction is released , the input of the prescaler 12 is connected to count source which had set at executing the stp instruction, and the output of the prescaler 12 is connected to timer 1. oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the cpu (remains at ?h?) until timer 1 underfl ows. the internal clock is supplied for the first time, when timer 1 un derflows. this en sures time for the clock oscillation using the ceramic resonators to be stabilized. when the oscillator is restarted by reset, apply ?l? level to the reset pin until the oscillati on is stable since a wait time will not be generated. in the flash memory l version, the built-in power source circuit is switched to the low power di ssipation mode at executing the stp instruction to reduce consum ption current. at returning from the stp instruction, the built-in power source circuit is switched to the normal mode, but a specified time is required from when the power supply to the flash memory is started until the flash memory operation is enable d. in this version, set a wait time of 100 s or more with the oscillation stabilizing time set after stp instruction releas ed function by using timer 1. (2) wait mode if the wit instruction is executed, the internal clock stops at an ?h? level, but the oscillator does not stop. the internal clock restarts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. to ensure that the interrupts will be received to release the stp or wit state, their interrupt enable bits must be set to ?1? before executing of the stp or wit instruction. when releasing the stp state, th e input of the prescaler 12 and timer 1 is connected to the count source which had set at executing the stp instruction a nd the prescaler 12 and timer 1 will start counting. set the timer 1 interrupt enable bit to ?0? before executing th e stp instruction. ? if you switch the mode between middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub clock to stabilize, especially immediately after power on a nd at returning from stop mode. when switching the mode betw een middle/high-speed and low-speed, set the frequency on condition that f(x in ) > 3 f(x cin ). ? when using the quartz-crystal oscillator of high frequency, such as 16 mhz etc., it may be necessary to select a specific oscillator with the specification demanded. ? when using the oscillation st abilizing time set after stp instruction released bit set to ?1?, evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12.
rev.1.00 oct 27, 2008 page 80 of 128 rej03b0266-0100 3804 group (spec.l) fig. 77 ceramic resonator circuit fig. 78 external clock input circuit x cin x cout x in x out c in c out c cin c cout rf rd rd note 1 : insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. also, if the oscillator manufacturer?s data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between x in and x out following the instruction. x in x out external oscillation circuit v cc v ss open x cin x cout v cc v ss c cin rf rd c cout
rev.1.00 oct 27, 2008 page 81 of 128 rej03b0266-0100 3804 group (spec.l) fig. 79 system clock generating circuit block diagram (single-chip mode) wit instruction stp instruction timing (internal clock) s r q s r q main clock stop bit s r q 1/2 1/4 x in x out x cout x cin interrupt request interrupt disable flag l reset port x c switch bit ?1? ?0? low-speed mode high-speed or middle-speed mode middle-speed mode high-speed or low-speed mode main clock division ratio selection bits (1) main clock division ratio selection bits (1) notes 1 : either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the cpu mode register. when low-speed mode is selected, set port x c switch bit (b4) to ?1?. 2 :f(x in )/16 is supplied as the count source to the prescaler 12 at reset, the count source before executing the stp instruction is supplied as the count source at executing stp instruction. 3 : when bit 0 of misrg is ?0?, timer 1 is set ?01 16 ? and prescaler 12 is set ?ff 16 ? automatically. when bit 0 of misrg is ?1? , set the appropriate value to them in accordance with oscillation stabilizing time required by the using oscillator because nothing is automatically set into timer 1 and prescaler 12. 4 : although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. prescaler 12 timer 1 reset or stp instruction (2) reset (3) (4) stp instruction divider
rev.1.00 oct 27, 2008 page 82 of 128 rej03b0266-0100 3804 group (spec.l) fig. 80 state transitions of system clock cm 4 : port x c switch bit 0 : i/o port function (stop oscillating) 1 : x cin- x cout oscillating function cm 5 : main clock (x in -x out ) stop bit 0 : operating 1 : stopped cm 7 , cm 6 : main clock division ratio selection bit b7 b6 00 : = f(x in )/2 (high-speed mode) 01 : = f(x in )/8 (middle-speed mode) 10 : = f(x cin )/2 (low-speed mode) 1 1 : not available reset cm 4 ?1? ?0? c m 4 ? 0 ? ? 1 ? c m 6 ? 1 ? ? 0 ? c m 4 ? 1 ? ? 0 ? c m 6 ? 1 ? ? 0 ? cm 7 ?1? ?0? cm 4 ?1? ?0? cm 5 ?1? ?0? cm 6 ?1? ?0? cm 6 ?1? ?0? cpu mode register (cpum : address 003b 16 ) b7 b4 c m 7 ? 0 ? ? 1 ? c m 6 ? 1 ? ? 0 ? high-speed mode (f( ) = 4 mhz) cm 7 =0 cm 6 =0 cm 5 =0 (8 mhz oscillating) cm 4 =0 (32 khz stopped) high-speed mode (f( ) = 4 mhz) cm 7 =0 cm 6 =0 cm 5 =0 (8 mhz oscillating) cm 4 =1 (32 khz oscillating) notes 1 : switch the mode by the allows shown between the mode bloc ks. (do not switch between t he modes directly without an allow.) 2 : the all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3 : timer operates in the wait mode. 4 : when the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and timer 1 in middle/high- speed mode. 5 : when the stop mode is ended, a delay of approximately 0.25 s occurs by timer 1 and timer 2 in low-speed mode. 6 : wait until oscillation stabilizes after oscillating the main clock x in before the switching from the low-speed mode to middle/ high-speed mode. 7 : the example assumes that 8 mhz is being applied to the x in pin and 32 khz to the x cin pin. indicates the internal clock. middle-speed mode (f( ) = 1 mhz) cm 7 =0 cm 6 =1 cm 5 =0 (8 mhz oscillating) cm 4 =0 (32 khz stopped) middle-speed mode (f( ) = 1 mhz) cm 7 =0 cm 6 =1 cm 5 =0 (8 mhz oscillating) cm 4 =1 (32 khz oscillating) low-speed mode (f( ) = 16 khz) cm 7 =1 cm 6 =0 cm 5 =0 (8 mhz oscillating) cm 4 =1 (32 khz oscillating) low-speed mode (f( ) = 16 khz) cm 7 =1 cm 6 =0 cm 5 =1 (8 mhz stopped) cm 4 =1 (32 khz oscillating)
rev.1.00 oct 27, 2008 page 83 of 128 rej03b0266-0100 3804 group (spec.l) flash memory mode the 3804 group (spec.l)?s flash memory version has the flash memory that can be rewritte n with a single power source. for this flash memory, three flash memory modes are available in which to read, program, an d erase: the parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and the cpu rewrite mode in which the flash memory can be manipulated by the central processing unit (cpu). this flash memory version has some blocks on the flash memory as shown in figure 81 and each block can be erased. in addition to the ordinary us er rom area to store the mcu operation control program, the fl ash memory has a boot rom area that is used to store a pr ogram to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode c ontrol program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the user?s application system. this boot rom area can be rewritten in only parallel i/o mode. summary table 15 lists the summary of the 3804 group (spec.l) flash memory version. note: 1. the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. this boot rom area can be erased and written in only parallel i/o mode. notes: 1. v cc = av cc = 2.7 v to 5.5 v, topr = 0 c to 60 c, unless otherwise noted. 2. definition of programming/erase count the programming/erase count refers to the num ber of erase operations per block. for exam ple, if block a is a 2 k-byte block and 2,048 1-byte writes are performed, all to different addresses, after which block a is erased, the programming/erase count is 1. note that for each erase operation it is not possible to perform more than one programming (write) operation to the same address (overwrites prohibited). 3. this is the number of times for which all electrical characteristics are guarantee d after a programming or erase operation. ( the guarantee covers the range from 1 to maximum value.) 4. on systems where reprogramming is performed a large number of ti mes, it is possible to reduce the effective number of overwri tes by sequentially shifting the write address, so that as much of the available area of the bloc k is used up through successive programming (write) operations before an erase operation is perform ed. for example, if each programming operation uses 16 bytes of space, a maximum of 128 programming operations may be performed before it becomes necessary to erase the block in order to continue. in this way the effective number of overwrites can be kept low. the effect ive overwrite count can be further reduced by evenly dividing operations between block a and block b. it is recommended that data be retained on the number of times each block has been erased and a limit count set. 5. if a block erase error occurs, execute t he clear status register command followed by the block erase command a minimum of thr ee times and until the erase error is no longer generated. table 15 summary of 3804 group (spec.l)?s flash memory version item specifications power source voltage (v cc )v cc = 2.7 to 5.5 v program/erase v pp voltage (v pp )v cc = 2.7 to 5.5 v flash memory mode 3 modes; parallel i/o mode, standard serial i/o mode, cpu rewrite mode erase block division user rom area/data rom area refer to figure 81. boot rom area (1) not divided (4 kbytes) program method in units of bytes erase method block erase program/erase control method program/erase control by software command number of commands 5 commands number of program/erase times 100(max.) rom code protection available in parallel i/o mode and standard serial i/o mode table 16 electrical characteristics of flash memory (program rom) symbol parameter test conditions limits unit min. typ. max. ? byte programming time v cc = 5.0 v, topr = 25 c ? 60 400 s ? block erase time (block 1) v cc = 5.0 v, topr = 25 c ? 0.5 9 s (block 2) ? 0.9 9 s (block 3) ? 1.3 9 s (block a, b) ? 0.3 9 s
rev.1.00 oct 27, 2008 page 84 of 128 rej03b0266-0100 3804 group (spec.l) boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the standard serial i/o mode becomes unusable.) see figure 81 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset and the cnv ss pin high after pulling the p4 5 /txd 1 pin and cnv ss pin high, the cpu starts operating (start address of progr am is stored into addresses fffc 16 and fffd 16 ) using the control program in the boot rom area. this mode is called the ?boot mode?. also, user rom area can be rewritten using the control program in the boot rom area. block address block addresses refer to the maximum address of each block. these addresses are used in the block erase command. cpu rewrite mode in cpu rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the central processing unit (cpu). in cpu rewrite mode, only the user rom area shown in figure 81 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite control program must be transferred to internal ram area before it can be executed. fig. 81 block diagram of built-in flash memory data block a: 2 kbytes block 3: 24 kbytes block 2: 16 kbytes block 1: 8 kbytes block 0: 8 kbytes ffff 16 e000 16 c000 16 8000 16 2000 16 1800 16 1000 16 user rom area data block b: 2 kbytes sfr area internal ram area (2 kbytes) ffff 16 1000 16 0fff 16 0fe0 16 083f 16 0040 16 0000 16 ffff 16 f000 16 boot rom area 4 kbytes sfr area internal flash memory area (60 kbytes) ram notes 1 : the boot rom area can be rewritten in a parallel i/o mode. (access to except boot rom area is disabled.) 2 : to specify a block, use the maximum address in the block.
rev.1.00 oct 27, 2008 page 85 of 128 rej03b0266-0100 3804 group (spec.l) outline performance cpu rewrite mode is usable in th e single-chip or boot mode. the only user rom area can be rewritten. in cpu rewrite mode, the cpu erases, programs and reads the internal flash memory as instructed by software commands. this rewrite control program must be transferred to internal ram area before it can be executed. the mcu enters cpu rewrite m ode by setting ?1? to the cpu rewrite mode select bit (bit 1 of address 0fe0 16 ). then, software commands can be accepted. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verifi ed by reading the status register. figure 82 shows the flash me mory control register 0. bit 0 of the flash memory control register 0 is the ry/by status flag used exclusively to read the operating status of the flash memory. during programming and er ase operations, it is ?0? (busy). otherwise, it is ?1? (ready). bit 1 of the flash memory contro l register 0 is the cpu rewrite mode select bit. when this bit is set to ?1?, the mcu enters cpu rewrite mode. and then, software commands can be accepted. in cpu rewrite mode, the cpu b ecomes unable to access the internal flash memory directly . therefore, use the control program in the internal ram for write to bit 1. to set this bit 1 to ?1?, it is necessary to write ?0? and then write ?1? in succession to bit 1. the bit can be set to ?0? by only writing ?0?. bit 2 of the flash memory control register 0 is the 8 kb user block e/w enable bit. by setting combination of bit 4 of the flash memory control register 2 and this bit as shown in table 17, e/w is disabled to user block in the cpu rewriting mode. bit 3 of the flash memory contro l register 0 is the flash memory reset bit used to reset the control circuit of internal flash memory. this bit is used when flash me mory access has failed. when the cpu rewrite mode select bit is ?1?, setting ?1? for this bit resets the control circuit. to release the reset, it is necessary to set this bit to ?0?. bit 5 of the flash memory control register 0 is the user rom area select bit and is valid only in the boot mode. setting this bit to ?1? in the boot mode switches an accessible area from the boot rom area to the user rom area. to use the cpu rewrite mode in the boot mode, set this bit to ?1 ?. to rewrite bit 5, execute the user original reprogramming control software transferred to the internal ram in advance. bit 6 of the flash memory control register 0 is the program status flag. this bit is set to ?1? when writing to flash memory is failed. when program error occurs, the block cannot be used. bit 7 of the flash memory contro l register 0 is the erase status flag. this bit is set to ?1? when erasing flash memory is failed. when erase error occurs, the block cannot be used. figure 83 shows the flash me mory control register 1. bit 0 of the flash memory control register 1 is the erase suspend enable bit. by setting this bit to ?1?, the erase suspend mode to suspend erase processing tempor ary when block erase command is executed can be used. in order to set this bit to ?1?, writing ?0? and ?1? in succession to bit 0. in order to set this bit to ?0?, write ?0? only to bit 0. bit 1 of the flash memory control register 1 is the erase suspend request bit. by setting this bit to ?1? when erase suspend enable bit is ?1?, the erase processing is suspended. bit 6 of the flash memory control register 1 is the erase suspend flag. this bit is cleared to ?0? at the flash erasing. fig. 82 structure of flash memory control register 0 fig. 83 structure of flash memory control register 1 flash memory cont rol register 0 (fmcr0: address : 0fe0 16 : initial value: 01 16 ) ry/by status flag 0 : busy (being written or erased) 1 : ready cpu rewrite mode select bit (1) 0 : cpu rewrite mode invalid 1 : cpu rewrite mode valid 8 kb user block e/w enable bit (1, 2) 0 : e/w disabled 1 : e/w enabled flash memory reset bit (3, 4) 0 : normal operation 1 : reset not used (do not write ?1? to this bit.) user rom area select bit (5) 0 : boot rom area is accessed 1 : user rom area is accessed program status flag 0: pass 1: error erase status flag 0: pass 1: error b7 b0 notes 1 : for this bit to be set to ?1?, the user needs to write a ?0? and then a ?1? to it in succession. for this bit to be set to ?0?, write ?0? only to this bit. 2 : this bit can be written only when cpu rewrite mode select bit is ?1?. 3 : effective only when the cpu rewrite mode select bit = ?1?. fix this bit to ?0? when the cpu rewrite mode select bit is ?0?. 4 : when setting this bit to ?1? (when the control circuit of flash memory is reset), the flash memory cannot be accessed for 10 s. 5 : write to this bit in program on ram flash memory control register 1 (fmcr1: address : 0fe1 16 : initial value: 40 16 ) erase suspend enable bit (1) 0 : suspend invalid 1 : suspend valid erase suspend request bit (2) 0 : erase restart 1 : suspend request not used (do not write ?1? to this bit.) erase suspend flag 0 : erase active 1 : erase inactive (erase suspend mode) not used (do not write ?1? to this bit.) b7 b0 notes 1 : for this bit to be set to ?1?, the user needs to write a ?0? and then a ?1? to it in succession. for this bit to be set to ?0?, write ?0? only to this bit. 2 : effective only when the suspend enable bit = ?1?.
rev.1.00 oct 27, 2008 page 86 of 128 rej03b0266-0100 3804 group (spec.l) fig. 84 structure of flash memory control register 2 figure 85 shows a flowchart for se tting/releasing cp u rewrite mode. fig. 85 cpu rewrite mode set/rel ease flowchart be sure to execute flash memory control register 2 (fmcr2: address : 0fe2 16 : initial value: 45 16 ) not used not used (do not write ?1? to this bit.) not used all user block e/w enable bit (1, 2) 0 : e/w disabled 1 : e/w enabled not used b7 b0 notes 1 : for this bit to be set to ?1?, the user needs to write a ?0? and then a ?1? to it in succession. for this bit to be set to ?0?, write ?0? only to this bit. 2 : effective only when the cpu rewrite mode select bit = ?1?. table 17 state of e/w inhibition function all user block e/w enable bit 8 kb user block e/w enable bit 8 kb 2 block addresses c000 16 to ffff 16 16 kb + 24 kb block addresses 2000 16 to bfff 16 data block addresses 1000 16 to 1fff 16 0 0 e/w disabled e/w disabled e/w enabled 0 1 e/w disabled e/w disabled e/w enabled 1 0 e/w disabled e/w enabled e/w enabled 1 1 e/w enabled e/w enabled e/w enabled start single-chip mode or boot mode set cpu mode register (1) jump to control program transferred to internal ram (subsequent operations are executed by control program in this ram) transfer cpu rewrite mode control program to internal ram set cpu rewrite mode select bit to ?1? (by writing ?0? and then ?1? in succession) using software command executes erase, program, or other operation end write ?0? to cpu rewrite mode select bit set all user block e/w enable bit to ?1? (by writing ?0? and then ?1? in succession) set 8 kb user block e/w enable bit (at e/w disabled; writing ?0? , at e/w enabled; writing ?0? and then ?1? in succession execute read array command (2) set all user block e/w enable bit to ?0? set 8 kb user block e/w enable bit to ?0? notes 1 : set the main clock as follows depending on the clock division ratio selection bits of cpu mode register (bits 6, 7 of address 003b 16 ). 2 : before exiting the cpu rewrite mode after completing erase or program operation, always be sure to execute the read array command.
rev.1.00 oct 27, 2008 page 87 of 128 rej03b0266-0100 3804 group (spec.l) take the notes described below when rewriting the flash memory in cpu rewrite mode. (1) operation speed during cpu rewrite mode, set the system clock to 4.0 mhz or less using the clock division rati o selection bits (bits 6 and 7 of address 003b 16 ). (2) instructions inhi bited against use the instructions which refer to the internal data of the flash memory cannot be used during cpu rewrite mode. (3) interrupts the interrupts cannot be used dur ing cpu rewrite mode because they refer to the internal data of the flash memory. (4) watchdog timer if the watchdog timer has been al ready activated, internal reset due to an underflow will not oc cur because the watchdog timer is surely cleared during program or erase. (5) reset reset is always valid. the mcu is activated using the boot mode at release of reset in the condition of cnv ss = ?h?, so that the program will begin at the address which is stored in addresses fffc 16 and fffd 16 of the boot rom area.
rev.1.00 oct 27, 2008 page 88 of 128 rej03b0266-0100 3804 group (spec.l) software commands table 18 lists the so ftware commands. after setting the cpu rewrite mode select bit to ?1?, execute a software command to specify an erase or program operation. each software command is explained below. ? read array command (ff 16 ) the read array mode is entere d by writing the command code ?ff 16 ? in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (d 0 to d 7 ). the read array mode is retained until another command is written. ? read status register command (70 16 ) when the command code ?70 16 ? is written in the first bus cycle, the contents of the status register are read out at the data bus (d 0 to d 7 ) by a read in the second bus cycle. the status register is expl ained in the next section. ? clear status register command (50 16 ) this command is used to clear th e bits sr4 and sr5 of the status register after they have been set. these bits indicate that operation has ended in an error. to use this command, write the command code ?50 16 ? in the first bus cycle. ? program command (40 16 ) program operation starts when the command code ?40 16 ? is written in the first bus cycle. th en, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and veri fication) will start. whether the write operation is completed can be confirmed by read status register or the ry/by status flag. when the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (d 0 to d 7 ). the status register bit 7 (sr7) is set to ?0? at the same time the write operation starts and is returned to ?1? upon completion of the write operation. in this cas e, the read status register mode remains active until the read array command (ff 16 ) is written. the ry/by status flag of the flash memory control register is ?0? during write operation and ?1? when the write operation is completed as is the status register bit 7. at program end, program result s can be checked by reading the status register. fig. 86 program flowchart notes: 1. srd = status register data 2. wa = write address, wd = write data 3. ba = block address to be erased (input the maximum address of each block.) 4. x denotes a given address in the user rom area. start write ?40 16 ? sr7 = ? 1 ? ? or ry/by = ? 1 ? ? read status register program completed no yes write write address write data sr4 = ?0?? program error no yes table 18 list of software co mmands (cpu rewrite mode) command cycle number first bus cycle second bus cycle mode address data (d 0 to d 7 ) mode address data (d 0 to d 7 ) read array 1 write x (4) ff 16 read status register 2 write x 70 16 read x srd (1) clear status register 1 write x 50 16 program 2 write x 40 16 write wa (2) wd (2) block erase 2 write x 20 16 write ba (3) d0 16
rev.1.00 oct 27, 2008 page 89 of 128 rej03b0266-0100 3804 group (spec.l) ? block erase command (20 16 /d0 16 ) by writing the command code ?20 16 ? in the first bus cycle and the confirmation command code ?d0 16 ? and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. whether the block erase operation is completed can be confirmed by read status register or the ry/by status flag of flash memory control register. at the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status re gister can be read out. the status register bit 7 (sr7) is set to ?0? at the same time the block erase operation starts and is returned to ?1? upon completion of the block erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is written. the ry/by status flag is ?0? during block erase operation and ?1? when the block erase operation is completed as is the status register bit 7. after the block erase ends, er ase results can be checked by reading the status register. for de tails, refer to the section where the status register is detailed. fig. 87 erase flowchart write ?20 16 ? write ?d0 16 ? blockaddress read status register sr7 = ? 1 ? ? or ry/by = ? 1 ? ? erase completed (write read command ?ff 16 ?) no yes start sr5 = ?0?? erase error yes no
rev.1.00 oct 27, 2008 page 90 of 128 rej03b0266-0100 3804 group (spec.l) ? status register the status register shows the operating status of the flash memory and whether erase op erations and programs ended successfully or in error. it ca n be read in the following ways: (1) by reading an arbitrary address from the user rom area after writing the read stat us register command (70 16 ) (2) by reading an arbitrary addr ess from the user rom area in the period from when the program starts or erase operation starts to when the read array command (ff 16 ) is input. also, the status register can be cleared by writing the clear status register command (50 16 ). after reset, the status register is set to ?80 16 ?. table 19 shows the status register. each bit in this register is explained below. ? sequencer status (sr7) the sequencer status indicates th e operating status of the flash memory. this bit is set to ?0 ? (busy) during write or erase operation and is set to ?1? when these ope rations ends. after power-on, the sequencer st atus is set to ?1? (ready). ? erase status (sr5) the erase status indicates the ope rating status of erase operation. if an erase error occurs, it is set to ?1?. when the erase status is cleared, it is reset to ?0?. ? program status (sr4) the program status indicates th e operating status of write operation. when a write error occurs, it is set to ?1?. the program status is reset to ?0? when it is cleared. if ?1? is written for any of the sr5 and sr4 bits, the read array, program, and block erase commands are not accepted. before executing these commands, execute the clear status register command (50 16 ) and clear the status register. also, if any commands are not correct, both sr5 and sr4 are set to ?1?. table 19 definition of each bit in status register each bit of srd bits status name definition ?1? ?0? sr7 (bit 7) sequencer status ready busy sr6 (bit 6) reserved ?? sr5 (bit 5) erase status terminated in error terminated normally sr4 (bit 4) program status terminated in error terminated normally sr3 (bit 3) reserved ?? sr2 (bit 2) reserved ?? sr1 (bit 1) reserved ?? sr0 (bit 0) reserved ??
rev.1.00 oct 27, 2008 page 91 of 128 rej03b0266-0100 3804 group (spec.l) full status check by performing full status check, it is possible to know the execution results of erase and program operations. figure 88 shows a full status check flowch art and the action to be taken when each error occurs. fig. 88 full status check flowchart and remedial procedure for errors read status register sr4 = ?1? and sr5 = ?1?? command sequence error yes execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. no sr5 = ?0?? yes erase error no should an erase error occur, the block in error cannot be used. sr4 = ?0?? yes program error no end (block erase, program) note: when one of sr5 and sr4 is set to ?1 ?, none of the read array, program, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. should a program error occur, the block in error cannot be used.
rev.1.00 oct 27, 2008 page 92 of 128 rej03b0266-0100 3804 group (spec.l) functions to inhibit rewriting flash memory version to prevent the contents of inte rnal flash memory from being read out or rewritten easily, this mcu incorporates a rom code protect function for use in parallel i/o mode and an id code check function for use in standard serial i/o mode. ? rom code protect function the rom code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the rom code protect control address (address ffdb 16 ) in parallel i/o mode. figure 89 shows the rom code protect control address (address ffdb 16 ). (this address exists in the user rom area.) if one or both of the pair of ro m code protect bits is set to ?0?, the rom code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. the ro m code protect is implemented in two levels. if level 2 is selected, the flash memory is protected even against readout by a shipment insp ection lsi tester , etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to ?00?, the rom code protect is turned off, so that the contents of internal flash memory can be readout or modified. once the rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parall el i/o mode. use the serial i/o or cpu rewrite mode to rewrite the contents of the rom code protect reset bits. rewriting of only the rom code protect control address (address ffdb 16 ) cannot be performed. wh en rewriting the rom code protect reset bit, rewrite the whole user rom area (block 0) containing the rom code protect control address. fig. 89 structure of rom code protect control address rom code protect contro l address (address ffdb 16 ) romcp (ff 16 when shipped) reserved bits (?1? at read/write) rom code protect level 2 set bits (romcp2) (1, 2) b3 b2 0 0 : protect enabled 0 1 : protect enabled 1 0 : protect enabled 1 1 : protect disabled rom code protect reset bits (romcr) (3) b5 b4 0 0 : protect removed 0 1 : protect set bits effective 1 0 : protect set bits effective 1 1 : protect set bits effective rom code protect level 1 set bits (romcp1) (1) b7 b6 0 0 : protect enabled 0 1 : protect enabled 1 0 : protect enabled 1 1 : protect disabled b7 1 1 b0 notes 1 : when rom code protect is turned on, the internal flash memory is protected against readout or modificati on in parallel i/o mode. 2 : when rom code protect level 2 is turned on, rom code readout by a shipment inspection lsi tester, etc. also is inhibited. 3 : the rom code protect reset bits can be used to turn off rom code protect level 1 and rom code protect level 2. however, since these bits cannot be modified in parallel i/o mode, they need to be rewritten in serial i/o mode or cpu rewrite mode.
rev.1.00 oct 27, 2008 page 93 of 128 rej03b0266-0100 3804 group (spec.l) ? id code check function use this function in standard se rial i/o mode. when the contents of the flash memory are not blank, the id code sent from the programmer is compared with the id code written in the flash memory to see if they match. if the id codes do not match, the commands sent from the programmer are not accepted. the id code consists of 8-bit data, and its areas are ffd4 16 to ffda 16 . write a program which has had the id code preset at these addresses to the flash memory. fig. 90 id code store addresses id7 id6 id5 id4 id3 id2 id1 address rom code protect control interrupt vector area ffd5 16 ffd4 16 ffd6 16 ffd7 16 ffd8 16 ffd9 16 ffda 16 ffdb 16
rev.1.00 oct 27, 2008 page 94 of 128 rej03b0266-0100 3804 group (spec.l) parallel i/o mode the parallel i/o mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. use the external device (write r) only for 3804 group (spec.l) flash memory version. for details, refer to the user?s manual of each writer manufacturer. ? user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in figure 81 can be rewritten. bo th areas of flash memory can be operated on in the same way. the boot rom area is 4 kbytes in size and located at addresses f000 16 through ffff 16 . make sure program and block erase operations are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an eras e block operation is applied to only one 4 kbyte block. the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. therefore, using th e mcu in standard serial i/o mode, do not rewrite to the boot rom area.
rev.1.00 oct 27, 2008 page 95 of 128 rej03b0266-0100 3804 group (spec.l) standard serial i/o mode the standard serial i/o mode inputs and outputs the software commands, addresses a nd data needed to operate (read, program, erase, etc.) the internal flash memory. this i/o is clock synchronized serial. this m ode requires a purpose-specific peripheral unit. the standard serial i/o mode is different from the parallel i/o mode in that the cpu controls flash memory re write (uses the cpu rewrite mode), rewr ite data input and so forth. the standard serial i/o mode is started by connecting ?h? to the cnv ss pin and ?h? to the p4 5 (bootent) pin, and releasing the reset operation. (in the ordinary microcomputer mode, set cnv ss pin to ?l? level.) this control program is written in the boot rom area when the product is shipped from renesas. accordingly, make note of the fact that the st andard serial i/o mode cannot be used if the boot rom area is re written in parallel i/o mode. the standard serial i/ o mode has st andard serial i/o mode 1 of the clock synchronous serial and standa rd serial i/o mode 2 of the clock asynchronous serial. table 20 and 21 show description of pin function (standard serial i/ o mode). figures 91 to 96 show the pin connections for the standard serial i/o mode. figures 97 and 98 show the operating wave form for standard serial i/o mode 1 and the operating waveform for standard serial i/o mode 1, respectively. figures 99 and 100 show the connection examples in standard serial i/o mode. in standard serial i/o mode, only the user rom area shown in figure 81 can be rewritten. the boot rom area cannot be written. in standard serial i/o mode, a 7- byte id code is used. when there is data in the flash memory, this function determines whether the id code sent from the peripheral unit (programmer) and those written in the flash memory match. the commands sent from the peripheral unit (programmer) are not accepted unless the id code matches.
rev.1.00 oct 27, 2008 page 96 of 128 rej03b0266-0100 3804 group (spec.l) table 20 description of pin function (flash memory serial i/o mode 1) pin name signal name i/o function v cc ,v ss power supply i apply 2.7 to 5.5 v to the v cc pin and 0 v to the v ss pin. cnv ss cnv ss i after input of port is set, input ?h? level. reset reset input i reset input pin. to reset the microcomputer, reset pin should be held at an ?l? level for 16 cycles or more of x in . x in clock input i connect an oscill ation circuit between the x in and x out pins. as for the connection method, refer to the ?clock generating circuit?. x out clock output o av ss analog power supply input connect av ss to v ss . v ref reference voltage input i apply reference voltage of a/d to this pin. p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 3 , p5 0 ? p5 7 , p6 0 ? p6 7 i/o port i/o input ?l? or ?h? level, or keep open. p4 4 rxd input i serial data input pin. p4 5 txd output o serial data output pin. p4 6 s clk input i serial clock input pin. p4 7 busy output o busy signal output pin. table 21 description of pin function (flash memory serial i/o mode 2) pin name signal name i/o function v cc ,v ss power supply i apply 2.7 to 5.5 v to the v cc pin and 0 v to the v ss pin. cnv ss cnv ss i after input of port is set, input ?h? level. reset reset input i reset input pin. to reset the microcomputer, reset pin should be held at an ?l? level for 16 cycles or more of x in . x in clock input i connect an oscill ation circuit between the x in and x out pins. as for the connection method, refer to the ?clock generating circuit?. x out clock output o av ss analog power supply input connect av ss to v ss . v ref reference voltage input i apply reference voltage of a/d to this pin. p0 0 ? p0 7 , p1 0 ? p1 7 , p2 0 ? p2 7 , p3 0 ? p3 7 , p4 0 ? p4 3 , p5 0 ? p5 7 , p6 0 ? p6 7 i/o port i/o input ?l? or ?h? level, or keep open. p4 4 rxd input i serial data input pin. p4 5 txd output o serial data output pin. p4 6 s clk input i input ?l? level. p4 7 busy output o busy signal output pin.
rev.1.00 oct 27, 2008 page 97 of 128 rej03b0266-0100 3804 group (spec.l) fig. 91 connection for standard serial i/o mode 1 (M38049FFLHP/kp) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 44 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 6 p1 4 p1 5 p1 7 p2 7( led 7) p2 0( led 0) p2 1( led 1) p2 2( led 2) p2 3( led 3) p2 4( led 4) p2 5( led 5) p2 6( led 6) v ss x out x in p4 2 /int 1 reset cnv ss p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 5 /t x d 3 p3 4 /r x d 3 p3 1 /da 2 p3 0 /da 1 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p3 7 /s rdy3 p3 6 /s clk3 p3 3 /scl p3 2 /sda p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p6 2 /an 2 p4 7 /s rdy1 /cntr 2 p5 3 /s rdy2 M38049FFLHP/kp 32 30 29 28 25 23 20 19 18 17 27 22 21 31 26 24 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 5 reset cnv ss * rxd txd sclk busy * connect oscillation circuit. indicates flash memory pin. package code: plqp0064kb-a (64p6q-a) / plqp0064ga-a (64p6u-a) v cc v ss
rev.1.00 oct 27, 2008 page 98 of 128 rej03b0266-0100 3804 group (spec.l) fig. 92 connection for standard serial i/o mode 2 (M38049FFLHP/kp) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 44 p0 0 /an 8 p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 6 p1 4 p1 5 p1 7 p2 7( led 7) p2 0( led 0) p2 1( led 1) p2 2( led 2) p2 3( led 3) p2 4( led 4) p2 5( led 5) p2 6( led 6) v ss x out x in p4 2 /int 1 reset cnv ss p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 5 /t x d 3 p3 4 /r x d 3 p3 1 /da 2 p3 0 /da 1 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 5 /an 5 p6 4 /an 4 p6 3 /an 3 p3 7 /s rdy3 p3 6 /s clk3 p3 3 /scl p3 2 /sda p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p6 2 /an 2 p4 7 /s rdy1 /cntr 2 p5 3 /s rdy2 M38049FFLHP/kp 32 30 29 28 25 23 20 19 18 17 27 22 21 31 26 24 1 2 3 4 6 7 8 9 10 11 12 13 14 15 16 5 reset cnv ss * rxd txd busy * connect oscillation circuit. indicates flash memory pin. package code: plqp0064kb-a (64p6q-a) / plqp0064ga-a (64p6u-a) v cc v ss ?l? input
rev.1.00 oct 27, 2008 page 99 of 128 rej03b0266-0100 3804 group (spec.l) fig. 93 connection for standard serial i/o mode 1 (m38049fflsp) p3 0 /da 1 p3 1 /da 2 p3 4 /r x d 3 p3 5 /t x d 3 p0 0 /an 8 p2 0 (led 0 ) p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 1 (led 1 ) p2 2 (led 2 ) p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) p2 7 (led 7 ) p3 2 /sda p3 3 /scl p3 6 / s clk3 p3 7 / s rdy3 m38049fflsp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p4 2 /int 1 cnv ss p4 0 /int 40 /x cout x in x out v ss reset p5 3 /s rdy2 p6 5 /an 5 p4 1 /int 00 /x cin p4 7 /s rdy1 / cntr 2 * v ss reset cnv ss r x d t x d s clk busy v cc package code: prdp0064ba-a (64p4b) * connect oscillation circuit. indicates flash memory pin.
rev.1.00 oct 27, 2008 page 100 of 128 rej03b0266-0100 3804 group (spec.l) fig. 94 connection for standard serial i/o mode 2 (m38049fflsp) p3 0 /da 1 p3 1 /da 2 p3 4 /r x d 3 p3 5 /t x d 3 p0 0 /an 8 p2 0 (led 0 ) p0 1 /an 9 p0 2 /an 10 p0 3 /an 11 p0 4 /an 12 p0 5 /an 13 p0 6 /an 14 p0 7 /an 15 p1 0 /int 41 p1 1 /int 01 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p2 1 (led 1 ) p2 2 (led 2 ) p2 3 (led 3 ) p2 4 (led 4 ) p2 5 (led 5 ) p2 6 (led 6 ) p2 7 (led 7 ) p3 2 /sda p3 3 /scl p3 6 / s clk3 p3 7 / s rdy3 m38049fflsp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v cc v ref av ss p6 7 /an 7 p6 6 /an 6 p6 4 /an 4 p6 3 /an 3 p6 2 /an 2 p6 1 /an 1 p6 0 /an 0 p5 7 /int 3 p5 6 /pwm p5 5 /cntr 1 p5 4 /cntr 0 p5 2 /s clk2 p5 1 /s out2 p5 0 /s in2 p4 6 /s clk1 p4 5 /t x d 1 p4 4 /r x d 1 p4 3 /int 2 p4 2 /int 1 cnv ss p4 0 /int 40 /x cout x in x out v ss reset p5 3 /s rdy2 p6 5 /an 5 p4 1 /int 00 /x cin p4 7 /s rdy1 / cntr 2 * v ss reset cnv ss r x d t x d ?l? input busy v cc package code: prdp0064ba-a (64p4b) * connect oscillation circuit. indicates flash memory pin.
rev.1.00 oct 27, 2008 page 101 of 128 rej03b0266-0100 3804 group (spec.l) fig. 95 connection for standard serial i/o mode 1 (m38049fflwg) 3 2 1 8 7 6 5 4 p6 1 /an 1 p6 0 /an 0 p5 5 /cntr 1 p5 2 /s clk2 p5 0 /s in2 p4 4 /r x d 1 p4 3 /int 2 cnv ss p6 7 /an 7 p6 6 /an 6 p5 7 /int 3 p5 4 /cntr 0 p4 7 /s rdy1 /cntr 2 p4 5 /t x d 1 p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 0 /da 1 p3 1 /da 2 p3 2 /sda p3 7 /s rdy3 p1 7 p1 4 p1 5 p1 6 p3 3 /scl p3 4 /r x d 3 p0 0 /an 8 p0 5 /an 13 p1 2 p1 3 p2 6 (led 6 )p2 7 (led 7 ) p3 5 /t x d 3 p0 1 /an 9 p0 3 /an 11 p0 6 /an 14 p1 1 /int 01 p2 5 (led 5 )p2 3 (led 3 )p2 4 (led 4 ) p3 6 /s clk3 p0 2 /an 10 p0 4 /an 12 p0 7 /an 15 p1 0 /int 41 p2 0 (led 0 )p2 1 (led 1 )p2 2 (led 2 ) p6 2 /an 2 p6 3 /an 3 v ref av ss v cc v ss x in x out abcdefgh abcdefgh 50 46 44 41 40 32 31 30 51 47 45 42 39 27 29 28 53 52 48 43 38 37 26 25 56 55 54 49 33 36 35 34 1 64 58 59 57 24 22 23 60 61 4 7 12 14 21 20 62 63 5 8 10 13 17 19 2 3 6 9 11 15 16 18 pin configuration (top view) package code: ptlg0064ja-a (64f0g) * connect oscillation circuit. indicates flash memory pin. 3 2 1 8 7 6 5 4 cnv ss reset v cc * v ss busy t x d r x d s clk p6 5 /an 5 p6 4 /an 4 p5 6 /pwm p5 3 /s rdy2 p5 1 /s out2 p4 6 /s clk1 p4 2 /int 1 reset
rev.1.00 oct 27, 2008 page 102 of 128 rej03b0266-0100 3804 group (spec.l) fig. 96 connection for standard serial i/o mode 2 (m38049fflwg) 3 2 1 8 7 6 5 4 p6 1 /an 1 p6 0 /an 0 p5 5 /cntr 1 p5 2 /s clk2 p5 0 /s in2 p4 4 /r x d 1 p4 3 /int 2 cnv ss p6 7 /an 7 p6 6 /an 6 p5 7 /int 3 p5 4 /cntr 0 p4 7 /s rdy1 /cntr 2 p4 5 /t x d 1 p4 0 /int 40 /x cout p4 1 /int 00 /x cin p3 0 /da 1 p3 1 /da 2 p3 2 /sda p3 7 /s rdy3 p1 7 p1 4 p1 5 p1 6 p3 3 /scl p3 4 /r x d 3 p0 0 /an 8 p0 5 /an 13 p1 2 p1 3 p2 6 (led 6 )p2 7 (led 7 ) p3 5 /t x d 3 p0 1 /an 9 p0 3 /an 11 p0 6 /an 14 p1 1 /int 01 p2 5 (led 5 )p2 3 (led 3 )p2 4 (led 4 ) p3 6 /s clk3 p0 2 /an 10 p0 4 /an 12 p0 7 /an 15 p1 0 /int 41 p2 0 (led 0 )p2 1 (led 1 )p2 2 (led 2 ) p6 2 /an 2 p6 3 /an 3 v ref av ss v cc v ss x in x out abcdefgh abcdefgh 50 46 44 41 40 32 31 30 51 47 45 42 39 27 29 28 53 52 48 43 38 37 26 25 56 55 54 49 33 36 35 34 1 64 58 59 57 24 22 23 60 61 4 7 12 14 21 20 62 63 5 8 10 13 17 19 2 3 6 9 11 15 16 18 pin configuration (top view) package code: ptlg0064ja-a (64f0g) * connect oscillation circuit. indicates flash memory pin. 3 2 1 8 7 6 5 4 cnv ss reset v cc v ss busy t x d r x d ?l?input p6 5 /an 5 p6 4 /an 4 p5 6 /pwm p5 3 /s rdy2 p5 1 /s out2 p4 6 /s clk1 p4 2 /int 1 reset *
rev.1.00 oct 27, 2008 page 103 of 128 rej03b0266-0100 3804 group (spec.l) fig. 97 operating waveform for standard serial i/o mode 1 fig. 98 operating waveform for standard serial i/o mode 2 power source reset cnv ss p4 5 (t x d) p4 6 (s clk ) p4 7 (busy) p4 4 (r x d) td(cnv ss -reset) td(p4 5 -reset) notes: in the standard serial i/o mode 1, input ?h? to the p4 6 pin. be sure to set the cnv ss pin to ?h? before rising reset. be sure to set the p4 5 pin to ?h? before rising reset. td(cnv ss -reset) td(p4 5 -reset) symbol min. max. typ. unit 0 0 ?? ms ms limits power source reset cnv ss p4 5 (t x d) p4 7 (busy) p4 4 (r x d) p4 6 (s clk ) td(cnv ss -reset) td(p4 5 -reset) td(cnv ss -reset) td(p4 5 -reset) symbol min. max. typ. unit 0 0 ?? ms ms limits notes: in the standard serial i/o mode 2, input ?h? to the p4 6 pin. be sure to set the cnv ss pin to ?h? before rising reset. be sure to set the p4 5 pin to ?h? before rising reset.
rev.1.00 oct 27, 2008 page 104 of 128 rej03b0266-0100 3804 group (spec.l) fig. 99 when using programmer (in standard serial i/ o mode 1) of suisei electronics system co., ltd, connection example 3804 group (spec. l) t_vdd t_vpp t_rxd t_sclk t_pgm/oe/md t_reset gnd reset circuit set the same termination as the single-chip mode. v cc p4 5 (t x d) p4 6 (sclk) p4 7 (busy) reset v ss av ss x in x out note: for the programming circuit, the wiring capacity of each signal pin must not exceed 47 pf. t_busy t_txd 4.7k p4 4 (r x d) cnv ss 4.7k n.c.
rev.1.00 oct 27, 2008 page 105 of 128 rej03b0266-0100 3804 group (spec.l) fig. 100 when using e8 programmer (in standard serial i/o mode 1), connection example 3804 group (spec. l) reset circuit set the same termination as the single-chip mode. v cc p4 5 (t x d) p4 4 (r x d) p4 6 (sclk) reset v ss av ss x in x out * 1 : open-collector buffer note : for the programming circuit, the wiring capacity of each signal pin must not exceed 47 pf. v cc 14 12 10 8 13 9 7 4 2 6 3 1 * 1 cnv ss 4.7 k 5 11 4.7 k p4 7 (busy) 4.7 k
rev.1.00 oct 27, 2008 page 106 of 128 rej03b0266-0100 3804 group (spec.l) notes notes on programming 1. processor status register (1) initializing of proc essor status register flags which affect program executio n must be initialized after a reset. in particular, it is essential to initialize the t and d flags because they have an important effect on calculations. after a reset, the contents of the processor status register (ps) are undefined except for the i flag which is ?1?. fig. 101 initialization of processor status register (2) how to reference the processor status register to reference the contents of the processor status register (ps), execute the php instruction once then read the contents of (s+1). if necessary, execute the plp instru ction to return the ps to its original status. fig. 102 stack memory contents after php instruction execution 2. decimal calculations (1) execution of decimal calculations the adc and sbc are the only instructions which will yield proper decimal notation, set the decimal mode flag (d) to ?1? with the sed instruction. af ter executing the adc or sbc instruction, execute another in struction before executing the sec, clc, or cld instruction. (2) notes on status flag in decimal mode when decimal mode is selected, the values of three of the flags in the status register (the n, v, and z flags) are invalid after a adc or sbc instruction is executed. the carry flag (c) is set to ?1? if a carry is generated as a result of the calculation, or is cleared to ?0 ? if a borrow is generated. to determine whether a calculation has generated a carry, the c flag must be initialized to ?0? before each calculation. to check for a borrow, the c flag must be initialized to ?1? before each calculation. fig. 103 execution of decimal calculations 3. jmp instruction when using the jmp instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 4. multiplication and division instructions ? the index x mode (t) and th e decimal mode (d) flags do not affect the mul and div instruction. ? the execution of these inst ructions does not change the contents of the processor status register. 5. ports the contents of the port direction registers cannot be read. the following cannot be used: ? the data transfer in struction (lda, etc.) ? the operation instruction when th e index x mode flag (t) is ?1? ? the instruction with the addres sing mode which uses the value of a direction register as an index ? the bit-test instruction (bbc or bbs, etc.) to a direction register ? the read-modify-write instructi ons (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direction registers. 6. instruction execution timing the instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the 740 family software manual. the frequency of the internal clock is the twice the x in cycle in high-speed mode, 8 times the x in cycle in middle-speed mode, and the twice the x cin in low-speed mode. reset initializing of flags main program stored ps (s) (s) + 1 set d flag to ?1? adc or sbc instruction nop instruction sec , clc , or cld instruction
rev.1.00 oct 27, 2008 page 107 of 128 rej03b0266-0100 3804 group (spec.l) countermeasures against noise (1) shortest wiring length 1. wiring for reset pin make the length of wiring which is connected to the reset pin as short as possible. especi ally, connect a capacitor across the reset pin and the v ss pin with the shortest possible wiring (within 20mm). the width of a pulse input into the reset pin is determined by the timing necessary conditions. if noise having a shorter pulse width than the standard is input to the reset pin, the reset is released before the internal st ate of the microcomputer is com- pletely initialized. this may cause a program runaway. fig. 104 wiring for the reset pin 2. wiring for clock input/output pins ? make the length of wiring whic h is connected to clock i/o pins as short as possible. ? make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. ? separate the v ss pattern only for osc illation from other v ss patterns. if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a program failure or program runaway. also, if a potential di fference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscillator, the correct cl ock will not be input in the microcomputer. fig. 105 wiring for clock i/o pins (2) connection of bypass capacitor across v ss line and v cc line in order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 f bypass capacitor across the v ss line and the v cc line as follows: ? connect a bypass capacitor across the v ss pin and the v cc pin at equal length. ? connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. ? use lines with a larger diameter than other signal lines for v ss line and v cc line. ? connect the power source wiring via a bypass capacitor to the v ss pin and the v cc pin. fig. 106 bypass capacitor across the v ss line and the v cc line reset reset circuit noise v ss v ss n.g. reset circuit v ss reset v ss o.k. noise x in x out v ss n.g. x in x out v ss o.k. v ss v cc v ss v cc n.g. o.k.
rev.1.00 oct 27, 2008 page 108 of 128 rej03b0266-0100 3804 group (spec.l) (3) oscillator concerns in order to obtain the stabiliz ed operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. be careful especially when range of volta ge and temperature is wide. also, take care to prevent an osci llator that generates clocks for a microcomputer operation from bei ng affected by other signals. 1. keeping oscillator away fr om large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the toler- ance of current value flows. in the system using a microcom puter, there are signal lines for controlling motors, leds, and ther mal heads or others. when a large current flows through those signal lines, strong noise occurs because of mutual inductance. 2. installing osc illator away from signa l lines where potential levels change frequently install an oscillator and a conne cting pattern of an oscillator away from signal lines where potential levels change fre- quently. also, do not cross such signal lines over the clock lines or the signal lines wh ich are sensitive to noise. signal lines where potenti al levels change fre quently (such as the cntr pin signal line) may affect other lines at signal rising edge or falling edge. if such lines cro ss over a clock line, clock wave- forms may be deformed, which causes a microcomputer failure or a program runaway. fig. 107 wiring for a large current signal line/wiring of signal lines where potential levels change frequently (4) analog input the analog input pin is connected to the capacitor of a voltage comparator. accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of a/d conversion when the analog signal source of high-impedance is connected to an analog input pin. in order to obtain the a/d conversion result stabilized more , please lower the impedance of an analog signal source, or a dd the smoothing capacitor to an analog input pin. (5) difference of memory size when memory size differ in one group, actual values such as an electrical characteristics, a/d conversion accuracy, and the amount of proof of noise incorre ct operation may differ from the ideal values. when these products are used switching, perform system evaluation for each product of every after confirming product specification. (6) wiring to cnv ss pin the cnv ss pin determines the flash memory mode. connect the cnv ss pin the shortest possible to the gnd pattern which is supplied to the v ss pin of the microcomputer. in addition connecting an approximately 5 k . resistor in series to the gnd could improve noise immunity. in this case as well as the above mention, connect the pin the shor test possible to the gnd pattern which is supplied to the v ss pin of the microcomputer. note. when the boot mode or the standard serial i/o mode is used, a switch of the inpu t level to the cnv ss pin is required. fig. 108 wiring for the cnv ss x in x out v ss m microcomputer mutual inductance large current gnd x in x out v ss cntr do not cross n.g. 1. keeping oscillator away from large current signal lines 2. installing oscillator away from signal lines where potential levels change frequently the shortest cnv ss v ss approx. 5k the shortest (note) (note) note: shows the microcomputer?s pin.
rev.1.00 oct 27, 2008 page 109 of 128 rej03b0266-0100 3804 group (spec.l) notes on peripheral functions notes on input and output ports 1. notes in standby state in standby state *1 for low-power dissipat ion, do not make input levels of an i/o port ?undefined? . even when an i/o port of n- channel open-drain is set as output mode, if output data is ?1?, the aforementioned not es are necessary. pull-up (connect the port to v cc ) or pull-down (connect the port to v ss ) these ports through a resistor. when determining a resistance value, note the following points: ? external circuit ? variation of output levels during the ordinary operation when using built-in pull-up resistor, note on varied current values: ? when setting as an input port : fix its input level ? when setting as an output port : prevent current from flowing out to external exclusive input ports are always in a high-impedance state. an output transistor becomes an off state when an i/o port is set as input mode by the dire ction register, so that the port enter a high- impedance state. at this time, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels are ?undefined?. this ma y cause power source current. even when an i/o port of n-channel open-drain is set as output mode by the direction register, if the contents of the port latch is ?1?, the same phenomenon as that of an input port will occur. *1 standby state : stop mode by executing stp instruction wait mode by execut ing wit instruction 2. modifying output data with bit managing instruction when the port latch of an i/o port is modified with the bit managing instruction *1 , the value of the unspecified bit may be changed. i/o ports are set to input or out put mode in bit units. reading from a port register or writi ng to it involves the following operations. ? port in input mode read: read the pin level. write: write to the port latch. ? port in output mode read: read the port latch or read the output from the peripheral function (specifications diff er depending on the port). write: write to the port latch. (the port latch value is output from the pin.) since bit managing instructions *1 are read-modify-write instructions, *2 using such an instruction on a port register causes a read and write to be performed simultaneously on the bits other than the one specified by the instruction. when an unspecified bit is in input mode, its pin level is read and that value is written to the port la tch. if the previous value of the port latch differs from the pin level, the port latch value is changed. if an unspecified bit is in output mode, the port latch is generally read. however, for some ports the peripheral function output is read, and the value is written to the port latch. in this case, if the previous value of the port latch differs from the peripheral function output, the port latch value is changed. *1 bit managing instructions: seb and clb instructions *2 read-modify-write instructions: instructions that read memory in byte units, modify the value, and then write the result to the same location in memory in byte units termination of unused pins 1. terminate unused pins (1) output ports : open (2) i/o ports : ? set the i/o ports for the inpu t mode and conne ct them to v cc or v ss through each resistor of 1 k to 10 k . ports that permit the selecting of a built-in pull-up resistor can also use this resistor. set the i/o ports for the output mode and open them at ?l? or ?h?. ? when opening them in the output mode, the input mode of the initial status remains until the m ode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may increase in the in put mode. with regard to an effects on the system, thoroug hly perform syst em evaluation on the user side. ? since the direction register se tup may be changed because of a program runaway or noise, set direction registers by program periodically to increase th e reliability of program. (3) the av ss pin when not using the a/d converter : ? when not using the a/d converte r, handle a power source pin for the a/d converter, av ss pin as follows: av ss : connect to the v ss pin. 2. termination remarks (1) i/o ports : do not open in the input mode. ? the power source current may increase depending on the first- stage circuit. ? an effect due to noise may be easily produced as compared with proper termination (2) in 1 and shown on the above. (2) i/o ports : when setting for the input mode, do not connect to v cc or v ss directly. if the direction register set up changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and v cc (or v ss ). (3) i/o ports : when setting for the input mode, do not connect multiple ports in a lump to v cc or v ss through a resistor. if the direction register set up changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. ? at the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from micro- computer pins.
rev.1.00 oct 27, 2008 page 110 of 128 rej03b0266-0100 3804 group (spec.l) notes on interrupts 1. change of relevant register settings when the setting of the following re gisters or bits is changed, the interrupt request bit may be set to ?1?. when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? interrupt edge selecti on register (address 003a 16 ) ? timer xy mode register (address 0023 16 ) ? timer z mode register (address 002a 16 ) set the above listed registers or bits as the following sequence. fig. 109 sequence of changing relevant register when setting the followings, the interrupt request bit may be set to ?1?. ? when setting external interrupt active edge concerned register: interrupt edge selection register (address 003a 16 ) timer xy mode regi ster (address 0023 16 ) timer z mode register (address 002a 16 ) ? when switching interrupt sources of an interrupt vector address where two or more in terrupt sources are allocated. concerned register: interrupt source select ion register (address 0039 16 ) 2. check of interrupt request bit when executing the bbc or bbs instruction to an interrupt request bit of an interrupt requ est register immediately after this bit is set to ?0?, execute one or more instructions before executing the bbc or bbs instruction. fig. 110 sequence of check of interrupt request bit if the bbc or bbs instruction is executed immediately after an interrupt request bit of an interr upt request regist er is cleared to ?0?, the value of the interrupt request bit before being cleared to ?0? is read. set the interrupt edge select bit (active edge switch bit) or the interrupt (source) select bit to ?1?. nop (one or more instructions) set the corresponding interrupt enable bit to ?0? (disabled). set the corresponding interrupt request bit to ?0? (no interrupt request issued). set the corresponding interrupt enable bit to ?1? (enabled). nop (one or more instructions) clear the interrupt request bit to ?0? (no interrupt issued) execute the bbc or bbs instruction
rev.1.00 oct 27, 2008 page 111 of 128 rej03b0266-0100 3804 group (spec.l) notes on 8-bit timer (timer 1, 2, x, y) ? if a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). ? when switching the count sour ce by the timer 12, x and y count source selection bits, the value of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count input signals. therefore, select the timer count source before set the value to the prescaler and the timer. ? set the double-function port of the cntr 0 /cntr 1 pin and port p5 4 /p5 5 to output in the pulse output mode. ? set the double-function port of cntr 0 /cntr 1 pin and port p5 4 /p5 5 to input in the event count er mode and the pulse width measurement mode. notes on 16-bit timer (timer z) 1. pulse output mode ? set the double-function port of the cntr 2 pin and port p4 7 to output. 2. pulse period measurement mode ? set the double-function port of the cntr 2 pin and port p4 7 to input. ? a read-out of timer value is impossible in this mode. the timer can be written to only duri ng timer stop (no measurement of pulse period). ? since the timer latch in this mode is specialized for the read- out of measured values, do not perform any write operation during measurement. ? ?ffff 16 ? is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. consequently, the timer value at start of pulse period measurement depends on the timer value just before measurement start. 3. pulse width measurement mode ? set the double-function port of the cntr 2 pin and port p4 7 to input. ? a read-out of timer value is impossible in this mode. the timer can be written to only duri ng timer stop (no measurement of pulse period). ? since the timer latch in this mode is specialized for the read- out of measured values, do not perform any write operation during measurement. ? ?ffff 16 ? is set to the timer when the timer underflows or when the valid edge of measurement start/completion is detected. consequently, the timer valu e at start of pulse width measurement depends on the timer value just before measurement start. 4. programmable waveform generating mode ? set the double-function port of the cntr 2 pin and port p4 7 to output. 5. programmable one-shot generating mode ? set the double-function port of cntr 2 pin and port p4 7 to output, and of int 1 pin and port p4 2 to input in this mode. ? this mode cannot be used in low-speed mode. ? if the value of the cntr 2 active edge swit ch bit is changed during one-shot generating en abled or generating one-shot pulse, then the output level from cntr 2 pin changes. 6. all modes ? timer z write control which write control can be selected by the timer z write control bit (bit 3) of the timer z mode register (address 002a 16 ), writing data to both the latch and the timer at the same time or writing data only to the latch. when the operation ?writing data only to the latch? is selected, the value is set to the timer latch by writing data to the address of timer z and the timer is updated at next underflow. after reset release, the operation ?w riting data to both th e latch and the timer at the same time? is selected, and the value is set to both the latch and the timer at the same time by writing data to the address of timer z. in the case of writing data only to the latch, if writing data to the latch and an underflow are perform ed almost at the same time, the timer value may become undefined. ? timer z read control a read-out of timer value is impossible in pulse period measurement mode and pulse width measurement mode. in the other modes, a read-out of timer value is possible regardless of count operating or stopped. however, a read-out of time r latch value is impossible. ? switch of interrupt active edge of cntr 2 and int 1 each interrupt active edge de pends on setting of the cntr 2 active edge switch bit and the int 1 active edge selection bit. ? switch of count source when switching the count sour ce by the timer z count source selection bits, the value of timer count is altered in inconsiderable amount owing to generating of thin pulses on the count input signals. therefore, select the timer count source before setting the value to the prescaler and the timer.
rev.1.00 oct 27, 2008 page 112 of 128 rej03b0266-0100 3804 group (spec.l) notes on serial interface 1. notes when selecting clock synchronous serial i/o (1) stop of transmission operation as for serial i/oi (i = 1, 3) th at can be used as either a clock synchronous or an asynchronous (u art) serial i/o, clear the serial i/oi enable bit and the transmit enable bit to ?0? (serial i/oi and transmit disabled). since transmission is not stoppe d and the transmission circuit is not initialized even if only the seri al i/oi enable bit is cleared to ?0? (serial i/oi disabled), the in ternal transmission is running (in this case, since pins txdi, rxdi, s clk i, and s rdy i function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/oi enable bit is set to ?1? at this time, the data during internally shifting is output to the txdi pi n and an operation failure occurs. (2) stop of receive operation as for serial i/oi (i = 1, 3) th at can be used as either a clock synchronous or an asynchronous (u art) serial i/o, clear the receive enable bit to ?0? (receive disabled), or clear the serial i/oi enable bit to ?0? (serial i/oi disabled). (3) stop of transmit/receive operation as for serial i/oi (i = 1, 3) th at can be used as either a clock synchronous or an asynchronous (uart) serial i/o, clear both the transmit enable bit and receive enable bit to ?0? (transmit and receive disabled). (when data is transmitted and re ceived in the clock synchronous serial i/o mode , any one of data transmission and reception cannot be stopped.) in the clock synchronous serial i/o mode, the same clock is used for transmission and reception. if any one of transmission and reception is disabled, a bit error occurs be cause transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also operates for data recept ion. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to ?0? (transmit disabled). also, the transmission circuit is not initialized by clearing the serial i/oi enable bit to ?0? (serial i/oi disabled) (refer to (1) in 1.). 2. notes when selecting clock asynchronous serial i/o (1) stop of transmission operation clear the transmit enable bit to ?0? (transmit disabled). the transmission operation does not stop by clearing the serial i/oi enable bit (i = 1, 3) to ?0?. this is the same as (1) in 1. (2) stop of receive operation clear the receive enable bit to ?0? (receive disabled). (3) stop of transmit/receive operation only transmission operation is stopped. clear the transmit enable bit to ?0? (transmit disabled). the transmission operation does not stop by clearing the serial i/oi enable bit (i = 1, 3) to ?0?. this is the same as (1) in 1. only receive operation is stopped. clear the receive enable bit to ?0? (receive disabled). 3. s rdy i (i = 1, 3) output of reception side when signals are output from the s rdy i pin on the reception side by using an external clock in the clock synchronous serial i/o mode, set all of the receive enable bit, the s rdy i output enable bit, and the transmit enable bit to ?1? (transmit enabled). 4. setting serial i/oi (i = 1, 3) control register again set the serial i/oi control regi ster again after the transmission and the reception circuits are re set by clearing both the transmit enable bit and the receive enable bit to ?0?. fig. 111 sequence of setting serial i/oi (i = 1, 3) control register again 5. data transmission control with referrin g to transmit shift register completion flag after the transmit data is written to the transmit buffer register, the transmit shift register completion flag changes from ?1? to ?0? with a delay of 0.5 to 1.5 shift clocks. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. 6. transmission control when external clock is selected when an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to ?1? at ?h? of the s clk i (i = 1, 3) input level. also, write the transmit data to the transmit buffer regist er at ?h? of the s clk i input level. 7. transmit interrupt request when transmit enable bit is set when using the transmit interr upt, take the following sequence. (1) set the serial i/oi transmit interrupt enable bit (i = 1, 3) to ?0? (disabled). (2) set the transmit enable bit to ?1?. (3) set the serial i/oi transmit interrupt request bit (i = 1, 3) to ?0? after 1 or more instruction has executed. (4) set the serial i/oi transmit interrupt enable bit (i = 1, 3) to ?1? (enabled). when the transmission enable bit is set to ?1?, the transmit buffer empty flag and transmit shift register shift completion flag are also set to ?1?. therefore, regardless of se lecting which timing for the generating of transmit interrupts, the interrupt request is generated and the transmit interrupt request bit is set at this point. 8. writing to baud rate generator i (brgi) (i = 1, 3) write data to the baud rate generato r i (brgi) (i = 1, 3) while the transmission/recepti on operation is stopped. can be set with the ldm instruction at the same time set the bits 0 to 3 and bit 6 of the serial i/oi control register clear both the transmit enable bit (te) and the receive enable bit (re) to ?0? set both the transmit enable bit (te) and the receive enable bit (re), or one of them to ?1?
rev.1.00 oct 27, 2008 page 113 of 128 rej03b0266-0100 3804 group (spec.l) notes on pwm the pwm starts from ?h? level af ter the pwm enable bit is set to enable and ?l? level is te mporarily output from the pwm pin. the length of this ?l? leve l output is as follows: n + 1 2 f(x in ) (s) (count source selection bit = ?0?, where n is the value set in the prescaler) n + 1 f(x in ) (s) (count source selection bit = ?1?, where n is the value set in the prescaler) notes on a/d converter 1. analog input pin make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 f to 1 f. further, be sure to verify the operation of application products on the user side. an analog input pin includes the capacitor for analog voltage comparison. accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. this may cause the a/d conversion precision to be worse. 2. a/d converter power source pin the av ss pin is a/d converter power source pins. regardless of using the a/d conversion function or not, connect it as following : ?av ss : connect to the v ss line if the av ss pin is opened, the microc omputer may have a failure because of noise or others. 3. clock frequency during a/d conversion the comparator consists of a cap acity coupling, and a charge of the capacity will be lost if the clock frequency is too low. thus, make sure the following during an a/d conversion. ?f(x in ) is 500 khz or more ? do not execute the stp instruction 4. difference between at 8-bit reading in 10-bit a/d mode and at 8-bit a/d mode at 8-bit reading in the 10-bit a/d mode, ??1/2 lsb? correction is not performed to th e a/d conversion result. in the 8-bit a/d mode, the a/d co nversion characteristics is the same as 3802 group?s characteristics because ??1/2 lsb? correction is performed. notes on d/a converter 1. v cc when using d/a converter the d/a converter accuracy when v cc is 4.0 v or less differs from that of when v cc is 4.0 v or more. when using the d/a converter, we recommend using a v cc of 4.0 v or more. 2. dai conversion register when not using d/a con- verter when a d/a converter is not us ed, set all values of the dai conversion registers (i = 1, 2) to ?00 16 ?. the initial value after reset is ?00 16 ?. notes on watchdog timer ? make sure that the watchdog timer h does not underflow while waiting stop release, because the watchdog timer keeps counting during that term. ? when the stp instruction disable bit has been set to ?1?, it is impossible to switch it to ?0? by a program. notes on reset pin connecting capacitor in case where the reset signal rise time is long, connect a ceramic capacitor or others across the reset pin and the v ss pin. use a 1000 pf or more capacitor for high frequency use. when connecting the capacitor, note the following : ? make the length of the wiring which is connected to a capacitor as short as possible. ? be sure to verify the operati on of application products on the user side. if the several nanosecond or se veral ten nanosecond impulse noise enters the reset pin, it may cause a microcomputer failure. notes on low-speed operation mode 1. using sub-clock to use a sub-clock, fix bit 3 of the cpu mode register to ?1? or control the rd (refer to figure 112) resistance value to a certain level to stabilize an oscillati on. for resistance value of rd, consult the oscillator manufacturer. fig. 112 ceramic resonator circuit when bit 3 of the cpu mode regist er is set to ?0?, the sub-clock oscillation may stop. 2. switch between middle/high-speed mode and low- speed mode if you switch the mode betwee n middle/high-speed and low- speed, stabilize both x in and x cin oscillations. the sufficient time is required for the sub cl ock to stabilize, especially immediately after power on and at returning from stop mode. when switching the mode between middle/high-speed and low- speed, set the frequenc y on condition that f(x in ) > 3 f(x cin ). quartz-crystal oscillator when using the quartz-crystal osc illator of high frequency, such as 16 mhz etc., it may be necessary to select a specific oscillator with the specification demanded. x cin x cout c cin c cout rd rf
rev.1.00 oct 27, 2008 page 114 of 128 rej03b0266-0100 3804 group (spec.l) notes on restarting oscillation ? restarting oscillation usually, when the mcu stops the clock oscillation by stp instruction and the stp instruct ion has been released by an external interrupt source, the fixed values of timer 1 and prescaler 12 (timer 1 = ?01 16 ?, prescaler 12 = ?ff 16 ?) are automatically reloaded in orde r for the oscillation to stabilize. the user can inhibit the automatic setting by writing ?1? to bit 0 of misrg (address 0010 16 ). however, by setting this bit to ?1?, the previous values, set just before the stp instruction was executed, will remain in timer 1 and prescaler 12. therefore, you wi ll need to set an appropriate value to each register, in ac cordance with the oscillation stabilizing time, before executing the stp instruction. oscillation will restart when an ex ternal interrupt is received. however, internal clock is supplied to the cpu only when timer 1 starts to underflow. this ensures time for the clock oscillation using the ceramic resonators to be stabilized. notes on using stop mode ? register setting since values of the prescaler 12 and timer 1 are automatically reloaded when returning from the stop mode, set them again, respectively. (when the oscillation stabilizing time set after stp instruction released bit is ?0?) ? clock restoration after restoration from the stop mode to the normal mode by an interrupt request, the contents of the cpu mode register previous to the stp instruction execution are retained. accordingly, if both main clock and sub clock were oscillating before execution of the stp instruction, the oscilla tion of both clocks is resumed at restoration. in the above case, when the main clock side is set as a system clock, the oscillation stabilizin g time for approximately 8,000 cycles of the x in input is reserved at restoration from the stop mode. at this time, note that th e oscillation on the sub clock side may not be stabilized even after the lapse of the oscillation stabilizing time of the main clock side. notes on wait mode ? clock restoration if the wait mode is released by a reset when x cin is set as the system clock and x in oscillation is stopped during execution of the wit instruction, x cin oscillation stops, x in oscillations starts, and x in is set as the system clock. in the above case, the reset pin should be held at ?l? until the oscillation is stabilized. notes on cpu rewrite mode of flash memory version 1. operation speed during cpu rewrite mode , set the system clock 4.0 mhz or less using the main clock division ratio selection bits (bits 6 and 7 of address 003b 16 ). 2. instructions inhibited against use the instructions which refer to the internal data of the flash memory cannot be used dur ing the cpu rewrite mode. 3. interrupts inhibited against use the interrupts cannot be used during the cpu rewrite mode because they refer to the internal data of the flash memory. 4. watchdog timer in case of the watchdog timer has been running already, the internal reset generated by watchdog timer underflow does not happen, because of watchdog timer is always clearing during program or erase operation. 5. reset reset is always vali d. in case of cnv ss = ?h? when reset is released, boot mode is active. so the program starts from the address contained in address fffc 16 and fffd 16 in boot rom area. notes on flash memory version the cnv ss pin determines the flash memory mode. connect the cnv ss pin the shortest possible to the gnd pattern which is supplied to the v ss pin of the microcomputer. in addition connecting an approximately 5 k . resistor in series to the gnd could improve noise immunity. in this case as well as the above mention, connect the pin the shor test possible to the gnd pattern which is supplied to the v ss pin of the microcomputer. note. when the boot mode or the standard serial i/o mode is used, a switch of the inpu t level to the cnv ss pin is required. fig. 113 wiring for the cnv ss notes on handling of power source pins in order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (v cc pin) and gnd pin (v ss pin), and between power source pin (v cc pin) and analog power source input pin (av ss pin). besides, connect the capacito r to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 f?0.1 f is recommended. power source voltage when the power source voltage va lue of a microcomputer is less than the value which is indicat ed as the recommended operating conditions, the microc omputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the sy stem by this unstable operation. the shortest cnv ss v ss approx. 5k the shortest (note) (note) note: shows the microcomputer?s pin.
rev.1.00 oct 27, 2008 page 115 of 128 rej03b0266-0100 3804 group (spec.l) electrical characteristics absolute maximum ratings note: 1. this value is 300 mw except sp package. table 22 absolute maximum ratings symbol parameter conditions ratings unit v cc power source voltages all voltages are based on v ss . when an input voltage is measured, output transistors are cut off. ? 0.3 to 6.5 v v i input voltage p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , v ref ? 0.3 to v cc + 0.3 v v i input voltage p3 2 , p3 3 ? 0.3 to 5.8 v v i input voltage reset , x in ? 0.3 to v cc + 0.3 v v i input voltage cnv ss ? 0.3 to v cc + 0.3 v v o p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , x out ? 0.3 to v cc + 0.3 v output voltage v o output voltage p3 2 , p3 3 ? 0.3 to 5.8 v p d power dissipation ta=25 c 1000 (1) mw t opr operating temperature ? 20 to 85 c t stg storage temperature ? 65 to 125 c
rev.1.00 oct 27, 2008 page 116 of 128 rej03b0266-0100 3804 group (spec.l) recommended operating conditions notes: 1. when using a/d converter, see a/d c onverter recommended operating conditions. 2. the start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and o perating temperature range, etc.. particularly a high-frequency oscillator mi ght require some notes in the low voltage operation. 3. when the oscillation frequency has a duty cycle of 50%. 4. when using the microcomputer in low- speed mode, set the sub-clock input osci llation frequency on condition that f(x cin ) < f(x in )/3. table 23 recommended operating conditions (1) (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. v cc power source voltage (1) when start oscillating (2) 2.7 5.0 5.5 v high-speed mode f( ) = f(x in )/2 f(x in ) 8.4 mhz 2.7 5.0 5.5 v f(x in ) 12.5 mhz 4.0 5.0 5.5 f(x in ) 16.8 mhz 4.5 5.0 5.5 middle-speed mode f( ) = f(x in )/8 f(x in ) 12.5 mhz 2.7 5.0 5.5 v f(x in ) 16.8 mhz 4.5 5.0 5.5 v ss power source voltage 0 v v ih ?h? input voltage p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 0.8 v cc v cc v v ih ?h? input voltage p3 2 , p3 3 0.8 v cc 5.5 v v ih ?h? input voltage (when i 2 c-bus input level is selected) sda, scl 0.7 v cc 5.5 v v ih ?h? input voltage (when smbus input level is selected) sda, scl 1.4 5.5 v v ih ?h? input voltage reset , x in , cnv ss 0.8 v cc v cc v v ih ?h? input voltage x cin 2v cc v v il ?l? input voltage p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 00.2 v cc v v il ?l? input voltage (when i 2 c-bus input level is selected) sda, scl 00.3 v cc v v il ?l? input voltage (when smbus input level is selected) sda, scl 00.6v v il ?l? input voltage reset , cnv ss 00.2 v cc v v il ?l? input voltage x in 0.16 v cc v v il ?l? input voltage x cin 0.4 v f(x in ) main clock input oscillation frequency (3) high-speed mode f( ) = f(x in )/2 2.7 v cc < 4.0 v mhz 4.0 v cc < 4.5 v mhz 4.5 v cc 5.5 v 16.8 mhz middle-speed mode f( ) = f(x in )/8 2.7 v cc < 4.5 v mhz 4.5 v cc 5.5 v 16.8 mhz f(x cin ) sub-clock input oscillation frequency (3, 4) 32.768 50 khz 9v cc 0.3 ? () 1.05 3 --------------------------------------------------------- - 24 v cc 60 ? () 1.05 3 ----------------------------------------------------------- 15 v cc 39 + () 1.1 7 --------------------------------------------------------
rev.1.00 oct 27, 2008 page 117 of 128 rej03b0266-0100 3804 group (spec.l) notes: 1. the total output current is the sum of all the currents flow ing through all the applicable ports. the total average current i s an average value measured over 100 ms. the total peak current is the peak value of all the currents. 2. the peak output current is the peak current flowing in each port. 3. the average output current i ol (avg), i oh (avg) are average value measured over 100 ms. table 24 recommended operating conditions (2) (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. i oh(peak) ?h? total peak output current (1) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 ? 80 ma i oh(peak) ?h? total peak output current (1) p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 ? 80 ma i ol(peak) ?l? total peak output current (1) p0 0 -p0 7 , p1 0 -p1 7 , p3 0 -p3 7 80 ma i ol(peak) ?l? total peak output current (1) p2 0 -p2 7 80 ma i ol(peak) ?l? total peak output current (1) p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 80 ma i oh(avg) ?h? total average output current (1) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 ? 40 ma i oh(avg) ?h? total average output current (1) p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 ? 40 ma i ol(avg) ?l? total average output current (1) p0 0 -p0 7 , p1 0 -p1 7 , p3 0 -p3 7 40 ma i ol(avg) ?l? total average output current (1) p2 0 -p2 7 40 ma i ol(avg) ?l? total average output current (1) p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 40 ma i oh(peak) ?h? peak output current (2) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 ? 10 ma i ol(peak) ?l? peak output current (2) p0 0 -p0 7 , p1 0 -p1 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 10 ma i ol(peak) ?l? peak output current (2) p2 0 -p2 7 20 ma i oh(avg) ?h? average output current (3) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 ? 5ma i ol(avg) ?l? average output current (3) p0 0 -p0 7 , p1 0 -p1 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 5ma i ol(avg) ?l? average output current (3) p2 0 -p2 7 10 ma
rev.1.00 oct 27, 2008 page 118 of 128 rej03b0266-0100 3804 group (spec.l) electrical characteristics note: 1. p3 5 is measured when the p3 5 /t x d 3 p-channel output disable bit of the uart3 control register (bit 4 of address 0033 16 ) is ?0?. p4 5 is measured when the p4 5 /t x d 1 p-channel output disable bit of the uart1 control register (bit 4 of address 001b 16 ) is ?0?. table 25 electrical characteristics (1) (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. v oh ?h? output voltage (1) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 i oh = ? 10 ma v cc = 4.0 to 5.5 v v cc ? 2.0 v i oh = ?1.0 ma v cc = 2.7 to 5.5 v v cc ? 1.0 v ol ?l? output voltage p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 i ol = 10 ma v cc = 4.0 to 5.5 v 2.0 v i ol = 1.6 ma v cc = 2.7 to 5.5 v 1.0 v ol ?l? output voltage p2 0 -p2 7 i ol = 20 ma v cc = 4.0 to 5.5 v 2.0 v i ol = 1.6 ma v cc = 2.7 to 5.5 v 0.4 v t+ ? v t ? hysteresis cntr 0 , cntr 1 , cntr 2 , int 0 -int 4 0.4 v v t+ ? v t ? hysteresis rxd 1 , s clk1 , s in2 , s clk2 , rxd 3 , s clk3 0.5 v v t+ ? v t ? hysteresis reset 0.5 v i ih ?h? input current p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 v i = v cc (pin floating, pull-up transistor ?off?) 5.0 a i ih ?h? input current reset , cnv ss v i = v cc 5.0 a i ih ?h? input current x in v i = v cc 4.0 a i il ?l? input current p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 v i = v ss (pin floating, pull-up transistor ?off?) ? 5.0 a i il ?l? input current reset , cnv ss v i = v ss ? 5.0 a i il ?l? input current x in v i = v ss ? 4.0 a i il ?l? input current (at pull-up) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 , p3 1 , p3 4 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 v i = v ss v cc = 5.0 v ? 80 ? 210 ? 420 a v i = v ss v cc = 3.0 v ? 30 ? 70 ? 140 v ram ram hold voltage when clock stopped 1.8 v cc v
rev.1.00 oct 27, 2008 page 119 of 128 rej03b0266-0100 3804 group (spec.l) table 26 electrical characteristics (2) (v cc = 2.7 to 5.5 v, ta = ?20 to 85 c, f(x cin )=32.768 khz (stopped in middle-speed mode), output transistors ?off?, ad converter not operated) symbol parameter test conditions limits unit min. typ. max. i cc power source current high-speed mode v cc = 5.0 v f(x in ) = 16.8 mhz 5.5 8.3 ma f(x in ) = 12.5 mhz 4.5 6.8 f(x in ) = 8.4 mhz 3.5 5.3 f(x in ) = 4.2 mhz 2.2 3.3 f(x in ) = 16.8 mhz (in wit state) 2.2 3.3 v cc = 3.0 v f(x in ) = 8.4 mhz 2.7 4.1 ma f(x in ) = 4.2 mhz 1.8 2.7 f(x in ) = 2.1 mhz 1.1 1.7 middle-speed mode v cc = 5.0 v f(x in ) = 16.8 mhz 3.0 4.5 ma f(x in ) = 12.5 mhz 2.4 3.6 f(x in ) = 8.4 mhz 2.0 3.0 f(x in ) = 16.8 mhz (in wit state) 2.1 3.2 v cc = 3.0 v f(x in ) = 12.5 mhz 1.7 2.6 ma f(x in ) = 8.4 mhz 1.5 2.3 f(x in ) = 6.3 mhz 1.3 2.0 low-speed mode v cc = 5.0 v f(x in ) = stopped 410 630 a in wit state 4.5 6.8 v cc = 3.0 v f(x in ) = stopped 400 600 a in wit state 3.7 5.6 in stp state (all oscillation stopped) ta = 25 c0.553.0 a ta = 85 c0.75 increment when a/d conversion is executed f(x in ) = 16.8 mhz, v cc = 5.0 v in middle-, high-speed mode 1000 a
rev.1.00 oct 27, 2008 page 120 of 128 rej03b0266-0100 3804 group (spec.l) a/d converter characteristics notes: 1. 8-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?1?. 2. 10-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?0?. notes: 1. 8-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?1?. 2. 10-bit a/d mode: when the conversion mode selection bit (bit 7 of address 0038 16 ) is ?0?. d/a converter characteristics note: 1. using one d/a converter, with the value in the da c onversion register of the other d/a converter being ?00 16 ?. power source circuit ti ming characteristics table 27 a/d converter recommended operating conditions (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter conditions limits unit min. typ. max. v cc power source voltage (when a/d converter is used) 8-bit a/d mode (1) 2.7 5.0 5.5 v 10-bit a/d mode (2) 2.7 5.0 5.5 v ref analog convert reference voltage 2.0 v cc v av ss analog power source voltage 0 v v ia analog input voltage an 0 -an 15 0v cc v f(x in ) main clock input oscillation frequency (when a/d converter is used) 2.7 v cc = v ref < 4.0 v 0.5 mhz 4.0 v cc = v ref < 4.5 v 0.5 4.5 v cc = v ref 5.5 v 0.5 16.8 9v cc 0.3 ? () 1.05 3 --------------------------------------------------------- - 24.6 v cc 62.7 ? () 1.05 3 --------------------------------------------------------------------- table 28 a/d converter characteristics (v cc = 2.7 to 5.5 v, v ss = av ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. ? resolution 8-bit a/d mode (1) 8bit 10-bit a/d mode (2) 10 ? absolute accuracy (excluding quantization error) 8-bit a/d mode (1) 2.7 v ref 5.5 v 2 lsb 10-bit a/d mode (2) 2.7 v ref 5.5 v 4 lsb t conv conversion time 8-bit a/d mode (1) 50 2tc(x in ) 10-bit a/d mode (2) 61 r ladder ladder resistor 12 35 100 k i vref reference power source input current at a/d converter operated v ref = 5.0 v 50 150 200 a at a/d converter stopped v ref = 5.0 v 5.0 a i i(ad) a/d port input current 5.0 a table 29 d/a converter characteristics (v cc = 2.7 to 5.5 v, v ref = 2.7 v to v cc , v ss = av ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. ? resolution 8bit ? absolute accuracy 4.0 v ref 5.5 v 1.0 % 2.7 v ref < 4.0 v 2.5 tsu setting time 3 s ro output resistor 2 3.5 5 k i vref reference power source input current (1) 3.2 ma table 30 power source circuit timing characteristics (v cc = 2.7 to 5.5 v, v ref = 2.7 v to v cc , v ss = av ss = 0 v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter test conditions limits unit min. typ. max. td(p ? r) internal power source stable time at power-on 2.7 v cc < 5.5 v 2 ms
rev.1.00 oct 27, 2008 page 121 of 128 rej03b0266-0100 3804 group (spec.l) timing requirements and switching characteristics table 31 timing requirements (1) (v cc = 2.7 to 5.5 v, v ss = 0v, ta = ?20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. t w (reset ) reset input ?l? pulse width td(p-r)ms + 16 x in cycle t c (x in ) main clock x in input cycle time 4.5 v cc 5.5 v 59.5 ns 4.0 v cc < 4.5 v 10000/(86 v cc ? 219) 2.7 v cc < 4.0 v 26 10 3 /(82 v cc ? 3) t wh (x in ) main clock x in input ?h? pulse width 4.5 v cc 5.5 v 25 ns 4.0 v cc < 4.5 v 4000/(86 v cc ? 219) 2.7 v cc < 4.0 v 10000/(82 v cc ? 3) t wl (x in ) main clock x in input ?l? pulse width 4.5 v cc 5.5 v 25 ns 4.0 v cc < 4.5 v 4000/(86 v cc ? 219) 2.7 v cc < 4.0 v 10000/(82 v cc ? 3) t c (x cin ) sub-clock x cin input cycle time 20 s t wh (x cin ) sub-clock x cin input ?h? pulse width 5 s t wl (x cin ) sub-clock x cin input ?l? pulse width 5 s t c (cntr) cntr 0 ? cntr 2 input cycle time 4.5 v cc 5.5 v 120 ns 4.0 v cc < 4.5 v 160 2.7 v cc < 4.0 v 250 t wh (cntr) cntr 0 ? cntr 2 input ?h? pulse width 4.5 v cc 5.5 v 48 ns 4.0 v cc < 4.5 v 64 2.7 v cc < 4.0 v 115 t wl (cntr) cntr 0 ? cntr 2 input ?l? pulse width 4.5 v cc 5.5 v 48 ns 4.0 v cc < 4.5 v 64 2.7 v cc < 4.0 v 115 t wh (int) int 00 , int 01 , int 1 , int 2 , int 3 , int 40 , int 41 input ?h? pulse width 4.5 v cc 5.5 v 48 ns 4.0 v cc < 4.5 v 64 2.7 v cc < 4.0 v 115 t wl (int) int 00 , int 01 , int 1 , int 2 , int 3 , int 40 , int 41 input ?l? pulse width 4.5 v cc 5.5 v 48 ns 4.0 v cc < 4.5 v 64 2.7 v cc < 4.0 v 115
rev.1.00 oct 27, 2008 page 122 of 128 rej03b0266-0100 3804 group (spec.l) note: 1. when bit 6 of address 001a 16 and bit 6 of address 0032 16 are ?1? (clock synchronous). divide this value by four when bit 6 of address 001a 16 and bit 6 of address 0032 16 are ?0? (uart). table 32 timing requirements (2) (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter limits unit min. typ. max. t c (s clk1 ) t c (s clk3 ) serial i/o1, serial i/o3 clock input cycle time (1) 4.5 v cc 5.5 v 250 ns 4.0 v cc < 4.5 v 320 2.7 v cc < 4.0 v 500 t wh (s clk1 ) t wh (s clk3 ) serial i/o1, serial i/o3 clock input ?h ? pulse width (1) 4.5 v cc 5.5 v 120 ns 4.0 v cc < 4.5 v 150 2.7 v cc < 4.0 v 240 t wl (s clk1 ) t wl (s clk3 ) serial i/o1, serial i/o3 clock input ?l ? pulse width (1) 4.5 v cc 5.5 v 120 ns 4.0 v cc < 4.5 v 150 2.7 v cc < 4.0 v 240 t su (r x d 1 -s clk1 ) t su (r x d 3 -s clk3 ) serial i/o1, serial i/o3 clock input setup time 4.5 v cc 5.5 v 70 ns 4.0 v cc < 4.5 v 90 2.7 v cc < 4.0 v 100 t h (s clk1 -r x d 1 ) t h (s clk3 -r x d 3 ) serial i/o1, serial i/o3 clock input hold time 4.5 v cc 5.5 v 32 ns 4.0 v cc < 4.5 v 40 2.7 v cc < 4.0 v 50 t c (s clk2 )serial i/o2 clock input cycle time 4.5 v cc 5.5 v 500 ns 4.0 v cc < 4.5 v 650 2.7 v cc < 4.0 v 1000 t wh (s clk2 )serial i/o2 clock input ?h ? pulse width 4.5 v cc 5.5 v 200 ns 4.0 v cc < 4.5 v 260 2.7 v cc < 4.0 v 400 t wl (s clk2 )serial i/o2 clock input ?l ? pulse width 4.5 v cc 5.5 v 200 ns 4.0 v cc < 4.5 v 260 2.7 v cc < 4.0 v 400 t su (s in2 -s clk2 )serial i/o2 clock input setup time 4.5 v cc 5.5 v 100 ns 4.0 v cc < 4.5 v 130 2.7 v cc < 4.0 v 200 t h (s clk2 -s in2 )serial i/o2 clock input hold time 4.5 v cc 5.5 v 100 ns 4.0 v cc < 4.5 v 130 2.7 v cc < 4.0 v 150
rev.1.00 oct 27, 2008 page 123 of 128 rej03b0266-0100 3804 group (spec.l) notes: 1. when the p4 5 /t x d 1 p-channel output disable bit of the uart1 control register (bit 4 of address 001b 16 ) is ?0?. 2. when the p3 5 /t x d 3 p4-channel output disable bit of the uart 3 control register (bit 4 of address 0033 16 ) is ?0?. table 33 switching characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ? 20 to 85 c, unless otherwise noted) symbol parameter te s t conditions limits unit min. typ. max. t wh (s clk1 ) t wh (s clk3 ) serial i/o1, serial i/o3 clock output ?h? pulse width 4.5 v cc 5.5 v fig.114 t c (s clk1 )/2-30, t c (s clk3 )/2-30 ns 4.0 v cc < 4.5 v t c (s clk1 )/2-35, t c (s clk3 )/2-35 2.7 v cc < 4.0 v t c (s clk1 )/2-40, t c (s clk3 )/2-40 t wl (s clk1 ) t wl (s clk3 ) serial i/o1, serial i/o3 clock output ?l? pulse width 4.5 v cc 5.5 v t c (s clk1 )/2-30, t c (s clk3 )/2-30 ns 4.0 v cc < 4.5 v t c (s clk1 )/2-35, t c (s clk3 )/2-35 2.7 v cc < 4.0 v t c (s clk1 )/2-40, t c (s clk3 )/2-40 t d (s clk1 -t x d 1 ) t d (s clk3 -t x d 3 ) serial i/o1, serial i/o3 output delay time (1) 4.5 v cc 5.5 v 140 ns 4.0 v cc < 4.5 v 200 2.7 v cc < 4.0 v 350 t v (s clk1 -t x d 1 ) t v (s clk3 -t x d 3 ) serial i/o1, serial i/o3 output valid time (1) 4.5 v cc 5.5 v ? 30 ns 4.0 v cc < 4.5 v ? 30 2.7 v cc < 4.0 v ? 30 t r (s clk1 ) t r (s clk3 ) serial i/o1, serial i/o3 rise time of clock output 4.5 v cc 5.5 v 30 ns 4.0 v cc < 4.5 v 35 2.7 v cc < 4.0 v 40 t f (s clk1 ) t f (s clk3 ) serial i/o1, serial i/o3 fall time of clock output 4.5 v cc 5.5 v 30 ns 4.0 v cc < 4.5 v 35 2.7 v cc < 4.0 v 40 t wh (s clk2 ) serial i/o2 clock output ?h? pulse width 4.5 v cc 5.5 v t c (s clk2 )/2-160 ns 4.0 v cc < 4.5 v t c (s clk2 )/2-200 2.7 v cc < 4.0 v t c (s clk2 )/2-240 t wl (s clk2 ) serial i/o2 clock output ?l? pulse width 4.5 v cc 5.5 v t c (s clk2 )/2-160 ns 4.0 v cc < 4.5 v t c (s clk2 )/2-200 2.7 v cc < 4.0 v t c (s clk2 )/2-240 t d (s clk2 -s out2 ) serial i/o2 output delay time 4.5 v cc 5.5 v 200 ns 4.0 v cc < 4.5 v 250 2.7 v cc < 4.0 v 300 t v (s clk2 -s out2 ) serial i/o2 output valid time 4.5 v cc 5.5 v 0 ns 4.0 v cc < 4.5 v 0 2.7 v cc < 4.0 v 0 t f (s clk2 ) serial i/o2 fall time of clock output 4.5 v cc 5.5 v 30 ns 4.0 v cc < 4.5 v 35 2.7 v cc < 4.0 v 40 t r (cmos) cmos rise time of output (2) 4.5 v cc 5.5 v 10 30 ns 4.0 v cc < 4.5 v 12 35 2.7 v cc < 4.0 v 15 40 t f (cmos) cmos fall time of output (2) 4.5 v cc 5.5 v 10 30 ns 4.0 v cc < 4.5 v 12 35 2.7 v cc < 4.0 v 15 40
rev.1.00 oct 27, 2008 page 124 of 128 rej03b0266-0100 3804 group (spec.l) fig. 114 circuit for measuring output switching characteristics (1) fig. 115 circuit for measuring output switching characteristics (2) measurement output pin 100 pf cmos output measurement output pin 100 pf n-channel open-drain output 1k
rev.1.00 oct 27, 2008 page 125 of 128 rej03b0266-0100 3804 group (spec.l) fig. 116 timing diagram (in single-chip mode) t c (cntr) t wl (cntr) t wh (cntr) 0.8v cc 0.2v cc cntr 0 , cntr 1 cntr 2 int 1 , int 2 , int 3 int 00 , int 40 int 01 , int 41 reset x in t wl (int) t wh (int) 0.8v cc 0.2v cc 0.8v cc 0.2v cc t w (reset) t c (x in ) t wl (x in ) t wh (x in ) 0.8v cc 0.2v cc t c (s clk1 ), t c (s clk2 ), t c (s clk3 ) t wl (s clk1 ), t wl (s clk2 ), t wl (s clk3 ) 0.8v cc 0.2v cc t wh (s clk1 ), t wh (s clk2 ), t wh (s clk3 ) t f t r t su (r x d 1 -s clk1 ), t su (s in2 -s clk2 ), t su (r x d 3 -s clk3 ) t h (s clk1 -r x d 1 ), t h (s clk2 -s in2 ), t h (s clk3 -r x d 3 ) t d (s clk1 -t x d 1 ), t d (s clk2 -s out2 ), t d (s clk3 -t x d 3 ) t v (s clk1 -t x d 1 ), t v (s clk2 -s out2 ), t v (s clk3 -t x d 3 ) 0.2v cc 0.8v cc s clk1 s clk2 s clk3 r x d 1 r x d 3 s in2 t x d 1 t x d 3 s out2 x cin t c (x cin ) t wl (x cin ) t wh (x cin ) 0.8v cc 0.2v cc single-chip mode timing diagram
rev.1.00 oct 27, 2008 page 126 of 128 rej03b0266-0100 3804 group (spec.l) note: 1. cb = total capacitance of 1 bus line fig. 117 timing diagram of multi-master i 2 c-bus table 34 multi-master i 2 c-bus bus line characteristics symbol parameter standard clock mode high-speed clock mode unit min. max. min. max. t buf bus free time 4.7 1.3 s t hd;sta hold time for start condition 4.0 0.6 s t low hold time for scl clock = ?0? 4.7 1.3 s t r rising time of both scl and sda signals 1000 20+0.1cb (1) 300 ns t hd;dat data hold time 0 0 0.9 s t high hold time for scl clock = ?1? 4.0 0.6 s t f falling time of both scl and sda signals 300 20+0.1cb (1) 300 ns t su;dat data setup time 250 100 ns t su;sta setup time for repeated start condition 4.7 0.6 s t su;sto setup time for stop condition 4.0 0.6 s t buf t hd:sta t hd:dta t low t r t f t high tsu :dat tsu :sta t hd:sta tsu :sto scl p s sr p sda s : start condition sr: restart condition p : stop condition
rev.1.00 oct 27, 2008 page 127 of 128 rej03b0266-0100 3804 group (spec.l) package outline diagrams showing the latest package dimensions and mounti ng information are available in the ?packages? section of the renesas technology website. 0 3.8 a 2 1.05 0.75 0.65 b 2 19.35 18.75 19.05 0.6 0.5 0.4 b p previous code jeita package code renesas code prdp0064ba-a 64p4b mass[typ.] 7.9g p-sdip64-17x56.4-1.78 0.32 0.25 0.2 max nom min dimension in millimeters symbol reference 56.6 56.4 56.2 d 17.15 17.0 16.85 e a 1.3 1.0 0.9 0.38 2.8 l c 1.778 e 15 b 3 a 1 5.08 1.528 2.028 include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. 33 64 32 1 seating plane * 1 * 2 * 3 * 3 e c a 1 a 2 d l a b 2 e b 3 b p e 1 e 1 terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark * 3 17 32 64 49 116 33 48 f * 1 * 2 x y b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e
rev.1.00 oct 27, 2008 page 128 of 128 rej03b0266-0100 3804 group (spec.l) terminal cross section b1 c1 bp c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. * 3 116 17 32 33 48 49 64 f * 1 * 2 x y index mark d h d e h e e b p z d z e detail f c a a 2 a 1 l l 1 previous code jeita package code renesas code plqp0064ga-a 64p6u-a mass[typ.] 0.7g p-lqfp64-14x14-0.80 1.0 0.125 0.35 1.0 1.0 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 14.1 14.0 13.9 d 14.1 14.0 13.9 e 1.4 a 2 16.2 16.0 15.8 16.2 16.0 15.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 0.15 v 0.20 w previous code jeita package code renesas code ptlg0064ja-a 64f0g mass[typ.] 0.07g p-tflga64-6x6-0.65 0.08 0.47 0.43 0.39 max nom min dimension in millimeters symbol reference 6.0 d 6.0 e 1.05 a x 0.65 e 0.10 y b 1 b 0.31 0.35 0.39 b w s w a s a h g f e d c b 12345678 s ys ab index mark sab v x4 (laser mark) index mark d e a b 1 b e e
(1/1) revision history 3804 group (spec.l) data sheet rev. date description page summary 1.00 oct. 27, 2008 - first edition issued all trademarks and registered trademarks are the property of their respective owners. revision history

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