k4s511533c-yl/n/p rev. 1.2 dec. 2002 cmos sdram revision 1.2 december 2002 32mx16 54csp 2/cs (vdd/vddq 3.0v/3.0v or 3.3v/3.3v) mobile sdram
k4s511533c-yl/n/p rev. 1.2 dec. 2002 cmos sdram the k4s511533c is 536,870,912 bits synchronous high data rate dynamic ram organized as 4 x 8,388,608 words by 16bits, fabricated with samsung's high performance cmos technology. synchronous design allows precise cycle control with the use of system clock i/o transactions are possible on every clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ? 3.0v power supply ? lvcmos compatible with multiplexed address ? four banks operation ? mrs cycle with address key programs -. cas latency (1 & 2 & 3) -. burst length (1, 2, 4, 8 & full page) -. burst type (sequential & interleave) ? all inputs are sampled at t he positive going edge of the system clock. ? burst read single- bit write operation. ? dqm for masking ? auto & self refresh ? 64ms refresh period (8k cycle) ? 2 /cs support. ? commercial temper ature operation (-25 c ~ 70 c). extended temperature operation (-25 c ~ 85 c). industrial temperature operation (-40 c ~ 85 c). ? 54balls ddp csp general description features functional block diagram 8m x 16bit x 4 ba nks mobile sdram samsung electronics reserves the right to c hange products or specification without notice. * ordering information - yn : low power, operating temp : -25 c ~ 85 c. - yl : low power, operating temp : -25 c ~ 70 c. - yp : low power, operating temp : -40 c ~ 85 c. note : 1. in case of 33mhz frequency, cl1 can be supported. part no. max freq. interface package k4s511533c-yl/n/p80 125mhz(cl=3) 100mhz(cl=2) lvcmos 54 csp k4s511533c-yl/n/p1h 100mhz(cl=2) k4s511533c-yl/n/p1l 100mhz(cl=3) *1 16mx16 16mx16 dq0~dq15 a0~a12, ba0, ba1 clk, /cas, /ras, /we, dqm, cke /cs1 /cs0
k4s511533c-yl/n/p rev. 1.2 dec. 2002 cmos sdram 54ball(6x9) csp 123789 av ss dq15 v ssq v ddq dq0 v dd bdq14dq13v ddq v ssq dq2 dq1 c dq12 dq11 v ssq v ddq dq4 dq3 d dq10 dq9 v ddq v ssq dq6 dq5 edq8 cs1 v ss v dd ldqm dq7 f udqm clk cke cas ras we g a12 a11 a9 ba0 ba1 cs0 h a8a7a6a0a1a10 jv ss a5 a4 a3 a2 v dd pin name pin function clk system clock cs 0 ~ 1 chip select cke clock enable a 0 ~ a 12 address ba 0 ~ ba 1 bank select address ras row address strobe cas column address strobe we write enable l(u)dqm data input/output mask dq 0 ~ 15 data input/output v dd /v ss power supply/ground v ddq /v ssq data output power/ground package dimension and pin configuration symbol min typ max a 1.001.101.30 a 1 0.27 0.32 0.37 e-9.50- e 1 -6.40- d - 15.50 - d 1 -6.40- e-0.80- b 0.400.450.50 z--0.10 [unit:mm] 521 63 4 8 97 f e d c b j h g a e d d/2 d 1 e 1 e e/2 a a1 z b encapsulant max. 0.20 k4s511533c-xxxx #a1 ball origin indicator < bottom view *1 > < top view *2 > < top view *2 > *1: bottom view *2: top view samsung week
k4s511533c-yl/n/p rev. 1.2 dec. 2002 cmos sdram dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a =commercial, extended and industrial) notes : 1. v ih (max) = 5.3v ac. the overshoot voltage duration is 3ns. 2. v il (min) = -2.0v ac. the under shoot voltage duration is 3ns. 3. any input 0v v in v ddq . input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v v out v ddq. parameter symbol min typ max unit note supply voltage v dd 2.7 3.0 3.6 v v ddq 2.7 3.0 3.6 v input logic high voltage v ih 2.2 3.0 v ddq +0.3 v 1 input logic low voltage v il -0.3 0 0.5 v 2 output logic high voltage v oh 2.4 - - v i oh = -2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i li -10 - 10 ua 3 absolute maximum ratings notes : permanent device damage may occur if absolute maximum ra tings are exceeded. functional operation should be restri cted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 4.6 v voltage on v dd supply relative to vss v dd , v ddq -1.0 ~ 4.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1w short circuit current i os 50 ma capacitance (v dd = 3.0v or 3.3v, t a = 23 c, f = 1mhz, v ref =0.9v 50 mv) pin symbol min max unit note clock c clk 3.0 9.0 pf ras , cas , we , cke, dqm c in 3.0 9.0 pf cs c in 1.5 4.5 pf address c add 3.0 9.0 pf dq 0 ~ dq 15 c out 6.0 13.0 pf
k4s511533c-yl/n/p rev. 1.2 dec. 2002 cmos sdram dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a = commercial, extended and industrial) notes : 1. measured with outputs open 2. measured with operating(icc1) condition for 1chip and prec harge stanby condition in non power down mode for 1chip(icc2n). (icc1 * = icc1 +icc2n) 3. measured with operating(icc4) condition for 1chip and acti ve stanby condition in non power down mode for 1chip(icc3n). (icc4 * = icc4 +icc3n) 4. measured with active stanby condition in power down mode for 1chip (icc3p/ps) and precharge stanby condition in power down mode for 1chip (icc2p/ps). (icc3p/ps * = icc3p/ps +icc2p/ps) 5. measured with active stanby condition in non power dow n mode for 1chip (icc3n/ns) and precharge stanby condition in non power down mode for 1chip (icc2n/ns). (icc3n/ns * = icc3n/ns +icc2n/ns) 6. refresh period is 64ms. measured with refresh condition for 1chip (icc5) and pr echarge stanby condition in non pow er down mode for 1chip (icc2n). (icc5 * = icc5 +icc2n) 7. k4s511533c-yl** 8. k4s511533c-yn** 9. k4s511533c-yp** 10. unless otherwise noted, input swing ievei is cmos(v ih /v il =v ddq /v ssq) parameter symbol test condition version unit note -80 -1h -1l operating current (one bank active) i cc1 * burst length = 1 t rc t rc (min) i o = 0 ma 100 90 85 ma 1.2 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = 10ns 2 ma i cc2 ps cke & clk v il (max), t cc = 2 precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 35 ma i cc2 ns cke v ih (min), clk v il (max), t cc = input signals are stable 25 active standby current in power-down mode i cc3 p * cke v il (max), t cc = 10ns 8 ma 4 i cc3 ps * cke & clk v il (max), t cc = 8 active standby current in non power-down mode (one bank active) i cc3 n * cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 45 ma 5 i cc3 ns * cke v ih (min), clk v il (max), t cc = input signals are stable 35 ma operating current (burst mode) i cc4 * i o = 0 ma page burst 4banks activated t ccd = 2clks 145 125 115 ma 1.3 refresh current i cc5 * t rc t rc (min) 190 170 160 ma 6 self refresh current i cc6 cke 0.2v -yl 1800 ua 7 -yn 8 -yp 9
k4s511533c-yl/n/p rev. 1.2 dec. 2002 cmos sdram operating ac parameter (ac operating conditions unless otherwise noted) notes : 1. the minimum number of clock cycles is determined by di viding the minimum time require d with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. minimum trdl=2clk and tdal(=trdl + tr p) is required to complete both of la st data wite command (trdl) and precharge command(trp). trdl=1clk can be supported only in the case under 100mhz wi th manual precharge mode. 4. all parts allow every cycle column address change. 5. in case of row precharge inte rrupt, auto precharge and read burst stop. parameter symbol version unit note - 80 -1h -1l row active to row active delay t rrd (min) 16 20 20 ns 1 ras to cas delay t rcd (min) 20 20 24 ns 1 row precharge time t rp (min) 20 20 24 ns 1 row active time t ras (min) 48 50 60 ns 1 t ras (max) 100 us row cycle time t rc (min) 68 70 84 ns 1 last data in to row precharge t rdl (min) 2 clk 2,3 last data in to active delay t dal (min) trdl + trp - 3 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 4 number of valid output data cas latency=3 2 ea 5 cas latency=2 1 cas latency=1 - 0 vddq 1200 ? 870 ? output 30pf v oh (dc) = 2.4v, i oh = -2ma v ol (dc) = 0.4v, i ol = 2ma vtt = 0.5 x vddq 50 ? output 30pf z0 = 50 ? (fig. 2) ac output load circuit (fig. 1) dc output load circuit ac operating test conditions (v dd = 2.7v ~ 3.6v, t a = commercial, extended and industrial) parameter value unit ac input levels (vih/vil) 2.4 / 0.4 v input timing measurem ent reference level 0.5 x v ddq v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 0.5 x v ddq v output load condition see fig. 2
k4s511533c-yl/n/p rev. 1.2 dec. 2002 cmos sdram ac characteristics (ac operating conditions unless otherwise noted) notes : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns , (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, trans ient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. parameter symbol -80 -1h -1l unit note min max min max min max clk cycle time cas latency=3 t cc 8 1000 10 1000 10 1000 ns 1 cas latency=2 10 10 12 cas latency=1 - - 25 clk to valid output delay cas latency=3 t sac 6 7 7 ns 1,2 cas latency=2 7 7 8 cas latency=1 - - 20 output data hold time cas latency=3 t oh 2.5 2.5 2.5 ns 2 cas latency=2 2.5 2.5 2.5 cas latency=1 - - 2.5 clk high pulse width t ch 2.5 3 3 ns 3 clk low pulse width t cl 2.5 3 3 ns 3 input setup time t ss 2.0 2.5 2.5 ns 3 input hold time t sh 1.0 1.5 1.5 ns 3 clk to output in low-z t slz 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 6 7 7 ns cas latency=2 7 7 8 cas latency=1 - - 20 notes : 1. this is to advise samsung customers that, in accordance wi th certain terms of an agreement, samsung is prohibited from selling any dram products configured in "multi-die plastic" format for use as components in general and scientific comput ers, such as mainframes, servers, work stations or desk top personal computers (hereinafter "prohibited computer use"). applications such as mobile, including cell phones, te lecom, including televisions and display monitors, or non-desktop computer systems, including laptops, notebook computers, are, however , permissible. "multi-die plastic" is defined as two or more dram die encapsulated within a single plastic leaded package. 2. samsung are not designed or manufactured for use in a device or system that is used under circ umstance in which human life is potentially at stake. please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear , military, vehicular or undersea repeater use.
k4s511533c-yl/n/p rev. 1.2 dec. 2002 cmos sdram simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) notes : 1. op code : operand code a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are the same as cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be i ssued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row acti ve and precharge, bank a is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row ac tive and precharge, bank b is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row acti ve and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, writ e, row active and precharge, bank d is selected. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at the positive going edge of clk masks the data-in at that same clk in write operation (write dqm latency is 0), but in read operation it makes the data- out hi-z state after 2 clk cycles. (read dqm latency is 2). command cken-1 cken cs ras cas we dqm ba 0,1 a 10 /ap a 11, a 12, a 9 ~ a 0 note register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a 0 ~a 8 ) 4 auto precharge enable h 4, 5 write & column address auto precharge disable h x l h l l x v l column address (a 0 ~a 8 ) 4 auto precharge enable h 4, 5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h x v x 7 no operation command h x h x x x x x l h h h
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