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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of th e date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology de scribed in this document for any purpose re lating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or om issions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ship s, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use re nesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of c ontrolled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any fo rm, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. 1. description the m37221m4h/m6h/m8h/mah-xxxsp/fp are single-chip micro- computers designed with cmos silicon gate technology. they have a osd, i 2 c-bus interface, and pwm, making them perfect for tv channel selection system. the m37221easp/fp have a built-in prom that can be written elec- trically. 2. features number of basic instructions ..................................................... 71 memory size rom ............. 16k bytes (M37221M4H-XXXSP/fp) 24k bytes (m37221m6h-xxxsp/fp) 32k bytes (m37221m8h-xxxsp/fp) 40k bytes ( m37221mah-xxxsp/fp, m37221easp/fp ) ram ............. 384 bytes (M37221M4H-XXXSP/fp) 448 bytes (m37221m6h-xxxsp/fp) 576 bytes (m37221m8h-xxxsp/fp) 704 bytes ( m37221mah-xxxsp/fp, m37221easp/fp ) (rom correction memory included) the minimum instruction execution time ......................................... 0.5 s (at 8 mhz oscillation frequency) power source voltage .................................................. 5 v ?10 % subroutine nesting maximum 96 levels ( m37221m4h/m6h-xxxsp/fp) maximum 128 levels ( m37221m8h/mah-xxxsp/fp, m37221easp/fp) interrupts ........................................................ 14 types, 14 vectors 8-bit timers ................................................................................... 4 programmable i/o ports (ports p0, p1, p2, p3 0 ?3 2 ) ..................................................... 27 input ports (ports p3 3 , p3 4 ) ......................................................... 2 output ports (ports p5 2 ?5 5 ) ...................................................... 4 led drive ports ............................................................................ 4 serial i/o ............................................................. 8-bit ? 1 channel multi-master i 2 c-bus interface ............................... 1 (2 systems) a-d comparator (6-bit resolution) ................................. 6 channels d-a converter (6-bit resolution) .................................................... 2 note: only m37221easp/fp has d-a converter. pwm output circuit .......................................... 14-bit ? 1, 8-bit ? 6 power dissipation .............................. high-speed mode : 165 mw (at v cc =5.5v, 8 mhz oscillation frequency, and osd on) rom correction function ................................................. 2 vectors osd function display characters .................................... 24 characters 5 2 lines (3 lines or more can be displayed by software) kinds of characters ........................................................ 256 kinds character display area .............................................. 12 ? 16 dots kinds of character sizes ..................................................... 3 kinds kinds of character colors .................................. 8 colors (r, g, b) coloring unit ................... character, character background, raster display position ............................................................................. horizontal: 64 levels vertical: 128 levels attribute .............................................................................. border 3. application tv single-chip 8-bit cmos microcomputer for voltage synthesizer with on-screen display controller rej03b0134-0100z rev.1.00 oct 01, 2002 rev.1.00 oct 01, 2002 page 1 of 110 rej03b0134-0100z m37221m4h/m6h/m8h/mah?xxsp/fp m37221easp/fp m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 2 of 110 rej03b0134-0100z t able of contents 1. description ............................................................... 1 2. features .................................................................... 1 3. application ................................................................ 1 4. pin configuration .................................................. 3 5. functional block diagram ................................. 5 6. performance overview ....................................... 6 7. pin description ........................................................ 8 8. functional description ..................................... 12 8.1 central processing unit (cpu) ......... 12 8.2 memory ....................................................... 13 8.3 interrupts ................................................ 19 8.4 timers .......................................................... 24 8.5 serial i/o ..................................................... 27 8.6 multi-master i 2 c-bus interface ........ 31 8.7 pwm output function ........................... 44 8.8 a-d comparator ....................................... 49 8.9 d-a converter .......................................... 51 8.10 rom correction function ................ 53 8.11 osd functions ........................................ 54 8.11.1 display position .............................. 58 8.11.2 character size ................................ 62 8.11.3 clock for osd ................................. 64 8.11.4 memory for osd ............................. 65 8.11.5 color register ................................. 68 8.11.6 border ............................................. 70 8.11.7 multiline display .............................. 71 8.11.8 osd output pin control ................. 72 8.11.9 raster coloring function ................ 73 8.12 software runaway detect function ... 74 8.13 reset circuit .......................................... 75 8.14 clock generating circuit ................. 76 8.15 display oscillation circuit .............. 77 8.16 auto-clear circuit ............................... 77 8.17 addressing mode .................................. 77 8.18 machine instructions ......................... 77 9. programming notes ............................................ 77 10. absolute maximum ratings ............................. 78 1 1. recommended operating conditions ......... 78 12. electric characteristics .............................. 79 13. a-d comparison characteristics ................. 81 14. d-a conversion characteristics ................. 81 15. multi-master i 2 c-bus bus line characteristics .... 81 16. prom programming method ........................... 82 17. data required for mask orders .................. 83 18. one time prom version m37221easp/fp marking ..... 84 19. appendix ................................................................. 85 20. package outline ................................................ 110 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 3 of 110 rej03b0134-0100z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 p0 6 /int2/a-d4 x out h sync v sync p0 0 /pwm0 p0 1 /pwm1 p0 2 /pwm2 p0 3 /pwm3 p0 4 /pwm4 p0 5 /pwm5 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 p2 6 p2 7 d-a p3 2 cnv ss x in v ss p5 2 /r p5 3 /g p5 4 /b p5 5 /out1 p2 0 /s clk p2 1 /s out p2 2 /s in p1 0 /out2 p1 1 /scl1 p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 5 /a-d1/int3 p1 6 /a-d2 p3 0 /a-d5 p3 1 /a-d6 reset osc1/p3 3 osc2/p3 4 v cc p1 7 /a-d3 m37221m4h/m6h/m8h/mah-xxxsp 4. pin configuration outline 42p4b fig. 4.1 pin configuration (1) (top view) outline 42p2r-a/e fig. 4.2 pin configuration (2) (top view) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 14 15 16 17 18 19 20 21 x out p0 0 /pwm0 p 0 1 / p w m 1 p 0 2 / p w m 2 p 0 3 / p w m 3 p 0 4 / p w m 4 cnv ss x in v s s 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 25 24 22 p5 2 /r p5 3 /g p5 4 /b p 5 5 / o u t 1 p 2 0 / s c l k p 2 1 / s o u t p 2 2 / s i n p 1 0 / o u t 2 p1 1 /scl1 p2 6 p2 7 d-a p3 2 osc1/p3 3 osc2/p3 4 p5 0 /h syn c p5 1 /v syn c p0 5 /pwm5 p0 6 /int2/a-d4 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 p1 6 /a-d2 p1 7 /a-d3 p3 0 /a-d5 p3 1 /a-d6 reset v c c 23 p1 5 /a-d1/int3 p1 4 /sda2 p1 3 /sda1 p1 2 /scl2 m37221m4h/m6h/m8h/mah-xxxfp m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 4 of 110 rej03b0134-0100z outline 42p4b fig. 4.3 pin configuration (3) (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 p0 6 /int2/a-d4 x out h sync v sync p0 0 /pwm0 p0 1 /pwm1 p0 2 /pwm2 p0 3 /pwm3 p0 4 /pwm4 p0 5 /pwm5 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 p2 6 p2 7 d-a p3 2 cnv ss x in v ss p5 2 /r p5 3 /g p5 4 /b p5 5 /out1 p2 0 /s clk p2 1 /s out p2 2 /s in p1 0 /out2 p1 1 /scl1 p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 5 /a-d1/int3 p1 6 /a-d2 p3 0 /a-d5/da1 p3 1 /a-d6/da2 reset osc1/p3 3 osc2/p3 4 v cc p1 7 /a-d3 m37221easp outline 42p2r-a/e fig. 4.4 pin configuration (4) (top view) 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 17 18 19 2 0 2 1 x o u t p 5 0 / h s y n c p5 1 /v syn c p0 0 /pwm0 p 0 1 / p w m 1 p 0 2 / p w m 2 p 0 3 / p w m 3 p 0 4 / p w m 4 p 0 5 / p w m 5 p0 7 /int1 p 2 3 / t i m 3 p 2 4 / t i m 2 p 2 5 cnv ss x i n v s s 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 25 24 2 3 22 p 5 2 / r p5 3 /g p5 4 /b p 5 5 / o u t 1 p 2 0 / s c l k p 2 1 / s o u t p 2 2 / s i n p 1 0 / o u t 2 p 1 1 / s c l 1 p 1 2 / s c l 2 p 1 3 / s d a 1 p 1 4 / s d a 2 reset v cc m 3 7 2 2 1 e a f p p2 6 p2 7 d-a p3 2 osc1/p3 3 osc2/p3 4 p0 6 /int2/a-d4 p1 5 /a-d1/int3 p1 6 /a-d2 p1 7 /a-d3 p3 0 /a-d5/da1 p3 1 /a-d6/da2 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 5 of 110 rej03b0134-0100z 5. functional block diagram fig. 5.1 functional block diagram of m37221 out1 clock input clock output x in x out reset input v cc v ss cnv ss clock output for display input ports p3 3, p3 4 osc1 osc2 clock input for display int 2 int1 pwm5 pwm4 pwm3 p wm2 pwm1 pwm0 p5 (4) b g r h s ync v s ync a-d comparator 14-bit pwm circuit 8-bit pwm circuit accumulator a (8) timer 4 t4 (8) timer 3 t3 (8) timer 2 t2 (8) timer 1 t1 (8) timer count source selection circuit tim2 tim3 instruction register (8) instruction decoder control signal osd circuit stack pointer s (8) index register y (8) index register x (8) processor status register ps (8) 8-bit arithmetic and logical unit program counter pc l (8) program counter pc h (8) ram rom data bus clock generating circuit reset address bus si/o(8) s in s cl k s out in t3 10 9 8 7 654 3 i/o port p0 28 29 3031 32 3334 35 p1 (8 ) i/o port p1 15 14 13 12 11 3637 38 p2 (8 ) i/o port p2 i/o ports p3 0 ep3 2 17 2627 16 p3 (3 ) p0 (8 ) 39 40 41 42 2 1 20 19 25 22 21 18 24 23 ( m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 6 of 110 rej03b0134-0100z parameter functions number of basic instructions 71 number of basic instructions 0.5 s (the minimum instruction execution time, at 8 mhz oscillation fre quency) instruction execution time 8 mhz (maximum) memory size rom M37221M4H-XXXSP/fp 16k bytes m37221m6h-xxxsp/fp 24k bytes m37221m8h-xxxsp/fp 32k bytes m37221mah-xxxsp/fp, 40k bytes m37221easp/fp ram M37221M4H-XXXSP/fp 384 bytes (rom correction memory included) m37221m6h-xxxsp/fp 448 bytes (rom correction memory included) m37221m8h-xxxsp/fp 576 bytes (rom correction memory included) m37221mah-xxxsp/fp, 704 bytes (rom correction memory included) m37221easp/fp osd rom 8 k bytes osd ram 96 bytes tinput/output ports p0 i/o 8-bit 5 1 (n-channel open-drain output structure, can be used as pwm output pins, int input pins, a-d input pin) p1 0 , p1 5 ep1 7 i/o 4-bit 1 (cmos input/output structure, can be used as osd output pin, a-d input pins, int input pin) p1 1 ep1 4 i/o 4-bit 1 (cmos input/output structure, can be used as multi-master i 2 c- bus interface) p2 0 , p2 1 i/o 2-bit 1 (cmos input/output or n-channel open-drain output structure, can be used as serial i/o pins) p2 2 ep2 7 i/o 6-bit 1 (cmos input/output structure, can be used as serial input pin, timer external clock input pins) p3 0 , p3 1 i/o 2-bit 1 (cmos input/output or n-channel open-drain output structure, can be used as a-d input pins, d-a conversion output pins m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 7 of 110 rej03b0134-0100z parameter functions osd display number of display characters 24 characters 2 lines function dot structure 12 16 dots kinds of characters 256 kinds kinds of character sizes 3 kinds character font coloring 1 screen: 8 kinds (per character unit) display position horizontal: 64 levels, vertical: 128 levels power source voltage 5 v 10 % power dissipation osd on 165 mw typ. (at oscillation frequency f(x in ) = 8 mhz, f osc = 8 mhz) osd off 110 mw typ. (at oscillation frequency f(x in ) = 8 mhz) in stop mode 1.65 mw (maximum) operating temperature range e10 ?c to 70 ?c device structure cmos silicon gate process package m37221m4h/m6h/m8h/mah-xxxsp, 42-pin plastic molded sdip m37221easp m37221m4h/m6h/m8h/mah-xxxfp, 42-pin plastic molded ssop m37221eafp t able 6.2 performance overview (continued) m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 8 of 110 rej03b0134-0100z 7. pin description t able 7.1 pin description power source cnv ss reset input clock input clock output i/o port p0 pwm output external interrupt input analog input i/o port p1 osd output multi-master i 2 c-bus interface analog input external interrupt input i/o port p2 timer external clock input serial i/o synchro- nizing clock input/ output serial i/o data input/output i/o port p3 analog input d-a conversion output input port p3 clock input for osd clock output for osd v cc , v ss. cnv ss reset x in x out p0 0 /pwm0e p0 5 /pwm5, p0 6 /int2/ a-d4 , p0 7 /int1 p1 0 /out2, p1 1 /scl1, p1 2 /scl2, p1 3 /sda1, p1 4 /sda2, p1 5 /a-d1/ int3, p1 6 /a-d2, p1 7 /a-d3 p2 0 /s clk , p2 1 /s out , p2 2 /s in , p2 3 /tim3, p2 4 /tim2, p2 5 ep2 7 p3 0 /a-d5/ da1, p3 1 /a-d6/ da2, p3 2 p3 3 /osc1, p3 4 /osc2 input input output i/o output input input i/o output i/o input input i/o input i/o i/o i/o input output input input output apply voltage of 5 v 10 % (typical) to v cc , and 0 v to v ss . this is connected to v ss . to enter the reset state, the reset input pin must be kept at a l for 2 s or more (under normal v cc conditions). if more time is needed for the quartz-crystal oscillator to stabilize, this ??condition should be maintained for the required time. this is the input pin for the main clock generating circuit. to control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins x in and x out . if an external clock is used, the clock source should be connected to the x in pin and the x out pin should be left open. port p0 is an 8-bit i/o port with a direction register allowing each i/o bit to be individually programmed as input or output. at reset, this port is set to input mode. the output structure is n-channel open-drain output (see note 1.) output pins p0 0 to p0 5 are also used as pwm output pins pwm0 to pwm4, respectively. the output structure is n-channel open-drain output. pins p0 6 , p0 7 are also used as external interrupt input pins int2 and int1 respectively. p0 6 pin is also used as analog input pin a-d4. i/o port p1 is a 8-bit i/o port and has basically the same functions as port p0. the output structure is cmos output (see note 1.) pins p1 0 is also used as osd output pin out2. the output structure is cmos output. pins p1 1 ?1 4 are used as scl1, scl2, sda1 and sda2 respectively, when multi-master i 2 c-bus interface is used. the output structure is n-channel open-drain output. pins p1 5 ?1 7 are also used as analog input pins a-d1 to a-d3 respectively. p1 5 pin is also used as external interrupt input pin int3. port p2 is an 8-bit i/o port and has basically the same functions as port p0. the output structure is cmos output. the output structure is cmos output (see note 1.) pins p2 3 , p2 4 are also used as timer external clock input pins tim3, tim2 respectively. p2 0 pin is also used as serial i/o synchronizing clock input/output pin s clk . the output structure is n-channel open-drain output. pins p2 1 , p2 2 are also used as serial i/o data input/output pins s out , s in respectively. the output structure is n-channel open-drain output. ports p3 0 ?3 2 are a 3-bit i/o port and has basically the same functions as port p0. either cmos output or n-channel open-drain output structure can be selected as the port p3 0 and p3 1 . the output structure of port p3 2 is n-channel open-drain output. (see notes 1, 2) pins p3 0 , p3 1 are also used as analog input pins a-d5, a-d6 respectively. pins p3 0 , p3 1 are also used as d-a conversion output pins da1, da2 respectively. (see note 3) ports p3 3 , p3 4 are a 2-bit input port. p3 3 pin is also used as osd clock input pin osc1. p3 4 pin is also used as osd clock output pin osc2. the output structure is cmos output. pin name name input/ output m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 9 of 110 rej03b0134-0100z t able 7.2 pin description (continued) output port p5 osd output h sync input v sync input da output p5 2 /r, p5 3 /g, p5 4 /b, p5 5 /out1 h sync v sync d-a ports p5 2 ep5 5 are a 4-bit output port. the output structure is cmos output. pins p5 2 ep5 5 are also used as osd output pins r, g, b, out1 respectively. the output structure is cmos output. this is a horizontal synchronizing signal input for osd. this is a vertical synchronizing signal input for osd. this is a 14-bit pwm output pin. output output input input output note 1 : port pi (i = 0 to 3) has a port pi direction register that can be used to program each bit for input (0) or an output (1). the pins programmed as 1 in the direction register are output pins. when pins are programmed as 0, they are input pins. when pins ar e programmed as output pins, the output data is written into the port latch and then output. when data is read from the output pi ns, the data of the port latch, not the output pin level, is read. this allows a previously output value to be read correctly even if t he output low voltage has risen due to, for example, a directly-driven light emitting diode. the input pins are in the floating state, so the values of the pins can be read. when data is written to the input pin, it is written only into the port latch, while the pin remains in the f loating state. 2 : to swich output structures, set by the following bits. p3 0 : bit 0 of port p3 output mode control register p3 1 : bit 1 of port p3 output mode control register when 0, cmos output; when 1, n-channel open-drain output. 3: only m37221easp/fp have a built-in d-a converter. m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 10 of 110 rej03b0134-0100z fig. 7.1 i/o pin block diagram (1) n-channel open-drain output ports p0 6 , p0 7 note: each port is also used as follow: p0 6 : int2/a-d4 p0 7 : int1 n-channel open drain output ports p0 0 ep0 5 , p3 2 note: each port is also used as follows: p0 0 ep0 5 : pwm0epwm5 cmos output ports p1, p2, p3 0 , p3 1 notes 1: each port is also used as follows: p1 0 : out2 p2 0 : s clk p1 1 : scl1 p2 1 : s out p1 2 : scl2 p2 2 : s in p1 3 : sda1 p2 3 : tim3 p1 4 : sda2 p2 4 : tim2 p1 5 : a-d1/int3 p3 0 : a-d5/da1 p1 6 : a-d2 p3 1 : a-d6/da2 p1 7 : a-d3 2: the output structure of ports p1 1 ep1 4 is n-channel open-drain output when using as multi-master i 2 c-bus inter face (it is the same with ports p0 6 and p0 7 ) 3: the output structure of ports p3 0 and p3 1 can be selected either cmos output or n-channel open-drain output (it is the same with ports p0 6 and p0 7 ) data bus direction register port latch data bus direction register port latch data bus direction register port latch ports p0 0 ?0 5 , p3 2 ports p1, p2, p3 0 , p 3 1 ports p0 6 , p0 7 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 11 of 110 rej03b0134-0100z cmos output d-a, r, g, b, out1, out2 note: each pin is also used as below: r : p5 2 g : p5 3 b : p5 4 out1 : p5 5 out2 : p1 0 fig. 7.2 i/o pin block diagram (2) schmidt input h sync , v sync internal circuit d-a, r, g, b, out1, out2 h sync , v sync internal circuit m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 12 of 110 rej03b0134-0100z 8. function block description 8.1 central processing unit (cpu) this microcomputer uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine instructions or the series 740 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 13 of 110 rej03b0134-0100z 8.2 memory 8.2.1 special function register (sfr) area the special function register (sfr) area in the zero page includes control registers such as i/o ports and timers. 8.2.2 ram ram is used for data storage and for stack area of subroutine calls and interrupts. 8.2.3 rom rom is used for storing user programs as well as the interrupt vector area. 8.2.4 osd ram ram used for specifying the character codes and colors for display. 8.2.5 osd rom rom used for storing character data for display. 8.2.6 interrupt vector area the interrupt vector area contains reset and interrupt vectors. 8.2.7 zero page the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area is pos- sible with only 2 bytes in the zero page addressing mode. 8.2.8 special page the special page addressing mode can be used to specify memory addresses in the special page area. access to this area is possible with only 2 bytes in the special page addressing mode. 8.2.9 rom correction memory (ram) this is used as the program area for rom correction. fig. 8.2.1 memory map (m37221m4h/m6h-xxxsp/fp) 0 0 0 0 1 6 00c0 16 00ff 16 0 1 b f 1 6 06b7 16 a 0 0 0 1 6 sfr area not used not used n o t u s e d f f f f 1 6 f f d e 1 6 ff00 16 0600 16 i n t e r r u p t v e c t o r a r e a n o t u s e d 10000 16 11fff 16 1ffff 16 osd rom (8k bytes) s p e c i a l p a g e osd ram (96 bytes) (see note) zero p age note: refer to table 8.11.4 osd ram. m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 14 of 110 rej03b0134-0100z fig. 8.2.2 memory map (m37221m8h/mah-xxxsp/fp, m37221easp/fp) 0 0 0 0 1 6 00c0 16 00ff 16 0 1 f f 1 6 06b7 16 6 0 0 0 1 6 sf r area n o t u s e d f f f f 1 6 f f d e 1 6 ff00 16 0 6 0 0 1 6 i nte rrupt vector ar ea not used 1 0 0 0 0 1 6 11fff 16 1ffff 16 osd rom (8k bytes) s p e c i a l p a g e o s d r a m ( 9 6 b y t e s ) ( s e e n o t e ) zero p age m 37221m8h- xxxs p/fp ram (576 bytes) 0 3 b f 1 6 0 3 0 0 1 6 02ff 16 0 2 c 0 1 6 0217 16 n o t u s e d 2 p a g e r e g i s t e r n o t u s e d 021b 16 note: refer to table 8.11.4 osd ram. m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 15 of 110 rej03b0134-0100z fig. 8.2.3 memory map of special function register (sfr) (1) p 3 0 s p31s pw0 pw1 pw2 pw3 pw4 pw5 pw6 pw7 pn2 pn3 pn4 sm0 sm1 sm2 sm3 sm5 sm6 ? 00 1 6 ? 00 16 ? 00 16 0 0 0 ? ? 0 0 ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? 00 16 ? ? ? 0 0 ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? da1s da2s da10 da11 da12 da13 da14 da15 d a 2 0 da21 da22 da23 da24 da25 sad0 sad1 sad2 sad3 sad4 sad5 sad6 rb w lrb ad0 aas al pin bb trx mst bc0 bc1 bc2 es0 als 10 bit sad bsel 0 bsel 1 ccr0 ccr1 ccr2 ccr3 ccr4 fast mode ack bit ack 00 16 00 16 00 16 0 0 0 0 0 1 ? 0 d 0 1 6 d 1 1 6 d 2 1 6 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c 0 1 6 c 1 1 6 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c 9 1 6 c b 1 6 c c 1 6 c d 1 6 c e 1 6 c f 1 6 ca 16 port p5 (p5) p o r t p 5 d i r e c t i o n r e g i s t e r ( d 5 ) p o r t p 3 o u t p u t m o d e c o n t r o l r e g i s t e r ( p 3 s ) ( n o t e 1 ) d a - h r e g i s t e r ( d a - h ) d a - l r e g i s t e r ( d a - l ) p w m 0 r e g i s t e r ( p w m 0 ) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) r e g i s t e r p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( d 0 ) p w m 1 r e g i s t e r ( p w m 1 ) p w m 2 r e g i s t e r ( p w m 2 ) pwm3 register (pwm3) pwm4 register (pwm4) pwm output control register 1 (pw) pwm output control register 2 (pn) serial i/o mode register (sm) serial i/o regsiter (sio) da1 conversion regist er (da1) (not e 2) da2 conversion regist er (da2) (not e 2) i c da ta shift r egister (s0) 2 i c addr ess register (s0d) 2 i c status register (s1) 2 i c control register (s1d) 2 i c clock control register (s2) 2 0 0 0 n o t e 1 : a s f o r , f i x b i t s 2 a n d 3 t o 0 . 2 : d o n o t h a v e t h i s r e g i s t e r . f i x t h i s r e g i s t e r t o 0 0 1 6 . 00 16 0 0 1 6 0 0 1 6 00 16 00 16 ? 00 1 6 a d d r e s s m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 16 of 110 rej03b0134-0100z fig. 8.2.4 memory map of special function register (sfr) (2) s t a t e i m m e d i a t e l y a f t e r r e s e t b 7 b 0 b 7b0 hr0 h r 1 h r 2 hr3 hr4 hr5 cv10 c v 1 1 cv12 c v 1 3 c v 1 4 c v 1 5 c v 1 6 cv20 c v 2 1 cv22 c v 2 3 c v 2 4 c v 2 5 c v 2 6 cs10 c s 1 1 cs20 c s 2 1 md10 md20 co01 c o 0 2 co03 c o 0 5 co11 co12 co13 co15 co21 co22 co23 co25 co31 c o 3 2 co33 c o 3 5 cc0 c c 1 c c 2 vsyc r /g/b out1 op5 op6 op7 hsyc ck0 c k 1 adm0 a d m 1 adm2 a d m 4 adc0 a d c 1 adc2 a d c 4a d c 3 a d c 5 t 34 m 0 t 3 4 m 1 t 34 m 2 t 3 4 m 3 t 3 4 m 4 t 12 m 0 t 1 2 m 1 t 12 m 2 t 1 2 m 3 t 1 2 m 4 ck0 re5 re4 re3 cm2 tm1r tm2r tm3r tm4r crtr vscr it3r c k 0 m s r 1 t 1 r 1t2r s 1 r t m 1 e tm2e t m 3 e tm4e c r t e v s c e it3e 1t1e 1 t 2 e s 1 e m s e t 3 4 m 5 ck0 ? 0 0 1 6 ? 0 0 0 0 0 0 0 ff 16 0 7 1 6 f f 1 6 0 7 1 6 co04 co14 co24 co34 c o 0 6 co16 co26 c o 3 6 co07 co17 co27 co37 c c 7 out2 iicr iice f0 16 f 1 1 6 f2 16 f3 16 f 4 1 6 f 5 1 6 f 6 1 6 f 7 1 6 f 8 1 6 f9 16 fa 16 fb 16 fc 16 f d 1 6 f e 1 6 f f 1 6 e 0 1 6 e 1 1 6 e 2 1 6 e 3 1 6 e4 16 e 5 1 6 e6 16 e7 16 e 8 1 6 e9 16 e b 1 6 e c 1 6 ed 16 e e 1 6 e f 1 6 ea 16 a d d r e s s o s d c o n t r o l r e g i s t e r ( c c ) o s d p o r t c o n t r o l r e g i s t e r ( c r t p ) a-d contro l register 1 (ad1) a-d contro l register 2 (ad2) t i m e r 1 ( t m 1 ) v e r t i c a l r e g i s t e r 2 ( c v 2 ) c o l o r r e g i s t e r 0 ( c o 0 ) c o l o r r e g i s t e r 1 ( c o 1 ) c h a r a c t e r s i z e r e g i s t e r ( c s ) border selecti on register (md) r e g i s t e r h o r i z o n t a l r e g i s t e r ( h r ) v e r t i c a l r e g i s t e r 1 ( c v 1 ) time r 2 (tm2) t i m e r 3 ( t m 3 ) t i m e r 4 ( t m 4 ) t i m e r 1 2 m o d e r e g i s t e r ( t 1 2 m ) t i m e r 3 4 m o d e r e g i s t e r ( t 3 4 m ) pwm5 register (pwm5) i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( r e ) t e s t r e g i s t e r ( t e s t ) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) color regist er 2 (co2) c o l o r r e g i s t e r 3 ( c o 3 ) o s d c l o c k s e l e c t i o n r e g i s t e r ( c k ) cpu mode register (cpum) b i t a l l o c a t i o n 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 00 16 0 0 1 6 000 0 0 111 1 10 0 0 0 0 00 16 0 000000 0 0 1 6 0 ? 0 ?????? ??????? 0 000???? ? 0 0000?0? ? ? ? 0000000? 1 1111100 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 0 0 1 6 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 17 of 110 rej03b0134-0100z fig. 8.2.5 memory map of 2 page register area b7 0 b7 0 2 1 7 1 6 2 1 8 1 6 2 1 9 1 6 2 1 b 1 6 2 1 a 1 6 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) r o m c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) rcr1 rcr0 00 16 00 16 00 16 00 16 0 000 16 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 18 of 110 rej03b0134-0100z fig. 8.2.6 internal state of processor status register and program counter at reset b 7 b0 b 7 b 0 1 r e g i s t e r p r o c e s s o r s t a t u s r e g i s t e r ( p s ) b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t p r o g r a m c o u n t e r ( p c h ) p r o g r a m c o u n t e r ( p c l ) c o n t e n t s o f a d d r e s s f f f f 1 6 c ontents of address fffe 16 i z c d b t v n?? ? ? ? ? ? : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : f unction bit : no f unction bit : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 imm ediately after reset : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 imm ediately after reset 1 0 < b i t a l l o c a t i o n > m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 19 of 110 rej03b0134-0100z priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 8.3 interrupts interrupts can be caused by 14 different sources comprising 4 exter- nal, 8 internal, 1 software, and 1 reset interrupts. interrupts are vec- tored interrupts with priorities as shown in table 8.3.1. reset is also included in the table as its operation is similar to an interrupt. when an interrupt is accepted, ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 20 of 110 rej03b0134-0100z (4) serial i/o interrupt this is an interrupt request from the clock synchronous serial i/o function. (5) f(x in )/4096 interrupt the f (x in )/4096 interrupt occurs regularly with a f(x in )/4096 pe- riod. set bit 0 of pwm output control register 1 to 0. (6) multi-master i 2 c-bus interface interrupt this is an interrupt request related to the multi-master i 2 c-bus interface. (7) brk instruction interrupt this software interrupt has the least significant priority. it does not have a corresponding interrupt enable bit, and it is not af- fected by the interrupt disable flag i (non-maskable). fig. 8.3.1 interrupt control interrupt request bi t interrupt enable bi t interrupt disable flag i brk instruction reset interrupt request m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 21 of 110 rej03b0134-0100z fig. 8.3.2 interrupt request register 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 0 0 f c bn a m e f u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 1 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d t i m e r 1 i n t e r r u p t r e q u e s t b i t ( t m 1 r ) 1 t i m e r 2 i n t e r r u p t r e q u e s t b i t ( t m 2 r ) 2 timer 3 interrupt request bit (tm3r) 3timer 4 interrupt request bit (tm4r) 4 osd interrupt request bit (crtr) 5 v sync interrupt request bit (vscr) 6 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( i i c r ) 7 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 22 of 110 rej03b0134-0100z fig. 8.3.4 interrupt control register 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) [ a d d r e s s 0 0 f e 1 6 ] bname fun ctions r w i n t e r r u p t c o n t r o l r e g i s t e r 1 0 timer 1 interrupt enable bit (tm1e) 0 : interrupt disabled 1 : interrupt enabled 1 timer 2 interrupt enable bit (tm2e) 2 timer 3 interrupt enable bit (tm3e) 3 4 osd interrupt enable bit (crte) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 0 0 0 0 0 rw rw rw rw rw r 7 timer 4 interrupt enable bit (tm4e) 0 : interrupt disabled 1 : interrupt enabled 5 v sync interrupt enable bit (vsce) 0 : interrupt disabled 1 : interrupt enabled 0 rw 6 0 : interrupt disabled 1 : interrupt enabled 0 rw int3 external interrupt enable bit (it3e) multi-master i 2 c-bu s inte rfac e interrup t enable bit (iice) 0 : interrupt disabled 1 : interrupt enabled w after reset fig. 8.3.5 interrupt control register 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 0 0 f f 1 6 ] bname f u n c t i o n s inte rrupt control register 2 0 i n t 1 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 1 e ) 0 : interrupt disabled 1 : interrupt enabled 1 i n t 2 e x t e r n a l i n t e r r u p t e n a b l e b i t ( i t 2 e ) 2 s e r i a l i / o i n t e r r u p t e n a b l e b i t ( s 1 e ) 3 4 f ( x i n ) / 4 0 9 6 i n t e r r u p t e n a b l e b i t ( m s e ) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled f i x t h i s b i t t o 0 . f i x t h e s e b i t s t o 0 . 0 00 a f t e r r e s e t 0 0 0 0 0 0 rw rw rw rw rw r r w w 5 t o 7 0 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 23 of 110 rej03b0134-0100z fig. 8.3.6 interrupt input polarity register n a m ef u n c t i o n s i n t 1 p o l a r i t y s w i t c h b i t ( r e 3 ) 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y i n t 2 p o l a r i t y s w i t c h b i t ( r e 4 ) i n t 3 p o l a r i t y s w i t c h b i t ( r e 5 ) n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . fix these bits to 0. f i x t h i s b i t t o 0 . n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . after rese t r w 0 0 0 0 0 0 r ? r w r w r w r w r ? r w 0 b 7b 6b 5b 4b 3b 2b 1b 0 i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( r e ) [ a d d r e s s 0 0 f 9 1 6 ] b i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r 0 1,2 3 4 5 6 7 0 00 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 24 of 110 rej03b0134-0100z 8.4 timers this microcomputer has 4 timers: timers 1 to 4. all timers are 8-bit timers with the 8-bit timer latch. the timer block diagram is shown in figure 8.4.3. all of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. by writing a count value to the correspond- ing timer latch (addresses 00f0 16 to 00f3 16 : timers 1 to 4), the value is also set to a timer, simultaneously. the count value is decremented by 1. the timer interrupt request bit is set to 1 by a timer overflow at the next count pulse, after the count value reaches 00 16 . 8.4.1 timer 1 t imer 1 can select one of the following count sources: f(x in )/16 f(x in )/4096 the count source of timer 1 is selected by setting bit 0 of timer 12 mode register 1 (address 00f4 16 ). t imer interrupt request occurs at timer 1 overflow. 8.4.2 timer 2 t imer 2 can select one of the following count sources: f(x in )/16 t imer 1 overflow signal external clock from the tim2 pin the count source of timer 2 is selected by setting bits 4 and 1 of timer 12 mode register (address 00f4 16 ). when timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8- bit prescaler. t imer 2 interrupt request occurs at timer 2 overflow. 8.4.3 timer 3 t imer 3 can select one of the following count sources: f(x in )/16 external clock from the h sync pin external clock from the tim3 pin the count source of timer 3 is selected by setting bits 5 and 0 of timer 34 mode register (address 00f5 16 ). t imer 3 interrupt request occurs at timer 3 overflow. 8.4.4 timer 4 t imer 4 can select one of the following count sources: f(x in )/16 f(x in )/2 t imer 3 overflow signal the count source of timer 3 is selected by setting bits 1 and 4 of timer 34 mode register (address 00f5 16 ). when timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8- bit prescaler. t imer 4 interrupt request occurs at timer 4 overflow. at reset, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. the f(x in )/16 is se- lected as the timer 3 count source. the internal reset is released by timer 4 overflow in this state and the internal clock is connected. at execution of the stp instruction, timers 3 and 4 are connected by hardware and ff 16 is automatically set in timer 3; 07 16 in timer 4. however, the f(x in )/16 is not selected as the timer 3 count source. so set both bit 0 of timer 34 mode register (address 00f5 16 ) and bit 6 at address 00c7 16 to 0 before execution of the stp instruction (f(x in )/16 is selected as the timer 3 count source). the internal stp state is released by timer 4 overflow in this state and the internal clock is connected. as a result of the above procedure, the program can start under a stable clock. the timer-related registers is shown in figures 8.4.1 and 8.4.2. m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 25 of 110 rej03b0134-0100z fig. 8.4.2 timer 34 mode register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 timer 34 mode register (t34m) [address 00f5 16 ] b a f t e r r e s e t rw timer 34 mo de register 0 n a m e f u n c t i o n s timer 3 count source selection bit (t34m0) 0 rw 1 timer 4 internal interrupt count source selection bit (t34m1) 0rw 2 3 timer 3 count stop bit (t34m2) 0: count start 1: count stop t i m e r 4 c o u n t s t o p b i t ( t 3 4 m 3 ) 0: count start 1: count stop 0 0 4 t i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 4 ) 0: internal clock source 1: f(x in )/2 0 5 t i m e r 3 e x t e r n a l c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 5 ) 0 : t i m 3 p i n i n p u t 1 : h s y n c p i n i n p u t 0 rw rw rw rw 0 : f ( x i n ) / 1 6 1 : e x t e r n a l c l o c k s o u r c e 0 : t i m e r 3 o v e r f l o w s i g n a l 1 : f ( x i n ) / 1 6 6 , 7n othing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0? r fig. 8.4.1 timer 12 mode register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 timer mode register (t12m) [address 00f4 16 ] b a f t e r r e s e t w t i m e r 1 2 m o d e r e g i s t e r 0 1 2 3 4 nam e functions timer 1 count source selection bit 1 (t12m0) 0: f(x in )/16 1: f(x in )/ 4096 timer 2 count source selection bit (t12m1) 0: interrupt clock source 1: external clock from tim2 pin timer 1 count stop bit (t12m2) 0: count start 1: count stop timer 2 count stop bit (t12m3) 0: count start 1: count stop timer 2 internal count source selection bit 2 (t12m4) r 0 0 0 0 0 w r w r w r w r w r 0: f(x in )/16 1: timer 1 overflow 5 fix this bit to 0. 0 w r 6, 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0? r 0 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 26 of 110 rej03b0134-0100z timer 1 (8) 1/4096 1/2 1/8 timer 1 latch (8) 8 8 8 t12m0 t12m2 t12m4 t12m1 t12m3 timer 2 (8) timer 2 latch (8) 8 8 8 timer 3 (8) timer 3 latch (8) 8 8 8 timer 4 (8) timer 4 latch (8) 8 8 8 data bus timer 1 interrupt request timer 2 interrupt request t34m0 t34m2 t34m5 t34m4 t34m3 t34m1 x in tim2 tim3 selection gate : connected to black colored side at reset t12m : timer 12 mode register t34m : timer 34 mode register ff 16 07 16 h sync reset stp instruction timer 3 interrupt request timer 4 interrupt request notes 1: h pulse width of external clock inputs tim2 and tim3 needs 4 machine cycles or more. 2: when the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3: in the stop mode or the wait mode, external clock inputs tim2 and tim3 cannot be used. fig. 8.4.3 timer block diagram m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 27 of 110 rej03b0134-0100z 8.5 serial i/o this microcomputer has a built-in serial i/o which can either transmit or receive 8-bit data serially in the clock synchronous mode. the serial i/o block diagram is shown in figure 8.5.1. the synchro- nous clock i/o pin (s clk ), data output pin (s out ), and data input pin (s in ) also functions as port p2. bit 3 of the serial i/o mode register (address 00dc 16 ) selects whether the synchronous clock is supplied internally or externally (from the s clk pin). when an internal clock is selected, bits 1 and 0 select whether f(x in ) or f(x cin ) is divided by 4, 16, 32, or 64. to use s in pin for serial i/o, set the corresponding bit of the port p2 direction regis- ter (address 00c5 16 ) to 0. fig. 8.5.1 serial i/o block diagram the operation of the serial i/o is described below. the operation of the serial i/o differs depending on the clock source; external clock or internal clock. 8 serial i/o shift register (8) data bus serial i/o interrupt request selection gate : connected to black colored side at reset. synchronization circuit f requency divider 1/8 1/4 1/16 sm1 sm0 serial i/o counter (8) sm5 : ls b msb s sm2 1/2 sm6 x in s in s out(/in) s clk 1/2 sm3 p2 1 latch p2 0 latch sm3 (address 00dd 16 ) sm : serial i/o mode register (see note) note : when the data is set in the serial i/o register (address 00dd 16 ), the register functions as the serial i/o shift register. m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 28 of 110 rej03b0134-0100z internal clock : the serial i/o counter is set to 7 during the write cycle into the serial i/o register (address 00dd 16 ), and the transfer clock goes high forcibly. at each falling edge of the transfer clock after the write cycle, serial data is output from the s out pin. transfer direction can be selected by bit 5 of the serial i/o mode register. at each rising edge of the transfer clock, data is input from the s in pin and data in the serial i/o register is shifted 1 bit. after the transfer clock has counted 8 times, the serial i/o counter becomes 0 and the transfer clock stops at high. at this time the interrupt request bit is set to 1. fig. 8.5.2 serial i/o timing (for lsb first) sy nchronous cloc k tr ansfer clock serial i/o register write sig nal s e r i a l i / o o u t p u t s o u t d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 (see note) s e r i a l i / o i n p u t s i n n o t e : w h e n a n i n t e r n a l c l o c k i s s e l e c t e d , t h e s o u t p i n i s a t h i g h - i m p e d a n c e a f t e r t r a n s f e r i s c o m p l e t e d . interrupt request bit is set to 1 external clock : the an external clock is selected as the clock source, the interrupt request is set to 1 after the transfer clock has been counted 8 counts. however, transfer operation does not stop, so the clock should be controlled externally. use the external clock of 1 mhz or less with a duty cycle of 50%. the serial i/o timing is shown in figure 8.5.2. when using an exter- nal clock for transfer, the external clock must be held at high for initializing the serial i/o counter. when switching between an inter- nal clock and an external clock, do not switch during transfer. also, be sure to initialize the serial i/o counter after switching. notes 1: on programming, note that the serial i/o counter is set by writing to the serial i/o register with the bit managing instructions, such as seb and clb. 2: when an external clock is used as the synchronous clock, write trans- mit data to the serial i/o register when the transfer clock input level is high. m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 29 of 110 rej03b0134-0100z fig. 8.5.3 serial i/o mode register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b0 s e r i a l i / o m o d e r e g i s t e r ( s m ) [ a d d r e s s 0 0 d c 1 6 ] bname f u n c t i o n s s e r i a l i / o m o d e r e g i s t e r 0 , 1i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s ( s m 0 , s m 1 ) b 1 b 0 0 0 : f ( x i n ) / 4 0 1 : f ( x i n ) / 1 6 1 0 : f ( x i n ) / 3 2 1 1 : f ( x i n ) / 6 4 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s m 2 ) 3 serial i/o port selection bit (sm3) 6 5 t r a n s f e r d i r e c t i o n s e l e c t i o n b i t ( s m 5 ) 0: p2 0 , p2 1 1: s clk, s out 0: external clock 1: internal clock 0: lsb first 1: msb first 4 fix this bit to 0. 7 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . a f t e r r e s e t rw 0 0 0 0 0 0rw rw rw r w rw rw 0r ? s e r i a l i n p u t p i n s e l e c t i o n b i t ( s m 6 ) 0 : i n p u t s i g n a l f r o m s i n p i n . 1 : i n p u t s i g n a l f r o m s o u t p i n . 0 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 30 of 110 rej03b0134-0100z 8.5.1 serial i/o common transmission/recep- tion mode by writing 1 to bit 6 of the serial i/o mode register, signals s in and s out are switched internally to be able to transmit or receive the serial data. figure 8.5.4 shows signals on serial i/o common transmission/re- ception mode. note: when receiving the serial data after writing ff 16 to the serial i/o regis- ter. fig. 8.5.4 signals on serial i/o common transmission/reception mode s e r i a l i / o s h i f t r e g i s t e r ( 8 ) 1 0 clock s c l k s out s i n s m 6 sm : seri al i/o mode register m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 31 of 110 rej03b0134-0100z function in conformity with philips i 2 c-bus standard: 10-bit addressing format 7-bit addressing format high-speed clock mode standard clock mode in conformity with philips i 2 c-bus standard: master transmission master reception slave transmission slave reception 16.1 khz to 400 khz (at t able 8.6.1 multi-master i 2 c-bus interface functions item format communication mode scl clock frequency note : we are not responsible for any third party s infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the i 2 c control register at address 00da 16 ) for connections between the i 2 c-bus interface and ports (scl1, scl2, sda1, sda2). 8.6 multi-master i 2 c-bus interface the multi-master i 2 c-bus interface is a serial communications cir- cuit, conforming to the philips i 2 c-bus data transfer format. this interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. figure 8.6.1 shows a block diagram of the multi-master i 2 c-bus in- terface and table 8.6.1 shows multi-master i 2 c-bus interface func- tions. this multi-master i 2 c-bus interface consists of the i 2 c address reg- ister, the i 2 c data shift register, the i 2 c clock control register, the i 2 c control register, the i 2 c status register and other control circuits. fig. 8.6.1 block diagram of multi-master i 2 c-bus interface i 2 c address register (s0d) b7 b0 sad6 sad5 sad4 sad3 sad2 sad1 sad0 rbw noise elimination circuit serial data (sda) address comparator b7 i c data shift register b0 data control circuit i 2 c clock control register (s2) system clock ( ) interrupt generating circuit interrupt request signal (iicirq) b7 mst trx bb pin al aas ad0 lrb b0 i c status register (s1) b7 b0 b sel1 b sel0 10bit sad als bc2 bc1 bc0 i 2 c control register (s1d) bit counter bb circuit clock control circuit noise elimination circuit serial clock (scl) b7 b0 ack ack bit f ast mode ccr4 ccr3 ccr2 ccr1 ccr0 internal data bus clock division s0 al circuit eso 2 2 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 32 of 110 rej03b0134-0100z 8.6.1 i 2 c data shift register the i 2 c data shift register (s0 : address 00d7 16 ) is an 8-bit shift register to store receive data and write transmit data. when transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the scl clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. when data is received, it is input to this register from bit 0 in synchronization with the scl clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. the i 2 c data shift register is in a write enable status only when the eso bit of the i 2 c control register (address 00da 16 ) is ?.?the bit counter is reset by a write instruction to the i 2 c data shift register. when both the eso bit and the mst bit of the i 2 c status register (address 00d9 16 ) are ?,?the scl is output by a write instruction to the i 2 c data shift register. reading data from the i 2 c data shift regis- ter is always enabled regardless of the eso bit value. note: to write data into the i 2 c data shift register after setting the mst bit to ??(slave mode), keep an interval of 8 machine cycles or more. fig. 8.6.2 data shift register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i 2 c data shift register (s0) [addre ss 00d7 16 ] b f u n c t i o n s a f t e r r e s e t r w i c d ata shif t r eg i ster 0 to 7 thi s i s an 8- bi t s hif t reg i ster to st ore receive data and write transmit data. i n d eterm i nate 2 n ote: 2 t o w r i t e d a t a i n t o t h e i c d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e m s t b i t t o 0 ( s l a v e m o d e ) , k e e p a n i n t e r v a l o f 8 m a c h i n e c y c l e s o r m o r e . n ame d 0 to d 7 r w m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 33 of 110 rej03b0134-0100z 8.6.2 i 2 c address register the i 2 c address register (address 00d8 16 ) consists of a 7-bit slave address and a read/write bit. in the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the start condition are detected. (1) bit 0: read/write bit (rbw) not used when comparing addresses, in the 7-bit addressing mode. in the 10-bit addressing mode, the first address data to be received is compared with the contents (sad6 to sad0 + rbw) of the i 2 c address register. the rbw bit is cleared to ??automatically when the stop condition is detected. (2) bits 1 to 7: slave address (sad0?ad6) these bits store slave addresses. regardless of the 7-bit address- ing mode and the 10-bit addressing mode, the address data trans- mitted from the master is compared with the contents of these bits. fig. 8.6.3 i 2 c address register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 r ea d /wr i te bi t (rbw) 1 t o 7 sl ave a dd ress ( sad0 to sad6) < o n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > t h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d . 0 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r s t a r t c o n d i t i o n ( r e a d s t a t e ) 1 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r r e s t a r t c o n d i t i o n ( w r i t e s t a t e ) < i n b o t h m o d e s > t h e a d d r e s s d a t a i s c o m p a r e d . i 2 c a d d r e s s r e g i s t e r i 2 c address register (s0d) [address 00d8 16 ] b n a m e function s 0 0 a f t e r r e s e t r w r r w m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 34 of 110 rej03b0134-0100z 8.6.3 i 2 c clock control register the i 2 c clock control register (address 00db 16 ) is used to set ack control, scl mode and scl frequency. (1) bits 0 to 4: scl frequency control bits (ccr0?cr4) these bits control the scl frequency. (2) bit 5: scl mode specification bit (fast mode) this bit specifies the scl mode. when this bit is set to ?,?the stan- dard clock mode is set. when the bit is set to ?,? the high-speed clock mode is set. (3) bit 6: ack bit (ack bit) this bit sets the sda status when an ack clock ? ? fig. 8.6.4 i 2 c address register (4) bit 7: ack clock bit (ack) this bit specifies a mode of acknowledgment which is an acknowl- edgment response of data transmission. when this bit is set to ?, the no ack clock mode is set. in this case, no ack clock occurs after data transmission. when the bit is set to ?,?the ack clock mode is set and the master generates an ack clock upon comple- tion of each 1-byte data transmission.the device for transmitting address data and control data releases the sda at the occurrence of an ack clock (make sda high) and receives the ack bit generated by the data receiving device. note: do not write data into the i 2 c clock control register during transmission. if data is written during transmission, the i 2 c clock generator is reset, so that data cannot be transmitted normally. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) [ a d d r e s s 0 0 d b 1 6 ] i 2 c c l o c k c o n t r o l r e g i s t e r 0 t o 4 s c l f r e q u e n c y c o n t r o l b i t s ( c c r 0 t o c c r 4 ) 7 5 6 s c l m o d e s p e c i f i c a t i o n b i t ( f a s t m o d e ) 0: s tan d ar d c l oc k mo d e 1: high-speed clock mode 0 s t a n d a r d c l o c k m o d e b nam e f u n c t i o n s a f t e r r e s e t r w 0 0 0 a c k b i t ( a c k b i t ) a c k c l o c k b i t ( a c k ) 0: ack i s returne d . 1: ack is not returned. 0: n o ack c l oc k 1: ack clock hi g h spee d clock mode s e t u p d i s a b l e d s e t u p d i s a b l e d 0 0 t o 0 2 s e t u p d i s a b l e d 333 03 s e t u p d i s a b l e d 2 5 0 0 4 1 0 0 4 0 0 ( s e e n o t e ) 0 5 83.3 1 6 6 0 6 5 0 0 / c c r v a l u e 1 0 0 0 / c c r v a l u e . . . 17.2 34.5 1 d 16.6 3 3 . 3 1 e 16.1 3 2 . 3 1 f ( a t = 4 m h z , u n i t : k h z ) n o t e : a t 4 0 0 k h z i n t h e h i g h - s p e e d c l o c k m o d e , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 3 : 2 i n t h e o t h e r c a s e s , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 1 : 1 s e t u p v a l u e o f c c r 4 c c r 0 r w r w r w r w m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 35 of 110 rej03b0134-0100z 8.6.4 i 2 c control register the i 2 c control register (address 00da 16 ) controls the data commu- nication format. (1) bits 0 to 2: bit counter (bc0?c2) these bits decide the number of bits for the next 1-byte data to be transmitted. an interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. when a start condition is received, these bits become ?00 2 ?and the address data is always transmitted and received in 8 bits. (2) bit 3: i 2 c-bus interface use enable bit (eso) this bit enables usage of the multimaster i 2 c bus interface. when this bit is set to ?,?interface is in the disabled status so the sda and the scl become high-impedance. when the bit is set to ?,?use of the interface is enabled. when eso = ?,?the following is performed. pin = ?,?bb = ??and al = ??are set (they are bits of the i 2 c status register at address 00d9 16 ). ? riting data to the i 2 c data shift register (address 00d7 16 ) is dis- abled. (3) bit 4: data format selection bit (als) this bit decides whether or not to recognize slave addresses. when this bit is set to ?,?the addressing format is selected, so that ad- dress data is recognized. when a match is found between a slave address and address data as a result of comparison or when a gen- eral call (refer to ?.6.5 i 2 c status register,?bit 1) is received, trans- mission processing can be performed. when this bit is set to ?,?the free data format is selected, so that slave addresses are not recog- nized. (4) bit 5: addressing format selection bit (10bit sad) this bit selects a slave address specification format. when this bit is set to ?,?the 7-bit addressing format is selected. in this case, only the high-order 7 bits (slave address) of the i 2 c address register (ad- dress 00d8 16 ) are compared with address data. when this bit is set to ?,?the 10-bit addressing format is selected and all the bits of the i 2 c address register are compared with the address data. (5) bits 6 and 7: connection control bits between i 2 c-bus interface and ports (bsel0, bsel1) these bits control the connection between scl and ports or sda and ports (refer to figure 8.6.5). fig. 8.6.5 connection port control by bsel0 and bsel1 note: set the corresponding direction register to ??to use the port as multi-master i 2 c-bus interface. 0 1 b s e l 0 scl1/p1 1 scl2/p1 2 ? ??bs el1 0 1 b s e l 0 sda1/p1 3 sda2/p1 4 0 1 b s e l 1 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e s c l sda m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 36 of 110 rej03b0134-0100z fig. 8.6.6 i 2 c control register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 to 2 b i t c o u n t e r ( n u m b e r o f t r a n s m i t / r e c i e v e b i t s ) ( b c 0 t o b c 2 ) b 2 b 1 b 0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c-bu s interface use enable bit (eso) 0: di sa bl e d 1: enabled 4 d a t a f o r m a t s e l e c t i o n b i t ( a l s ) 0 : a d d r e s s i n g f o r m a t 1 : f r e e d a t a f o r m a t 5 a d d r e s s i n g f o r m a t s e l e c t i o n b i t ( 1 0 b i t s a d ) 0 : 7 - b i t a d d r e s s i n g f o r m a t 1 : 1 0 - b i t a d d r e s s i n g f o r m a t 6, 7 c onnect i on c ontro l bi ts between i c-bus interface and ports ( bsel0, bsel1) b 7 b 6 c onnect i on port (s ee note ) 0 0: none 0 1: scl1, sda1 1 0: scl2, sda2 1 1: scl1, sda1, scl2, sda2 0 0 0 0 0 i 2 c c o n t r o l r e g i s t e r ( s 1 d ) [ a d d r e s s 0 0 d a 1 6 ] i 2 c cont rol register b n a m e f u n c t i o n s a f t e r r e s e t r w 2 r w r w r w r w r w m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 37 of 110 rej03b0134-0100z 8.6.5 i 2 c status register the i 2 c status register (address 00d9 16 ) controls the i 2 c-bus inter- face status. the low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. (1) bit 0: last receive bit (lrb) this bit stores the last bit value of received data and can also be used for ack receive confirmation. if ack is returned when an ack clock occurs, the lrb bit is set to ?.?if ack is not returned, this bit is set to ?.? except in the ack mode, the last bit value of received data is input. the state of this bit is changed from ??to ??by executing a write instruction to the i 2 c data shift register (address 00d7 16 ). (2) bit 1: general call detecting flag (ad0) this bit is set to ??when a general call ? ? (3) bit 2: slave address comparison flag (aas) this flag indicates a comparison result of address data. (4) bit 3: arbitration lost ? detecting flag (al) in the master transmission mode, when a device other than the mi- crocomputer sets the sda to ?,? arbitration is judged to have been lost, so that this bit is set to ?.?at the same time, the trx bit is set to ?,?so that immediately after transmission of the byte whose arbitra- tion was lost is completed, the mst bit is set to ?.?when arbitration is lost during slave address transmission, the trx bit is set to ??and the reception mode is set. consequently, it becomes possible to re- ceive and recognize its own slave address transmitted by another master device. ? (5) bit 4: i 2 c-bus interface interrupt request bit (pin) this bit generates an interrupt request signal. each time 1-byte data is transmitted, the state of the pin bit changes from ??to ?.?at the same time, an interrupt request signal is sent to the cpu. the pin bit is set to ??in synchronization with a falling edge of the last clock (including the ack clock) of an internal clock and an interrupt re- quest signal occurs in synchronization with a falling edge of the pin bit. when detecting the stop condition in slave, the multi-master i 2 c-bus interface interrupt request bit (ir) is set to ??(interrupt re- quest) regardless of falling of pin bit. when the pin bit is ?,?the scl is kept in the ??state and clock generation is disabled. figure 8.6.8 shows an interrupt request signal generating timing chart. the pin bit is set to ??in any one of the following conditions. ? riting ??to the pin bit executing a write instruction to the i 2 c data shift register (address 00d7 16 ) (see note) when the eso bit is ? at reset note: it takes 8 bclk cycles or more until pin bit becomes ??after write instructions are executed to these registers. the conditions in which the pin bit is set to ??are shown below: immediately after completion of 1-byte data transmission (includ- ing when arbitration lost is detected) immediately after completion of 1-byte data reception in the slave reception mode, with als = ??and immediately after completion of slave address or general call address reception in the slave reception mode, with als = ??and immediately after completion of address data reception (6) bit 5: bus busy flag (bb) this bit indicates the status of the bus system. when this bit is set to ?,?this bus system is not busy and a start condition can be gen- erated. when this bit is set to ?,?this bus system is busy and the occurrence of a start condition is disabled by the start condition duplication prevention function (see note). this flag can be written by software only in the master transmission mode. in the other modes, this bit is set to ??by detecting a start condition and set to ??by detecting a stop condition. when the eso bit of the i 2 c control register (address 00da 16 ) is ??at reset, the bb flag is kept in the ??state. (7) bit 6: communication mode specification bit (transfer direction specification bit: trx) this bit decides the direction of transfer for data communication. when this bit is ?,?the reception mode is selected and the data of a trans- mitting device is received. when the bit is ?,?the transmission mode is selected and address data and control data are output into the sda in synchronization with the clock generated on the scl. when the als bit of the i 2 c control register (address 00da 16 ) is ? in the slave reception mode, the trx bit is set to ??(transmit) if the ___ least significant bit (r/w bit) of the address data transmitted by the ___ master is ?.?when the als bit is ??and the r/w bit is ?,?the trx bit is cleared to ?? (receive). the trx bit is cleared to ??in one of the following conditions. when arbitration lost is detected. when a stop condition is detected. when occurence of a start condition is disabled by the start condition duplication prevention function (note). when mst = ??and a start condition is detected. when mst = ??and ack non-return is detected. at reset m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 38 of 110 rej03b0134-0100z (8) bit 7: communication mode specification bit (master/slave specification bit: mst) this bit is used for master/slave specification in data communica- tions. when this bit is ?,?the slave is specified, so that a start condition and a stop condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. when this bit is ?,?the master is specified and a start condition and a stop condition are gener- ated, and also the clocks required for data communication are gen- erated on the scl. the mst bit is cleared to ??in any of the following conditions. immediately after completion of 1-byte data transmission when arbitration lost is detected when a stop condition is detected. when occurence of a start condition is disabled by the start condition duplication prevention function (note). at reset fig. 8.6.7 i 2 c status register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i 2 c s t a t u s r e g i s t e r ( s 1 ) [ a d d r e s s 0 0 d 9 1 6 ] i 2 c s t a t u s r e g i s t e r 0 3 4 5 6 , 7 b 7 b 6 0 0 : slave re cieve mode 0 1 : slave transmit mode 1 0 : master recieve mode 1 1 : master transmit mode 1 2 0 0 0 1 0 b n a m e f u n c t i o n s a f t e r r e s e t r w c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s ( t r x , m s t ) 0 : b us f ree 1 : bus busy b u s b u s y f l a g ( b b ) 0 : i nterrupt req uest i ssue d 1 : no interrupt request issued i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( p i n ) 0 : n ot d etecte d 1 : detected a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) ( s e e n o t e ) 0 : add re ss m i smatc h 1 : address match s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) ( s e e n o t e ) 0 : n o genera l ca ll d etecte d 1 : general call detected g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) ( s e e n o t e ) 0 : l ast bi t = 0 1 : last bit = 1 l a s t r e c e i v e b i t ( l r b ) ( s e e n o t e ) n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . i n d e t e r m i n a t e r r r r rw r w 0 r w ( s e e n o t e ) ( s e e n o t e ) (s ee note ) (s ee note ) fig. 8.6.8 interrupt request signal generation timing sc l pin i i c i r q note: the start condition duplication prevention function disables the start condition generation, bit counter reset, and scl output, when the follow- ing condition is satisfied: a start condition is set by another master device. m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 39 of 110 rej03b0134-0100z 8.6.6 start condition generation method when the eso bit of the i 2 c control register (address 00da 16 ) is ?, execute a write instruction to the i 2 c status register (address 00d9 16 ) to set the mst, trx and bb bits to ?.? a start condition will then be generated. after that, the bit counter becomes ?00 2 ?and an scl is output for 1 byte . the start condition generation timing and bb bit set timing are different in the standard clock mode and the high- speed clock mode. refer to figure 8.6.9 for the start condition generation timing diagram, and table 8.6.2 for the start condition/ stop condition generation timing table. fig. 8.6.9 start condition generation timing diagram i 2 c status registe write signal set time for bb flag hold time setup time scl sda bb flag setup time 8.6.7 stop condition generation method when the eso bit of the i 2 c control register (address 00da 16 ) is ?, execute a write instruction to the i 2 c status register (address 00d9 16 ) to set the mst bit and the trx bit to ??and the bb bit to ?? a stop condition will then be generated. the stop condition generation tim- ing and the bb flag reset timing are different in the standard clock mode and the high-speed clock mode. refer to figure 8.6.10 for the stop condition generation timing diagram, and table 8.6.2 for the start condition/stop condition generation timing table. fig. 8.6.10 stop condition generation timing diagram t able 8.6.2 start condition/stop condition generation tim- ing table item setup time (start condition) setup time (stop condition) hold time set/reset time for bb flag standard clock mode 5.0 s (20 cycles) 4.25 s (17 cycles) 5.0 s (20 cycles) 3.0 s (12 cycles) high-speed clock mode 2.5 s (10 cycles) 1.75 s (7 cycles) 2.5 s (10 cycles) 1.5 s (6 cycles) note: absolute time at m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 40 of 110 rej03b0134-0100z 8.6.8 start/stop condition detect conditions the start/stop condition detect conditions are shown in figure 8.6.11 and table 8.6.3. only when the 3 conditions of table 8.6.3 are satisfied, a start/stop condition can be detected. note: when a stop condition is detected in the slave mode (mst = 0), an interrupt request signal ?icirq?is generated to the cpu. fig. 8.6.11 start condition/stop condition detect timing dia- gram standard clock mode 6.5 s (26 cycles) < scl release time 3.25 s (13 cycles) < setup time 3.25 s (13 cycles) < hold time high-speed clock mode 1.0 s (4 cycles) < scl release time 0.5 s (2 cycles) < setup time 0.5 s (2 cycles) < hold time t able 8.6.3 start condition/stop condition detect conditions note: absolute time at 8.6.9 address data communication there are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. the respective ad- dress communication formats are described below. (1) 7-bit addressing format to support the 7-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00da 16 ) to ?.?the first 7-bit address data transmitted from the master is compared with the high-order 7- bit slave address stored in the i 2 c address register (address 00d8 16 ). at the time of this comparison, address comparison of the rbw bit of the i 2 c address register (address 00d8 16 ) is not made. for the data transmission format when the 7-bit addressing format is selected, refer to figure 8.6.12, (1) and (2). (2) 10-bit addressing format to support the 10-bit addressing format, set the 10bit sad bit of the i 2 c control register (address 00da 16 ) to ?.?an address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the i 2 c address register (address 00d8 16 ). at the time of this comparison, an address com- parison is performed between the rbw bit of the i 2 c address regis- ____ ter (address 00d8 16 ) and the r/w bit, which is the last bit of the address data transmitted from the master. in the 10-bit addressing ____ mode, the r/w bit not only specifies the direction of communication for control data but is also processed as an address data bit. when the first-byte address data matches the slave address, the aas bit of the i 2 c status register (address 00d9 16 ) is set to ?.?after the second-byte address data is stored into the i 2 c data shift register (address 00d7 16 ), perform an address comparison between the sec- ond-byte data and the slave address by software. when the address data of the 2nd byte matches the slave address, set the rbw bit of the i 2 c address register (address 00d8 16 ) to ??by software. this ____ processing can match the 7-bit slave address and r/w data, which are received after a restart condition is detected, with the value of the i 2 c address register (address 00d8 16 ). for the data transmis- sion format when the 10-bit addressing format is selected, refer to figure 8.6.12, (3) and (4). m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 41 of 110 rej03b0134-0100z 8.6.10 example of master transmission an example of master transmission in the standard clock mode, at the scl frequency of 100 khz with the ack return mode enable, is shown below. ? ? ? ? ? ? ? 8.6.11 example of slave reception an example of slave reception in the high-speed clock mode, at the scl frequency of 400 khz, with the ack non-return mode enabled while using the addressing format, is shown below. ? ? ? ? ? ? ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 42 of 110 rej03b0134-0100z fig. 8.6.12 address data communication format ss l a v e a d d r e s s a d a t aa d a t aa / a p r / w 7 b i t s 0 ? t o 8 b i t s1 to 8 bits ss l a v e a d d r e s s a d a t a ad a t a ap 7 b i t s 1 ? t o 8 b i t s1 to 8 bits ( 1 ) a m a s t e r - t r a n s m i t t e r t r a n s m i t s d a t a t o a s l a v e - r e c e i v e r s s l a v e a d d r e s s 1 s t 7 b i t s a a d a t a 7 b i t s 0 ? b i t s1 to 8 bits (2) a master-receiver receives data from a slave-transmitte r s l a v e a d d r e s s 2 n d b y t e a d a t aa / a p 1 t o 8 b i t s s s l a v e a d d r e s s 1 s t 7 b i t s a a 7 b i t s 0 ? b i t s7 bit s (3) a master-transmitter transmits data to a slave-receiver with a 10-bit address s l a v e a d d r e s s 2 n d b y t e data 1 to 8 bits sr slav e address 1st 7 bits a data a p 1 t o 8 b i t s ? (4) a master-receiver receives data from a slave-transmitter with a 10-bit address s:st art conditio np : stop condition a:ack bit r/w : read/write bit sr : restart c ondit ion from ma ster to slave from sl ave to master r / w r / w r/w r/w 8.6.12 precautions when using multi-master i 2 c-bus interface (1) read-modify-write instruction precautions for executing the read-modify-write instructions such as seb, and clb, is for each register of the multi-master i 2 c-bus inter- face are described below. ? 2 c data shift register (s0) when executing the read-modify-write instruction for this register during transfer, data may become an arbitrary value. ? 2 c address register (s0d) when the read-modify-write instruction is executed for this register at detection of the stop condition, data may become an arbitrary ______ value. it is because hardware changes the read/write bit (rbw) at the timing. ? 2 c status register (s1) do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. ? 2 c control register (s1d) when the read-modify-write instruction is executed for this register at detection of the start condition or at completion the byte trans- fer, data may become an arbitrary value. because hardware changes the bit counter (bc0?c2) at the timing. ? 2 c clock control register (s2) the read-modify-write instruction can be executed for this register. (2) start condition generation procedure us- ing multi-master ? ? ? ? ? ? ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 43 of 110 rej03b0134-0100z (3) restart condition generation procedure ? ? ? ? ? ? ? ? (4) stop condition generation procedure ? ? ? ? ? (5) writing to i 2 c status register do not execute an instruction to set the pin bit to ??from ??and an instruction to set the mst and trx bits to ??from ??simultaneously as it may cause the scl pin the sda pin to be released after about one machine cycle. also, do not execute an instruction to set the mst and trx bits to ??from ??when the pin bit is ?,?as it may cause the same problem. (6) process after stop condition generation do not write data in the i 2 c data shift register s0 and the i 2 c status register s1 until the bus busy flag bb becomes ??after generation the stop condition in the master mode. doing so may cause the stop condition waveform from being generated normally. reading the registers does not cause the same problem. m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 44 of 110 rej03b0134-0100z 8.7 pwm output function this microcomputer is equipped with two 14-bit pwm (da) and six 8-bit pwms (pwm0epwm5). da1 and da2 have a 14-bit resolution with the minimum resolution bit width of 0.25 s and a repeat period of 4096 s (for f(x in ) = 8 mhz). pwm0epwm7 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 s and repeat period of 1024 s (for f(x in ) = 8 mhz). figure 8.7.1 shows the pwm block diagram. the pwm timing gen- erating circuit applies individual control signals to da and pwm0e pwm5 using f(x in ) divided by 2 as a reference signal. 8.7.1 data setting when outputting da, first set the high-order 8 bits to the da-h regis- ter (address 00ce 16 ), then the low-order 6 bits to the da-l register (address 00cf 16 ). when outputting pwm0epwm5, set 8-bit output data to the pwmi register (i means 0 to 5; addresses 00d0 16 to 00d4 16 , 00f6 16 ). 8.7.2 transferring data from registers to pwm circuit data transfer from the 8-bit pwm register to the 8-bit pwm circuit is executed when writing data to the register. the signal output from the 8-bit pwm output pin corresponds to the contents of this register. also, data transfer from the da register (addresses 00ce 16 and 00cf 16 ) to the 14-bit pwm circuit is executed at writing data to the da-l register (address 00cf 16 ). reading from the da-h register (address 00ce 16 ) means reading this transferred data. accordingly, it is possible to confirm the data being output from the da output pin by reading the da register. 8.7.3 operating of 8-bit pwm the following explains the pwm operation. first, set bit 0 of pwm output control register 1 (address 00d5 16 ) to 0 (at reset, bit 0 is already set to 0 automatically), so that the pwm count source is supplied. pwm0epwm5 are also used as ports p0 0 ep0 5 , respectively. set those of the port p0 direction register to 1. and select each output polarity by bit 3 of pwm output control register 2 (address 00d6 16 ). then, set bits 2 to 7 of pwm output control register 1 to 1 (pwm output). the pwm waveform is output from the pwm output pins by setting these registers. figure 8.7.2 shows the 8-bit pwm timing. one cycle (t) is com- posed of 256 (2 8 ) segments. 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. refer to figure 8.7.2 (a). the 8-bit pwm outputs a waveform which is the logical sum (or) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit pwm register. several examples are shown in figure 8.7.2 (b). 256 kinds of output (high area: 0/256 to 255/256) are selected by changing the contents of the pwm register. an en- tirely high selection cannot be output, i.e. 256/256. 8.7.4 operating of 14-bit pwm as with 8-bit pwm, set the bit 0 of pwm output control register 1 (address 00d5 16 ) to 0 (at reset, bit 0 is already set to 0 automati- cally), so that the pwm count source is supplied. next, select the output polarity by bit 2 of pwm output control register 2 (address 00d6 16 ). then, the 14-bit pwm outputs from the d-a output pin by setting bit 1 of pwm output control register 1 to 0 (at reset, this bit already set to 0 automatically) to select the da output. the output example of the 14-bit pwm is shown in figure 8.7.3. the 14-bit pwm divides the data of the da latch into the low-order 6 bits and the high-order 8 bits. the fundamental waveform is determined with the high-order 8-bit data d h . a high area with a length t ? s ( m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 45 of 110 rej03b0134-0100z fig. 8.7.1 pwm block diagram m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 46 of 110 rej03b0134-0100z fig. 8.7.2 pwm timing ( a ) p u l s e s s h o w i n g t h e w e i g h t o f e a c h b i t 1 3 5 7 9 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 0 1 8 0 1 9 0 2 0 0 2 1 0 2 2 0 2 3 0 2 4 0 2 5 0 2 5 5 4 1 2 2 0 2 8 3 6 4 4 5 2 6 0 6 8 7 6 8 4 9 2 1 0 0 1 0 8 1 1 6 1 2 4 1 3 2 1 4 0 1 4 8 1 5 6 1 6 4 1 7 2 1 8 0 1 8 8 1 9 6 2 0 4 2 1 2 2 2 0 2 2 8 2 3 6 2 4 4 2 5 2 8 1 6 4 8 8 0 1 1 2 1 4 4 1 7 6 2 0 8 2 4 0 2 4 4 0 5 6 7 2 8 8 1 0 4 1 2 0 1 3 6 1 5 2 1 6 8 1 8 4 2 0 0 2 1 6 2 3 2 2 4 8 3 2 9 6 1 6 0 2 2 4 6 4 1 9 2 b i t 7 2 6 1 0 1 4 1 8 2 2 2 6 3 0 3 4 3 8 4 2 4 6 5 0 5 4 5 8 6 2 6 6 7 0 7 4 7 8 8 2 8 6 9 0 9 4 9 8 1 0 2 1 0 6 1 1 0 1 1 4 1 1 8 1 2 2 1 2 6 1 3 0 1 3 4 1 3 8 1 4 2 1 4 6 1 5 0 1 5 4 1 5 8 1 6 2 1 6 6 1 7 0 1 7 4 1 7 8 1 8 2 1 8 6 1 9 0 1 9 4 1 9 8 2 0 2 2 0 6 2 1 0 2 1 4 2 1 8 2 2 2 2 2 6 2 3 0 2 3 4 2 3 8 2 4 2 2 4 6 2 5 0 2 5 4 b i t 6 b i t 5 b i t 4 b i t 3 b i t 2 b i t 1 1 2 8 b i t 0 p w m o u t p u t t = 4 s t = 1 0 2 4 s f ( x i n ) = 8 m h z ( b ) e x a m p l e o f 8 - b i t p w m t 0 0 1 6 ( 0 ) 0 1 1 6 ( 1 ) 1 8 1 6 ( 2 4 ) f f 1 6 ( 2 5 5 ) t = 2 5 6 t m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 47 of 110 rej03b0134-0100z fig. 8.7.3 14-bit pwm timing (f(x in ) = 8 mhz) 0.25 s b 7b0 b6 b 5b4b3b 2b 1 0 0 010110 b 1 3b6 00 010110 b0 b5 101000 s e t 2 c 1 6 t o d a - h r e g i s t e r . [ d a - h r e g i s t e r ] d h at wr iting of da-l b 0 b 6b 5b 4b 3b 2b 1 0 10100 s e t 2 8 1 6 t o d a - l r e g i s t e r . [ d a - l r e g i s t e r ] d l at wr iting of da-l t h e s e b i t s d e c i d e h i g h l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m . t h e s e b i t s d e c i d e s m a l l e r i n t e r v a l t m i n w h i c h h i g h l e v a l a r e a i s [ h i g h l e v e l a r e a o f f u n d a m e n t a l w a v e f o r m + s h i g h - o r d e r 8 - b i t v a l u e o f d a l a t c h ? s ? s ? s ? = 0 . 2 5 s t = 4096 s r epeat period t 0 t 1 t 2 t 3 t 4 t 5 t 59 t 60 t 61 t 62 t 63 [ d a l a t c h ] b 7 2c 2b 2a 03 02 01 00 2c 2b 2a 03 02 01 00 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 48 of 110 rej03b0134-0100z fig. 8.7.4 pwm output control register 1 fig. 8.7.5 pwm output control register 2 b7 b 6 b 5 b 4 b 3 b 2 b 1 b0 p w m o u t p u t c o n t r o l r e g i s t e r 1 ( p w ) [ a d d r e s s 0 0 d 5 b a f t e r r e s e t rw pwm ou tput control register 1 0 1 2 3 4 0 n a m ef unctions da, pwm count source selection bit (pw0) 0 : c o u n t s o u r c e s u p p l y 1 : c o u n t s o u r c e s t o p p 0 0 / p w m 0 o u t p u t s e l e c t i o n b i t ( p w 2 ) 0 : p 0 0 o u t p u t 1 : p w m 0 o u t p u t p 0 1 / p w m 1 o u t p u t s e l e c t i o n b i t ( p w 3 ) 0: p0 1 output 1: pwm1 output p0 2 /pwm2 output selection bit (pw4) 0 : p 0 2 o u t p u t 1 : p w m 2 o u t p u t 5 p0 3 /pwm3 output selection bit (pw5) 0 : p 0 3 o u t p u t 1 : p w m 3 o u t p u t 6 p0 4 /pwm4 output selection bit (pw6) 0 : p 0 4 o u t p u t 1 : p w m 4 o u t p u t d a / p n 4 s e l e c t i o n b i t ( p w 1 ) 0 : d a o u t p u t 1 : p n 4 o u t p u t 7 p0 5 /pwm5 output selection bit (pw7) 0 : p 0 5 o u t p u t 1 : p w m 5 o u t p u t 0 0 0 0 0 0 0 1 6 ] rw rw rw rw rw rw rw rw 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r ? 2 3 4 da output polarity selection bit (pn2) 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y pwm output polarity selection bit (pn3) da general-purpose output bit (pn4) 0 : o u t p u t l o w 1 : o u t p u t h i g h 5 t o 7 0 0 0 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y r w r w r w 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r ? b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p w m o u t p u t c o n t r o l r e g i s t e r 2 ( p n ) [ a d d r e s s 0 0 d 6 1 6 ] b a f t e r r e s e t r w p w m o u t p u t c o n t r o l r e g i s t e r 2 n a m e f u n c t i o n s 0 , 1 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 49 of 110 rej03b0134-0100z 8.8 a-d comparator a-d comparator consists of a 6-bit d-a converter and a comparator. the a-d comparator block diagram is shown in figure 8.8.1. the reference voltage v ref for d-a conversion is set by bits 0 to 5 of the a-d control register 2 (address 00ef 16 ). the comparison result of the analog input voltage and the reference voltage v ref is stored in bit 4 of the a-d control register 1 (address 00ee 16 ). for a-d comparison, set 0 to corresponding bits of the direction register to use ports as analog input pins. write the data to select analog input pins for bits 0 to 2 of the a-d control register 1 and write the digital value corresponding to v ref to be compared to bits 0 to 5 of the a-d control register 2. the voltage comparison is started by writing to the a-d control register 2, and it is completed after 16 machine cycles (nop instruction ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 50 of 110 rej03b0134-0100z fig. 8.8.2 a-d control register 1 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a-d c ontrol register 1 (ad1) [address 00ee 16 ] b a f t e r r e s e t rw a - d c o n t r o l r e g i s t e r 1 0 t o 2 a na l og i nput p i n se l ect i on bits (adm0 to adm2) n a m ef unctions b 2 b 1 b 0 0 0 0 : a - d 1 0 0 1 : a - d 2 0 1 0 : a - d 3 0 1 1 : a - d 4 1 0 0 : a - d 5 1 0 1 : a - d 6 1 1 0 : d o n o t s e t 1 1 1 : d o n o t s e t 4 s torage bi t o f compar i son result (adm4) 0 : i n p u t v o l t a g e < r e f e r e n c e v o l t a g e 1 : i n p u t v o l t a g e > r e f e r e n c e v o l t a g e 0 i n d e t e r m i n a t e 0 3 thi s bi t i s a wr i te di sa bl e bi t. w hen this bit is read out, the value is 0. rw r r ? 0 5 to 7 n ot hi ng i s ass i gne d . thi s bi ts are wr i te di sa bl e bi ts. w hen these bits are read out, the values are 0. r ? ? fig. 8.8.3 a-d control register 2 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a - d c o n t r o l r e g i s t e r 2 ( a d 2 ) [ a d d r e s s 0 0 e f 1 6 ] b a f t e r r e s e t rw a - d c o n t r o l r e g i s t e r 2 0 to 5 6 , 7 0 0 n a m e f u n c t i o n s d - a c o n v e r t e r s e t b i t s ( a d c 0 t o a d c 5 ) b0 b1 b2 b3 b4 b 5 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e e d o u t , t h e v a l u e s a r e 0 . 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 3/128 v cc : 5/128 v cc : 1 2 3 / 1 2 8 v c c : 1 2 5 / 1 2 8 v c c : 1 2 7 / 1 2 8 v c c : 1/128 v cc rw r ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 51 of 110 rej03b0134-0100z fig. 8.9.1 d-a converter block diagram 8.9 d-a converter this microcomputer has 2 d-a converters with 6-bit resolution. d-a converter block diagram is shown in figure 8.9.1. d-a conversion is performed by setting the value in the da conver- sion register. the result of d-a conversion is output from the da pin by setting 1 to the da output enable bit of the port p3 output mode control register (bits 2 and 3 at address 00cd 16 ). the output analog voltage v is determined with the value n (n: deci- mal number) in the da conversion register. v = v cc ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 52 of 110 rej03b0134-0100z fig. 8.9.2 p3 output mode control register fig. 8.9.3 da conversion register i (i = 1, 2) b 7b 6b 5b4b 3b 2b 1b 0 d a c o n v e r s i o n r e g i s t e r i ( i = 1 , 2 ) ( d a i ) [ a d d r e s s e s 0 0 d e 1 6 , 0 0 d f 1 6 ] a f t e r r e s e t d a c o n v e r s i o n r e g i s t e r i 0 to 5 6 0 0 d a c o n v e r s i o n s e l e c t i o n b i t ( d a i 0 t o d a i 5 ) b 0 b 1 b 2 b 3 b 4 b5 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 1 / 6 4 v c c : 2 / 6 4 v c c : 6 1 / 6 4 v c c : 6 2 / 6 4 v c c : 6 3 / 6 4 v c c : 0/64v cc 0 7 0 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r ? r w r w r w bn a m e f u n c t i o n s f i x t h i s b i t t o 0 . n o t e : w h e n u s e m 3 7 2 2 1 m 4h/m6h/m8h/mah-xxxsp/fp, t h e r e i s n o t t h i s r e g i s t e r . f i x t o 0 0 1 6 . b7 b 6b 5b 4b 3b 2b 1b 0 p 3 o u t p u t m o d e c o n t r o l r e g i s t e r ( p 3 s ) [ a d d r e s s 0 0 c d 1 6 ] p 3 o u t p u t m o d e c o n t r o l r e g i s t e r 0 4 t o 7 p 3 0 o u t p u t f o r m s e l e c t i o n b i t ( p 3 0 s ) 0: cmos output 1: n-channel open-drain output 1 p 3 1 o u t p u t f o r m s e l e c t i o n b i t ( p 3 1 s ) 0: cmos output 1: n-channel open-drain output 2 d a 1 o u t p u t e n a b l e b i t ( d a 1 s ) 0: p 3 0 i nput/output 1: da1 output 3 d a 2 o u t p u t e n a b l e b i t ( d a 2 s ) 0: p 3 1 i nput/output 1: da2 output a f t e r r e s e t r w bn a m e f u n c t i o n s 0 0 0 0 0 r w r w r w r w r? n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 53 of 110 rej03b0134-0100z fig. 8.10.2 rom correction enable register fig. 8.10.1 rom correction address registers 8.10 rom correction function this can correct program data in the rom. up to 2 addresses can be corrected ; a program for correction is stored in the rom correction memory in the ram as the top address. there are 2 vectors for rom correction : v ector 1 : address 02c0 16 v ector 2 : address 02e0 16 set the address of the rom data to be corrected into the rom cor- rection address register. when the value of the counter matches the rom data address in the top address of the rom correction vector, the main program branches to the correction program stored in the rom memory. to return from the correction program to the main program, the op code and operand of the jmp instruction (total of 3 bytes) are necessary at the end of the correction program. the rom correction function is controlled by the rom correction enable regis- ter. notes 1: specify the first address (op code address) of each instruction as the rom correction address. 2: use the jmp instruction (total of 3 bytes) to return from the correction program to the main program. 3: do not set the same rom correction address to both vectors 1 and 2. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) [ a d d r e s s 0 2 1 b 1 6 ] bafter reset r o m c o r r e c t i o n e n a b l e r e g i s t e r 0 v ector 1 ena bl e bi t (rcr 0 ) n a m eunctions 0: di sa bl e d 1: enabl ed 1 v e c t o r 2 e n a b l e b i t ( r cr 1 ) 0: di sa bl e d 1: enabled 4 t o 7 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 0 0 0 0 2 , 3 f i x t h e s e b i t s t o 0 . 0 rw rw rw r? rw f 0 2 1 7 1 6 r o m c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) 0 2 1 8 1 6 r o m c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) 0 2 1 9 1 6 r o m c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) 0 2 1 a 1 6 r o m c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 54 of 110 rej03b0134-0100z 8.11 osd functions t able 8.11.1 outlines the osd functions. this microcomputer incor- porates an osd control circuit of 24 characters ? ? ? ? ? ? ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 55 of 110 rej03b0134-0100z the osd circuit has an extended display mode. this mode allows multiple lines (3 lines or more) to be displayed on the screen by inter- rupting the display each time one line is displayed and rewriting data in the block for which display has been terminated by software. figure 8.11.1 shows the configuration of an osd character. figure 8.11.2 shows the block diagram of the osd circuit. figure 8.11.3 shows osd control register. fig. 8.11.1 configuration of osd character display area 12 dots 16 dots m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 56 of 110 rej03b0134-0100z fig. 8.11.2 block diagram of osd circuit d i s p l a y o s c i l l a t i o n c i r c u i t o s c 1 o s c 2 h s y n c v s y n c o s d r a m 1 0 b i t s ? ? ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 57 of 110 rej03b0134-0100z fig. 8.11.3 osd control register b7 b6 b5 b4 b3 b2 b1 b0 osd control register (cc) [address 00ea 16 ] b name functions after reset r w osd control register 0 all-blocks display control bit (cc0) (see note) 0 : all-blocks display off 1 : all-blocks display on 0 1 block 1 display control bit (cc1) 0 : block 1 display off 1 : block 1 display on 0 2 0 : block 2 display off 1 : block 2 display on 0 3 to 6 0 note: display is controlled by logical product (and) between the all-blocks display control bit and each block control bit. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. block 2 display control bit (cc2) rw rw rw r? 7 0 : p1 0 1 : out2 0 p1 0 /out2 pin switch bit (cc7) rw m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 58 of 110 rej03b0134-0100z 8.11.1 display position the display positions of characters are specified in units called blocks. there are 2 blocks : blocks 1 and 2. up to 24 characters can be displayed in each block (refer to 8.11.3 memory for osd). the display position of each block can be set in both horizontal and vertical directions by software. the display start position in the horizontal direction can be selected for all blocks from 64-step display positions in units of 4t c (t c = osd oscillation cycle). the display start position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines. blocks are displayed in conformance with the following rules: block 2 is displayed after the display of block 1 is completed (figure 8.11.4 (a)). when the display position of block 1 is overlapped with that of block 2 (figure 8.11.4 (b)), block 1 is displayed in front. when another block display position appears while one block is displayed (figure 8.11.4 (c)),only block 1 is displayed. similarly, when multiline display, block 1 is displayed after the display of block 2 is completed. fig. 8.11.4 display position hr c v 2 b l o c k 1 bl oc k 2 ( a ) e x a m p l e w h e n e a c h b l o c k i s s e p a r a t e d bl oc k 1 ( b ) e x a m p l e w h e n b l o c k 2 o v e r l a p s w i t h b l o c k 1 (bl oc k 2 i s not di sp l aye d) hr c v 1 c v 2 ( c ) e xamp l e w h en bl oc k 2 over l aps i n process o f bl oc k 1 b l o c k 2 n otes 1: cv 1 or cv 2 i n di cates t h e vert i ca l di sp l ay start pos i t i on o f di sp l ay bl oc k 1 or 2. 2: hr indicates the horizontal display start position of display block 1 or 2. c v 1 hr cv 1 = cv 2 cv 1 bl oc k 1 ( secon d) m37221m4h/m6h/m8h/mah?xxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 59 of 110 rej03b0134-0100z the vertical display start position is determined by counting the hori- zontal sync signal (h sync ). at this time, when v sync and h sync are positive polarity (negative polarity), the count starts at the rising edge (falling edge) of h sync signal after the fixed cycle of the rising edge (falling edge) of v sync signal. so the interval from the rising edge (falling edge) of v sync signal to the rising edge (falling edge) of h sync signal needs enough time (2 machine cycles or more) to avoid jitters. the polarity of h sync and v sync signals can be select with the osd port control register (address 00ec 16 ). fig. 8.11.5 supplement explanation for display position w h e n b i t s 0 a n d 1 o f t h e o s d p o r t c o n t r o l r e g i s t e r ( a d d r e s s 0 0 e c 1 6 ) a r e s e t t o 1 ( n e g a t i v e p o l a r i t y ) v s y n c s i g n a l i n p u t v s y n c c o n t r o l s i g n a l i n m i c r o c o m p u t e r 0 . 1 2 5 t o 0 . 2 5 [ s ] ( a t f ( x i n ) = 8 m h z ) peri od of counting h sync signal (see note 2) h sync si g nal in p ut not co unt 12345 n o t e s 1 : t h e v e r t i c a l p o s i t i o n i s d e t e r m i n e d b y c o u n t i n g f a l l i n g e d g e o f h s y n c s i g n a l a f t e r r i s i n g e d g e o f v s y n c c o n t r o l s i g n a l i n t h e m i c r o c o m p u t e r . 2 : d o n o t g e n e r a t e f a l l i n g e d g e o f h s y n c s i g n a l n e a r r i s i n g e d g e o f v s y n c c o n t r o l s i g n a l i n m i c r o c o m p u t e r t o a v o i d j i t t e r . 3 : t h e p u l s e w i d t h o f v s y n c a n d h s y n c n e e d s 8 m a c h i n e c y c l e s o r m o r e . 8 m a c h i n e c y c l e s o r m o r e 8 ma chine cycles or more m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 60 of 110 rej03b0134-0100z fig. 8.11.6 vertical position register i the vertical display start position for each block can be set in 512 steps (where each step is 1t h (t h : h sync cycle)) as values 00 16 to 7f 16 in vertical position register i (i = 1 and 2) (addresses 00e1 16 and 00e2 16 ) the vertical position register i is shown in figure 8.11.6. b7 b6 b5 b4 b3 b2 b1 b0 ve r tical position register i (cvi) (i = 1 and 2) [addresses 00e1 16, 00e2 16 ] b name functions after reset r w ve r tical position register i 0 to 6 7 ve r tical display start positions 128 steps (00 16 to 7f 16 ) indeterminate 0 (cvi : cvi0 to cvi6) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw r? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 61 of 110 rej03b0134-0100z the horizontal display start position is common to all blocks, and can be set in 64 steps (where 1 step is 4t c , t c being the osd oscillation cycle) as values 00 16 to 3f 16 in bits 0 to 5 of the horizontal posi- tion register (address 00d1 16 ). the horizontal position register is shown in figure 8.11.7. fig. 8.11.7 horizontal position register b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hr) [address 00e0 16 ] b name functions after reset rw horizontal position register 0 to 5 6, 7 horizontal display start positions (hr0 to hr5) 64 steps (00 16 to 3f 16 ) 0 0 nothing is assigned. these bits are write disable bits. when thses bits are read out, the values are 0. rw r? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 62 of 110 rej03b0134-0100z fig. 8.11.8 character size register 8.11.2 character size the size of characters to be displayed can be from 3 sizes for each block. use the character size register (address 00e4 16 ) to set a char- acter size. the character size of block 1 can be specified by using bits 0 and 1 of the character size register; the character size of block 2 can be specified by using bits 2 and 3. figure 8.11.8 shows the character size register. the character size can be selected from 3 sizes: minimum size, me- dium size and large size. each character size is determined by the number of scanning lines in the height (vertical) direction and the oscillating cycle for display (t c ) in the width (horizontal) direction. the minimum size consists of [1 scanning line] ? ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 63 of 110 rej03b0134-0100z mini- mum medium large horizontal display start position fig. 8.11.9 display start position of each character size (horizontal direction) notes 1: the display start position in the horizontal direction is not affected by the character size. in other words, the horizontal display start position is common to all blocks even when the character size varies with each block (refer to figure 8.11.9). 2: i indicates 1 or 2. set values of character size register width (horizontal) direction t c : oscillating cycle for display 1 t c 2 t c 3 t c height (vertical) direction scanning lines 1 2 3 character size minimum medium large this is not available csi1 0 0 1 1 csi0 0 1 0 1 t able. 8.11.2 relation between set values in character size register and character sizes m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 64 of 110 rej03b0134-0100z 8.11.3 clock for osd the following 2 types of clocks can be selected for osd display. main clock supplied from x in pin main clock supplied from x in pin divided by i.5 clock from the ceramic resonator or the lc or oscillator from the pins osc1 and osc2 clock from the ceramic resonator or the quartz-crystal oscillator supplied from pins osc1 and osc2. the osd clock for each block can be selected by the osd clock selection register (address 00ed 16 ). when selecting the main clock, set the oscillation frequency to 8 mhz. fig. 8.11.10 osd clock selection circuit b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 o s d c l o c k s e l e c t i o n r e g i s t e r ( c k ) [ a d d r e s s 0 0 e d 1 6 ] b n a m e f u n c t i o n s a f t e r r e s e t r w osd cl oc k s e l ect i on r eg i ster 0 , 1 o s d c l o c k s e l e c t i o n b i t s ( c k 0 , c k 1 ) 0 s i n c e t h e m a i n c l o c k i s u s e d a s t h e c l o c k f o r d i s p l a y , t h e o s c i l l a t i o n f r e q u e n c y i s l i m i t e d . b e c a u s e o f t h i s , t h e c h a r a c t e r s i z e i n w i d t h ( h o r i z o n t a l ) d i r e c t i o n i s a l s o l i m i t e d . i n t h i s c a s e , p i n s o s c 1 a n d o s c 2 a r e a l s o u s e d a s i n p u t p o r t s p 3 3 a n d p 3 4 r e s p e c t i v e l y . t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g t h e f o l l o w i n g a c r o s s t h e p i n s o s c 1 a n d o s c 2 . a c e r a m i c r e s o n a t o r o n l y f o r o s d a q u a r t z - c r y s t a l o s c i l l a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r ( s e e n o t e ) 2 t o 7 0 0 0 0 0 0 0 b 1 t h e c l o c k f o r d i s p l a y i s s u p p l i e d b y c o n n e c t i n g r c o r l c a c r o s s t h e p i n s o s c 1 a n d o s c 2 . f u n c t i o n s 00 b 0 o s d o s c i l l a t i o n f r e q u e n c y = f ( x i n ) o s d o s c i l l a t i o n f r e q u e n c y = f ( x i n ) / 1 . 5 n o t e : i t i s n e c e s s a r y t o c o n n e c t o t h e r c e r a m i c r e s o n a t o r o r q u a r t z - c r y s t a l o s c i l l a t o r f o r o s d a c r o s s t h e p i n s x i n a n d x o u t . 0 0 1 1 1 1 fi x t h ese bi ts to 0. r w r w m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 65 of 110 rej03b0134-0100z 8.11.4 memory for osd there are 2 types of memory for osd: osd rom (addresses 10000 16 to 11fff 16 ) used to store character dot data and osd ram (ad- dresses 0600 16 to 06b7 16 ) used to specify the characters and colors to be displayed. fig. 8.11.11 character font data storing address (1) osd rom (addresses 10000 16 to 11fff 16 ) the dot pattern data for osd characters is stored in the osd rom. to specify the kinds of character font, it is necessary to write the character code (table 8.11.3) into the osd ram. the osd rom has a capacity of 8k bytes. since 32 bytes are re- quired for 1 character data, the rom can stores up to 256 kinds of characters. the osd rom space is broadly divided into 2 areas. the [vertical 16 dots] ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 66 of 110 rej03b0134-0100z block block 1 block 2 display position (from left) 1st character 2nd character 3rd character : 22nd character 23rd character 24th character not used 1st character 2nd character 3rd character : 22nd character 23rd character 24th character character code specification 0600 16 0601 16 0602 16 : 0615 16 0616 16 0617 16 0618 16 : 061f 16 0620 16 0621 16 0622 16 : 0635 16 0636 16 0637 16 color specification 0680 16 0681 16 0682 16 : 0695 16 0696 16 0697 16 0698 16 : 069f 16 06a0 16 06a1 16 06a2 16 : 06b5 16 06b6 16 06b7 16 t able 8.11.3 character code list (partially abbreviated) (2) osd ram (addresses 0600 16 to 06b7 16 ) the osd ram is allocated at addresses 0600 16 to 06b7 16 , and is divided into a display character code specification part, and color code specification part for each block. table 8.11.4 shows the con- tents of the osd ram. for example, to display 1 character position (the left edge) in block 1, write the character code in address 0600 16 , write the color code at 0680 16 . the structure of the osd ram is shown in figure 8.11.12. t able 8.10.4 contents of osd ram character code 00 16 character data storage address left 8 dots lines right 4 dots lines 10000 16 1000f 16 10800 16 1080f 16 01 16 10010 16 1001f 16 10810 16 1081f 16 02 16 10020 16 1002f 16 10820 16 1082f 16 03 16 10030 16 1003f 16 10830 16 1083f 16 : :: 7e 16 107e0 16 107ef 16 10fe0 16 10fef 16 7f 16 107f0 16 107ff 16 10ff0 16 10fff 16 80 16 11000 16 1100f 16 11800 16 1180f 16 81 16 11010 16 1101f 16 11810 16 1181f 16 : :: fd 16 117d0 16 117df 16 11fd0 16 11fdf 16 fe 16 117e0 16 117ef 16 11fe0 16 11fef 16 ff 16 117f0 16 117ff 16 to 11ff0 16 11fff 16 to to to to to to to to to to to to to to to to to to to to to m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 67 of 110 rej03b0134-0100z fig. 8.11.12 bit structure of osd ram [color specification] 0 0 : specifying color register 0 0 1 : specifying color register 1 1 0 : specifying color register 2 1 1 : specifying color register 3 color register specification 0 1 block 1 [character specification] specify 256 characters (00 16 to ff 16 ) character code 70 block 2 [character specification] 1st character : 0620 16 24th character : 0637 16 1st character : 0680 16 24th character : 0697 16 1st character : 0600 16 24th character : 0617 16 70 [color specification] 1st character : 06a0 16 24th character : 06b7 16 0 1 to to to to specify 256 characters (00 16 to ff 16 ) character code 0 0 : specifying color register 0 0 1 : specifying color register 1 1 0 : specifying color register 2 1 1 : specifying color register 3 color register specification m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 68 of 110 rej03b0134-0100z 8.11.5 color register the color of a displayed character can be specified by setting the color to one of the 4 registers (co0 to co3: addresses 00e6 16 to 00e9 16 ) and then specifying that color register with the osd ram. there are 3 color outputs; r, g and b. by using a combination of these outputs, it is possible to set 8 colors. however, since only 4 color registers are available, up to 4 colors can be disabled at one time. r, g and b outputs are set by using bits 1 to 3 in the color register. bit 5 is used to specify whether a character output or blank output. bits 4, 6 and 7 are used to specify character background color. figure 8.11.12 shows the color register. fig. 8.11.13 color register i b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c o l o r r e g i s t e r i ( c o i ) ( i = 0 t o 3 ) [ a d d r e s s e s 0 0 e 6 1 6 t o 0 0 e 9 1 6 ] b n ame f u n c t i o n s a f t e r r e s e t r w c o l o r r e g i s t e r i 0 0 r ? 1 g s i gna l output se l ect i on bit (c oi2) 0: n o c h aracter i s output 1: char acter is output 0 r w 2 r s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 3 ) 0: n o c h aracter i s output 1: char acter is output r w 3 b s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 4 ) ( s e e n o t e 1 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 4 o u t 1 s i g n a l o u t p u t c o n t r o l b i t ( c o i 5 ) ( s e e n o t e s 1 , 2 ) 0 : c h a r a c t e r i s o u t p u t 1 : b l a n k i s o u t p u t r w 5 g s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 6 ) ( s e e n o t e 1 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 6 r s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 7 ) ( s e e n o t e 2 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 7 r w b s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 1 ) 0 : n o c h a r a c t e r i s o u t p u t 1 : c h a r a c t e r i s o u t p u t n ot hi ng i s ass i gne d . thi s bi t i s a wr i te di sa bl e bi t. w hen this bit is read out, the value is 0. n o t e s 1 : w h e n b i t 5 = 0 a n d b i t 4 = 1 , t h e r e i s o u t p u t s a m e a s a c h a r a c t e r o r b o r d e r o u t p u t f r o m p i n o u t 1 . d o n o t s e t b i t 5 = 0 a n d b i t 4 = 0 . 2 : w h e n o n l y b i t 7 = 1 a n d b i t 5 0 , t h e r e i s o u t p u t f r o m p i n o u t 2 . 0 0 0 0 0 0 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 69 of 110 rej03b0134-0100z t able 8.11.5 display example of character background coloring (when green is set for a character and blue is set for backgroun d color) b o r d e r s e l e c t i o n r e g i s t e r color register i c o i 7 c o i 6 c o i 5 c o i 4 c o i 3 c o i 2 c o i 1 m d 0 g o u t p u tb output out1 output c h a r a c t e r o u t p u to u t 2 o u t p u t 0 ? ? ? ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 70 of 110 rej03b0134-0100z 8.11.6 border an border of 1 clock (1 dot) equivalent size can be added to a char- acter to be displayed in both horizontal and vertical directions. the border is output from the out1 pin. in this case, set bit 5 of a color register to 0 (character is output). border can be specified in units of block by using the border selec- tion register (address 00e5 16 ). figure 8.11.14 shows the border se- lection register. table 8.11.6 shows the relationship between the val- ues set in the border selection register and the character border func- tion. fig. 8.11.14 border selection register t able 8.11.6 relationship between set value in border selection register and character border function b7 b6 b5 b4 b3 b2 b1 b0 border selection register (md) [address 00e5 16 ] b name functions after reset r w border selection register 0 block 1 out1 output border selection bit (md10) 0 : same output as r, g, b is output 1 : border output indeterminate 2 block 2 out1 output border selection bit (md20) 0 : same output as r, g, b is output 1 : border output indeterminate rw rw 0 3 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r? 0 1 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. r? r, g, b output out1 output r, g, b output out1 output functions ordinary border including character example of output mdi0 0 1 border selection register note: i indicates 1or 2 fig. 8.11.15 example of border m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 71 of 110 rej03b0134-0100z 8.11.7 multiline display this microcomputer can ordinarily display 2 lines on the crt screen by displaying 2 blocks at different vertical positions. in addition, it can display up to 16 lines by using osd interrupts. an osd interrupt request occurs at the point at which that display of each block has been completed. in other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scan- ning line exceeds the block. note: an osd interrupt does not occur at the end of display when the block is not displayed. in other words, if a block is set to display off by the display control bit of the osd control register (address 00ea 16 ), an osd inter- rupt request does not occur (refer to figure 8.11.16). fig. 8.11.16 note on occurence of osd interrupt b l o c k 1 ( o n d i s p l a y ) blo ck 2 ( on display) b l o c k 1 ? ( o n d i s p l a y ) b l o c k 2 ? ( o n d i s p l a y ) b l o c k 1 ( o n d i s p l a y ) blo ck 2 ( on display) b l o c k 1 ? ( o f f d i s p l a y ) blo ck 2? (off display) o s d i n t e r r u p t r e q u e s t o s d i n t e r r u p t r e q u e s t o s d i n t e r r u p t r e q u e s t osd interr upt request o s d i n t e r r u p t r e q u e s t o s d i n t e r r u p t r e q u e s t no osd interr upt request on display (osd interrupt request occurs at the end of block display) off display (osd interrupt request does not occur at the end of block display) n o o s d i n t e r r u p t r e q u e s t m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 72 of 110 rej03b0134-0100z 8.11.8 osd output pin control the osd output pins r, g, b and out1 can also function as ports p5 2 ep5 5 . set the corresponding bit of the port p5 direction register (address 00cb 16 ) to 0 to specify these pins as osd output pins, or to 1 to specify as the general-purpose port p5. the out2 can also function as port p1 0 . set bit 0 of the osd port control register (address 00ec 16 ) to 1 (output mode). after that, set bit 7 of the osd control register to 1 to specify the pin as osd output pin, or set it to 0 to specify as port p1 0 . the input polarity of the h sync and v sync , and the output polarity of signals r, g, b, out1 and out2 can be specified with the osd port control register (address 00ec). set bits to 0 to specify positive polarity; set it to 1 to specify negative polarity (refer to figure 8.11.13). the osd port control register is shown in figure 8.11.17. fig. 8.11.17 osd port control register b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 o s d p o r t c o n t r o l r e g i s t e r ( c r t p ) [ a d d r e s s 0 0 e c 1 6 ] b n a m e f u n c t i o n s af ter rese t r w osd p ort c ontro l r eg i ster 0 h sync i n put po l ar i ty switch bit (hsyc) 0 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 10 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 2 r / g / b output po l ar i ty sw i tc h bit (r /g/b) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 30 4 out 1 output po l ar i ty s witch bit (out1) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 5 r s i gna l outp ut sw i tc h bi t (op5) 0 : r s i g n a l o u t p u t 1 : m u t e s i g n a l o u t p u t 0 6 g s i gna l output sw i tc h bit( op6) 0 : g s i gna l output 1 : mute signal output 0 7 b s i gna l output sw i tc h bit( op7) 0 : b s i g n a l o u t p u t 1 : m u t e s i g n a l o u t p u t 0 v sync i nput po l ar i ty s witch bit (vsyc) r w r w r w r w r w r w r w r w out 2 output po l ar i ty s witch bit (out2) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 73 of 110 rej03b0134-0100z 8.11.9 raster coloring function an entire screen (raster) can be colored by setting crt port control register. since each of the r, g and b pins can be switched to raster coloring output, 8 raster colors can be obtained. when the character color/character background color overlaps with the raster color, the color (r, g, b, out1, out2), specified for the character color/character background color, takes priority over the raster color. this ensures that character color/character background color is not mixed with the raster color. an example of raster coloring is shown in figure 8.11.18. fig. 8.11.18 example of raster coloring h sync a ' a o u t 1 r g b : c h a r a c t e r c o l o r r e d ( r + o u t 1 + o u t 2 ) : b o r d e r c o l o r b l a c k ( o u t 1 + o u t 2 ) : b a c k g r o u n d c o l o r m a g e n t a ( r + b + o u t 1 + o u t 2 ) : raster color blue (b + out1 + out2) s i g n a l s a c r o s s a - a ' o u t 2 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 74 of 110 rej03b0134-0100z fig. 8.12.1 sequence at detecting software runaway detection 8. 12 software runaway detect function this microcomputer has a function to decode undefined instructions to detect a software runaway. when an undefined op-code is input to the cpu as an instruction code during operation, the following processing is done. ? ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 75 of 110 rej03b0134-0100z 8.13. reset circuit when the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage is 5 v 10 %, hold the reset pin at low for 2 s or more, then return to high. then, as shown in figure 8.13.2, reset is released and the program starts from the address formed by using the content of address ffff 16 as the high-order address and the content of the address fffe 16 as the low-order address. the internal states of the microcomputer at reset are shown in figures 8.2.3 to 8.2.6. an example of the reset circuit is shown in figure 8.13.1. the reset input voltage must be kept 0.6 v or less until the power source voltage surpasses 4.5 v. fig. 8.13.2 reset sequence fig. 8.13.1 example of reset circuit p o w e r s o u r c e v o l t a g e 0 v reset input voltage 0 v 4 . 5 v 0 . 6 v p o w e r o n v c c r e s e t v s s microcomputer 1 5 4 3 0 . 1 f m 5 1 9 5 3 a l x i n m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 76 of 110 rej03b0134-0100z 8.14 clock generating circuit the built-in clock generating circuit is shown in figure 8.13.3. when the stp instruction is executed, the internal clock stops at high. at the same time, timers 3 and 4 are connected by hardware and ff 16 is set in timer 3 and 07 16 is set in the timer 4. select f(x in )/16 as the timer 3 count source (set bit 0 of the timer mode register 2 to 0 before the execution of the stp instruction). moreover, set the timer 3 and timer 4 interrupt enable bits to disabled (0) before ex- ecution of the stp instruction). the oscillator restarts when external interrupt is accepted. however, the internal clock keeps its high until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. when the wit instruction is executed, the internal clock stops in the high but the oscillator continues running. this wait state is re- leased when an interrupt is accepted (see note). since the oscillator does not stop, the next instruction can be executed at once. when returning from the stop or the wait state, to accept an interrupt, set the corresponding interrupt enable bit to 1 before executing the stp or the wit instructions. note: in the wait mode, the following interrupts are invalid. v sync interrupt osd interrupt timer 2 interrupt using external clock input from tim2 pin as count source timer 3 interrupt using external clock input from tim3 pin as count source timer 4 interrupt using f(x in )/2 as count source timer 1 interrupt using f(x in )/4096 as count source f(x in )/4096 interrupt multi-master i 2 c-bus interface interrupt a circuit example using a ceramic resonator (or a quartz-crystal os- cillator) is shown in figure 8.14.1. use the circuit constants in accor- dance with the resonator manufacture?s recommended values. a cir- cuit example with external clock input is shown in figure 8.14.2. in- put the clock to the x in pin, and open the x out pin. fig. 8.14.1 ceramic resonator circuit example fig. 8.14.2 external clock input circuit example x in x out c in microcomputer c out x in microcomputer vcc vss external oscillation circuit fig. 8.14.3 clock generating circuit block diagram i n t e r r u p t r e q u e s t i n t e r r u p t d i s a b l e f l a g i r e s e t s q r stp inst ruct ion s q r w i t i n s t r u c t i o n s q r stp instruction r e s e t i n t e r n a l c l o c k m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 77 of 110 rej03b0134-0100z reset vss vcc circuit example 1 reset vss vcc circuit example 2 note : make the level change from l to h at the point at which the power source voltage exceeds the specified voltage. 8.15 display oscillation circuit the osd oscillation circuit has a built-in clock oscillation circuits, so that a clock for osd can be obtained simply by connecting an lc, an rc, a ceramic resonator, or a quartz-crystal oscillator across the pins osc1 and osc2. which of the sub-clock or the osd oscillation cir- cuit is selected by setting bits 0 and 1 of the osd clock selection register (address 00ed 16 ). 8.17 addressing mode the memory access is reinforced with 17 kinds of addressing modes. refer to series 740 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 78 of 110 rej03b0134-0100z 10. absolute maximum ratings 1 1. recommended operating conditions (t a = e10 ?c to 70 ?c, v cc = 5 v 10 %, unless otherwise noted) power source voltage v cc input voltage cnv ss input voltage p0 0 ep0 7 ,p1 0 ep1 7 , p2 0 ep2 7 , p3 0 ep3 4 , osc1, x in , h sync , v sync , reset output voltage p0 0 ep0 7 , p1 0 ep1 7 , p2 0 ep2 7 , p3 0 ep3 2 , r, g, b, out1, d-a, x out , osc2 circuit current r, g, b, out1, p1 0 ep1 7 , p2 0 ep2 7 , p3 0 , p3 1 , d-a circuit current r, g, b, out1, p0 0 ep0 7 , p1 0 , p1 5 ep1 7 , p2 0 ep2 3 , p3 0 ep3 2 , d-a circuit current p1 1 ep1 4 circuit current p2 4 ep2 7 power dissipation operating temperature storage temperature symbol v cc v i v i v o i oh i ol1 i ol2 i ol3 p d t opr t stg conditions all voltages are based on v ss . output transistors are cut off. t a = 25 ?c ratings e0.3 to 6 e0.3 to 6 e0.3 to v cc + 0.3 e0.3 to v cc + 0.3 0 to 1 (note 1) 0 to 2 (note 2) 0 to 6 (note 2) 0 to 10 (note 3) 550 e10 to 70 e40 to 125 unit v v v v ma ma ma ma mw ?c ?c parameter v v v v v v v ma ma ma ma mhz mhz khz mhz khz max. 5.5 0 v cc v cc 0.4 v cc 0.3 v cc 0.2 v cc 1 2 6 10 8.1 8.0 100 1 400 power source voltage (note 4), during cpu, crt operation power source voltage h input voltage p0 0 ep0 7 ,p1 0 ep1 7 , p2 0 ep2 7 , p3 0 ep3 4 , s in , s clk , h sync , v sync , reset, x in , osc1, tim2, tim3, int1, int2, int3 h input voltage scl1, scl2, sda1, sda2 (when using i 2 c-bus) l input voltage p0 0 ep0 7 ,p1 0 ep1 7 , p2 0 ep2 7 , p3 0 ep3 4 l input voltage scl1, scl2, sda1, sda2 (when using i 2 c-bus) l input voltage h sync , v sync , reset,tim2, tim3, int1, int2, int3, x in , osc1, s in , s clk h average output current (note 1) r, g, b, out1, d-a, p1 0 ep1 7 , p2 0 ep2 7 , p3 0 , p3 1 l average output current (note 2) r, g, b, out1, d-a, p0 0 ep0 7 , p1 0 , p1 5 ep1 7 , p2 0 ep2 7 , p3 0 ep3 2 l average output current (note 2) p1 1 ep1 4 l average output current (note 3) p2 4 ep2 7 oscillation frequency (for cpu operation) (note 5) x in oscillation frequency (for crt display) (note 5) osc1 input frequency tim2, tim3 input frequency s clk input frequency scl1, scl2 v cc v ss v ih1 v ih2 v il1 v il2 v il3 i oh i ol1 i ol2 i ol3 f cpu f crt f hs1 f hs2 f hs3 min. 4.5 0 0.8v cc 0.7v cc 0 0 0 7.9 5.0 typ. 5.0 0 8.0 limits symbol parameter unit notes 1: the total current that flows out of the ic must be 20 ma (max.). 2: the total input current to ic (i ol1 + i ol2 ) must be 30 ma or less. 3: the total average input current for ports p2 4 ep2 7 to ic must be 20 ma or less. 4: connect 0.1 f or more capacitor externally across the power source pins v cc ev ss so as to reduce power source noise. also connect 0.1 f or more capacitor externally across the pins v cc ecnv ss . 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 79 of 110 rej03b0134-0100z max. 40 60 300 0.4 0.4 0.6 3.0 0.7 1.3 5 5 130 i cc v oh v ol v t+ e v te i izh i izl r bs v cc = 5.5 v, f(x in ) = 0 v cc = 4.5 v i oh = e0.5 ma v cc = 4.5 v i ol = 0.5 ma v cc = 4.5 v v cc = 4.5 v i ol = 10.0 ma v cc = 5.0 v v cc = 5.0 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 0 v v cc = 4.5 v i ol = 3 ma i ol = 6 ma ma a v v v a a ? f or more capacitor externally between the power source pins v cc ev ss so as to reduce power source noise. also connect 0.1 f or more capacitor externally between the pins v cc ecnv ss . 5: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. when using the data slicer, use 8 mhz. 6: p0 6 , p0 7 , p1 5 , p2 3 , p2 4 have hysteresis when used as interrupt input pins or timer input pins. p1 1 ep1 4 have hysteresis when these pins are used as multi- master i 2 c-bus interface ports. p2 0 ep2 2 have the hysteresis when used as serial i/o pins. 7: pin names in each parameter are described as below. (1) dedicated pins: dedicated pin names. (2) double-/triple-function ports same limits: i/o port name. function other than parts vary from i/o port limits: function pin name. 5 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 80 of 110 rej03b0134-0100z fig.12.1 measurement 1 3 5 2 4 v s s v c c v v oh or v ol i o h o r i o l 4 . 5 v e a c h o u t p u t p i n a f t e r s e t t i n g e a c h o u t p u t p i n t o h i g h l e v e l w h e n m e a s u r i n g v o h a n d t o l o w l e v e l w h e n m e a s u r i n g v o l , e a c h p i n i s m e a s u r e d . vss vcc 5 . 0 v each input pin v s s v c c v bs 4 . 5 v s c l 1 o r s d a 1 i b s a r b s = v b s / i b s s c l 2 o r s d a 2 r b s v s s v c c 5 . 5 v each input pin a i izh or i izl a v s s v c c x i n x o u t o s c 1 o s c 2 i c c 8 . 0 0 m h z p i n v c c i s m a d e t h e o p e r a t i o n s t a t e a n d i s m e a s u r e d t h e c u r r e n t , w i t h a c e r a m i c r e s o n a t o r . + power source voltage m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 81 of 110 rej03b0134-0100z max. 6 2 3 4 min. 1 t yp. 2.5 13. a-d comparison characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = 10 ?c to 70 ?c, unless otherwise noted) resolution absolute accuracy max. 6 2 bits lsb min. 0 limits unit t est conditions parameter symbol ? ? t yp. 1 15. multi-master i 2 c-bus bus line characteristics bus free time hold time for start condition low period of scl clock rising time of both scl and sda signals data hold time high period of scl clock falling time of both scl and sda signals data set-up time set-up time for repeated start condition set-up time for stop condition t buf t hd; sta t low t r t hd; dat t high t f t su; dat t su; sta t su; sto max. 1000 300 min. 1.3 0.6 1.3 20+0.1c b 0 0.6 20+0.1c b 100 0.6 0.6 max. 300 0.9 300 s s s ns s s ns ns s s unit standard clock mode high-speed clock mode parameter symbol note: c b = total capacitance of 1 bus line fig.15.1 definition diagram of timing on multi-master i 2 c-bus min. 4.7 4.0 4.7 0 4.0 250 4.7 4.0 sda scl p t buf s t hd ; sta t low t r t hd ; dat t high t f t su ; dat t su ; sta sr p t su ; sto t hd ; sta s sr p : start condition : restart condition : stop condition 14. d-a conversion characteristics (v cc = 5 v 10 %, v ss = 0 v, f(x in ) = 8 mhz, t a = 10 ?c to 70 ?c, unless otherwise noted) resolution absolute accuracy setting time output resistor bits lsb s k ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 82 of 110 rej03b0134-0100z 16. prom programming method the built-in prom of the one time prom version (blank) and the built-in eprom version can be read or programmed with a general- purpose prom programmer using a special programming adapter. product m37221easp m37221eafp the prom of the one time prom version (blank) is not tested or screened in the assembly process nor any following processes. to ensure proper operation after programming, the procedure shown in figure 16.1 is recommended to verify programming. fig. 16.1 programming and testing of one time prom version programming with prom programmer screening (caution) (150?c for 40 hours) verification with prom programmer functional check in target device caution : the screening temperature is far higher than the storage temperature. never expose to 150?c exceeding 100 hours. name of programming adapter pca7408 pca7439 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 83 of 110 rej03b0134-0100z 17. data required for mask orders the following are necessary when ordering a mask rom product: mask rom order confirmation form mark specification form data to be written to rom, in eprom form (32-pin dip type 27c101, three identical copies) or fdk m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 84 of 110 rej03b0134-0100z 18. one time prom version m37221easp/fp marking m37221easp xxxxxx xxxxxx is lot number m37221eafp xxxxxx xxxxxx is lot number m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 85 of 110 rej03b0134-0100z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 p0 6 /int2/a-d4 x out h sync v sync p0 0 /pwm0 p0 1 /pwm1 p0 2 /pwm2 p0 3 /pwm3 p0 4 /pwm4 p0 5 /pwm5 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 p2 6 p2 7 d-a p3 2 cnv ss x in v ss p5 2 /r p5 3 /g p5 4 /b p5 5 /out1 p2 0 /s clk p2 1 /s out p2 2 /s in p1 0 /out2 p1 1 /scl1 p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 5 /a-d1/int3 p1 6 /a-d2 p3 0 /a-d5 p3 1 /a-d6 reset osc1/p3 3 osc2/p3 4 v cc p1 7 /a-d3 m37221m4h/m6h/m8h/mah-xxxsp 19. appendix pin configuration (top view) outline 42p4b outline 42p2r-a/e 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 14 15 16 17 18 19 20 21 x out p0 0 /pwm0 p 0 1 / p w m 1 p 0 2 / p w m 2 p 0 3 / p w m 3 p 0 4 / p w m 4 cnv ss x in v s s 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 25 24 22 p5 2 /r p5 3 /g p5 4 /b p 5 5 / o u t 1 p 2 0 / s c l k p 2 1 / s o u t p 2 2 / s i n p 1 0 / o u t 2 p1 1 /scl1 p2 6 p2 7 d-a p3 2 osc1/p3 3 osc2/p3 4 p5 0 /h syn c p5 1 /v syn c p0 5 /pwm5 p0 6 /int2/a-d4 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 p1 6 /a-d2 p1 7 /a-d3 p3 0 /a-d5 p3 1 /a-d6 reset v c c 23 p1 5 /a-d1/int3 p1 4 /sda2 p1 3 /sda1 p1 2 /scl2 m37221m4h/m6h/m8h/mah-xxxfp m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 86 of 110 rej03b0134-0100z outline 42p4b outline 42p2r-a/e 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 17 18 19 2 0 2 1 x o u t p 5 0 / h s y n c p5 1 /v syn c p0 0 /pwm0 p 0 1 / p w m 1 p 0 2 / p w m 2 p 0 3 / p w m 3 p 0 4 / p w m 4 p 0 5 / p w m 5 p0 7 /int1 p 2 3 / t i m 3 p 2 4 / t i m 2 p 2 5 cnv ss x i n v s s 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 25 24 2 3 22 p 5 2 / r p5 3 /g p5 4 /b p 5 5 / o u t 1 p 2 0 / s c l k p 2 1 / s o u t p 2 2 / s i n p 1 0 / o u t 2 p 1 1 / s c l 1 p 1 2 / s c l 2 p 1 3 / s d a 1 p 1 4 / s d a 2 reset v cc m 3 7 2 2 1 e a f p p2 6 p2 7 d-a p3 2 osc1/p3 3 osc2/p3 4 p0 6 /int2/a-d4 p1 5 /a-d1/int3 p1 6 /a-d2 p1 7 /a-d3 p3 0 /a-d5/da1 p3 1 /a-d6/da2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 p0 6 /int2/a-d4 x out h sync v sync p0 0 /pwm0 p0 1 /pwm1 p0 2 /pwm2 p0 3 /pwm3 p0 4 /pwm4 p0 5 /pwm5 p0 7 /int1 p2 3 /tim3 p2 4 /tim2 p2 5 p2 6 p2 7 d-a p3 2 cnv ss x in v ss p5 2 /r p5 3 /g p5 4 /b p5 5 /out1 p2 0 /s clk p2 1 /s out p2 2 /s in p1 0 /out2 p1 1 /scl1 p1 2 /scl2 p1 3 /sda1 p1 4 /sda2 p1 5 /a-d1/int3 p1 6 /a-d2 p3 0 /a-d5/da1 p3 1 /a-d6/da2 reset osc1/p3 3 osc2/p3 4 v cc p1 7 /a-d3 m37221easp m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 87 of 110 rej03b0134-0100z memory map 0 0 0 0 1 6 00c0 16 00ff 16 0 1 b f 1 6 06b7 16 a 0 0 0 1 6 sf r area not used not used n o t u s e d f f f f 1 6 f f d e 1 6 ff00 16 0600 16 i n t e r r u p t v e c t o r a r e a n o t u s e d 10000 16 11fff 16 1ffff 16 osd rom (8k bytes) s p e c i a l p a g e osd ram (96 bytes) (see note) zero p age note: refer to table 8.11.4 osd ram. m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 88 of 110 rej03b0134-0100z 0 0 0 0 1 6 00c0 16 00ff 16 0 1 f f 1 6 06b7 16 6 0 0 0 1 6 sf r area n o t u s e d f f f f 1 6 f f d e 1 6 ff00 16 0 6 0 0 1 6 i nte rrupt vector ar ea not used 1 0 0 0 0 1 6 11fff 16 1ffff 16 osd rom (8k bytes) s p e c i a l p a g e o s d r a m ( 9 6 b y t e s ) ( s e e n o t e ) zero p age m 37221m8h- xxxsp/fp ram (576 bytes) 0 3 b f 1 6 0 3 0 0 1 6 02ff 16 0 2 c 0 1 6 0217 16 n o t u s e d 2 p a g e r e g i s t e r n o t u s e d 021b 16 note: refer to table 8.11.4 osd ram. m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 89 of 110 rej03b0134-0100z memory map of special function register (sfr) p 3 0 s p31s pw0 pw1 pw2 pw3 pw4 pw5 pw6 pw7 pn2 pn3 pn4 sm0 sm1 sm2 sm3 sm5 sm6 ? 00 1 6 ? 00 16 ? 00 16 0 0 0 ? ? 0 0 ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? ? ? ? ? 00 16 ? ? ? 0 0 ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? da1s da2s da10 da11 da12 da13 da14 da15 d a 2 0 da21 da22 da23 da24 da25 sad0 sad1 sad2 sad3 sad4 sad5 sad6 rb w lrb ad0 aas al pin bb trx mst bc0 bc1 bc2 es0 als 10 bit sad bsel 0 bsel 1 ccr0 ccr1 ccr2 ccr3 ccr4 fast mode ack bit ack 00 16 00 16 00 16 0 0 0 0 0 1 ? 0 d 0 1 6 d 1 1 6 d 2 1 6 d3 16 d4 16 d5 16 d6 16 d7 16 d8 16 d9 16 da 16 db 16 dc 16 dd 16 de 16 df 16 c 0 1 6 c 1 1 6 c2 16 c3 16 c4 16 c5 16 c6 16 c7 16 c8 16 c 9 1 6 c b 1 6 c c 1 6 c d 1 6 c e 1 6 c f 1 6 ca 16 port p5 (p5) p o r t p 5 d i r e c t i o n r e g i s t e r ( d 5 ) p o r t p 3 o u t p u t m o d e c o n t r o l r e g i s t e r ( p 3 s ) ( n o t e 1 ) d a - h r e g i s t e r ( d a - h ) d a - l r e g i s t e r ( d a - l ) p w m 0 r e g i s t e r ( p w m 0 ) port p1 (p1) port p1 direction register (d1) port p3 (p3) port p3 direction register (d3) port p2 (p2) port p2 direction register (d2) r e g i s t e r p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( d 0 ) p w m 1 r e g i s t e r ( p w m 1 ) p w m 2 r e g i s t e r ( p w m 2 ) pwm3 register (pwm3) pwm4 register (pwm4) pwm output control register 1 (pw) pwm output control register 2 (pn) serial i/o mode register (sm) serial i/o regsiter (sio) da1 conversion regist er (da1) (not e 2) da2 conversion regist er (da2) (not e 2) i c da ta shift r egister (s0) 2 i c addr ess register (s0d) 2 i c status register (s1) 2 i c control register (s1d) 2 i c clock control register (s2) 2 0 0 0 n o t e 1 : a s f o r , f i x b i t s 2 a n d 3 t o 0 . 2 : d o n o t h a v e t h i s r e g i s t e r . f i x t h i s r e g i s t e r t o 0 0 1 6 . 00 16 0 0 1 6 0 0 1 6 00 16 00 16 ? 00 1 6 a d d r e s s m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 90 of 110 rej03b0134-0100z state immediately after reset b 7 b0 b 7b0 hr0 h r 1 h r 2 h r 3 hr4 h r 5 cv10 c v 1 1 cv12 cv13 cv14 c v 1 5 c v 1 6 cv20 cv21 cv22 cv23 cv24 cv25 cv26 cs10 c s 1 1 cs20 cs21 md10 md20 co01 co02 co03 c o 0 5 co11 co12 co13 c o 1 5 co21 co22 co23 co25 co31 co32 co33 c o 3 5 cc0 c c 1 c c 2 v s y c r/g/b out1 o p 5 o p 6 o p 7 hsyc ck0 ck1 adm0 adm1 adm2 adm4 adc0 a d c 1 adc2 adc4 adc3 a d c 5 t 34 m 0 t 3 4 m 1 t 34 m 2 t 34 m 3 t 34 m 4 t 12 m 0 t 1 2 m 1 t 12 m 2 t 12 m 3 t 12 m 4 ck0 re5 re4 re3 cm2 tm1r t m 2 r tm3r tm4r crtr v s c r it3r ck0 msr 1t1r 1t2r s1r t m 1 e tm2e t m 3 e tm4e crte v s c e it3e 1t1e 1 t 2 e s 1 e mse t 3 4 m 5 ck0 ? 00 16 ? 0 0 0 0 0 0 0 ff 16 07 16 ff 16 07 16 c o 0 4 c o 1 4 co24 c o 3 4 c o 0 6 c o 1 6 co26 c o 3 6 c o 0 7 c o 1 7 co27 c o 3 7 c c 7 out2 i i c r i i c e f 0 1 6 f 1 1 6 f2 16 f3 16 f 4 1 6 f 5 1 6 f 6 1 6 f 7 1 6 f 8 1 6 f9 16 f a 1 6 f b 1 6 f c 1 6 f d 1 6 f e 1 6 f f 1 6 e 0 1 6 e 1 1 6 e 2 1 6 e 3 1 6 e 4 1 6 e5 16 e6 16 e7 16 e 8 1 6 e 9 1 6 e b 1 6 e c 1 6 ed 16 ee 16 e f 1 6 e a 1 6 a d d r e s s o s d c o n t r o l r e g i s t e r ( c c ) o s d p o r t c o n t r o l r e g i s t e r ( c r t p ) a-d contro l register 1 (ad1) a-d contro l register 2 (ad2) time r 1 (tm1) v e r t i c a l r e g i s t e r 2 ( c v 2 ) c o l o r r e g i s t e r 0 ( c o 0 ) color regist er 1 (co1) c h a r a c t e r s i z e r e g i s t e r ( c s ) b o r d e r s e l e c t i o n r e g i s t e r ( m d ) r egister h o r i z o n t a l r e g i s t e r ( h r ) vertical regi ster 1 (cv1) t i m e r 2 ( t m 2 ) t i m e r 3 ( t m 3 ) t i m e r 4 ( t m 4 ) t i m e r 1 2 m o d e r e g i s t e r ( t 1 2 m ) time r 34 mode regi ster (t34m) p w m 5 r e g i s t e r ( p w m 5 ) i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( r e ) test re gister (test) i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) i n t e r r u p t c o n t r o l r e g i s t e r 1 ( i c o n 1 ) i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) color regist er 2 (co2) c o l o r r e g i s t e r 3 ( c o 3 ) o s d c l o c k s e l e c t i o n r e g i s t e r ( c k ) cpu mode register (cpum) bit allocation 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 000 0 0 111 1 10 0 0 0 0 00 16 0 000000 0 0 1 6 0 ? 0 ?????? ??????? 0 000???? ? 0 0000?0? ? ? ? 0000000? 1 1111100 00 16 00 16 0 0 1 6 0 0 1 6 00 16 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 91 of 110 rej03b0134-0100z b7 0 b7 0 2 1 7 1 6 2 1 8 1 6 2 1 9 1 6 2 1 b 1 6 2 1 a 1 6 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) r o m c o r r e c t i o n a d d r e s s 1 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 1 ( l o w - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( h i g h - o r d e r ) r o m c o r r e c t i o n a d d r e s s 2 ( l o w - o r d e r ) rcr1 rcr0 00 16 00 16 00 16 00 16 0 000 16 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 92 of 110 rej03b0134-0100z internal state of processor status register and program counter at reset b 7 b0 b 7 b 0 1 r e g i s t e r p r o c e s s o r s t a t u s r e g i s t e r ( p s ) b i t a l l o c a t i o ns t a t e i m m e d i a t e l y a f t e r r e s e t p r o g r a m c o u n t e r ( p c h ) p r o g r a m c o u n t e r ( p c l ) c o n t e n t s o f a d d r e s s f f f f 1 6 c ontents of address fffe 16 i z c d b t v n?? ? ? ? ? ? : f i x t o t h i s b i t t o 0 ( d o n o t w r i t e t o 1 ) : f unction bit : no f unction bit : f i x t o t h i s b i t t o 1 ( d o n o t w r i t e t o 0 ) n a m e : : 0 imm ediately after reset : i n d e t e r m i n a t e i m m e d i a t e l y a f t e r r e s e t 0 1 ? : 1 imm ediately after reset 1 0 < b i t a l l o c a t i o n > m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 93 of 110 rej03b0134-0100z structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows: v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e b i t a t t r i b u t e s ( n o t e 1 ) ( n o t e 2 ) b i t p o s i t i o n 2 : b i t a t t r i b u t e s t h e a t t r i b u t e s o f c o n t r o l r e g i s t e r b i t s a r e c l a s s i f i e d i n t o 3 t y p e s : r e a d - o n l y , w r i t e - o n l y a n d r e a d a n d w r i t e . i n t h e f i g u r e , t h e s e a t t r i b u t e s a r e r e p r e s e n t e d a s f o l l o w s : : bit in which nothing is assigned n o t e s 1 : v a l u e s i m m e d i a t e l y a f t e r r e s e t r e l e a s e 0 0 a f t e r r e s e t r e l e a s e 1 1 a f t e r r e s e t r e l e a s e i n d e t e r m i n a t e i n d e t e r m i n a t e a f t e r r e s e t r e l e a s e r e a d e n a b l e d r e a d d i s a b l e d r e r read w r i t e e n a b l e d w r i t e d i s a b l e d 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . w write w e ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 94 of 110 rej03b0134-0100z address 00c7 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p ort p 3 di rect i on reg i ster (d 3 ) [add re ss 00 c 7 16 ] b n a m e f u n c t i o n s a f t e r r e s e t r w p o r t p 3 d i r e c t i o n r e g i s t e r 0 0 : p ort p 3 0 i nput mo d e 1 : port p3 0 output mode 0 1 0 : p ort p 3 1 i nput mo d e 1 : port p3 1 output mode 0 p o r t p 3 d i r e c t i o n r e g i s t e r r w r w i n d e t e r m i n a t e n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e i n d e t e r m i n a t e . r ? 3 t o 7 20 : p ort p 3 2 i nput mo d e 1 : port p3 2 output mode 0 r w addresses 00c1 16 , 00c3 16 , 00c5 16 b7 b6 b5 b4 b3 b2 b1 b0 port pi direction register (di) (i=0,1,2) [addresses 00c1 16, 00c3 16 , 00c5 16 ] b name functions after reset r w port pi direction register 00 : port pi 0 input mode 1 : port pi 0 output mode 0 1 0 : port pi 1 input mode 1 : port pi 1 output mode 0 2 0 : port pi 2 input mode 1 : port pi 2 output mode 0 30 : port pi 3 input mode 1 : port pi 3 output mode 0 40 : port pi 4 input mode 1 : port pi 4 output mode 0 50 : port pi 5 input mode 1 : port pi 5 output mode 0 60 : port pi 6 input mode 1 : port pi 6 output mode 0 7 0 : port pi 7 input mode 1 : port pi 7 output mode 0 port pi direction register rw rw rw rw rw rw rw rw m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 95 of 110 rej03b0134-0100z address 00cb 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p ort p 5 di rect i on reg i ster (d 5 ) [add re ss 00 cb 16 ] b n ame f unct i ons af ter rese t r w p o r t p 5 d i r e c t i o n r e g i s t e r 0 , 10 r ? n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 2 0 : r s i g n a l o u t p u t 1 : p o r t p 5 2 o u t p u t 0 r w 3 p o r t p 5 3 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 3 s e l ) 0 : g s i g n a l o u t p u t 1 : p o r t p 5 3 o u t p u t 0 r w 4 p o r t p 5 4 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 4 s e l ) 0 : b s i g n a l o u t p u t 1 : p o r t p 5 4 o u t p u t 0 r w 5 p o r t p 5 5 o u t p u t s i g n a l s e l e c t i o n b i t ( p 5 5 s e l ) 0 : out 1 s i gna l output 1 : port p5 5 output 0 r w 6 , 7 p ort p 5 2 output s i gna l selecti on bit (p52sel) i n d e t e r m i n a t e r ? n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . address 00cd 16 b 7b 6b5b 4b 3b 2b 1b 0 p 3 o u t p u t m o d e c o n t r o l r e g i s t e r ( p 3 s ) [ a d d r e s s 0 0 c d 1 6 ] p 3 o u t p u t m o d e c o n t r o l r e g i s t e r 0 4 t o 7 p 3 0 o u t p u t f o r m s e l e c t i o n b i t ( p 3 0 s ) 0: cmos output 1: n-channel open-drain output 1 p 3 1 o u t p u t f o r m s e l e c t i o n b i t ( p 3 1 s ) 0: cmos output 1: n-channel open-drain output 2 d a 1 o u t p u t e n a b l e b i t ( d a 1 s ) 0: p 3 0 i nput/output 1: da1 output 3 d a 2 o u t p u t e n a b l e b i t ( d a 2 s ) 0: p 3 1 i nput/output 1: da2 output a f t e r r e s e t r w bn a m e f u n c t i o n s 0 0 0 0 0 r w r w r w r w r? n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 96 of 110 rej03b0134-0100z address 00d5 16 b7 b 6 b 5 b 4 b 3 b2 b 1 b0 p w m o u t p u t c o n t r o l r e g i s t e r 1 ( p w ) [ a d d r e s s 0 0 d 5 b a f t e r r e s e t rw pwm ou tput control register 1 0 1 2 3 4 0 n a m ef unctions da, pwm count source selection bit (pw0) 0 : c o u n t s o u r c e s u p p l y 1 : c o u n t s o u r c e s t o p p 0 0 / p w m 0 o u t p u t s e l e c t i o n b i t ( p w 2 ) 0 : p 0 0 o u t p u t 1 : p w m 0 o u t p u t p 0 1 / p w m 1 o u t p u t s e l e c t i o n b i t ( p w 3 ) 0: p0 1 output 1: pwm1 output p0 2 /pwm2 output selection bit (pw4) 0 : p 0 2 o u t p u t 1 : p w m 2 o u t p u t 5 p0 3 /pwm3 output selection bit (pw5) 0 : p 0 3 o u t p u t 1 : p w m 3 o u t p u t 6 p0 4 /pwm4 output selection bit (pw6) 0 : p 0 4 o u t p u t 1 : p w m 4 o u t p u t d a / p n 4 s e l e c t i o n b i t ( p w 1 ) 0 : d a o u t p u t 1 : p n 4 o u t p u t 7 p0 5 /pwm5 output selection bit (pw7) 0 : p 0 5 o u t p u t 1 : p w m 5 o u t p u t 0 0 0 0 0 0 0 1 6 ] rw rw rw rw rw rw rw rw address 00d6 16 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r ? 2 3 4 da output polarity selection bit (pn2) 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y pwm output polarity selection bit (pn3) da general-purpose output bit (pn4) 0 : o u t p u t l o w 1 : o u t p u t h i g h 5 t o 7 0 0 0 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y r w r w r w 0 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r ? b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 p w m o u t p u t c o n t r o l r e g i s t e r 2 ( p n ) [ a d d r e s s 0 0 d 6 1 6 ] b after rese t r w p w m o u t p u t c o n t r o l r e g i s t e r 2 nam e f u n c t i o n s 0 , 1 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 97 of 110 rej03b0134-0100z address 00d7 16 address 00d8 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 r ea d /wr i te bi t (rbw) 1 t o 7 sl ave a dd ress ( sad0 to sad6) < o n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e > t h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s c o m p a r e d . 0 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r s t a r t c o n d i t i o n ( r e a d s t a t e ) 1 : w a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r r e s t a r t c o n d i t i o n ( w r i t e s t a t e ) < i n b o t h m o d e s > t h e a d d r e s s d a t a i s c o m p a r e d . i 2 c a d d r e s s r e g i s t e r i 2 c address register (s0d) [address 00d8 16 ] b n a m e function s 0 0 a f t e r r e s e t r w r? r w b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i 2 c d a t a s h i f t r e g i s t e r ( s 0 ) [ a d d r e s s 0 0 d 7 1 6 ] b f u n c t i o n s a f t e r r e s e t r w i c d ata shif t r eg i ster 0 t o 7 thi s i s an 8- bi t s hif t reg i ster to st ore receive data and write transmit data. i n d e t e r m i n a t e 2 n ote: 2 t o w r i t e d a t a i n t o t h e i c d a t a s h i f t r e g i s t e r a f t e r s e t t i n g t h e m s t b i t t o 0 ( s l a v e m o d e ) , k e e p a n i n t e r v a l o f 8 m a c h i n e c y c l e s o r m o r e . n ame d 0 to d 7 r w m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 98 of 110 rej03b0134-0100z address 00d9 16 address 00da 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i 2 c s t a t u s r e g i s t e r ( s 1 ) [ a d d r e s s 0 0 d 9 1 6 ] i 2 c s t a t u s r e g i s t e r 0 3 4 5 6 , 7 b 7 b 6 0 0 : slave re cieve mode 0 1 : slave transmit mode 1 0 : master recieve mode 1 1 : master transmit mode 1 2 0 0 0 1 0 b n a m e f u n c t i o n s a f t e r r e s e t r w c o m m u n i c a t i o n m o d e s p e c i f i c a t i o n b i t s ( t r x , m s t ) 0 : b us f ree 1 : bus busy b u s b u s y f l a g ( b b ) 0 : i nterrupt req uest i ssue d 1 : no interrupt request issued i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( p i n ) 0 : n ot d etecte d 1 : detected a r b i t r a t i o n l o s t d e t e c t i n g f l a g ( a l ) ( s e e n o t e ) 0 : add re ss m i smatc h 1 : address match s l a v e a d d r e s s c o m p a r i s o n f l a g ( a a s ) ( s e e n o t e ) 0 : n o genera l ca ll d etecte d 1 : general call detected g e n e r a l c a l l d e t e c t i n g f l a g ( a d 0 ) ( s e e n o t e ) 0 : l ast bi t = 0 1 : last bit = 1 l a s t r e c e i v e b i t ( l r b ) ( s e e n o t e ) n o t e : t h e s e b i t s a n d f l a g s c a n b e r e a d o u t , b u t c a n n n o t b e w r i t t e n . i n d e t e r m i n a t e r? r? r? r? rw r w 0 r w ( s e e n o t e ) ( s e e n o t e ) ( s e e n o t e ) (s ee note ) b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 t o 2 b i t c o u n t e r ( n u m b e r o f t r a n s m i t / r e c i e v e b i t s ) ( b c 0 t o b c 2 ) b 2 b 1 b 0 0 0 0 : 8 0 0 1 : 7 0 1 0 : 6 0 1 1 : 5 1 0 0 : 4 1 0 1 : 3 1 1 0 : 2 1 1 1 : 1 3 i 2 c - b u s i n t e r f a c e u s e e n a b l e b i t ( e s o ) 0 : d i s a b l e d 1 : e n a b l e d 4 d a t a f o r m a t s e l e c t i o n b i t ( a l s ) 0 : a d d r e s s i n g f o r m a t 1 : f r e e d a t a f o r m a t 5 a d d r e s s i n g f o r m a t s e l e c t i o n b i t ( 1 0 b i t s a d ) 0 : 7 - b i t a d d r e s s i n g f o r m a t 1 : 1 0 - b i t a d d r e s s i n g f o r m a t 6 , 7 c o n n e c t i o n c o n t r o l b i t s b e t w e e n i c - b u s i n t e r f a c e a n d p o r t s ( b s e l 0 , b s e l 1 ) b 7 b 6 c o n n e c t i o n p o r t ( s e e n o t e ) 0 0 : n o n e 0 1 : s c l 1 , s d a 1 1 0 : s c l 2 , s d a 2 1 1 : s c l 1 , s d a 1 , s c l 2 , s d a 2 0 0 0 0 0 i 2 c c o n t r o l r e g i s t e r ( s 1 d ) [ a d d r e s s 0 0 d a 1 6 ] i 2 c cont rol register b n a m e f u n c t i o n s a f t e r r e s e t r w 2 r w r w r w r w r w m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 99 of 110 rej03b0134-0100z address 00db 16 address 00dc 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 i 2 c c l o c k c o n t r o l r e g i s t e r ( s 2 ) [ a d d r e s s 0 0 d b 1 6 ] i 2 c c l o c k c o n t r o l r e g i s t e r 0 t o 4 s c l f r e q u e n c y c o n t r o l b i t s ( c c r 0 t o c c r 4 ) 7 5 6 s c l m o d e s p e c i f i c a t i o n b i t ( f a s t m o d e ) 0 : s t a n d a r d c l o c k m o d e 1 : h i g h - s p e e d c l o c k m o d e 0 s t a n d a r d c l o c k m o d e b n a m e f u n c t i o n s a f t e r r e s e t r w 0 0 0 a c k b i t ( a c k b i t ) a c k c l o c k b i t ( a c k ) 0 : a c k i s r e t u r n e d . 1 : a c k i s n o t r e t u r n e d . 0 : n o a c k c l o c k 1 : a c k c l o c k h i g h s p e e d c l o c k m o d e s e t u p d i s a b l e d s e t u p d i s a b l e d 0 0 t o 0 2 s e t u p d i s a b l e d 3 3 3 0 3 s e t u p d i s a b l e d 2 5 0 0 4 1 0 0 4 0 0 ( s e e n o t e ) 0 5 8 3 . 31 6 6 0 6 5 0 0 / c c r v a l u e 1 0 0 0 / c c r v a l u e . . . 1 7 . 2 3 4 . 5 1 d 1 6 . 63 3 . 3 1 e 1 6 . 1 3 2 . 3 1 f ( a t = 4 m h z , u n i t : k h z ) n o t e : a t 4 0 0 k h z i n t h e h i g h - s p e e d c l o c k m o d e , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 3 : 2 i n t h e o t h e r c a s e s , t h e d u t y i s a s b e l o w . 0 p e r i o d : 1 p e r i o d = 1 : 1 s e t u p v a l u e o f c c r 4 e c c r 0 r w r w r w r w b 7 b 6 b 5 b 4 b 3 b 2 b 1 b0 s e r i a l i / o m o d e r e g i s t e r ( s m ) [ a d d r e s s 0 0 d c 1 6 ] bname f u n c t i o n s s e r i a l i / o m o d e r e g i s t e r 0, 1 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s ( s m 0 , s m 1 ) b1 b0 0 0: f(x in )/4 0 1: f(x in )/16 1 0: f(x in )/32 1 1: f(x in )/ 64 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s m 2 ) 3 s e r i a l i / o p o r t s e l e c t i o n b i t ( s m 3 ) 6 5 t r a n s f e r d i r e c t i o n s e l e c t i o n b i t ( s m 5 ) 0: p2 0 , p2 1 1: s clk, s out 0: external clock 1: internal clock 0: lsb first 1: msb first 4 f i x t h i s b i t t o 0 . 7 n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . a f t e r r e s e t rw 0 0 0 0 0 0rw rw rw r w rw rw 0r ? s e r i a l i n p u t p i n s e l e c t i o n b i t ( s m 6 ) 0: input signal from s in pin. 1: input signal from s out pin. 0 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 100 of 110 rej03b0134-0100z address 00e0 16 addresses 00de 16 and 00df 16 b 7b 6b 5b4b 3b 2b 1b 0 d a c o n v e r s i o n r e g i s t e r i ( i = 1 , 2 ) ( d a i ) [ a d d r e s s e s 0 0 d e 1 6 , 0 0 d f 1 6 ] a f t e r r e s e t d a c o n v e r s i o n r e g i s t e r i 0 to 5 6 0 0 d a c o n v e r s i o n s e l e c t i o n b i t ( d a i 0 t o d a i 5 ) b 0 b 1 b 2 b 3 b 4 b5 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 1 / 6 4 v c c : 2 / 6 4 v c c : 6 1 / 6 4 v c c : 6 2 / 6 4 v c c : 6 3 / 6 4 v c c : 0/64v cc 0 7 0 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r ? r w r w r w bn a m e f u n c t i o n s f i x t h i s b i t t o 0 . n o t e : w h e n u s e m 3 7 2 2 1 m 4h/m6h/m8h/mah-xxxsp/fp, t h e r e i s n o t t h i s r e g i s t e r . f i x t o 0 0 1 6 . b7 b6 b5 b4 b3 b2 b1 b0 horizontal position register (hr) [address 00e0 16 ] b name functions after reset rw horizontal position register 0 to 5 6, 7 horizontal display start positions (hr0 to hr5) 64 steps (00 16 to 3f 16 ) 0 0 nothing is assigned. these bits are write disable bits. when thses bits are read out, the values are 0. rw r? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 101 of 110 rej03b0134-0100z addresses 00e1 16 and 00e2 16 address 00e4 16 b7 b6 b5 b4 b3 b2 b1 b0 ve r tical position register i (cvi) (i = 1 and 2) [addresses 00e1 16, 00e2 16 ] b name functions after reset r w ve r tical position register i 0 to 6 7 ve r tical display start positions 128 steps (00 16 to 7f 16 ) indeterminate 0 (cvi : cvi0 to cvi6) nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. rw r? b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c h a r a c t e r s i z e r e g i s t e r ( c s ) [ a d d r e s s 0 0 e 4 1 6 ] b n am e f unct i on s af ter reset r w c h a r a c t e r s i z e r e g i s t e r 0, 1 ch aracter s i ze o f bl oc k 1 selecti on bits (cs10, cs11) 00 : mi n i mum s i ze 01 : medium size 10 : large size 11 : do not set. i n d eterm i nat e 2 , 3 4 t o 7 0 c h a r a c t e r s i z e o f b l o c k 2 s e l e c t i o n b i t s ( c s 2 0 , c s 2 1 ) 0 0 : m i n i m u m s i z e 0 1 : m e d i u m s i z e 1 0 : l a r g e s i z e 1 1 : d o n o t s e t . n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . i n d e t e r m i n a t e r w r w r ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 102 of 110 rej03b0134-0100z address 00e5 16 addresses 00e6 16 to 00e9 16 b7 b6 b5 b4 b3 b2 b1 b0 border selection register (md) [address 00e5 16 ] b name functions after reset r w border selection register 0 block 1 out1 output border selection bit (md10) 0 : same output as r, g, b is output 1 : border output indeterminate 2 block 2 out1 output border selection bit (md20) 0 : same output as r, g, b is output 1 : border output indeterminate rw rw 0 3 to 7 nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. r? 0 1 nothing is assigned. this bit is a write disable bit. when this bit is read out, the value is 0. r? b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 c o l o r r e g i s t e r i ( c o i ) ( i = 0 t o 3 ) [ a d d r e s s e s 0 0 e 6 1 6 t o 0 0 e 9 1 6 ] b n ame f u n c t i o n s a f t e r r e s e t r w c o l o r r e g i s t e r i 0 0 r ? 1 g s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 2 ) 0 : n o c h a r a c t e r i s o u t p u t 1 : c h a r a c t e r i s o u t p u t 0 r w 2 r s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 3 ) 0: n o c h aracter i s output 1: char acter is output r w 3 b s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 4 ) ( s e e n o t e 1 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 4 o u t 1 s i g n a l o u t p u t c o n t r o l b i t ( c o i 5 ) ( s e e n o t e s 1 , 2 ) 0 : c h a r a c t e r i s o u t p u t 1 : b l a n k i s o u t p u t r w 5 g s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 6 ) ( s e e n o t e 1 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 6 r s i g n a l o u t p u t ( b a c k g r o u n d ) s e l e c t i o n b i t ( c o i 7 ) ( s e e n o t e 2 ) 0 : n o b a c k g r o u n d c o l o r i s o u t p u t 1 : b a c k g r o u n d c o l o r i s o u t p u t r w 7 r w b s i g n a l o u t p u t s e l e c t i o n b i t ( c o i 1 ) 0 : n o c h a r a c t e r i s o u t p u t 1 : c h a r a c t e r i s o u t p u t n ot hi ng i s ass i gne d . thi s bi t i s a wr i te di sa bl e bi t. w hen this bit is read out, the value is 0. n otes 1: wh en bi t 5 = 0 an d bi t 4 = 1, t h ere i s outp ut same as a c h aracter or border output from pin out1. do not se t bit 5 = 0 an d bit 4 = 0. 2: when only bit 7 =1 a nd bit 5 0, there is output from pin out2. 0 0 0 0 0 0 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 103 of 110 rej03b0134-0100z address 00ea 16 addresses 00ec 16 b7 b6 b5 b4 b3 b2 b1 b0 osd control register (cc) [address 00ea 16 ] b name functions after reset r w osd control register 0 all-blocks display control bit (cc0) (see note) 0 : all-blocks display off 1 : all-blocks display on 0 1 block 1 display control bit (cc1) 0 : block 1 display off 1 : block 1 display on 0 2 0 : block 2 display off 1 : block 2 display on 0 3 to 6 0 note: display is controlled by logical product (and) between the all-blocks display control bit and each block control bit. nothing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. block 2 display control bit (cc2) rw rw rw r? 7 0 : p1 0 1 : out2 0 p1 0 /out2 pin switch bit (cc7) rw b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 osd port contro l reg i ster ( crtp) [add re ss 00 ec 16 ] b n a m e f u n c t i o n s af ter rese t r w o s d p o r t c o n t r o l r e g i s t e r 0 h s y n c i n p u t p o l a r i t y s w i t c h b i t ( h s y c ) 0 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 10 : p o s i t i v e p o l a r i t y i n p u t 1 : n e g a t i v e p o l a r i t y i n p u t 0 2 r / g / b o u t p u t p o l a r i t y s w i t c h b i t ( r / g / b ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 30 4 o u t 1 o u t p u t p o l a r i t y s w i t c h b i t ( o u t 1 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t 0 5 r s i g n a l o u t p u t s w i t c h b i t ( o p 5 ) 0 : r s i g n a l o u t p u t 1 : m u t e s i g n a l o u t p u t 0 6 g s i g n a l o u t p u t s w i t c h b i t ( o p 6 ) 0 : g s i g n a l o u t p u t 1 : m u t e s i g n a l o u t p u t 0 7 b s i g n a l o u t p u t s w i t c h b i t ( o p 7 ) 0 : b s i g n a l o u t p u t 1 : m u t e s i g n a l o u t p u t 0 v s y n c i n p u t p o l a r i t y s w i t c h b i t ( v s y c ) r w r w r w r w r w r w r w r w o u t 2 o u t p u t p o l a r i t y s w i t c h b i t ( o u t 2 ) 0 : p o s i t i v e p o l a r i t y o u t p u t 1 : n e g a t i v e p o l a r i t y o u t p u t m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 104 of 110 rej03b0134-0100z address 00ed 16 addresses 00ee 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 o s d c l o c k s e l e c t i o n r e g i s t e r ( c k ) [ a d d r e s s 0 0 e d 1 6 ] b n a m e f u n c t i o n s a f t e r r e s e t r w o s d c l o c k s e l e c t i o n r e g i s t e r 0, 1 osd c l oc k selecti on bits (ck0,c k1) 0 s i n c e t h e m a i n c l o c k i s u s e d a s t h e c l o c k f o r d i s p l a y , t h e o s c i l l a t i o n f r e q u e n c y i s l i m i t e d . b e c a u s e o f t h i s , t h e c h a r a c t e r s i z e i n w i d t h ( h o r i z o n t a l ) d i r e c t i o n i s a l s o l i m i t e d . i n t h i s c a s e , p i n s o s c 1 a n d o s c 2 a r e a l s o u s e d a s i n p u t p o r t s p 3 3 a n d p 3 4 r e s p e c t i v e l y . t h e c l o c k f o r o s d i s s u p p l i e d b y c o n n e c t i n g t h e f o l l o w i n g a c r o s s t h e p i n s o s c 1 a n d o s c 2 . a c e r a m i c r e s o n a t o r o n l y f o r o s d a q u a r t z - c r y s t a l o s c i l l a t o r o n l y f o r o s d a n d a f e e d b a c k r e s i s t o r ( s e e n o t e ) 2 t o 7 0 0 0 0 0 0 0 b 1 t h e c l o c k f o r d i s p l a y i s s u p p l i e d b y c o n n e c t i n g r c o r l c a c r o s s t h e p i n s o s c 1 a n d o s c 2 . f unct i ons 00 b 0 osd osc ill at i on freq uency = f(x in ) o s d o s c i l l a t i o n f r e q u e n c y = f ( x i n ) / 1 . 5 n ote: i t i s necessary to connect ot h er ce ram i c resonator or quartz-crysta l osc ill ator f or osd acro ss t h e p ins x in an d x out . 0 0 1 1 1 1 fi x t h ese bi ts to 0. r w r w b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a-d c ontrol register 1 (ad1) [address 00ee 16 ] b a f t e r r e s e t rw a - d c o n t r o l r e g i s t e r 1 0 t o 2 a n a l o g i n p u t p i n s e l e c t i o n b i t s ( a d m 0 t o a d m 2 ) name f u n c t i o n s b 2 b 1 b 0 0 0 0 : a - d 1 0 0 1 : a - d 2 0 1 0 : a - d 3 0 1 1 : a - d 4 1 0 0 : a - d 5 1 0 1 : a - d 6 1 1 0 : d o n o t s e t 1 1 1 : d o n o t s e t 4 s t o r a g e b i t o f c o m p a r i s o n r e s u l t ( a d m 4 ) 0 : i n p u t v o l t a g e < r e f e r e n c e v o l t a g e 1 : i n p u t v o l t a g e > r e f e r e n c e v o l t a g e 0 i n d e t e r m i n a t e 0 3 t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . rw r r ? 0 5 to 7 n o t h i n g i s a s s i g n e d . t h i s b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . r ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 105 of 110 rej03b0134-0100z address 00ef 16 addresses 00f4 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 a - d c o n t r o l r e g i s t e r 2 ( a d 2 ) [ a d d r e s s 0 0 e f 1 6 ] b a f t e r r e s e t rw a - d c o n t r o l r e g i s t e r 2 0 to 5 6 , 7 0 0 n a m e f u n c t i o n s d - a c o n v e r t e r s e t b i t s ( a d c 0 t o a d c 5 ) b0 b1 b2 b3 b4 b 5 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e e d o u t , t h e v a l u e s a r e 0 . 1 000000 00000 0 0000 0 0 111 1 1 11111 1 111111 : 3/128 v cc : 5/128 v cc : 1 2 3 / 1 2 8 v c c : 1 2 5 / 1 2 8 v c c : 1 2 7 / 1 2 8 v c c : 1/128 v cc rw r ? b7 b6 b5 b4 b3 b2 b1 b0 timer mode register (t12m) [address 00f4 16 ] b a f t e r r e s e t w timer 12 mo de register 0 1 2 3 4 nam e functions timer 1 count source selection bit 1 (t12m0) 0: f(x in )/16 1: f(x in )/ 4096 timer 2 count source selection bit (t12m1) 0: interrupt clock source 1: external clock from tim2 pin timer 1 count stop bit (t12m2) 0: count start 1: count stop timer 2 count stop bit (t12m3) 0: count start 1: count stop timer 2 internal count source selection bit 2 (t12m4) r 0 0 0 0 0 w r w r w r w r w r 0: f(x in )/16 1: timer 1 overflow 5 fix this bit to 0. 0 w r 6 , 7n othing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0? r 0 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 106 of 110 rej03b0134-0100z address 00f5 16 addresses 00f9 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 t i m e r 3 4 m o d e r e g i s t e r ( t 3 4 m ) [ a d d r e s s 0 0 f 5 1 6 ] b a f t e r r e s e t rw t i m e r 3 4 m o d e r e g i s t e r 0 n a m e f u n c t i o n s t i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 0 ) 0 rw 1 timer 4 internal interrupt count source selection bit (t34m1) 0rw 2 3 t i m e r 3 c o u n t s t o p b i t ( t 3 4 m 2 ) 0: count start 1: count stop timer 4 count stop bit (t34m3) 0: count start 1: count stop 0 0 4 t i m e r 4 c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 4 ) 0: internal clock source 1: f(x in )/2 0 5 t i m e r 3 e x t e r n a l c o u n t s o u r c e s e l e c t i o n b i t ( t 3 4 m 5 ) 0 : t i m 3 p i n i n p u t 1 : h s y n c p i n i n p u t 0 rw rw rw rw 0 : f ( x i n ) / 1 6 1 : e x t e r n a l c l o c k s o u r c e 0 : t i m e r 3 o v e r f l o w s i g n a l 1 : f ( x i n ) / 1 6 6 , 7n othing is assigned. these bits are write disable bits. when these bits are read out, the values are 0. 0? r n a m ef u n c t i o n s i n t 1 p o l a r i t y s w i t c h b i t ( r e 3 ) 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y 0 : p o s i t i v e p o l a r i t y 1 : n e g a t i v e p o l a r i t y i n t 2 p o l a r i t y s w i t c h b i t ( r e 4 ) i n t 3 p o l a r i t y s w i t c h b i t ( r e 5 ) n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . fix these bits to 0. f i x t h i s b i t t o 0 . n o t h i n g i s a s s i g n e d . t h i s b i t i s a w r i t e d i s a b l e b i t . w h e n t h i s b i t i s r e a d o u t , t h e v a l u e i s 0 . after rese t r w 0 0 0 0 0 0 r ? r w r w r w r w r ? r w 0 b 7b 6b 5b 4b 3b 2b 1b 0 i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r ( r e ) [ a d d r e s s 0 0 f 9 1 6 ] b i n t e r r u p t i n p u t p o l a r i t y r e g i s t e r 0 1,2 3 4 5 6 7 0 00 m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 107 of 110 rej03b0134-0100z address 00fb 16 addresses 00fc 16 b a f t e r r e s e t rw 0 , 1 2 3 t o 7 i n d eterm i nate i n d eterm i nate name f u n c t i o n s f i x t h e s e b i t s t o 1 . 1 s t a c k p a g e s e l e c t i o n b i t ( c m 2 ) ( s e e n o t e ) 0: 0 page 1: 1 page c p u m o d e r e g i s t e r ( c m ) [ a d d r e s s 0 0 f b 1 6 ] r w rw r w n o t e : t h i s b i t i s s e t t o 1 a f t e r t h e r e s e t r e l e a s e . b 7b 6b 5 b4 b 3 b 2 b 1 b0 c p u m o d e r e g i s t e r 1 1 0 0 1 1 1 f i x t h e s e b i t s t o 0 . b 7 b 6 b 5 b 4 b 3 b 2 b 1 b0 i n t e r r u p t r e q u e s t r e g i s t e r 1 ( i r e q 1 ) [ a d d r e s s 0 0 f c bn a m e functions a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 1 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d t i m e r 1 i n t e r r u p t r e q u e s t b i t ( t m 1 r ) 1 timer 2 interrupt request bit (tm2r) 2 t i m e r 3 i n t e r r u p t r e q u e s t b i t ( t m 3 r ) 3t i m e r 4 i n t e r r u p t r e q u e s t b i t ( t m 4 r ) 4 osd interrupt request bit (crtr) 5 v s y n c i n t e r r u p t r e q u e s t b i t ( v s c r ) 6 m u l t i - m a s t e r i 2 c - b u s i n t e r f a c e i n t e r r u p t r e q u e s t b i t ( i i c r ) 7 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 0 ? ? ? ? ? ? ? ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 108 of 110 rej03b0134-0100z address 00fd 16 addresses 00fe 16 b 7b 6 b 5 b 4b 3 b 2 b 1 b0 i n t e r r u p t r e q u e s t r e g i s t e r 2 ( i r e q 2 ) [ a d d r e s s 0 0 f d bn a m e f u n c t i o n s a f t e r r e s e t rw i n t e r r u p t r e q u e s t r e g i s t e r 2 0 i n t 1 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 1 r ) 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 1 i n t 2 e x t e r n a l i n t e r r u p t r e q u e s t b i t ( i t 2 r ) 2 s e r i a l i / o i n t e r r u p t r e q u e s t b i t ( s 1 r ) 3 4 f ( x i n ) / 4 0 9 6 i n t e r r u p t r e q u e s t b i t ( m s r ) 5, 6 7 f i x t h i s b i t t o 0 . 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d 0 ? ? ? ? ? m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 109 of 110 rej03b0134-0100z address 00ff 16 addresses 021b 16 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b0 i n t e r r u p t c o n t r o l r e g i s t e r 2 ( i c o n 2 ) [ a d d r e s s 0 0 f f 1 6 ] bn a m ef u n c t i o n s i n t e r r u p t c o n t r o l r e g i s t e r 2 0 int1 external interrupt enable bit (it1e) 0 : interrupt disabled 1 : interrupt enabled 1 int2 external interrupt enable bit (it2e) 2 serial i/o interrupt enable bit (s1e) 3 4 f(x in )/ 4096 interrupt enable bit (mse) 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled fix this bit to 0. fix these bits to 0. 0 00 a f t e r r e s e t 0 0 0 0 0 0 rw rw rw rw rw r r w w 5 t o 7 0 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 r o m c o r r e c t i o n e n a b l e r e g i s t e r ( r c r ) [ a d d r e s s 0 2 1 b 1 6 ] bafter reset r o m c o r r e c t i o n e n a b l e r e g i s t e r 0 v ector 1 ena bl e bi t (rcr 0 ) n a m eunctions 0: di sa bl e d 1: enabl ed 1 v e c t o r 2 e n a b l e b i t ( r cr 1 ) 0: di sa bl e d 1: enabled 4 t o 7 n o t h i n g i s a s s i g n e d . t h e s e b i t s a r e w r i t e d i s a b l e b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e v a l u e s a r e 0 . 0 0 0 0 0 2 , 3 f i x t h e s e b i t s t o 0 . 0 rw rw rw r? rw f m37221m4h/m6h/m8h/mahexxxsp/fp m37221easp/fp rev.1.00 oct 01, 2002 page 110 of 110 rej03b0134-0100z 20. package outline sdip42-p-600-1.78 weigh t(g) jedec code 4.1 eiaj package code lead material alloy 42/cu alloy 42p4b plastic 42pin 600mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ?.8 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 ?. 778 15.24 3.0 0 ?5 5.5 e e 1 42 22 21 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d mmp ssop42-p-450-0.80 w eight(g) jedec code 0.63 eiaj package code lead material alloy 42 42p2r-a/e plastic 42pin 450mil ssop symbol min nom max a a 2 b c d e l l 1 y dimension in millimeters h e a 1 i 2 .25 0 .05 0 .13 0 .3 17 .2 8 .63 11 .3 0 .27 1 .0 2 .3 0 .15 0 .5 17 .4 8 .8 0 .93 11 .5 0 .765 1 .43 11 .4 2 .4 0 .2 0 .7 17 .6 8 .23 12 .7 0 .15 0 b 2 ?5 0 0 e10 e e 1 42 22 21 1 h e e d e y f a a 2 a 1 l 1 l c e b 2 e 1 i 2 recommended mount pad detail f z z 1 detail g e e z 1 0.75 e e 0.9 z b g revision history rev. date description page summary m37221m4h/m6h/m8h/mah?xxsp/fp m37221easp/fp 1.00 oct 01, 2002 first edition issued a - 1 keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is al ways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating i n the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents in formation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or e rrors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technolo gy corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under cir cumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materia ls. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. unit2607 ruijing building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices ? 200 4. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon .2.0 |
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