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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 2001 mos integrated circuit pd4481162, 4481182, 4481322, 4481362 8m-bit zerosb tm sram pipelined operation document no. m15562ej1v0ds00 (1st edition) date published june 2001 ns cp(k) printed in japan preliminary data sheet description the pd4481162 is a 524,288-word by 16-bit, the pd4481182 is a 524,288-word by 18-bit, the pd4481322 is a 262,144-word by 32-bit and the pd4481362 is a 262,144-word by 36-bit zerosb static ram fabricated with advanced cmos technology using full cmos six-transistor memory cell. the pd4481162, pd4481182, pd4481322 and pd4481362 are optimized to eliminate dead cycles for read to write, or write to read transitions. these zerosb static rams integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as sram core. all input registers are controlled by a positive edge of the single clock input (clk). the pd4481162, pd4481182, pd4481322 and pd4481362 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory. zz has to be set low at the normal operation. when zz is set high, the sram enters power down state (?sleep?). in the ?sleep? state, the sram internal state is preserved. when zz is set low again, the sram resumes normal operation. the pd4481162, pd4481182, pd4481322 and pd4481362 are packaged in 100-pin plastic lqfp with a 1.4 mm package thickness or 165-pin tape fbga for high density and low capacitive loading. features ? low voltage core supply (a version : v dd = 3.3 0.165v, c version : v dd = 2.5 0.125v) ? synchronous operation ? 100 percent bus utilization ? internally self-timed write control ? burst read / write : interleaved burst and linear burst sequence ? fully registered inputs and outputs for pipelined operation ? all registers triggered off positive clock edge ? 3.3v or 2.5v lvttl compatible : all inputs and outputs ? fast clock access time : 3.2 ns (200 mhz), 3.5 ns (167 mhz) , 4.2 ns (133 mhz) ? asynchronous output enable : /g ? burst sequence selectable : mode ? sleep mode : zz (zz = open or low : normal operation) ? separate byte write enable : /bw1 - /bw4 ( pd4481322 and pd4481362), /bw1 - /bw2 ( pd4481162 and pd4481182) ? three chip enables for easy depth expansion ? common i/o using three state outputs
2 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 ordering information (1/2) part number access time ns clock frequency mhz core supply voltage v i/o interface package pd4481162gf-a50 3.2 200 3.3 0.165 3.3 v or 2.5 v 100-pin plastic lqfp pd4481162gf-a60 3.5 167 lvttl (14 x 20) pd4481162gf-a75 4.2 133 pd4481182gf-a50 3.2 200 pd4481182gf-a60 3.5 167 pd4481182gf-a75 4.2 133 pd4481322gf-a50 3.2 200 pd4481322gf-a60 3.5 167 pd4481322gf-a75 4.2 133 pd4481362gf-a50 3.2 200 pd4481362gf-a60 3.5 167 pd4481362gf-a75 4.2 133 pd4481162gf-c50 3.2 200 2.5 0.125 2.5 v pd4481162gf-c60 3.5 167 lvttl pd4481162gf-c75 4.2 133 pd4481182gf-c50 3.2 200 pd4481182gf-c60 3.5 167 pd4481182gf-c75 4.2 133 pd4481322gf-c50 3.2 200 pd4481322gf-c60 3.5 167 pd4481322gf-c75 4.2 133 pd4481362gf-c50 3.2 200 pd4481362gf-c60 3.5 167 pd4481362gf-c75 4.2 133 pd4481162f9-a50-eqx 3.2 200 3.3 0.165 3.3 v or 2.5 v 165-pin tape fbga pd4481162f9-a60-eqx 3.5 167 lvttl (13 x 15) pd4481162f9-a75-eqx 4.2 133 pd4481182f9-a50-eqx 3.2 200 pd4481182f9-a60-eqx 3.5 167 pd4481182f9-a75-eqx 4.2 133 pd4481322f9-a50-eqx 3.2 200 pd4481322f9-a60-eqx 3.5 167 pd4481322f9-a75-eqx 4.2 133 pd4481362f9-a50-eqx 3.2 200 pd4481362f9-a60-eqx 3.5 167 pd4481362f9-a75-eqx 4.2 133 remark "eqx" of part number is package specifications. however, this is not available.
3 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 (2/2) part number access time ns clock frequency mhz core supply voltage v i/o interface package pd4481162f9-c50-eqx 3.2 200 2.5 0.125 2.5 v 165-pin tape fbga pd4481162f9-c60-eqx 3.5 167 lvttl (13 x 15) pd4481162f9-c75-eqx 4.2 133 pd4481182f9-c50-eqx 3.2 200 pd4481182f9-c60-eqx 3.5 167 pd4481182f9-c75-eqx 4.2 133 pd4481322f9-c50-eqx 3.2 200 pd4481322f9-c60-eqx 3.5 167 pd4481322f9-c75-eqx 4.2 133 pd4481362f9-c50-eqx 3.2 200 pd4481362f9-c60-eqx 3.5 167 pd4481362f9-c75-eqx 4.2 133 remark "eqx" of part number is package specifications. however, this is not available.
4 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 pin configurations (marking side) / indicates active low signal. 100-pin plastic lqfp (14 20) [ pd4481162gf, pd4481182gf] nc nc nc v dd q v ss q nc nc i/o9 i/o10 v ss q v dd q i/o11 i/o12 v dd v dd v dd v ss i/o13 i/o14 v dd q v ss q i/o15 i/o16 i/op2, nc nc v ss q v dd q nc nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 a18 nc nc v dd q v ss q nc i/op1, nc i/o8 i/o7 v ss q v dd q i/o6 i/o5 v ss v dd v dd zz i/o4 i/o3 v dd q v ss q i/o2 i/o1 nc nc v ss q v dd q nc nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a6 a7 /ce ce2 nc nc /bw2 /bw1 /ce2 v dd v ss clk /we /cke /g adv nc a17 a8 a9 mode a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc nc a10 a11 a12 a13 a14 a15 a16 remark refer to package drawings for 1-pin index mark.
5 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 pin identifications [ pd4481162gf, pd4481182gf] symbol pin no. description a0 - a18 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, synchronous address input 44, 45, 46, 47, 48, 49, 50, 83, 80 i/o1 - i/o16 58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, synchronous data in, 18, 19, 22, 23 synchronous / asynchronous data out i/op1, nc note 74 synchronous data in (parity), i/op2, nc note 24 synchronous / asynchronous data out (parity) adv 85 synchronous address load / advance input /ce, ce2, /ce2 98, 97, 92 synchronous chip enable input /we 88 synchronous write enable input /bw1, /bw2 93, 94 synchronous byte write enable input /g 86 asynchronous output enable input clk 89 clock input /cke 87 synchronous clock enable input mode 31 asynchronous burst sequence select input have to tied to v dd or v ss during normal operation zz 64 asynchronous power down state input v dd 14, 15, 16, 41, 65, 66, 91 power supply v ss 17, 40, 67, 90 ground v dd q 4, 11, 20, 27, 54, 61, 70, 77 output buffer power supply v ss q 5, 10, 21, 26, 55, 60, 71, 76 output buffer ground nc 1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, no connection 51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96 note nc (no connection) is used in the pd4481162gf. i/op1 - i/op2 are used in the pd4481182gf.
6 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 100-pin plastic lqfp (14 20) [ pd4481322gf, pd4481362gf] i/op3, nc i/o17 i/o18 v dd q v ss q i/o19 i/o20 i/o21 i/o22 v ss q v dd q i/o23 i/o24 v dd v dd v dd v ss i/o25 i/o26 v dd q v ss q i/o27 i/o28 i/o29 i/o30 v ss q v dd q i/o31 i/o32 i/op4, nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/op2, nc i/o16 i/o15 v dd q v ss q i/o14 i/o13 i/o12 i/o11 v ss q v dd q i/o10 i/o9 v ss v dd v dd zz i/o8 i/o7 v dd q v ss q i/o6 i/o5 i/o4 i/o3 v ss q v dd q i/o2 i/o1 i/op1, nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 a6 a7 /ce ce2 /bw4 /bw3 /bw2 /bw1 /ce2 v dd v ss clk /we /cke /g adv nc a17 a8 a9 mode a5 a4 a3 a2 a1 a0 nc nc v ss v dd nc nc a10 a11 a12 a13 a14 a15 a16 remark refer to package drawings for 1-pin index mark.
7 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 [ pd4481322gf, pd4481362gf] symbol pin no. description a0 - a17 37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, synchronous address input 45, 46, 47, 48, 49, 50, 83 i/o1 - i/o32 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, synchronous data in, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, synchronous / asynchronous data out 18, 19, 22, 23, 24, 25, 28, 29 i/op1, nc note 51 synchronous data in (parity), i/op2, nc note 80 synchronous / asynchronous data out (parity) i/op3, nc note 1 i/op4, nc note 30 adv 85 synchronous address load / advance input /ce, ce2, /ce2 98, 97, 92 synchronous chip enable input /we 88 synchronous write enable input /bw1 - /bw4 93, 94, 95, 96 synchronous byte write enable input /g 86 asynchronous output enable input clk 89 clock input /cke 87 synchronous clock enable input mode 31 asynchronous burst sequence select input have to tied to v dd or v ss during normal operation zz 64 asynchronous power down state input v dd 14, 15, 16, 41, 65, 66, 91 power supply v ss 17, 40, 67, 90 ground v dd q 4, 11, 20, 27, 54, 61, 70, 77 output buffer power supply v ss q 5, 10, 21, 26, 55, 60, 71, 76 output buffer ground nc 38, 39, 42, 43, 84 no connection note nc (no connection) is used in the pd4481322gf. i/op1 - i/op4 are used in the pd4481362gf.
8 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 165-pin tape fbga [ pd4481162f9-eqx, pd4481182f9-eqx] top view 1234567891011 a nc a7 /ce /bw2 nc /ce2 /cke adv a17 a8 a18 b nc a6 ce2 nc /bw1 clk /we /g nc a9 nc cncncv dd qv ss v ss v ss v ss v ss v dd q nc i/op1 d nc i/o9 v dd qv dd v ss v ss v ss v dd v dd q nc i/o8 e nc i/o10 v dd qv dd v ss v ss v ss v dd v dd q nc i/o7 f nc i/o11 v dd qv dd v ss v ss v ss v dd v dd q nc i/o6 g nc i/o12 v dd qv dd v ss v ss v ss v dd v dd q nc i/o5 hncv dd nc v dd v ss v ss v ss v dd nc nc zz j i/o13 nc v dd qv dd v ss v ss v ss v dd v dd q i/o4 nc k i/o14 nc v dd qv dd v ss v ss v ss v dd v dd q i/o3 nc l i/o15 nc v dd qv dd v ss v ss v ss v dd v dd q i/o2 nc m i/o16 nc v dd qv dd v ss v ss v ss v dd v dd q i/o1 nc n i/op2 nc v dd qv ss nc nc v dd v ss v dd qnc nc p nc nc a5 a2 tdi a1 tdo a10 a13 a14 nc r mode nc a4 a3 tms a0 tck a11 a12 a15 a16
9 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 [ pd4481162f9-eqx, pd4481182f9-eqx] symbol pin no. description a0 - a18 6r, 6p, 4p, 4r, 3r, 3p, 2b, 2a, 10a, 10b, 8p, 8r, 9r, 9p, 10p, 10r, 11r, 9a, 11a synchronous address input i/o1 - i/o16 10m, 10l, 10k, 10j, 11g, 11f, 11e, 11d, 2d, 2e, 2f, 2g, 1j, 1k, 1l, 1m synchronous data in, synchronous / asynchronous data out i/op1, nc note 11c synchronous data in (parity), i/op2, nc note 1n synchronous / asynchronous data out (parity) adv 8a synchronous address load / advance input /ce, ce2, /ce2 3a, 3b, 6a synchronous chip enable input /we 4h synchronous write enable input /bw1, /bw2 5b, 4a synchronous byte write enable input /g 8b asynchronous output enable input clk 6b clock input /cke 7a synchronous clock enable input mode 1r asynchronous burst sequence select input have to tied to v dd or v ss during normal operation zz 11h asynchronous power down state input v dd 2h, 4d, 4e, 4f, 4g, 4h, 4j, 4k, 4l, 4m, 7n, 8d, 8e, 8f, 8g, 8h, 8j, 8k, 8l, 8m power supply v ss 4c, 4n, 5c, 5d, 5e, 5f, 5g, 5h, 5j, 5k, 5l, 5m, 6c, 6d, 6e, 6f, 6g, 6h, 6j, 6k, 6l, 6m, 7c, 7d, 7e, 7f, 7g, 7h, 7j, 7k, 7l, 7m, 8c, 8n ground v dd q 3c, 3d, 3e, 3f, 3g, 3j, 3k, 3l, 3m, 3n, 9c, 9d, 9e, 9f, 9g, 9j, 9k, 9l, 9m, 9n output buffer power supply nc 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1p, 2c, 2j, 2k, 2l, 2m, 2n, 2p, 2r, 3h, 4b, 5a, 5n, 6n, 9b, 9h, 10c, 10d, 10e, 10f, 10g, 10h, 10n, 11b, 11j, 11k, 11l, 11m, 11n, 11p no connection tms 5r test mode select (jtag) tdi 5p test data input (jtag) tck 7r test clock input (jtag) tdo 7p test data output (jtag) note nc (no connection) is used in the pd4481162f9-eqx. i/op1 - i/op2 are used in the pd4481182f9-eqx .
10 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 165-pin tape fbga [ pd4481322f9-eqx, pd4481362f9-eqx] top view 1234567891011 a nc a7 /ce /bw3 /bw2 /ce2 /cke adv a17 a8 nc b nc a6 ce2 /bw4 /bw1 clk /we /g nc a9 nc c i/op3 nc v dd qv ss v ss v ss v ss v ss v dd q nc i/op2 d i/o18 i/o17 v dd qv dd v ss v ss v ss v dd v dd q i/o16 i/o15 e i/o20 i/o19 v dd qv dd v ss v ss v ss v dd v dd q i/o14 i/o13 f i/o22 i/o21 v dd qv dd v ss v ss v ss v dd v dd q i/o12 i/o11 g i/o24 i/o23 v dd qv dd v ss v ss v ss v dd v dd q i/o10 i/o9 h nc v dd nc v dd v ss v ss v ss v dd nc nc zz j i/o26 i/o25 v dd qv dd v ss v ss v ss v dd v dd q i/o8 i/o7 k i/o28 i/o27 v dd qv dd v ss v ss v ss v dd v dd q i/o6 i/o5 l i/o30 i/o29 v dd qv dd v ss v ss v ss v dd v dd q i/o4 i/o3 m i/o32 i/o31 v dd qv dd v ss v ss v ss v dd v dd q i/o2 i/o1 n i/op4 nc v dd qv ss nc nc v dd v ss v dd q nc i/op1 p nc nc a5 a2 tdi a1 tdo a10 a13 a14 nc r mode nc a4 a3 tms a0 tck a11 a12 a15 a16
11 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 [ pd4481322f9-eqx, pd4481362f9-eqx] symbol pin no. description a0 - a17 6r, 6p, 4p, 4r, 3r, 3p, 2b, 2a, 10a, 10b, 8p, 8r, 9r, 9p, 10p, 10r, 11r, 9a synchronous address input i/o1 - i/o32 11m, 10m, 11l, 10l, 11k, 10k, 11j, 10j, 11g, 10g, 11f, 10f, 11e, 10e, 11d, 10d, 2d, 1d, 2e, 1e, 2f, 1f, 2g, 1g, 2j, 1j, 2k, 1k, 2l, 1l, 2m, 1m synchronous data in, synchronous / asynchronous data out i/op1, nc note 11n synchronous data in (parity), i/op2, nc note 11c synchronous / asynchronous data out (parity) i/op3, nc note 1c i/op4, nc note 1n adv 8a synchronous address load / advance input /ce, ce2, /ce2 3a, 3b, 6a synchronous chip enable input /we 7b synchronous write enable input /bw1 - /bw4 5b, 5a, 4a, 4b synchronous byte write enable input /g 8b asynchronous output enable input clk 6b clock input /cke 7a synchronous clock enable input mode 1r asynchronous burst sequence select input have to tied to v dd or v ss during normal operation zz 11h asynchronous power down state input v dd 2h, 4d, 4e, 4f, 4g, 4h, 4j, 4k, 4l, 4m, 7n, 8d, 8e, 8f, 8g, 8h, 8j, 8k, 8l, 8m power supply v ss 4c, 4n, 5c, 5d, 5e, 5f, 5g, 5h, 5j, 5k, 5l, 5m, 6c, 6d, 6e, 6f, 6g, 6h, 6j, 6k, 6l, 6m, 7c, 7d, 7e, 7f, 7g, 7h, 7j, 7k, 7l, 7m, 8c, 8n ground v dd q 3c, 3d, 3e, 3f, 3g, 3j, 3k, 3l, 3m, 3n, 9c, 9d, 9e, 9f, 9g, 9j, 9k, 9l, 9m, 9n output buffer power supply nc 1a, 1b, 1h, 1p, 2c, 2n, 2p, 2r, 3h, 5n, 6n, 9b, 9h, 10c, 10h, 10n, 11a, 11b, 11p no connection tms 5r test mode select (jtag) tdi 5p test data input (jtag) tck 7r test clock input (jtag) tdo 7p test data output (jtag) note nc (no connection) is used in the pd4481322f9-eqx. i/op1 - i/op4 are used in the pd4481362f9-eqx.
12 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 block diagrams [ pd4481162, pd4481182] a0 - a18 mode clk /cke adv /bw1 /bw2 /we /g /ce ce2 /ce2 address register 0 burst logic write address register 0 write registry and data coherency control logic write drivers data steering adv k a1 a0 a1 a0 sense amplifiers read logic input register 0 e output buffers e i/o1 - i/o16 i/op1, i/op2 19 17 19 19 19 16/18 16/18 16/18 16/18 write address register 1 output registers e input register 1 e 16/18 zz power down control k memory cell array 512 x 16 columns (8,388,608 bits) 512 x 18 columns (9,437,184 bits) 1,024 rows burst sequence [ pd4481162, pd4481182] interleaved burst sequence table (mode = open or v dd ) external address a18 - a2, a1, a0 1st burst address a18 - a2, a1, /a0 2nd burst address a18 - a2, /a1, a0 3rd burst address a18 - a2, /a1, /a0 linear burst sequence table (mode = v ss ) external address a18 - a2, 0, 0 a18 - a2, 0, 1 a18 - a2, 1, 0 a18 - a2, 1, 1 1st burst address a18 - a2, 0, 1 a18 - a2, 1, 0 a18 - a2, 1, 1 a18 - a2, 0, 0 2nd burst address a18 - a2, 1, 0 a18 - a2, 1, 1 a18 - a2, 0, 0 a18 - a2, 0, 1 3rd burst address a18 - a2, 1, 1 a18 - a2, 0, 0 a18 - a2, 0, 1 a18 - a2, 1, 0
13 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 [ pd4481322, pd4481362] a0 - a17 mode clk /cke adv /bw1 /bw2 /we /g /ce ce2 /ce2 address register 0 burst logic write address register 0 write registry and data coherency control logic write drivers data steering adv k a1 a0 a1 a0 sense amplifiers read logic input register 0 e output buffers e i/o1 - i/o32 i/op1 - i/op4 18 16 18 18 18 32/36 32/36 32/36 32/36 write address register 1 output registers e input register 1 e 32/36 /bw3 /bw4 zz power down control k memory cell array 256 x 32 columns (8,388,608 bits) 256 x 36 columns (9,437,184 bits) 1,024 rows [ pd4481322, pd4481362] interleaved burst sequence table (mode = open or v dd ) external address a17 - a2, a1, a0 1st burst address a17 - a2, a1, /a0 2nd burst address a17 - a2, /a1, a0 3rd burst address a17 - a2, /a1, /a0 linear burst sequence table (mode = v ss ) external address a17 - a2, 0, 0 a17 - a2, 0, 1 a17 - a2, 1, 0 a17 - a2, 1, 1 1st burst address a17 - a2, 0, 1 a17 - a2, 1, 0 a17 - a2, 1, 1 a17 - a2, 0, 0 2nd burst address a17 - a2, 1, 0 a17 - a2, 1, 1 a17 - a2, 0, 0 a17 - a2, 0, 1 3rd burst address a17 - a2, 1, 1 a17 - a2, 0, 0 a17 - a2, 0, 1 a17 - a2, 1, 0
14 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 state diagram deselect begin read burst read begin write burst write write read read ds ds write read burst burst write read write read burst write burst ds burst ds ds command operation ds deselect read new read write new write burst burst read, burst write or continue deselect remarks 1. states change on the rising edge of the clock. 2. a stall of ignore clock edge cycle is not shown in the above diagram. this is because /cke high only blocks the clock (clk) input and does not change the state of the device.
15 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 asynchronous truth table operation /g i/o read cycle l data-out read cycle h hi-z write cycle hi-z, data-in deselected hi-z remark : don ? t care synchronous truth table operation /ce ce2 /ce2 adv /we /bws /cke clk i/o address note deselected h l ll h hi-z none 1 deselected l l ll h hi-z none 1 deselected hl ll h hi-z none 1 continue deselected h ll h hi-z none 1 read cycle / begin burst l h l l h ll h data-out external read cycle / continue burst h ll h data-out next write cycle / begin burst lhllllll h data-in external write cycle / continue burst h lll h data-in next write cycle / write abort l h l l l h l l h hi-z external write cycle / write abort h hll hhi-z next stall / ignore clock edge hl h ? current 2 notes 1. deselect status is held until new ? begin burst ? entry. 2. if an ignore clock edge command occurs during a read operation, the i/o bus will remain active (low-z). if it occurs during a write cycle, the bus will remain hi-z. no write operation will be performed during the ignore clock edge cycle. remarks 1. : don ? t care 2. /bws = l means any one or more byte write enables (/bw1, /bw2, /bw3 or /bw4) are low. /bws = h means all byte write enables (/bw1, /bw2, /bw3 or /bw4) are high.
16 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 partial truth table for write enables [ pd4481162, pd4481182] operation /we /bw1 /bw2 read cycle h write cycle / byte 1 (i/o [1:8], i/op1) l l h write cycle / byte 2 (i/o [9:16], i/op2) l h l write cycle / all bytes l l l write abort / nop l h h remark : don ? t care [ pd4481322, pd4481362] operation /we /bw1 /bw2 /bw3 /bw4 read cycle h write cycle / byte 1 (i/o [1:8], i/op1) l l h h h write cycle / byte 2 (i/o [9:16], i/op2) l h l h h write cycle / byte 3 (i/o [17:24], i/op3) l h h l h write cycle / byte 4 (i/o [25:32], i/op4) l h h h l write cycle / all bytes lllll write abort / nop l h h h h remark : don ? t care zz (sleep) truth table zz chip status 0.2 v active open active v dd ? 0.2 v sleep
17 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 electrical specifications absolute maximum ratings parameter symbol conditions min. typ. max. unit supply voltage for a version v dd ? 0.5 +4.0 v for c version ? 0.5 +3.0 output supply voltage v dd q ? 0.5 v dd v input voltage v in ? 0.5 note v dd + 0.5 v input / output voltage v i/o ? 0.5 note v dd q + 0.5 v operating ambient temperature t a 070 c storage temperature t stg ? 55 +125 c note ? 2.0 v (min.) (pulse width : 2 ns) caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (t a = 0 to 70 c) for a version [ pd4481162-axx, pd4481182-axx, pd4481322-axx, pd4481362-axx] parameter symbol conditions min. typ. max. unit supply voltage v dd 3.135 3.3 3.465 v 2.5 v lvttl interface output supply voltage v dd q 2.375 2.5 2.9 v high level input voltage v ih 1.7 v dd q + 0.3 v low level input voltage v il ? 0.3 note +0.7 v 3.3 v lvttl interface output supply voltage v dd q 3.135 3.3 3.465 v high level input voltage v ih 2.0 v dd q + 0.3 v low level input voltage v il ? 0.3 note +0.8 v note ? 0.8 v (min.) (pulse width : 2 ns) for c version [ pd4481162-cxx, pd4481182-cxx, pd4481322-cxx, pd4481362-cxx] parameter symbol conditions min. typ. max. unit supply voltage v dd 2.375 2.5 2.625 v output supply voltage v dd q 2.375 2.5 2.625 v high level input voltage v ih 1.7 v dd q + 0.3 v low level input voltage v il ? 0.3 note +0.7 v note ? 0.8 v (min.) (pulse width : 2 ns)
18 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 dc characteristics (t a = 0 to 70c, v dd = 3.3 0.165 v or 2.5 0.125 v) parameter symbol test condition min. typ. max. unit input leakage current i li v in (except zz, mode) = 0 v to v dd ? 2+2 a i/o leakage current i lo v i/o = 0 v to v dd q, outputs are disabled. ? 2+2 a operating supply current i dd device selected, cycle = max. -a50, -c50 400 ma v in v il or v in v ih , -a60, -c60 350 i i/o = 0 ma -a75, -c75 300 standby supply current i sb device deselected, cycle = 0 mhz, tbd ma v in v il or v in v ih , all inputs are static. i sb1 device deselected, cycle = 0 mhz, tbd v in 0.2 v or v in v dd ? 0.2 v, v i/o 0.2 v, all inputs are static. i sb2 device deselected, cycle = max. 130 v in v il or v in v ih power down supply current i sbzz zz v dd ? 0.2 v, v i/o v dd q + 0.2 v tbd ma 2.5 v lvttl interface high level output voltage v oh i oh = ? 2.0 ma 1.7 v i ol = ? 1.0 ma 2.1 low level output voltage v ol i oh = +2.0 ma 0.7 v i ol = +1.0 ma 0.4 3.3 v lvttl interface high level output voltage v oh i oh = ? 4.0 ma 2.4 v low level output voltage v ol i ol = +8.0 ma 0.4 v capacitance (t a = 25 c, f = 1mhz) parameter symbol test condition min. typ. max. unit input capacitance c in v in = 0 v 5.0 pf input / output capacitance c i/o v i/o = 0 v 8.0 pf clock input capacitance c clk v clk = 0 v 6.0 pf remark these parameters are not 100 % tested.
19 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 ac characteristics (t a = 0 to 70c, v dd = 3.3 0.165 v or 2.5 0.125 v) ac test conditions 2.5 v lvttl interface input waveform (rise / fall time 2.4 ns) test points v ss 2.4 v v ddq /2 v ddq /2 output waveform test points v ddq /2 v ddq /2 3.3 v lvttl interface input waveform (rise / fall time 3.0 ns) test points v ss 3.0 v 1.5 v 1.5 v output waveform test points 1.5 v 1.5 v output load condition c l : 30 pf 5 pf (tkhqx1, tkhqx2, tglqx, tghqz, tkhqz) figure external load at test v t = +1.2 v / +1.5 v i/o (output) 50 ? z o = 50 ? c l remark c l includes capacitances of the probe and jig, and stray capacitances.
20 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 read and write cycle parameter symbol -a50, -c50 -a60, -c60 -a75, -c75 unit notes (200 mhz) (167 mhz) (133 mhz) standard alias min. max. min. max. min. max. cycle time tkhkh tcyc 5 ? 6 ? 7.5 ? ns clock access time tkhqv tcd ? 3.2 ? 3.5 ? 4.2 ns output enable access time tglqv toe ? 3.2 ? 3.5 ? 4.2 ns clock high to output active tkhqx1 tdc1 1.5 ? 1.5 ? 1.5 ? ns 1, 2 clock high to output change tkhqx2 tdc2 1.5 ? 1.5 ? 1.5 ? ns output enable to output active tglqx tolz 0 ? 0 ? 0 ? ns 1 output disable to output hi-z tghqz tohz 03.203.504.2 ns 1 clock high to output hi-z tkhqz tcz 1.5 3.2 1.5 3.5 1.5 3.5 ns 1, 2 clock high pulse width tkhkl tch 1.8 ? 1.8 ? 2.2 ? ns clock low pulse width tklkh tcl 1.8 ? 1.8 ? 2.2 ? ns setup times address tavkh tas 1.5 ? 1.5 ? 1.5 ? ns address status tadsvkh tss data in tdvkh tds write enable twvkh tws address advance tadvvkh ? chip enable tevkh ? hold times address tkhax tah 0.5 ? 0.5 ? 0.5 ? ns address status tkhadsx tsh data in tkhdx tdh write enable tkhwx twh address advance tkhadvx ? chip enable tkhex ? power down entry time tzze tzze 10 ? 12 ? 15 ? ns power down recovery time tzzr tzzr 10 ? 12 ? 15 ? ns notes 1. transition is measured 200 mv from steady state. 2. to avoid bus contention, the output buffers are designed such that tkhqz (device turn-off) is faster than tkhqx1 (device turn-on) at a given temperature and voltage. the specs as shown do not imply bus contention because tkhqx1 is a min. parameter that is worse case at totally different conditions (0 c, v dd max.) than tkhqz, which is a max. parameter (worse case at 70 c, v dd min.).
21 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 read / write cycle write d (a1) clk /cke /ces adv /we data in data out /g /bws address command 12345678910 d (a1) d (a2) d (a2+1) d (a5) q (a3) q (a4) q (a4+1) q (a6) write d (a2) burst write d (a2+1) read q (a3) read q (a4) burst read q (a4+1) write d (a5) read q (a6) write q (a7) deselect tkhkh tevkh tkhex tcvkh tkhcx tkhkl tklkh tdvkh tkhdx tkhqx1 tkhqv tkhqx2 tghqz tglqx tkhqx2 tglqv tkhqz tadvvkh tkhadvx twvkh tkhwx twvkh tkhwx note 1 note 2 a2 a7 tavkh tkhax a1 a3 a4 a5 a6 notes 1. /ces refers to /ce, ce2 and /ce2. when /ces is low, /ce and /ce2 are low and ce2 is high. when /ces is high, /ce and /ce2 are high and ce2 is low. 2. /bws refers to /bw1, /bw2, /bw3 and /bw4. when /bws is low, any one or more byte write enables (/bw1, /bw2, /bw3 or /bw4) are low.
22 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 nop, stall and deselect cycle 12345678910 write d (a1) clk /cke /ces adv /we data in data out /bws address command d (a1) d (a4) q (a2) q (a3) q (a5) read q (a2) stall read q (a3) write d (a4) stall nop read q (a5) deselect continue deselect tkhqx2 tkhqz a2 a1 a3 a4 a5
23 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 power down (zz) cycle 12345678910 clk /cke adv /we /g data out address q (a1) 11 12 q1 (a2) zz tkhkh tkhkl tzzeh tzzes tzzrh tzzrs power down (i sbzz ) state a1 a2 /ces note /bws note tklkh note /we or /ces must be held high at clk rising edge (clock edge no.2 and no.3 in this figure) prior to power down state entry.
24 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 jtag specification the pd4481162, pd4481182, pd4481322 and pd4481362 support a limited set of jtag functions as in ieee standard 1149.1. test access port (tap) pins pin name description tck test clock input. all input are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms test mode select. this is the command input for the tap controller state machine. tdi test data input. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is deter-mined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction. tdo test data output. output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. remark the device does not have trst (tap reset). the test-logic reset state is entered while tms is held high for five rising edges of tck. the tap controller state is also reset on the sram power-up. jtag dc characteristics (t j = 0 to 70 c) parameter symbol conditions min. typ. max. unit note jtag input high voltage v ih 2.0 v dd + 0.3 v jtag input low voltage v il ? 0.3 +0.8 v jtag output high voltage v oh i oh = ? 8 ma 2.4 ? v jtag output low voltage v ol i ol = 8 ma ? 0.4 v
25 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 jtag ac test conditions (t j = 0 to 70 c) input waveform (rise / fall time = 1 ns (20 to 80 %)) test points 1.5 v 1.5 v 0 v 3.0 v output waveform test points 1.5 v 1.5 v output load (v tt =1.5 v) tdo z o = 50 ? v tt 50 ?
26 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 jtag ac characteristics (t j = 0 to 70 c) parameter symbol conditions min. typ. max. unit note clock cycle time (tck) t thth 100 ? ns clock phase time (tck) t thtl / t tlth 40 ? ns setup time (tms / tdi) t mvth / t dvth 10 ? ns hold time (tms / tdi) t thmx / t thdx 10 ? ns tck low to tdo valid (tdo) t tlqv ? 20 ns jtag timing diagram t thth t tlqv t tlth t thtl t mvth t thdx t dvth t thmx tck tms tdi tdo
27 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 scan register definition (1) register name description instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run-test/idle or the various data register state. the register can be loaded when it is placed between the tdi and tdo pins. the instruction register is automatically preloaded with the idcode instruction at power-up whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the rams tap to another device in the scan chain with as little delay as possible. id register the id register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction register. the register is then placed between the tdi and tdo pins when the controller is moved into shift-dr state. boundary register the boundary register, under the control of the tap controller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. several tap instructions can be used to activate the boundary register. the scan exit order tables describe which device bump connects to each boundary register location. the first column defines the bit ? s position in the boundary register. the shift register bit nearest tdo (i.e., first to be shifted out) is defined as bit 1. the second column is the name of the input or i/o at the bump and the third column is the bump number. scan register definition (2) register name 512k x 16/18 256k x 16/18 unit instruction register 3 3 bit bypass register 1 1 bit id register 32 32 bit boundary register 51 70 bit id register definition part number organization id [31:28] vendor revision no. id [27:12] part no. id [11:1] vendor id no. id [0] fix bit pd4481162 512k x 16 xxxx 0000 0000 0000 1000 00000010000 1 pd4481182 512k x 18 xxxx 0000 0000 0000 1001 00000010000 1 pd4481322 256k x 16 xxxx 0000 0000 0000 1010 00000010000 1 pd4481362 256k x 18 xxxx 0000 0000 0000 1011 00000010000 1
28 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 scan exit order [ pd4481162f9-eqx / pd4481182f9-eqx (512k words by 16/18 bits)] bit no. signal name bump id bit no. signal name bump id 1 a10 tbd 26 /we tbd 2 a11 tbd 27 clk tbd 3a12 tbd 28/ce2 tbd 4a13 tbd 29/bw1 tbd 5a14 tbd 30/bw2 tbd 6 a15 tbd 31 ce2 tbd 7 a16 tbd 32 /ce tbd 8 i/o tbd 33 a7 tbd 9 i/o tbd 34 a6 tbd 10 i/o tbd 35 i/o tbd 11 i/o tbd 36 i/o tbd 12 zz tbd 37 i/o tbd 13 i/o tbd 38 i/o tbd 14 i/o tbd 39 nc tbd 15 i/o tbd 40 i/o tbd 16 i/o tbd 41 i/o tbd 17 i/o tbd 42 i/o tbd 18 a18 tbd 43 i/o tbd 19 a9 tbd 44 i/o tbd 20 a8 tbd 45 mode tbd 21 a17 tbd 46 a5 tbd 22 nc tbd 47 a4 tbd 23 adv tbd 48 a3 tbd 24 /g tbd 49 a2 tbd 25 /cke tbd 50 a1 tbd 51 a0 tbd
29 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 [ pd4481322f9-eqx / pd4481362f9-eqx (256k words by 32/36 bits)] bit no. signal name bump id bit no. signal name bump id 1a10 tbd 36/ce2 tbd 2a11 tbd 37/bw1 tbd 3a12 tbd 38/bw2 tbd 4a13 tbd 39/bw3 tbd 5a14 tbd 40/bw4 tbd 6 a15 tbd 41 ce2 tbd 7 a16 tbd 42 /ce tbd 8 i/o tbd 43 a7 tbd 9 i/o tbd 44 a6 tbd 10 i/o tbd 45 i/o tbd 11 i/o tbd 46 i/o tbd 12 i/o tbd 47 i/o tbd 13 i/o tbd 48 i/o tbd 14 i/o tbd 49 i/o tbd 15 i/o tbd 50 i/o tbd 16 i/o tbd 51 i/o tbd 17 zz tbd 52 i/o tbd 18 i/o tbd 53 i/o tbd 19 i/o tbd 54 nc tbd 20 i/o tbd 55 i/o tbd 21 i/o tbd 56 i/o tbd 22 i/o tbd 57 i/o tbd 23 i/o tbd 58 i/o tbd 24 i/o tbd 59 i/o tbd 25 i/o tbd 60 i/o tbd 26 i/o tbd 61 i/o tbd 27 a9 tbd 62 i/o tbd 28 a8 tbd 63 i/o tbd 29 a17 tbd 64 mode tbd 30 nc tbd 65 a5 tbd 31 adv tbd 66 a4 tbd 32 /g tbd 67 a3 tbd 33 /cke tbd 68 a2 tbd 34 /we tbd 69 a1 tbd 35 clk tbd 70 a0 tbd
30 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 jtag instructions instructions description extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic 0s. extest is not implemented in this device. therefore this device is not 1149.1 compliant. nevertheless, this rams tap does respond to an all zeros instruction, as follows. with the extest (000) instruction loaded in the instruction register the ram responds just as it does in response to the sample instruction, except the ram output are forced to hi-z any time the instruction is loaded. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capture-dr mode and places the id register between the tdi and tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. bypass the bypass instruction is loaded in the instruction register when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample sample is a standard 1149.1 mandatory public instruction. when the sample instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e., in a metastable state). although allowing the tap to sample metastable input will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture setup plus hold time (t cs plus t ch ). the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo pins. this functionality is not standard 1149.1 compliant. sample-z if the sample-z instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (hi-z) and the boundary register is connected between tdi and tdo when the tap controller is moved to the shift-dr state. jtag instruction cording ir2 ir1 ir0 instruction note 0 0 0 extest 1 0 0 1 idcode 0 1 0 sample-z 1 0 1 1 bypass 1 0 0 sample 1 0 1 bypass 1 1 0 bypass 1 1 1 bypass note 1. tristate all data drivers and capture the pad values into a serial scan latch.
31 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 tap controller state diagram test-logic-reset run-test / idle select-dr-scan capture-dr capture-ir shift-dr exit1-dr pause-dr exit2-dr update-dr update-ir exit2-ir pause-ir exit1-ir shift-ir select-ir-scan 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 0 0 10 10 11 1 0 1 1 0 1 0 11 disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude mid level inputs. tdi and tms are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a 1k resistor. tdo should be left unconnected.
32 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 test logic operation (instruction scan) tck controller state tdi tms tdo test-logic-reset run-test/idle select-dr-scan select-ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir shift-ir exit1-ir update-ir run-test/idle idcode instruction register state new instruction output inactive output from instruction register output from instruction register
33 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 test logic operation (data scan) tck controller state tdi tms tdo run-test/idle select-dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr shift-dr exit1-dr update-dr test-logic-reset instruction instruction register state idcode output inactive output from instruction register output from instruction register run-test/idle select-dr-scan select-ir-scan
34 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 package drawings 100-pin plastic lqfp (14x20) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 22.0 0.2 20.0 0.2 0.65 (t.p.) 0.575 j 16.0 0.2 k c 14.0 0.2 i 0.13 1.0 0.2 l 0.5 0.2 f 0.825 n p q 0.10 1.4 0.125 0.075 s100gf-65-8et-1 s 1.7 max. h 0.32 + 0.08 ? 0.07 m 0.17 + 0.06 ? 0.05 r3 + 7 ? 3 m 80 81 51 50 30 31 100 1 s s n j detail of lead end c d a b r k m l p i s q g f h
35 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 165-pin tape fbga (13x15) tbd
36 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 recommended soldering condition please consult with our sales offices for soldering conditions of the pd4481162, 4481182, 4481322 and 4481362. types of surface mount devices pd4481162gf : 100-pin plastic lqfp (14 x 20) pd4481182gf : 100-pin plastic lqfp (14 x 20) pd4481322gf : 100-pin plastic lqfp (14 x 20) pd4481362gf : 100-pin plastic lqfp (14 x 20) pd4481162f9-eqx : 165-pin tape fbga (13 x 15) pd4481182f9-eqx : 165-pin tape fbga (13 x 15) pd4481322f9-eqx : 165-pin tape fbga (13 x 15) pd4481362f9-eqx : 165-pin tape fbga (13 x 15)
37 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 [memo]
38 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 [memo]
39 preliminary data sheet m15562ej1v0ds pd4481162, 4481182, 4481322, 4481362 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd4481162, 4481182, 4481322, 4481362 zerosb is a trademark of nec corporation. m8e 00. 4 the information in this document is current as of june, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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