View RH1020-CQ84V_6855517.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

april 2005 i ? 2005 actel corporation see the actel website for the latest version of the datasheet. v3.1 radiation-hardened fpgas features ? guaranteed total dose radiation capability ? low single event upset susceptibility ? high dose rate survivability ? latch-up immunity guaranteed ? qml qualified devices ? commercial devices available for prototyping and pre-production requirements ? gate capacities of 2,000 and 8,000 gate array gates ? more design flexibilit y than custom asics ? significantly greater dens ities than discrete logic devices ? replaces up to 200 ttl packages ? design library with over 500 macro functions ? single-module sequential functions ? wide-input combin atorial functions ? up to two high-speed, low-skew clock networks ? two in-circuit diagnostic probe pins support speed analysis to 50 mhz ? non-volatile, user programmable devices ? fabricated in 0.8 epitaxial bulk cmos process ? unique in-system diagnostic and verification capability with silicon explorer product family profile device rh1020 rh1280 capacity system gates gate array equivalent gates pld equivalent gates ttl equivalent packages 20-pin pal equivalent packages 3,000 2,000 6,000 50 20 12,000 8,000 20,000 200 80 logic modules s-modules c-modules 547 0 547 1,232 624 608 flip-flops (maximum) 273 998 routing resources horizontal tracks/channel vertical tracks/channel plice antifuse elements 22 13 186,000 35 15 750,000 user i/os (maximum) 69 140 packages (by pin count) ceramic quad flat pack (cqfp) 84 172 v3.1
radiation-hardened fpgas ii v3.1 ordering information ceramic device resources figure 1-1 ? ordering information application v = qml qualified package type cq = ceramic quad flat pack part number rh1280 = 8000 gates rh1020 = 2000 gates package lead count rh1280 ? cq 172 v cqfp 84-pin cqfp 172-pin rh1020 69 ? rh1280 ? 140
v3.1 iii table of contents radiation-hardened fpgas general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 radiation survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 qml qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 development tool support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 radhard architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 the rh1020 logic module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 qml flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 radiation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 timing models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 parameter measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 sequential module timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 8 84-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 172-pin cqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -3 list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 international traffic in arms regulations (itar) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1

radiation-hardened fpgas v3.1 1-1 radiation-hardened fpgas general description actel corporation, the leader in antifuse-based field programmable gate arrays (fpgas), offers fully guaranteed radhard versio ns of the a1280 and a1020 devices with gate densities of 8,000 and 2,000 gate array gates, respectively. the rh1020 and rh1280 devices are processed in 0.8 , two-level metal epitaxial bulk cmos technology. the devices are based on the actel patented channeled array architecture, and employ actel?s plice antifuse technology. this arch itecture offers gate array flexibility, high performance, and fast design implementation through user programming. actel devices also provide unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. on-chip clock drivers with hard-wired distribution networks provide efficient clock distribution with minimum skew. a security fuse may be programmed to disable all further programming, and to protect the design from being copied or reverse engineered. the rh1020 and rh1280 are available as fully qualified qml devices. unlike traditional asic devices, the design does not have to be finalized six months prior to receiving the devices. customers can make design modifications and program new devices within hours. these devices are fabricated , assembled, and tested at the lockheed-martin space and electronics facility in manassas, virginia on an optimized radiation-hardened cmos process. radiation survivability in addition to all electrical limits, all radiation characteristics are tested and guaranteed, reducing overall system-level risks. with total dose hardness of 300 krad (si), latch-up immunity, and a tested single event upset (seu) of less than 1x10 ?6 errors/bit-day, these are the only radhard, high-density field programmable products available today. qml qualification lockheed martin space and electronics in manassas, virginia has achieved full qml certification, assuring that quality management, procedures, processes, and controls are in place from wafer fabrication through final test. qml qualification means that quality is built into the production process rather than verified at the end of the line by expensive and destructive testing. qml also ensures continuous process improvement, a focus on enhanced quality and reliab ility, and shortened product introduction and cycle time. actel corporation has also achieved qml certification. all rh1020 and rh1280 devices will be shipped with a "qml" marking, signifying that the devices and processes have been reviewed and approved by desc for qml status. development tool support the radhard family of fpgas is fully supported by both actel libero ? integrated design environment (ide) and designer fpga development software. actel libero ide is a design management environment, seamlessly integrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. additionally, libero ide allows users to integrate both schematic and hdl synthesis into a single flow and verify the entire design in a single environment. libero ide includes synplify ? for actel from synplicity ? , viewdraw ? for actel from mentor graphics ? , model sim ? hdl simulator from mentor graphics, waveformer lite? from synapticad?, and designer software from actel. refer to the libero ide flow diagram for more information (located on the actel website). actel designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for fpga development. the designer software includes timing-driven place-and-ro ute, and a world-class integrated static timing anal yzer and constraints editor. with the designer software, a user can select and lock package pins while only minimally impacting the results of place-and-route. additionally, the back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with silicon explorer ii, actel?s integrated verification and logic analysis tool. another tool included in the designer software is the actgen macro builder, which easily creates popular and commonly used logic functions for implementation in your schematic or hdl design. actel's designer software is compat ible with the most popular fpga design entry and verification tools from companies such as mentor graphics, synplicity, synopsys, and cadence design systems. the designer software is available for both the windows and unix operating systems.
radiation-hardened fpgas 1-2 v3.1 applications the rh1020 and rh1280 devices are targeted for use in military and space applicati ons subject to radiation effects. 1. accumulated total dose effects with the significant in crease in earth-orbiting satellite launches and the ever-decreasing time-to- launch design cycles, the rh1020 and rh1280 devices offer the best combination of total dose radiation hardness and quick design implementation necessary for this increasingly competit ive industry. in addition, the high total dose capability allows the use of these devices for deep space probes, which encounter other planetary bodies where the total dose radiation effects are more pronounced. 2. single event effects (see) many space applications ar e more concerned with the number of single event upsets and potential for latch- up in space. the rh1020 and rh1280 devices are latch-up immune, guarant eeing that no latch-up failures will occur. single event upsets can occur in these devices as with all semiconductor products, but the rate of upset is low, as shown in table 1-2 on page 1-6 . 3. high dose rate survivability an additional radiation concern is high dose rate survivability. solar flares and sudden nuclear events can cause immediate high levels of radiation. the radhard devices are appropriate for use in these types of applications, including missile systems, ground-based communication systems, and orbiting satellites. radhard architecture the rh1020 and rh1280 architecture is composed of fine-grained building blocks that produce fast and efficient logic designs. all the devices are composed of logic modules, routing resources, clock networks, and i/o modules, which are the building blocks for fast logic designs. logic modules rh1280 devices contain two types of logic modules, combinatorial (c-modules) and sequential (s-modules). rh1020 devices contain only c-modules. the c-module, shown in figure 1-1 , implements the following function: y = !s1 !s0 d00 + !s1 s0 d01 + s1 !s0 d10 + s1 s0 d11 eq 1-1 where s0 = a0 b0 s1 = a1 + b1 the s-module, shown in figure 1-2 on page 1-3 , is designed to implement high-speed sequential functions within a single logic modul e. the s-module implements the same combinatorial logic function as the c-module while adding a sequential element. the sequential element can be configured as either a d-flip-flop or a transparent latch. to incr ease flexibility, the s-module register can be bypassed so it implements purely combinatorial logic. flip-flops can also be created using two c-modules. the single event upset (seu) charac teristics differ between an s-module flip-flop and a f lip-flop created using two c-modules. for details see the radiation specifications table on table 1-2 on page 1-6 and the design techniques for radhard field programmable gate arrays application note. the rh1020 logic module the rh1020 logic module is an 8-input, one-output logic circuit chosen for the wide range of functions it implements and for its effi cient use of interconnect routing resources ( figure 1-3 on page 1-3 ). the logic module can implem ent the four basic logic functions (nand, and, or, and nor) in gates of two, three, or four inputs. each function may have many versions, with different co mbinations of active-low inputs. the logic module can also implement a variety of d-latches, exclusivity func tions, and-ors, and or-ands. no dedicated hardwired latches or flip-flops are required in the array, since latches and flip-flops may be constructed from logic modules wherever needed in the application. figure 1-1 ? c-module implementation d00 d01 d10 d11 s0 s1 y a0 b0 a1 b1
radiation-hardened fpgas v3.1 1-3 i/o modules i/o modules provide the interface between the device pins and the logic array. a variety of user functions, determined by a library macro selection, can be implemented in the i/o modules (refer to the antifuse macro library guide for more information). i/o modules contain a tristate buffer, and input and output latches which can be configured for input, output, or bidirectional pins ( figure 1-4 ). figure 1-2 ? s-module implementation d11 d01 d00 d10 y out s1 s0 up to 7-input function plus d-type flip-flop with clear d11 d01 d00 d10 y s1 s0 up to 7-input function plus latch y up to 4-input function plus latch with clear d11 d01 d00 d10 yout s1 s0 up to 8-input function (same as c-module) s d1 d0 clr dq out clr dq out gate dq gate figure 1-3 ? rh1020 logic module note: *can be configured as a latch or d flip-flop (using c-module). figure 1-4 ? i/o module en pa d from array to array g/clk* qd g/clk* qd
radiation-hardened fpgas 1-4 v3.1 radhard devices contain flexible i/o structures in that each output pin has a dedicated output enable control. the i/o module can be used to latch input and/or output data, providing a fast set-up time. in addition, the actel designer software tools can build a d-flip-flop, using a c-module, to register input and/or output signals. actel designer development tools provide a design library of i/o macros that can implement all i/o configurations supported by the radhard fpgas. routing structure the radhard device architecture uses vertical and horizontal routing tracks to interconnect the various logic and i/o modules. these routing tracks are metal interconnects that may either be of continuous length or broken into segments. vary ing segment lengths allow over 90 percent of the circuit interconnects to be made with only two antifuse connections. segments can be joined together at the ends , using antifuses to increase their length up to the full length of the track. all interconnects can be accomplished with a maximum of four antifuses. horizontal routing horizontal channels are located between the rows of modules, and are composed of several routing tracks. the horizontal routing trac ks within the channel are divided into one or more segments. the minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. any segment that spans more than one-third the row leng th is considered a long horizontal segment. a typical channel is shown in figure 1-5 . non-dedicated horizontal routing tracks are used to route signal nets. dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. vertical routing another set of routing tracks run vertically through the module. there are three types of vertical tracks, input, output, and long, that can be divided into one or more segments. each segment in an input track is dedicated to the input of a particular module. each segment in an output track is dedicated to the output of a particular module. long segments are uncommitted and can be assigned during routing. each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. long vertical tracks contain either one or two segments. an example of ve rtical routing tracks and segments is shown in figure 1-5 . antifuse structures an antifuse is a "normally open" structure as opposed to the normally closed fuse structure used in proms or pals. the use of antifuses to implement a programmable logic device results in highly testable structures, as well as efficient programming al gorithms. the structure is highly testable because there are no pre-existing connections, enabling temp orary connections to be made using pass transistors. these temporary connections can isolate individual antifuses to be programmed, as well as is olate individual circuit structures to be tested. this can be done both before and after programming. for exampl e, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. related documents application notes design techniques for radhard field programmable gate arrays http://www.actel.com/documents/des_tech_rh_an.pdf analysis of sdi/dclk issue for rh1020 and rt1020 http://www.actel.com/doc uments/sdi_dclk_an.pdf simultaneously switching noise and signal integrity http://www.actel.com/documents/ssn_an.pdf user?s guides antifuse macro library guide http://www.actel.com/d ocuments/libguide_ug.pdf figure 1-5 ? routing structure vertical routing tracks segmented horizontal routing tracks logic modules antifuses
radiation-hardened fpgas v3.1 1-5 qml flow absolute maximum ratings test inspection method wafer lot acceptance lmfs procedure man-stc-q014 serialization required ? 100% die adhesion test 2027 (stud pull) bond pull test 2011 (wirebond) internal visual 2010, condition a temperature cycle 1010, condition c, 50 cycles constant acceleration 2001, condition d or e, y1 orientation only particle impact noise detection (pind) 2020, condition a x-ray radiography 2012 pre burn-in electrical parameters (t0) per device specification dynamic burn-in 1015, 240 hour minimum, 125c interim electrical parameters (t1) per device specification percent defective allowable (p da) lmfs procedure man-stc-q016 static burn-in 1015, 144 hour minimum, 125c minimum final electrical parameters (t 2) per device specification percent defective allowable (p da) lmfs procedure man-stc-q016 seal ? fine/gross leak 1014 external visual (as required) 2009 table 1-1 ? free air temperature range symbol parameter limits units v cc dc supply voltage 2,3,4,5 ?0.5 to +7.0 v v i input voltage ?0.5 to v cc +0.5 v v o output voltage ?0.5 to v cc +0.5 v i io i/o source/sink current 6 20 ma t stg storage temperature 2 ?65 to +150 c notes: 1. stresses beyond those listed under "absolute maximu m ratings" may cause permanent damage to the device. 2. exposure to absolute maximum rated cond itions for extended periods may affect de vice reliability. devices should not be opera ted outside the recommended operating conditions. 3. v pp = v cc , except during device operation. 4. v sv = v cc , except during device operation. 5. v ks = gnd , except during device operation. 6. device inputs are normally high impedance and draw extremely low current. however, when inpu t voltage is greater than v cc + 0.5 v or less than gnd ? 0.5v, the internal protection di ode will be forward-biased and can draw excessive current.
radiation-hardened fpgas 1-6 v3.1 recommended operating conditions electrical specifications radiation specifications parameter military units temperature range 1 ?55 to +125 c power supply tolerance 2 10 %v cc notes: 1. case temperature (t c ) is used. 2. all power supplies must be in the recommended operating range. symbol group a subgroups limits units test conditions min. max. v oh 1 (i oh = ?4 ma) 1, 2, 3 3.7 v v ol 1 (i ol = 4 ma) 1, 2, 3 0.4 v v ih 1, 2, 3 2.2 v cc + 0.3 v v il 1, 2, 3 ?0.3 0.8 v input transition time t r , t f 2 ?500ns c io , i/o capacitance 2 420pf i ih , i il v in = v cc or gnd v cc = 5.5 v 1, 2, 3 ?10 10 a i ozl , i ozh v out = v cc or gnd v cc = 5.5 v 1, 2, 3 ?10 10 a i cc standby 3 1, 2, 3 25 ma notes: 1. only one output tested at a time. v cc = min. 2. not tested, for information only. 3. all outputs unloaded. all inputs = v cc or gnd. table 1-2 ? radiation specifications 1, 2 symbol characteristics conditions min. max. units rtd total dose 300 k rad (si) sel single event latch-up ?55c t case 125c 0 fails/device-day seu1 3 single event upset for s-modules ?55c t case 125c 1e-6 upsets/bit-day seu2 3 single event upset for c-modules ?55c t case 125c 1e-7 upsets/bit-day seu3 3 single event fuse rupture ?55c t case 125c <1 fit (fails/device/1e9 hrs) rnf neutron fluence >1 e+12 n/cm 2 notes: 1. measured at room temperat ure unless otherwise stated. 2. device electrical characteristics are guaranteed for post-irradiation levels at worst-case conditions. 3. 10% worst-case particle environment, geosynchronous orbit, 0. 025" of aluminum shielding. specification set using the creme code upset rate calculation method with a 2 epi thickness.
radiation-hardened fpgas v3.1 1-7 package thermal characteristics the device junction to case thermal characteristics is jc , and the junction to ambient air ch aracteristics is ja . the thermal characteristics for ja are listed with two different air flow rates, as shown in table 1-3 . maximum junction temperature is 150c. a sample calculation of the maximum power dissipation for an 84-pin ceramic quad flat pack at commercial temperature is shown in eq 1-2 . eq 1-2 power dissipation general power equation p = [i cc standby + i cc active] v cc + i ol v ol n + i oh (v cc ? v oh ) m eq 1-3 where i cc standby is the current flowing when no inputs or outputs are changing. i cc active is the current flowing due to cmos switching. i ol , i oh are ttl sink/source currents. v ol , v oh are ttl level output voltages. n equals the number of outputs driving ttl loads to v ol . m equals the number of outputs driving ttl loads to v oh . accurate values for n and m are difficult to determine because they depend on the family type, design details, and on the system i/o. the power can be divided into two components: static and active. static power components actel fpgas have small static power components that result in lower power dissipation than pals or plds. by integrating multiple pals/p lds into one fpga, an even greater reduction in board- level power dissipation can be achieved. the power due to standby cu rrent is typically a small component of the overall power. standby power is calculated below for militar y, worst case conditions. i cc v cc power 25 ma 5.5 v 138 mw (max) 1 ma 5.5 v 5.5 mw (typ) active power components power dissipation in cmos devices is usually dominated by the active (dynamic) power dissipation. this component is frequency-dependent and a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to pc board traces and load devi ce inputs. an additional component of the active power dissipation is the totempole current in cmos transistor pairs. the net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. the power dissipated by a cmos circuit can be expressed by eq 1-4 : power (uw) = c eq v cc 2 f eq 1-4 table 1-3 ? thermal characteristics package type pin count jc ja units still air 1.0 m/s 200 ft. / min. 2.5 m/s 500 ft. / min. ceramic quad flat pack 84 2.0 40.0 33.0 30.0 c/w ceramic quad flat pack 172 2.0 28.0 23.1 21.0 c/w note: jc for cqfp packages refers to the thermal resistance between the junction and the bottom of the package. max. junction temperature c () max. commercial temperature c () ? ja (c/w) ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------- 150 c70 c ? 40c/w ------------------------------------ 2.0 w ==
radiation-hardened fpgas 1-8 v3.1 where equivalent capacitance equivalent capacitance is calculated by measuring i cc active at a specified fre quency and voltage for each circuit component of intere st. measurements have been made over a range of frequencies at a fixed value of v cc . equivalent capacitance is frequency-independent so the results may be used over a wide range of operating conditions. equivalent capacitance values follow. c eq values for actel fpgas to calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. eq 1-5 shows a piece-wise linear summation over all components. power = v cc 2 [(m c eqm f m ) modules + (n c eqi f n ) inputs + (p (c eqo + c l ) f p ) outputs + 0.5 (q 1 c eqcr f q1 ) routed_clk1 + (r 1 f q1 ) routed_clk1 + 0.5 (q 2 c eqcr f q2 ) routed_clk2 + (r 2 f q2 ) routed_clk2 ] eq 1-5 where fixed capacitance values for actel fpgas (pf) r1 r2 device type routed_clk1 routed_clk2 rh1020 69 n/a rh1280 168 168 determining average switching frequency to determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. the following guidelines are meant to represent worst-case scenarios, so they can be generally used to predict the upper limits of power dissipation. these guid elines are as follow: c eq = equivalent capacitance in pf v cc = power supply in volts (v) f = switching frequency in mhz rh1020 rh1280 modules (c eqm )3.7 5.2 input buffers (c eqi ) 22.1 11.6 output buffers (c eqo ) 31.2 23.8 routed array clock buffer loads (c eqcr )4.6 3.5 m = number of logic mo dules switching at f m n = number of input buffers switching at f n p = number of output buffers switching at f p q 1 = number of clock loads on the first routed array clock q 2 = number of clock loads on the second routed array clock (rh1280 only) r 1 = fixed capacitance due to first routed array clock r 2 = fixed capacitance due to second routed array clock (rh1280 only) c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c l = output lead capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz f q2 = average second routed array clock rate in mhz (rh1280 only) logic modules (m) = 80% of modules inputs switching (n) = # inputs/4 outputs switching (p) = # outputs/4 first routed array clock loads (q 1 ) = 40% of sequential modules second routed array clock loads (q 2 ) (rh1280 only) = 40% of sequential modules load capacitance (c l ) = 35 pf average logic module switching rate (f m ) =f/10 average input switching rate (f n ) =f/5 average output switching rate (f p ) =f/10 average first routed array clock rate (f q1 ) =f average second routed array clock rate (f q2 ) (rh1280 only) =f/2
radiation-hardened fpgas v3.1 1-9 timing models figure 1-6 ? rh1020 timing model note: ? input module predicted routing delay. figure 1-7 ? rh1280 timing model t ird1 = 1.2 ns t ird4 = 4.2 ns t ird8 = 8.9 ns t pd = 3.9 ns t co = 3.9 ns output delay input delay i/o module logic module i/o module array clock predicted routing delays fo = 128 internal delays t rd1 = 1.2 ns t rd2 = 1.9 ns t rd4 = 4.2 ns t rd8 = 8.9 ns t enhz = 13.5 ns t dlh = 9.1 ns t ird2 = 1.9 ns t inyl = 4.2 ns t ckh = 7.6 ns f max = 55 mhz t inyl = 2.3 ns t inh = 0.0 ns t insu = 0.6 ns t ingl = 5.3 ns output delays input delays i/o module dq ? internal delays combinatorial logic module sequential logic module i/o module i/o module array clocks dq dq predicted ro uti ng delays g g fo = 384 t ird2 = 7.5 ns t pd = 4.7 ns t rd1 = 2.7 ns t rh2 = 3.4 ns t rd4 = 4.8 ns t rd8 = 9.0 ns t dlh = 8.7 ns t dlh = 8.7 ns f max = 95 mhz t ckh = 11.2 ns t lco = 17.7 ns (64 loads, pad-pad) t sud = 0.7 ns t hd = 0.0 ns t co = 4.7 ns t rd1 = 2.7 ns t outh = 0.0 ns t outsu = 0.6 ns t glh = 7.6 ns t enhz = 9.7 ns combin- atorial logic included in t sud
radiation-hardened fpgas 1-10 v3.1 parameter measurement output buffer delays ac test loads input buffer delays module delays figure 1-8 ? output buffer delays to ac test loads (shown below) pad d e tribuff in 50% pa d v ol 1.5v 50% 1.5v e 50% pa d v ol 1.5v 50% 10% e 50% pa d gnd 1.5v 50% 90% v t dlh t dhl t enzl t enlz t enzh t enhz v oh v oh figure 1-9 ? ac test loads load 1 (used to measure propagation delay) load 2 (used to measure rising/falling edges) 35 pf to the output under test v cc gnd to the output under test 35 pf r to v cc for t plz / t pzl r to gnd for t phz / t pzh r = 1 k figure 1-10 ? input buffer delays pa d y inbuf pa d 3v 0v 1.5v y gnd v cc 50% t inyh 1.5v 50% t inyl figure 1-11 ? module delays s a b y s, a or b y 50% t plh y 50% 50% 50% 50% 50% t phl t phl t plh
radiation-hardened fpgas v3.1 1-11 sequential module timing characteristics flip-flops and latches note: d represents all data functions involving a, b, and s for multiplexed flip-flops. figure 1-12 ? flip-flops and latches figure 1-13 ? input buffer latches (positive edge triggered) d e clk clr pre y d 1 g, c l k e q pre, clr t wc l ka t wasyn t hd t suena t sud t rs t a t wclki t co t hena g pa d pa d clk data g clk clkbuf ibdl data t su ext t insu t h ext t inh
radiation-hardened fpgas 1-12 v3.1 figure 1-14 ? output buffer latches d g pad obdlhs d g t outsu t outh
radiation-hardened fpgas v3.1 1-13 timing characteristics table 1-4 ? rh1020 timing characteristics (worst-case military conditions, v cc = 4.5 v, t j = 125c, rtd = 300 krad (si)) parameter description min. max. units logic module propagation delays t pd1 single module 3.9 ns t pd2 dual module macros 9.2 ns t co sequential clk to q 3.9 ns t go latch g to q 3.9 ns t rs flip-flop (latch) reset to q 3.9 ns logic module predicted routing delays 1 t rd1 fo=1 routing delay 1.2 ns t rd2 fo=2 routing delay 1.9 ns t rd3 fo=3 routing delay 2.8 ns t rd4 fo=4 routing delay 4.2 ns t rd8 fo=8 routing delay 8.9 ns logic module sequential timing 2 t sud flip-flop (latch) data input set-up 7.5 ns t hd flip-flop (latch) data input hold 0.0 ns t suena flip-flop (latch) enable set-up 7.5 ns t hena flip-flop (latch) enable hold 0.0 ns t wclka flip-flop (latch) clock active pulse width 9.2 ns t wasyn flip-flop (latch) asynchronous pulse width 9.2 ns t a flip-flop clock input period 19.2 ns f max flip-flop (latch) clock frequency 50 mhz input module propagation delays t inyh pad to y high 4.2 ns t inyl pad to y low 4.2 ns input module predicted routing delays 1, 3 t ird1 fo=1 routing delay 1.2 ns t ird2 fo=2 routing delay 1.9 ns t ird3 fo=3 routing delay 2.8 ns t ird4 fo=4 routing delay 4.2 ns t ird8 fo=8 routing delay 8.9 ns notes: 1. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timing analysis or simulation is required to determin e actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 2. set-up times assume fanout of 3. further testing informati on can be obtained from the directtime analyzer utility. 3. optimization techniques may furt her reduce delays by 0 to 4 ns. 4. the hold time for the dfme1a macro may be greater than 0 ns. us e the designer v3.0 (or later) ti mer to check the hold time for this macro.
radiation-hardened fpgas 1-14 v3.1 table 1-5 ? rh1020 timing characteristics (worst-case military conditions, v cc = 4.5 v, t j = 125c, rtd = 300 krad (si)) parameter description min. max. units global clock network t ckh input low to high fo = 16 fo = 128 6.6 7.6 ns t ckl input high to low fo = 16 fo = 128 8.7 9.5 ns t pwh minimum pulse width high fo = 16 fo = 128 8.8 9.2 ns t pwl minimum pulse width low fo = 16 fo = 128 1.6 2.4 ns t cksw maximum skew fo = 16 fo = 128 1.6 2.5 ns t p minimum period fo = 16 fo = 128 17.9 19.2 ns f max maximum frequency fo = 16 fo = 128 55 50 mhz ttl output module timing 1 t dlh data to pad high 9.1 ns t dhl data to pad low 10.2 ns t enzh enable pad z to high 8.9 ns t enzl enable pad z to low 10.7 ns t enhz enable pad high to z 13.5 ns t enlz enable pad low to z 12.2 ns d tlh delta low to high 0.08 ns/pf d thl delta high to low 0.11 ns/pf cmos output module timing 1 t dlh data to pad high 10.7 ns t dhl data to pad low 8.7 ns t enzh enable pad z to high 8.1 ns t enzl enable pad z to low 11.2 ns t enhz enable pad high to z 13.5 ns t enlz enable pad low to z 12.2 ns d tlh delta low to high 0.14 ns/pf d thl delta high to low 0.08 ns/pf notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching noise and signal integrity application note .
radiation-hardened fpgas v3.1 1-15 table 1-6 ? rh1280 timing characteristics (worst-case military conditions, v cc = 4.5 v, t j = 125c, rtd = 300 krad (si)) parameter description min. max. units logic module propagation delays 1 t pd1 single module 4.7 ns t co sequential clk to q 4.7 ns t go latch g to q 4.7 ns t rs flip-flop (latch) reset to q 4.7 ns logic module predicted routing delays 2 t rd1 fo=1 routing delay 2.7 ns t rd2 fo=2 routing delay 3.4 ns t rd3 fo=3 routing delay 4.1 ns t rd4 fo=4 routing delay 4.8 ns t rd8 fo=8 routing delay 9.0 ns sequential timing characteristics 3, 4 t sud flip-flop (latch) data input set-up 0.7 ns t hd flip-flop (latch) data input hold 0.0 ns t suena flip-flop (latch) enable set-up 1.4 ns t hena flip-flop (latch) enable hold 0.0 ns t wclka flip-flop (latch) clock active pulse width 6.6 ns t wasyn flip-flop (latch) asynchronous pulse width 6.6 ns t a flip-flop clock input period 13.5 ns t inh input buffer latch hold 0.0 ns t insu input buffer latch set-up 0.6 ns t outh output buffer latch hold 0.0 ns t outsu output buffer latch set-up 0.6 ns f max flip-flop (latch) clock frequency 95 mhz notes: 1. for dual-module macros, use t pd + t rd1 + t pdn , t co + t rd1 + t pdn , or t pd1 + t rd1 + t sud , whichever is appropriate. 2. routing delays are for typical designs ac ross worst-case operating co nditions. these parameters sh ould be used for estimating device performance. post-route timing an alysis or simulation is required to dete rmine actual worst-cas e performance. post-rou te timing is based on actual routing delay measurements performed on the device prior to shipment. 3. data applies to macros based on the s-module. timing para meters for sequential macros constructed from c-modules can be obtained from the directtime analyzer utility. 4. set-up and hold timing parameters for the input buffer latch are defined with re spect to the pad and the d input. external se t-up/ hold timing parameters must account for dela y from an external pad signal to the g inputs. delay from an external pad signal to the g input subtracts (adds) to the internal set-up (hold) time.
radiation-hardened fpgas 1-16 v3.1 table 1-7 ? rh1280 timing characteristics (worst-case military conditions, v cc = 4.5 v, t j = 125c, rtd = 300 krad (si)) parameter description min. max. units input module propagation delays t inyh pad to y high 1.9 ns t inyl pad to y low 2.3 ns t ingh g to y high 4.1 ns t ingl g to y low 5.3 ns input module predicted routing delays* t ird1 fo=1 routing delay 6.8 ns t ird2 fo=2 routing delay 7.5 ns t ird3 fo=3 routing delay 8.2 ns t ird4 fo=4 routing delay 8.9 ns t ird8 fo=8 routing delay 11.7 ns global clock network t ckh input low to high fo = 32 fo = 384 9.6 11.2 ns t ckl input high to low fo = 32 fo = 384 9.6 11.2 ns t pwh minimum pulse width high fo = 32 fo = 384 5.8 6.2 ns t pwl minimum pulse width low fo = 32 fo = 384 5.8 6.2 ns t cksw maximum skew fo = 32 fo = 384 1.1 1.1 ns t suext input latch external set-up fo = 32 fo = 384 0.0 0.0 ns t hext input latch external hold fo = 32 fo = 384 4.6 5.8 ns t p minimum period fo = 32 fo = 384 11.8 13.0 ns f max maximum frequency fo = 32 fo = 384 105 95 mhz note: *routing delays are for typical designs ac ross worst-case operating conditions. these pa rameters should be used for estimating device performance. post-route timing analys is or simulation is required to determin e actual worst-case performance. post-route timing is based on actual routing delay m easurements performed on the device prior to shipment. optimization techniques may further reduce delays by 0 to 4 ns.
radiation-hardened fpgas v3.1 1-17 table 1-8 ? rh1280 timing characteristics (worst-case military conditions, v cc = 4.5 v, t j = 125c, rtd = 300 krad (si)) parameter description min. max. units ttl output module timing 1 t dlh data to pad high 6.8 ns t dhl data to pad low 7.6 ns t enzh enable pad z to high 6.8 ns t enzl enable pad z to low 7.6 ns t enhz enable pad high to z 9.7 ns t enlz enable pad low to z 9.7 ns t glh g to pad high 7.6 ns t ghl g to pad low 8.9 ns t lco i/o latch clock-out (pad-to-pad ), 64 clock loading 17.7 ns t aco array clock-out (pad-to-pad ), 64 clock loading 25.0 ns d tlh capacitive loading, low to high 0.07 ns/pf d thl capacitive loading, high to low 0.09 ns/pf cmos output module timing 1 t dlh data to pad high 8.7 ns t dhl data to pad low 6.4 ns t enzh enable pad z to high 6.8 ns t enzl enable pad z to low 7.6 ns t enhz enable pad high to z 9.7 ns t enlz enable pad low to z 9.7 ns t glh g to pad high 7.6 ns t ghl g to pad low 8.9 ns t lco i/o latch clock-out (pad-to-pad ), 64 clock loading 20.1 ns t aco array clock-out (pad-to-pad ), 64 clock loading 29.5 ns d tlh capacitive loading, low to high 0.09 ns/pf d thl capacitive loading, high to low 0.08 ns/pf notes: 1. delays based on 35 pf loading. 2. sso information can be found in the simultaneously switching noise and signal integrity application note.
radiation-hardened fpgas 1-18 v3.1 pin description clka clock a (input) ttl clock input for clock dist ribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. clkb clock b (input) not applicable for rh1020. ttl clock input for clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. dclk 1 diagnostic clock (input) ttl clock input for diagnostic probe and device programming. dclk is acti ve when the mode pin is high. this pin functions as an i/o when the mode pin is low. if the program fuse is not programmed and dclk is undefined, it is configured as an inactive input. in this case, tie the dclk pin to ground. if the program fuse is programmed and dclk is un defined, it will become an active low output.the program fuse must be programmed if the dclk pin is used as an output or a bidirectional pin. gnd ground low supply voltage. i/o input/output (input, output) the i/o pin functions as an in put, output, three-state, or bidirectional buffer. input and output levels are compatible with standard ttl and cmos specifications. unused i/o pins are automatically driven low by the designer software. mode mode (input) the mode pin controls the use of multi-function pins (dclk, pra, prb, sdi). when the mode pin is high, the special functions are active. when the mode pin is low, the pins function as i/os. to provide debugging capability, the mode pin should be terminated to gnd through a 10 k resistor so that the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. pra, i/o probe a (output) the probe a pin is used to output data from any user- defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when verification has been completed. the pin?s probe capabilities can be permanently disabled to protect programmed design confidentiality. pra is accessible when the mode pin is high. this pin functions as an i/o when the mode pin is low. prb, i/o probe b (output) the probe b pin is used to output data from any user- defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when verification has been completed. the pin?s probe capabilities can be permanently disabled to protect programmed design confidentiality. prb is accessible when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdi 1 serial data input (input) serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. if the program fuse is not programmed and sdi is undefined, it is configured as an inactive input. in this case, tie the sdi pin to ground. if the program fuse is programmed and sdi is und efined, it will become an active low output.the program fuse must be programmed if the sdi pin is used as an output or a bidirectional pin. v cc 5.0v supply voltage high supply voltage. 1. please refer to the actel technical brief analysis of sdi/dclk issue for rh1020 and rt1020 .
radiation-hardened fpgas v3.1 2-1 package pin assignments 84-pin cqfp note for package manufacturing and environmental info rmation, visit the package resource center at http://www.actel.com/products/ rescenter/package/index.html . figure 2-1 ? 84-pin cqfp (top view) pin #1 index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 84-pin cqfp 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
radiation-hardened fpgas 2-2 v3.1 84-pin cqfp pin number rh1020 function 1nc 2i/o 3i/o 4i/o 5i/o 6i/o 7gnd 8gnd 9i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 v cc 15 v cc 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 v cc 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 gnd 30 i/o 31 i/o 32 i/o 33 i/o 34 i/o 35 v cc 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 gnd 50 gnd 51 i/o 52 i/o 53 clka, i/o 54 i/o 55 mode 56 v cc 57 v cc 58 i/o 59 i/o 60 i/o 61 sdi, i/o 62 dclk, i/o 63 pra, i/o 64 prb, i/o 65 i/o 66 i/o 67 i/o 68 i/o 69 i/o 70 i/o 84-pin cqfp pin number rh1020 function 71 gnd 72 i/o 73 i/o 74 i/o 75 i/o 76 i/o 77 v cc 78 i/o 79 i/o 80 i/o 81 i/o 82 i/o 83 i/o 84 i/o 84-pin cqfp pin number rh1020 function
radiation-hardened fpgas v3.1 2-3 172-pin cqfp note for package manufacturing and environmental info rmation, visit the package resource center at http://www.actel.com/products/ rescenter/package/index.html . figure 2-2 ? 172-pin cqfp (top view) 172-pin cqfp pin #1 index 172 171 170 169 168 167 166 165 164 137 136 135 134 133 132 131 130 44 45 46 47 48 49 50 51 52 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 122 123 12 4 125 12 6 127 12 8 129 43 42 41 40 39 38 37 36 35 8 7 6 5 4 3 2 1
radiation-hardened fpgas 2-4 v3.1 172-pin cqfp pin number rh1280a function 1mode 2i/o 3i/o 4i/o 5i/o 6i/o 7gnd 8i/o 9i/o 10 i/o 11 i/o 12 v cc 13 i/o 14 i/o 15 i/o 16 i/o 17 gnd 18 i/o 19 i/o 20 i/o 21 i/o 22 gnd 23 v cc 24 v cc 25 i/o 26 i/o 27 v cc 28 i/o 29 i/o 30 i/o 31 i/o 32 gnd 33 i/o 34 i/o 35 i/o 36 i/o 37 gnd 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 i/o 50 v cc 51 i/o 52 i/o 53 i/o 54 i/o 55 gnd 56 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 i/o 64 i/o 65 gnd 66 v cc 67 i/o 68 i/o 69 i/o 70 i/o 172-pin cqfp pin number rh1280a function 71 i/o 72 i/o 73 i/o 74 i/o 75 gnd 76 i/o 77 i/o 78 i/o 79 i/o 80 v cc 81 i/o 82 i/o 83 i/o 84 i/o 85 i/o 86 i/o 87 i/o 88 i/o 89 i/o 90 i/o 91 i/o 92 i/o 93 i/o 94 i/o 95 i/o 96 i/o 97 i/o 98 gnd 99 i/o 100 i/o 101 i/o 102 i/o 103 gnd 104 i/o 105 i/o 172-pin cqfp pin number rh1280a function 106 gnd 107 v cc 108 gnd 109 v cc 110 v cc 111 i/o 112 i/o 113 v cc 114 i/o 115 i/o 116 i/o 117 i/o 118 gnd 119 i/o 120 i/o 121 i/o 122 i/o 123 gnd 124 i/o 125 i/o 126 i/o 127 i/o 128 i/o 129 i/o 130 i/o 131 sdi, i/o 132 i/o 133 i/o 134 i/o 135 i/o 136 v cc 137 i/o 138 i/o 139 i/o 140 i/o 172-pin cqfp pin number rh1280a function
radiation-hardened fpgas v3.1 2-5 141 gnd 142 i/o 143 i/o 144 i/o 145 i/o 146 i/o 147 i/o 148 pra, i/o 149 i/o 150 clka, i/o 151 v cc 152 gnd 153 i/o 154 clkb, i/o 155 i/o 156 prb, i/o 157 i/o 158 i/o 159 i/o 160 i/o 161 gnd 162 i/o 163 i/o 164 i/o 165 i/o 166 v cc 167 i/o 168 i/o 169 i/o 170 i/o 171 dclk, i/o 172 i/o 172-pin cqfp pin number rh1280a function

radiation-hardened fpgas v3.1 3-1 datasheet information list of changes the following table lists critical changes that were made in the current version of the document. datasheet categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are desi gnated as "product brief," "advance d," "production," and "datasheet supplement." the definitions of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advanced or production) containing general product information. this brief gives an overview of specific device and family information. advanced this datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. unmarked (production) this datasheet version contains informat ion that is considered to be final. datasheet supplement the datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. the supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications th at do not differ between the two families. international traffic in arms regulations (itar) the product described in this datasheet are subject to the international traf fic in arms regulations (itar). they require an approved export license prior to export from th e united states. an export in cludes release of product or disclosure of technology to a foreign nati onal inside or outsid e the united states. previous version changes in current version (v3 . 1) page v3.0 "development tool support" section was updated. 1-1 ta b l e 1 - 1 was updated. 1-5 ta b l e 1 - 2 was updated. 1-6 ta b l e 1 - 3 was updated. 1-7 the "dclk diagnostic clock (input)" section was updated. 1-18 the "sdi1 serial data input (input)" section was updated. 1-18
5172123-3/4.05 actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. dunlop house, riverside way camberley, surrey gu15 3yl united kingdom phone +44 (0) 1276 401 450 fax +44 (0) 1276 401 490 actel japan www.jp.actel.com exos ebisu bldg. 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 actel hong kong www.actel.com.cn suite 2114, two pacific place 88 queensway, admiralty hong kong phone +852 2185 6460 fax +852 2185 6488 www.actel.com actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners.

▲Up To Search▲

Price & Availability of RH1020-CQ84V

	To Download RH1020-CQ84V Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .