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| mitsubishi 8-bit single-chip microcomputer 740 family / 38000 series user? manual 38k0 group before using this material, please visit the above website to confirm that this is the most current document available. http://www.infomicom.maec.co.jp/indexe.htm rev. 1.0 revision date: jan. 17, 2003
keep safety first in your circuit designs! notes regarding these materials mitsubishi electric corporation puts the maximum effort into making semiconductor prod- ucts better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with ap- propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non- flammable material or (iii) prevention against any malfunction or mishap. these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, pro- grams and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http:// www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa- tion as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semicon- ductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or repro- duce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be im- ported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/ or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein. revision history 38k0 group user? manual rev. date description page summary (1/1) 1.0 01/17/03 first edition preface this user? manual describes mitsubishi? cmos 8- bit microcomputers 38k0 group. after reading this manual, the user should have a through knowledge of the functions and features of the 38k0 group, and should be able to fully utilize the product. the manual starts with specifications and ends with application examples. for details of software, refer to the ?40 family software manual? before using this manual this user? manual consists of the following three chapters. refer to the chapter appropriate to your conditions, such as hardware design or software development. chapter 3 also includes necessary information for systems development. you must refer to that chapter. 1. organization chapter 1 hardware this chapter describes features of the microcomputer and operation of each peripheral function. chapter 2 application this chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. chapter 3 appendix this chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the notes, and the list of registers. ? for the mask rom confirmation form and the mark specifications, refer to the ?itsubishi mcu technical information?homepage (http://www.infomicom.maec.co.jp/). 2. structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows : n o t e 2 : b i t a t t r i b u t e s . . . . . . . . .t h e a t t r i b u t e s o f c o n t r o l r e g i s t e r b i t s a r e c l a s s i f i e d i n t o 3 b y t e s : r e a d - o n l y , w r i t e - o n l y a n d r e a d a n d w r i t e . i n t h e f i g u r e , t h e s e a t t r i b u t e s a r e r e p r e s e n t e d a s f o l l o w s : : b i t i n w h i c h n o t h i n g i s a r r a n g e d 0 1 : n a m e function a t reset rw b 0 1 2 3 4 0 0 0 0 0 ? ? contents immediately after reset release bit attributes (n ote 1 ) p r o c e s s o r m o d e b i t s s t a c k p a g e s e l e c t i o n b i t n o t h i n g a r r a n g e d f o r t h e s e b i t s . t h e s e a r e w r i t e d i s a b l e d b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e c o n t e n t s a r e 0 . fix this bit to 0. m a i n c l o c k ( x i n - x o u t ) s t o p b i t internal system clock selection bit 0 0 : si ng l e-c hi p mo d e 1 0 : 1 1 : n ot ava il a bl e b1 b0 0 : 0 page 1 : 1 page 0 : o perat i ng 1 : s toppe d 0 : x in - x out se l ecte d 1 : x cin - x cout se l ecte d : b i t t h a t i s n o t u s e d f o r c o n t r o l o f t h e c o r r e s p o n d i n g f u n c t i o n 0 n o t e 1 : . c o n t e n t s i m m e d i a t e l y a f t e r r e s e t r e l e a s e 0 . . . . . . . 0 a t r e s e t r e l e a s e 1 . . . . . . . 1 a t r e s e t r e l e a s e ? . . . . . . .u n d e f i n e d a t r e s e t r e l e a s e ? ? ? bits ? ? i 38k0 group user? manual table of contents table of contents chapter 1 hardware description ............................................................................................................................... . 1-2 features ............................................................................................................................... ..... 1-2 pin configuration .................................................................................................................. 1-2 functional block .................................................................................................................. 1-3 pin description ........................................................................................................................ 1-4 part numbering ....................................................................................................................... 1-5 group expansion .................................................................................................................... 1-6 memory type ............................................................................................................................ 1-6 memory size ............................................................................................................................. 1- 6 packages ............................................................................................................................... .... 1-6 functional description ...................................................................................................... 1-7 central processing unit (cpu) .............................................................................................. 1-7 memory ............................................................................................................................... ..... 1-11 i/o ports ............................................................................................................................... ... 1-13 interrupts ..................................................................................................................... ............ 1-17 timers ............................................................................................................................... ....... 1-20 serial i/o ............................................................................................................................... .. 1-22 usb function .......................................................................................................................... 1-26 external bus interface (exb) ............................................................................................... 1-52 multichannel ram .................................................................................................................. 1-71 a-d converter ......................................................................................................................... 1-73 watchdog timer ..................................................................................................................... 1-75 reset circuit ........................................................................................................................... 1-76 pll circuit (frequency synthesizer) ................................................................................... 1-77 clock generating circuit ....................................................................................................... 1-79 flash memory mode .............................................................................................................. 1-82 notes on programming ................................................................................................... 1-108 notes on usage ................................................................................................................... 1-110 data required for mask orders .............................................................................. 1-110 functional description supplement ....................................................................... 1-111 chapter 2 application 2.1 i/o port ............................................................................................................................... ...... 2-2 2.1.1 memory map ................................................................................................................... 2-2 2.1.2 related registers ............................................................................................................ 2-3 2.1.3 handling of unused pins ............................................................................................... 2-5 2.1.4 notes on input and output pins ................................................................................... 2-6 2.1.5 termination of unused pins .......................................................................................... 2-7 2.2 interrupt ............................................................................................................................... .... 2-8 2.2.1 memory map ................................................................................................................... 2-8 2.2.2 related registers ............................................................................................................ 2-8 2.2.3 interrupt source ............................................................................................................ 2-11 2.2.4 interrupt operation ........................................................................................................ 2-12 2.2.5 interrupt control ............................................................................................................ 2-15 2.2.6 int interrupt .................................................................................................................. 2-18 2.2.7 key input interrupt ....................................................................................................... 2-19 2.2.8 notes on interrupts ...................................................................................................... 2-21 ii 38k0 group user? manual table of contents 2.3 timer ............................................................................................................................... ........ 2-23 2.3.1 memory map ................................................................................................................. 2-23 2.3.2 related registers .......................................................................................................... 2-23 2.3.3 timer application examples ........................................................................................ 2-28 2.3.4 notes on timer .............................................................................................................. 2-39 2.4 serial i/o ............................................................................................................................... . 2-40 2.4.1 memory map ................................................................................................................. 2-40 2.4.2 related registers .......................................................................................................... 2-41 2.4.3 serial i/o connection examples ................................................................................. 2-45 2.4.4 setting of serial i/o transfer data format ................................................................. 2-47 2.4.5 serial i/o application examples ................................................................................. 2-48 2.4.6 notes on serial i/o ...................................................................................................... 2-66 2.5 usb function ........................................................................................................................ 2-69 2.6 external bus interface(exb) .............................................................................................. 2-70 2.7 a-d converter ....................................................................................................................... 2-71 2.7.1 memory map ................................................................................................................. 2-71 2.7.2 related registers .......................................................................................................... 2-71 2.7.3 a-d converter application examples .......................................................................... 2-74 2.7.4 notes on a-d converter .............................................................................................. 2-76 2.8 watchdog timer .................................................................................................................... 2-77 2.8.1 memory map ................................................................................................................. 2-77 2.8.2 related registers .......................................................................................................... 2-77 2.8.3 watchdog timer application examples ..................................................................... 2-79 2.8.4 notes on watchdog timer ............................................................................................ 2-80 2.9 reset ............................................................................................................................... ........ 2-81 2.9.1 connection example of reset ic ................................................................................ 2-81 ____________ 2.9.2 notes on reset pin ................................................................................................... 2-82 2.10 frequency synthesizer (pll) .......................................................................................... 2-83 2.10.1 memory map ............................................................................................................... 2-83 2.10.2 related registers ........................................................................................................ 2-83 2.10.3 functional description ................................................................................................ 2-85 2.10.4 notes on pll ............................................................................................................ . 2-88 2.11 clock generating circuit .................................................................................................. 2-89 2.11.1 memory map ............................................................................................................... 2-89 2.11.2 related registers ........................................................................................................ 2-89 2.11.3 oscillation control ....................................................................................................... 2-91 2.12 standby function ............................................................................................................... 2-94 2.12.1 memory map ............................................................................................................... 2-94 2.12.2 related registers ........................................................................................................ 2-94 2.12.3 stop mode ................................................................................................................... 2-95 2.12.4 wait mode ................................................................................................................... 2-99 2.12.5 notes on stand-by function ..................................................................................... 2-101 2.13 flash memory ................................................................................................................... 2-102 2.13.1 overview .................................................................................................................... 2-102 2.13.2 memory map ............................................................................................................. 2-102 2.13.3 related registers ...................................................................................................... 2-103 2.13.4 parallel i/o mode ..................................................................................................... 2-104 2.13.5 standard serial i/o mode ........................................................................................ 2-104 2.13.6 cpu rewrite mode ................................................................................................... 2-105 2.13.7 flash memory mode application examples .......................................................... 2-106 2.13.8 notes on cpu rewrite mode .................................................................................. 2-111 iii 38k0 group user? manual table of contents chapter 3 appendix 3.1 electrical characteristics ..................................................................................................... 3-2 3.1.1 absolute maximum ratings ............................................................................................ 3-2 3.1.2 recommended operating conditions ............................................................................ 3-3 3.1.3 electrical characteristics ................................................................................................ 3-5 3.1.4 a-d converter characteristics ....................................................................................... 3-7 3.1.5 timing requirements ...................................................................................................... 3-8 3.1.6 switching characteristics ............................................................................................... 3-9 3.1.7 recommended operating conditions .......................................................................... 3-11 3.1.8 electrical characteristics .............................................................................................. 3-13 3.1.9 a-d converter characteristics ..................................................................................... 3-15 3.1.10 timing requirements .................................................................................................. 3-16 3.1.11 switching characteristics ........................................................................................... 3-19 3.2 standard characteristics .................................................................................................... 3-28 3.3 notes on use ........................................................................................................................ 3-29 3.3.1 notes on input and output ports ................................................................................ 3-29 3.3.2 termination of unused pins ........................................................................................ 3-30 3.3.3 notes on interrupts ...................................................................................................... 3-31 3.3.4 notes on timer .............................................................................................................. 3-32 3.3.5 notes on serial i/o ...................................................................................................... 3-33 3.3.6 notes on usb function ................................................................................................ 3-35 3.3.7 notes on a-d converter .............................................................................................. 3-36 3.3.8 notes on watchdog timer ............................................................................................ 3-36 _____________ 3.3.9 notes on reset pin ................................................................................................... 3-36 3.3.10 notes onpll ............................................................................................................... 3-36 3.3.11 notes on stand-by function ....................................................................................... 3-37 3.3.12 notes on cpu rewrite mode .................................................................................... 3-37 3.3.13 notes on programming .............................................................................................. 3-38 3.3.14 notes on flash memory version ............................................................................... 3-40 3.3.15 electric characteristic differences between mask rom and flash memory version mcus ........................................................................................................................... 3-40 3.4 countermeasures against noise ...................................................................................... 3-41 3.4.1 shortest wiring length .................................................................................................. 3-41 3.4.2 connection of bypass capacitor across v ss line and v cc line ............................... 3-43 3.4.3 wiring to analog input pins ........................................................................................ 3-44 3.4.4 oscillator concerns ....................................................................................................... 3-45 3.4.5 setup for i/o ports ....................................................................................................... 3-46 3.4.6 providing of watchdog timer function by software .................................................. 3-47 3.5 list of registers ................................................................................................................... 3-48 3.6 package outline ................................................................................................................... 3-82 3.7 machine instructions .......................................................................................................... 3-84 3.8 list of instruction code ..................................................................................................... 3-95 3.9 sfr memory map ................................................................................................................ 3-96 3.10 pin configurations ........................................................................................................ ..... 3-97 iv 38k0 group user? manual list of figures list of figures chapter 1 hardware fig. 1 pin configuration of 38k0 group ..................................................................................... 1-2 fig. 2 functional block diagram ................................................................................................. 1-3 fig. 3 part numbering .................................................................................................................. 1-5 fig. 4 memory expansion plan ................................................................................................... 1-6 fig. 5 740 family cpu register structure ................................................................................. 1-7 fig. 6 register push and pop at interrupt generation and subroutine call .......................... 1-8 fig. 7 structure of cpu mode register ................................................................................... 1-10 fig. 8 memory map diagram ..................................................................................................... 1-11 fig. 9 memory map of special function register (sfr) ......................................................... 1-12 fig. 10 port block diagram (1) ................................................................................................. 1-14 fig. 11 port block diagram (2) ................................................................................................. 1-15 fig. 12 structure of port i/o-related registers ........................................................................ 1-16 fig. 13 interrupt control ..................................................................................................... ........ 1-18 fig. 14 structure of interrupt-related registers ....................................................................... 1-18 fig. 15 connection example when using key input interrupt and port p0 block diagram1-19 fig. 16 structure of timer x mode register ............................................................................ 1-20 fig. 17 timer block diagram ..................................................................................................... 1-21 fig. 18 block diagram of clock synchronous serial i/o ........................................................ 1-22 fig. 19 operation of clock synchronous serial i/o function ................................................. 1-22 fig. 20 block diagram of uart serial i/o .............................................................................. 1-23 fig. 21 operation of uart serial i/o function ....................................................................... 1-23 fig. 22 structure of serial i/o control registers ..................................................................... 1-25 fig. 23 usb function overview ................................................................................................. 1-26 fig. 24 usb function control circuit (usbfcc) block diagram ......................................... 1-27 fig. 25 usb port external circuit (d0+, d0-, usbv ref , tron) block diagram (4.0v v cc 5.25v) ........................................................................................................................ 1-28 fig. 26 usb port external circuit (d0+, d0-, usbv ref , tron) block diagram (3.0v v cc 4.0v) .......................................................................................................................... 1-28 fig. 27 example setting of buffer area beginning address .................................................. 1-29 fig. 28 examples of interrupt source dependant buffer area offset address .................... 1-29 fig. 29 usb device interrupt control ....................................................................................... 1-31 fig. 30 usb related registers ................................................................................................... 1-32 fig. 31 structure of usb control register ............................................................................... 1-33 fig. 32 structure of usb function enable register ................................................................ 1-33 fig. 33 structure of usb function address register .............................................................. 1-34 fig. 34 structure of frame number register low .................................................................. 1-34 fig. 35 structure of frame number register high ................................................................. 1-34 fig. 36 structure of usb interrupt source enable register ................................................... 1-35 fig. 37 structure of usb interrupt source register ................................................................ 1-36 fig. 38 structure of endpoint index register .......................................................................... 1-36 fig. 39 structure of ep00 stage register ................................................................................ 1-37 fig. 40 structure of ep00 control register 1 .......................................................................... 1-37 fig. 41 structure of ep00 control register 2 .......................................................................... 1-37 fig. 42 structure of ep00 control register 3 .......................................................................... 1-38 fig. 43 structure of ep00 interrupt source register .............................................................. 1-38 v 38k0 group user? manual list of figures fig. 44 structure of ep00 byte number register .................................................................... 1-39 fig. 45 structure of ep00 buffer area set register ................................................................ 1-39 fig. 46 structure of ep01 set register .................................................................................... 1-40 fig. 47 structure of ep01 control register 1 .......................................................................... 1-40 fig. 48 structure of ep01 control register 2 .......................................................................... 1-41 fig. 49 structure of ep01 control register 3 .......................................................................... 1-41 fig. 50 structure of ep01 interrupt source register .............................................................. 1-41 fig. 51 structure of ep01 byte number register 0 ................................................................ 1-42 fig. 52 structure of ep01 byte number register 1 ................................................................ 1-42 fig. 53 structure of ep01 max. packet size register ........................................................... 1-42 fig. 54 structure of ep01 buffer area set register ................................................................ 1-43 fig. 55 structure of ep02 set register .................................................................................... 1-44 fig. 56 structure of ep02 control register 1 .......................................................................... 1-44 fig. 57 structure of ep02 control register 2 .......................................................................... 1-45 fig. 58 structure of ep02 control register 3 .......................................................................... 1-45 fig. 59 structure of ep02 interrupt source register .............................................................. 1-45 fig. 60 structure of ep02 byte number register 0 ................................................................ 1-46 fig. 61 structure of ep02 byte number register 1 ................................................................ 1-46 fig. 62 structure of ep02 max. packet size register ........................................................... 1-46 fig. 63 structure of ep02 buffer area set register ................................................................ 1-47 fig. 64 structure of ep03 set register .................................................................................... 1-48 fig. 65 structure of ep03 control register 1 .......................................................................... 1-48 fig. 66 structure of ep03 control register 2 .......................................................................... 1-49 fig. 67 structure of ep03 control register 3 .......................................................................... 1-49 fig. 68 structure of ep03 interrupt source register .............................................................. 1-49 fig. 69 structure of ep03 byte number register 0 ................................................................ 1-50 fig. 70 structure of ep03 byte number register 1 ................................................................ 1-50 fig. 71 structure of ep03 max. packet size register ........................................................... 1-50 fig. 72 structure of ep03 buffer area set register ................................................................ 1-51 fig. 73 external bus interface .................................................................................................. 1-52 fig. 74 data transfer timing of memory channel ................................................................... 1-52 fig. 75 external bus interface (exb) pin assignment ........................................................... 1-53 fig. 76 block diagram of external bus interface (exb) ........................................................ 1-54 fig. 77 exb related registers (1) ............................................................................................. 1-58 fig. 78 exb related registers (2) ............................................................................................. 1-58 fig. 79 structure of exb interrupt source enable register ................................................... 1-59 fig. 80 structure of exb interrupt source register ................................................................ 1-59 fig. 81 structure of exb index register .................................................................................. 1-60 fig. 82 structure of register window 1 .................................................................................. 1-60 fig. 83 structure of register window 2 .................................................................................. 1-60 fig. 84 index00[low]; structure of external i/o configuration register ................................ 1-61 fig. 85 index00[high]; structure of external i/o configuration register ............................. 1-61 fig. 86 index01[low]; structure of transmit/receive buffer register ................................... 1-62 fig. 87 index02[low]; structure of memory channel operation mode register ................... 1-62 fig. 88 index03[low]; structure of memory address counter ............................................... 1-62 fig. 89 index03[high]; structure of memory address counter .............................................. 1-63 fig. 90 index04[low]; structure of end address register ...................................................... 1-63 fig. 91 index04[high]; structure of end address register ..................................................... 1-63 fig. 92 cpu channel receiving operation ............................................................................... 1-64 fig. 93 cpu channel tranmitting operation ............................................................................. 1-65 fig. 94 memory channel receiving operation (1) ................................................................... 1-66 fig. 95 memory channel receiving operation (2) ................................................................... 1-67 vi 38k0 group user? manual list of figures fig. 96 memory channel receiving operation (3) ................................................................... 1-68 fig. 97 memory channel tranmitting operation (1) ................................................................. 1-69 fig. 98 memory channel tranmitting operation (2) ................................................................. 1-70 fig. 99 multichannel ram timing diagram (no wait) ............................................................. 1-71 fig. 100 multichannel ram timing diagram (one wait) ......................................................... 1-71 fig. 101 multichannel ram operation example ...................................................................... 1-72 fig. 102 structure of a-d control register .............................................................................. 1-73 fig. 103 10-bit a-d mode reading ........................................................................................... 1-73 fig. 104 a-d converter block diagram .................................................................................... 1-74 fig. 105 block diagram of watchdog timer ............................................................................ 1-75 fig. 106 structure of watchdog timer control register .......................................................... 1-75 fig. 108 reset sequence .......................................................................................................... 1-76 fig. 107 example of reset circuit ............................................................................................. 1-76 fig. 109 block diagram of pll circuit ..................................................................................... 1-77 fig. 110 structure of pll control register .............................................................................. 1-78 fig. 111 ceramic resonator or quartz-crystal oscilltor circuit .............................................. 1-80 fig. 112 external clock input circuit ........................................................................................ 1-80 fig. 114 system clock generating circuit block diagram (single-chip mode) ..................... 1-80 fig. 113 structure of misrg .................................................................................................... 1-80 fig. 115 state transitions of clock ........................................................................................... 1-81 fig. 116 block diagram of built-in flash memory ................................................................... 1-83 fig. 117 structure of flash memory control register .............................................................. 1-84 fig. 118 cpu rewrite mode set/release flowchart ................................................................. 1-85 fig. 119 program flowchart ....................................................................................................... 1-87 fig. 120 erase flowchart ........................................................................................................... 1-88 fig. 121 full status check flowchart and remedial procedure for errors ........................... 1-90 fig. 122 structure of rom code protect control register ..................................................... 1-91 fig. 123 id code store addresses ........................................................................................... 1-92 fig. 124 pin connection diagram in standard serial i/o mode (1) ...................................... 1-96 fig. 125 timing for page read .................................................................................................. 1-98 fig. 126 timing for reading status register ............................................................................ 1-98 fig. 127 timing for clear status register ................................................................................. 1-99 fig. 128 timing for page program ........................................................................................... 1-99 fig. 129 timing for erase all blocks ...................................................................................... 1-100 fig. 130 timing for download ................................................................................................. 1-101 fig. 131 timing for version information output .................................................................... 1-102 fig. 132 timing for boot rom area output .......................................................................... 1-102 fig. 133 timing for id check .................................................................................................. 1-103 fig. 134 id code storage addresses ..................................................................................... 1-103 fig. 135 full status check flowchart and remedial procedure for errors ......................... 1-106 fig. 136 example circuit application for standard serial i/o mode ................................... 1-107 fig. 137 definition of a-d conversion accuracy ................................................................... 1-109 fig. 138 a-d conversion equivalent circuit ........................................................................... 1-112 fig. 139 a-d conversion timing chart .................................................................................... 1-112 vii 38k0 group user? manual list of figures chapter 2 application fig. 2.1.1 memory map of registers related to i/o port ........................................................... 2-2 fig. 2.1.2 structure of port pi (i = 0 to 6) ................................................................................. 2-3 fig. 2.1.3 structure of port pi direction register (i = 0 to 6) .................................................. 2-3 fig. 2.1.4 structure of port p0 pull-up control register ............................................................ 2-4 fig. 2.1.5 structure of port p5 pull-up control register ............................................................ 2-4 fig. 2.2.1 memory map of registers related to interrupt .......................................................... 2-8 fig. 2.2.2 structure of interrupt request register 1 ................................................................... 2-8 fig. 2.2.3 structure of interrupt request register 2 ................................................................... 2-9 fig. 2.2.4 structure of interrupt control register 1 .................................................................... 2-9 fig. 2.2.5 structure of interrupt control register 2 .................................................................. 2-10 fig. 2.2.6 structure of interrupt edge selection register ........................................................ 2-10 fig. 2.2.7 interrupt operation diagram ....................................................................................... 2-12 fig. 2.2.8 changes of stack pointer and program counter upon acceptance of interrupt request ............................................................................................................................... ...... 2-13 fig. 2.2.9 time up to execution of interrupt processing routine ........................................... 2-14 fig. 2.2.10 timing chart after acceptance of interrupt request ........................................... 2-14 fig. 2.2.11 interrupt control diagram ......................................................................................... 2-15 fig. 2.2.12 example of multiple interrupts ................................................................................ 2-17 fig. 2.2.13 connection example and port p0 block diagram when using key input interrupt . ............................................................................................................................... .... 2-19 fig. 2.2.14 registers setting related to key input interrupt (corresponding to figure 2.2.13) . ............................................................................................................................... .... 2-20 fig. 2.2.15 sequence of changing relevant register ............................................................... 2-21 fig. 2.2.16 sequence of check of interrupt request bit .......................................................... 2-22 fig. 2.3.1 memory map of registers related to timers ............................................................ 2-23 fig. 2.3.2 structure of prescaler 12, prescaler x ................................................................... 2-23 fig. 2.3.3 structure of timer 1 .................................................................................................. 2-24 fig. 2.3.4 structure of timer 2, timer x .................................................................................. 2-24 fig. 2.3.5 structure of timer x mode register ......................................................................... 2-25 fig. 2.3.6 structure of interrupt request register 1 ................................................................. 2-26 fig. 2.3.7 structure of interrupt request register 2 ................................................................. 2-26 fig. 2.3.8 structure of interrupt control register 1 .................................................................. 2-27 fig. 2.3.9 structure of interrupt control register 2 .................................................................. 2-27 fig. 2.3.10 timers connection and setting of division ratios ................................................. 2-29 fig. 2.3.11 related registers setting ......................................................................................... 2-29 fig. 2.3.12 control procedure ..................................................................................................... 2-30 fig. 2.3.13 peripheral circuit example ....................................................................................... 2-31 fig. 2.3.14 timers connection and setting of division ratios ................................................. 2-31 fig. 2.3.15 related registers setting ......................................................................................... 2-32 fig. 2.3.16 control procedure ..................................................................................................... 2-32 fig. 2.3.17 judgment method of valid/invalid of input pulses ............................................... 2-33 fig. 2.3.18 related registers setting ......................................................................................... 2-34 fig. 2.3.19 control procedure ..................................................................................................... 2-35 fig. 2.3.20 timers connection and setting of division ratios ................................................. 2-36 fig. 2.3.21 related registers setting ......................................................................................... 2-37 fig. 2.3.22 control procedure ..................................................................................................... 2-38 fig. 2.4.1 memory map of registers related to serial i/o ...................................................... 2-40 fig. 2.4.2 structure of transmit/receive buffer register ........................................................ 2-41 fig. 2.4.3 structure of serial i/o status register ..................................................................... 2-41 fig. 2.4.4 structure of serial i/o control register .................................................................... 2-42 fig. 2.4.5 structure of uart control register .......................................................................... 2-42 viii 38k0 group user? manual list of figures fig. 2.4.6 structure of baud rate generator ............................................................................. 2-43 fig. 2.4.7 structure of interrupt edge selection register ........................................................ 2-43 fig. 2.4.8 structure of interrupt request register 2 ................................................................. 2-44 fig. 2.4.9 structure of interrupt control register 2 .................................................................. 2-44 fig. 2.4.10 serial i/o connection examples (1) ....................................................................... 2-45 fig. 2.4.11 serial i/o connection examples (2) ....................................................................... 2-46 fig. 2.4.12 serial i/o transfer data format ............................................................................... 2-47 fig. 2.4.13 connection diagram ................................................................................................. 2-48 fig. 2.4.14 timing chart .............................................................................................................. 2-48 fig. 2.4.15 registers setting related to transmitting side ...................................................... 2-49 fig. 2.4.16 registers setting related to receiving side ........................................................... 2-50 fig. 2.4.17 control procedure of transmitting side .................................................................. 2-51 fig. 2.4.18 control procedure of receiving side ...................................................................... 2-52 fig. 2.4.19 connection diagram ................................................................................................. 2-53 fig. 2.4.20 timing chart .............................................................................................................. 2-53 fig. 2.4.22 setting of serial i/o transmission data ................................................................. 2-54 fig. 2.4.21 registers setting related to serial i/o .................................................................. 2-54 fig. 2.4.23 control procedure of serial i/o .............................................................................. 2-55 fig. 2.4.24 connection diagram ................................................................................................. 2-56 fig. 2.4.25 timing chart .............................................................................................................. 2-57 fig. 2.4.26 related registers setting ......................................................................................... 2-57 fig. 2.4.27 control procedure of master unit ........................................................................... 2-58 fig. 2.4.28 control procedure of slave unit ............................................................................. 2-59 fig. 2.4.29 connection diagram (communication using uart) ............................................ 2-60 fig. 2.4.30 timing chart (using uart) ..................................................................................... 2-60 fig. 2.4.31 registers setting related to transmitting side ...................................................... 2-62 fig. 2.4.32 registers setting related to receiving side ........................................................... 2-63 fig. 2.4.33 control procedure of transmitting side .................................................................. 2-64 fig. 2.4.34 control procedure of receiving side ...................................................................... 2-65 fig. 2.4.35 sequence of setting serial i/o control register again ......................................... 2-67 fig. 2.7.1 memory map of registers related to a-d converter .............................................. 2-71 fig. 2.7.2 structure of a-d control register .............................................................................. 2-71 fig. 2.7.3 structure of a-d conversion register 1 ................................................................... 2-72 fig. 2.7.4 structure of a-d conversion register 2 ................................................................... 2-72 fig. 2.7.5 structure of interrupt request register 2 ................................................................. 2-73 fig. 2.7.6 structure of interrupt control register 2 .................................................................. 2-73 fig. 2.7.7 connection diagram ................................................................................................... 2-74 fig. 2.7.8 related registers setting ........................................................................................... 2-74 fig. 2.7.9 control procedure for 8-bit read .............................................................................. 2-75 fig. 2.7.10 control procedure for 10-bit read .......................................................................... 2-75 fig. 2.8.1 memory map of registers related to watchdog timer ............................................ 2-77 fig. 2.8.2 structure of watchdog timer control register ......................................................... 2-77 fig. 2.8.3 structure of cpu mode register .............................................................................. 2-78 fig. 2.8.4 watchdog timer connection and division ratio setting .......................................... 2-79 fig. 2.8.5 related registers setting ........................................................................................... 2-80 fig. 2.8.6 control procedure ....................................................................................................... 2-80 fig. 2.9.1 example of poweron reset circuit ............................................................................ 2-81 fig. 2.9.2 ram backup system .................................................................................................. 2-81 fig. 2.10.1 memory map of registers related to pll .............................................................. 2-83 fig. 2.10.2 structure of usb control register .......................................................................... 2-83 fig. 2.10.3 structure of cpu mode register ............................................................................ 2-84 fig. 2.10.4 structure of pll control register ........................................................................... 2-84 ix 38k0 group user? manual list of figures fig. 2.10.5 block diagram for frequency synthesizer circuit .................................................. 2-85 fig. 2.10.6 related registers setting when hardware reset ................................................... 2-86 fig. 2.10.7 related registers setting when stop mode ........................................................... 2-87 fig. 2.10.8 related registers setting when recovery from stop mode ................................. 2-88 fig. 2.11.1 memory map of registers related to clock generating circuit ............................ 2-89 fig. 2.11.2 structure of usb control register .......................................................................... 2-89 fig. 2.11.3 structure of cpu mode register ............................................................................ 2-90 fig. 2.11.4 structure of pll control register ........................................................................... 2-90 fig. 2.11.5 related registers setting ......................................................................................... 2-91 fig. 2.11.6 related registers setting ......................................................................................... 2-93 fig. 2.12.1 memory map of registers related to standby function ........................................ 2-94 fig. 2.12.2 structure of misrg ................................................................................................. 2-94 fig. 2.12.3 oscillation stabilizing time at restoration by reset input .................................... 2-96 fig. 2.12.4 execution sequence example at restoration by occurrence of int0 interrupt request ............................................................................................................................... .... 2-98 fig. 2.12.5 reset input time ..................................................................................................... 2-100 fig. 2.13.1 memory map of flash memory version for 38k0 group ................................... 2-102 fig. 2.13.2 memory map of registers related to flash memory ........................................... 2-103 fig. 2.13.3 structure of flash memory control register ........................................................ 2-103 fig. 2.13.4 rewrite example of built-in flash memory in standard serial i/o mode ......... 2-106 fig. 2.13.5 connection example in standard serial i/o mode (1) ....................................... 2-107 fig. 2.13.6 connection example in standard serial i/o mode (2) ....................................... 2-107 fig. 2.13.7 connection example in standard serial i/o mode (3) ....................................... 2-108 fig. 2.13.8 example of rewrite system for built-in flash memory in cpu rewrite mode . 2-109 fig. 2.13.9 cpu rewrite mode beginning/release flowchart ................................................. 2-110 chapter 3 appendix fig. 3.1.1 output switching characteristics measurement circuit ............................................ 3-9 fig. 3.1.2 usb output switching characteristics measurement circuit (1) for d0- .............. 3-10 fig. 3.1.3 usb output switching characteristics measurement circuit (2) for d0+ ............. 3-10 fig. 3.1.4 output switching characteristics measurement circuit .......................................... 3-19 fig. 3.1.5 usb output switching characteristics measurement circuit (1) for d0- .............. 3-21 fig. 3.1.6 usb output switching characteristics measurement circuit (2) for d0+ ............. 3-21 fig. 3.1.7 timing chart (1) .......................................................................................................... 3-22 fig. 3.1.8 timing chart (2) .......................................................................................................... 3-23 fig. 3.1.9 timing chart (3) .......................................................................................................... 3-24 fig. 3.1.10 timing chart (4) ........................................................................................................ 3-25 fig. 3.1.11 timing chart (5) ........................................................................................................ 3-26 fig. 3.1.12 timing chart (6) ........................................................................................................ 3-27 fig. 3.3.1 sequence of changing relevant register ................................................................. 3-31 fig. 3.3.2 sequence of check of interrupt request bit ............................................................ 3-32 fig. 3.3.3 sequence of setting serial i/o control register again ........................................... 3-34 fig. 3.3.4 initialization of processor status register ................................................................ 3-38 fig. 3.3.5 sequence of plp instruction execution .................................................................. 3-38 fig. 3.3.6 stack memory contents after php instruction execution ..................................... 3-38 fig. 3.3.7 status flag at decimal calculations .......................................................................... 3-39 fig. 3.4.1 selection of packages ............................................................................................... 3-41 fig. 3.4.3 wiring for clock i/o pins ........................................................................................... 3-42 fig. 3.4.4 wiring for cnv ss pin .................................................................................................. 3-42 fig. 3.4.5 wiring for the v pp pin of the flash memory version .............................................. 3-43 fig. 3.4.6 bypass capacitor across the v ss line and the v cc line ........................................ 3-43 fig. 3.4.7 analog signal line and a resistor and a capacitor ................................................ 3-44 x 38k0 group user? manual list of figures fig. 3.4.8 wiring for a large current signal line ...................................................................... 3-45 ___________ fig. 3.4.9 wiring of reset pin ................................................................................................. 3-45 fig. 3.4.10 v ss pattern on the underside of an oscillator ...................................................... 3-46 fig. 3.4.11 setup for i/o ports ................................................................................................... 3-46 fig. 3.4.12 watchdog timer by software ................................................................................... 3-47 fig. 3.5.1 structure of port pi .................................................................................................... 3-48 fig. 3.5.2 structure of port pi direction register ..................................................................... 3-48 fig. 3.5.3 structure of usb control register ............................................................................. 3-49 fig. 3.5.4 structure of usb function enable register .............................................................. 3-49 fig. 3.5.5 structure of usb function address register ............................................................ 3-49 fig. 3.5.6 structure of frame number register low ................................................................ 3-50 fig. 3.5.7 structure of frame number register high ............................................................... 3-50 fig. 3.5.8 structure of usb interrupt source enable register ................................................ 3-50 fig. 3.5.9 structure of usb interrupt source register ............................................................. 3-51 fig. 3.5.10 structure of endpoint index register ...................................................................... 3-51 fig. 3.5.11 structure of ep00 stage register ........................................................................... 3-52 fig. 3.5.12 structure of ep01 set register ............................................................................... 3-52 fig. 3.5.13 structure of ep02 set register ............................................................................... 3-53 fig. 3.5.14 structure of ep03 set register ............................................................................... 3-53 fig. 3.5.15 structure of ep00 control register 1 ..................................................................... 3-54 fig. 3.5.16 structure of ep01 control register 1 ..................................................................... 3-54 fig. 3.5.17 structure of ep02 control register 1 ..................................................................... 3-54 fig. 3.5.18 structure of ep03 control register 1 ..................................................................... 3-55 fig. 3.5.19 structure of ep00 control register 2 ..................................................................... 3-55 fig. 3.5.20 structure of ep01 control register 2 ..................................................................... 3-55 fig. 3.5.21 structure of ep02 control register 2 ..................................................................... 3-56 fig. 3.5.22 structure of ep03 control register 2 ..................................................................... 3-56 fig. 3.5.23 structure of ep00 control register 3 ..................................................................... 3-56 fig. 3.5.24 structure of ep01 control register 3 ..................................................................... 3-57 fig. 3.5.25 structure of ep02 control register 3 ..................................................................... 3-57 fig. 3.5.26 structure of ep03 control register 3 ..................................................................... 3-57 fig. 3.5.27 structure of ep00 interrupt source register ......................................................... 3-58 fig. 3.5.28 structure of ep01 interrupt source register ......................................................... 3-59 fig. 3.5.29 structure of ep02 interrupt source register ......................................................... 3-59 fig. 3.5.30 structure of ep03 interrupt source register ......................................................... 3-60 fig. 3.5.31 structure of ep00 byte number register ............................................................... 3-60 fig. 3.5.32 structure of ep01 byte number register 0 ........................................................... 3-60 fig. 3.5.33 structure of ep02 byte number register 0 ........................................................... 3-61 fig. 3.5.34 structure of ep03 byte number register 0 ........................................................... 3-61 fig. 3.5.35 structure of ep01 byte number register 1 ........................................................... 3-61 fig. 3.5.36 structure of ep02 byte number register 1 ........................................................... 3-62 fig. 3.5.37 structure of ep03 byte number register 1 ........................................................... 3-62 fig. 3.5.38 structure of prescaler12, prescaler x .................................................................. 3-62 fig. 3.5.39 structure of timer 1 ................................................................................................ 3-63 fig. 3.5.40 structure of timer 2, timer x ................................................................................ 3-63 fig. 3.5.41 structure of timer x mode register ...................................................................... 3-64 fig. 3.5.42 structure of transmit/receive buffer register ...................................................... 3-64 fig. 3.5.43 structure of serial i/o status register ................................................................... 3-65 fig. 3.5.44 structure of exb interrupt source enable register ............................................ 3-65 fig. 3.5.45 structure of exb interrupt source register ........................................................... 3-66 fig. 3.5.46 structure of exb index register ............................................................................. 3-66 fig. 3.5.47 structure of register window 1 .............................................................................. 3-67 xi 38k0 group user? manual list of figures fig. 3.5.48 index00[low]; structure of external i/o configuration register ......................... 3-67 fig. 3.5.49 index01[low]; structure of transmit/receive buffer register .............................. 3-68 fig. 3.5.50 index02[low]; structure of memory channel operation mode register .............. 3-68 fig. 3.5.51 index03[low]; structure of memory address counter ........................................... 3-68 fig. 3.5.52 index04[low]; structure of end address register ................................................. 3-69 fig. 3.5.53 structure of register window 2 .............................................................................. 3-69 fig. 3.5.54 index00[high]; structure of external i/o configuration register ........................ 3-69 fig. 3.5.55 index03[high]; structure of memory address counter ......................................... 3-70 fig. 3.5.56 index04[high]; structure of end address register ................................................ 3-70 fig. 3.5.57 structure of a-d control register ............................................................................ 3-70 fig. 3.5.58 structure of a-d conversion register 1 ................................................................. 3-71 fig. 3.5.59 structure of a-d conversion register 2 ................................................................. 3-71 fig. 3.5.60 structure of watchdog timer control register ....................................................... 3-72 fig. 3.5.61 structure of cpu mode register ............................................................................ 3-72 fig. 3.5.62 structure of interrupt request register 1 ............................................................... 3-73 fig. 3.5.63 structure of interrupt request register 2 ............................................................... 3-73 fig. 3.5.64 structure of interrupt control register 1 ................................................................ 3-74 fig. 3.5.65 structure of interrupt control register 2 ................................................................ 3-74 fig. 3.5.66 structure of serial i/o control register .................................................................. 3-75 fig. 3.5.67 structure of uart control register ........................................................................ 3-75 fig. 3.5.68 structure of baud rate generator ........................................................................... 3-76 fig. 3.5.69 structure of ep01 max. packet size register ...................................................... 3-76 fig. 3.5.70 structure of ep02 max. packet size register ...................................................... 3-76 fig. 3.5.71 structure of ep03 max. packet size register ...................................................... 3-77 fig. 3.5.72 structure of ep00 buffer area set register ........................................................... 3-77 fig. 3.5.73 structure of ep01 buffer area set register ........................................................... 3-77 fig. 3.5.74 structure of ep02 buffer area set register ........................................................... 3-78 fig. 3.5.75 structure of ep03 buffer area set register ........................................................... 3-78 fig. 3.5.76 structure of port p0 pull-up control register ........................................................ 3-79 fig. 3.5.77 structure of port p5 pull-up control register ........................................................ 3-79 fig. 3.5.78 structure of interrupt edge selection register ...................................................... 3-80 fig. 3.5.79 structure of pll control register ........................................................................... 3-80 fig. 3.5.80 structure of misrg ................................................................................................. 3-81 fig. 3.5.81 structure of flash memory control register .......................................................... 3-81 xii 38k0 group user? manual list of tables list of tables chapter 1 hardware table 1. pin description ............................................................................................................... 1-4 table 2. list of 38k0 group products (standard) .................................................................... 1-6 table 3. list of 38k0 group products (l version) ................................................................... 1-6 table 4 push and pop instructions of accumulator or processor status register ............... 1-8 table 5 set and clear instructions of each bit of processor status register ....................... 1-9 table 6 i/o ports functions ....................................................................................................... 1-13 table 7 interrupt vector addresses and priority ..................................................................... 1-17 table 8 usb interrupt sources ................................................................................................. 1-30 table 9 summary of 38k0 group? flash memory version ................................................... 1-82 table 10 list of software commands (cpu rewrite mode) .................................................. 1-87 table 11 definition of each bit in status register .................................................................. 1-89 table 12 description of pin function (standard serial i/o mode) ....................................... 1-95 table 13 software commands (standard serial i/o mode) .................................................. 1-97 table 14 status register (srd) .............................................................................................. 1-104 table 15 status register 1 (srd1) ........................................................................................ 1-104 table 16 relative formula for a reference voltage vref of a-d converter and vref ... 1-111 table 17 change of a-d conversion register during a-d conversion .............................. 1-111 chapter 2 application table 2.1.1 handling of unused pins .......................................................................................... 2-5 table 2.2.1 interrupt sources, vector addresses and priority of 38k0 group ...................... 2-11 table 2.2.2 list of interrupt bits according to interrupt source ............................................. 2-16 table 2.3.1 cntr 0 active edge selection bit function ............................................................ 2-25 table 2.4.1 setting examples of baud rate generator values and transfer bit rate values 2-61 table 2.10.1 pll operation mode selection bits setting example ........................................ 2-85 table 2.10.2 usb clock division ratio selection bits setting example .................................. 2-86 table 2.11.1 example of internal clock f(f) generation using main clock f(x in ) .................. 2-91 table 2.11.2 example of internal clock f(f) generation using fsyn ..................................... 2-92 table 2.12.1 state in stop mode ............................................................................................... 2-95 table 2.12.2 state in wait mode ................................................................................................ 2-99 table 2.13.1 setting of programmers when parallel programming ..................................... 2-104 table 2.13.2 connection example to flash programmer when serial programming (4 wires).. ............................................................................................................................. 2- 104 table 2.13.3 setting condition in serial i/o mode ............................................................... 2-106 xiii 38k0 group user? manual list of tables chapter 3 appendix table 3.1.1 absolute maximum ratings ....................................................................................... 3-2 table 3.1.2 recommended operating conditions (vcc = 4.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) ........................................................................... 3-3 table 3.1.3 recommended operating conditions (vcc = 4.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) ........................................................................... 3-4 table 3.1.4 electrical characteristics (1) (vcc = 4.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) ........................................................................................... 3-5 table 3.1.5 electrical characteristics (2) (vcc = 4.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) ........................................................................................... 3-6 table 3.1.6 a-d converter characteristics (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85?, unless otherwise noted) ........................................................................................... 3-7 table 3.1.7 timing requirements (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ........................................................................................................ 3-8 table 3.1.8 timing requirements of external bus interface (exb)8 (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ........................................... 3-8 table 3.1.9 switching characteristics (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ........................................................................................... 3-9 table 3.1.10 switching characteristics of external bus interface (exb) (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) .................................. 3-9 table 3.1.11 switching characteristics (usb ports) (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ..................................................................... 3-10 table 3.1.12 recommended operating conditions (vcc = 3.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) ....................................................................... 3-11 table 3.1.13 recommended operating conditions (vcc = 3.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) ....................................................................... 3-12 table 3.1.14 electrical characteristics (1) (vcc = 3.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) ....................................................................................... 3-13 table 3.1.15 electrical characteristics (2) (vcc = 3.00 to 5.25 v, vss = 0 v, ta = ?0 to 85?, unless otherwise noted) ....................................................................................... 3-14 table 3.1.16 a-d converter characteristics (v cc = 3.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85?, unless otherwise noted) ....................................................................................... 3-15 table 3.1.17 timing requirements (1) (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ....................................................................................... 3-16 table 3.1.18 timing requirements (2) (v cc = 3.00 to 4.00 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ....................................................................................... 3-16 table 3.1.19 timing requirements of external bus interface (exb) (1) (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ................................ 3-17 table 3.1.20 timing requirements of external bus interface (exb) (2) (v cc = 3.00 to 4.00 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ....................................... 3-18 table 3.1.21 switching characteristics (1) (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ....................................................................................... 3-19 table 3.1.22 switching characteristics (2) (v cc = 3.00 to 4.00 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ....................................................................................... 3-19 table 3.1.23 switching characteristics of external bus interface (exb) (1) (v cc = 4.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ........................... 3-20 table 3.1.24 switching characteristics of external bus interface (exb) (2) (v cc = 3.00 to 4.00 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ........................... 3-20 table 3.1.25 switching characteristics (usb ports) (v cc = 3.00 to 5.25 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ..................................................................... 3-21 chapter 1 hardware description features pin configuration functional block pin description part numbering group expansion functional description notes on programming notes on usage data required for mask orders functional description supplement hardware 1-2 38k0 group user? manual description the 38k0 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 38k0 group has the usb function, an 8-bit bus interface, a serial i/o, three 8-bit timers, and an 8-channel 10-bit a-d con- verter, which are available for the pc peripheral i/o device. the various microcomputers in the 38k0 group include variations of internal memory size and packaging. for details, refer to the section on part numbering. features basic machine-language instructions ....................................... 71 the minimum instruction execution time .......................... 0.25 ? (at 8 mhz system clock ? ) system clock ? : reference frequency to internal circuit except usb function memory size rom ................................................................ 16 k to 32 k bytes ram ............................................................... 1024 to 2048 bytes programmable input/output ports ............................................. 48 software pull-up resistors interrupts .................................................. 15 sources, 15 vectors usb function (full-speed usb2.0 specification) ...... 4 endpoints external bus interface ....................................... 8-bit ? 1 channel timers ............................................................................. 8-bit ? 3 watchdog timer ............................................................. 16-bit ? 1 serial i/o ...................... 8-bit ? 1 (uart or clock-synchronized) a-d converter ................................................ 10-bit ? 8 channels (8-bit reading available) led direct drive port ................................................................... 4 clock generating circuit (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage (standard) system clock/internal clock division mode at 8 mhz/through mode ( = 8 mhz) ................... 4.00 to 5.25 v at 6 mhz/through mode ( = 6 mhz) ................... 4.00 to 5.25 v power source voltage (l version) system clock/internal clock division mode at 12 mhz/through mode ( = 12 mhz) (under planning) .......... ................... 4.50 to 5.25 v at 12 mhz/2-divide mode( = 6 mhz) ................... 4.00 to 5.25 v at 8 mhz/through mode ( = 8 mhz) ................... 4.00 to 5.25 v at 6 mhz/through mode ( = 6 mhz) ................... 3.00 to 5.25 v power dissipation at 5 v power source voltage .................................. 125 mw (typ.) (at 8 mhz system clock, in through mode) at 3.3 v power source voltage ................................ 30 mw (typ.) (at 6 mhz system clock, in through mode) operating temperature range .................................... ?0 to 85? packages fp ........................................ 64p6u-a (64-pin 14 ? 14 mm lqfp) hp ........................................ 64p6q-a (64-pin 10 ? 10 mm lqfp) notes the specifications of this product are subject to change because it is under development. inquire the use of mitsubishi electric cor- poration. package type : 64p6u-a/64p6q-a fig. 1 pin configuration of 38k0 group pin configuration (top view) 32 31 30 29 28 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 27 64 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 tron p2 3 p2 2 p2 1 p2 0 d0- d0+ usbv ref dv cc pv cc p0 3 p0 2 p0 1 p0 0 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 /int 1 p5 1 /cntr 0 p5 0 /int 0 pv ss p1 0 /dq 0 /an 0 p0 6 p0 7 p4 0 /e x dreq/r x d p1 1 /dq 1 /an 1 p1 2 /dq 2 /an 2 p1 3 /dq 3 /an 3 p1 4 /dq 4 /an 4 p1 5 /dq 5 /an 5 p1 6 /dq 6 /an 6 p1 7 /dq 7 /an 7 p6 0 (led 0 ) p6 1 (led 1 ) p6 2 (led 2 ) p6 3 (led 3 ) p4 1 /e x dack/t x d p4 2 /e x tc/s clk p4 3 /e x a1/s rdy p3 0 p3 1 p3 2 p3 3 /e x int p3 4 /e x cs p3 5 /e x wr p3 6 /e x rd p3 7 /e x a0 m38k07m4-xxxfp/hp m38k09f8fp/hp p2 4 p0 4 p2 7 p2 6 cnv ss v cc e v ref v ss x out v cc cnv ss 2 x in reset p2 5 p0 5 m38k07m4l-xxxfp/hp m38k09f8lfp/hp description/features/pin configuration 1-3 38k0 group user s manual hardware functional block diagram (package : 64p6u-a/64p6q-a) fig. 2 functional block diagram c n t r 0 v s s r e s e t v c c x i n w a t c h d o g t i m e r t i m e r x ( 8 ) t i m e r 1 ( 8 ) t i m e r 2 ( 8 ) x o u t c l o c k g e n e r a t i n g c i r c u i t r a m d a t a b u s c p u r a m i / f r o m c n v s s c n v s s 2 p v c c p v s s p 5 ( 8 ) i n t 1 i n t 0 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 p 6 ( 4 ) 1 6 1 7 1 8 1 9 p 4 ( 4 ) s i / o e x t b u s ( 8 ) p 3 ( 8 ) 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 d 0 + u s b d 0 - t r o n u s b v r e f d v c c 2 2 2 3 2 4 2 6 2 5 p 0 ( 8 ) 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 v r e f p 1 ( 8 ) 1 0 - b i t a - d c o n v e r t e r ( 8 ) 1 0 6 3 6 4 1 2 3 4 5 6 2 0 2 1 1 2 1 3 1 1 1 4 8 7 1 5 p 2 ( 8 ) 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 v c c e 9 functional block functional block hardware 1-4 38k0 group user s manual pin description table 1. pin description function apply voltage of 4.0 v 5.25v (standard) or 3.0 v 5.25 v (l version) to v cc , and 0 v to v ss . power source pin for ports p1, p3, p4 and analog circuit. connect this pin to v cc . this pin controls the operation mode of the chip. connect this pin to v ss . in the flash memory mode, this pin becoems v pp power source input pin. this pin controls the operation mode of the chip. connect this pin to v ss . reference voltage input pin for a-d converter. power source pin for analog circuit. connect the dv cc and pv cc pins to v cc , and the pv ss pin to v ss . reset input pin for active l input and output pins for the main clock generating circuit. connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. power source pin for usb port circuit. in vcc = 4.00 to 5.25 v use the built-in usb reference voltage circuit. in vcc = 3.60 to 4.00 v apply 3.3 v power supply from the external because use of the built-in usb reference voltage circuit is prohibited in this voltage range. in vcc = 3.00 to 3.60 v connect this pin to v cc because use of the built-in usb reference voltage circuit is prohibited in this voltage range. output pin to pull-up d0+ by 1.5 k ? usb upstream i/o port usb input level usb output level output structure 8-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure pull-up control is enabled. 8-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure 8-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure 8-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure 4-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure 8-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure 4-bit i/o port i/o direction register allows each pin to be individually programmed as either input or output. cmos compatible input level cmos 3-state output structure output large current for led drive is enabled. key input pins (key-on wake up interrupt) a-d converter input pins external bus interface function pins external bus interface function pins serial i/o function pins external bus interface function pins interrupt input pin timer x funciton pin interrupt input pin pin v cc , v ss v cc e cnv ss cnv ss 2 v ref dv cc pv cc , pv ss reset x in x out usbv ref tron d0+, d0- p0 0 p0 7 p1 0 /dq 0 /an 0 p1 7 /dq 7 /an 7 p2 0 p2 7 p3 0 p3 2 p3 3 /exint p3 4 /excs p3 5 /exwr p3 6 /exrd p3 7 /exa0 p4 0 /exdreq/rxd p4 1 /exdack/txd p4 2 /extc/s clk p4 3 /exa1/s rdy p5 0 /int 0 p5 1 /cntr 0 p5 2 /int 1 p5 3 p5 7 p6 0 p6 3 name power source analog power source cnv ss cnv ss 2 analog reference voltage input analog power source reset input clock input clock output usb reference power source usb reference voltage output usb upstream i/o i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p4 i/o port p5 i/o port p6 function except a port function pin description 1-5 38k0 group user s manual hardware part numbering fig. 3 part numbering m 3 8 k0 7 m 4 - x x x f p product rom/prom size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes the first 128 bytes and the last 2 bytes of rom are reserved areas ; they cannot be used as a user s rom area. however, they can be programmed or erased in the flash memory version, so that users can use them. memory type m : mask rom version f : flash memory version ram size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes rom number omitted in the flash memory version. : s t a n d a r d o m i t t e d i n t h e f l a s h m e m o r y v e r s i o n . p a c k a g e t y p e f p : 6 4 p 6 u - a p a c k a g e h p : 6 4 p 6 q - a p a c k a g e 9 : 3 6 8 6 4 b y t e s a : 4 0 9 6 0 b y t e s b : 4 5 0 5 6 b y t e s c : 4 9 1 5 2 b y t e s d : 5 3 2 4 8 b y t e s e : 5 7 3 4 4 b y t e s f : 6 1 4 4 0 b y t e s part numbering hardware 1-6 38k0 group user? manual group expansion mitsubishi plans to expand the 38k0 group as follows. memory type support for mask rom and flash memory versions. memory size flash memory size .......................................................... 32 kbytes mask rom size ............................................................... 16 kbytes ram size .......................................................... 1024 to 2048 bytes packages 64p6u-a .................................. 0.8 mm-pitch plastic molded lqfp 64p6q-a .................................. 0.5 mm-pitch plastic molded lqfp 100d0m ........................... 0.65 mm-pitch metal seal piggy back memory expansion plan fig. 4 memory expansion plan as of december 2002 remarks package 64p6u-a 64p6q-a 64p6u-a 64p6q-a 100d0m product m38k07m4-xxxfp m38k07m4-xxxhp m38k09f8fp M38K09F8HP m38k09rfs ram size (bytes) 1024 2048 2048 16384 (16254) rom size (bytes) rom size for user in ( ) 32768 (32638) mask rom version flash memory version emulator mcu (for program evaluation) 256 512 1,024 2,048 8k 16k 32k 60k rom size (bytes) ram size (bytes) products under development or planning: the development schedule and specification may be revised without notice. m38k09f8l : under development : mass production m38k09f8 m38k07m4l m38k07m4 currently products are listed below. table 2. list of 38k0 group products (standard) table 3. list of 38k0 group products (l version) as of december 2002 remarks package 64p6u-a 64p6q-a 64p6u-a 64p6q-a 100d0m product m38k07m4l-xxxfp m38k07m4l-xxxhp m38k09f8lfp m38k09f8lhp m38k09rfs ram size (bytes) 1024 2048 2048 16384 (16254) rom size (bytes) rom size for user in ( ) 32768 (32638) mask rom version flash memory version use of standard product only group expansion 1-7 38k0 group user s manual hardware functional description functional description central processing unit (cpu) the 38k0 group uses the standard 740 family instruction set. re- fer to the table of 740 family addressing modes and machine instructions or the 740 family software manual for details on the instruction set. machine-resident 740 family instructions are as follows: the fst and slw instruction cannot be used. the stp, wit, mul, and div instruction can be used. the cpu has the 6 registers. the register structure is shown in figure 5. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the contents of the stack pointer. the high-order 8 bits of the stack address are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . figure 6 shows the store and the return movement into the stack. if there are registers other than those described in figure 5, the users need to store them with the program. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 5 740 family cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag hardware 1-8 38k0 group user s manual functional description table 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 6 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) 1 m ( s )( p c l ) execute rts (pc l )m (s) (s) (s) 1 ( s ) ( s ) + 1 (s) (s) + 1 (pc h )m (s) subroutine pop return address from stack p u s h r e t u r n a d d r e s s o n s t a c k m (s) (ps) execute rti (ps) m (s) ( s ) ( s ) 1 (s) (s) + 1 i n t e r r u p t s e r v i c e r o u t i n e pop contents of processor status register from stack m (s) (pc h ) (s) 1 m ( s )( p c l ) ( s ) ( s ) 1 (pc l )m (s) (s) (s) + 1 (s) (s) + 1 (pc h )m (s) p o p r e t u r n a d d r e s s f r o m s t a c k i flag is set from 0 to 1 fetch the jump vector p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0 1-9 38k0 group user s manual hardware functional description [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide mcu operation. branch opera- tions can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed between accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled between memory locations. bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 5 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag hardware 1-10 38k0 group user s manual functional description [cpu mode register (cpum)] 003b 16 the cpu mode register contains the stack page selection bit and the internal system clock selection bit. the cpu mode register is allocated at address 003b 16 . fig. 7 structure of cpu mode register p r o c e s s o r m o d e b i t s b 1b 0 00 : s i n g l e - c h i p m o d e 01 : 10 : n o t a v a i l a b l e 11 : s t a c k p a g e s e l e c t i o n b i t 0 : 0 p a g e 1 : 1 p a g e n o t u s e d ( r e t u r n s 1 w h e n r e a d ) ( d o n o t w r i t e 0 t o t h i s b i t ) n o t u s e d ( r e t u r n s 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t ) s y s t e m c l o c k s e l e c t i o n b i t 0 : m a i n c l o c k ( x i n ) 1 : f s y n s y s t e m c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b 7b 6 00 : 1-11 38k0 group user s manual hardware functional description memory special function register (sfr) area the special function register area in the zero page contains con- trol registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is user area for storing programs. in the flash memory version, program and erase can be performed in the reserved area. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 8 memory map diagram 1 9 2 2 5 6 3 8 4 5 1 2 6 4 0 7 6 8 8 9 6 1 0 2 4 1 5 3 6 2 0 4 8 00 ff 16 013f 16 01bf 16 023f 16 02bf 16 033f 16 03bf 16 043f 16 063f 16 083f 16 ram area r a m s i z e ( b y t e s ) a d d r e s s x x x x 1 6 409 6 819 2 1228 8 1638 4 2048 0 2457 6 2867 2 3276 8 3686 4 4096 0 4505 6 4915 2 5324 8 5734 4 6144 0 f 000 16 e000 16 d000 16 c000 16 b000 16 a000 16 9000 16 8000 16 7000 16 6000 16 5000 16 4000 16 3000 16 2000 16 1000 16 f 080 16 e080 16 d080 16 c080 16 b080 16 a080 16 9080 16 8080 16 7080 16 6080 16 5080 16 4080 16 3080 16 2080 16 1080 16 rom area rom s i ze (bytes) a d d r e s s y y y y 1 6 a d d r e s s z z z z 1 6 0100 16 0000 16 0040 16 0 fe 0 16 ff 00 16 ffdc 16 f f f e 1 6 ffff 16 xxxx 16 yyyy 16 zzzz 16 ram r o m s f r a r e a n ot use d i n t e r r u p t v e c t o r a r e a r eserve d rom area (128 bytes) z e r o p a g e s pec i a l page r e s e r v e d r o m a r e a 0 fff 16 s f r a r e a hardware 1-12 38k0 group user? manual functional description fig. 9 memory map of special function register (sfr) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 0 0 2 a 1 6 0 0 2 b 1 6 002 c 16 002 d 16 0 0 2 e 1 6 0 0 2 f 1 6 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 0 0 3 a 1 6 0 0 3 b 1 6 003 c 16 003 d 16 0 0 3 e 1 6 003 f 16 0000 16 0 0 0 1 1 6 0 0 0 2 1 6 0003 16 0 0 0 4 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0009 16 0 0 0 a 1 6 000 b 16 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0010 16 0 0 1 1 1 6 0012 16 0 0 1 3 1 6 0014 16 0 0 1 5 1 6 0016 16 0017 16 0018 16 0019 16 001 a 16 0 0 1 b 1 6 0 0 1 c 1 6 001 d 16 001 e 16 0 0 1 f 1 6 p o r t p 0 ( p 0 ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 4 ( p 4 ) p ort p 4 di rect i on reg i ster (p 4 d) p o r t p 5 ( p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( p 5 d ) p ort p 6 (p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) s er i a l i / o status reg i ster (siosts) i nterrupt contro l reg i ster 2 (icon 2 ) t ransm i t/ r ece i ve b u ff er reg i ster (tb/rb) cpu mo d e reg i ster (cpum) i nterrupt request reg i ster 1 (ireq 1 ) i nterrupt request reg i ster 2 (ireq 2 ) i nterrupt contro l reg i ster 1 (icon 1 ) p resca l er 12 (pre 12 ) ti mer 2 (t 2 ) p resca l er x (prex) ti mer x (tx) ti mer 1 (t 1 ) ti mer x mo d e reg i ster (tm) a - d contro l reg i ster (adcon) a - d convers i on reg i ster 1 (ad 1 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p ort p 3 di rect i on reg i ster (p 3 d) r eserve d (n ote ) r e s e r v e d ( n o t e ) u s b c o n t r o l r e g i s t e r ( u s b c o n ) u s b f u n c t i o n e n a b l e r e g i s t e r ( u s b a e ) usb f unct i on a dd ress reg i ster (usba 0 ) e n d p o i n t i n d e x r e g i s t e r ( u s b i n d e x ) e n d p o i n t f i e l d r e g i s t e r 1 ( e p x x r e g 1 ) e n d po i nt fi e ld reg i ster 2 (epxxreg 2 ) e n d p o i n t f i e l d r e g i s t e r 3 ( e p x x r e g 3 ) e n d p o i n t f i e l d r e g i s t e r 4 ( e p x x r e g 4 ) e n d p o i n t f i e l d r e g i s t e r 5 ( e p x x r e g 5 ) e n d po i nt fi e ld reg i ster 6 (epxxreg 6 ) e n d p o i n t f i e l d r e g i s t e r 7 ( e p x x r e g 7 ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) f r a m e n u m b e r r e g i s t e r l o w ( f n u m l ) f r a m e n u m b e r r e g i s t e r h i g h ( f n u m h ) u s b i n t e r r u p t s o u r c e e n a b l e r e g i s t e r ( u s b i c o n ) u s b i n t e r r u p t s o u r c e r e g i s t e r ( u s b i r e q ) e x b i n t e r r u p t s o u r c e e n a b l e r e g i s t e r ( e x b i c o n ) e xb i n t e r r u p t s o u r c e r e g i s t e r ( e x b i r e q ) r eserve d (n ote ) exb i n d ex reg i ster (exbindex) e x b f i e l d r e g i s t e r 1 ( e x b r e g 1 ) e x b f i e l d r e g i s t e r 2 ( e x b r e g 2 ) a - d convers i on reg i ster 2 (ad 2 ) watchdog timer control register (wdtcon) r eserve d (n ote ) 0 fe 0 16 0 f e 1 1 6 0 fe 2 16 0 f e 3 1 6 0 f e 4 1 6 0 fe 5 16 0 f e 6 1 6 0 f e 7 1 6 0 fe 8 16 0 f e 9 1 6 0 fea 16 fl as h memory contro l reg i ster (fmcr) p l l c o n t r o l r e g i s t e r ( p l l c o n ) p ort p 5 pu ll -up contro l reg i ster (pull 5 ) e n d po i nt fi e ld reg i ster 8 (epxxreg 8 ) e n d po i nt fi e ld reg i ster 9 (epxxreg 9 ) s e r i a l i / o c o n t r o l r e g i s t e r ( s i o c o n ) uart contro l reg i ster (uartcon) b a u d r a t e g e n e r a t o r ( b r g ) p o r t p 0 p u l l - u p c o n t r o l r e g i s t e r ( p u l l 0 ) interrupt edge selection register (intedge) r e s e r v e d ( n o t e ) 0 f e b 1 6 0 f e c 1 6 0 f e d 1 6 0 fee 16 0 f e f 1 6 0 f f 0 1 6 0 ff 1 16 0 f f 2 1 6 0 f f 3 1 6 0 ff 4 16 0 f f 5 1 6 0 ff 6 16 0 ff 7 16 0 ff 8 16 0 ff 9 16 0 ffa 16 0 ffb 16 0 f f c 1 6 0 f f d 1 6 0 ffe 16 0 f f f 1 6 r eserve d (n ote ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r eserve d (n ote ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r eserve d (n ote ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) m i s r g r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) r eserve d (n ote ) r e s e r v e d ( n o t e ) r e s e r v e d ( n o t e ) n o t e : d o n o t w r i t e a n y d a t a t o t h e s e a d d r e s s e s , b e c a u s e t h e s e a r e a s a r e r e s e r v e d . r e s e r v e d ( n o t e ) 1-13 38k0 group user s manual hardware functional description i/o ports the i/o ports have direction registers which determine the input/ output direction of each individual pin. each bit in a direction reg- ister corresponds to one pin, and each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin be- comes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are floating. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. table 6 i/o ports functions related sfrs port p0 pull-up control register a-d control register exb control register exb control register exb control register serial i/o control register exb control register serial i/o control register exb control register serial i/o control register exb control register serial i/o control register exb control register port p5 pull-up control register interrupt edge selection register timer x mode register input/output input/output, individual bits name port p0 port p1 port p2 port p3 port p4 port p5 port p6 pin p0 0 p0 7 p1 0 p1 7 p2 0 p2 7 p3 0 p3 2 p3 3 /e x int p3 4 /e x cs p3 5 /e x wr p3 6 /e x rd p3 7 /e x a0 p4 0 /rxd/ exdreq p4 1 /txd/ exdack p4 2 /s clk / extc p4 3 /s rdy / exa1 p5 0 /int 0 p5 2 /int 1 p5 1 /cntr 0 p5 3 p5 7 p6 0 p6 3 non-port function key-on wake up a-d conversion input external bus interface funciton i/o external bus interface funciton output external bus interface funciton input serial i/o input external bus interface funciton output serial i/o output external bus interface funciton input serial i/o i/o external bus interface funciton input serial i/o output external bus interface funciton input external interrupt input timer x function i/o i/o format cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output (power source is v cc e) cmos compatible input level cmos 3-state output cmos compatible input level cmos 3-state output (power source is vcce) cmos compatible input level cmos 3-state output diagram no. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) note: make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate poten- tial, a current will flow from v cc to v ss through the input-stage gate. hardware 1-14 38k0 group user s manual functional description fig. 10 port block diagram (1) ( 4 ) p o r t s p 3 0 p 3 2 ( 1 ) p o r t p 0 d a t a b u s p o r t l a t c h k e y - o n w a k e - u p i n p u t p u l l - u p c o n t r o l b i t ( 5 ) p o r t p 3 3 e x i n t o u t p u t ( 6 ) p o r t s p 3 4 , p 3 5 , p 3 6 , p 3 7 e x c s ( p 3 4 ) e x w r ( p 3 5 ) e x r d ( p 3 6 ) e x a 0 ( p 3 7 ) ( 2 ) p o r t p 1 analog input pin selection bit a - d c o n v e r s i o n i n p u t e x o e e x t e r n a l b u s i n t e r f a c e e n a b l e b i t o u t p u t b u f f e r i n p u t b u f f e r ( 3 ) p o r t p 2 d i r e c t i o n r e g i s t e r e x b d a t a o u t p u t e x b d a t a i n p u t v c c e v c c e v c c e v cc e d a t a b u s p o r t l a t c h d i r e c t i o n r e g i s t e r d a t a b u s p o r t l a t c h direction register d a t a b u sp o r t l a t c h d i r e c t i o n r e g i s t e r e x t e r n a l b u s i n t e r f a c e e n a b l e b i t port latch d a t a b u s d i r e c t i o n r e g i s t e r external bus interface enable bit e x t e r n a l b u s i n t e r f a c e e n a b l e b i t d a t a b u sp o r t l a t c h direction register 1-15 38k0 group user s manual hardware functional description fig. 11 port block diagram (2) e x d r e q o u t p u t s e r i a l i / o i n p u t e x d a c k s e r i a l i / o e n a b l e b i t e x t c serial i/o synchronous clock selection bit e x a 1 cntr 0 interrupt input pulse output mode int 0 (p5 0 ), int 1 (p5 2 ) interrupt input v cc e v c c e v cc e v c c e s r d y o u t p u t e n a b l e b i t ( 7 ) p o r t p 4 0 d i r e c t i o n r e g i s t e r direction register d i r e c t i o n r e g i s t e r direction register p o r t l a t c h port latch p o r t l a t c h p o r t l a t c h p o r t l a t c h port latch p o r t l a t c h p o r t l a t c h direction register d i r e c t i o n r e g i s t e r direction register d i r e c t i o n r e g i s t e r d a t a b u s d a t a b u s data bus data bus d a t a b u s data bus d a t a b u s d a t a b u s serial i/o output ( 8 ) p o r t p 4 1 (9) port p4 2 ( 1 0 ) p o r t p 4 3 (11) ports p5 0, p5 2 (12) port p5 1 (13) ports p5 3 p5 7 (14) port p6 serial i/o enable bit serial i/o enable bit s e r i a l i / o e n a b l e b i t e x t e r n a l b u s i n t e r f a c e e n a b l e b i t e x t e r n a l b u s i n t e r f a c e e n a b l e b i t e x t e r n a l b u s i n t e r f a c e e n a b l e b i t e x t e r n a l b u s i n t e r f a c e e n a b l e b i t external bus interface enable bit e x t e r n a l b u s i n t e r f a c e e n a b l e b i t e x t e r n a l b u s i n t e r f a c e e n a b l e b i t receive enable bit r e c e i v e e n a b l e b i t pull-up control bit serial i/o mode selection bit s e r i a l i / o m o d e s e l e c t i o n b i t timer output s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t s e r i a l i / o o u t p u t s e r i a l i / o e x t e r n a l c l o c k i n p u t serial i/o clock output serial i/o enable bit hardware 1-16 38k0 group user s manual functional description fig. 12 structure of port i/o-related registers p 0 0 pu ll -up contro l bi t 0 : no pull-up 1 : pull-up p0 1 pull-up control bit 0 : no pull-up 1 : pull-up p0 2 pull-up control bit 0 : no pull-up 1 : pull-up p0 3 pull-up control bit 0 : no pull-up 1 : pull-up p0 4 pull-up control bit 0 : no pull-up 1 : pull-up p0 5 pull-up control bit 0 : no pull-up 1 : pull-up p0 6 pull-up control bit 0 : no pull-up 1 : pull-up p0 7 pull-up control bit 0 : no pull-up 1 : pull-up p ort p 0 pu ll -up contro l reg i ster (pull0 : address 0ff0 16 ) b 7 b 0 p 5 0 pu ll -up contro l bi t 0 : no pull-up 1 : pull-up nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are 0 . p5 2 pull-up control bit 0 : no pull-up 1 : pull-up nothing is arranged for these bits. these are write disabled bits. when these bits are read out, the contents are 0 . p ort p 5 pu ll -up contro l reg i ster (pull5 : address 0ff2 16 ) b 7 b 0 1-17 38k0 group user s manual hardware functional description interrupt request generating conditions at reset at detection of usb bus reset signal (2.5 (note 4) at completion of serial i/o data reception at completion of serial i/o data transmission at detection of either rising or falling edge of cntr 0 input at falling of conjunction of input level for port p0 (at input mode) at completion of a-d conversion at brk instruction execution notes 1 : vector addresses contain interrupt jump destination addresses. 2 : reset function in the same way as an interrupt with the highest priority. 3 : nothing is arranged in these vector addresses. 4 : fix bit 1 of interrupt control register 2 (address 003f 16 ) to 0 . interrupts i nterrupts occur by fifteen sources: four external, ten internal, and one software. interrupt control each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the brk instruction. an interrupt occurs if the corre- sponding interrupt request and enable bits are 1 and the inter- rupt disable flag is 0 . interrupt enable bits can be set or cleared by software. interrupt request bits can be cleared by software, but cannot be set by software. the brk instruction cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruction interrupt. when several interrupts occur at the same time, the interrupts are received according to priority. interrupt operation by acceptance of an interrupt, the following operations are auto- matically performed: 1. the contents of the program counter and the processor status register are automatically pushed onto the stack. 2. the interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. the interrupt jump destination address is read from the vector table into the program counter. interrupt source reset (note 2) usb bus reset usb sof usb device external bus int 0 timer x timer 1 timer 2 int 1 (note 3) serial i/o reception serial i/o transmission cntr 0 key-on wake up a-d conversion brk instruction low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 table 7 interrupt vector addresses and priority priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vector addresses (note 1) notes on interrupts when setting the followings, the interrupt request bit may be set to 1 . when switching external interrupt active edge related register: interrupt edge selection register (address 0ff3 16 ), timer x mode register (address 0023 16 ) when not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ? 0 (disabled). ? ? 0 after 1 or more instructions have been executed. ? 1 (enabled). hardware 1-18 38k0 group user? manual functional description fig. 13 interrupt control fig. 14 structure of interrupt-related registers i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t i n t e r r u p t d i s a b l e f l a g ( i ) b r k i n s t r u c t i o n r e s e t i n t e r r u p t r e q u e s t b 7 b 0 i n t e r r u p t e d g e s e l e c t i o n r e g i s t e r i n t 0 i n t e r r u p t e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) i n t 1 i n t e r r u p t e d g e s e l e c t i o n b i t n o t u s e d ( r e t u r n 0 w h e n r e a d ) ( i n t e d g e : a d d r e s s 0 f f 3 1 6 ) i n t e r r u p t r e q u e s t r e g i s t e r 1 usb b us reset i nterrupt request bi t usb sof interrupt request bit usb device interrupt request bit exb interrupt request bit int 0 interrupt request bit timer x interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit 0 : n o i nterrupt request i ssue d 1 : interrupt request issued (ireq 1 : a dd ress 003 c 16 ) 0 : f a lli ng e d ge act i ve 1 : rising edge active b 7 b 0 i n t e r r u p t r e q u e s t r e g i s t e r 2 i n t 1 i n t e r r u p t r e q u e s t b i t n o t h i n g i s a r r a n g e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e c o n t e n t s a r e 0 . s e r i a l i / o r e c e i v e i n t e r r u p t r e q u e s t b i t s e r i a l i / o t r a n s m i t i n t e r r u p t r e q u e s t b i t c n t r 0 i n t e r r u p t r e q u e s t b i t k e y - o n w a k e - u p i n t e r r u p t r e q u e s t b i t a - d c o n v e r s i o n i n t e r r u p t r e q u e s t b i t n o t h i n g i s a r r a n g e d f o r t h i s b i t . t h i s i s a w r i t e d i s a b l e d b i t . w h e n t h i s b i t i s r e a d o u t , t h e c o n t e n t s a r e 0 . (ireq 2 : a dd ress 003 d 16 ) b 7 b 0 i nterrupt contro l reg i ster 1 (icon 1 : a dd ress 003 e 16 ) b 7 b 0 u s b b u s r e s e t i n t e r r u p t e n a b l e b i t u s b s o f i n t e r r u p t e n a b l e b i t u s b d e v i c e i n t e r r u p t e n a b l e b i t e x b i n t e r r u p t e n a b l e b i t i n t 0 i n t e r r u p t e n a b l e b i t t i m e r x i n t e r r u p t e n a b l e b i t t i m e r 1 i n t e r r u p t e n a b l e b i t t i m e r 2 i n t e r r u p t e n a b l e b i t ? 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . ? 0 c a n b e s e t b y s o f t w a r e , b u t 1 c a n n o t b e s e t . i nterrupt contro l reg i ster 2 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d (icon 2 : a dd ress 003 f 16 ) b 7 b 0 i n t 1 i n t e r r u p t e n a b l e b i t f i x t h i s b i t t o 0 . s e r i a l i / o r e c e i v e i n t e r r u p t e n a b l e b i t s e r i a l i / o t r a n s m i t i n t e r r u p t e n a b l e b i t c n t r 0 i n t e r r u p t e n a b l e b i t k e y - o n w a k e - u p i n t e r r u p t e n a b l e b i t a - d c o n v e r s i o n i n t e r r u p t e n a b l e b i t f i x t h i s b i t t o 0 . 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d 0 : n o i nterrupt request i ssue d 1 : interrupt request issued 1-19 38k0 group user s manual hardware functional description key input interrupt (key-on wake up) a key-on wake up interrupt request is generated by applying a falling edge to any pin of port p0 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 15, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p0 0 p0 3 . fig. 15 connection example when using key input interrupt and port p0 block diagram ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 p o r t p 0 1 l a t c h port p0 1 direction register = 0 p o r t p 0 2 l a t c h port p0 2 direction register = 0 p o r t p 0 3 l a t c h p o r t p 0 3 d i r e c t i o n r e g i s t e r = 0 p o r t p 0 4 l a t c h p o r t p 0 4 d i r e c t i o n r e g i s t e r = 1 p o r t p 0 5 l a t c h port p0 5 direction register = 1 port p0 6 latch p o r t p 0 6 d i r e c t i o n r e g i s t e r = 1 p o r t p 0 7 l a t c h p o r t p 0 7 d i r e c t i o n r e g i s t e r = 1 p0 0 input p0 1 input p0 2 input p 0 3 i n p u t p 0 4 o u t p u t p 0 5 o u t p u t p0 6 output p0 7 output p u l l 0 r e g i s t e r b i t 7 = 0 port p0 input reading circuit port pxx l level output ? ? ? 0 p u l l 0 r e g i s t e r b i t 5 = 0 p u l l 0 r e g i s t e r b i t 4 = 0 p u l l 0 r e g i s t e r b i t 3 = 1 p u l l 0 r e g i s t e r b i t 2 = 1 pull 0 register bit 1 = 1 p u l l 0 r e g i s t e r b i t 0 = 1 hardware 1-20 38k0 group user s manual functional description timers the 38k0 group has three timers: timer x, timer 1, and timer 2. the division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. all timers are down count timers. when the timer reaches 00 16 , an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is contin- ued. when a timer underflows, the interrupt request bit corre- sponding to that timer is set to 1 . fig. 16 structure of timer x mode register timer 1 and timer 2 the count source of prescaler 12 is the system clock divided by 16. the output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow periodically sets the interrupt request bit. timer x timer x can each select in one of four operating modes by setting the timer x mode register. (1) timer mode the timer counts the count source selected by timer count source selection bit. (2) pulse output mode the timer counts the system clock divided by 16. whenever the contents of the timer reach 00 16 , the signal output from the cntr 0 pin is inverted. if the cntr 0 active edge selection bit is 0 , output begins at h . if it is 1 , output starts at l . when using a timer in this mode, set the corresponding port p5 1 direction register to output mode. (3) event counter mode operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the cntr 0 pin. when the cntr 0 active edge selection bit is 0 , the rising edge of the cntr 0 pin is counted. when the cntr 0 active edge selection bit is 1 , the falling edge of the cntr 0 pin is counted. (4) pulse width measurement mode if the cntr 0 active edge selection bit is 0 , the timer counts the system clock divided by 16 while the cntr 0 pin is at h . if the cntr 0 active edge selection bit is 1 , the timer counts it while the cntr 0 pin is at l . the count can be stopped by setting 1 to the timer x count stop bit in any mode. the corresponding interrupt request bit is set each time a timer underflows. t i m e r x m o d e r e g i s t e r ( t m : a d d r e s s 0 0 2 3 1 6 ) t i m e r x o p e r a t i n g m o d e b i t s b 1 b 0 00 : t i m e r m o d e 01 : p u l s e o u t p u t m o d e 10 : e v e n t c o u n t e r m o d e 11 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 0 a c t i v e e d g e s w i t c h b i t 0 : f a l l i n g e d g e a c t i v e f o r c n t r 0 i n t e r r u p t c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e 1 : r i s i n g e d g e a c t i v e f o r c n t r 0 i n t e r r u p t c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e t i m e r x c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p n o t u s e d ( r e t u r n 0 w h e n r e a d ) b 7 b 0 1-21 38k0 group user s manual hardware functional description fig. 17 timer block diagram q q 1 0 p 5 1 / c n t r 0 1 / 1 6 0 1 r t s y s t e m c l o c k 1/16 p r e s c a l e r x l a t c h ( 8 ) prescaler x (8) timer x latch (8) timer x (8) t i m e r x i n t e r r u p t r e q u e s t b i t toggle flip-flop t i m e r x c o u n t s t o p b i t p u l s e w i d t h m e a s u r e m e n t m o d e e v e n t c o u n t e r m o d e c n t r 0 i n t e r r u p t r e q u e s t b i t p u l s e o u t p u t m o d e port p5 1 latch port p5 1 direction register cntr 0 active edge selection bit t i m e r x l a t c h w r i t e p u l s e o u t p u t m o d e timer mode pulse output mode d a t a b u s d i v i d e r prescaler 12 latch (8) prescaler 12 (8) timer 1 latch (8) timer 1 (8) timer 2 latch (8) timer 2 (8) timer 2 interrupt request bit timer 1 interrupt request bit c n t r 0 a c t i v e e d g e s e l e c t i o n b i t d a t a b u s system clock divider hardware 1-22 38k0 group user s manual functional description serial i/o serial i/o can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer (baud rate generator) is also provided for baud rate generation. (1) clock synchronous serial i/o mode clock synchronous serial i/o mode can be selected by setting the mode selection bit of the serial i/o control register (bit 6 of ad- dress 0fe0 16 ) to 1 . for clock synchronous serial i/o, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the trancemit/receive buffer register. fig. 18 block diagram of clock synchronous serial i/o fig. 19 operation of clock synchronous serial i/o function p 4 2 / e x t c / s c l k p 4 3 / e x a 1 / s r d y p 4 0 / e x d r e q / r x d s y s t e m c l o c k 1/4 1 / 4 f / f serial i/o status registe r s e r i a l i / o c o n t r o l r e g i s t e r r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 2 6 1 6 r e c e i v e s h i f t r e g i s t e r r e c e i v e b u f f e r f u l l f l a g ( r b f ) r ece i ve i nterrupt request (ri) clock control circuit s h i f t c l o c k s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) b a u d r a t e g e n e r a t o r add ress 0 fe 2 16 b r g c o u n t s o u r c e s e l e c t i o n b i t clock control circuit f a l l i n g - e d g e d e t e c t o r d ata b us add ress 0026 16 shif t c l oc k t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) t ransm i t b u ff er empty fl ag (tbe) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t ransm i t i nterrupt source se l ect i on bi t add ress 0027 16 d ata b us a d d r e s s 0 f e 0 1 6 transmit buffer register transmit shift register p 4 1 / e x dack / t x d r e c e i v e e n a b l e s i g n a l s r d y d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 r b f = 1 t s c = 1 t b e = 0 t b e = 1 t s c = 0 t rans f er s hif t c l oc k (1/2 to 1/2048 of the internal clock, or an external clock) s er i a l output t x d s e r i a l i n p u t r x d w r i t e s i g n a l t o r e c e i v e / t r a n s m i t b u f f e r r e g i s t e r ( a d d r e s s 0 0 2 6 1 6 ) o verrun error (oe) detection n o t e s 1 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e g e n e r a t e d e i t h e r w h e n t h e t r a n s m i t b u f f e r r e g i s t e r h a s e m p t i e d ( t b e = 1 ) o r a f t e r t h e t r a n s m i t s h i f t o p e r a t i o n h a s e n d e d ( t s c = 1 ) , b y s e t t i n g t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 2 : i f d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 0 , t h e t r a n s m i t c l o c k i s g e n e r a t e d c o n t i n u o u s l y a n d s e r i a l d a t a i s o u t p u t c o n t i n u o u s l y f r o m t h e t x d p i n . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r e c e i v e b u f f e r f u l l f l a g ( r b f ) b e c o m e s 1 . d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 1-23 38k0 group user s manual hardware functional description (2) asynchronous serial i/o (uart) mode clock asynchronous serial i/o mode (uart) can be selected by setting the serial i/o mode selection bit of the serial i/o control register to 0 . eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. the transmit buffer can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 20 block diagram of uart serial i/o fig. 21 operation of uart serial i/o function s ystem c l oc k 1 / 4 o e p e f e 1/16 1 / 1 6 d a t a b u s r e c e i v e b u f f e r r e g i s t e r a d d r e s s 0 0 2 6 1 6 r ece i ve s hif t reg i ster r ece i ve b u ff er f u ll fl ag (rbf) r ece i ve i nterrupt request (ri) b au d rate generator f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) a d d r e s s 0 f e 2 1 6 s t / s p / p a g e n e r a t o r transmit buffer register d ata b us t ransm i t s hif t reg i ster add ress 0026 16 t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) add ress 0027 16 std etector s p d e t e c t o r uart contro l reg i ster a d d r e s s 0 f e 1 1 6 c h a r a c t e r l e n g t h s e l e c t i o n b i t add ress 0 fe 0 16 brg count source se l ect i on bit t ransm i t i nterrupt source se l ect i on bit s er i a l i / o sync h ronous c l oc k se l ect i on bi t cl oc k contro l c i rcu i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s s e r i a l i / o 1 c o n t r o l r e g i s t e r p 4 2 / e x tc / s cl k s e r i a l i / o s t a t u s r e g i s t e r p 4 0 / e x dreq / r x d p 4 1 / e x dack / t x d tsc =0 tbe=1 rbf =0 tbe =0 t b e = 0 r b f = 1 r b f = 1 s t d 0 d 1 s p d 0 d 1 s t sp tbe =1 t s c = 1 ? ? 1 : e r r o r f l a g d e t e c t i o n o c c u r s a t t h e s a m e t i m e t h a t t h e r b f f l a g b e c o m e s 1 ( a t 1 s t s t o p b i t , d u r i n g r e c e p t i o n ) . 2 : t h e t r a n s m i t i n t e r r u p t ( t i ) c a n b e g e n e r a t e d t o o c c u r w h e n e i t h e r t h e t b e o r t s c f l a g b e c o m e s 1 , d e p e n d i n g o n t h e s e t t i n g o f t h e t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) o f t h e s e r i a l i / o 1 c o n t r o l r e g i s t e r . 3 : t h e r e c e i v e i n t e r r u p t ( r i ) i s s e t w h e n t h e r b f f l a g b e c o m e s 1 . 4 : a f t e r d a t a i s w r i t t e n t o t h e t r a n s m i t b u f f e r r e g i s t e r w h e n t s c = 1 , 0 . 5 t o 1 . 5 c y c l e s o f t h e d a t a s h i f t c y c l e i s n e c e s s a r y u n t i l c h a n g i n g t o t s c = 0 . n o t e s s e r i a l o u t p u t t x d s e r i a l i n p u t r x d r ece i ve b u ff er rea d s i gna l t r a n s m i t o r r e c e i v e c l o c k hardware 1-24 38k0 group user s manual functional description [serial i/o control register (siocon)] 0fe0 16 the serial i/o control register contains eight control bits for the se- rial i/o function. [uart control register (uartcon)] 0fe1 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer. [serial i/o status register (siosts)] 0027 16 the read-only serial i/o status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to 0 when the receive buffer is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing 0 to the serial i/o enable bit sioe (bit 7 of the serial i/o control register) also clears all the status flags, including the error flags. all bits of the serial i/o status register are initialized to 0 at reset, but if the transmit enable bit (bit 4) of the serial i/o control register has been set to 1 , the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become 1 . [transmit buffer/receive buffer register (tb/ rb)] 0026 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer register is write- only and the receive buffer register is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer regis- ter is 0 . [baud rate generator (brg)] 0fe2 16 the baud rate generator determines the baud rate for serial trans- fer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. notes on serial i/o when setting the transmit enable bit to 1 , the serial i/o transmit interrupt request bit is automatically set to 1 . when not requiring the interrupt occurrence synchronized with the transmission enalbed, take the following sequence. ? 0 (disabled). ? 1 . ? 0 after 1 or more instructions have been executed. ? 1 (enabled). 1-25 38k0 group user s manual hardware functional description fig. 22 structure of serial i/o control registers b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : s y s t e m c l o c k 1 : s y s t e m c l o c k / 4 s e r i a l i / o s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d . b r g o u t p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . 1 : e x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d . e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . s r d y o u t p u t e n a b l e b i t ( s r d y ) 0 : p 4 3 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 4 3 p i n o p e r a t e s a s s r d y o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o m o d e s e l e c t i o n b i t ( s i o m ) 0 : a s y n c h r o n o u s s e r i a l i / o ( u a r t ) 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o d i s a b l e d ( p i n s p 4 0 p 4 3 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o e n a b l e d ( p i n s p 4 0 p 4 3 c a n o p e r a t e a s s e r i a l i / o p i n s ) s e r i a l i / o c o n t r o l r e g i s t e r ( s i o c o n : a d d r e s s 0 f e 0 1 6 ) b7 b0 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t r e g i s t e r s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) s e r i a l i / o s t a t u s r e g i s t e r ( s i o s t s : a d d r e s s 0 0 2 7 1 6 ) b 7b 0 u a r t c o n t r o l r e g i s t e r ( u a r t c o n : a d d r e s s 0 f e 1 1 6 ) c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) 0 : 8 b i t s 1 : 7 b i t s p a r i t y e n a b l e b i t ( p a r e ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d p a r i t y s e l e c t i o n b i t ( p a r s ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s n o t u s e d ( r e t u r n 0 w h e n r e a d ) ( t h i s i s a w r i t e d i s a b l e d b i t . ) n o t u s e d ( r e t u r n 1 w h e n r e a d ) b 7b 0 hardware 1-26 38k0 group user s manual functional description usb function 38k0 group is equipped with a usb function control circuit (usbfcc) that enables effective interfacing with the host-pc. this circuit is in compliance with usb2.0 s full-speed transfer mode (12 mbps, equivalent to usb1.1). this circuit also supports all four transfer-types specified in the standard usb specification. the usbfcc has four endpoints that can select its transfer type. although endpoint 0 is fixed to control transfer, the endpoints 1 to 3 can be set to interrupt transfer, bulk transfer, or isochronous transfer. a dedicated circuit automatically performs stage management for control transfer and packet management for transactions, which are necessary for matching of data transmit/receive timing, error detection, and retry after error. this dedicated control circuit en- ables the user to develop a program or timing design very easily. each endpoint can be programmed for data transfer conditions so that the endpoints are adaptive for all usb device class transfer systems. the data buffer of each endpoint can be assigned to any area in the multi-channel ram. this feature offers highly efficient memory usage by avoiding re-buffering and enabling simple data modifica- tion. the transmit/receive data is directly transferred to the data buffer via the control circuit (direct ram access type) without disturbing the cpu operation. this mechanism enables the cpu to transfer data smoothly with no drop in performance. in addition to this buffer function, a double-buffer setting will keep a re-buffering stall at a minimum and increase the overall data throughput (max. 64 bytes x 2 channels). as other special signals control, the endpoints have detection functions for the usb bus reset signal, resume signal, suspend signal, and sof signal, and also have a remote wake-up signal transmit function. when completing data transfer or receiving a special signal, the endpoint generates the corresponding interrupt to the cpu (3 vec- tors/18 factors). with all this essential yet comprehensive built-in hardware, your system using the 38k0 group will be ready for any usb applica- tion that comes its way. usb data transfer the usb specification promises 12 mbps data transfer in the full- speed mode, that is equivalent to 1.5 m bytes per second of data transactions. however, in usb data transfer, bit-stuffing may be executed de- pending on the bit patterns of the transfer data, possibly resulting in 1-byte data (normally 8 bits) handled as up to 10 bits. because usb uses asynchronous transfers, the clock cycle of the usb internal reference clock may change to adjust to the clock phase. therefore, the access timing of the usbfcc for the multi- channel ram will change owing to the frequency of internal clock fig. 23 usb function overview interrupt request data transmit/receive path [direct ram access type] 38k0 group mcu usb bus (usb-host) external mcu cpu program rom usb multi-channel ram built-in peripheral functions external bus interface (exb) 1-27 38k0 group user s manual hardware functional description usb function control circuit (usbfcc) block diagram the following diagram shows the usbfcc block diagram. the cir- cuit comprises: (1) serial interface engine (sie) (2) device control unit (dcu) (3) internal memory interface (mif) (4) cpu interface (cif) fig. 24 usb function control circuit (usbfcc) block diagram (1) serial interface engine (sie) the sie performs the following usb lower-layer protocols (pack- ets, transactions): sampling of receive data and clock, generation of transmit clock serial-to-parallel conversion of transmit/receive data nrzi (non return zero invert) encode/decode bit stuffing/unstuffing sync (synchronization pattern) detection, eop (end of packet) detection usb address detection, endpoint detection crc (cyclic redundancy check) generation and checking (2) device control unit (dcu) the dcu manages the following usb upper-layer protocols (ad- dress/endpoint and control-transfer sequence): status control for each endpoint control-transfer sequence control memory interface status control (3) memory interface (mif) the mif controls the flow of data transfer between the sie and the multi-channel ram under the management of the dcu. (4) cpu interface (cif) the cif performs the following functions: mode setting via registers, dcu control signal generation, dcu status signal reading interrupt signal generation internal bus interface control. c p u c i f u s b f u n c t i o n c o n t r o l c i r c u i t d c u m i f s i e d c u c o n t r o l d c u s t a t u s mif control sie control sie status transmit/receive data u s b t r a n s c e i v e r d 0 + d 0 - multi-channel ram hardware 1-28 38k0 group user s manual functional description usb port external circuit configuration the operation mode of the usb port driver circuit can be config- ured by usb control register (address 0010 16 ). figure 25 and figure 26 show the usb port external circuit block diagram. 1 0 usb reference voltage circuit pll uclkcon v refe v refcon dv cc full speed + - usbe usbe usb module x out f vco troncon trone usbvref tron d0+ d0- 2.2 ? ? ? fig. 25 usb port external circuit (d0+, d0-, usbv ref , tron) block diagram (4.0v v cc 5.25v) fig. 26 usb port external circuit (d0+, d0-, usbv ref , tron) block diagram (3.0v v cc 4.0v) 1 0 pll uclkcon full speed + - usbe usbe usb module x out f vco troncon trone usbvref tron d0+ d0- 27 ? ? ? (note) note: in vcc = 3.0 v to 3.6 v connect this pin to vcc. 1-29 38k0 group user s manual hardware functional description endpoint buffer area setting the buffer area used in data transfer can be assigned to any area of the multi-channel ram for each endpoint. buffer area beginning address the buffer area configuration register (address 0fed 16 ) defines the beginning address of the buffer area (every 32 bytes) for each endpoint. however, the only ram area is configurable. 00h [address 0000 16 ], 01h [address 0020 16 ]: not configurable 02h [address 0040 16 ] to 1fh [address 03e0 16 ]: configurable interrupt-source dependant buffer area offset address an offset value is added to the beginning address of each source, which is specified by the interrupt source register (address 001d 16 ), for each endpoint. this section describes in detail the beginning address specified by the buffer area set register as offset address 00h, according to each endpoint. (1) endpoint 00 endpoint 00 has two kinds of interrupt sources for accessing the buffer. the respective address offsets are: bsrdy00 (setup buffer ready interrupt): offset address = 00h brdy00 (out or in buffer ready interrupt): offset address = 08h (2) endpoint 01 the buffer area offset address for each interrupt source for of end- point 01 varies according to the contents of the ep01 set register (address 0019 16 ). in single buffer mode (dblb01 = 0 ): endpoint 01 has only one interrupt source for accessing the buffer. b0rdy01 (buffer 0 ready interrupt): offset address = 00h in double buffer mode (dblb01 = 1 ): endpoint 01 has two kinds of interrupt sources for accessing the buffer. b0rdy01 (buffer 0 ready interrupt): offset address = 00h b1rdy01 (buffer 1 ready interrupt): the offset address varies according to the double buffer begin- ning address set bit (bsiz01). -offset address = 08h when bsiz01 = 00 -offset address = 10h when bsiz01 = 01 -offset address = 40h when bsiz01 = 10 -offset address = 80h when bsiz01 = 11 (3) endpoints 02 and 03 same as endpoint 01. notes the selected ram area must be within addresses 0040 16 to 03ff 16 . make sure the buffer area beginning address is set in agreement with the offset address and the number of transmit/receive data bytes. this is particularly important when in the double buffer mode or when handling 64-byte data. fig. 27 example setting of buffer area beginning address fig. 28 examples of interrupt source dependant buffer area offset address 0fed 16 = 15h 0000 16 0020 16 0040 16 0060 16 02a0 16 03e0 16 memory sfr ram 00 01 02 03 15 1f 0fed 16 disabled to be used 0000 0000 0010 1010 (a) when selecting endpoint 00 memory 02a0 16 02a8 16 offset 00 h 08 h bsrdy00 brdy00 02a0 16 00 h b0rdy01 02a0 16 0320 16 00 h 80 h b0rdy01 b1rdy01 memory offset (b) when selecting single buffer mode memory offset (c) when selecting double buffer mode (when bsiz01 = 11) hardware 1-30 38k0 group user s manual functional description usb interrupt function usb interrupt control circuit (usbintcon) has 3 requests and 16 usb-device interrupt request sources. each interrupt source register enables the user to easily determine which interrupt has occurred. table 8 shows the list of usb interrupt sources. table 8 usb interrupt sources interrupt request bit (ireq1: address 003c 16 ) usb bus reset usb interrupt bit (usbireq: address 0017 16 ) interrupt source at usb bus reset signal detection: after enabling the usb module (usbe = 1 ), an interrupt request occurs when 2.5 1 ), an interrupt request occurs when sof packet is detected in d0+/d0- port. its occurrence does not depend on frame-time or crc value after sof packet is transferred. (normally, sof packet detection occurs only when f usb = 48 mhz) at endpoint 00 data transfer complete: buffer ready (read/write enabled state) control transfer completed status stage transition setup buffer ready (read enabled state) control transfer error at endpoint 01 data transfer complete: buffer 0 ready (read/write enabled state) buffer 1 ready (read/write enabled state) transfer error at endpoint 02 data transfer complete: buffer 0 ready (read/write enabled state) buffer 1 ready (read/write enabled state) transfer error at endpoint 03 data transfer complete: buffer 0 ready (read/write enabled state) buffer 1 ready (read/write enabled state) transfer error at suspend signal detection: after enabling the usb module (usbe = 1 ), an interrupt request occurs when 3 ms j state is detected in d0+/d0- port. (equivalent to 144,000 clock-length when f usb = 48mhz) at resume signal detection: after enabling the usb module (usbe = 1 ) and resume interrupt (rsme = 1 ), an interrupt request occurs when a bus state change (j state to se0 or k state) is detected in d0- port. usb sof usb device ep00 ep01 ep02 ep03 sus rsm 1-31 38k0 group user s manual hardware functional description fig. 29 usb device interrupt control [epxxreg5] [ep00req] brdy00 ep00 [usbireq] ep00e [usbicon] [ep01req] b0rdy01 ep01 ep01e usb device interrupt request [ep02req] ep02 ep02e [ep03req] ep03 ep03e sus suse rsm rsme ctend00 ctsts00 bsydy00 err00 b1rdy01 err01 b0rdy02 b1rdy02 err02 b0rdy03 b1rdy03 err03 hardware 1-32 38k0 group user? manual functional description usb register list the usb register list is shown below. 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 usb control register usb function enable register usb function address register frame number register low frame number register high usb interrupt source enable register usb interrupt source register endpoint index register endpoint field register 1 endpoint field register 2 endpoint field register 3 endpoint field register 4 endpoint field register 5 endpoint field register 6 endpoint field register 7 endpoint field register 8 endpoint field register 9 usbcon usbae usba0 fnuml fnumh usbicon usbireq usbindex epxxreg1 epxxreg2 epxxreg3 epxxreg4 epxxreg5 epxxreg6 epxxreg7 epxxreg8 epxxreg9 usbe uclkcon usbdife vrefe vrefcon trone troncon wkup symbol address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ad0e usbadd0[6:0] fnum[7:0] fnum[10:8] rsme suse ep03e ep02e ep01e ep00e rsm sus ep03 ep02 ep01 ep00 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 (1) endpoint 00 (2) endpoint 01 (3) endpoint 02 (4) endpoint 03 ep00stg ep00con1 ep00con2 ep00con3 ep00req ep00byt ep00buf setup00 ep00 stage register ep00 control register 1 ep00 control register 2 ep00 control register 3 ep00 interrupt source register ep00 byte number register ep00 buffer area set register bval00 ctende00 err00 bsrdy00 ctsts00 ctend00 brdy00 bbyt00[3:0] 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 ep01 set register ep01 control register 1 ep01 control register 2 ep01 control register 3 ep01 interrupt source register ep01 byte number register 0 ep01 byte number register 1 ep01 max. packet size register ep01 buffer area set register ep01cfg ep01con1 ep01con2 ep01con3 ep01req ep01byt0 ep01byt1 ep01max ep01buf typ01[1:0] dir01 itmd01 sqcl01 dblb01 bsiz01[1:0] b0val01 b1val01 err01 b1rdy01 b0rdy01 b0byt01[6:0] b1byt01[6:0] mxps01[6:0] 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 ep02cfg ep02con1 ep02con2 ep02con3 ep02req ep02byt0 ep02byt1 ep02max ep02buf typ02[1:0] dir02 itmd02 sqcl02 dblb02 bsiz02[1:0] b0val02 b1val02 err02 b1rdy02 b0rdy02 b0byt02[6:0] b1byt02[6:0] mxps02[6:0] 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0fec 16 0fed 16 ep03 set register ep03 control register 1 ep03 control register 2 ep03 control register 3 ep03 interrupt source register ep03 byte number register 0 ep03 byte number register 1 ep03 max. packet size register ep03 buffer area set register ep02 set register ep02 control register 1 ep02 control register 2 ep02 control register 3 ep02 interrupt source register ep02 byte number register 0 ep02 byte number register 1 ep02 max. packet size register ep02 buffer area set register ep03cfg ep03con1 ep03con2 ep03con3 ep03req ep03byt0 ep03byt1 ep03max ep03buf typ03[1:0] dir03 itmd03 sqcl03 dblb03 bsiz03[1:0] b0val03 b1val03 err03 b1rdy03 b0rdy03 b0byt03[6:0] b1byt03[6:0] mxps03[6:0] : not used usb sfr pid00[1:0] badd02[4:0] badd01[4:0] pid01[1:0] pid02[1:0] badd03[4:0] pid03[1:0] epidx[1:0] badd00[4:0] fig. 30 usb related registers 1-33 38k0 group user s manual hardware functional description usb related registers the usb related registers are shown below. b7 at reset w function bit name bit symbol b0 remote wakeup bit tron output control bit tron output enable bit usb reference voltage control bit usb reference voltage enable bit usb difference input enable bit usb clock select bit usb module operation enable bit wkup troncon trone vrefcon vrefe usbdife uclkcon usbe o o o o o o o o o o o o o o o o 0 0 0 0 0 0 0 0 usb control register ( usbcon) [address 0010 16 ] : state remainin g 0 : returning to bus idle state by writing 1 first and then 0 . (remote wakeup signal) 1 : k-state output 0 : l output mode (valid in trone = 1 ) 1 : h output mode (valid in trone = 1 ) 0 : tron port output disabled (hi-z state) 1 : tron port output enabled 0 : normal mode (valid in vrefe = 1 ) 1 : low current mode (valid in vrefe = 1 ) 0 : usb reference voltage circuit operation disabled 1 : usb reference voltage circuit operation enabled 0 : upstream-port difference input circuit operation disabled 1 : upstream--port difference input circuit operation enabled 0 : external oscillating clock f(x in ) 1 : pll circuit output clock f vco 0 : usb module reset 1 : usb module operation enabled h/w s/w r fig. 31 structure of usb control register fig. 32 structure of usb function enable register b7 bit name bit symbol b0 usb function enable bit not used ad0e b7:b1 0 usb function enable register (usbae) [address 0011 16 ] 0: usb function address register invalidated 1: usb function address register validated write 0 when writing. 0 is read when reading. at reset function h/w s/w o o o o : state remaining 0000000 w r hardware 1-34 38k0 group user s manual functional description fig. 33 structure of usb function address register b7 b0 usb function address bit not used usbadd0 [6:0] b7 0 0 usb function address register ( usba0) [address 0012 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining in ad0e = 0 , this value changes after writing. in ad0e = 1 , this value changes after completion of set_address control transferring. write 0 when writing. 0 is read when reading. 0 w r fig. 34 structure of frame number register low b7 b0 frame number low bit fnum [7:0] in- definite in- definite frame number register low ( fnuml) [address 0014 16 ] the frame number is updated at sof reception. bit name bit symbol at reset function h/w s/w o ? fig. 35 structure of frame number register high b7 b0 fnum [10:8] b7:b3 frame number register high ( fnumh) [address 0015 16 ] in- definite in- definite bit name bit symbol at reset function h/w s/w o o frame number high bit not used the frame number is updated at sof reception. write 0 when writing. 0 is read when reading. ? : state remaining 00000 w r 1-35 38k0 group user s manual hardware functional description b7 b0 ep00e ep01e ep02e ep03e b5:b4 suse rsme 0 0 0 0 0 0 0 0 0 0 0 0 usb interrupt source enable register ( usbicon) [address 0016 16 ] 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled write 0 when writing. 0 is read when reading. 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled bit name bit symbol at reset function h/w s/w o o o o o o o o o o o o o o usb function/endpoint 0 interrupt enable bit usb function/endpoint 1 interrupt enable bit usb function/endpoint 2 interrupt enable bit usb function/endpoint 3 interrupt enable bit not used suspend interrupt enable bit resume interrupt enable bit w r 00 : state remaining fig. 36 structure of usb interrupt source enable register hardware 1-36 38k0 group user s manual functional description b7 b0 usb function/endpoint 0 interrupt bit usb function/endpoint 1 interrupt bit usb function/endpoint 2 interrupt bit usb function/endpoint 3 interrupt bit not used suspend interrupt bit resume interrupt bit ep00 ep01 ep02 ep03 b5:b4 sus rsm 0 0 0 0 0 0 0 0 0 0 0 0 usb interrupt source register ( usbireq) [address 0017 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o ? ? ? ? ? 1 when any one of ep00 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing ep00 interrupt source register to 00 16 . writing to this bit causes no state change. this bit is set to 1 when any one of ep01 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing ep01 interrupt source register to 00 16 . writing to this bit causes no state change. this bit is set to 1 when any one of ep02 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing ep02 interrupt source register to 00 16 . writing to this bit causes no state change. this bit is set to 1 when any one of ep03 interrupt source register s bits at least is set to 1 . this bit is cleared to 0 by clearing ep03 interrupt source register to 00 16 . writing to this bit causes no state change. write 0 when writing. 0 is read when reading. 0 : no interrupt request issued 1 : interrupt request issued this bit is set to 1 when detecting 3 ms or more of j- state, using usb clock (f usb ) at 48 mhz. 0 can be set by software, but 1 cannot be set. this bit is set to 1 when the usb bus state changes from j-state to k-state or se0 in the resume interrupt enable bit = 1 . it is also 1 in the condition of internal clock stopped. this bit is cleared to 0 by clearing the resume interrupt enable bit. writing to this bit causes no state change. w r 00 : state remaining fig.37 structure of usb interrupt source register b7 b0 endpoint index bit not used epidx [1:0] b7:b3 0 endpoint index register ( usbindex) [address 0018 16 ] b1 b0 0 0 : endpoint 0 0 1 : endpoint 1 1 0 : endpoint 2 1 1 : endpoint 3 write 0 when writing. 0 is read when reading. bit name bit symbol at reset function o o o o : state remaining h/w s/w 000000 w r fig. 38 structure of endpoint index register 1-37 38k0 group user s manual hardware functional description (1) endpoint 00 b7 b0 setup packet detection bit not used setup00 b7:b1 1 1 ep00 stage register ( ep00stg) [address 0019 16 ] bit name bit symbol at reset function h/w s/w this bit is set to 1 at reception of setup packet. writing 0 to this bit clears this bit if the next setup token does not occur. writing 1 to this bit causes no state change of the status flags. write 0 when writing. 0 is read when reading. o o o o : state remaining 000 0 000 w r fig. 39 structure of ep00 stage register fig. 40 structure of ep00 control register 1 b7 b0 response pid bit not used pid00 [1:0] b7:b2 0 ep00 control register 1 ( ep00con1) [address 001a 16 ] bit name bit symbol at reset function h/w s/w b1 b0 0 0 : nak 0 1 : automatic response (ack, nak, data0, data1) 1 x : stall at occurrence of control transfer error: b1 is set to 1 by the hardware. at reception of setup token: b1 and b0 are cleared to 0 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 000000 w r b7 b0 buffer enable bit not used bval00 b7:b1 0 ep00 control register 2 ( ep00con2) [address 001b 16 ] bit name bit symbol at reset function h/w s/w 0 : nak transmission (sie is disabled to read a buffer.) 1 : transmitting/receiving data set state (sie is possible to read from/write to a buffer.) at reception of setup token: this bit is cleared to 0 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 000 0 0 0 0 w r fig. 41 structure of ep00 control register 2 hardware 1-38 38k0 group user s manual functional description fig. 42 structure of ep00 control register 3 b7 b0 control transfer completion enable bit not used ctende00 b7:b1 0 ep00 control register 3 ( ep00con3) [address 001c 16 ] 0 : nak transmission in the status stage 1 : control transfer completion enabled (sie transmits null/ack.) (valid in pid00 = 01 2 ) at reception of setup token: this bit is cleared to 0 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining bit name bit symbol at reset function h/w s/w 000 0 0 0 0 w r b7 b0 usb function/endpoint 0 buffer ready interrupt bit usb function/endpoint 0 control transfer completion interrupt bit usb function/endpoint 0 status stage transition interrupt bit usb function/endpoint 0 setup buffer ready interrupt bit usb function/endpoint 0 error interrupt bit not used brdy00 ctend00 ctsts00 bsrdy00 err00 b7:b5 0 0 0 0 0 0 0 0 0 0 ep00 interrupt source register (ep00req) [address 001d 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o o o o o o 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when the buffer is ready state (enabled to be read/written) on usb function/endpoint 0. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when control transfer is completed (null/ack transmission in the status stage) on usb function/endpoint 0. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when transition to status stage occurs in ctende00 = 0 (control transfer completion disabled) on usb function/endpoint 0. 0 can be set by software, but 1 cannot be set. 1-39 38k0 group user s manual hardware functional description b7 b0 bbyt00 [3:0] b7:b4 0 ep00 byte number register ( ep00byt) [address 001e 16 ] out : the received byte number is automatically set. in : set the transmitting byte number. write 0 when writing. 0 is read when reading. bit name bit symbol at reset function h/w s/w o o o o transmit/receive byte number bit not used : state remaining 0000 w r fig. 44 structure of ep00 byte number register b7 b0 ep00 beginning address set bit not used badd00 [4:0] b7:b5 0 ep00 buffer area set register ( ep00buf) [address 0fed 16 ] bit name bit symbol at reset function h/w s/w set the beginning address of ep00 s buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 0040 16 0 0 0 1 1 : 0060 16 .............. 1 1 1 1 0 : 03c0 16 1 1 1 1 1 : 03e0 16 write 0 when writing. 0 is read when reading. o o o o : state remaining 000 w r fig. 45 structure of ep00 buffer area set register hardware 1-40 38k0 group user s manual functional description (2) endpoint 01 fig. 46 structure of ep01 set register fig. 47 structure of ep01 control register 1 b7 b0 double buffer beginning address set bit buffer mode select bit sequence toggle bit clear bit interrupt toggle mode select bit transfer direction bit transfer type bite bsiz01 [1:0] dblb01 sqcl01 itmd01 dir01 typ01 [1:0] 0 0 0 0 0 0 ep01 set register ( ep01cfg) [address 0019 16 ] bit name bit symbol at reset function h/w s/w in double buffer mode set the beginning address of buffer 1 area, using a relative value for the beginning address of buffer 0. b1b0 0 0 = 8 bytes 0 1 = 16 bytes 1 0 = 64 bytes 1 1 = 128 bytes 0 : single buffer mode 1 : double buffer mode 0 : toggle bit clear disabled 1 : writing 1 clears the toggle bit and data0 is used as the next data pid. 0 is always read when reading. 0 : normal mode 1 : contin uous toggle mode (valid at interrupt in transfer) 0 : out (data is received from the host.) 1 : in (data is transmitted to the host.) b7b6 0 0 : transfer disabled 0 1 : bulk transfer 1 0 : interrupt transfer 1 1 : isochronous transfer o o o o o o o o o o o o : state remaining w r b7 b0 response pid bit not used pid01 [1:0] b7:b2 0 ep01 control register 1 ( ep01con1) [address 001a 16 ] bit name bit symbol at reset function h/w s/w b1 b0 0 0 : nak 0 1 : automatic response (ack, nak, data0, data1) 1 x : stall at occurrence of over-max. packet size : b1 is set to 1 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 000000 w r 1-41 38k0 group user s manual hardware functional description fig. 49 structure of ep01 control register 3 fig. 50 structure of ep01 interrupt source register b7 b0 b0val01 b7:b1 0 ep01 control register 2 ( ep01con2) [address 001b 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 0 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). write 0 when writing. 0 is read when reading. 00 0 00 0 0 w r fig. 48 structure of ep01 control register 2 b7 b0 b1val01 b7:b1 0 ep01 control register 3 ( ep01con3) [address 001c 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 1 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). in double buffer mode this bit is valid. write 0 when writing. 0 is read when reading. 0000000 w r b7 b0 b0rdy01 b1rdy01 err01 b7:b3 0 0 0 0 0 0 ep01 interrupt source register (ep01req) [address 001d 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o o usb function/endpoint 1 buffer 0 ready interrupt bit usb function/endpoint 1 buffer 1 ready interrupt bit usb function/endpoint 1 error interrupt bit not used 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when the buffer 0 is ready state (enabled to be read/written) on usb function/endpoint 1. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued in single buffer mode this bit is invalid. this bit is set to 1 when the buffer 1 is ready state (enabled to be read/written) on usb function/endpoint 1 in double buffer mode. 0 can be set by software, but 1 cannot be set. 0: no interrupt request issued 1: interrupt request issued this bit is set to 1 when stall response occurs on usb function/endpoint 1. 0 can be set by software, but 1 cannot be set. write 0 when writing. 0 is read when reading. 00000 w r hardware 1-42 38k0 group user s manual functional description fig. 51 structure of ep01 byte number register 0 b7 b0 b0byt01 [6:0] b7 0 0 ep01 byte number register 0 ( ep01byt0) [address 001e 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: set the transmitting byte number. double buffer mode : set the transmitting byte number of buffer 0. single buffer mode : the received byte number is automatically set. double buffer mode : the received byte number of buffer 0 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? 0 0 ep01 byte number register 1 ( ep01byt1) [address 001f 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: these bits are invalid. double buffer mode : set the transmitting byte number of buffer 1. single buffer mode: these bits are invalid. double buffer mode : the received byte number of buffer 1 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? fig. 52 structure of ep01 byte number register 1 b7 b0 mxps01 [6:0] b7 ep01 max. packet size register (ep01max) [address 0fec 16 ] 0 bit name bit symbol at reset function h/w s/w : state remaining o o o o max. packet size bit not used in : these bits are invalid. out : set the maximum packet size. write 0 when writing. 0 is read when reading. 0 w r fig. 53 structure of ep01 max. packet size register 1-43 38k0 group user s manual hardware functional description b7 b0 ep01 beginning address set bit not used badd01 [4:0] b7:b5 0 ep01 buffer area set register ( ep01buf) [address 0fed 16 ] bit name bit symbol at reset function h/w s/w set the beginning address of ep01 s buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 0040 16 0 0 0 1 1 : 0060 16 .............. 1 1 1 1 0 : 03c0 16 1 1 1 1 1 : 03e0 16 write 0 when writing. 0 is read when reading. o o o o : state remaining 000 w r fig. 54 structure of ep01 buffer area set register hardware 1-44 38k0 group user s manual functional description (3) endpoint 02 fig. 55 structure of ep02 set register fig. 56 structure of ep02 control register 1 b7 b0 double buffer beginning address set bit buffer mode select bit sequence toggle bit clear bit interrupt toggle mode select bit transfer direction bit transfer type bite bsiz02 [1:0] dblb02 sqcl02 itmd02 dir02 typ02 [1:0] 0 0 0 0 0 0 ep02 set register ( ep02cfg) [address 0019 16 ] bit name bit symbol at reset function h/w s/w in double buffer mode set the beginning address of buffer 1 area, using a relative value for the beginning address of buffer 0. b1b0 0 0 = 8 bytes 0 1 = 16 bytes 1 0 = 64 bytes 1 1 = 128 bytes 0 : single buffer mode 1 : double buffer mode 0 : toggle bit clear disabled 1 : writing 1 clears the toggle bit and data0 is used as the next data pid. 0 is always read when reading. 0 : normal mode 1 : contin uous toggle mode (valid at interrupt in transfer) 0 : out (data is received from the host.) 1 : in (data is transmitted to the host.) b7b6 0 0 : transfer disabled 0 1 : bulk transfer 1 0 : interrupt transfer 1 1 : isochronous transfer o o o o o o o o o o o o : state remaining w r b7 b0 response pid bit not used pid02 [1: 0] b7:b2 0 ep02 control register 1 ( ep02con1) [address 001a 16 ] bit name bit symbol at reset function h/w s/w b1 b0 0 0 : nak 0 1 : automatic response (ack, nak, data0, data1) 1 x : stall at occurrence of over-max. packet size : b1 is set to 1 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 00 0 0 00 w r 1-45 38k0 group user s manual hardware functional description b7 b0 b0val02 b7:b1 0 ep02 control register 2 ( ep02con2) [address 001b 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 0 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). write 0 when writing. 0 is read when reading. 00 0 00 0 0 w r fig. 57 structure of ep02 control register 2 b7 b0 b1val02 b7:b1 0 ep02 control register 3 ( ep02con3) [address 001c 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 1 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). in double buffer mode this bit is valid. write 0 when writing. 0 is read when reading. 00 0 00 0 0 w r fig. 58 structure of ep02 control register 3 fig. 59 structure of ep02 interrupt source register b7 b0 b0rdy02 b1rdy02 err02 b7 to b3 0 0 0 0 0 0 ep02 interrupt source register (ep02req) [address 001d 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o o usb function/endpoint 2 buffer 0 ready interrupt bit usb function/endpoint 2 buffer 1 ready interrupt bit usb function/endpoint 2 error interrupt bit not used 0 : no interrupt request issued 1 : interrupt request issued this bit is set to 1 when the buffer 0 is ready state (enabled to be read/written) on usb function/endpoint 2. 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued in single buffer mode this bit is invalid. this bit is set to 1 when the buffer 1 is ready state (enabled to be read/written) on usb function/endpoint 2 in double buffer mode. 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued this bit is set to 1 when stall response occurs on usb function/endpoint 2. 0 can be set by software, but 1 cannot be set. write 0 when writing. 0 is read when reading. 00 0 00 w r hardware 1-46 38k0 group user s manual functional description fig. 60 structure of ep02 byte number register 0 b7 b0 b0byt02 [6:0] b7 0 0 ep02 byte number register 0 ( ep02byt0) [address 001e 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: set the transmitting byte number. double buffer mode : set the transmitting byte number of buffer 0. single buffer mode: the received byte number is automatically set. double buffer mode : the received byte number of buffer 0 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? 0 0 ep02 byte number register 1 ( ep02byt1) [address 001f 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: these bits are invalid. double buffer mode : set the transmitting byte number of buffer 1. single buffer mode: these bits are invalid. double buffer mode : the received byte number of buffer 1 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? fig. 61 structure of ep02 byte number register 1 b7 b0 mxps02 [6:0] b7 ep02 max. packet size register (ep02max) [address 0fec 16 ] 0 bit name bit symbol at reset function h/w s/w : state remaining o o o o max. packet size bit not used in : these bits are invalid. out : set the maximum packet size. write 0 when writing. 0 is read when reading. 0 w r fig. 62 structure of ep02 max. packet size register 1-47 38k0 group user s manual hardware functional description b7 b0 ep02 beginning address set bit not used badd02 [4:0] b7:b5 0 ep02 buffer area set register ( ep02buf) [address 0fed 16 ] bit name bit symbol at reset function h/w s/w set the beginning address of ep02 s buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 0040 16 0 0 0 1 1 : 0060 16 .............. 1 1 1 1 0 : 03c0 16 1 1 1 1 1 : 03e0 16 write 0 when writing. 0 is read when reading. o o o o : state remaining 000 w r fig. 63 structure of ep02 buffer area set register hardware 1-48 38k0 group user s manual functional description (4) endpoint 03 fig. 64 structure of ep03 set register fig. 65 structure of ep03 control register 1 b7 b0 double buffer beginning address set bit buffer mode select bit sequence toggle bit clear bit interrupt toggle mode select bit transfer direction bit transfer type bit bsiz03 [1:0] dblb03 sqcl03 itmd03 dir03 typ03 [1:0] 0 0 0 0 0 0 ep03 set register ( ep03cfg) [address 0019 16 ] bit name bit symbol at reset function h/w s/w in double buffer mode set the beginning address of buffer 1 area, using a relative value for the beginning address of buffer 0. b1b0 0 0 = 8 bytes 0 1 = 16 bytes 1 0 = 64 bytes 1 1 = 128 bytes 0 : single buffer mode 1 : double buffer mode 0 : toggle bit clear disabled 1 : writing 1 clears the toggle bit and data0 is used as the next data pid. 0 is always read when reading. 0 : normal mode 1 : contin uous toggle mode (valid at interrupt in transfer) 0 : out (data is received from the host.) 1 : in (data is transmitted to the host.) b7b6 0 0 : transfer disabled 0 1 : bulk transfer 1 0 : interrupt transfer 1 1 : isochronous transfer o o o o o o o o o o o o : state remaining w r b7 b0 response pid bit not used pid03 [1:0] b7:b2 0 ep03 control register 1 ( ep03con1) [address 001a 16 ] bit name bit symbol at reset function h/w s/w b1 b0 0 0 : nak 0 1 : automatic response (ack, nak, data0, data1) 1 x : stall at occurrence of over-max. packet size : b1 is set to 1 by the hardware. write 0 when writing. 0 is read when reading. o o o o : state remaining 000000 w r 1-49 38k0 group user s manual hardware functional description fig. 66 structure of ep03 control register 2 b7 b0 b0val03 b7:b1 0 ep03 control register 2 ( ep03con2) [address 001b 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 0 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). write 0 when writing. 0 is read when reading. 00 0 00 0 0 w r b7 b0 b1val03 b7:b1 0 ep03 control register 3 ( ep03con3) [address 001c 16 ] bit name bit symbol at reset function h/w s/w o o o o : state remaining buffer 1 enable bit not used when the selected endpoint is in, writing 1 to this bit makes the transmitting data a set state (sie is possible to read). when the selected endpoint is out, writing 1 to this bit makes data reception possible (sie is possible to write). in double buffer mode this bit is valid. write 0 when writing. 0 is read when reading. 0000000 w r fig. 67 structure of ep03 control register 3 b7 b0 b0rdy03 b1rdy03 err03 b7:b3 0 0 0 0 0 0 ep03 interrupt source register (ep03req) [address 001d 16 ] bit name bit symbol at reset function h/w s/w o o o o o o o o usb function/endpoint 3 buffer 0 ready interrupt bit usb function/endpoint 3 buffer 1 ready interrupt bit usb function/endpoint 3 error interrupt bit not used 0 : no interrupt request issued 1 : interrupt request issued this bit is set to 1 when the buffer 0 is ready state (enabled to be read/written) on usb function/endpoint 3. 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued in single buffer mode this bit is invalid. this bit is set to 1 when the buffer 1 is ready state (enabled to be read/written) on usb function/endpoint 3 in double buffer mode. 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued this bit is set to 1 when stall response occurs on usb function/endpoint 3. 0 can be set by software, but 1 cannot be set. write 0 when writing. 0 is read when reading. 00000 w r fig. 68 structure of ep03 interrupt source register hardware 1-50 38k0 group user s manual functional description fig. 69 structure of ep03 byte number register 0 fig. 71 structure of ep03 max. packet size register b7 b0 b1byt03 [6:0] b7 0 0 ep03 byte number register 1 ( ep03byt1) [address 001f 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: these bits are invalid. double buffer mode : set the transmitting byte number of buffer 1. single buffer mode: these bits are invalid. double buffer mode : the received byte number of buffer 1 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? 0 0 ep03 byte number register 0 ( ep03byt0) [address 001e 16 ] bit name bit symbol at reset function h/w s/w in : transmit byte number bit out : receive byte number bit not used : state remaining single buffer mode: set the transmitting byte number. double buffer mode : set the transmitting byte number of buffer 0. single buffer mode: the received byte number is automatically set. double buffer mode : the received byte number of buffer 0 is automatically set. write 0 when writing. 0 is read when reading. o o o o ? fig. 70 structure of ep03 byte number register 1 b7 b0 mxps03 [6:0] b7 ep03 max. packet size register (ep03max) [address 0fec 16 ] 0 bit name bit symbol at reset function h/w s/w : state remaining o o o o max. packet size bit not used in : these bits are invalid. out : set the maximum packet size. write 0 when writing. 0 is read when reading. 0 w r 1-51 38k0 group user s manual hardware functional description b7 b0 ep03 beginning address set bit not used badd03 [4:0] b7:b5 0 ep03 buffer area set register ( ep03buf) [address 0fed 16 ] bit name bit symbol at reset function h/w s/w set the beginning address of ep03 s buffer area. (32-byte unit) b4b3b2b1b0 0 0 0 1 0 : 0040 16 0 0 0 1 1 : 0060 16 .............. 1 1 1 1 0 : 03c0 16 1 1 1 1 1 : 03e0 16 write 0 when writing. 0 is read when reading. o o o o : state remaining 000 w r fig. 72 structure of ep03 buffer area set register hardware 1-52 38k0 group user s manual functional description external bus interface (exb) the external bus interface (exb) controls the data transfer be- tween the external mcu and the 38k0 group s cpu or its cpu channel it is a data transfer course by the interrupt processing between the external mcu and the 38k0 group s cpu. memory channel it is a data transfer course by direct ram access of the memory channel controller between the external mcu and the 38k0 group s memory (multichannel ram) cpu channel [interrupt type] memory channel [direct ram access type] 38k0 group usb bus (usb host) external mcu cpu program rom peripheral functions external bus interface (exb) usb multichannel ram fig. 73 external bus interface address cs, rd, wr, dma acknowledge access cycle time from externals: 3 clocks or more of 5 clocks or more of fig. 74 data transfer timing of memory channel memory (multichannel ram). the external bus interface is shown below. data transfer of memory channel when the burst mode is selected with the burst bit of the memory channel operation mode register, data transfer can be carried out at the highest speed. after the external bus interface detects a rise of external read signal/write signal and synchronizes it with the in- ternal clock 1-53 38k0 group user s manual hardware functional description exb pin assignment the external bus interface (exb) pins are shown bellow. the 38k0 group can transmit/receive a data to/from an external mcu, using the following signals: control input signal ................ 4 (excs, exa0, exrd, exwr) data input/output pin .............. 8 (dq 0 to dq 7 ) interrupt output signal ............ 1 (exint) additionally, the dma interface signal and the buffer status read select signal of 38k0 group can be set up per one by the program. control input signal ................ 3 (extc, exdack, exrd, exa1) interrupt output signal ............ 1 (exdreq) external chip select external address external read external write external data external interrupt dma request terminal count dma acknowledge status read select external pins cpu multichannel ram external bus interface (exb) 38k0 group p3 4 /excs [ l ] p3 7 /exa0 [address] p3 6 /exrd [ l ] p3 5 /exwr [ l ] p1 0 /dq 0 /an 0 p1 7 /dq 7 /an 7 [data] p3 3 /exint [ l ] p4 0 /exdreq/rxd [ l ] p4 2 /extc/s clk [ l ] p4 1 /exdack/txd [ l ] p4 3 /exa 1 /s rdy [ h ] 8 : functions as normal ports just after reset. fig. 75 external bus interface (exb) pin assignment hardware 1-54 38k0 group user s manual functional description exb block diagram the block diagram of external bus interface (exb) is shown below. the external bus interface (exb) consists of: (1) external i/o interface part (2) cpu interface part (3) internal memory interface part (4) transmit/receive data buffer part external i/o interface cpu interface index register external i/o configuration register exb interrupt source enable register cch_wr external mcu bus cch_rd p3 4 /excs cpu channel txb_rdy controller rxb_rdy p3 7 /exa0 p3 6 /exrd memory channel control memory channel operation mode register memory channel transmit buffer control transmit buffer register receive buffer register memory channel controller end address register memory address counter memory channel status p3 5 /exwr mch_rd mch_wr mch_tc p4 1 /exdack/txd mrx_enb p4 2 /extc/s clk mtx_enb p4 3 /exa1/s rdy memory address request acknowledge memory read data memory write data p3 3 /exint mch_req p4 0 /exdreq/rxd fifo_stt mrdsel stt_sel buf_wr transmit/receive data buffer exoe p1 0 /dq 0 /an 0 p1 7 /dq 7 /an 7 multichannel ram command decoder output selector decoder data selector configuration signal internal memory interface : functions as normal ports just after reset. fig. 76 block diagram of external bus interface (exb) 1-55 38k0 group user s manual hardware functional description (1) external i/o interface part the external i/o interface part consists of a command decoder and an output selector. a command decoder generates the follow- ing signals to each unit. cpu interface part cpu channel read (cch_rd) cpu channel write (cch_wr) internal memory interface part memory channel read (mch_rd) memory channel write (mch_wr) memory channel terminal count (mch_tc) transmit/receive data buffer part buffer write (buf_wr) external i/o interface part status selection (stt_sel) output enable (exoe) access to the cpu channel can be controlled only by setup of external signals. access to the memory channel can be controlled by the value of the external i/o configuration register and the state (mrx_enb, mtx_enb signals) of the internal memory interface part. the output selector has the function which selects from the state of cpu channel (txb_rdy and rxd_rdy) and the state of memory channel (mch_req) as the signal assigned to p3 3 / exint pin and p4 0 /exdreq/rxd pin. (2) cpu interface part the cpu interface part consists of the decoder/data selector of the cpu channel, the cpu write register and cpu channel con- troller decoder/data selector of cpu channel a write operation to the cpu register is performed by generating a write signal for each register with an address decode signal and a write signal. a read operation from the cpu register is performed by generat- ing an output enable signal of the internal data bus with an module select signal and a read signal and generating a select signal for each register with an address decode signal. cpu write register there are three cpu write registers as follows: exb interrupt source enable register index register external i/o configuration register the exb interrupt source register is a read-only register. a status signal of the cpu channel controller and a status signal of the memory channel controller in the internal memory interface part are generated. cpu channel controller the cpu channel controller generates the following signals, using bits 0 and 1 (rxb_enb, txb_enb) of exb interrupt source en- able register. memory channel transmitting buffer control signal (mrd_sel), generated in the internal memory interface part cpu channel command signal (cch_rd, cch_wr), generated in the external i/o interface part signals rxb_rdy/rxb_full and txb_rdy/txb_empty, gener- ated with read/write signals from the cpu channel hardware 1-56 38k0 group user s manual functional description (3) internal memory interface part the internal memory interface part consists of the cpu register and the memory channel controller. cpu register the cpu register consists of the follows: memory channel operation mode register memory address counter end address register the cpu can set the beginning address into the memory address counter when the memory channel operation enable bit (mc_enb) of exb interrupt source enable register is 0 . when this bit is 1 , the write operation from the cpu is invalid and each access from the external bus causes count-up operation. memory channel controller the cpu register consists of the follows: main sequencer internal memory request signal generating circuit external memory channel request signal generating circuit address end detection circuit terminal end input processing circuit (4) transmit/receive data buffer part the transmit/receive data buffer part consists of the 8-bit transmit buffer register (txbuf) and the 8-bit receive buffer register (rxbuf). both cpu channel and memory channel use the same transmit buffer register/receive buffer register to transfer a data to an exter- nal mcu bus. (5) external pin the external bus interface has the following pins to connect with an external mcu bus. chip select ........................... p3 4 /excs address ................................ p3 7 /exa0 data ...................................... p1 0 /dq 0 /an 0 to p1 7 /dq 7 /an 7 read .................................... p3 6 /exrd write ..................................... p3 5 /exwr interrupt request .................. p3 3 /exint it also has the following pins to connect with an external dmac. each pin can be programmed for an ordinary port function or a dma interface pin function. dma request ........................ p4 0 /exdreq/rxd dma acknowledgment ......... p4 1 /exdack/txd terminal count ..................... p4 2 /extc/s clk it also has the status read select pin (p4 3 /exa1/s rdy pin) to con- firm a ready status of the data buffer from an external mcu bus this pin functions as a port just after reset. the status read select function can be set by a program. status read select ................ p4 3 /exa1/s rdy cpu channel: communication with 38k0 group cpu when a read/write operation is performed from an external mcu bus in address signal exa0 = h , the interrupt is generated and the 38k0 group cpu can confirm its access. the 38k0 group cpu judges the interrupt source and it starts a data transmission/recep- tion with an external mcu bus. memory channel: communication with 38k0 group memory multichannel ram when a read/write operation is performed from an external mcu bus in address signal exa0 = l , access to the multichannel ram is performed. then an address of the multichannel ram is made by the external bus interface and it is increased at each access completion. consequently, fifo access is performed. even if a read/write operation is performed in dack = l instead of excs = l and exa0 = l , fifo access to the multichannel ram is performed. the beginning address and the end address must be set by the cpu in advance. 1-57 38k0 group user s manual hardware functional description p3 3 /exint pin any one of the following signals for this pin can be selected: txb_rdy (transmit buffer ready) output rxb_rdy (receive buffer ready) output mch_req (memory channel request) output either txb_rdy or rxb_rdy is normally selected. the memory channel request is for an access request signal to the memory channel. in a small system, a data transfer processing to the internal memory is performed in the interrupt routine. according to that situation, the 38k0 group has the function automatically to switch an interrupt factor attached on the interrupt pin by program. p4 0 /exdreq/rxd pin this pin is a port at the initial state. which signal can be set by program. rxb_rdy (receive buffer ready) output mch_req (memory channel request) output mch_req of dmac is normally selected. the output method of the memory channel request signal depends on the burst bit (burst) of memory channel operation mode register. when the burst bit is 0 , this signal is periodically output at each 1-byte transfer. (see figures 94 and 97.) when the burst bit is 1 , this signal is continuously output while the memory address counter is counting from the beginning ad- dress to the end address (see figures 95 and 98.) p4 1 /exdack/txd pin this pin is a port at the initial state. the dma acknowledge signal can be set by program. the dma acknowledge signal dack = l is the same state as that of cs = l and a0 = l . access to multichannel ram is started by a rise of read signal or write signal which is set during this term. note : if the dma acknowledge signal and the chip select signal are simultaneously active (dack = l and cs = l ), also set the address signal a0 to l . if a0 is h , the memory channel and the cpu channel are activated simultaneously and it might cause some error. p4 2 /extc/s clk pin this pin is a port at the initial state. the terminal count signal can be set by program. if the terminal count signal is set at one bus cycle while a memory channel operation write is being performed, the 38k0 group con- firms that its bus cycle is the write cycle of the last data and sets the memory channel status bits to 11 2 , and the interrupt is gener- ated and the memory channel operation ends even if the memory address counter has not reached the end address. the cpu can obtain the last address where the data is written by reading out the value of memory address counter. (see figure 96.) hardware 1-58 38k0 group user s manual functional description exb register list the exb register list is shown below. fig. 77 exb related registers (1) exb interrupt source enable register this register enables/disables access from an external bus and an internal interrupt. ?xb interrupt source register this register indicates the state of cpu channel s transmit/receive buffer register and the memory channel. the same value can be read out from the external mcu bus by using the buffer status read select signal (a1 pin = h ). ?xb index register/register windows 1, 2 the accessible register is switched by treating addresses 0034 16 and 0035 16 as a register window depending on the value of exb index register at address 0033 16 . external i/o configuration register this register selects the function of each pin. transmit/receive buffer register this register consists of the receive buffer register (rxbuf) and the transmit buffer register (txbuf) memory channel operation mode register this register sets the operation mode of the memory channel. memory address counter this is a counter to set the beginning address which fifo ac- cesses. this register is increased by access from the external mcu bus. end address register this register is to set the end address which fifo accesses. mc_enb txb_enb rxb_emb mc_sts[1:0] txb_empty rxb_full index[2:0] 0 : 0 fixed : not used low_win[7:0] high_win[7:0] exb sfr symbol bit7 bit6 bit5 bit4 bit3 00000 bit2 bit1 bit0 exbicon exbireq exbindex exbreg1 exbreg2 0030 16 0031 16 0033 16 0034 16 0035 16 exb interrupt source enable register exb interrupt source register register window 1 (low) register window 2 (high) exb index register address register name index bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00 16 low low a1_ctr int_ctr[2:0] exb_ctr high high tc_ctr dak_ctr[1:0] drq_ctr[1:0] 01 16 low at cpu read : rxbuf[7:0] at cpu write : txbuf[7:0] high 02 16 low burst mc_dir[1:0] high 03 16 low im_a[7:0] high 00000 im_a[10:8] 04 16 low end_a[7:0] high 00000 end_a[10:8] external i/o configu- ration register transmit/receive buffer register memory channel ope- ration mode register memory address counter end address register exb sfr register name symbol exbcfgl exbcfgh rxbuf/txbuf mchmod memadl memadh endadl endadh 0 : 0 fixed : not used fig. 78 exb related registers (2) 1-59 38k0 group user s manual hardware functional description exb related registers the exb related registers are shown below. b7 b0 cpu channel receive enable bit cpu channel transmit enable bit memory channel operation enable bit not used rxb_enb txb_enb mc_enb b7:b3 0 0 0 e xb interrupt source enable register ( exbicon) [address 0030 16 ] ( note ) 00 000 bit name bit symbol at reset function h/w s/w 0 : operation disabled (interrupt disabled) 1 : operation enabled (receive buffer full interrupt enabled) 0 : operation disabled (interrupt disabled) 1 : operation enabled (transmit buffer empty interrupt enabled) 0 : operation disabled (memory channel operation end interrupt disabled) 1 : operation enabled (memory channel operation end interrupt disabled) write 0 when writing. 0 is read when reading. o o o o o o o o : state remaining w r note: do not set each bit simultaneously. fig. 79 structure of exb interrupt source enable register b7 b0 rxb_full txb_empty mc_sts [1:0] ( note 2 ) b7:b4 0000 0 0 0 0 (note 3) 0 (note 4) 0 e xb interrupt source register ( exbireq) [address 0031 16 ] ( note 1 ) bit name bit symbol at reset function h/w s/w o o o o o : state remaining receive buffer full bit transmit buffer empty bit memory channel status bits not used 0 : receive buffer empty 1 : receive buffer full 0 : transmit buffer full 1 : transmit buffer empty b3b2 0 0 : memory channel operation stopped 0 1 : memory channel being operating; no external access 1 0 : memory channel being operating; external accessing 1 1 : memory channel operation end; memory channel operation end interrupt generated write 0 when writing. 0 is read when reading. notes 1 : when the the exa1 pin control bit of external i/o configuration register is 1 , the external mcu bus can read this register contents by setting the exa1 pin to h . 2 : the memory channel status bits indicate the status of memory channel. in mc_enb = 0 these bits are always 00 2 . when the memory channel operation ends, these bits are set to 11 2 and the memory channel operation end interrupt is generated. these bits can be read out during operation, so that it will show that whether the external mcu bus is accessing or not. 3 : this bit is cleared to 0 when reading the transmit/receive buffer register in the cpu channel receive enable bit = 1 or when the cpu channel receive enable bit is 0 . 4 : this bit is cleared to 0 when writing to the transmit/receive buffer register in the cpu channel transmit enable bit = 1 or when the cpu channel transmit enable bit is 0 . w r fig. 80 structure of exb interrupt source register hardware 1-60 38k0 group user s manual functional description b7 b0 index [2:0] b7:b3 0 exb index register (exbindex) [address 0033 16 ] 00000 bit name bit symbol at reset function h/w s/w o o o o index bits not used the accessible register, using the register window, depends on these index bits contents as follows: b2b1b0 0 0 0 : external i/o configuration register 0 0 1 : transmit/receive buffer register 0 1 0 : memory channel operation mode register 0 1 1 : memory address counter 1 0 0 : end address register 1 0 1 : do not set. 1 1 0 : do not set. 1 1 1 : do not set. write 0 when writing. 0 is read when reading. : state remaining w r fig. 81 structure of exb index register b7 b0 low_win [7:0] in- definite in- definite register window 1 (exbreg1) [address 0034 16 ] bit name bit symbol at reset function h/w s/w oo the accessible register, using this register window, depends on the exb index register contents as follows: index value 00 16 : external i/o configuration register 01 16 : transmit/receive buffer register 02 16 : memory channel operation mode register 03 16 : memory address counter 04 16 : end address register w r b7 b0 high_win [7:0] in- definite in- definite register window 2 (exbreg2) [address 0035 16 ] bit name bit symbol at reset function h/w s/w oo the accessible register, using this register window, depends on the exb index register contents as follows: index value 00 16 : external i/o configuration register 01 16 : transmit/receive buffer register 02 16 : memory channel operation mode register 03 16 : memory address counter 04 16 : end address register w r fig. 82 structure of register window 1 fig. 83 structure of register window 2 1-61 38k0 group user s manual hardware functional description b7 b0 exb_ctr int_ctr [2:0] a1_ctr b7:b5 index = 00 16 : external i/o configuration register (exbcfgl) [address 0034 16 ] 0 0 0 000 bit name bit symbol at reset function h/w s/w 0 : port 1 : exb function pin selects a signal of p3 3 /exint pin. on/off is programmed by each bit. an output logical sum of p3 3 /exint pins set for on are performed and it is output as an l active signal. b3b2b1 0 0 1 : rxb_rdy (rxbuf ready) output 0 1 0 : txb_rdy (txbuf ready) output 1 0 0 : mch_req (memory channel request) output others : do not set. 0 : port 1 : a1 input (used to read status) write 0 when writing. 0 is read when reading. exb pin control bit (pins p1 0 to p1 7 , p3 0 to p3 4 ) p3 3 /exint pin control bit p4 3 /exa1 pin control bit not used o o o o o o o o : state remaining w r fig. 84 index00[low]; structure of external i/o configuration register fig. 85 index00[high]; structure of external i/o configuration register b7 b0 drq_ctr [1:0] dak_ctr [1:0] tc_ctr b7:b5 index = 00 16 : external i/o configuration register (exbcfgh) [address 0035 16 ] 0 0 0 000 bit name bit symbol at reset function h/w s/w b1b0 0 0 : port 0 1 : do not set. 1 0 : exdreq function; rxb_rdy (rxbuf ready) output 1 1 : exdreq function; mch_req (memory channel request) output specifies p4 1 /exdack/txd pin function. selects which mode; requiring read or write signal, or not requiring it for use of dma acknowledge function. b3b2 0 0 : port 0 1 : do not set. 1 0 : exdack function; dma acknowledge input (mode for read and write signals used together) 1 1 :exdack function; dma acknowledge input (mode for read and write signals not required) 0 : port 1 : extc (terminal count) input write 0 when writing. 0 is read when reading. p4 0 /exdreq/rxd pin control bit p4 1 /exdack/txd pin control bit p4 2 /extc/s clk pin control bit not used o o o o o o o o : state remaining w r hardware 1-62 38k0 group user s manual functional description b7 b0 rxbuf/ txbuf 0 index =01 16 : transmit/receive buffer register (rxbuf/txbuf) [address 0034 16 ] bit name bit symbol at reset function h/w s/w oo the data received from an external bus is written here at the rise timing of external write signal. the data transmitted to an external bus is written here at the timing of internal cpu write or memory write. the receive buffer register (rxbuf) contents can be read out by reading to this address with the cpu. the data which the cpu has written to this address is stored in the transmit buffer register (txbuf). however, do not perform write operation with the cpu to this address if the memory channel direction control bits of memory channel operation mode register is 10 2 (transmit mode) and the memory channel status bits of exb interrupt source register are 01 2 or 10 2 (memory channel being operating). w r fig. 86 index01[low]; structure of transmit/receive buffer register b7 b0 mc_dir [1:0] burst b7:b3 0 0 index =02 16 : memory channel operation mode register (mchmod) [address 0034 16 ] 00000 bit name bit symbol at reset function h/w s/w b1b0 0 0 : operation disabled 0 1 : receive mode 1 0 : transmit mode 1 1 : do not set. 0 : cycle mode (each byte transfer according to assertion or negation) 1 : burst mode (continuous transfer till the terminal count) write 0 when writing. 0 is read when reading. o o o o o o : state remaining memory channel direction control bit burst bit not used w r fig. 87 index02[low]; structure of memory channel operation mode register b7 b0 im_a [7:0] 0 index = 03 16 : memory address counter (memadl) [address 0034 16 ] bit name bit symbol at reset function h/w s/w oo register to set the low-order address of memory channel operation beginning. this contents are increased each time one memory access ends. w r fig. 88 index03[low]; structure of memory address counter 1-63 38k0 group user s manual hardware functional description b7 b0 im_a [10:8] b7:b3 0 index = 03 16 : memory address counter (memadh) [address 0035 16 ] 00000 bit name bit symbol at reset function h/w s/w o o o o : state remaining not used register to set the high-order address of memory channel operation start. this contents are increased each time one memory access ends. write 0 when writing. 0 is read when reading. w r fig. 89 index03[high]; structure of memory address counter b7 b0 end_a [7:0] 0 index = 04 16 : end address register (endadl) [address 0034 16 ] bit name bit symbol at reset function h/w s/w oo : state remaining register to set the low-order address of memory channel operation end. w r fig. 90 index04[low]; structure of end address register b7 b0 end_a [10:8] b7:b3 0 index = 04 16 : end address register (endadh) [address 0035 16 ] 00000 bit name bit symbol at reset function h/w s/w o o o o : state remaining not used register to set the high-order address of memory channel operation end. write 0 when writing. 0 is read when reading. w r fig. 91 index04[high]; structure of end address register hardware 1-64 38k0 group user s manual functional description ??? 1 cs = 0 a0 = 1 cs = 0 read exrd ? ? ? 1 (receive buffer full interrupt enabled) ? l . if the cpu channel receive enable bit (rxb_enb) is 0 , both the receive buffer full bit (rxb_full) and the receive buffer ready signal (rxb_rdy) to an external are inactive. ? l and wxa0 = h , it will result in as follows: the data is written into the receive buffer (rxbuf) negation of the receive buffer ready signal (rxb_rdy) to an external is made the rxb_full interrupt is generated. ? 0 . exb operation timing diagram (1) cpu channel receiving operation cpu channel receiving operation is shown bellow. fig. 92 cpu channel receiving operation 1-65 38k0 group user s manual hardware functional description #0 #1 txb_rdy txb_rdy #0 #1 ? ? ? ? ? ? ? ? 1 (transmit buffer empty interrupt enabled) ? 0 , both the transmit buffer empty bit (txb_empty) and the transmit buffer ready signal (txb_rdy) to an external are inactive. ? 0 and assertion of the transmit buffer ready signal (txb_rdy) to an external is made. ? l and exa0 = h , it will result in as follows: the contents of the transmit buffer (txbuf) is read out the transmit buffer empty bit (txb_empty) is set to 1 negation of the transmit buffer ready signal (txb_rdy) to an external is made. a0 = 1 cs = 0 a0 = 1 cs = 0 (2) cpu channel transmitting operation cpu channel transmitting operation is shown bellow. fig. 93 cpu channel tranmitting operation hardware 1-66 38k0 group user s manual functional description dma acknowledge exdack #0 #1 mch_req mch_req mwr detection mwr detection #0 #1 012 3 5 req req 0100 16 0101 16 0102 16 ack ack dma request exdreq ? ? ?? ? ?? ? ? ? ? ? 0 cs = 0 a0 = 0 cs = 0 1-67 38k0 group user s manual hardware functional description dack = 0 dack = 0 dack = 0 #0 #1 #2 mch_req #0 #1 #2 012 3 5 req req req 0100 16 0101 16 0102 16 0103 16 ack ack ack dma acknowledge exdack mwr detection mwr detection dma request exdreq ? ? ? ? ? ? ??? ??? ? ? x cs = 1 a0 = x cs = 1 a0 = x cs = 1 hardware 1-68 38k0 group user s manual functional description tc #0 #1 mch_req #0 #1 012 3 (5) 5 req 0100 16 0101 16 0102 16 ack ack dma acknowledge exdack mwr detection mwr detection dma request exdreq ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 (burst mode) memory address counter (example) 0100 16 end address register (example) 0107 16 1-69 38k0 group user s manual hardware functional description #0 #1 mch_req mch_req #0 #1 012 34 5 req req 0100 16 0101 16 0102 16 ack ack dma acknowledge exdack mrd detection mrd detection dma request exdreq ? ? ? ? ? ?? ?? ? ? ? ? ? ? ? 0 a0 = x cs = 1 dack = 0 a0 = x cs = 1 hardware 1-70 38k0 group user s manual functional description #0 #1 #2 mch_req #0 #1 #2 012 3 4 5 req req req 0100 16 0101 16 0102 16 0103 16 ack ack ack dma acknowledge exdack mrd detection mrd detection dma request exdreq ? ? ?? ? ? ? ?? ??? ? ? ? ? 1 (burst mode) memory address counter (example) 0100 16 end address register (example) 0102 16 1-71 38k0 group user s manual hardware functional description multichannel ram the 38k0 group has the built-in multichannel ram including the small logic circuit (ram i/f) instead of ordinary ram. the multichannel ram has the usb channel and the exb channel in addition to the cpu channel. the multichannel ram controls access from cpu, usb and exb, synchronizing control with . s access has priority to the exb s. the one wait function (onw function) of 38000 series cpu is used internally to control access with the cpu. when receiving an access request from the usb or the exb, the multichannel ram outputs onw signal to wait the cpu for one clock, and access of the usb or the exb is performed. if the multichannel ram is outputting onw signal while the cpu is in the state of reading/writing for the ram area, the cpu read cycle or write cycle is extended by 1 period of h hardware 1-72 38k0 group user s manual functional description multichannel ram operation example the multichannel ram operation example is shown below. this example shows the case that an external mcu uses the 38k0 group as a peripheral lsi (usb controller). the following explains that the external mcu reads out the data which is received via the usb. ? ? ? ? ? ? ? ? 1-73 38k0 group user s manual hardware functional description comparator and control circuit the comparator and control circuit compares an analog input volt- age with the comparison voltage, and then stores the result in the a-d conversion registers 1, 2. when an a-d conversion is com- pleted, the control circuit sets the ad conversion completion bit and the ad interrupt request bit to 1 . note that because the comparator consists of a capacitor cou- pling, set f(system clock) to 500 khz or more during an a-d conversion. fig. 102 structure of a-d control register fig. 103 10-bit a-d mode reading a - d c o n t r o l r e g i s t e r ( a d c o n : a d d r e s s 0 0 3 6 1 6 ) a d c o n v e r s i o n c o m p l e t i o n b i t 0 : c o n v e r s i o n i n p r o g r e s s 1 : c o n v e r s i o n c o m p l e t e d a n a l o g i n p u t p i n s e l e c t i o n b i t s 0 0 0 : p 1 0 / d q 0 / a n 0 0 0 1 : p 1 1 / d q 1 / a n 1 0 1 0 : p 1 2 / d q 2 / a n 2 0 1 1 : p 1 3 / d q 3 / a n 3 1 0 0 : p 1 4 / d q 4 / a n 4 1 0 1 : p 1 5 / d q 5 / a n 5 1 1 0 : p 1 6 / d q 6 / a n 6 1 1 1 : p 1 7 / d q 7 / a n 7 n o t u s e d ( i n d e f i n i t e a t r e a d ) ( t h e s e b i t s a r e w r i t e d i s a b l e d b i t s . ) b 7 b 0 10-bit reading (read address 0038 16 before 0037 16 ) note : bits 2 to 7 of address 0038 16 become 0 at reading. b 8 b 7 b 6 b 5 b4 b3 b 2 b1 b0 b 7 b0 b 9 b7 b 0 b 9 b 8 b 7 b6 b5 b 4 b 3 b2 b7 b 0 0 ( a d d r e s s 0 0 3 8 1 6 ) (a d d r e s s 0 0 3 7 1 6 ) 8-bit reading (read only address 0037 16 ) (address 0037 16 ) a-d converter the functional blocks of the a-d converter are described below. [a-d conversion register 1, 2 (ad1, ad2)] 0037 16 , 0038 16 the a-d conversion register is a read-only register that stores the result of an a-d conversion. when reading this register during an a-d conversion, the previous conversion result is read. bit 7 of the a-d conversion register 2 must be set to 0 .not only 10-bit reading but also only high-order 8-bit reading of conversion result can be performed by selecting the reading procedure of the a-d conversion registers 1, 2 after a-d conversion is completed (in figure 103). the 8-bit reading inclined to msb is performed when reading the a-d converter register 1 after a-d conversion is started or reset; and when the a-d converter register 1 is read after reading the a- d converter register 2, the 8-bit reading inclined to lsb is performed. [a-d control register (adcon)] 0036 16 the a-d control register controls the a-d conversion process. bits 0 to 2 select a specific analog input pin. bit 3 signals the comple- tion of an a-d conversion. the value of this bit remains at 0 during an a-d conversion, and changes to 1 when an a-d con- version ends. writing 0 to this bit starts the a-d conversion. comparison voltage generator the comparison voltage generator divides the voltage between v ref and av ss into 1024, and that outputs the comparison volt- age. the a-d converter successively compares the comparison voltage v ref in each mode, dividing the v ref voltage (see below), with the input voltage. 10-bit reading v ref = ? 1023) 8-bit reading v ref = ? 255) channel selector the channel selector selects one of the input ports p1 7 /an 7 p1 0 / an 0 . v ref 256 v ref 1024 hardware 1-74 38k0 group user s manual functional description fig. 104 a-d converter block diagram p 1 0 / d q 0 / a n 0 p 1 1 / d q 1 / a n 1 p 1 2 / d q 2 / a n 2 p 1 3 / d q 3 / a n 3 p 1 4 / d q 4 / a n 4 p 1 5 / d q 5 / a n 5 p 1 6 / d q 6 / a n 6 p 1 7 / d q 7 / a n 7 d a t a b u s a - d c o n t r o l r e g i s t e r ( a d d r e s s 0 0 3 6 1 6 ) v ss b 7b 0 3 1 0 a-d control circuit comparator r e s i s t o r l a d d e r a-d conversion register 2 a-d conversion register 1 (address 0038 16 ) (address 0037 16 ) c h a n n e l s e l e c t o r a - d i n t e r r u p t r e q u e s t v ref 1-75 38k0 group user s manual hardware functional description fig. 106 structure of watchdog timer control register fig. 105 block diagram of watchdog timer watchdog timer the watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). the watchdog timer consists of an 8-bit watchdog timer l and an 8-bit watchdog timer h. standard operation of watchdog timer when any data is not written into the watchdog timer control reg- ister (address 0039 16 ) after resetting, the watchdog timer is in the stop state. the watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 0039 16 ) and an internal reset occurs at an underflow of the watch- dog timer h. accordingly, programming is usually performed so that writing to the watchdog timer control register (address 0039 16 ) may be started before an underflow. when the watchdog timer control reg- ister (address 0039 16 ) is read, the values of the high-order 6 bits of the watchdog timer h, stp instruction disable bit (bit 6), and watchdog timer h count source selection bit (bit 7) are read. initial value of watchdog timer at reset or writing to the watchdog timer control register (address 0039 16 ), each watchdog timer h and l is set to ff 16 . 0 , the count source becomes the underflow signal of watchdog timer l. the detection time is set to 131.072 ms at sys- tem clock 8 mhz frequency. when this bit is set to 1 , the count source becomes the system clock divided by 16. the detection time in this case is set to 512 0 after resetting. 0 , the stp instruction is enabled. when this bit is 1 , the stp instruction is disabled. once the stp instruction is executed, an internal reset occurs. when this bit is set to 1 , it cannot be rewritten to 0 by program. this bit is cleared to 0 after resetting. s y s t e m c l o c k 0 1 1 / 1 6 reset f f 1 6 i s s e t w h e n w a t c h d o g t i m e r c o n t r o l r e g i s t e r i s w r i t t e n t o . w a t c h d o g t i m e r l ( 8 ) watchdog timer h count source selection bit w a t c h d o g t i m e r h ( 8 ) d a t a b u s f f 1 6 i s s e t w h e n w a t c h d o g t i m e r c o n t r o l r e g i s t e r i s w r i t t e n t o . s t p i n s t r u c t i o n d i s a b l e b i t s t p i n s t r u c t i o n r e s e t c i r c u i t internal reset b 0 stp instruction disable bit 0: stp instruction enabled 1: stp instruction disabled watchdog timer h count source selection bit 0: watchdog timer l underflow 1: system clock/16 watchdog timer h (for read-out of high-order 6 bit) w a t c h d o g t i m e r c o n t r o l r e g i s t e r ( w d t c o n : a d d r e s s 0 0 3 9 1 6 ) b 7 hardware 1-76 38k0 group user s manual functional description fig. 107 example of reset circuit fig. 108 reset sequence 0 v 0 v v cc reset v cc reset (note) 0.2v cc poweron power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc = 4.0 v (standard) vcc = 3.0 v (l version) r e s e t i n t e r n a l r e s e t d a t a f ( l level for 16 cycles or more of x in . then the reset pin is returned to an h level (the power source voltage should be between 4.0 v and 5.25 v for standard or between 3.0 v and 5.25 v for l ver- sion, and the oscillation should be stable), reset is released. after the reset is completed, the program starts from the address con- tained in address fffd 16 (high-order byte) and address fffc 16 (low-order byte). make sure that the reset input voltage is 0.8 v for v cc of 4.0 v (standard), it is 0.6 v for v cc of 3.0 v (l version). 1-77 38k0 group user s manual hardware functional description pll circuit (frequency synthesizer) the pll circuit generates f vco (pll output clock), which is re- quired for f usb (usb clock) and f syn (f usb division clock), from f(x in ) (external input reference clock). figure 109 shows the pll circuit block diagram. it is possible to input 6 or 12 mhz clock from the externals as a standard clock input. when using the usb function, set the pll operation mode selection bit so that fvco may be set to 48 mhz. the pll circuit operates by setting the pll operation enable bit to 1 . when supplying f vco to the usb block, wait for the oscillation stable time (1ms or less) of pll before selecting f vco with the usb clock selection bit. according to the setting of the usb clock division ratio selection bit, the division clock of f usb is supplied to f syn . when using this clock as system clock, set the usb clock division ratio selection bit so that it may be set to 6 mhz, 8 mhz or 12 mhz. (however, using it only when f usb is 48mhz is recommended). fig. 109 block diagram of pll circuit pll f usb f ( x i n ) f vco p l l c o n division circuit f s y n (address 0ff8 16 ) u s b c o n (address 0010 16 ) hardware 1-78 38k0 group user s manual functional description fig. 110 structure of pll control register p l l c o n t r o l r e g i s t e r ( p l l c o n : a d d r e s s 0 f f 8 1 6 ) not used (return 0 when read) usb clock division ratio selection bits b4b3 0 0: divided by 8 (f syn = f usb /8) 0 1: divided by 6 (f syn = f usb /6) 1 0: divided by 4 (f syn = f usb /4) 1 1: not selected pll operation mode selection bits b6b5 0 0: not multiplied (f vco = f xin ) 0 1: double (f vco = f xin ? ? ? 1-79 38k0 group user s manual hardware functional description clock generating circuit an oscillation circuit can be formed by connecting a resonator be- tween x in and x out . use the circuit constants in accordance with the resonator manufacturer s recommended values. no external resistor is needed between x in and x out since a feed-back resis- tor exists on-chip. frequency control either f syn or f(x in ) can be selected as an internal system clock. furthermore, the frequency of internal clock pll cir- cuit . (2) f(x in ) clock the frequency applied to the x in pin is used as an internal system clock frequency. oscillation control (1) stop mode if the stp instruction is executed, the internal clock h level, and the x in oscillator stops. when the oscillation stabi- lizing time set after stp instruction released bit is 0, the prescaler 12 is set to ff 16 and timer 1 is set to 01 16 . when the oscillation stabilizing time set after stp instruction released bit is 1, set the sufficient time for oscillation of used oscillator to stabi- lize since nothing is set to the prescaler 12 and timer 1. x in divided by 16 is compulsorily connected to the input of the prescaler 12. oscillator restarts when an external interrupt (includ- ing usb resume interrupt) is received, but the internal clock h until timer 1 underflows. the internal clock l level to the reset pin until the oscillation is stable since a wait time will not be generated automatically. (2) wait mode if the wit instruction is executed, the internal clock h level, but the oscillator does not stop. the internal clock 1 before ex- ecuting of the stp or wit instruction. when releasing the stp state, the prescaler 12 and timer 1 will start counting the clock x in divided by 16. accordingly, set the timer 1 interrupt enable bit to 0 before executing the stp instruc- tion. 1 , evaluate time to stabilize oscillation of the used oscillator and set the value to the timer 1 and prescaler 12. hardware 1-80 38k0 group user s manual functional description fig. 114 system clock generating circuit block diagram (single-chip mode) fig. 111 ceramic resonator or quartz-crystal oscilltor circuit fig. 112 external clock input circuit fig. 113 structure of misrg c i n c o u t x i n x o u t x o u t e x t e r n a l o s c i l l a t i o n c i r c u i t o p e n v cc v ss x i n m i s r g ( m i s r g : a d d r e s s 0 f f b 1 6 ) o s c i l l a t i o n s t a b i l i z i n g t i m e s e t a f t e r s t p i n s t r u c t i o n r e l e a s e d b i t 0 : a u t o m a t i c a l l y s e t 0 1 1 6 t o t i m e r 1 , f f 1 6 t o p r e s c a l e r 1 2 1 : a u t o m a t i c a l l y s e t n o t h i n g n o t u s e d ( i n d e f i n i t e a t r e a d ) b 0 b 7 p l l 1 / 8 1 / 41 / 6 f u s b x i n x o u t f s i o f a d 1 / 8 1 / 4 1 / 2 1 / 1 s r q s r q s r q 1 / 2 f f 1 6 0 1 1 6 1 / 2 1 / 2 1 / 2 f v c o f s y n u s b c l o c k s e l e c t i o n b i t u s b c l o c k d i v i s i o n r a t i o n s e l e c t i o n b i t s s y s t e m c l o c k d i v i s i o n r a t i o n s e l e c t i o n b i t s t i m e r 1 p r e s c a l e r 1 2 r e s e t o r s t p i n s t r u c t i o n t i m i n g 1-81 38k0 group user s manual hardware functional description fig. 115 state transitions of clock n o t e s r e s e t c m 7 1 0 cm6 0 1 x in 8-divide mode f( p l l c i r c u i t i n d e t a i l s f o r e n a b l i n g / d i s a b l i n g p l l o p e r a t i o n a n d u s a g e n o t e s o f f s y n . 5 : s e t t h e s y s t e m c l o c k t o x i n w h e n e n t e r i n g s t o p m o d e . 6 : i n a l l m o d e s , s w i t c h i n g t o w a i t m o d e i s p o s s i b l e . w h e n i t i s r e l e a s e d , t h e m c u r e t u r n s t o t h e o r i g i n a l m o d e . i n w a i t m o d e t h e t i m e r s c a n o p e r a t e . c m 5 1 0 r e m a r k s : t h i s d i a g r a m a s s u m e s t h a t t h e 6 m h z s i g n a l s a r e a p p l i e d t o x i n p i n . x in 4-divide mode f( 1 0 c m 6 0 1 c m 7 0 1 c m 6 0 1 c m 7 1 0 x i n 2 - d i v i d e m o d e f ( 0 1 x in through mode f( 0 1 f( syn ) through mode f( 1 0 under planning f( syn ) through mode f( 0 1 cm6 0 1 note : set pllcon [4:3] = 00 before switching the system clock from x in to f syn . cm5 0 1 cm6 0 1 note : set pllcon [4:3] = 01 before switching the system clock from x in to f syn . c m 5 0 1 cm5 0 1 note : set pllcon [4:3] = 00 before switching the system clock from x in to f syn . note : set pllcon [4:3] = 01 before switching the system clock from x in to f syn . hardware 1-82 38k0 group user s manual functional description flash memory mode the 38k0 group s flash memory version has an internal new dinor (divided bit line nor) flash memory that can be rewritten with a single power source when v cc is 4.5 to 5.25 v, and 2 power sources when v cc is 3.0 to 4.5 v. for this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and the cpu rewrite mode in which the flash memory can be manipulated by the central processing unit (cpu). summary table 9 lists the summary of the 38k0 group s flash memory ver- sion. this flash memory version has some blocks on the flash memory as shown in figure 116 and each block can be erased. the flash memory is divided into user rom area and boot rom area. in addition to the ordinary user rom area to store the mcu op- eration control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the user s application sys- tem. this boot rom area can be rewritten in only parallel i/o mode. table 9 summary of 38k0 group s flash memory version notes 1: in the parallel i/o mode or the standard serial i/o mode, use the exclusive external equipment flash programmer which support s the 38k0 group (flash memory version). 2: the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. this boot rom area can be re- written in only parallel i/o mode. item power source voltage (vcc) program/erase v pp voltage (v pp ) flash memory mode erase block division user rom area boot rom area program method erase method program/erase control method number of commands number of program/erase times data retention period rom code protection specifications 4.00 5.25 v (standard), 3.00 5.25 v (l version) (program and erase in 4.00 to 5.25 v of vcc.) 3.00 4.00 v(only l version) (program and erase in 3.00 to 5.25 v of vcc.) 4.50 5.25 v 3 modes; flash memory can be manipulated as follows: cpu rewrite mode: manipulated by the central processing unit (cpu). parallel i/o mode: manipulated using an external programmer ( note 1 ) standard serial i/o mode: manipulated using an external programmer ( note 1 ) 1 block (32 kbytes) 1 block (4 kbytes) ( note 2 ) byte program batch erasing program/erase control by software command 6 commands 100 times 10 years available in parallel i/o mode and standard serial i/o mode 1-83 38k0 group user s manual hardware functional description fig. 116 block diagram of built-in flash memory (1) cpu rewrite mode in cpu rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the central process- ing unit (cpu). in cpu rewrite mode, only the user rom area shown in figure 116 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite con- trol program must be transferred to internal ram area to be executed before it can be executed. microcomputer mode and boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the stan- dard serial i/o mode becomes unusable.) see figure 116 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset by pulling the p1 6 (ce ) pin high, the cnv ss pin high, the cpu starts operating using the control program in the boot rom area. this mode is called the boot mode. block address block addresses refer to the maximum address of each block. these addresses are used in the block erase command. u s e r r o m a r e a 4 kb y t e s f f f f 1 6 b o o t r o m a r e a notes 1 : the boot rom area can be rewritten in only parallel i/o mode. (access to any other areas is inhibited.) 2 : to specify a block, use the maximum address in the block. b l o c k 1 : 3 2 k b y t e s 8000 16 f0 0 0 1 6 f f f f 1 6 hardware 1-84 38k0 group user s manual functional description outline performance (cpu rewrite mode) cpu rewrite mode is usable in the single-chip or boot mode. the only user rom area can be rewritten in cpu rewrite mode. in cpu rewrite mode, the cpu erases, programs and reads the in- ternal flash memory as instructed by software commands. this rewrite control program must be transferred to a memory such as the internal ram before it can be executed. the mcu enters cpu rewrite mode by applying 4.50 v to 5.25 v to the cnv ss pin and setting 1 to the cpu rewrite mode select bit (bit 1 of address 0ffe 16 ). software commands are accepted once the mode is entered. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verified by reading the status register. figure 117 shows the flash memory control register. bit 0 is the ry/by status flag used exclusively to read the operat- ing status of the flash memory. during programming and erase operations, it is 0 (busy). otherwise, it is 1 (ready). this is equivalent to the ry/by pin function in parallel i/o mode. bit 1 is the cpu rewrite mode select bit. when this bit is set to 1 , the mcu enters cpu rewrite mode. software commands are accepted once the mode is entered. in cpu rewrite mode, the flash memory control register (address 0ffe 16 ) fmcr ( note 1 ) ry/by status flag 0: busy (being written or erased) 1: ready cpu rewrite mode select bit ( note 2 ) 0: normal mode (software commands invalid) 1: cpu rewrite mode (software commands acceptable) cpu rewrite mode entry flag 0: normal mode (software commands invalid) 1: cpu rewrite mode flash memory reset bit ( note 3 ) 0: normal operation 1: reset user area / boot area select bit ( note 4 ) 0: user rom area accessed 1: boot rom area accessed reserved bits (indefinite at read/ 0 at write) b0 b 7 n o t e s1 : t h e c o n t e n t s o f f l a s h m e m o r y c o n t r o l r e g i s t e r a r e x x x 0 0 0 0 1 j u s t a f t e r r e s e t r e l e a s e . 2 : f o r t h i s b i t t o b e s e t t o 1 , t h e u s e r n e e d s t o w r i t e 0 a n d t h e n 1 t o i t i n s u c c e s s i o n . i f i t i s n o t t h i s p r o c e d u r e , t h i s b i t w i l l n o t b e s e t t o 1 . a d d i t i o n a l l y , i t i s r e q u i r e d t o e n s u r e t h a t n o i n t e r r u p t w i l l b e g e n e r a t e d d u r i n g t h a t i n t e r v a l . u s e t h e c o n t r o l p r o g r a m i n t h e a r e a e x c e p t t h e b u i l t - i n f l a s h m e m o r y f o r w r i t e t o t h i s b i t . 3 : t h i s b i t i s v a l i d w h e n t h e c p u r e w r i t e m o d e s e l e c t b i t i s 1 . s e t t h i s b i t 3 t o 0 s u b s e q u e n t l y a f t e r s e t t i n g b i t 3 t o 1 . 4 : u s e t h e c o n t r o l p r o g r a m i n t h e a r e a e x c e p t t h e b u i l t - i n f l a s h m e m o r y f o r w r i t e t o t h i s b i t . cpu becomes unable to access the internal flash memory directly. therefore, use the control program in a memory other than inter- nal flash memory for write to bit 1. to set this bit to 1 , it is necessary to write 0 and then write 1 in succession. the bit can be set to 0 by only writing 0 . bit 2 is the cpu rewrite mode entry flag. this flag indicates 1 in cpu rewrite mode, so that reading this flag can check whether cpu rewrite mode has been entered or not. bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory. this bit is used when exiting cpu rewrite mode and when flash memory access has failed. when the cpu rewrite mode select bit is 1 , setting 1 for this bit resets the control circuit. to set this bit to 1 , it is necessary to write 0 and then write 1 in succession. to release the reset, it is necessary to set this bit to 0 . bit 4 is the user area/boot area select bit. when this bit is set to 1 , boot rom area is accessed, and cpu rewrite mode in boot rom area is available. in boot mode, this bit is set to 1 auto- matically. reprogramming of this bit must be in a memory other than internal flash memory. figure 118 shows a flowchart for setting/releasing cpu rewrite mode. fig. 117 structure of flash memory control register 1-85 38k0 group user s manual hardware functional description fig. 118 cpu rewrite mode set/release flowchart e n d s t a r t execute read array command or reset flash memory by setting flash memory reset bit (by writing 1 and then 0 in succession) (note 3) s i n g l e - c h i p m o d e o r b o o t m o d e ( n o t e 1 ) s e t c p u m o d e r e g i s t e r ( n o t e 2 ) u s i n g s o f t w a r e c o m m a n d e x e c u t e e r a s e , p r o g r a m , o r o t h e r o p e r a t i o n j u m p t o c o n t r o l p r o g r a m t r a n s f e r r e d i n m e m o r y o t h e r t h a n i n t e r n a l f l a s h m e m o r y ( s u b s e q u e n t o p e r a t i o n s a r e e x e c u t e d b y c o n t r o l p r o g r a m i n t h i s m e m o r y ) t r a n s f e r c p u r e w r i t e m o d e c o n t r o l p r o g r a m t o m e m o r y o t h e r t h a n i n t e r n a l f l a s h m e m o r y n o t e s1 : w h e n s t a r t i n g t h e m c u i n t h e s i n g l e - c h i p m o d e o r m e m o r y e x p a n s i o n m o d e , s u p p l y 4 . 5 v t o 5 . 2 5 v t o t h e c n v s s p i n u n t i l c h e c k i n g t h e c p u r e w r i t e m o d e e n t r y f l a g . 2 : s e t t h e s y s t e m c l o c k d i v i s i o n r a t i o n s e l e c t i o n b i t s o f c p u m o d e r e g i s t e r ( b i t s 6 a n d 7 a t a d d r e s s 0 0 3 b 1 6 ) . 3 : b e f o r e e x i t i n g t h e c p u r e w r i t e m o d e a f t e r c o m p l e t i n g e r a s e o r p r o g r a m o p e r a t i o n , a l w a y s b e s u r e t o e x e c u t e t h e r e a d a r r a y c o m m a n d o r r e s e t t h e f l a s h m e m o r y . write 0 to cpu rewrite mode select bit set cpu rewrite mode select bit to 1 (by writing 0 and then 1 in succession) c h e c k c p u r e w r i t e m o d e e n t r y f l a g hardware 1-86 38k0 group user s manual functional description notes on cpu rewrite mode take the notes described below when rewriting the flash memory in cpu rewrite mode. h , so that the pro- gram will begin at the address which is stored in addresses fffc 16 and fffd 16 of the boot rom area. 1-87 38k0 group user s manual hardware functional description software commands table 10 lists the software commands. after setting the cpu rewrite mode select bit to 1 , write a soft- ware command to specify an erase or program operation. each software command is explained below. ff 16 in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the contents of the specified ad- dress are read out at the data bus (d 0 to d 7 ). the read array mode is retained intact until another command is written. 70 16 is written in the first bus cycle, the contents of the status register are read out at the data bus (d 0 to d 7 ) by a read in the second bus cycle. the status register is explained in the next section. 50 16 in the first bus cycle. 40 16 is writ- ten in the first bus cycle. then, if the address and data to program are written in the 2nd bus cycle, the control circuit of flash memory (data programming and verification) will start a program. whether the write operation is completed can be confirmed by _____ reading the status register or the ry/by status flag. when the program starts, the read status register mode is entered automati- cally and the contents of the status register is read at the data bus (db 0 to db 7 ). the status register bit 7 (sr7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. in this case, the read status reg- ister mode remains active until the read array command (ff 16 ) is written. table 10 list of software commands (cpu rewrite mode) ____ during the program movement, the ry/by status flag of flash memory control register is set to 0 . when the program com- pletes, it becomes 1 . at program end, program results can be checked by reading the status register. fig. 119 program flowchart command program c l e a r s t a t u s r e g i s t e r r e a d a r r a y r e a d s t a t u s r e g i s t e r x x first bus cycle second bus cycle ff 16 70 16 50 16 40 16 write write write write xsrd r e a d write e r a s e a l l b l o c k s20 16 write x 20 16 w r i t e (note 1) wa (note 2) wd (note 2) block erase 2 0 1 6 write d0 16 w r i t eba ( n o t e 3 ) mode a d d r e s s m o d ea d d r e s s data (d 0 to d 7 ) (d 0 to d 7 ) (note 4) n o t e s 1 : s r d = s t a t u s r e g i s t e r d a t a 2 : w a = w r i t e a d d r e s s , w d = w r i t e d a t a 3 : b a = b l o c k a d d r e s s t o b e e r a s e d ( i n p u t t h e m a x i m u m a d d r e s s o f e a c h b l o c k . ) 4 : x d e n o t e s a g i v e n a d d r e s s i n t h e u s e r r o m a r e a . c y c l e n u m b e r 1 2 1 2 2 2 x x x x d a t a s t a r t w r i t e 4 0 1 6 s t a t u s r e g i s t e r r e a d program completed n o y e s w r i t e a d d r e s s w r i t e d a t a sr4 = 0 ? program error no yes s r 7 = 1 ? o r r y / b y = 1 ? w r i t e hardware 1-88 38k0 group user s manual functional description 20 16 in the first bus cycle and the confirmation command code 20 16 in the second bus cycle that follows, the operation of erase all blocks (erase and erase verify) starts. whether the erase all blocks command is terminated can be con- ____ firmed by reading the status register or the ry/by status flag of flash memory control register. when the erase all blocks operation starts, the read status register mode is entered automatically and the contents of the status register can be read out at the data bus (d 0 to d 7 ). the status register bit 7 (sr7) is set to 0 at the same time the erase operation starts and is returned to 1 upon comple- tion of the erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is writ- ten. ____ the ry/by status flag is 0 during erase operation and 1 when the erase operation is completed as is the status register bit 7. after the erase all blocks end, erase results can be checked by reading the status register. for details, refer to the section where the status register is detailed. 20 16 in the first bus cycle and the confirmation command code d0 16 and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. whether the block erase operation is completed can be confirmed ____ by reading the status register or the ry/by status flag of flash memory control register. at the same time the block erase opera- tion starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the block erase operation starts and is returned to 1 upon completion of the block erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is writ- ten. ____ the ry/by status flag is 0 during block erase operation and 1 when the block erase operation is completed as is the status reg- ister bit 7. after the block erase ends, erase results can be checked by read- ing the status register. for details, refer to the section where the status register is detailed. w r i t e 2 0 1 6 2 0 1 6 / d 0 1 6 b l o c k a d d r e s s erase completed n o y e s s t a r t write sr5 = 0 ? e r a s e e r r o r y e s no 2 0 1 6 : e r a s e a l l b l o c k s d 0 1 6 : b l o c k e r a s e s r 7 = 1 ? o r r y / b y = 1 ? s t a t u s r e g i s t e r r e a d fig. 120 erase flowchart 1-89 38k0 group user s manual hardware functional description table 11 definition of each bit in status register status register (srd) the status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. it can be read in the following ways: (1) by reading an arbitrary address from the user rom area after writing the read status register command (70 16 ) (2) by reading an arbitrary address from the user rom area in the period from when the program starts or erase operation starts to when the read array command (ff 16 ) is input. also, the status register can be cleared by writing the clear status register command (50 16 ). after reset, the status register is set to 80 16 . table 11 shows the status register. each bit in this register is ex- plained below. sequencer status (sr7) the sequencer status indicates the operating status of the flash memory. this bit is set to 0 (busy) during write or erase operation and is set to 1 when these operations ends. after power-on, the sequencer status is set to 1 (ready). erase status (sr5) the erase status indicates the operating status of erase operation. if an erase error occurs, it is set to 1 . when the erase status is cleared, it is set to 0 . program status (sr4) the program status indicates the operating status of write opera- tion. when a write error occurs, it is set to 1 . the program status is set to 0 when it is cleared. if 1 is written for any of the sr5 and sr4 bits, the program, erase all blocks, and block erase commands are not accepted. before executing these commands, execute the clear status regis- ter command (50 16 ) and clear the status register. each bit of srd0 bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) definition 1 0 sequencer status reserved erase status program status reserved reserved reserved reserved ready - terminated in error terminated in error - - - - status name busy - terminated normally terminated normally - - - - hardware 1-90 38k0 group user s manual functional description full status check by performing full status check, it is possible to know the execu- tion results of erase and program operations. figure 121 shows a full status check flowchart and the action to be taken when each error occurs. fig. 121 full status check flowchart and remedial procedure for errors r e a d s t a t u s r e g i s t e r s r 4 = 1 a n d s r5 = 1 ? n o y e s s r 5 = 0 ? y e s er a s e e r r o r n o s r 4 = 0 ? yes n o c o m m a n d s e q u e n c e e r r o r program error e n d ( b l o c k e r a s e , p r o g r a m ) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should an erase error occur, the block in error cannot be used. n o t e : w h e n o n e o f s r 5 a n d s r 4 i s s e t t o 1 , n o n e o f t h e p r o g r a m , e r a s e a l l b l o c k s , a n d b l o c k e r a s e c o m m a n d s i s a c c e p t e d . e x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d ( 5 0 1 6 ) b e f o r e e x e c u t i n g t h e s e c o m m a n d s . should a program error occur, the block in error cannot be used. 1-91 38k0 group user s manual hardware functional description functions to inhibit rewriting flash memory version to prevent the contents of internal flash memory from being read out or rewritten easily, this mcu incorporates a rom code protect function for use in parallel i/o mode and an id code check func- tion for use in standard serial i/o mode. 0 , the rom code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. the rom code protect is implemented in two levels. if level 2 is se- lected, the flash memory is protected even against readout by a shipment inspection lsi tester, etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to 00 , the rom code protect is turned off, so that the contents of internal flash memory can be read out or modified. once the rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use the serial i/o or cpu rewrite mode to rewrite the contents of the rom code pro- tect reset bits. fig. 122 structure of rom code protect control register r o m c o d e p r o t e c t c o n t r o l r e g i s t e r ( a d d r e s s f f d b 1 6 ) r o m c p reserved bits ( 1 at read/write) rom code protect level 2 set bits (romcp2) ( notes 1, 2 ) b3b2 0 0: protect enabled 0 1: protect enabled 1 0: protect enabled 1 1: protect disabled rom code protect reset bits ( note 3 ) b5b4 0 0: protect removed 0 1: protect set bits effective 1 0: protect set bits effective 1 1: protect set bits effective rom code protect level 1 set bits (romcp1) ( note 1 ) b7b6 0 0: protect enabled 0 1: protect enabled 1 0: protect enabled 1 1: protect disabled b 0 b 7 n o t e s1 : w h e n r o m c o d e p r o t e c t i s t u r n e d o n , t h e i n t e r n a l f l a s h m e m o r y i s p r o t e c t e d a g a i n s t r e a d o u t o r m o d i f i c a t i o n i n p a r a l l e l i / o m o d e . 2 : w h e n r o m c o d e p r o t e c t l e v e l 2 i s t u r n e d o n , r o m c o d e r e a d o u t b y a s h i p m e n t i n s p e c t i o n l s i t e s t e r , e t c . a l s o i s i n h i b i t e d . 3 : t h e r o m c o d e p r o t e c t r e s e t b i t s c a n b e u s e d t o t u r n o f f r o m c o d e p r o t e c t l e v e l 1 a n d r o m c o d e p r o t e c t l e v e l 2 . h o w e v e r , s i n c e t h e s e b i t s c a n n o t b e m o d i f i e d i n p a r a l l e l i / o m o d e , t h e y n e e d t o b e r e w r i t t e n i n s e r i a l i / o m o d e o r c p u r e w r i t e m o d e . hardware 1-92 38k0 group user s manual functional description id code check function use this function in standard serial i/o mode. when the contents of the flash memory are not blank, the id code sent from the pro- grammer is compared with the id code written in the flash memory to see if they match. if the id codes do not match, the commands sent from the programmer are not accepted. the id code consists of 8-bit data, and its areas are ffd4 16 to ffda 16 . write a pro- gram which has had the id code preset at these addresses to the flash memory. fig. 123 id code store addresses rom cord protect control id7 id6 id5 id4 id3 id2 id1 ffdb 16 ffda 16 ffd9 16 ffd8 16 ffd7 16 ffd6 16 ffd5 16 ffd4 16 address interrupt vector area 1-93 38k0 group user s manual hardware functional description (2) parallel i/o mode parallel i/o mode is the mode which parallel output and input soft- ware command, address, and data required for the operations (read, program, erase, etc.) to a built-in flash memory. use the ex- clusive external equipment flash programmer which supports the 38k0 group (flash memory version). refer to each programmer maker s handling manual for the details of the usage. user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in fig- ure 116 can be rewritten. both areas of flash memory can be operated on in the same way. the boot rom area is 4 kbytes in size. it is located at addresses f000 16 through ffff 16 . make sure program and block erase opera- tions are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 4 kbyte block. the boot rom area has had a standard serial i/o mode control pro- gram stored in it when shipped from the mitsubishi factory. there- fore, using the device in standard serial i/o mode, you must perform program and block erase in the user rom area. hardware 1-94 38k0 group user s manual functional description (3) standard serial i/o mode the standard serial i/o mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. this i/o is clock synchronized serial. this mode requires a purpose-specific pe- ripheral unit.the standard serial i/o mode is different from the parallel i/o mode in that the cpu controls flash memory rewrite (uses the cpu rewrite mode), rewrite data input and so forth. the standard serial i/o mode is started by connecting h to the p1 6 (ce) pin and h to the p4 2 (s clk ) pin and h to the cnv ss (v pp ) pin (apply 4.5 v to 5.25 v to vpp from an external source), and re- leasing the reset operation. (in the ordinary microcomputer mode, set cnvss pin to l level.) this control program is written in the boot rom area when the product is shipped from mitsubishi. accordingly, make note of the fact that the standard serial i/o mode cannot be used if the boot rom area is rewritten in parallel i/o mode. figure 124 shows the pin connections for the standard serial i/o mode. in standard serial i/o mode, serial data i/o uses the four serial i/o pins s clk , rxd, txd and s rdy (busy). the s clk pin is the trans- fer clock input pin through which an external transfer clock is input. the txd pin is for cmos output. the s rdy (busy) pin out- puts l level when ready for reception and h level when reception starts. serial data i/o is transferred serially in 8-bit units. in standard serial i/o mode, only the user rom area shown in figure 116 can be rewritten. the boot rom area cannot. in standard serial i/o mode, a 7-byte id code is used. when there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the id code matches. outline performance (standard serial i/o mode) in standard serial i/o mode, software commands, addresses and data are input and output between the mcu and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial i/o. in reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the s clk pin, and are then input to the mcu via the rxd pin. in transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the txd pin. the txd pin is for cmos output. transfer is in 8-bit units with lsb first. when busy, such as during transmission, reception, erasing or program execution, the s rdy (busy) pin is h level. accordingly, always start the next transfer after the s rdy (busy) pin is l level. also, data and status registers in a memory can be read after in- putting software commands. status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. here following explains software commands, status registers, etc. 1-95 38k0 group user s manual hardware functional description table 12 description of pin function (standard serial i/o mode) pin name signal name i/o v cc ,v ss power supply v cc e power supply cnv ss v pp i cnv ss 2 cnv ss 2i v ref analog reference voltage i dv cc , pv cc analog power supply pv ss analog power supply ____________ reset reset input i x in clock input i x out clock output o usbv ref usb reference voltage input tron usb reference voltage output o d0+,d0- usb upstream input i/o p0 0 to p0 7 input port p0 i p1 0 to p1 5 input port p1 i p1 6 input port p1 i p1 7 input port p1 i p2 0 to p2 7 input port p2 i p3 0 to p3 7 input port p3 i p4 0 rxd input i p4 1 txd output o p4 2 s clk input i p4 3 busy output o p5 0 to p5 7 input port p5 i p6 0 to p6 3 input port p6 i function apply 4.00 to 5.25 v (standard) or 3.00 to 5.25 v (l version) to the vcc pin and 0 v to the vss pin. connect this pin to vcc. connect this pin to v pp (v pp = 4.50 to 5.25 v). connect this pin to vss. connect this pin to vcc when not using. connect this pin to vcc. connect this pin to vss. to reset, input l level for 20 cycles or longer clocks of l level when not using. input l or h level, or keep open. input l or h level, or keep open. input l or h level, or keep open. input h level only at release of reset. input l or h level, or keep open. input l or h level, or keep open. input l or h level, or keep open. this is a serial data input pin. this is a serial data output pin. this is a serial clock input pin.input h level only at release of reset. this is a busy output pin. input l or h level, or keep open. input l or h level, or keep open. hardware 1-96 38k0 group user s manual functional description fig. 124 pin connection diagram in standard serial i/o mode (1) p0 6 1 2 3 4 7 8 9 10 11 12 13 14 15 16 5 6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p1 2 /dq 2 /an 2 p1 5 /dq 5 /an 5 cnv ss cnv ss 2 p6 0 (led 0 ) p6 1 (led 1 ) p6 2 (led 2 ) v cc v ss x in x out p6 3 (led 3 ) pv ss p2 3 p2 4 p1 3 /dq 3 /an 3 p1 4 /dq 4 /an 4 45 46 47 48 pv cc dv cc usbv ref tron d0+ d0- p2 0 p2 1 p2 2 p2 5 p2 6 p2 7 p5 0 /int 0 p5 1 /cntr 0 p5 2 /int 1 p5 3 p5 4 p5 5 p5 6 p5 7 p0 0 p0 1 p0 2 p0 3 p0 4 p0 5 p0 7 p4 0 /e x dreq/r x d p4 1 /e x dack/t x d p4 2 /e x tc/s clk p4 3 /e x a 1 /s rdy p3 0 p3 1 p3 2 p3 3 /e x int p3 4 /e x cs p3 5 /e x wr p3 6 /e x rd p3 7 /e x a0 p1 0 /dq 0 /an 0 p1 1 /dq 1 /an 1 reset p1 6 /dq 6 /an 6 p1 7 /dq 7 /an 7 v cc e v ref v pp vcc vss t x d busy r x d s clk reset connect to oscillator circuit. packa g e outline: 64p6u-a, 64p6q-a ( note 1 ) notes 1 : connect to vcc in the case of vcc = 4.5 v to 5.25 v. connect to v pp (= 4.5 v to 5.25 v) in the case of vcc = 3.0 v to 4.5 v. 2 : supply vcc at releasimg reset. mode setup method signal value cnvss 4.5 to 5.25 v s clk vcc ( note 2 ) reset vss 1-97 38k0 group user s manual hardware functional description software commands table 13 lists software commands. in standard serial i/o mode, erase, program and read are controlled by transferring software commands via the rxd pin. software commands are explained 2nd byte address (middle) 3rd byte address (high) 4th byte data output 5th byte data output 6th byte data output ..... data output to 259th byte data input to 259th byte ff 16 when id is not verified not acceptable 1st byte transfer notes1: shading indicates transfer from the internal flash memory microcomputer to a programmer. all other data is transferred from a programmer to the in- ternal flash memory microcomputer. 2: srd refers to status register data. srd1 refers to status register 1 data. 3: all commands can be accepted when the flash memory is totally blank. 4: address low is a 0 to a 7 ; address middle is a 8 to a 15 ; address high is a 16 to a 23 . address-high a 16 to a 23 are always 00 16 . here below. basically, the software commands of the standard se- rial i/o mode are the same as that of the parallel i/o mode, but the block erase function is excluded, and 4 commands are added: id check, download, version data output and boot rom area output functions. table 13 software commands (standard serial i/o mode) control command 1 page read 2 page program 41 16 address (middle) address (high) data input data input data input not acceptable not acceptable acceptable 3 erase all blocks a7 16 d0 16 srd1 output 4 read status register 70 16 srd output 5 clear status register 50 16 address (low) address (middle) not acceptable 6 id check function f5 16 acceptable 7 download function fa 16 size (low) size (high) address (high) check- sum id size id1 to id7 not acceptable 8 version data output function fb 16 data input to required number of times acceptable fc 16 version data output address (high) version data output data output version data output data output version data output data output version data output to 9th byte data output to 259th byte not acceptable 9 boot rom area output function version data output address (middle) hardware 1-98 38k0 group user s manual functional description 70 16 com- mand code is transferred with the 1st byte, the contents of the status register (srd) with the 2nd byte and the contents of status register 1 (srd1) with the 3rd byte are read. the contents of software commands are explained as follows. ff 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 to d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output se- quentially from the smallest address first synchronized with the fall of the clock. data0 data255 a 8 t o a 1 5 a 16 to a 23 f f 1 6 s c l k r x d t x d s r d y ( b u s y ) s r d o u t p u t s r d 1 o u t p u t s c l k r x d t x d s r d y ( b u s y ) 70 16 fig. 125 timing for page read fig. 126 timing for reading status register 1-99 38k0 group user s manual hardware functional description fig. 127 timing for clear status register 50 16 com- mand code is sent with the 1st byte, the aforementioned bits are cleared. when the clear status register operation ends, the s rdy (busy) signal changes from h to l level. s clk rxd txd s rdy (busy) 5 0 1 6 a 8 t o a 1 5 a 1 6 t o a 2 3 4 1 1 6 d a t a 0 d a t a 2 5 5 s clk rxd txd s rdy (busy) 41 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, as write data (d 0 to d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is auto- matically written. when reception setup for the next 256 bytes ends, the s rdy (busy) signal changes from h to l level. the result of the page program can be known by reading the status register. for more information, see the section on the status register. fig. 128 timing for page program hardware 1-100 38k0 group user s manual functional description a7 16 command code with the 1st byte. (2) transfer the verify command code d0 16 with the 2nd byte. with the verify command code, the erase operation will start and continue for all blocks in the flash memory. when erase all blocks end, the s rdy (busy) signal changes from h to l level. the result of the erase operation can be known by reading the status register. a7 16 d 0 1 6 s c l k r x d t x d s r d y ( b u s y ) fig. 129 timing for erase all blocks 1-101 38k0 group user s manual hardware functional description fa 16 command code with the 1st byte. (2) transfer the program size with the 2nd and 3rd bytes. (3) transfer the check sum with the 4th byte. the check sum is added to all data sent with the 5th byte onward. (4) the program to execute is sent with the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. fig. 130 timing for download f a 1 6 p r o g r a m d a t a program data data size (low) check sum s clk rxd txd s rdy (busy) d a t a s i z e ( h i g h ) hardware 1-102 38k0 group user s manual functional description fb 16 command code with the 1st byte. (2) the version information will be output from the 2nd byte on- ward. this data is composed of 8 ascii code characters. fig. 131 timing for version information output fb 16 x v e r s clk rxd txd s rdy (busy) fc 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 to d 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output se- quentially from the smallest address first synchronized with the fall of the clock. fig. 132 timing for boot rom area output f c 1 6 a 8 t o a 1 5 a 1 6 t o a 2 3 d a t a 0d a t a 2 5 5 s cl k rx d tx d s rdy (busy) 1-103 38k0 group user s manual hardware functional description f5 16 command code with the 1st byte. (2) transfer addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 ( 00 16 ) of the 1st byte of the id code with the 2nd, 3rd and 4th respec- tively. (3) transfer the number of data sets of the id code with the 5th byte. (4) transfer the id code with the 6th byte onward, starting with the 1st byte of the code. hardware 1-104 38k0 group user s manual functional description 80 16 . sequencer status (sr7) the sequencer status indicates the operating status of the the flash memory. after power-on and recover from deep power down mode, the se- quencer status is set to 1 (ready). this status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. erase status (sr5) the erase status indicates the operating status of erase opera- tion. if an erase error occurs, it is set to 1 . when the erase status is cleared, it is set to 0 . program status (sr4) the program status indicates the operating status of write opera- tion. if a write error occurs, it is set to 1 . when the program status is cleared, it is set to 0 . srd0 bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) definition 1 0 table 14 status register (srd) status name sequencer status reserved erase status program status reserved reserved reserved reserved ready - terminated in error terminated in error - - - - busy - terminated normally terminated normally - - - - 1-105 38k0 group user s manual hardware functional description 00 16 when power is turned on and the flag status is maintained even after the reset. table 15 status register 1 (srd1) 00 not verified 01 verification mismatch 10 reserved 11 verified sr15 (bit7) sr14 (bit6) sr13 (bit5) sr12 (bit4) sr11 (bit3) sr10 (bit2) sr9 (bit1) sr8 (bit0) boot update completed bit reserved reserved checksum match bit id check completed bits data reception time out reserved 1 update completed - - match time out - 0 not update - - mismatch normal operation - definition srd1 bits status name boot update completed bit (sr15) this flag indicates whether the control program was downloaded to the ram or not, using the download function. check sum consistency bit (sr12) this flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download func- tion. id check completed bits (sr11 and sr10) these flags indicate the result of id checks. some commands cannot be accepted without an id check. data reception time out (sr9) this flag indicates when a time out error is generated during data reception. if this flag is attached during data reception, the re- ceived data is discarded and the mcu returns to the command wait state. hardware 1-106 38k0 group user s manual functional description full status check results from executed erase and program operations can be known by running a full status check. figure 135 shows a flow- chart of the full status check and explains how to remedy errors which occur. r e a d s t a t u s r e g i s t e r s r 4 = 1 a n d s r5 = 1 ? n o y e s s r 5 = 0 ? y e s erase error n o s r 4 = 0 ? y e s no c o m m a n d s e q u e n c e e r r o r program error e n d ( e r a s e , p r o g r a m ) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should an erase error occur, the block in error cannot be used. note : when one of sr5 to sr4 is set to 1 , none of the program, erase all blocks, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. should a program error occur, the block in error cannot be used. fig. 135 full status check flowchart and remedial procedure for errors 1-107 38k0 group user s manual hardware functional description example circuit application for standard serial i/o mode figure 136 shows a circuit application for the standard serial i/o mode. control pins will vary according to a programmer, therefore see a programmer manual for more information. s r d y ( b u s y ) s cl k rxd txd cnvss c l o c k i n p u t b u s y o u t p u t d a t a i n p u t d a t a o u t p u t m 3 8 k 0 9 f 8 n o t e s 1 : c o n t r o l p i n s a n d e x t e r n a l c i r c u i t r y w i l l v a r y a c c o r d i n g t o a p r o g r a m m e r . f o r m o r e i n f o r m a t i o n , s e e t h e p r o g r a m m e r m a n u a l . 2 : i n t h i s e x a m p l e , t h e v p p p o w e r s u p p l y i s s u p p l i e d f r o m a n e x t e r n a l s o u r c e ( p r o g r a m m e r ) . t o u s e t h e u s e r s p o w e r s o u r c e , c o n n e c t t o 4 . 5 v t o 5 . 2 5 v . v p p p o w e r s o u r c e i n p u t v c c v c c p 1 6 ( c e ) fig. 136 example circuit application for standard serial i/o mode hardware 1-108 38k0 group user s manual notes on programming notes on programming processor status register the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. af- ter a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. interrupts the contents of the interrupt request bits do not change immedi- ately after they have been written. after writing to an interrupt request register, execute at least one instruction before perform- ing a bbc or bbs instruction. decimal calculations to calculate in decimal notation, set the decimal mode flag (d) to 1 , then execute an adc or sbc instruction. after executing an adc or sbc instruction, execute at least one instruction be- fore executing a sec, clc, or cld instruction. in decimal mode, the values of the negative (n), overflow (v), and zero (z) flags are invalid. timers when n (0 to 255) is written to a timer latch, the frequency divi- sion ratio is 1/(n+1). when a count source of timer x is switched, stop a count of timer x. multiplication and division instructions the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. the execution of these instructions does not change the con- tents of the processor status register. ports the contents of the port direction registers cannot be read. the following cannot be used: the data transfer instruction (lda, etc.) the operation instruction when the index x mode flag (t) is 1 the addressing mode which uses the value of a direction regis- ter as an index the bit-test instruction (bbc or bbs, etc.) to a direction register the read-modify-write instructions (ror, clb, or seb, etc.) to a direction register. use instructions such as ldm and sta, etc., to set the port direc- tion registers. a-d converter the comparator uses capacitive coupling amplifier whose charge will be lost if the clock frequency is too low. therefore, make sure that f(system clock) in the middle/high- speed mode is at least on 500 khz during an a-d conversion. do not execute the stp or wit instruction during an a-d conver- sion. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock 1-109 38k0 group user s manual hardware notes on programming definition of a-d conversion accuracy the a-d conversion accuracy is defined below (refer to figure 137). relative accuracy ? 0 to 1. ? 1023 to 1022. ? ? absolute accuracy this means a deviation from the ideal characteristics between 0 to v ref of actual a-d conversion characteristics. v ref 1024 vn: analog input voltage when the output data changes from n to n + 1 (n = 0 to 1022) 1 lsb at relative accuracy 1 lsb at absolute accuracy v ot 1022 analog voltage v ref v 1022 v n v 1 v 0 zero transition voltage (v 0t ) full-scale transition voltage (v fst ) non-linearity error= actual a-d conversion characteristics v n+1 n+1 n 1022 1023 1 0 ideal line of a-d conversion between v 0 to v 1022 output data b a a: 1lsb at relative accuracy b: v n+1 -v n c: difference between the ideal vn and actual vn differential non-linearity error= b-a a [lsb] c c a [lsb] fig. 137 definition of a-d conversion accuracy hardware 1-110 38k0 group user s manual notes on usage/data required for mask orders notes on usage handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (vcc pin) and gnd pin (vss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic or electrolytic capacitor of 1.0 the usb specification requires a driver-impedance 28 to 44 ?. ? make sure the usb d+/d- lines do not cross any other wires. keep a large gnd area to protect the usb lines. also, make sure you use a usb specification compliant connecter for the connec- tion. usbv ref pin treatment (noise elimination) connect a capacitor between the usbv ref pin and the vss pin. the capacitor should have a 2.2 in vcc = 3.0 to 3.6 v operation, connect the usbv ref pin directly to the vcc pin in order to supply power to the usb port circuit. in addition, you will need to disable the built-in usb reference volt- age circuit in this operation (set bit 4 of the usb control register to 0 .) if you are using the bus powered supply in this condition, the dc-dc converter must be placed outside the mcu. in vcc = 4.00 to 5.25 v operation, do not connect the external dc-dc converter to the usbv ref pin. use the built-in usb refer- ence voltage circuit. flash memory version the cnvss pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (v pp pin) as well. to improve the noise reduction, connect a track between cnvss pin and vss pin or vcc pin with 1 to 10 k ? ? ? ? 1-111 38k0 group user? manual hardware functional description supplement functional description supplement a-d converter a-d conversion is started by setting ad conversion completion bit to ?.?during a-d conversion, internal operations are performed as follows. 1. after the start of a-d conversion, a-d conversion register goes to ?0 16 . 2. the highest-order bit of a-d conversion register is set to ?,?and the comparison voltage vref is input to the comparator. then, v ref is compared with analog input voltage v in . 3. as a result of comparison, when v ref < v in , the highest-order bit of a-d conversion register becomes ?.?when v ref > v in , the highest-order bit becomes ?. by repeating the above operations up to the lowest-order bit of the a-d conversion register, an analog value converts into a digital value. a-d conversion completes at 122 clock cycles (15.25 s at system clock = 8 mhz, through mode) after it is started, and the result of the conversion is stored into the a-d conversion register. concurrently with the completion of a-d conversion, a-d conversion interrupt request occurs, so that the ad conversion interrupt request bit is set to ?. table 16 relative formula for a reference voltage v ref of a-d converter and v ref v ref 1024 ? 1 ? 10: a result of the first comparison to the tenth comparison table 17 change of a-d conversion register during a-d conversion at start of conversion first comparison second comparison third comparison after completion of tenth comparison 0 a result of a-d conversion ? 1 change of a-d conversion register 0 value of comparison voltage (v ref ) v ref 2 v ref 2 v ref 4 v ref 2 v ref 4 v ref 8 when n = 0 v ref = 0 when n = 1 to 1023 v ref = ? n n: value of a-d converter (decimal numeral) v ref 2 v ref 4 v ref 1024 ??? 0 0 000 0 000 1 0 0 00 0 0 0 0 0 10 0 0 0 0 000 ? 1 ? 2 00 0 0 0 0 0 1 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 ? 7 ? 8 ? 9 ? 10 hardware 1-112 38k0 group user s manual figures 138 shows the a-d conversion equivalent circuit, and fig- ure 139 shows the a-d conversion timing chart. fig. 138 a-d conversion equivalent circuit fig. 139 a-d conversion timing chart functional description supplement v ss v cc v ss v cc an 0 an 1 an 2 an 3 an 4 v ref v ss v ref v in c b1 b0 b2 about 2 kw sampling clock a-d control register built-in d-a converter reference clock chopper amplifier a-d conversion register 2 a-d conversion register 1 ad conversion interrupt request an 5 an 6 an 7 write signal for a-d control register ad conversion completion bit sampling clock chapter 2 application 2.1 i/o port 2.2 interrupt 2.3 timer 2.4 serial i/o 2.5 usb function 2.6 external bus interface (exb) 2.7 a-d converter 2.8 watchdog timer 2.9 reset 2.10 frequency synthesizer (pll) 2.11 clock generating circuit 2.12 standby function 2.13 flash memory 38k0 group user? manual application 2.1 i/o port 2-2 2.1 i/o port this paragraph explains the registers setting method and the notes related to the i/o ports. 2.1.1 memory map fig. 2.1.1 memory map of registers related to i/o port 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port p4 (p4) port p4 direction register (p4d) port p5 (p5) port p5 direction register (p5d) port p6 (p6) port p6 direction register (p6d) port p0 pull-up control register (pull0) port p5 pull-up control register (pull5) 000a 16 000b 16 000c 16 000d 16 0ff0 16 0ff2 16 38k0 group user s manual application 2-3 2.1 i/o port 2.1.2 related registers fig. 2.1.2 structure of port pi (i = 0 to 6) fig. 2.1.3 structure of port pi direction register (i = 0 to 6) port pi b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi 0 port pi 1 port pi 2 port pi 3 port pi 4 port pi 5 port pi 6 port pi 7 in output mode write read port latch in input mode write : port latch read : value of pins port pi (pi) (i = 0, 1, 2, 3, 4, 5, 6) (note) [address : 00 16 , 02 16 , 04 16 , 06 16, 08 16 , 0a 16 , 0c 16 ] ? ? ? ? ? ? ? ? note: since the following ports are not allocated, the corrrsponding bits can not be used. p4 4 to p4 7 p6 4 to p6 7 port pi direction register b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name port pi direction register 0 0 0 0 0 0 0 0 port pi direction register (pid) (i = 0, 1, 2, 3, 4, 5, 6) (note) [address : 01 16 , 03 16 , 05 16 , 07 16, 09 16 , 0b 16 , 0d 16 ] 0 : port pi 0 input mode 1 : port pi 0 output mode 0 : port pi 1 input mode 1 : port pi 1 output mode 0 : port pi 2 input mode 1 : port pi 2 output mode 0 : port pi 3 input mode 1 : port pi 3 output mode 0 : port pi 4 input mode 1 : port pi 4 output mode 0 : port pi 5 input mode 1 : port pi 5 output mode 0 : port pi 6 input mode 1 : port pi 6 output mode 0 : port pi 7 input mode 1 : port pi 7 output mode ? ? ? ? ? ? ? ? note: since the following ports are not allocated, the corrrsponding bits can not be used. p4 4 to p4 7 p6 4 to p6 7 38k0 group user? manual application 2.1 i/o port 2-4 fig. 2.1.4 structure of port p0 pull-up control register fig. 2.1.5 structure of port p5 pull-up control register b7 b6 b5 b4 b3 b2 b1 b0 rw 0 0 2 0 3 0 4 0 5 0 6 0 7 0 1 0 p0 0 pul l-up control bit port p0 pull-up control register (pull0) [address : 0ff0 16 ] b function at reset name port p0 pull-up control register 0 : no pull-up 1 : pull-up p0 0 pul l-up control bit 0 : no pull-up 1 : pull-up p0 0 pul l-up control bit 0 : no pull-up 1 : pull-up p0 0 pul l-up control bit 0 : no pull-up 1 : pull-up p0 0 pul l-up control bit 0 : no pull-up 1 : pull-up p0 0 pul l-up control bit 0 : no pull-up 1 : pull-up p0 0 pul l-up control bit 0 : no pull-up 1 : pull-up p0 0 pul l-up control bit 0 : no pull-up 1 : pull-up b7 b6 b5 b4 b3 b2 b1 b0 r w 0 0 2 0 3 0 40 50 60 7 0 1 0 p5 0 pul l-up control bit port p5 pull-up control register (pull5) [address : 0ff2 16 ] b function at reset name port p5 pull-up control register 0 : no pull-up 1 : pull-up p5 2 pul l-up control bit 0 : no pull-up 1 : pull-up nothing is arranged for this bit. this is a write disabled bit. when this bit is read out, the contents are 0 . nothing is arranged for these bits. these are write disabled bits. when these bits are read out, the contents are 0 . 38k0 group user s manual application 2-5 2.1 i/o port 2.1.3 handling of unused pins table 2.1.1 handling of unused pins pins/ports name p0, p1, p2, p3, p4, p5, p6 v ref x out usbv ref tron d0+, d0- handling set to the input mode and connect each to vcc or vss through a resistor of 1 k ? to 10 k ? . set to the output mode and open at l or h level. connect to vss (gnd). open, only when using an external clock. connect to v cc open connect each to vss through a resistor of 1 k ? to 10 k ? . 38k0 group user s manual application 2.1 i/o port 2-6 2.1.4 notes on input and output pins (1) modifying output data with bit managing instruction when the port latch of an i/o port is modified with the bit managing instruction* 1 , the value of the unspecified bit may be changed. reason the bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. accordingly, when these instructions are executed on a bit of the port latch of an i/o port, the following is executed to all bits of the port latch. as for a bit which is set for an input port : the pin state is read in the cpu, and is written to this bit after bit managing. as for a bit which is set for an output port : the bit value of the port latch is read in the cpu, and is written to this bit after bit managing. note the following : even when a port which is set as an output port is changed for an input port, its port latch holds the output data. as for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its port latch contents. * 1 bit managing instructions : seb , and clb instructions 38k0 group user s manual application 2-7 2.1 i/o port 2.1.5 termination of unused pins (1) terminate unused pins ? i/o ports : set the i/o ports for the input mode and connect them to v cc or v ss through each resistor of 1 k ? to 10 k ? . with regard to ports which can select the built-in pull-up resistor, the built-in pull- up resistor can be used. set the i/o ports for the output mode and open them at l or h . when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the system, thoroughly perform system evaluation on the user side. since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. (2) termination remarks ? i/o ports : do not open in the input mode. reason the power source current may increase depending on the first-stage circuit. an effect due to noise may be easily produced as compared with proper termination shown in (1). ? i/o ports : when setting for the input mode, do not connect to v cc or v ss directly. reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between a port and v cc (or v ss ). ? i/o ports : when setting for the input mode, do not connect multiple ports in a lump to v cc or v ss through a resistor. reason if the direction register setup changes for the output mode because of a program runaway or noise, a short circuit may occur between ports. at the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. 2-8 38k0 group user s manual application 2.2 interrupt 2.2 interrupt this paragraph explains the registers setting method and the notes related to the interrupt. 2.2.1 memory map fig. 2.2.1 memory map of registers related to interrupt 2.2.2 related registers 003f 16 interrupt control register 1 (icon1) interrupt request register 2 (ireq2) interrupt request register 1 (ireq1) 003e 16 003d 16 003c 16 0ff3 16 interrupt edge selection register (intedge) interrupt control register 2 (icon2) b7 b6 b5 b4 b3 b2 b1 b0 rw 0 0 2 0 3 0 4 0 5 0 6 0 7 0 1 0 usb bus reset interrupt request bit interrupt request register 1 (ireq1) [address : 3c 16 ] b function at reset name interrupt request register 1 usb sof interrupt request bit usb device interrupt request bit exb interrupt request bit int 0 interrupt request bit timer x interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ? 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? ? fig. 2.2.2 structure of interrupt request register 1 38k0 group user s manual application 2-9 2.2 interrupt b7 b6 b5 b4 b3 b2 b1 b0 rw 0 0 2 0 3 0 4 0 5 0 6 0 7 0 1 0 int 1 interrupt request bit interrupt request register 2 (ireq2) [address : 3d 16 ] b function at reset name interrupt request register 2 serial i/o receive interrupt request bit serial i/o transmit interrupt request bit cntr 0 interrupt request bit key-on wake-up interrupt request bit a/d conversion interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ? 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? nothing is arranged for this bits. this is a write disabled bit. when this bit is read out, the contents are 0 . nothing is arranged for this bits. this is a write disabled bit. when this bit is read out, the contents are 0 . fig. 2.2.3 structure of interrupt request register 2 fig. 2.2.4 structure of interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 rw 0 0 2 0 3 0 4 0 5 0 6 0 7 0 1 0 usb bus reset interrupt enable bit interrupt control register 1 (icon1) [address : 3e 16 ] b function at reset name interrupt control register 1 usb sof interrupt enable bit usb device interrupt enable bit exb interrupt enable bit int 0 interrupt enable bit timer x interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 2-10 38k0 group user? manual application 2.2 interrupt b7 b6 b5 b4 b3 b2 b1 b0 rw 0 0 2 0 3 0 4 0 5 0 6 0 7 0 1 0 int 1 interrupt enable bit interrupt control register 2 (icon2) [address : 3d 16 ] b function at reset name interrupt control register 2 serial i/o receive interrupt enable bit serial i/o transmit interrupt enable bit cntr 0 interrupt enable bit key-on wake-up interrupt enable bit a/d conversion interrupt enable bit fix this bit to 0 . 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled fix this bit to 0 . 0 : interrupt disabled 1 : interrupt enabled 0 0 fig. 2.2.5 structure of interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 rw 0 0 2 0 3 0 4 0 5 0 60 7 0 1 0 0 : falling edge active 1 : rising edge active int 0 interrupt edge selection bit interrupt edge selection register (intedge) [address : 0ff3 16 ] b function at reset name nothing is arranged for these bits. these are write disabled bits. when these bits are read out, the contents are 0 . interrupt edge selection register 0 : falling edge active 1 : rising edge active int 1 interrupt edge selection bit nothing is arranged for this bits. this is a write disabled bit. when this bit is read out, the contents are 0 . fig. 2.2.6 structure of interrupt edge selection register 38k0 group user s manual application 2-11 2.2 interrupt 2.2.3 interrupt source the 38k0 group permits interrupts of 15 sources. these are vector interrupts with a fixed priority system. accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. this priority is determined by hardware, but a variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. for interrupt sources, vector addresses and interrupt priority, refer to table 2.2.1. table 2.2.1 interrupt sources, vector addresses and priority of 38k0 group remarks low fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 high fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 notes 1: vector addresses contain interrupt jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. 3 : nothing is arranged in these vector addresses. 4 : fix bit 1 of interrupt control register 2 (address 003f 16 ) to 0 . vector addresses (note 1) non-maskable valid when usb mode valid when usb mode valid when usb mode valid when external bus is selected external interrupt (active edge selectable) stp release timer underflow external interrupt (active edge selectable) (note 4) valid when serial i/o is selected valid when serial i/o is selected external interrupt (active edge selectable) external interrupt (active edge selectable) non-maskable software interrupt interrupt source reset (note 2) usb bus reset usb sof usb device external bus int 0 timer x timer 1 timer 2 int 1 (note 3) serial i/o reception serial i/o transmission cntr 0 key-on wake up a-d conversion brk instruction priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 interrupt request generating conditions at reset at detection of usb bus reset signal (2.5 s interval se0) at detection of usb sof signal at detection of resume signal (k state or se0) or suspend signal (3 ms interval bus idle), or at completion of transaction at completion of reception or transmission or at completion of dma transmission at detection of either rising or falling edge of int 0 input at timer x underflow at timer 1 underflow at timer 2 underflow at detection of either rising or falling edge of int 1 input (note 4) at completion of serial i/o data reception at completion of serial i/o data transmission at detection of either rising or falling edge of cntr 0 input at falling of conjunction of input level for port p0 (at input mode) at completion of a-d conversion at brk instruction execution 2-12 38k0 group user s manual application 2.2 interrupt 2.2.4 interrupt operation when an interrupt request is accepted, the contents of the following registers just before acceptance of the interrupt requests is automatically pushed onto the stack area in the order of ? , ? and ? . ? high-order contents of program counter (pc h ) ? low-order contents of program counter (pc l ) ? contents of processor status register (ps) after the contents of the above registers are pushed onto the stack area, the accepted interrupt vector address enters the program counter and consequently the interrupt processing routine is executed. when the rti instruction is executed at the end of the interrupt processing routine, the contents of the above registers pushed onto the stack area are restored to the respective registers in the order of ? , ? and ? ; and the microcomputer resumes the processing executed just before acceptance of the interrupts. figure 2.2.7 shows an interrupt operation diagram. fig. 2.2.7 interrupt operation diagram i n t e r r u p t o c c u r s ( a c c e p t i n g i n t e r r u p t r e q u e s t ) e x e c u t i n g r o u t i n e s u s p e n d e d o p e r a t i o n r e s u m e p r o c e s s i n g : operation commanded by software : i n t e r n a l o p e r a t i o n p e r f o r m e d a u t o m a t i c a l l y contents of program counter (high-order) are pushed onto stack contents of program counter (low-order) are pushed onto stack contents of processor status register are pushed onto stack c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r a r e p o p p e d f r o m s t a c k contents of program counter (low-order) are popped from stack contents of program counter (high-order) are popped from stack r t i i n s t r u c t i o n i n t e r r u p t p r o c e s s i n g r o u t i n e 38k0 group user s manual application 2-13 2.2 interrupt (1) processing upon acceptance of interrupt request upon acceptance of an interrupt request, the following operations are automatically performed. ? the processing being executed is stopped. ? the contents of the program counter and the processor status register are pushed onto the stack area. figure 2.2.8 shows the changes of the stack pointer and the program counter upon acceptance of an interrupt request. ? concurrently with the push operation, the jump destination address (the beginning address of the interrupt processing routine) of the occurring interrupt stored in the vector address is set in the program counter, then the interrupt processing routine is executed. ? after the interrupt processing routine is started, the corresponding interrupt request bit is automatically cleared to 0 . the interrupt disable flag is set to 1 so that multiple interrupts are disabled. accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination address in the vector area corresponding to each interrupt. fig. 2.2.8 changes of stack pointer and program counter upon acceptance of interrupt request interrupt disable flag = 0 p r o g r a m c o u n t e r stack pointer program counter (low-order) p r o g r a m c o u n t e r ( h i g h - o r d e r ) pc l p c h ( s ) s p r o g r a m c o u n t e r s t a c k p o i n t e r pc l p c h (s) 3 s vector address (from interrupt vector area) i n t e r r u p t d i s a b l e f l a g = 1 interrupt request is accepted s t a c k a r e a (s) processor status register p r o g r a m c o u n t e r ( l o w - o r d e r ) program counter (high-order) (s) ( s ) 3 s t a c k a r e a 2-14 38k0 group user s manual application 2.2 interrupt (2) timing after acceptance of interrupt request the interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently being executed. figure 2.2.9 shows the time up to execution of interrupt processing routine and figure 2.2.10 shows the timing chart after acceptance of interrupt request. fig. 2.2.10 timing chart after acceptance of interrupt request fig. 2.2.9 time up to execution of interrupt processing routine interrupt request generated main routine interrupt processing routine 7 to 23 cycles (when f(x in ) = 6 mhz; system clock 8 mhz /through mode (8 mhz), 0.875 s to 2.875 s) 2 cycles 5 cycles start of interrupt processing 0 to 16 cycles waiting time for post-processing of pipeline stack push and vector fetch ? ? when executin g div instruction p c h p c l ps a l a h s , s p s s-2, sps s-1, sps p c b l b h a l , a h : c p u o p e r a t i o n c o d e f e t c h c y c l e (t h i s i s a n i n t e r n a l s i g n a l t h a t c a n n o t b e o b s e r v e d f r o m t h e e x t e r n a l u n i t . ) : v e c t o r a d d r e s s o f e a c h i n t e r r u p t : j u m p d e s t i n a t i o n a d d r e s s o f e a c h i n t e r r u p t : 0 0 1 6 o r 0 1 1 6 s y n c b l , b h a l , a h s p s data bus n o t u s e d a d d r e s s b u s s y n c r d w r 38k0 group user s manual application 2-15 2.2 interrupt 2.2.5 interrupt control the acceptance of all interrupts, excluding the brk instruction interrupt, can be controlled by the interrupt request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. figure 2.2.11 shows an interrupt control diagram. fig. 2.2.11 interrupt control diagram the interrupt request bit, interrupt enable bit and interrupt disable flag function independently and do not affect each other. an interrupt is accepted when all the following conditions are satisfied. interrupt request bit .......... 1 interrupt enable bit ........... 1 interrupt disable flag ........ 0 though the interrupt priority is determined by hardware, a variety of priority processing can be performed by software using the above bits and flag. table 2.2.2 shows a list of interrupt control bits according to the interrupt source. (1) interrupt request bits the interrupt request bits are allocated to the interrupt request register 1 (address 3c 16 ) and interrupt request register 2 (address 3d 16 ). the occurrence of an interrupt request causes the corresponding interrupt request bit to be set to 1 . the interrupt request bit is held in the 1 state until the interrupt is accepted. when the interrupt is accepted, this bit is automatically cleared to 0 . each interrupt request bit can be set to 0 , but cannot be set to 1 , by software. (2) interrupt enable bits the interrupt enable bits are allocated to the interrupt control register 1 (address 003e 16 ) and the interrupt control register 2 (address 3f 16 ). the interrupt enable bits control the acceptance of the corresponding interrupt request. when an interrupt enable bit is 0 , the corresponding interrupt request is disabled. if an interrupt request occurs when this bit is 0 , the corresponding interrupt request bit is set to 1 but the interrupt is not accepted. in this case, unless the interrupt request bit is set to 0 by software, the interrupt request bit remains in the 1 state. when an interrupt enable bit is 1 , the corresponding interrupt is enabled. if an interrupt request occurs when this bit is 1 , the interrupt is accepted (when interrupt disable flag = 0 ). each interrupt enable bit can be set to 0 or 1 by software. i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t i n t e r r u p t d i s a b l e f l a g b r k i n s t r u c t i o n r e s e t i n t e r r u p t r e q u e s t 2-16 38k0 group user s manual application 2.2 interrupt (3) interrupt disable flag the interrupt disable flag is allocated to bit 2 of the processor status register. the interrupt disable flag controls the acceptance of interrupt request except brk instruction. when this flag is 1 , the acceptance of interrupt requests is disabled. when the flag is 0 , the acceptance of interrupt requests is enabled. this flag is set to 1 with the sei instruction and is set to 0 with the cli instruction. when a main routine branches to an interrupt processing routine, this flag is automatically set to 1 , so that multiple interrupts are disabled. to use multiple interrupts, set this flag to 0 with the cli instruction within the interrupt processing routine. figure 2.2.12 shows an example of multiple interrupts. table 2.2.2 list of interrupt bits according to interrupt source usb bus reset usb sof usb device external bus int 0 timer x timer 1 timer 2 int 1 serial i/o receive serial i/o transmit cntr 0 key-on wake-up a-d converter interrupt enable bit address 003e 16 003e 16 003e 16 003e 16 003e 16 003e 16 003e 16 003e 16 003f 16 003f 16 003f 16 003f 16 003f 16 003f 16 bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b2 b3 b4 b5 b6 interrupt request bit address 003c 16 003c 16 003c 16 003c 16 003c 16 003c 16 003c 16 003c 16 003d 16 003d 16 003d 16 003d 16 003d 16 003d 16 bit b0 b1 b2 b3 b4 b5 b6 b7 b0 b2 b3 b4 b5 b6 interrupt source 38k0 group user s manual application 2-17 2.2 interrupt fig. 2.2.12 example of multiple interrupts reset i = 1 i n t e r r u p t 1 i = 1 i = 0 i = 1 rti i n t e r r u p t r e q u e s t 1 i n t e r r u p t r e q u e s t nesting t i m e multiple interrupt c1 = 1 c2 = 1 i = 0 i n t e r r u p t r e q u e s t 2 m a i n r o u t i n e i n t e r r u p t 2 r t i : i n t e r r u p t d i s a b l e f l a g : i n t e r r u p t e n a b l e b i t o f i n t e r r u p t 1 : i n t e r r u p t e n a b l e b i t o f i n t e r r u p t 2 : s e t a u t o m a t i c a l l y . : s e t b y s o f t w a r e . i c1 c2 i = 0 i = 0 c 1 = 0 , c 2 = 0 2-18 38k0 group user s manual application 2.2 interrupt 2.2.6 int interrupt the int interrupt requests is generated when the microcomputer detects a level change of each int pin (int 0 , int 1 ). (1) active edge selection int 0 and int 1 can be selected from either a falling edge or rising edge detection as an active edge by the interrupt edge selection register. in the 0 state, the falling edge of the corresponding pin is detected. in the 1 state, the rising edge of the corresponding pin is detected. 38k0 group user s manual application 2-19 2.2 interrupt 2.2.7 key input interrupt a key input interrupt request is generated by applying l level to any port p0 pin that has been set to the input mode. in other words, it is generated when and of the input level goes from 1 to 0 . (1) connection example when key input interrupt is used when using the key input interrupt, compose an active-low key matrix which inputs to port p0. figure 2.2.13 shows a connection example and the port p0 block diagram when using a key input interrupt. in the connection example in figure 2.2.13, a key input interrupt request is generated by pressing one of the keys corresponding to ports p0 0 to p0 3 . fig. 2.2.13 connection example and port p0 block diagram when using key input interrupt ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? p o r t p 0 0 l a t c h port p0 0 direction register = 0 port p0 1 latch port p0 1 direction register = 0 p o r t p 0 2 l a t c h port p0 2 direction register = 0 port p0 3 latch port p0 3 direction register = 0 p o r t p 0 4 l a t c h port p0 4 direction register = 1 p o r t p 0 5 l a t c h port p0 5 direction register = 1 p o r t p 0 6 l a t c h port p0 6 direction register = 1 p o r t p 0 7 l a t c h port p0 7 direction register = 1 p 0 0 i n p u t p 0 1 i n p u t p 0 2 i n p u t p 0 3 i n p u t p0 4 output p0 5 output p 0 6 o u t p u t p0 7 output pull 0 register bit 7 = 0 p o r t p 0 i n p u t r e a d i n g c i r c u i t p o r t p x x l l e v e l o u t p u t ? p-channel transistor for pull-up ? ? cmos output buffer k e y i n p u t i n t e r r u p t r e q u e s t pull 0 register bit 6 = 0 pull 0 register bit 5 = 0 pull 0 register bit 4 = 0 pull 0 register bit 3 = 1 pull 0 register bit 2 = 1 pull 0 register bit 1 = 1 pull 0 register bit 0 = 1 2-20 38k0 group user s manual application 2.2 interrupt (2) related registers setting figure 2.2.14 shows the related registers setting (corresponding to figure 2.2.13). fig. 2.2.14 registers setting related to key input interrupt (corresponding to figure 2.2.13) p0d 0 10 1 ireq2 b0 b7 b0 b7 key-on wake-up interrupt request port p0 direction register (address 01 16 ) bits corresponding to p0 7 to p0 0 interrupt request register 2 (address 3d 16 ) 1 pull0 1 b0 b7 port p0 pull-up control register (address 0ff0 16 ) p0 0 to p0 3 pull-up 10 0 icon2 b0 b7 interrupt control register 2 (address 3f 16 ) 0 ke y -on wake-u p interru p t: enabled 0: input port 1: output port 1 11 0 1 0 38k0 group user? manual application 2-21 2.2 interrupt 2.2.8 notes on interrupts (1) change of relevant register settings when the setting of the following registers or bits is changed, the interrupt request bit may be set to ?? when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ?nterrupt edge selection register (address 0ff3 16 ) ?imer x mode register (address 23 16 ) set the above listed registers or bits as the following sequence. fig. 2.2.15 sequence of changing relevant register reason when setting the following, the interrupt request bit may be set to ?? ?hen setting external interrupt active edge concerned register: interrupt edge selection register (address 0ff3 16 ) timer x mode register (address 23 16 ) set the corresponding interrupt enable bit to ? (disabled) . set the interrupt edge select bit (active edge switch bit) or the interrupt (source) select bit to ?? nop (one or more instructions) set the corresponding interrupt request bit to ? (no interrupt request issued). set the corresponding interrupt enable bit to ? (enabled). 2-22 38k0 group user? manual application 2.2 interrupt (2) check of interrupt request bit when executing the bbc or bbs instruction to an interrupt request bit of an interrupt request register immediately after this bit is set to ??by using a data transfer instruction, execute one or more instructions before executing the bbc or bbs instruction. clear the interrupt request bit to ??(no interrupt issued) nop (one or more instructions) execute the bbc or bbs instruction data transfer instruction: ldm, lda, sta, stx, and sty instructions fig. 2.2.16 sequence of check of interrupt request bit reason if the bbc or bbs instruction is executed immediately after an interrupt request bit of an interrupt request register is cleared to ?? the value of the interrupt request bit before being cleared to ? is read. 38k0 group user s manual application 2-23 2.3 timer 2.3 timer this paragraph explains the registers setting method and the notes related to the timers. 2.3.1 memory map fig. 2.3.1 memory map of registers related to timers 2.3.2 related registers fig. 2.3.2 structure of prescaler 12, prescaler x 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 prescaler 12 (pre12) timer 1 (t1) timer 2 (t2) timer x mode register (tm) prescaler x (prex) timer x (tx) 003c 16 003e 16 interrupt control register 1 (icon1) 003d 16 003f 16 interrupt request register 1 (ireq1) interrupt request register 2 (ireq2) interrupt control register 2 (icon2) prescaler 12, prescaler x b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 1 1 1 1 1 1 1 prescaler 12 (pre12) [address : 20 16 ] prescaler x (prex) [address : 24 16 ] set a count value of each prescaler. the value set in this register is written to both each prescaler and the corresponding prescaler latch at the same time. when this register is read out, the count value of the corres- ponding prescaler is read out. 2-24 38k0 group user s manual application 2.3 timer fig. 2.3.3 structure of timer 1 fig. 2.3.4 structure of timer 2, timer x timer 1 b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 0 0 0 0 0 0 0 timer 1 (t1) [address : 21 16 ] set a count value of timer 1. the value set in this register is written to both timer 1 and timer 1 latch at the same time. when this register is read out, the timer 1 s count value is read out. timer 2, timer x b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 1 2 3 4 5 6 7 name 1 1 1 1 1 1 1 1 timer 2 (t2) [address : 22 16 ] timer x (tx) [address : 25 16 ] set a count value of each timer. the value set in this register is written to both each timer and each timer latch at the same time. when this register is read out, each timer s count value is read out. 38k0 group user? manual application 2-25 2.3 timer fig. 2.3.5 structure of timer x mode register timer x operation modes timer mode pulse output mode event counter mode pulse width measurement mode cntr 0 active edge selection bit (bits 2 of address 23 16 ) contents ? cntr 0 interrupt request occurrence: falling edge ; no influence to timer count ? cntr 0 interrupt request occurrence: rising edge ; no influence to timer count ? pulse output start: beginning at ??level cntr 0 interrupt request occurrence: falling edge ? pulse output start: beginning at ??level cntr 0 interrupt request occurrence: rising edge ? timer x: rising edge count cntr 0 interrupt request occurrence: falling edge ? timer x: falling edge count cntr 0 interrupt request occurrence: rising edge ? timer x: ??level width measurement cntr 0 interrupt request occurrence: falling edge ? timer x: ??level width measurement cntr 0 interrupt request occurrence: rising edge table 2.3.1 cntr 0 active edge selection bit function b7 b6 b5 b4 b3 b2 b1 b0 b function at reset rw 0 2 3 4 5 6 7 name 0 0 0 timer x mode register (tm) [address : 23 16 ] timer x mode register 0 0 0 : timer mode 0 1 : pulse output mode 1 0 : event counter mode 1 1 : pulse width measurement mode b1 b0 1 0 timer x operating mode bits cntr 0 active edge selection bit the function depends on the operating mode of timer x. (refer to table 2.3.1) timer x count stop bit 0 : count start 1 : count stop nothing is arranged for these bits. these are write disabled bits. when these bits are read out, the contents are 0 . 0 0 0 2-26 38k0 group user s manual application 2.3 timer fig. 2.3.6 structure of interrupt request register 1 fig. 2.3.7 structure of interrupt request register 2 b7 b6 b5 b4 b3 b2 b1 b0 rw 0 0 2 0 3 0 4 0 5 0 6 0 7 0 1 0 usb bus reset interrupt request bit interrupt request register 1 (ireq1) [address : 3c 16 ] b function at reset name interrupt request register 1 usb sof interrupt request bit usb device interrupt request bit exb interrupt request bit int 0 interrupt request bit timer x interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ? 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? ? ? b7 b6 b5 b4 b3 b2 b1 b0 rw 0 0 2 0 3 0 4 0 5 0 6 0 7 0 1 0 int 1 interrupt request bit interrupt request register 2 (ireq2) [address : 3d 16 ] b function at reset name interrupt request register 2 serial i/o receive interrupt request bit serial i/o transmit interrupt request bit cntr 0 interrupt request bit key-on wake-up interrupt request bit a/d conversion interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued ? 0 can be set by software, but 1 cannot be set. 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued 0 : no interrupt request issued 1 : interrupt request issued ? ? ? ? ? ? nothing is arranged for this bits. this is a write disabled bit. when this bit is read out, the contents are 0 . nothing is arranged for this bits. this is a write disabled bit. when this bit is read out, the contents are 0 . 38k0 group user s manual application 2-27 2.3 timer fig. 2.3.8 structure of interrupt control register 1 fig. 2.3.9 structure of interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 rw 0 0 2 0 3 0 4 0 5 0 6 0 7 0 1 0 usb bus reset interrupt enable bit interrupt control register 1 (icon1) [address : 3e 16 ] b function at reset name interrupt control register 1 usb sof interrupt enable bit usb device interrupt enable bit exb interrupt enable bit int 0 interrupt enable bit timer x interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled b7 b6 b5 b4 b3 b2 b1 b0 rw 0 0 2 0 3 0 4 0 5 0 6 0 7 0 1 0 int 1 interrupt enable bit interrupt control register 2 (icon2) [address : 3d 16 ] b function at reset name interrupt control register 2 serial i/o receive interrupt enable bit serial i/o transmit interrupt enable bit cntr 0 interrupt enable bit key-on wake-up interrupt enable bit a/d conversion interrupt enable bit fix this bit to 0 . 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled 0 : interrupt disabled 1 : interrupt enabled fix this bit to 0 . 0 : interrupt disabled 1 : interrupt enabled 0 0 2-28 38k0 group user s manual application 2.3 timer 2.3.3 timer application examples (1) basic functions and uses [function 1] control of event interval (timer x, timer 1, timer 2) when a certain time, by setting a count value to each timer, has passed, the timer interrupt request occurs. |
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