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CS22220 wireless pcmcia controller 1 of 34 ds557pp2 rev. 3.0 www.cirrus.com 1 description the cirrus logic CS22220 wireless network controller enables high performance, 11 megabits per second digital wireless data connectivity for pcmcia, mobile, embedded systems and other cost sensitive applications . the CS22220 is a highly integrated single-chip pcmcia solution for wireless networks supporting video, audio, voice, and data traffic. the programmable controller executes cirrus logic?s whitecap?2 networking protocol that provides wi-fi? (802.11b) compliance as well as multimedia and quality of service (qos) support. the device includes several high performance components including an arm7tdmi risc processor core, a forward error correction (fec) codec and a wireless radio mac supporting up to11 mbps throughput. the CS22220 utilizes state of the art 0.18um cmos process and is housed in a 208 fpbga compact (15mm x 15mm) package, which has low-lead inductance suitable for highly integrated radio applications. the core is powered at 1.8 v with 3.3v (5.0v tolerant) i/o to reduce overall power consumption. in addition, the CS22220 supports low power management for the host and radio interfaces. the CS22220 is designed to be an integral part of a pc card (pcmcia 2.1/jeida 4.2). the pcmcia host interface also supports both little endian and big endian protocol for easy interfacing to popular microprocessors in embedded system applications. figure 1. example system block diagram 11 mbps wireless baseband i/f CS22220 wireless pcmcia controller 802.11b compatible 2.4 ghz digital radio phy transceiver 2.4 ghz direct sequence s p read s p ectru m system memory sdram (up to 4mb) sram (up to 256kb) pcmcia host or embedded cpu networking data boot rom/flash (upto1mb) CS22220 data sheet wireless pcmcia controller
CS22220 wireless pcmcia controller 2 of 34 ds557pp2 rev. 3.0 www.cirrus.com 2 features embedded arm core and system support logic ? high performance arm7tdmi risc processor core up to 77mhz ? 4kb integrated, one-way set associative, unified, write through cache ? individual interrupt for each functional block ? two 23-bit programmable (periodic or one-shot) general purpose timers ? 8 dword (32-bits) memory write and read buffers for high system performance ? abort cycle detection and reporting for debugging ? arm performance monitoring function for system fine-tuning ? programmable performance improvement logic based on system configuration enhanced memory controller unit ? programmable memory controller unit supporting sdram /async sram/boot rom/flash interface ? 16-bit data bus with 12-bit address supporting up to 4mb up to 103 mhz (100/133mhz sdram) ? 8-bit data bus with addressing support up to 1mb of boot rom/flash. ? programmable sdram timing and size parameters such as cas latencies and number of banks, columns, and rows ? flexible independent dma engines for pcmcia and digital radio functional units fec codec ? high performance reed-solomon coding for error correction (255:239 block coding) ? reduces error probability of a typical 10e-3 error rate environment to 10e-9 ? programmable rate fec engine to optimize channel efficiency ? low latency, fully pipelined hardware encoding and decoding. supports byte-wise single cycle throughput up to 77mhz, with a sustain rate of 77mbps. ? double buffering (63 dword read/write buffer) to enhance system performance digital radio mac interface ? glue-less interface to 802.11b baseband transceivers ? up to 11mbps data rates ? 32 dword transmit/receive fifo ? supports clear channel assessment (cca) power management ? host (pcmcia) acpi compliant ? programmable sleep timer for arm core and system low power management ? independent power management control for individual functional units ? supports variable rate radio transmit, receive, and standby radio power modes clock and pll interface ? single 44mhz crystal oscillator reference clock ? internal pll to generate internal and on board clocks pcmcia interface ? 16 bit pcmcia i/o target device supporting memory map or program i/o using 11 address bits ? independent dma controller to transfer data between pcmcia and main memory ? fully compliant with pcmcia 2.1/jeida 4.2 standard ? supports big endian and little endian (default) data formats ? supports custom mode for embedded applications where the interface becomes a generic memory address/data interface chip processing and packaging ? 208 fpbga package and 0.18um state of the art cmos process ? 1.8 v core for low power consumption. 3.3v i/o - 5v tolerant i/o
CS22220 wireless pcmcia controller 3 of 34 ds557pp2 rev. 3.0 www.cirrus.com important notice "preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "advance" product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other parts of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or technologies described in this material and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. an export license and/or quota needs to be obtained from the competent authorities of the chinese government if any of the products or technologies described in this material is subject to the prc foreign trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ("critical applications"). cirrus products are not designed, authorized, or warranted to be suitable for use in life- support devices or systems or other critical applications. inclusion of cirrus products in such applications is understood to be fully at the customer's risk. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. use of this product in any manner that complies with the mpeg-2 video standard as defined in iso documents is 13818-1 (including annexes c, d, f, j, and k), is 13818-2 (including annexes a, b, c, and d, but excluding scalable extensions), and is 13818-4 (only as it is needed to clarify is 13818-2) is expressly prohibited without a license under applicable patents in the mpeg-2 patent portfolio, which license is available from mpeg la, l.l.c. 250 steele street, suite 300, denver, colorado 80296.
CS22220 wireless pcmcia controller 4 of 34 ds557pp2 rev. 3.0 www.cirrus.com 3 functional description figure 2. block diagram of major functional units digital radio interface memory/boot rom controller arbiter arm 7tdmi radio mac w/ dma ctrl fec codec jtag/test interface system memory pcmcia clock/pll pcmcia controller w/dma ctrl crystal or oscillator 4kb cache timer (2) interrupt controller sleep timer system control bus dma dma read/write buffer
CS22220 wireless pcmcia controller 5 of 34 ds557pp2 rev. 3.0 www.cirrus.com 3.1 embedded arm core and system support logic the processing elements of the CS22220 include the arm7tdmi core and its associated system control logic. the arm processor and system controller consists of a memory management unit, 4-kb write through cache controller, 20 irq and 4 firq interrupt controller, and 2 general purpose timers. the arm processor and integrated system support logic provide the necessary execution engine to support a real time multi-tasking operating system, the network protocol stack, and firmware services. memory management unit arm instructions and data are fetched from system memory a cache-line (4/8 ? dwords /programmable) at a time when caching is turned on. during a cache line fill, critical word data, i.e., the access that caused the miss, is forwarded to the arm and also written into the data ram cache. the non-critical words in the line fetched following the critical word are then written to the cache on a dword basis, as they become available. memory writes are posted to dual 4-dwords (32-bit) memory write posting buffers. write posts use the sequential addressing feature on the memory bus. with dual buffering an out of sequence write will post to one write buffer while the other buffer is flushed to memory. there is one 8dword read buffer in the mem block. the buffer is used for both cacheable and non-cacheable memory space. interrupt controller the interrupt controller provides two interrupt channels to the arm processor. one interrupt channel is presented to the arm on its nfiq , and the other channel is presented on its nirq pin. these are referred to as the fiq channel and the irq channel. both channels operate in identical but independent fashion. the fiq channel has a higher priority on the arm processor than the irq channel. the interrupt controller includes a control register for each logical interrupt in the arm complex. the control register serves the following main purposes: ? provides the mapping between the ext_int inputs (physical interrupts) and the logical interrupt ? selects the particular type of signaling expected on the ext_int inputs: level, edge, active level high/low etc. ? enable or disable a logical interrupt
CS22220 wireless pcmcia controller 6 of 34 ds557pp2 rev. 3.0 www.cirrus.com 3.2 digital radio interface the CS22220 digital radio mac i/f supports multiple radio baseband and rf interfaces. the baseband registers can be programmed during the configuration time using the control port interface. the mac also provides the capability of programming the signal, service and length on per packet basis without arm intervention. this significantly improves the performance of the system. there are three primary digital interface ports for the CS22220 that are used for configuration and during normal operation. these ports are: ? the control port, which is used to configure, set power consumption modes, write and/or read the status of the radio base band registers. ? the tx port, which is used to output the data that needs to be transmitted from the network processor. ? the rx port, which is used to input the received demodulated data to the network processor 3.3 fec codec the fec codec performs reed-solomon coding to protect the data before it is transmitted to a noisy channel. it is a similar code as employed by the digital broadcast industry, such as itu-t j.83 for dvb. the rs(255, 8) code implemented by the CS22220 can reduce error probability to 1/10e-9 in a typical 1/10e-3 error rate environment. the encoder/decoder can be programmed to vary the coding block length ( n ) and correctable error ( t ) to optimize the tradeoff between channel utilization and data protection. the range of n iscurrentlysettobefrom20to255,andthe t is 8. the symbol size is fixed at 8 bits. coding parameters can be set real time, allowing maximum flexibility for the system to adjust the fec setting, such as block size, in order to optimize channel efficiency. the encoder also has a very low latency of two cycles. both the encoder and decoder are fully pipelined in structure to achieve single cycle throughput. the fec can be disabled in firmware.
CS22220 wireless pcmcia controller 7 of 34 ds557pp2 rev. 3.0 www.cirrus.com 3.4 programmable memory controller the CS22220 incorporates a general-purpose memory controller. the memory controller supports both sdram/async sram memory interface and a flash memory interface. in the ram configuration, the system memory interface supports up to 4-mbyte of 16-bit sdram running at frequency up to 103 mhz (using 133mhz sdram) single-state access cycles or 256kb of 16 bit async sram. the memory controller provides programming of sdram parameters such as cas latency, refresh rate and etc; these registers are located in miscellaneous configuration registers. the CS22220 memory controller supports the power saving feature of the sdram by toggling the clock enable (cke) signal. when there are no pending memory requests from any internal requester, the CS22220 will keep cke low to cause the sdram to stay in power down mode. once a memory request is active, the CS22220 will assert cke high to cause the sdram to come out of power down mode. typically, this can reduce memory power consumption by up to 50%. in rom configuration, firmware for CS22220 is stored in non-volatile memory and is accessed through the boot rom interface. the maximum addressable rom space supported is 1mb. rom read/write and output enable are shared with ram control pins. 3.5 pcmcia interface the pc-card interface implemented in cirrus logic CS22220 is fully compliant with pcmcia 2.1/jeida 4.2. the interface supports 16 data bits pcmcia program i/o and memory mapped accesses using 11 address bits. pcmcia interface allows laptop users to connect to home network to access data and multimedia streams with ease. the interface provides both memory and i/o access. the pcmcia interface incorporates an independent dma controller to transfer data to/from the main memory. the arm has the flexibility in controlling how often it is interrupted and simplifies the packet transmit/receive protocol. the dma controller is programmed during power up. the CS22220 pccard interface incorporates a custom mode, which can be used for embedded applications, by bypassing the standard pc card pnp configuration requirements. this interface thus becomes a generic asynchronous 16 bit data interface. this mode is useful when interfacing the CS22220 wireless network controller directly to an embedded micro-controller capable of supporting a 16 bit data bus.
CS22220 wireless pcmcia controller 8 of 34 ds557pp2 rev. 3.0 www.cirrus.com 4 pinout and signal descriptions figure 3. CS22220 logical pin groupings digital radio interface nperr, nserr txclk txpe txd txrdy cca bbrnw nresetb txpebb nbbcs bbas txpape bbsclk bbsdx synthle rxpebb nrpd rxd mdrdy rxclk CS22220 controller smclk sma[11:0] nsmcs[1:0] nsmras nsmcas smd[15:0] nsmwe smdqm[1:0] system memory interface smcke jtag interface xtalclki n xtalou t tdo td i tc k tms ntrst nbrce clock interface xtracl k pllagnd pllavcc plldgnd plldvcc pllplus pll power interface npcinpack pcd[15:0] niois16 npcwait npcstschg npcirq npcreg npciord pciowr ext_reset pca[10:0] npce1 npce2 npcoe npcwe pcmcia interface ntes t
CS22220 wireless pcmcia controller 9 of 34 ds557pp2 rev. 3.0 www.cirrus.com this section provides detailed information on the CS22220 signals. the signal descriptions are useful for hardware designers who are interfacing the CS22220 with other devices. system memory interface the system memory interface supports standard sdram interface, async sram and flash. there are a total of 38 signals in this interface. smclk output system mem clock for sdram. currently the interface supports 100 mhz for a maximum bandwidth of 200mbytes/sec. nsmcs0 output chip select bit 0. this signal is used to select or deselect the sdram for command entry. when smncs is low it qualifies the sampling of nsmras, nsmcas and nsmwe. also, used as testmode(2) when ntest pin is '0'. nsmcs1 output chip select bit 1. nbrce output chip select for rom access. this signal is used to select or deselect the boot rom memory. nsmras output row address select. used in combination with nsmcas, nsmwe and nsmcs to specify which sdram page to open for access. also used during reset to latch in the strap value for clk_bypass; if set to a '1' implies bypassing clock module; whatever clk is applied on the input clock is used for memclk and ctlclk. also shared as the romoe signal. nsmcas output column address select. used in combination with nsmras, nsmwe and nsmcs to specify which piece of data to access in selected page. also used during reset to latch in the strap value for same_freq; if set to a '1' implies internal mem_clk and arm_clk are running at the same frequency and 180 degrees out of phase. nsmwe output write enable. used in combination with nsmras, nsmcas, and nsmwe to specify whether the current cycle is a read or a write cycle. also used during reset to latch in the strap value for tst_bypass; if set to a '1' implies pll bypass. also shared as the romwe to do flash programming.
CS22220 wireless pcmcia controller 10 of 34 ds557pp2 rev. 3.0 www.cirrus.com smdqm[1:0] output data mask bit 1:0. these signals function as byte enable lines masking unwanted bytes on memory writes. also, used as testmode(1:0) when ntest pin is '0'. smcke output clock enable. smcke is used to enable and disable clocking of internal ram logic. sma0 output address bit0. the address bus specifies either the row address or column address. also, this is shared as boot-rom address bit0. also used during reset to latch in the strap value for pccsel, if set to a '1' implies pccard mode sma1 output address bit1. also, this is shared as boot-rom address bit1. this pin should be pull-down. sma2 output address bit2. also, this is shared as boot-rom address bit2. this pin should be pull-down. sma3 output address bit3. also shared as boot-rom address bit3. this pin should be pull-down. sma4 output address bit4. also shared as boot-rom address bit4. also used during reset to latch in the strap value for romcfg; if set to a '1' implies pccard configuration data should be downloaded from rom. sma5 output address bit5. also shared as boot-rom address bit5. also used during reset to latch in the strap value for test_rst_enb; if set to a '0' implies normal operation mode. sma6 output address bit6. also shared as boot-rom address bit6. also used during reset to latch in the strap value for freq_sel(0). freq_sel(2:0) is used to select the multiplication factor for the internal pll (000=1x, and 111=8x).
CS22220 wireless pcmcia controller 11 of 34 ds557pp2 rev. 3.0 www.cirrus.com sma7 output address bit7. also shared as boot-rom address bit7. also used during reset to latch in the strap value for freq_sel(1). freq_sel(2:0) is used to select the multiplication factor for the internal pll (000=1x, and 111=8x). sma8 output address bit8. also shared as boot-rom address bit8. also used during reset to latch in the strap value for freq_sel(2). freq_sel(2:0) is used to select the multiplication factor for the internal pll (000=1x, and 111=8x). sma9 output address bit9. also shared as boot-rom address bit9. also used during reset to latch in the strap value for sdram_delay(0). sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns, and 111=1.75ns with each .25ns increments). sma10 output address bit10. also shared as boot-rom address bit10. also used during reset to latch in the strap value for sdram_delay(1). sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns, and 111=1.75ns with each .25ns increments). sma11 output address bit11. also shared as boot-rom address bit11. also used during reset to latch in the strap value for sdram_delay(2). sdram_delay(2:0) is used to select the delay factor for the internal memory clock (000=0ns, and 111=1.75ns with each .25ns increments). smd[7:0] bi-directional data bus. the data bus contains the data to be written to memory on a writecycleandthereadreturndataonareadcycle. smd[15:8] bi-directional shared data bus. the data bus contains the data to be written to ram memory on a write cycle and the read return data on a read cycle. data bit [15:8] is also shared as boot rom address bit [19:12]. digital radio interface all radio input buffers are schmitt triggered input buffers. there are total of 26 signals in this interface. txclk input transmit clock is a clock input from the radio baseband processor. this signal is used to clock out the transmit data on the rising edge of txclk.
CS22220 wireless pcmcia controller 12 of 34 ds557pp2 rev. 3.0 www.cirrus.com txpebb output baseband transmit power enable, an output from the mac to the radio baseband processor. when active, the baseband processor transmitter is configured to be operational, otherwise the transmitter is in standby mode. txd output it is the serial data output from the mac to the radio baseband processor. the data is transmitted serially with the lsb first. the data is driven by the mac on the rising edge of txclk and is sampled by the radio baseband processor on the falling or rising edge of txclk depending on baseband requirements. txrdy input transmit data ready is an input to the mac from the radio baseband processor to indicate that the radio baseband processor is ready to receive the data packet over the txd signal. the signal is sampled by the mac on the rising edge of txclk. cca input clear channel assessment is an input from the radio baseband processor to signal that the channel is clear to transmit. when this signal is a 0, the channel is clear to transmit. when this signal is a 1, the channel is not clear to transmit. this helps the mac to determine when to switch from receive to transmit mode. bbrnw output baseband read/write is an output from the mac to indicate the direction of the sd bus when used for reading or writing data. this signal has to be setup to the rising edge of bbsclk for the baseband processor and is driven on the rising edge of the armclk corresponding the falling edge of bbsclk. nresetbb output baseband reset is an output of the mac to reset the baseband processor. bbas output baseband address strobe is used to envelop the address or the data on the bbsdx bus. a logic 1 envelops the address and a logic 0 envelops the data. this signal has to be setup to the rising edge of bbsclk for the baseband processor and is driven on the falling edge of bbsclk. nbbcs output baseband chip select is an active low output to activate the serial control port. when inactive the sd, bbsclk, bbas and bbrnw signals are ?don?t cares?.
CS22220 wireless pcmcia controller 13 of 34 ds557pp2 rev. 3.0 www.cirrus.com txpape output radio power amplifier power enable is a software-controlled output. this signal is used to gate power to the power amplifier. txpe output radio transmit power enable indicates if transmit mode is enabled. when low, this signal indicates transmitter is in standby mode. rxpebb output baseband receive power enable is an output that indicates if the mac is in receive mode. output to baseband processor enables receive mode in baseband processor. bbsclk output baseband serial clock is a programmable output generated by dividing arm_clk by 14 (default). this clock is used for the serial control port to sample the control and data signals. bbsdx bi-directional baseband serial data is a bi-directional serial data bus, which is used to transfer address and data to/from the internal registers of the baseband processor. synthle output synthesizerlatchenableisanactivehighsignalusedtosenddatatothe synthesizer. nrpd output radio power down enable. this active low signal is used to power management purpose for the radio circuitry. rxclk input this is an input from the baseband processor. it is used to clock in received data from baseband processor. mdrdy input receive data ready is an input signal from the baseband processor, indicating a data packet is ready to be transferred to the mac. the signal returns to an inactive state when there is no more receiver data or when the link has been interrupted. this signal is sampled on the falling or rising edge of rxclk depending on baseband requirements. rxd input receive data is an input from the baseband processor transferring demodulated header information and data in a serial format. the data is frame aligned with md_rdy. this signal is sampled on the falling or rising edge of rxclk depending on baseband requirements.
CS22220 wireless pcmcia controller 14 of 34 ds557pp2 rev. 3.0 www.cirrus.com dacavcc input analog power for dac. this is 3.3v. dacagnd input analog ground for dac. pll and clock interface there are three clock pins and five pll power pins. there are a total of 8 signals in this interface. xtal_clkin input 44 mhz reference clock input/crystal clock input. xtalout input reference crystal clock output. xtraclk input second clock input to the clock module. this input clock is used depending on the clock configuration, which is determined by three strapping pin values. pllagnd input analog pll ground. pllavcc input analog pll power. this is 3.3v. plldgnd input digital pll ground. plldvcc input digital pll power. this is 1.8v. pllplus input analog pll ground.
CS22220 wireless pcmcia controller 15 of 34 ds557pp2 rev. 3.0 www.cirrus.com pc card interface the pc card interface is pcmcia 2.1 fully compliant interface. the following provides detail pin description. pcd[15:0] bi-directional data lines. the data bus contains the data to be written on a write cycle and the read return data on a read cycle. pca[10:0] input address lines. signal pca[10:0] are address bus input lines. pca10 is the most significant bit. during memory word access mode, a0 is not used. during i/o word access cycle, a0 must be negated. npce[2:1] input card enable. these lines are active low input signals. npce1 enables even numbered addresses and npce2 enables odd numbered addresses. npoe input output enable. this signal is used to gate memory read data from memory card. npcwe input write enable. this is active low input signal is used for strobing memory write data into the memory card. npcreg input attribute memory select. assertion of this signal indicates the access is limited to attribute memory and to i/o space. attribute memory is a separate accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. npcireq output interrupt request. this signal is asserted to indicate to the host system that a pc card device requires host software service. npcstschg output pc card status changed ? not supported. this pin is used as a mode strap pin. when asserted during reset, pc card i/f uses the big endian protocol; otherwise pulled low (default), it uses the little endian protocol.
CS22220 wireless pcmcia controller 16 of 34 ds557pp2 rev. 3.0 www.cirrus.com npcwait output the wait signal is asserted by a pc card to delay completion of the memory access or i/o access. niois16 output the niois16 output signal is asserted when the address at the socket corresponds to an i/o address to which the card responds, and the i/o port addressed is capable of 16-bit access. npcinpack output input port acknowledge. this output signal is asserted when the pc card is selected and can respond to an i/o read cycle at the address on the address bus. npciord input the host asserts niord to read data from a pc card?s i/o space. npciowr input the host asserts npciowr to write data to a pc card?s i/o space. system and pc card reset ext_reset input the reset signal clears the configuration option register and places the card in an unconfigured state.the system must place the reset signal in a high-z state during card power up. the signal must remain high impedance for at least 1 msec after vcc becomes valid. jtag interface tdo output test data output. this input has an integral pull up. tdi input test data input. tck input test clock signal. tms input test mode select. this input has an internal pull up. ntrst input test interface reset. this input has an internal pull up.
CS22220 wireless pcmcia controller 17 of 34 ds557pp2 rev. 3.0 www.cirrus.com miscellaneous interface ntest input chip test mode pin. used in conjunction with smncs0, smdqm[0:1]. pull up for normal operation spio_0:8,12:15 bi-directional special purpose i/o reserved for supporting custom interfaces. * check with cirrus logic support for supported options and usage. power and ground vcc (5v and 3.3v) 1 input 5v inputs. there are a total of 3 pins. vdd (3.3v) input 3.3v inputs. there are a total of 22 pins. vee (1.8v) input 1.8v inputs to the core. there are a total of 9 pins. vss input ground. there are total of 28 pins. 1 5v or 3.3v depending on desired pcmcia configuration
CS22220 wireless pcmcia controller 18 of 34 ds557pp2 rev. 3.0 www.cirrus.com figure 4. CS22220 208 pin fpbga pinout diagram
CS22220 wireless pcmcia controller 19 of 34 ds557pp2 rev. 3.0 www.cirrus.com table 1. pin listing by name ball name ball name ball name ball name a07 (n/c) k03 pca08 t16 sma00 e16 txpape a13 (n/c) l04 pca09 u17 sma01 b17 txpe b08 (n/c) l01 pca10 p14 sma02 e15 txpebb c03 (n/c) e04 pcd00 t17 sma03 d16 txrdy c07 (n/c) d03 pcd01 r17 sma04 a01 vcc c08 (n/c) c01 pcd02 p15 sma05 j01 vcc c12 (n/c) r03 pcd03 n14 sma06 t02 vcc r05 (n/c) r01 pcd04 p17 sma07 b03 vdd t06 (n/c) p02 pcd05 n15 sma08 a12 vdd h17 bbas n01 pcd06 m14 sma09 b04 vdd k17 bbncs n02 pcd07 m16 sma10 b11 vdd h15 bbrnw d02 pcd08 m15 sma11 b14 vdd j16 bbsclk d04 pcd09 u07 smcke c06 vdd h14 bbsdx b02 pcd10 u11 smclk c15 vdd t04 cal_en r02 pcd11 t08 smd00 d09 vdd c16 cca p03 pcd12 r10 smd01 e17 vdd d11 dacavdd p01 pcd13 p11 smd02 f04 vdd c13 dacavss n03 pcd14 t11 smd03 g16 vdd d12 rsvd n04 pcd15 r11 smd04 j15 vdd b12 rsvd a16 pllagnd p12 smd05 k01 vdd h01 ext_reset d14 pllavcc r12 smd06 n17 vdd g15 mdrdy b15 plldgnd p13 smd07 p16 vdd l15 nbrce a17 plldvcc u12 smd08 r04 vdd m03 npce1 a15 pllplus r13 smd09 r08 vdd m02 npce2 f15 rlink u13 smd10 t01 vdd g02 npcinpack b16 rnpd u14 smd11 t10 vdd c02 npciois16 u01 rsvd r14 smd12 t12 vdd l03 npciord t03 rsvd u15 smd13 t14 vdd l02 npciowr e14 rsvd u16 smd14 u09 vdd h03 npcireq p06 rsvd r15 smd15 a09 vee m04 npcoe u05 rsvd u06 smdqm00 c09 vee f03npcreg p05rsvd t07smdqm01 d07vee d01 npcstschg u04 rsvd p08 smncas j03 vee g03 npcwait t05 rsvd r06 smncs00 j04 vee k02 npcwe a02 rsvd p07 smncs01 j14 vee g14 nresetbb a03 rsvd l16 smnras k16 vee k14 ntest a04 rsvd l14 smnwe r09 vee c11 ntrst a05 rsvd u03 synth_le1 t09 vee e02 pca00 a06 rsvd p04 synth_le2 a08 vss e03 pca01 b05 rsvd j17 synthle a11 vss e01 pca02 b06 rsvd a10 tck a14 vss f02 pca03 c04 rsvd b10 tdi b01 vss g04 pca04 d06 rsvd c10 tdo b07 vss f01 pca05 g17 rxclk d10 tms b09 vss g01 pca06 f14 rxd d17 txclk c05 vss h02 pca07 f17 rxpebb d15 txd c17 vss
CS22220 wireless pcmcia controller 20 of 34 ds557pp2 rev. 3.0 www.cirrus.com ball name ball name ball name ball name d08 vss l17 vss r16 vss c14 xtalclkin f16 vss m01 vss t13 vss d13 xtalout h04 vss m17 vss t15 vss b13 xtraclk h16 vss n16 vss u02 vss j02 vss p09 vss u08 vss k04 vss p10 vss u10 vss k15 vss r07 vss d05 wc_wifi
CS22220 wireless pcmcia controller 21 of 34 ds557pp2 rev. 3.0 www.cirrus.com table 2. pin listing by ball ball name ball name ball name ball name a01 vcc c12 (n/c) g16 vdd n04 pcd15 a02 rsvd c13 dacavss g17 rxclk n14 sma06 a03 rsvd c14 xtalclkin h01 ext_reset n15 sma08 a04 rsvd c15 vdd h02 pca07 n16 vss a05 rsvd c16 cca h03 npcireq n17 vdd a06 rsvd c17 vss h04 vss p01 pcd13 a07 (n/c) d01 npcstschg h14 bbsdx p02 pcd05 a08 vss d02 pcd08 h15 bbrnw p03 pcd12 a09 vee d03 pcd01 h16 vss p04 synth_le2 a10 tck d04 pcd09 h17 bbas p05 rsvd a11 vss d05 wc_wifi j01 vcc p06 rsvd a12 vdd d06 rsvd j02 vss p07 smncs01 a13 (n/c) d07 vee j03 vee p08 smncas a14 vss d08 vss j04 vee p09 vss a15 pllplus d09 vdd j14 vee p10 vss a16 pllagnd d10 tms j15 vdd p11 smd02 a17 plldvcc d11 dacavdd j16 bbsclk p12 smd05 b01 vss d12 rsvd j17 synthle p13 smd07 b02 pcd10 d13 xtalout k01 vdd p14 sma02 b03 vdd d14 pllavcc k02 npcwe p15 sma05 b04 vdd d15 txd k03 pca08 p16 vdd b05 rsvd d16 txrdy k04 vss p17 sma07 b06 rsvd d17 txclk k14 ntest r01 pcd04 b07 vss e01 pca02 k15 vss r02 pcd11 b08 (n/c) e02 pca00 k16 vee r03 pcd03 b09 vss e03 pca01 k17 bbncs r04 vdd b10 tdi e04 pcd00 l01 pca10 r05 (n/c) b11 vdd e14 rsvd l02 npciowr r06 smncs00 b12 rsvd e15 txpebb l03 npciord r07 vss b13 xtraclk e16 txpape l04 pca09 r08 vdd b14 vdd e17 vdd l14 smnwe r09 vee b15 plldgnd f01 pca05 l15 nbrce r10 smd01 b16 rnpd f02 pca03 l16 smnras r11 smd04 b17 txpe f03 npcreg l17 vss r12 smd06 c01 pcd02 f04 vdd m01 vss r13 smd09 c02 npciois16 f14 rxd m02 npce2 r14 smd12 c03 (n/c) f15 rlink m03 npce1 r15 smd15 c04 rsvd f16 vss m04 npcoe r16 vss c05 vss f17 rxpebb m14 sma09 r17 sma04 c06 vdd g01 pca06 m15 sma11 t01 vdd c07 (n/c) g02 npcinpack m16 sma10 t02 vcc c08 (n/c) g03 npcwait m17 vss t03 rsvd c09 vee g04 pca04 n01 pcd06 t04 cal_en c10 tdo g14 nresetbb n02 pcd07 t05 rsvd c11 ntrst g15 mdrdy n03 pcd14 t06 n/c
CS22220 wireless pcmcia controller 22 of 34 ds557pp2 rev. 3.0 www.cirrus.com ball name ball name ball name ball name t07 smdqm01 t14 vdd u04 rsvd u11 smclk t08 smd00 t15 vss u05 rsvd u12 smd08 t09 vee t16 sma00 u06 smdqm00 u13 smd10 t10 vdd t17 sma03 u07 smcke u14 smd11 t11 smd03 u01 rsvd u08 vss u15 smd13 t12 vdd u02 vss u09 vdd u16 smd14 t13 vss u03 synth_le1 u10 vss u17 sma01
CS22220 wireless pcmcia controller 23 of 34 ds557pp2 rev. 3.0 www.cirrus.com 5 specifications table 3. absolute maximum ratings symbol parameter limits units v ee voltage at core -0.18 to 2.0 v v dd dc supply ( i/o) -0.3 to 3.9 v v in input voltage -0.1 to v dd +0.3 v i in dc input current +/- 10 a t stgp storage temperature range -40 to 125 c table 4. recommended operating conditions symbol parameter limits units v dd v ee dc supply 3.15 to 3.60 (3v i/o) 1.6 to 2.0 (core) v xtalin input frequency 1 44 mhz f tck jtag clock frequency 0 to 10 mhz t a ambient temperature 0 to +70 c t j junction temperature 0 to +105 c notes: 1. the xtalin & xtalout pins have minimal esd protection. 2. this device may have esd sensitivity above 500v hbm per jesd22-a114. normal esd precautions need to be followed. table 5. capacitance symbol parameter value units c in input capacitance 3.4 pf c out output capacitance 4.0 pf table 6. dc characteristics symbol parameter condition min typ. max units v il voltage input low -0.50 0.3 * v dd v v ih voltage input high 0.7 * v dd v dd +0.3 v v ol voltage output low i ol = 800 a v ss +0.1 v v oh voltage output high i oh = 800 a v ss -0.1 v i il input leakage current v in =v ss or v dd -10 10 a i oz 3-state output leakage current v oh =v ss or v dd -10 10 a i dd i ee dynamic supply current note 1 v dd =3.3v v dd =1.8v 35 135 ma
CS22220 wireless pcmcia controller 24 of 34 ds557pp2 rev. 3.0 www.cirrus.com 5.1 ac characteristics and timing table 7. system memory interface timings parameter parameter description min max units t d smd smclk to smd[31:0] output delay 7 ns t d sma smclk to sma[11:0] output delay 4.7 ns t d smdqm smclk to smdqm[3:0] output delay 5.1 ns t d smncs smclk to smncs[1:0] output delay 4.1 ns t d smnwe smclk to smnwe output delay 4.5 ns t d smcke smclk to smcke output delay 4.3 ns t d smncas smclk to smncas output delay 4.0 ns t d smnras smclk to smnras output delay 5.0 ns t per smclk smclk period 72 103 ns t su smd smd[31:0] setup to smclk 1.0 ns t h smd smd[31:0] hold from smclk 2.4 ns notes: 1. outputs are loaded with 35pf on smd, 25pf on sma, smdqm, smnras, and smncas and 20pf on smclk, smncs, and smcke. 2. an attempt has been made to balance the setup time needed by the sdram and the setup needed by cs22210 to read data. if there is a problem meeting setup on the sdram, there is a programmable delay line on smclk which can help meet the setup time. care must be taken, however, not to violate the setup on the return read data. the delay can be increased by a multiple of 0.25ns by using the sma[11:09] pins to selectively set the clock delay . smclk smd[15:0] sma[13:0] smdqm[1:0] smncs[1:0] smnwe smcke smnras smncas write data write data row addr column addr row addr t d smcke t d smnras t d smncas t d smnwe t d sma t d smd t d smdqm t d smncs figure 5. system memory interface ?write? timing diagram
CS22220 wireless pcmcia controller 25 of 34 ds557pp2 rev. 3.0 www.cirrus.com smclk smd[15:0] sma[13:0] smdqm[1:0] smncs[1:0] smnwe smcke smnras smncas data data row addr column addr row addr active active t per smclk t d smcke t d smnras t d smncas t d sma t d smncs t su smd t h smd figure 6. system memory interface 'read' timing diagram
CS22220 wireless pcmcia controller 26 of 34 ds557pp2 rev. 3.0 www.cirrus.com table 8. rom/flash memory ?read? timing item symbol min max clock period (1) t per smclk 72 mhz 103 mhz ce to smd latched data (2) t id smd 221 ns oe de-asserted to oe asserted (3) t f smras 6(t per smclk ) rom address to output delay (4) t acc 220 ns smclk to sma output delay t d sma 4.0 ns smclk to brce output delay (ce) t d brce 4.5 ns smclk to smras output delay (oe) t d smras 5.0 ns smd setup to smclk t su smd 1.0 ns smd hold from smclk t h smd 2.4 ns 1. the memclock timing is derived by bootstrap pll settings. synchronous modes at 77 mhz & 72 mhz are currently supported. 2. t id smd is based on the fm_romrdlat register settings ? default is 09h max. (77mhz ~ 17 times smclk = 221ns). 3. t f smras is the minimum time required before the next oe is active on the bus (6 times smclk). the rom device must release the bus within this time frame (77mhz ~ 78 ns). 4. based on default fm_romrdlat register settings (note: 09h translates to 11h) see fm_romrdlat register settings for more information) smclk smd[7:0] sma[11:0], smd[13:8] smnwe brce (ce) smras (oe) data address t per smclk t d t d smras t d t ld smd t d brce t d smras brce t acc sma t su smd t h smd t f smras figure 7. rom memory interface 'read' timing diagram
CS22220 wireless pcmcia controller 27 of 34 ds557pp2 rev. 3.0 www.cirrus.com 5.2 pcmcia interface timing diagrams figure 8. attribute/common memory ?read? timing diagram table 9. common memory ?read? timing specification 100 ns speed version item symbol min max read cycle time t c r 100 address accesss time t a (a) 100 card enable access time t a (ce) 100 output enable access time t a (oe) 50 output disable time from pc_noe t dis (oe) 50 output disable time from pc_nce t en (ce) 5 data valid from address change t v (a) 0 address setup time t su (a) 10 address hold time t h (a) 15 card enable setup time t su (ce) 0 card enable hold time t h (ce) 15 pc_nwait valid from pc_noe t v (wt-oe) 35 pc_nwait pulse width t w (wt) 12 us data setup for pc_nwait released t v (wt) 0 pc_a[25:0], pc_nreg pc_nce pc_noe pc_nwait pc_d[15:0] t c (r) t a (ce) t a (a) t h (a) t v (a) t h (ce) t dis (ce) t dis (oe) t su (ce) t su (a) t a (oe) t v (wt-oe) t en (oe) t v (wt) t w (wt)
CS22220 wireless pcmcia controller 28 of 34 ds557pp2 rev. 3.0 www.cirrus.com table 10. attribute memory ?read? timing specification 600 ns speed version item symbol min max read cycle time t c r 600 address accesss time t a (a) 600 card enable access time t a (ce) 600 output enable access time t a (oe) 300 output disable time from pc_noe t dis (oe) 150 output enable time from pc_nce t en (oe) 5 data valid from address change t v (a) 0 address setup time t su (a) 100 address hold time t h (a) 35 card enable setup time t su (ce) 0 card enable hold time t h (ce) 35 pc_nwait valid from pc_noe t v (wt-oe) 100 pc_nwait pulse width t w (wt) 12 us data setup for pc_nwait released t v (wt) 0 figure 9. memory ?write? timing diagram pc_a[25:0], pc_nreg pc_nce pc_noe pc_nwait pc_d[15:0](din) t c (w) t su (ce-weh) t su (ce) t su (a-weh) t su (a) t su (oe-we) t w (we) pc_nwe pc_d[15:0](dout) valid data input t v (wt-we) t v (wt) t w (wt) t su (d-weh) t dis (we) t dis (oe) t en (we) t h (ce) t rec (we) t h (d) t h (oe-we) t en (oe)
CS22220 wireless pcmcia controller 29 of 34 ds557pp2 rev. 3.0 www.cirrus.com table 11. common memory ?write? timing specification 100 ns speed version item symbol min max write cycle time t c w 100 write pulse width t w (we) 60 address setup time t su (a) 10 address setup time for pc_nwe t su (a-weh) 70 card enable setup time for pc_nwe t su (ce-weh) 70 data setup time for pc_nwe t su (d-weh) 40 data hold time t h (d) 15 write recovery time t rec (we) 15 output disable time from pc_nwe t dis (we) 50 output disable time from pc_noe t dis (oe) 50 output enable time from pc_nwe t en (we) 5 output enable time from pc_noe t en (oe) 5 output enable setup from pc_nwe t su (oe-we) 10 output enable hold from pc_nwe t h (oe-we) 10 card enable setup time t su (ce) 0 card enable hold time t h (ce) 15 pc_nwait valid from pc_nwe t v (wt-we) 35 pc_nwait pulse width t w (wt) 12 us pc_nwe high from pc_nwait released 0 table 12. attribute memory ?write? timing specification 600 ns speed version item symbol min max write cycle time t c w 600 write pulse width t w (we) 300 address setup time t su (a) 50 address setup time for pc_nwe t su (a-weh) 350 card enable setup time for pc_nwe t su (ce-weh) 300 data setup time for pc_nwe t su (d-weh) 150 data hold time t h (d) 70 write recovery time t rec (we) 70 output disable time from pc_nwe t dis (we) 150 output disable time from pc_noe t dis (oe) 150 output enable time from pc_nwe t en (we) 5 output enable time from pc_noe t en (oe) 5 output enable setup from pc_nwe t su (oe-we) 35 output enable hold from pc_nwe t h (oe-we) 35 card enable setup time t su (ce) 0 card enable hold time t h (ce) 35 pc_nwait valid from pc_nwe t v (wt-we) 100 pc_nwait pulse width t w (wt) 12 us pc_nwe high from pc_nwait released 0
CS22220 wireless pcmcia controller 30 of 34 ds557pp2 rev. 3.0 www.cirrus.com figure 10. i/o ?read? timing diagram table 13. i/o ?read? (input) timing specification item symbol min max data delay after pc_niord t d (iord) 100 data hold following pc_niord t h (iord) 0 pc_niord width time t w iord 165 address setup before pc_niord t su a (iord) 70 address hold following pc_niord t h a(iord) 20 pc_nce setup before pc_niord t su ce (iord) 5 pc_nce hold following pc_niord t h ce (iord) 20 pc_nreg setup before pc_niord t su reg (iord) 5 pc_nreg hold before pc_niord t h reg (iord) 0 pc_ninpack delay falling from pc_niord t df inpack (iord) 0 45 pc_ninpack delay rising from pc_niord t dr inpack (iord) 45 pc_niois16 delay falling from address t df iois16 (adr) 35 pc_niois16 delay rising from address t dr iois16 (adr) 35 pc_nwait delay falling from pc_niord t d wt (iord) 35 data delay from pc_nwait rising t dr (wt) 0 pc_nwait width time t w (wt) 12,000 t su reg (iord) t su ce (iord) t h a (iord) t h reg (iord) t h ce (iord) t w (iord) t su a (iord) t df iois16 (adr) t df inpack (iord) t w (wt) t h (iord) t df wt (iord) pc_a[25:0] pc_nreg pc_nce pc_niord pc_iois16 pc_nwait pc_d[15:0] pc_ninpack t dr inpack (adr) t dr iois16 (adr) t d (iord) t dr (wt)
CS22220 wireless pcmcia controller 31 of 34 ds557pp2 rev. 3.0 www.cirrus.com figure 11. i/o ?write? timing diagram table 14. i/o ?write? (output) timing specification item symbol min max data setup after pc_niowr t d (niowr) 60 data hold following pc_niowr t h (niowr) 30 pc_niowr width time t w iowr 165 address setup before pc_niowr t su a (niowr) 70 address hold following pc_niowr t h a (niowr) 20 pc_nce setup before pc_niowr t su ce (niowr) 5 pc_nce hold following pc_niowr t h ce (niowr) 20 pc_nreg setup before pc_niowr t su reg (niowr) 5 pc_nreg hold following pc_niowr t h reg (niowr) 0 pc_niois16 delay falling from address t df iois16 (adr) 35 pc_niois16 delay rising from address t dr iois16 (adr) 35 pc_nwa it delay falling from pc_niowr t d wt (niowr) 35 pc_nwait width time t w (wt) 12,000 pc_niowr width time t dr iowr (wt) 0 t su reg (iowr) t su ce (iowr) t h a(iowr) t h reg (iowr) t h ce (iowr) t w (iowr) t su a(iowr) t df iois16 (adr) t df wt (iowr) t dr iowr (wt) t w (wt) t h (iowr) t su (iowr) pc_a[25:0] pc_nreg pc_nce pc_niowr pc_iois16 pc_nwait pc_d[15:0] t dr iois16 (adr)
CS22220 wireless pcmcia controller 32 of 34 ds557pp2 rev. 3.0 www.cirrus.com table 15. radio mac ac timings ? intersil modes parameter parameter description min max units t d bbas bbas output delay from falling bbsclk 8.2 ns t d bbrnw bbrnw output delay from falling bbsclk 8.0 ns t d nbbcs nbbcs output delay from falling bbsclk 59.0 ns t d bbsdx bbsdx output delay from falling bbsclk 7.0 ns t su bbsdx bbsdx setup to rising edge of bbsclk 14.8 ns t h bbsdx bbsdx hold from rising edge of bbsclk 0.0 ns t d txd txd output delay from rising txclk (smac mode) 33.5 ns t d txd txd output delay from rising txclk (rmac mode) 15.4 ns t su rxd rxdsetuptorisingedgeofrxclk 1.0 ns t h rxd rxd hold from rising edge of rxclk 1.8 ns t su mdrdy mdrdy setup to falling edge of rxclk 2 ns t h mdrdy mdrdy hold from falling edge of rxclk 1 ns t d txpebb txpebb output delay from rising txclk 15.0 ns t d rxpebb rxpebb output delay from rising rxclk 16.0 ns t su txrdy txrdy setup to falling edge of txclk 6.5 ns t h txrdy txrdy hold from falling edge of txclk 0 ns t duty rxclk 2 rxclk period see note ns t duty txclk 2 txclk period see note ns notes: 1. cca signal is double synchronized to armclkin. 2. armclk must be at least 4 times the txclk and rxclk frequency. 3. harris baseband (3824/3824a) generates rxclk and txclk of 4 mhz. the duty cycle varies between 33-40% with a high time of 90.9ns and low time that alternates between 136 and 182ns. the clock period varies between 227 and 272 ns, giving an effective period of 250ns. 4. txd delay in 802.11b mode is the result of sampling the txclk with the ctlclk, therefore the maximum delay is equal to two ctlclk periods plus the flop-to-output delay. in this table, ctlclk is assumed to have a 13 ns period. 5. bbncs output delay = [(1/armclk freq)*ceiling(ser_clk_div/2)] + 7ns, the specified value is based on armclk of 77 mhz and ser_clk_div=8.
CS22220 wireless pcmcia controller 33 of 34 ds557pp2 rev. 3.0 www.cirrus.com table 16. radio mac ac timings ? rfmd modes parameter parameter description min max units t d bbrnw bbrnw output delay from falling bbsclk 6.7 ns t d nbbcs nbbcs output delay from falling bbsclk 110.79 ns t d bbsdx bbsdx output delay from falling bbsclk 7.0 ns t su bbsdx bbsdx setup to rising edge of bbsclk 14.5 ns t h bbsdx bbsdx hold from rising edge of bbsclk 0.0 ns t d txd txd output delay from rising txclk (smac mode) 33.5 ns t d txd txd output delay from rising txclk (rmac mode) 15.4 ns t su rxd rxdsetuptorisingedgeofrxclk 1.0 ns t h rxd rxd hold from rising edge of rxclk 1.8 ns t su mdrdy mdrdy setup to falling edge of rxclk 2 ns t h mdrdy mdrdy hold from falling edge of rxclk 1 ns t d txpebb txpebb output delay from rising txclk 15.0 ns t d rxpebb rxpebb output delay from rising rxclk 16.0 ns t su txrdy txrdy setup to falling edge of txclk 6.5 ns t h txrdy txrdy hold from falling edge of txclk 0 ns notes: 1. cca signal is double synchronized to armclkin. 2. armclk must be at least 4 times the txclk and rxclk frequency. 3. txd delay in 802.11b mode is the result of sampling the txclk with the ctlclk, therefore the maximum delay is equal to two ctlclk periods plus the flop-to-output delay. in this table, ctlclk is assumed to have a 13 ns period. 4. bbncs output delay = [(1/armclk freq)*ceiling(ser_clk_div/2)] + 7ns, the specified value is based on armclk of 77 mhz and ser_clk_div=8. table 17. package specifications symbol parameter value units jc junction-to-case thermal resistance 2.5 c/w ja junction-to-open air thermal resistance 26.9 c/w t j_max max junction temperature 105 c notes: 1. armclk / memclk = 77mhz
CS22220 wireless pcmcia controller 34 of 34 ds557pp2 rev. 3.0 www.cirrus.com 6 packaging the CS22220 controller is available in a 208 fine pitch ball grid array (fpbga) package. figure 12 contains the package mechanical drawing. figure 12. CS22220 208 fpbga-pin mechanical drawing

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