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x24257 characteristics subject to change without notice. 2 of 21 xicor e 2 proms are designed and tested for applica- tions requiring extended endurance. inherent data retention is greater than 100 years. pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. for selecting typical values, refer to the pull- up resistor selection graph at the end of this data sheet. device select (s 0 , s 1 , s 2 ) the device select inputs (s 0 , s 1 , s 2 ) are used to set bits in the slave address. this allows up to eight devices to share a common bus. these inputs can be static or actively driven. if used statically they must be tied to v ss or v cc as appropriate. if actively driven, they must be driven with cmos levels (driven to v cc or v ss ) and they must be constant between each start and stop issued on the sda bus. these pins have an active pull down internally and will be sensed as low if the pin is left unconnected. write protect (wp) wp must be constant between each start and stop issued on the sda bus and is always active (not gated). the wp pin has an active pull down to disable the write protection when the input is left ?oating. the write protect input controls the hardware write pro- tect feature. when held low, hardware write protec- tion is disabled. when this input is held high, and the wpen bit in the write protect register is set high, the write protect register is protected, preventing changes to the block lock protection and wpen bits. pin names pin configuration symbol description s 0 , s 1 , s 2 device select inputs sda serial data scl serial clock wp write protect v ss ground v cc supply voltage nc no connect 8 lead pdip/soic v cc wp scl s 0 s 1 1 2 3 4 6 7 8 x24257 v ss sda s 2 5 14 lead tssop v cc wp scl s 0 s 1 nc 1 2 3 4 7 6 5 x24257 v ss sda nc nc nc nc 8 9 10 11 12 14 13 nc 8-lead xbga: top view s 1 sda s 2 scl vcc vss s 0 wp 8 7 6 5 1 2 3 4 s 2
x24257 characteristics subject to change without notice. 3 of 21 device operation the device supports a bidirectional bus oriented proto- col. the protocol de?nes any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers, and pro- vide the clock for both transmit and receive operations. therefore, the device will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. figure 1. data validity figure 2. definition of start and stop scl sda data stable data change scl sda start bit stop bit
x24257 characteristics subject to change without notice. 4 of 21 stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 3. the device will respond with an acknowledge after rec- ognition of a start condition and its slave address. if both the device and a write operation have been selected, the device will respond with an acknowledge after the receipt of each subsequent 8-bit word. in the read mode the device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. if an acknowledge is not detected, the device will terminate further data trans- missions. the master must then issue a stop condition to return the device to the standby power mode and place the device into a known state. figure 3. acknowledge response from receiver scl from master data output from transmitter 1 89 data output from receiver start acknowledge device addressing following a start condition, the master must output the address of the slave it is accessing. the ?rst four bits of the slave address byte are the device type identi?er bits. these must equal 1010. the next 3 bits are the device select bits s 0 , s 1 , and s 2 . this allows up to 8 devices to share a single bus. these bits are com- pared to the s 0 , s 1 , and s 2 device select input pins. the last bit of the slave address byte de?nes the operation to be performed. when the r/w bit is a one, then a read operation is selected. when it is zero then a write operation is selected. refer to figure 4. after loading the slave address byte from the sda bus, the device compares the device type bits with the value 1010 and the device select bits with the status of the device select input pins. if the compare is not success- ful, no acknowledge is output during the ninth clock cycle and the device returns to the standby mode. on power up the internal address is unde?ned, so the ?rst read or write operation must supply an address. the word address is either supplied by the master or obtained from an internal counter, depending on the operation. the master must supply the two word address bytes as shown in figure 4. the internal organization of the e 2 array is 512 pages by 64 bytes per page. the page address is partially contained in the word address byte 1 and partially in bits 7 through 6 of the word address byte 0. the byte address is contained in bits 5 through 0 of the word address byte 0. see figure 4.
x24257 characteristics subject to change without notice. 5 of 21 figure 4. device addressing 1 s 1 s 0 r/w device select 010 device type identifier slave address byte d7 d2 d1 d6 d5 d4 d3 data byte a2 a1 a0 a5 low order word address a4 a3 word address byte 0 * a10 a9 a8 a14 high order word address a11 x24257 word address byte 1 a13 a12 a7 a6 d0 *this bit is 0 for access to the array and 1 for access to the control register s 2 write operations byte write for a write operation, the device follows 3 byte proto- col, consisting of one slave address byte, one word address byte 1, and the word address byte 0, which gives the master access to any one of the words in the array. upon receipt of the word address byte 0, the device responds with an acknowledge, and waits for the ?rst eight bits of data. after receiving the 8 bits of the data byte, the device again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. while the internal write cycle is in progress the device inputs are disabled and the device will not respond to any requests from the master. the sda pin is at high impedance. see figure 5. page write the device is capable of a 64 byte page write opera- tion. it is initiated in the same manner as the byte write operation; but instead of terminating the write opera- tion after the ?rst data word is transferred, the master can transmit up to sixty-three more words. the device will respond with an acknowledge after the receipt of each word, and then the byte address is internally incremented by one. the page address remains con- stant. when the counter reaches the end of the page, it rolls over and goes back to the ?rst byte of the cur- rent page. this means that the master can write 64 bytes to the page beginning at any byte. if the master begins writing at byte 32, and loads 64 bytes, then the ?rst 32 bytes are written to bytes 32 through 63, and the last 16 words are written to bytes 0 through 31. afterwards, the address counter would point to byte 32.
x24257 characteristics subject to change without notice. 6 of 21 if the master writes more than 64 bytes, then the previ- ously loaded data is overwritten by the new data, one byte at a time. the master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer to figure 6 for the address, acknowl- edge, and data transfer sequence. figure 5. byte write sequence figure 6. page write sequence signals from the master sda bus signals from the slave s t a r t slave address s t o p a c k a c k a c k a c k word address byte 1 data 1 0 1 0 word address byte 0 s p 0 s t a r t slave address s t o p a c k a c k a c k a c k a c k data (0) signals from the master sda bus signals from the slave (n) word address byte 1 word address byte 0 0 s p data 1 0 1 0 (0 n 64) stop and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and its associated ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte + ack is sent, then the device will reset itself without performing the write. the contents of the array will not be affected. acknowledge polling the maximum write cycle time can be signi?cantly reduced using acknowledge polling. to initiate acknowledge polling, the master issues a start condi- tion followed by the slave address byte for a write or read operation. if the device is still busy with the inter- nal write cycle, then no ack will be returned. if the device has completed the internal write operation, an ack will be returned and the host can then proceed with the read or write operation. refer to figure 7.
x24257 characteristics subject to change without notice. 7 of 21 figure 7. acknowledge polling sequence read operations read operations are initiated in the same manner as write operations with the exception that the r/w bit of the slave address byte is set to one. there are three basic read operations: current address reads, ran- dom reads, and sequential reads. current address read internally, the device contains an address counter that maintains the address of the last word read or written incremented by one. after a read operation from the last address in the array, the counter will roll over to the ?rst address in the array. after a write operation to the last address in a given page, the counter will roll over to the ?rst address on the same page. upon receipt of the slave address byte with the r/w bit set to one, the device issues an acknowledge and then transmits the eight bits of the data byte. the master terminates the read operation when it does not respond with an acknowledge during the ninth clock and then issues a stop condition. refer to figure 8 for the address, acknowledge, and data transfer sequence. it should be noted that the ninth clock cycle of the read operation is not a dont care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. figure 8. current address read sequence byte load completed by issuing stop. enter ack polling issue start issue slave address byte (read or write) ack returned? high voltage cycle complete. continue sequence? continue normal read or write command sequence proceed issue stop no yes yes issue stop no from the s t a r t slave address s t o p a c k data signals from the master sda bus signals slave 1 sp 010 1
x24257 characteristics subject to change without notice. 8 of 21 random read random read operation allows the master to access any memory location in the array. prior to issuing the slave address byte with the r/w bit set to one, the master must ?rst perform a dummy write operation. the master issues the start condition and the slave address byte with the r/w bit low, receives an acknowledge, then issues the word address byte 1, receives another acknowledge, then issues the word address byte 0. after the device acknowledges receipt of the word address byte 0, the master issues another start condition and the slave address byte with the r/ w bit set to one. this is followed by an acknowledge and then eight bits of data from the device. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. refer to figure 9 for the address, acknowledge, and data transfer sequence. the device will perform a similar operation called set current address if a stop is issued instead of the sec- ond start shown in figure 9. the device will go into standby mode after the stop and all bus activity will be ignored until a start is detected. the effect of this oper- ation is that the new address is loaded into the address counter, but no data is output by the device. the next current address read operation will read from the newly loaded address. sequential read sequential reads can be initiated as either a current address read or random read. the ?rst data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indicating it requires additional data. the device continues to out- put data for each acknowledge received. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all byte addresses, allowing the entire memory contents to be read during one operation. at the end of the address space the counter rolls over to address 0000h and the device continues to output data for each acknowledge received. refer to figure 10 for the acknowledge and data transfer sequence. figure 9. random read sequence figure 10. sequential read sequence signals from the master sda bus signals from the slave s t a r t slave address s t o p a c k a c k a c k word address byte 1 slave address 0 word address byte 0 s t a r t 1 data a c k s p s 1010 slave address s s t o p a c k a c k a c k a c k data (1) data (2) signals from the master sda bus signals from the slave data (nC1) data (n) 1 (n is any integer greater than 1) p
x24257 characteristics subject to change without notice. 9 of 21 control register (cr) the control register is located in an area logically separated from the array and is only accessible via a byte write to the register address of ffffh. the con- trol register is physically part of the array. the control register can only be modi?ed by perform- ing a byte write operation directly to the address of the register and only one data byte is allowed for each reg- ister write operation. prior to initiating a nonvolatile write to the control register, the wel and rwel bits must be set using a two step process, with the whole sequence requiring 3 steps. the user must issue a stop, after sending this byte to the register, to initiate the high voltage cycle that writes bp2, bp1, bp0 and wpen to the nonvolatile bits. the part will not acknowledge any data bytes written after the ?rst byte is entered. a stop must also be issued after a volatile register write operation to put the device into standby. after a write to the cr, the address counter contents are unde?ned. the state of the control register can be read by per- forming a random read at the address of the register at any time. only one byte is read by the register read operation. the part will reset itself after the ?rst byte is read. the master should supply a stop condition to be consistent with the bus protocol, but a stop is not required to end this operation. after the read of the cr, the address counter contents are reset to zero, but the user will be told these bits are unde?ned and instructed to do a random read. table 1. control register rwel: register write enable latch the rwel bit must be set to 1 prior to a write to control register. wel: write enable latch (volatile) the wel bit controls the access to the memory and to the register during a write operation. this bit is a vola- tile latch that powers up in the low (disabled) state. while the wel bit is low, writes to any address, including any control registers will be ignored (no acknowledge will be issued after the data byte). the wel bit is set by writing a 1 to the wel bit and zeros to the other bits of the control register. once set, wel remains set until either it is reset to 0 (by writing a 0 to the wel bit and zeros to the other bits of the control register) or until the part powers up again. writes to wel bit do not cause a high voltage write cycle, so the device is ready for the next operation immediately after the stop condition. bp2, bp1, bp0: block protect bits (nonvolatile) the block protect bits, bp2, bp1 and bp0, determine which blocks of the array are write protected. a write to a protected block of memory is ignored. the block pro- tect bits will prevent write operations to one of eight segments of the array. the partitions are described in table 2. 76543210 wpen x x bp1 bp0 rwel wel bp2 table 2. block protect bits bp2 bp1 bp0 protected addresses array lock 0 0 0 none none 0 0 1 6000h - 7fffh (8k bytes) upper 1/4 (q4) 0 1 0 4000h - 7fffh (16k bytes) upper 1/2 (q3, q4) 0 1 1 0000h - 7fffh (32k bytes) full array (all) 1 0 0 0000h - 003fh (64 bytes) first page (p1) 1 0 1 0000h - 007fh (128 bytes) first 2 pgs (p2) 1 1 0 0000h - 00ffh (256 bytes) first 4 pgs (p4) 1 1 1 0000h - 01ffh (512 bytes) first 8 pgs (p8)
x24257 characteristics subject to change without notice. 10 of 21 figure 11. block protection configuration bp2- bp0 000 001 010 011 100 101 110 111 write protect enable bit - wpen - (nonvolatile) the write protect (wp ) pin and the write protect enable (wpen) bit in the control register control the programmable hardware write protect feature. hard- ware write protection is enabled when the wp pin is high and the wpen bit is high, and disabled when either the wp pin is low. when the chip is hardware write protected, nonvolatile writes are disabled to the control register, including the block protect bits and the wpen bit itself, as well as to the block sections in the memory array. only the sections of the memory array that are not block protected can be written. note that since the wpen bit is write protected, it cannot be changed back to a low state; so write protection is enabled as long as the wp pin is held high. table 3. write protect enable bit and wp pin function wp wpen memory array not block protected memory array block protected block lock bits wpen bit protection low x writes ok writes blocked writes ok writes ok software high 0 writes ok writes blocked writes ok writes ok software high 1 writes ok writes blocked writes blocked writes blocked hardware none 1 page 2 pages 4 pages 8 pages 1/2 array 1/4 array all array
x24257 characteristics subject to change without notice. 11 of 21 unused bits: bits 5 & 6 are unused. all writes to the control regis- ter must have a zero in these bit positions. the data byte output during a control register read will contain zeros in these bit locations. writing to the control register changing any of the nonvolatile bits of the control reg- ister requires the following steps: ? write a 02h to the control register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation pre- ceeded by a start and ended with a stop). ? write a 06h to the control register to set both the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation preceeded by a start and ended with a stop). ? write a value to the control register that has all the control bits set to the desired state, with the wel bit set to 1 and the rwel bit set to 0. this can be represented as n 00 s t 01 r in binary, where n is the wpen bit and rst are the bp2-bp0 bits. (operation preceeded by a start and ended with a stop). since this is nonvolatile write cycle it will take up to 10ms to complete. the rwel bit is reset by this cycle and the sequence must be repeated to change the non- volatile bits again. if bit 2 is set to 1 in this third step ( n 00 s t 11 r ) then the rwel bit remains set and the wpen, bp2, bp1 and bp0 bits remain unchanged. ? a read operation occurring between any of the previ- ous operations will not interrupt the register write operation. ? the rwel bit cannot be reset without writing to the nonvolatile control bits in the control register, power cycling the device or attempting a write to a write protected block. to illustate, a sequence of writes to the device consist- ing of [02h, 06h, 02h] will reset all of the nonvolatile bits to 0 and clear the rwel bit. a sequence of [02h, 06h, 06h] will leave the nonvolatile bits unchanged and the rwel bit remains set.
x24257 characteristics subject to change without notice. 12 of 21 absolute maximum ratings* temperature under bias 24257.............................................C65 c to +135 c storage temperature.........................C65 c to +150 c voltage on any pin with respect to v ss ....................................... C1v to +7v d.c. output current.............................................. 5ma lead temperature (soldering, 10 seconds) ..................................300 c recommended operating conditions *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci- ?cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. temperature min. max. commercial 0 c +70 c industrial C40 c +85 c supply voltage limits x24257 4.5v to 5.5v x24257C2.5 2.5v to 5.5v x24257C1.8 1.8v to 3.6v d.c. operating characteristics v cc equals the range indicated for each device type, unless otherwise stated. v cc = 1.8 to 3.6v v cc = 2.5 to 5.5v v cc = 4.5 to 5.5v symbol parameter min. max. min. max. min. max. units test conditions i cc1 active supply current (read) 0.5 1 1 ma v il = v cc x 0.1 v ih = v cc x 0.9 f scl = 400khz sda = open i cc2 active supply current (write) 1.5 3 3 ma i sb1 (2) standby current ac 111mav il = v cc x 0.1 v ih = v cc x 0.9 f scl = 400khz sda = open v sb standby voltage (test) v cc C 0.1 v cc C 0.2 v cc C 0.3 v i sb2 (2) standby current dc 1 1 10 ma v sda = v scl = v sb, others = gnd or v sb i li input leakage current 10 10 10 ma v in = gnd to v cc i lo output leakage current 10 10 10 ma v sda = gnd to v cc device is in standby(2) v ll (3) input low voltage C0.5 v cc x 0.3 C0.5 v cc x 0.3 C0.5 v cc x 0.3 v v ih (3) input high voltage v cc x 0.7 v cc + 0.5 v cc x 0.7 v cc + 0.5 v cc x 0.7 v cc + 0.5 v v hys schmitt trigger input hysteresis fixed input level 0.2 0.2 0.2 v v cc related level v cc x 0.05 v cc x 0.05 v cc x 0.05 v v ol output low voltage 0.4 0.4 0.4 v i ol = 3ma
x24257 characteristics subject to change without notice. 13 of 21 capacitance t a = +25c, f = 1mhz, v cc = 5v notes: (1) the device enters the active state after any start, and remains active until: 9 clock cycles later if the device select bits in the slave address byte are incorrect; 200ns after a stop ending a read operation; or t wc after a stop ending a write operation. (2) the device goes into standby: 200ns after any stop, except those that initiate a high voltage write cycle; t wc after a stop that inti- ates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct device select bits in the slav e address byte. (3) vil min. and vih max. are for reference only and are not tested. symbol parameter max. units test conditions c i/o (3) input/output capacitance (sda) 8pf v i/o = 0v c in (3) input capacitance (s 0 , s 1 , s 2 , scl, wp) 6pf v in = 0v a.c. conditions of test equivalent a.c. load circuit input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load 5v 1.53k w 100pf output for v ol = 0.4v i ol = 3ma a.c. operating characteristics (over the recommended operating conditions, unless otherwise specified.) read & write cycle limits symbol parameter v cc 1.8v v cc 2.5v units min. max. min. max. f scl scl clock frequency 0 100 0 400 khz t in pulse width suppression time at inputs n/a n/a 50 ns t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 m s t buf time the bus must be free before a new transmission can start 4.7 1.3 m s t low clock low period 4.7 1.3 m s t high clock high period 4.0 0.6 m s t su:sta start condition setup time 4.7 0.6 m s t hd:sta start condition hold time 4.0 0.6 m s t su:dat data in setup time 250 100 ns t hd:dat data in hold time 0 0 m s t su:sto stop condition setup time 4.7 0.6 m s t dh data output hold time 300 50 ns
x24257 characteristics subject to change without notice. 14 of 21 power-up timing (4) notes: (4) t pur and t puw are the delays required from the time v cc is stable until the speci?ed operation can be initiated. these parameters are periodically sampled and not 100% tested. (5) typical values are for t a = 25 c and nominal supply voltage (5v), cb = total capacitance of one bus line in pf. bus timing t r sda and scl rise time 1000 20+ .1cb (3) 300 ns t f sda and scl fall time 300 20+ .1cb (3) 300 ns t su:s0, s1, s2, wp s0, s1, s2, and wp setup time 0.4 0.6 ns t hd:s0, s1, s2, wp s0, s1, s2, and wp hold time 0 0 ns cb capacitive load for each bus line 400 400 pf symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 5 ms a.c. operating characteristics (continued) (over the recommended operating conditions, unless otherwise specified.) read & write cycle limits symbol parameter v cc 1.8v v cc 2.5v units min. max. min. max. t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high
x24257 characteristics subject to change without notice. 15 of 21 s0, s1, s2, and wp pin timing write cycle limits notes: (6) t wc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write cycle. during the write cycle, the x24257 bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. write cycletiming symbol parameter min. typ. max. units t wc (6) write cycle time 5 10 ms t su: s0, s1, s2, wp scl sda in s0, s1, s2, and wp slave address byte clk 1 clk 9 t hd: s0, s1, s2, wp scl sda 8th bit word n ack t wc stop condition start condition
x24257 characteristics subject to change without notice. 16 of 21 guidelines for calculating typical values of bus pull-up resistors symbol table 120 100 80 40 60 20 20 40 60 80 100 120 0 0 resistance (k w ) bus capacitance (pf) min. resistance max. resistance r max = c bus t r r min = i ol min v cc max waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance
x24257 characteristics subject to change without notice. 17 of 21 packaging information note: all dimensions in inches (in p arentheses in millimeters) 14-lead plastic, tssop, package type v see detail a .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .193 (4.9) .200 (5.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0 e 8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x)
x24257 characteristics subject to change without notice. 18 of 21 packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 C 8 x 45 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
x24257 characteristics subject to change without notice. 19 of 21 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (.508) 0.012 (.305) .080 (2.03) .070 (1.78) .213 (5.41) .205 (5.21) 0 8 .330 (8.38) .300 (7.62) .212 (5.38) .203 (5.16) .035 (.889) .020 (.508) .010 (.254) .007 (.178) ref pin 1 id .050 (1.27) bsc 8-lead plastic, 0.200 wide small outline gullwing package typ a (eiaj soic) .013 (.330) .004 (.102)
x24257 characteristics subject to change without notice. 20 of 21 packaging information all dimensions in m (to convert to inches, 1 m = 3.94 x 10 -5 inch) all dimensions are typical values x24257: bottom view 8-lead xbga: top view s 1 sda s 2 scl v cc v ss s o wp 8 7 6 5 1 2 3 4 .137 .079 8-lead xbga complete part number top mark x24257z-2.5 xacg x24257zi-2.5 xach f d c s 1 s 0 v ss s 2 wp v cc sda scl a1 pin 1 8-lead xbga x24257b-2.5 xacg x24257bi-2.5 xach a1 e c e a dwg symbol 8l xbga a contact factory a1 contact factory c contact factory d contact factory e contact factory e contact factory f contact factory d
x24257 characteristics subject to change without notice. 21 of 21 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?cation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devi ces from patent infringement. xicor, inc. makes no warranty of merchantability or ?tness for any purpose. xicor, inc. reserves the right to discontinue production and change s peci?cations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor andthe xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, and xdc p are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?cant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ordering information device x24257 x x -x v cc range blank = 5v 10% 2.5 = 2.5v to 5.5v temperature range blank = 0 c to +70 c i = C40 c to +85 c package x24257 s8 = 8-lead soic (jedec) blank = 4.5v to 5.5v, 0 c to +70 c i = 4.5v to 5.5v, C40 c to +85 c j = 2.5v to 5.5v, 0 c to +70 c k = 2.5v to 5.5v, C40 c to +85 c x24257 x x s8 = 8-lead soic, 150 mil wide, jedec 1.8 = 1.8v to 3.6v ag = 1.8v to 3.6v, 0c to +70c ah = 1.8v to 3.6v, C40c to +85c v14 = 14-lead tssop v14 = 14-lead tssop z = 8-lead xbga xbga package complete part number top mark x24257zi - 2.5 xach lead tssop/soic x24257z - 2.5 xacg part mark convention x24257bi - 2.5 xach x24257b - 2.5 xacg a8 = 8-lead soic, 200 mil wide, eiaj a8 = 8-lead soic (eiaj) b = 8-lead xbga

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