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rej03b0283-0001 rev.0.01 sep. 01, 2009 page 1 of 27 r8c/35c group renesas mcu 1. overview 1.1 features the r8c/35c group of single-chip mcus incorporates the r8c cpu core, employing sophisticated instructions for a high level of efficiency. with 1 mbyte of address sp ace, and it is capable of executing instructions at high speed. in addition, the cpu core boasts a multiplier for high-speed operation processing. power consumption is low, and the supported operating modes allow additional power control. these mcus are designed to maximize emi/ems performance. integration of many peripheral functions, including multifun ction timer and serial inte rface, reduces the number of system components. the r8c/35c group has data flash (1 kb 4 blocks) with the background operation (bgo) function. 1.1.1 applications electronic household appliances, office equipment, audio equipment, cons umer equipment, etc. rej03b0283-0001 rev.0.01 sep. 01, 2009 preliminary notice: this is not a final specification. some parametric limits are subject to change.
r8c/35c group 1. overview rej03b0283-0001 rev.0.01 sep. 01, 2009 page 2 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. 1.1.2 specifications tables 1.1 and 1.2 outline the specifications for r8c/35c group. table 1.1 specifications for r8c/35c group (1) item function specification cpu central processing unit r8c cpu core ? number of fundamental instructions: 89 ? minimum instruction execution time: 50 ns (f(xin) = 20 mhz, vcc = 2.7 to 5.5 v) 200 ns (f(xin) = 5 mhz, vcc = 1.8 to 5.5 v) ? multiplier: 16 bits 16 bits 32 bits ? multiply-accumulate instruction: 16 bits 16 bits + 32 bits 32 bits ? operation mode: single-chip mode (address space: 1 mbyte) memory rom, ram, data flash refer to table 1.3 product list for r8c/35c group . power supply voltage detection voltage detection circuit ? power-on reset ? voltage detection 3 (detection level of voltage detection 0 and voltage detection 1 selectable) i/o ports programmable i/o ports ? input-only: 1 pin ? cmos i/o ports: 47, selectable pull-up resistor ? high current drive ports: 47 clock clock generation circuits 4 circuits: xin clock oscillation circuit, xcin clock oscillation circuit (32 khz), high-speed on-chip oscillator (with frequency adjustment function), low-speed on-chip oscillator ? oscillation stop detection: xin clock oscillation stop detection function ? frequency divider circuit: dividing selectable 1, 2, 4, 8, and 16 ? low power consumption modes: standard operating mode (high-speed cl ock, low-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode real-time clock (timer re) interrupts ? number of interrupt vectors: 69 ? external interrupt: 9 (int 5, key input 4) ? priority levels: 7 levels watchdog timer ? 14 bits 1 (with prescaler) ? reset start selectable ? low-speed on-chip oscillator for watchdog timer selectable dtc (data transfer controller) ? 1 channel ? activation sources: 33 ? transfer modes: 2 (normal mode, repeat mode) timer timer ra 8 bits 1 (with 8-bit prescaler) timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse wi dth measurement mode, pulse period measurement mode timer rb 8 bits 1 (with 8-bit prescaler) timer mode (period timer), programmable waveform generation mode (pwm output), programmable one-shot generation mode, programmable wait one- shot generation mode timer rc 16 bits 1 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 3 pins), pwm2 mode (pwm output pin) timer rd 16 bits 2 (with 4 capture/compare registers) timer mode (input capture function, output compare function), pwm mode (output 6 pins), reset synchronous pwm mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary pwm mode (output three-phase waveforms (6 pins), triangular wave modulation), pwm3 mode (pwm output 2 pins with fixed period) timer re 8 bits 1 real-time clock mode (count seconds, minu tes, hours, days of week), output compare mode
r8c/35c group 1. overview rej03b0283-0001 rev.0.01 sep. 01, 2009 page 3 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. note: 1. specify the d version if d ve rsion functions are to be used. table 1.2 specifications for r8c/35c group (2) item function specification serial interface uart0, uart1 clock synchronous serial i/o/uart 2 channel uart2 clock synchronous serial i/o/uart, i 2 c mode (i 2 c-bus), multiprocessor communication function synchronous serial communication unit (ssu) 1 (shared with i 2 c-bus) i 2 c bus 1 (shared with ssu) lin module hardware lin: 1 (timer ra, uart0) a/d converter 10-bit resolution 12 channels, includes sample and hold function, with sweep mode d/a converter 8-bit resolution 2 circuits comparator b 2 circuits flash memory ? programming and eras ure voltage: vcc = 2.7 to 5.5 v ? programming and erasure enduranc e: 10,000 times (data flash) 1,000 times (program rom) ? program security: rom code protect, id code check ? debug functions: on-chip debug, on-board flash rewrite function ? background operation (bgo) function operating frequency/supply voltage f(xin) = 20 mhz (vcc = 2.7 to 5.5 v) f(xin) = 5 mhz (vcc = 1.8 to 5.5 v) current consumption typ. 6.5 ma (vcc = 5.0 v, f(xin) = 20 mhz) typ. 3.5 ma (vcc = 3.0 v, f(xin) = 10 mhz) typ. 3.5 a (vcc = 3.0 v, wait mode (f(xcin) = 32 khz)) typ. 2.0 a (vcc = 3.0 v, stop mode) operating ambient temperature -20 to 85 c (n version) -40 to 85 c (d version) (1) package 52-pin lqfp package code: plqp0052ja-a (previous code: 52p6a-a)
r8c/35c group 1. overview rej03b0283-0001 rev.0.01 sep. 01, 2009 page 4 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. 1.2 product list table 1.3 lists product list for r8c/35c group, and figur e 1.1 shows a part number, memory size, and package of r8c/35c group. (d): under development (p): under planning figure 1.1 part number, memory size, and package of r8c/35c group table 1.3 product list for r8c/35c group current of sep. 2009 part no. rom capacity ram capacity package type remarks program rom data flash r5f21354cnfp (d) 16 kbytes 1 kbyte 4 1.5 kbytes plqp0052ja-a n version r5f21355cnfp (d) 24 kbytes 1 kbyte 4 2 kbytes plqp0052ja-a r5f21356cnfp (d) 32 kbytes 1 kbyte 4 2.5 kbytes plqp0052ja-a r5f21357cnfp (p) 48 kbytes 1 kbyte 4 4 kbytes plqp0052ja-a r5f21358cnfp (p) 64 kbytes 1 kbyte 4 6 kbytes plqp0052ja-a r5f2135acnfp (p) 96 kbytes 1 kbyte 4 8 kbytes plqp0052ja-a R5F2135CCNFP (p) 128 kbytes 1 kbyte 4 10 kbytes plqp0052ja-a r5f21354cdfp (d) 16 kbytes 1 kbyte 4 1.5 kbytes plqp0052ja-a d version r5f21355cdfp (d) 24 kbytes 1 kbyte 4 2 kbytes plqp0052ja-a r5f21356cdfp (d) 32 kbytes 1 kbyte 4 2.5 kbytes plqp0052ja-a r5f21357cdfp (p) 48 kbytes 1 kbyte 4 4 kbytes plqp0052ja-a r5f21358cdfp (p) 64 kbytes 1 kbyte 4 6 kbytes plqp0052ja-a r5f2135acdfp (p) 96 kbytes 1 kbyte 4 8 kbytes plqp0052ja-a r5f2135ccdfp (p) 128 kbytes 1 kbyte 4 10 kbytes plqp0052ja-a part no. r 5 f 21 35 6 c n fp package type: fp: plqp0052ja-a (0.65 mm pin-pitch, 10 mm square body) classification n: operating ambient temperature -20c to 85c d: operating ambient temperature -40c to 85c rom capacity 4: 16 kb 5: 24 kb 6: 32 kb 7: 48 kb 8: 64 kb a: 96 kb c: 128 kb r8c/35c group r8c/3x series memory type f: flash memory renesas mcu renesas semiconductor
r8c/35c group 1. overview rej03b0283-0001 rev.0.01 sep. 01, 2009 page 5 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram d/a converter (8 bits 2) r8c cpu core system clock generation circuit xin-xout high-speed on-chip oscillator low-speed on-chip oscillator xcin-xcout memory rom (1) ram (2) multiplier r0h r0l r1h r2 r3 r1l a0 a1 fb sb usp isp intb pc flg i/o ports notes: 1. rom size varies with mcu type. 2. ram size varies with mcu type. 8 port p1 8 port p3 5 1 port p4 8 port p0 8 port p2 2 port p5 timers timer ra (8 bits 1) timer rb (8 bits 1) timer rc (16 bits 1) timer rd (16 bits 2) timer re (8 bits 1) uart or clock synchronous serial i/o (8 bits 3) i 2 c bus or ssu (8 bits 1) peripheral functions watchdog timer (14 bits) a/d converter (10 bits 12 channels) lin module comparator b voltage detection circuit dtc 8 port p6 low-speed on-chip oscillator for watchdog timer
r8c/35c group 1. overview rej03b0283-0001 rev.0.01 sep. 01, 2009 page 6 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. 1.4 pin assignment figure 1.3 shows the pin assignment (top view). tables 1.4 and 1.5 outlines the pin name information by pin number. figure 1.3 pin assignment (top view) 27 39 38 37 36 35 34 33 32 26 14 15 16 17 18 19 20 21 22 23 24 25 1 345678910111213 2 52 51 50 49 48 47 46 45 44 43 42 41 40 p5_7 p6_0(/treo) p6_1 p6_2(/clk1) p6_3(/txd1) p6_4(/rxd1) p0_0/an7(/trcioa/trctrg) p0_1/an6(/txd1/trcioa/trctrg) p0_2/an5(/rxd1/trcioa/trctrg) p0_3/an4(/clk1/trciob) p0_5/an2(/trciob) p0_6/an1/da0(/trciod) p0_4/an3/treo(/trciob) p2_7(/trdiod1) p2_6(/trdioc1) p2_5(/trdiob1) p2_4(/trdioa1) p2_3(/trdiod0) p2_2(/trciod/trdiob0) p2_1(/trcioc/trdioc0) p2_0(/int1/trciob/trdioa0/trdclk) p3_6(/int1) p3_1(/trbo) p0_7/an0/da1(/trcioc) p6_7(/int3/trciod) p6_6/int2(/txd2/sda2/trcioc) p6_5/int4(/clk1/clk2/trciob) p4_5/adtrg/int0(/rxd2/scl2) p1_7/ivcmp1/int1(/traio) p1_6/ivref1(/clk0) p1_5(/int1/rxd0/traio) p1_3/an11/kl3/trbo(/trcioc) p1_2/an10/kl2(/trciob) p1_0/an8/ki0(/trciod) p1_1/an9/ki1(/trcioa/trctrg) p1_4(/txd0/trcclk) p5_6(/trao) p3_7/sda/sso/trao(/rxd2/scl2/txd2/sda2) vcc/avcc p4_6/xin vss/avss reset p4_4(/xcout) p3_2(/int1/int2/traio) p4_3(/xcin) p4_7/xout notes: 1. can be assigned to the pin in parentheses by a program. 2. confirm the pin 1 position on the package by referring to the package dimensions. 31 30 29 28 p3_5/scl/ssck(/clk2/trciod) p3_4/ivref3/ssi(/rxd2/scl2/txd2/sda2/trcioc) p3_3/ivcmp3/int3/scs(/cts2/rts2/trcclk) p3_0(/trao) p4_2/vref mode r8c/35c group plqp0052ja-a(52p6a-a) (top view)
r8c/35c group 1. overview rej03b0283-0001 rev.0.01 sep. 01, 2009 page 7 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. note: 1. can be assigned to the pin in parentheses by a program. table 1.4 pin name information by pin number (1) pin number control pin port i/o pin functions for peripheral modules interrupt timer serial interface ssu i 2 c bus a/d converter, d/a converter, comparator b 1p5_6(trao) 2p3_2 (int1 /int2 ) (traio) 3p3_0(trao) 4p4_2 vref 5mode 6(xcin)p4_3 7 (xcout) p4_4 8 reset 9xoutp4_7 10 vss/avss 11 xin p4_6 12 vcc/avcc 13 p3_7 trao (rxd2/scl2/ txd2/sda2) sso sda 14 p3_5 (trciod) (clk2) ssck scl 15 p3_4 (trcioc) (rxd2/scl2/ txd2/sda2) ssi ivref3 16 p3_3 int3 (trcclk) (cts2 /rts2 )scs ivcmp3 17 p2_7 (trdiod1) 18 p2_6 (trdioc1) 19 p2_5 (trdiob1) 20 p2_4 (trdioa1) 21 p2_3 (trdiod0) 22 p2_2 (trciod/ trdiob0) 23 p2_1 (trcioc/ trdioc0) 24 p2_0 (int1 ) (trciob/ trdioa0/ trdclk) 25 p3_6 (int1 ) 26 p3_1 (trbo) 27 p6_7 (int3 ) (trciod) 28 p6_6 int2 (trcioc) (txd2/sda2) 29 p6_5 int4 (trciob) (clk1/clk2) 30 p4_5 int0 (rxd2/scl2) adtrg 31 p1_7 int1 (traio) ivcmp1 32 p1_6 (clk0) ivref1 33 p1_5 (int1 ) (traio) (rxd0) 34 p1_4 (trcclk) (txd0) 35 p1_3 ki3 trbo (/trcioc) an11
r8c/35c group 1. overview rej03b0283-0001 rev.0.01 sep. 01, 2009 page 8 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. note: 1. can be assigned to the pin in parentheses by a program. table 1.5 pin name information by pin number (2) pin number control pin port i/o pin functions for peripheral modules interrupt timer serial interface ssu i 2 c bus a/d converter, d/a converter, comparator b 36 p1_2 ki2 (trciob) an10 37 p1_1 ki1 (trcioa/ trctrg) an9 38 p1_0 ki0 (trciod) an8 39 p0_7 (trcioc) an0/da1 40 p0_6 (trciod) an1/da0 41 p0_5 (trciob) an2 42 p0_4 treo (/trciob) an3 43 p0_3 (trciob) (clk1) an4 44 p0_2 (trcioa/ trctrg) (rxd1) an5 45 p0_1 (trcioa/ trctrg) (txd1) an6 46 p0_0 (trcioa/ trctrg) an7 47 p6_4 (rxd1) 48 p6_3 (txd1) 49 p6_2 (clk1) 50 p6_1 51 p6_0 (treo) 52 p5_7
r8c/35c group 1. overview rej03b0283-0001 rev.0.01 sep. 01, 2009 page 9 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. 1.5 pin functions tables 1.6 and 1.7 list pin functions. i: input o: output i/o: input and output notes: 1. refer to the oscillator manufacturer for oscillation characteristics. table 1.6 pin functions (1) item pin name i/o type description power supply input vcc, vss ? apply 1.8 v to 5.5 v to the vcc pin. apply 0 v to the vss pin. analog power supply input avcc, avss ? power supply for the a/d converter. connect a capacitor between avcc and avss. reset input reset i input ?l? on this pin resets the mcu. mode mode i connect this pin to vcc via a resistor. xin clock input xin i these pins are provid ed for xin clock generation circuit i/o. connect a ceramic resonator or a crystal oscillator between the xin and xout pins (1) . to use an external clock, input it to the xout pin and leave the xin pin open. xin clock output xout i/o xcin clock input xcin i these pins are provided for xcin clock generation circuit i/o. connect a crystal oscillator between the xcin and xcout pins (1) . to use an external clock, input it to the xcin pin and leave the xcout pin open. xcin clock output xcout o int interrupt input int0 to int4 iint interrupt input pins. int0 is timer rb, rc and rd input pin. key input interrupt ki0 to ki3 i key input interrupt input pins timer ra traio i/o timer ra i/o pin trao o timer ra output pin timer rb trbo o timer rb output pin timer rc trcclk i external clock input pin trctrg i external trigger input pin trcioa, trciob, trcioc, trciod i/o timer rc i/o pins timer rd trdioa0, trdioa1, trdiob0, trdiob1, trdioc0, trdioc1, trdiod0, trdiod1 i/o timer rd i/o pins trdclk i external clock input pin timer re treo o divided clock output pin serial interface clk0, clk1, clk2 i/o transfer clock i/o pins rxd0, rxd1, rxd2 i serial data input pins txd0, txd1, txd2 o serial data output pins cts2 i transmission control input pin rts2 o reception control output pin scl2 i/o i 2 c mode clock i/o pin sda2 i/o i 2 c mode data i/o pin i 2 c bus scl i/o clock i/o pin sda i/o data i/o pin ssu ssi i/o data i/o pin scs i/o chip-select signal i/o pin ssck i/o clock i/o pin sso i/o data i/o pin
r8c/35c group 1. overview rej03b0283-0001 rev.0.01 sep. 01, 2009 page 10 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. i: input o: output i/o: input and output table 1.7 pin functions (2) item pin name i/o type description reference voltage input vref i reference voltage input pin to a/d converter and d/a converter a/d converter an0 to an11 i analog input pins to a/d converter adtrg i ad external trigger input pin d/a converter da0, da1 o d/a converter output pins comparator b ivcmp1, ivcmp3 i comparator b analog voltage input pins ivref1, ivref3 i comparator b reference voltage input pins i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_3 to p4_7, p5_6, p5_7, p6_0 to p6_7 i/o cmos i/o ports. each port has an i/o select direction register, allowing each pin in the port to be directed for input or output individually. any port set to input can be set to use a pull-up resistor or not by a program. all ports can be used as led drive ports. input port p4_2 i input-only port
r8c/35c group 2. central processing unit (cpu) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 11 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. 2. central processi ng unit (cpu) figure 2.1 shows the cpu registers. the cpu contains 13 registers. r0, r1, r2, r3, a0, a1, and fb configure a register bank. there are two sets of register bank. figure 2.1 cpu registers r2 b31 b15 b8b7 b0 data registers (1) address registers (1) r3 r0h (high-order of r0) r2 r3 a0 a1 intbh b15 b19 b0 intbl fb frame base register (1) the 4 high order bits of intb are intbh and the 16 low order bits of intb are intbl. interrupt table register b19 b0 usp program counter isp sb user stack pointer interrupt stack pointer static base register pc flg flag register carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved bit processor interrupt priority level reserved bit c ipl d z s b o i u b15 b0 b15 b0 b15 b0 b8 b7 note: 1. these registers comprise a regist er bank. there are two register banks. r1h (high-order of r1) r0l (low-order of r0) r1l (low-order of r1)
r8c/35c group 2. central processing unit (cpu) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 12 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. 2.1 data registers (r 0, r1, r2, and r3) r0 is a 16-bit register for transfer, ar ithmetic, and logic operations. the same applies to r1 to r3. r0 can be split into high-order bits (r0h) and low-order bits (r0l) to be used separately as 8-bit data registers. r1h and r1l are analogous to r0h and r0l. r2 can be combined with r0 and used as a 32-bit data register (r2r0). r3r1 is analogous to r2r0. 2.2 address registers (a0 and a1) a0 is a 16-bit register for address register indirect addr essing and address register relative addressing. it is also used for transfer, arithmetic, and logic operations. a1 is an alogous to a0. a1 can be comb ined with a0 and as a 32- bit address register (a1a0). 2.3 frame base register (fb) fb is a 16-bit register for fb relative addressing. 2.4 interrupt table register (intb) intb is a 20-bit register that indicates the starti ng address of an interrupt vector table. 2.5 program counter (pc) pc is 20 bits wide and indicates the addres s of the next instruction to be executed. 2.6 user stack pointer (usp) a nd interrupt stack pointer (isp) the stack pointers (sp), usp and isp, are each 16 bits wide. the u flag of flg is used to switch between usp and isp. 2.7 static base register (sb) sb is a 16-bit register for sb relative addressing. 2.8 flag register (flg) flg is an 11-bit register indicating the cpu state. 2.8.1 carry flag (c) the c flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 debug flag (d) the d flag is for debugging only. set it to 0. 2.8.3 zero flag (z) the z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 sign flag (s) the s flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 register bank select flag (b) register bank 0 is selected when the b flag is 0. regi ster bank 1 is selected when this flag is set to 1. 2.8.6 overflow flag (o) the o flag is set to 1 when an operation results in an overflow; otherwise to 0.
r8c/35c group 2. central processing unit (cpu) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 13 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. 2.8.7 interrupt enable flag (i) the i flag enables maskable interrupts. interrupts are disabled when the i flag is set to 0, and are enabled when the i flag is set to 1. the i flag is set to 0 when an interrupt request is acknowledged. 2.8.8 stack pointer select flag (u) isp is selected when the u flag is set to 0; usp is selected when the u flag is set to 1. the u flag is set to 0 when a hardware interrupt requ est is acknowledged or the int instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is 3 bits wide and assigns processor interrupt priority le vels from level 0 to level 7. if a requested interrupt has higher priori ty than ipl, the interrupt is enabled. 2.8.10 reserved bit if necessary, set to 0. when read, the content is undefined.
r8c/35c group 3. memory rej03b0283-0001 rev.0.01 sep. 01, 2009 page 14 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. 3. memory 3.1 r8c/35c group figure 3.1 is a memory map of r8c/35c group. the r8 c/35c group has a 1-mbyte a ddress space from addresses 00000h to fffffh. the internal rom (program rom) is allocated lower addresses, beginning with address 0ffffh. for example, a 32-kbyte internal rom area is allocated addresses 08000h to 0ffffh. the fixed interrupt vector table is allocated addresses 0ffdch to 0ffffh. the starting address of each interrupt routine is stored here. the internal rom (data flash) is allocated addresses 03000h to 03fffh. the internal ram is allocat ed higher addresses, beginning with address 00400h. for example, a 2.5-kbyte internal ram area is allocated addresses 00400h to 00dffh. the internal ram is used not only for data storage but also as a stack area when a subroutine is called or when an interrupt request is acknowledged. special function registers (sfrs) are allocated addres ses 00000h to 002ffh and 02c0 0h to 02fffh. peripheral function control registers are allocated here. all unallocated spaces within the sfrs are reserved and cannot be accessed by users. figure 3.1 memory map of r8c/35c group 0ffffh 0ffdch notes: 1. data flash indicates block a (1 kbyte), block b (1 kbyte), block c (1 kbyte), and block d (1 kbyte). 2. the blank areas are reserved and cannot be accessed by users. fffffh 0ffffh 0yyyyh 0xxxxh 00400h 002ffh 00000h internal rom (program rom) internal ram sfr (refer to 4. special function registers (sfrs) ) 02fffh 02c00h sfr (refer to 4. special function registers (sfrs) ) zzzzzh internal rom (program rom) 03fffh 03000h internal rom (data flash) (1) 0ffd8h reserved area undefined instruction overflow brk instruction address match single step watchdog timer, oscillation stop detection, voltage monitor address break (reserved) reset part number r5f21354cnfp, r5f21354cdfp r5f21355cnfp, r5f21355cdfp r5f21356cnfp, r5f21356cdfp r5f21357cnfp, r5f21357cdfp r5f21358cnfp, r5f21358cdfp r5f2135acnfp, r5f2135acdfp R5F2135CCNFP, r5f2135ccdfp internal rom internal ram size address 0yyyyh size address 0xxxxh address zzzzzh 16 kbytes 24 kbytes 32 kbytes 48 kbytes 64 kbytes 96 kbytes 128 kbytes 0c000h 0a000h 08000h 04000h 04000h 04000h 04000h 1.5 kbytes 2 kbytes 2.5 kbytes 4 kbytes 6 kbytes 8 kbytes 10 kbytes 009ffh 00bffh 00dffh 013ffh 01bffh 023ffh 02bffh ? ? ? ? 13fffh 1bfffh 23fffh
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 15 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. 4. special function registers (sfrs) an sfr (special function register) is a control register for a peripheral function. tables 4.1 to 4.12 list the special function registers and table 4.13 lists the id code areas and option function select area. table 4.1 sfr information (1) (1) x: undefined notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. the cwr bit in the rstfr register is set to 0 after power-on and voltage monitor 0 reset. hardware reset, software reset, or watchdog timer reset does not affect this bit. 3. the csproini bit in the ofs register is set to 0. 4. the lvdas bit in the ofs register is set to 1. 5. the lvdas bit in the ofs register is set to 0. address register symbol after reset 0000h 0001h 0002h 0003h 0004h processor mode register 0 pm0 00h 0005h processor mode register 1 pm1 00h 0006h system clock control register 0 cm0 00101000b 0007h system clock control register 1 cm1 00100000b 0008h module standby control register mstcr 00h 0009h system clock control register 3 cm3 00h 000ah protect register prcr 00h 000bh reset source determination register rstfr 0xxxxxxxb (2) 000ch oscillation stop detection register ocd 00000100b 000dh watchdog timer reset register wdtr xxh 000eh watchdog timer start register wdts xxh 000fh watchdog timer control register wdtc 00111111b 0010h 0011h 0012h 0013h 0014h 0015h high-speed on-chip oscillator control register 7 fra7 when shipping 0016h 0017h 0018h 0019h 001ah 001bh 001ch count source protection mode register cspr 00h 10000000b (3) 001dh 001eh 001fh 0020h 0021h 0022h 0023h high-speed on-chip oscillator control register 0 fra0 00h 0024h high-speed on-chip oscillator control register 1 fra1 when shipping 0025h high-speed on-chip oscillator control register 2 fra2 00h 0026h on-chip reference voltage control register ocvrefcr 00h 0027h 0028h clock prescaler reset flag cpsrf 00h 0029h high-speed on-chip oscillator control register 4 fra4 when shipping 002ah high-speed on-chip oscillator control register 5 fra5 when shipping 002bh high-speed on-chip oscillator control register 6 fra6 when shipping 002ch 002dh 002eh 002fh high-speed on-chip oscillator control register 3 fra3 when shipping 0030h voltage monitor circuit control register cmpa 00h 0031h voltage monitor circuit edge select register vcac 00h 0032h 0033h voltage detect register 1 vca1 00001000b 0034h voltage detect register 2 vca2 00h (4) 00100000b (5) 0035h 0036h voltage detection 1 level select register vd1ls 00000111b 0037h 0038h voltage monitor 0 circuit control register vw0c 1100x010b (4) 1100x011b (5) 0039h voltage monitor 1 circuit control register vw1c 10001010b
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 16 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.2 sfr information (2) (1) x: undefined notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. selectable by the iicsel bit in the ssuiicsr register. address register symbol after reset 003ah voltage monitor 2 circuit control register vw2c 10000010b 003bh 003ch 003dh 003eh 003fh 0040h 0041h flash memory ready interrupt control register fmrdyic xxxxx000b 0042h 0043h 0044h 0045h 0046h int4 interrupt control register int4ic xx00x000b 0047h timer rc interrupt control register trcic xxxxx000b 0048h timer rd0 interrupt control register trd0ic xxxxx000b 0049h timer rd1 interrupt control register trd1ic xxxxx000b 004ah timer re interrupt control register treic xxxxx000b 004bh uart2 transmit interrupt control register s2tic xxxxx000b 004ch uart2 receive interrupt control register s2ric xxxxx000b 004dh key input interrupt control register kupic xxxxx000b 004eh a/d conversion interrupt control register adic xxxxx000b 004fh ssu interrupt control register / iic bus interrupt control register (2) ssuic / iicic xxxxx000b 0050h 0051h uart0 transmit interrupt control register s0tic xxxxx000b 0052h uart0 receive interrupt control register s0ric xxxxx000b 0053h uart1 transmit interrupt control register s1tic xxxxx000b 0054h uart1 receive interrupt control register s1ric xxxxx000b 0055h int2 interrupt control register int2ic xx00x000b 0056h timer ra interrupt control register traic xxxxx000b 0057h 0058h timer rb interrupt control register trbic xxxxx000b 0059h int1 interrupt control register int1ic xx00x000b 005ah int3 interrupt control register int3ic xx00x000b 005bh 005ch 005dh int0 interrupt control register int0ic xx00x000b 005eh uart2 bus collision detection interrupt control register u2bcnic xxxxx000b 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h voltage monitor 1 interrupt control register vcmp1ic xxxxx000b 0073h voltage monitor 2 interrupt control register vcmp2ic xxxxx000b 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 17 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.3 sfr information (3) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 0080h dtc activation control register dtctl 00h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h dtc activation enable register 0 dtcen0 00h 0089h dtc activation enable register 1 dtcen1 00h 008ah dtc activation enable register 2 dtcen2 00h 008bh dtc activation enable register 3 dtcen3 00h 008ch dtc activation enable register 4 dtcen4 00h 008dh dtc activation enable register 5 dtcen5 00h 008eh dtc activation enable register 6 dtcen6 00h 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h uart0 transmit/receive mode register u0mr 00h 00a1h uart0 bit rate register u0brg xxh 00a2h uart0 transmit buffer register u0tb xxh 00a3h xxh 00a4h uart0 transmit/receive control register 0 u0c0 00001000b 00a5h uart0 transmit/receive control register 1 u0c1 00000010b 00a6h uart0 receive buffer register u0rb xxh 00a7h xxh 00a8h uart2 transmit/receive mode register u2mr 00h 00a9h uart2 bit rate register u2brg xxh 00aah uart2 transmit buffer register u2tb xxh 00abh xxh 00ach uart2 transmit/receive control register 0 u2c0 00001000b 00adh uart2 transmit/receive control register 1 u2c1 00000010b 00aeh uart2 receive buffer register u2rb xxh 00afh xxh 00b0h uart2 digital filter function select register urxdf 00h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh uart2 special mode register 5 u2smr5 00h 00bch uart2 special mode register 4 u2smr4 00h 00bdh uart2 special mode register 3 u2smr3 000x0x0xb 00beh uart2 special mode register 2 u2smr2 x0000000b 00bfh uart2 special mode register u2smr x0000000b
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 18 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.4 sfr information (4) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 00c0h a/d register 0 ad0 xxh 000000xxb 00c1h 00c2h a/d register 1 ad1 xxh 00c3h 000000xxb 00c4h a/d register 2 ad2 xxh 00c5h 000000xxb 00c6h a/d register 3 ad3 xxh 00c7h 000000xxb 00c8h a/d register 4 ad4 xxh 00c9h 000000xxb 00cah a/d register 5 ad5 xxh 00cbh 000000xxb 00cch a/d register 6 ad6 xxh 00cdh 000000xxb 00ceh a/d register 7 ad7 xxh 00cfh 000000xxb 00d0h 00d1h 00d2h 00d3h 00d4h a/d mode register admod 00h 00d5h a/d input select register adinsel 11000000b 00d6h a/d control register 0 adcon0 00h 00d7h a/d control register 1 adcon1 00h 00d8h d/a0 register da0 00h 00d9h d/a1 register da1 00h 00dah 00dbh 00dch d/a control register dacon 00h 00ddh 00deh 00dfh 00e0h port p0 register p0 xxh 00e1h port p1 register p1 xxh 00e2h port p0 direction register pd0 00h 00e3h port p1 direction register pd1 00h 00e4h port p2 register p2 xxh 00e5h port p3 register p3 xxh 00e6h port p2 direction register pd2 00h 00e7h port p3 direction register pd3 00h 00e8h port p4 register p4 xxh 00e9h port p5 register p5 xxh 00eah port p4 direction register pd4 00h 00ebh port p5 direction register pd5 00h 00ech port p6 register p6 xxh 00edh 00eeh port p6 direction register pd6 00h 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch 00fdh 00feh 00ffh
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 19 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.5 sfr information (5) (1) note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 0100h timer ra control register tracr 00h 0101h timer ra i/o control register traioc 00h 0102h timer ra mode register tramr 00h 0103h timer ra prescaler register trapre ffh 0104h timer ra register tra ffh 0105h lin control register 2 lincr2 00h 0106h lin control register lincr 00h 0107h lin status register linst 00h 0108h timer rb control register trbcr 00h 0109h timer rb one-shot control register trbocr 00h 010ah timer rb i/o control register trbioc 00h 010bh timer rb mode register trbmr 00h 010ch timer rb prescaler register trbpre ffh 010dh timer rb secondary register trbsc ffh 010eh timer rb primary register trbpr ffh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h timer re second data register / counter data register tresec 00h 0119h timer re minute data register / compare data register tremin 00h 011ah timer re hour data register trehr 00h 011bh timer re day of week data register trewk 00h 011ch timer re control register 1 trecr1 00h 011dh timer re control register 2 trecr2 00h 011eh timer re count source select register trecsr 00001000b 011fh 0120h timer rc mode register trcmr 01001000b 0121h timer rc control register 1 trccr1 00h 0122h timer rc interrupt enable register trcier 01110000b 0123h timer rc status register trcsr 01110000b 0124h timer rc i/o control register 0 trcior0 10001000b 0125h timer rc i/o control register 1 trcior1 10001000b 0126h timer rc counter trc 00h 0127h 00h 0128h timer rc general register a trcgra ffh 0129h ffh 012ah timer rc general register b trcgrb ffh 012bh ffh 012ch timer rc general register c trcgrc ffh 012dh ffh 012eh timer rc general register d trcgrd ffh 012fh ffh 0130h timer rc control register 2 trccr2 00011000b 0131h timer rc digital filter function select register trcdf 00h 0132h timer rc output master enable register trcoer 0 1111111b 0133h timer rc trigger control register trcadcr 00h 0134h 0135h timer rd control expansion register trdecr 00h 0136h timer rd trigger control register trdadcr 00h 0137h timer rd start register trdstr 11111100b 0138h timer rd mode register trdmr 00001110b 0139h timer rd pwm mode register trdpmr 10001000b 013ah timer rd function control register trdfcr 10000000b 013bh timer rd output master enable register 1 trdoer1 ffh 013ch timer rd output master enable register 2 trdoer2 0 1111111b 013dh timer rd output control register trdocr 00h 013eh timer rd digital filter function select register 0 trddf0 00h 013fh timer rd digital filter function select register 1 trddf1 00h
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 20 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.6 sfr information (6) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 0140h timer rd control register 0 trdcr0 00h 0141h timer rd i/o control register a0 trdiora0 10001000b 0142h timer rd i/o control register c0 trdiorc0 10001000b 0143h timer rd status register 0 trdsr0 11100000b 0144h timer rd interrupt enable register 0 trdier0 11100000b 0145h timer rd pwm mode output level control register 0 trdpocr0 1111 1000b 0146h timer rd counter 0 trd0 00h 0147h 00h 0148h timer rd general register a0 trdgra0 ffh 0149h ffh 014ah timer rd general register b0 trdgrb0 ffh 014bh ffh 014ch timer rd general register c0 trdgrc0 ffh 014dh ffh 014eh timer rd general register d0 trdgrd0 ffh 014fh ffh 0150h timer rd control register 1 trdcr1 00h 0151h timer rd i/o control register a1 trdiora1 10001000b 0152h timer rd i/o control register c1 trdiorc1 10001000b 0153h timer rd status register 1 trdsr1 11000000b 0154h timer rd interrupt enable register 1 trdier1 11100000b 0155h timer rd pwm mode output level control register 1 trdpocr1 1111 1000b 0156h timer rd counter 1 trd1 00h 0157h 00h 0158h timer rd general register a1 trdgra1 ffh 0159h ffh 015ah timer rd general register b1 trdgrb1 ffh 015bh ffh 015ch timer rd general register c1 trdgrc1 ffh 015dh ffh 015eh timer rd general register d1 trdgrd1 ffh 015fh ffh 0160h uart1 transmit/receive mode register u1mr 00h 0161h uart1 bit rate register u1brg xxh 0162h uart1 transmit buffer register u1tb xxh 0163h xxh 0164h uart1 transmit/receive control register 0 u1c0 00001000b 0165h uart1 transmit/receive control register 1 u1c1 00000010b 0166h uart1 receive buffer register u1rb xxh 0167h xxh 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 21 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.7 sfr information (7) (1) x: undefined notes: 1. the blank areas are reserved an d cannot be accessed by users. 2. selectable by the iicsel bit in the ssuiicsr register. address register symbol after reset 0180h timer ra pin select register trasr 00h 0181h timer rb/rc pin select register trbrcsr 00h 0182h timer rc pin select register 0 trcpsr0 00h 0183h timer rc pin select register 1 trcpsr1 00h 0184h timer rd pin select register 0 trdpsr0 00h 0185h timer rd pin select register 1 trdpsr1 00h 0186h timer pin select register timsr 00h 0187h 0188h uart0 pin select register u0sr 00h 0189h uart1 pin select register u1sr 00h 018ah uart2 pin select register 0 u2sr0 00h 018bh uart2 pin select register 1 u2sr1 00h 018ch ssu/iic pin select register ssuiicsr 00h 018dh 018eh int interrupt input pin select register intsr 00h 018fh i/o function pin select register pinsr 00h 0190h 0191h 0192h 0193h ss bit counter register ssbr 1111 1000b 0194h ss transmit data register l / iic bus transmit data register (2) sstdr / icdrt ffh 0195h ss transmit data register h sstdrh ffh 0196h ss receive data register l / iic bus receive data register (2) ssrdr / icdrr ffh 0197h ss receive data register h (2) ssrdrh ffh 0198h ss control register h / iic bus control register 1 (2) sscrh / iccr1 00h 0199h ss control register l / iic bus control register 2 (2) sscrl / iccr2 0 1111101b 019ah ss mode register / iic bus mode register (2) ssmr / icmr 00010000b / 00011000b 019bh ss enable register / iic bus interrupt enable register (2) sser / icier 00h 019ch ss status register / iic bus status register (2) sssr / icsr 00h / 0000x000b 019dh ss mode register 2 / slave address register (2) ssmr2 / sar 00h 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h flash memory status register fst 10000x00b 01b3h 01b4h flash memory control register 0 fmr0 00h 01b5h flash memory control register 1 fmr1 00h 01b6h flash memory control register 2 fmr2 00h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 22 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.8 sfr information (8) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 01c0h address match interrupt register 0 rmad0 xxh 01c1h xxh 01c2h 0000xxxxb 01c3h address match interrupt enable register 0 aier0 00h 01c4h address match interrupt register 1 rmad1 xxh 01c5h xxh 01c6h 0000xxxxb 01c7h address match interrupt enable register 1 aier1 00h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h pull-up control register 0 pur0 00h 01e1h pull-up control register 1 pur1 00h 01e2h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h 01e9h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h port p1 drive capacity control register p1drr 00h 01f1h port p2 drive capacity control register p2drr 00h 01f2h drive capacity control register 0 drr0 00h 01f3h drive capacity control register 1 drr1 00h 01f4h 01f5h input threshold control register 0 vlt0 00h 01f6h input threshold control register 1 vlt1 00h 01f7h 01f8h comparator b control register 0 intcmp 00h 01f9h 01fah external input enable register 0 inten 00h 01fbh external input enable register 1 inten1 00h 01fch int input filter select register 0 intf 00h 01fdh int input filter select register 1 intf1 00h 01feh key input enable register 0 kien 00h 01ffh
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 23 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.9 sfr information (9) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 2c00h dtc transfer vector area xxh 2c01h dtc transfer vector area xxh 2c02h dtc transfer vector area xxh 2c03h dtc transfer vector area xxh 2c04h dtc transfer vector area xxh 2c05h dtc transfer vector area xxh 2c06h dtc transfer vector area xxh 2c07h dtc transfer vector area xxh 2c08h dtc transfer vector area xxh 2c09h dtc transfer vector area xxh 2c0ah dtc transfer vector area xxh : dtc transfer vector area xxh : dtc transfer vector area xxh 2c3ah dtc transfer vector area xxh 2c3bh dtc transfer vector area xxh 2c3ch dtc transfer vector area xxh 2c3dh dtc transfer vector area xxh 2c3eh dtc transfer vector area xxh 2c3fh dtc transfer vector area xxh 2c40h dtc control data 0 dtcd0 xxh 2c41h xxh 2c42h xxh 2c43h xxh 2c44h xxh 2c45h xxh 2c46h xxh 2c47h xxh 2c48h dtc control data 1 dtcd1 xxh 2c49h xxh 2c4ah xxh 2c4bh xxh 2c4ch xxh 2c4dh xxh 2c4eh xxh 2c4fh xxh 2c50h dtc control data 2 dtcd2 xxh 2c51h xxh 2c52h xxh 2c53h xxh 2c54h xxh 2c55h xxh 2c56h xxh 2c57h xxh 2c58h dtc control data 3 dtcd3 xxh 2c59h xxh 2c5ah xxh 2c5bh xxh 2c5ch xxh 2c5dh xxh 2c5eh xxh 2c5fh xxh 2c60h dtc control data 4 dtcd4 xxh 2c61h xxh 2c62h xxh 2c63h xxh 2c64h xxh 2c65h xxh 2c66h xxh 2c67h xxh 2c68h dtc control data 5 dtcd5 xxh 2c69h xxh 2c6ah xxh 2c6bh xxh 2c6ch xxh 2c6dh xxh 2c6eh xxh 2c6fh xxh
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 24 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.10 sfr information (10) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 2c70h dtc control data 6 dtcd6 xxh 2c71h xxh 2c72h xxh 2c73h xxh 2c74h xxh 2c75h xxh 2c76h xxh 2c77h xxh 2c78h dtc control data 7 dtcd7 xxh 2c79h xxh 2c7ah xxh 2c7bh xxh 2c7ch xxh 2c7dh xxh 2c7eh xxh 2c7fh xxh 2c80h dtc control data 8 dtcd8 xxh 2c81h xxh 2c82h xxh 2c83h xxh 2c84h xxh 2c85h xxh 2c86h xxh 2c87h xxh 2c88h dtc control data 9 dtcd9 xxh 2c89h xxh 2c8ah xxh 2c8bh xxh 2c8ch xxh 2c8dh xxh 2c8eh xxh 2c8fh xxh 2c90h dtc control data 10 dtcd10 xxh 2c91h xxh 2c92h xxh 2c93h xxh 2c94h xxh 2c95h xxh 2c96h xxh 2c97h xxh 2c98h dtc control data 11 dtcd11 xxh 2c99h xxh 2c9ah xxh 2c9bh xxh 2c9ch xxh 2c9dh xxh 2c9eh xxh 2c9fh xxh 2ca0h dtc control data 12 dtcd12 xxh 2ca1h xxh 2ca2h xxh 2ca3h xxh 2ca4h xxh 2ca5h xxh 2ca6h xxh 2ca7h xxh 2ca8h dtc control data 13 dtcd13 xxh 2ca9h xxh 2caah xxh 2cabh xxh 2cach xxh 2cadh xxh 2caeh xxh 2cafh xxh
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 25 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.11 sfr information (11) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. address register symbol after reset 2cb0h dtc control data 14 dtcd14 xxh 2cb1h xxh 2cb2h xxh 2cb3h xxh 2cb4h xxh 2cb5h xxh 2cb6h xxh 2cb7h xxh 2cb8h dtc control data 15 dtcd15 xxh 2cb9h xxh 2cbah xxh 2cbbh xxh 2cbch xxh 2cbdh xxh 2cbeh xxh 2cbfh xxh 2cc0h dtc control data 16 dtcd16 xxh 2cc1h xxh 2cc2h xxh 2cc3h xxh 2cc4h xxh 2cc5h xxh 2cc6h xxh 2cc7h xxh 2cc8h dtc control data 17 dtcd17 xxh 2cc9h xxh 2ccah xxh 2ccbh xxh 2ccch xxh 2ccdh xxh 2cceh xxh 2ccfh xxh 2cd0h dtc control data 18 dtcd18 xxh 2cd1h xxh 2cd2h xxh 2cd3h xxh 2cd4h xxh 2cd5h xxh 2cd6h xxh 2cd7h xxh 2cd8h dtc control data 19 dtcd19 xxh 2cd9h xxh 2cdah xxh 2cdbh xxh 2cdch xxh 2cddh xxh 2cdeh xxh 2cdfh xxh 2ce0h dtc control data 20 dtcd20 xxh 2ce1h xxh 2ce2h xxh 2ce3h xxh 2ce4h xxh 2ce5h xxh 2ce6h xxh 2ce7h xxh 2ce8h dtc control data 21 dtcd21 xxh 2ce9h xxh 2ceah xxh 2cebh xxh 2cech xxh 2cedh xxh 2ceeh xxh 2cefh xxh
r8c/35c group 4. special function registers (sfrs) rej03b0283-0001 rev.0.01 sep. 01, 2009 page 26 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. table 4.12 sfr information (12) (1) x: undefined note: 1. the blank areas are reserved an d cannot be accessed by users. table 4.13 id code areas and option function select area notes: 1. the option function select area is allocated in the flash memory , not in the sfrs. set appropriate values as rom data by a pr ogram. do not write additions to the option function select area. if the block including the option function select area is erased, th e option function select area is set to ffh. when blank products are shipped, the option function select area is set to ffh. it is set to the written value after written by the user. when factory-programming products are shipped, the value of the option function select area is the value programmed by the user . 2. the id code areas are allocated in the flash memory, not in the sfrs. set appropriate values as rom data by a program. do not write additions to the id code areas. if the block includ ing the id code areas is erased, the id code areas are set to f fh. when blank products are shipped, the id code areas are set to ffh. they are set to the written value after written by the user. when factory-programming products are shipped, the value of the id code areas is the value programmed by the user. address register symbol after reset 2cf0h dtc control data 22 dtcd22 xxh 2cf1h xxh 2cf2h xxh 2cf3h xxh 2cf4h xxh 2cf5h xxh 2cf6h xxh 2cf7h xxh 2cf8h dtc control data 23 dtcd23 xxh 2cf9h xxh 2cfah xxh 2cfbh xxh 2cfch xxh 2cfdh xxh 2cfeh xxh 2cffh xxh 2d00h : 2fffh address area name symbol after reset : ffdbh option function select register 2 ofs2 (note 1) : ffdfh id1 (note 2) : ffe3h id2 (note 2) : ffebh id3 (note 2) : ffefh id4 (note 2) : fff3h id5 (note 2) : fff7h id6 (note 2) : fffbh id7 (note 2) : ffffh option function select register ofs (note 1)
r8c/35c group package dimensions rej03b0283-0001 rev.0.01 sep. 01, 2009 page 27 of 27 under development preliminary specification specifications in this manual are tentative and subject to change. package dimensions diagrams showing the latest package dimensions and mounti ng information are available in the ?packages? section of the renesas technology website. include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. detail f c a l1 l a2 a1 index mark x y * 3 * 1 * 2 f 39 27 13 1 40 52 26 14 zd ze d hd e he bp terminal cross section c bp c1 b1 previous code jeita package code renesas code plqp0052ja-a 52p6a-a mass[typ.] 0.3g p-lqfp52-10x10-0.65 1.0 0.125 0.30 1.1 1.1 0.13 0.20 0.145 0.09 0.37 0.32 0.27 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.65 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 e
c - 1 revision history r8c/35c grou p shortsheet rev. date description page summary 0.01 sep. 01, 2009 ? first edition issued all trademarks and registered trademarks are the property of thei r respective owners. r8c/35c group shortsheet revision history
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