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integrated silicon solution, inc. www.issi.com 1-800-379-4774 1 rev. 00b 02/10/2010 copyright ? 2010 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and before placing orders for products. is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls 128k x 8 high-speed cmos static ram features high speed: ( is63/64wv1288dall/dbll) ? high-speed access time: 8, 10, 12, 20 ns ? low active power: 135 mw (typical) ? low standby power: 12 w (typical) cmos standby low power : ( is63/64wv1288dals/dbls) ? high-speed access time: 25, 35 ns ? low active power: 55 mw (typical) ? low standby power: 12 w (typical) cmos standby ? single power supply v d d 1.65v to 2.2v (is63wv1288daxx) v d d 2.4v to 3.6v (is63/64wv1288dbxx) ? multiple center power and ground pins for greater noise immunity ? easy memory expansion with ce and oe options ? ce power-down ? fully static operation: no clock or refresh required ? ttl compatible inputs and outputs ? lead-free available description the issi is63/64wv1288dxxx is a very high-speed, low power, 131,072-word by 8-bit cmos static ram. the is63/64wv1288dbll is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices. when ce is high (deselected), the device assumes a standby mode at which the power dissipation can be re - duced down to 25 w (typical) with cmos input levels. the is63/64wv1288dbll operates from a single v d d power supply. the is63/64wv1288dxxx is available in 32-pin tsop (type ii), 32-pin stsop (type i), 48-ball minibga (6mm x 8mm), and 32-pin soj (300-mil) pack- ages. functional block diagram a0-a16 ce oe we 128k x 8 memory array decoder column i/o control circuit gnd vdd i/o data circuit i/o0-i/o7 preliminary information february 2010
2 integrated silicon solution, inc. www.issi.com rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls pin descriptions a0-a16 address inputs ce chip enable input oe output enable input we write enable input i/o0-i/o7 bidirectional ports v d d power gnd ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 ce i/o0 i/o1 vdd gnd i/o2 i/o3 we a4 a5 a6 a7 a16 a15 a14 a13 oe i/o7 i/o6 gnd vdd i/o5 i/o4 a12 a11 a10 a9 a8 pin configuration 32-pin tsop (type ii) (t) 32-pin stsop (type i) (h) pin configuration 48-mini bga (b) (6 mm x 8 mm) pin configuration 32-pin soj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a0 a1 a2 a3 ce i/o0 i/o1 vdd gnd i/o2 i/o3 we a4 a5 a6 a7 a16 a15 a14 a13 oe i/o7 i/o6 gnd vdd i/o5 i/o4 a12 a11 a10 a9 a8 1 2 3 4 5 6 a b c d e f g h nc oe a2 a6 a7 nc i/o 0 nc a1 a5 ce i/o 7 i/o 1 nc a0 a4 nc i/o 6 gnd nc nc a3 nc v dd v dd nc nc nc nc gnd i/o 2 nc a14 a11 i/o 4 i/o 5 i/o 3 nc a15 a12 we a8 nc a10 a16 a13 a9 nc
integrated silicon solution, inc. www.issi.com 3 rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls truth table m ode we ce oe i/o operation v d d current not selected x h x high-z i s b 1 , i s b 2 (power-down) output disabled h l h high-z i c c 1 , i c c 2 read h l l d o u t i c c 1 , i c c 2 write l l x d i n i c c 1 , i c c 2 absolute maximum ratings (1) symbol parameter value unit v t e r m terminal voltage with respect to gnd C0.5 to v d d +0.5 v t s t g storage temperature C65 to +150 c p t power dissipation 1.5 w v d d v d d related to gnd -0.2 to +3.9 v note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
4 integrated silicon solution, inc. www.issi.com rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls ac test loads figure 1. r1 5 pf including jig and scope r2 output vtm figure 2. z o = 50? vdd/2 50? output 30 pf including jig and scope ac test conditions p arameter unit unit unit (2.4v-3.6v) (3.3v + 5%) (1.65v-2.2v) input pulse level 0.4v to v d d - 0.3v 0.4v to v d d - 0.3v 0.4v to v d d - 0.3v input rise and fall times 1v/ ns 1v/ ns 1v/ ns input and output timing vdd /2 vdd + 0.05 0.9v and reference level (v ref ) 2 output load see figures 1 and 2 see figures 1 and 2 see figures 1 and 2 r1 ( ? ) 1909 317 13500 r2 ( ? ) 1105 351 10800 v t m (v) 3.0v 3.3v 1.8v
integrated silicon solution, inc. www.issi.com 5 rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls dc electrical characteristics (over operating range) v d d = 2.4v-3.6v symbol parameter test conditions min. max. unit v o h output high voltage v d d = min., i o h = C1.0 ma 1.8 v v o l output low voltage v d d = min., i o l = 1.0 ma 0.4 v v i h input high voltage 2.0 v d d + 0.3 v v i l input low voltage (1) C0.3 0.8 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v a c (pulse width < 10 ns). not 100% tested. dc electrical characteristics (over operating range) v d d = 3.3v + 5% symbol parameter test conditions min. max. unit v o h output high voltage v d d = min., i o h = C4.0 ma 2.4 v v o l output low voltage v d d = min., i o l = 8.0 ma 0.4 v v i h input high voltage 2 v d d + 0.3 v v i l input low voltage (1) C0.3 0.8 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v a c (pulse width < 10 ns). not 100% tested. dc electrical characteristics (over operating range) v d d = 1.65v-2.2v symbol parameter test conditions v d d min. max. unit v o h output high voltage i o h = -0.1 ma 1.65-2.2v 1.4 v v o l output low voltage i o l = 0.1 ma 1.65-2.2v 0.2 v v i h input high voltage 1.65-2.2v 1.4 v d d + 0.2 v v i l (1) input low voltage 1.65-2.2v C0.2 0.4 v i l i input leakage gnd v i n v d d C1 1 a i l o output leakage gnd v o u t v d d , outputs disabled C1 1 a note: 1. v i l (min.) = C0.3v dc; v i l (min.) = C2.0v ac (pulse width < 10 ns). not 100% tested. v i h (max.) = v d d + 0.3v dc; v i h (max.) = v d d + 2.0v a c (pulse width < 10 ns). not 100% tested.
6 integrated silicon solution, inc. www.issi.com rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls operating range ( v d d ) (is63wv1288dbll) (1) ra nge ambient temperature v d d (8 n s ) 1 v d d (10 n s ) 1 commercial 0c to +70c 3.3v + 5% 2.4v-3.6v industrial C40c to +85c 3.3v + 5% 2.4v-3.6v note: 1. when operated in the range of 2.4v-3.6v, the device meets 10ns. when operated in the range of 3.3v + 5%, the device meets 8ns. operating range ( v d d ) (is64wv1288dbll) (2) ra nge ambient temperature v d d (8 n s ) 2 v d d (10 n s ) 2 automotive C40c to +125c 3.3v + 5% 2.4v-3.6v note: 2. when operated in the range of 2.4v-3.6v, the device meets 10ns. when operated in the range of 3.3v + 5%, the device meets 8ns. high speed (is63wv1288dall/dbll) operating range ( v d d ) (is63wv1288dall) ran ge ambient temperature v d d s peed commercial 0c to +70c 1.65v-2.2v 20ns industrial C40c to +85c 1.65v-2.2v 20ns automotive C40c to +125c 1.65v-2.2v 20ns power supply characteristics (1) (over operating range) -8 -10 -12 -20 symbol parameter test conditions min. max. min. max. min. max. min. max. unit i c c v d d dynamic operating v d d = max., com. 65 50 45 40 ma supply current i o u t = 0 ma, f = f m a x ind. 70 55 50 45 ce = v i l auto. (3) 65 55 50 v i n v d d C 0.3v, or typ. (2) 45 45 v i n 0.4v i s b 2 cmos standby v d d = max., com. 40 40 40 40 a current (cmos inputs) ce v d d C 0.2v, ind. 55 55 55 55 v i n v d d C 0.2v, or auto. 90 90 90 v i n 0.2v , f = 0 typ. (2) 4 4 note: 1. at f = f m a x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested. 3. for automotive grade at 15ns, typ. icc = 38ma, not 100% tested.
integrated silicon solution, inc. www.issi.com 7 rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls power supply characteristics (1) (over operating range) -25 -35 -45 symbol parameter test conditions min. max. min. max. min. max. unit i c c v d d dynamic operating v d d = max., com. 15 15 12 ma supply current i o u t = 0 ma, f = f m a x ind. 20 20 18 ce = v i l auto. 30 30 25 v i n v d d C 0.3v, or typ. (2) 18 v i n 0.4v i s b 2 cmos standby v d d = max., com. 40 40 40 a current (cmos inputs) ce v d d C 0.2v, ind. 50 50 50 v i n v d d C 0.2v, or auto. 75 75 75 v i n 0.2v , f = 0 typ. (2) 4 note: 1. at f = f m a x , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested. operating range ( v d d ) (is63wv1288dbls) ra nge ambient temperature v d d (35 n s ) commercial 0c to +70c 2.4v-3.6v industrial C40c to +85c 2.4v-3.6v low power (is63wv1288dals/dbls) operating range ( v d d ) (is63wv1288dals) ran ge ambient temperature v d d speed commercial 0c to +70c 1.65v-2.2v 45ns industrial C40c to +85c 1.65v-2.2v 45ns automotive C40c to +125c 1.65v-2.2v 55ns operating range ( v d d ) (is64wv1288dbls) r ange ambient temperature v d d (35 n s ) automotive C40c to +125c 2.4v-3.6v
8 integrated silicon solution, inc. www.issi.com rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls read cycle switching characteristics (1) (over operating range) -8 ns -10 ns -12 ns symbol parameter min. max. min. max. min. max. unit t r c read cycle time 8 10 12 ns t a a address access time 8 10 12 ns t o h a output hold time 2 2 2 ns t a c e ce access time 8 10 12 ns t d o e oe access time 4 5 6 ns t l z o e (2) oe to low-z output 0 0 0 ns t h z o e (2) oe to high-z output 0 4 0 5 0 6 ns t l z c e (2) ce to low-z output 3 3 3 ns t h z c e (2) ce to high-z output 0 4 0 5 0 6 ns t p u ce to power up time 0 0 0 ns t p d ce to power down time 8 10 12 ns notes: 1. test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v load- ing specifed in figure 1. 2. tested with the loading specifed in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. read cycle switching characteristics (1) (over operating range) -20 ns -25 ns -35 ns -45 ns symbol parameter min. max. min. max. min. max. min. max. unit t r c read cycle time 20 25 35 45 ns t a a address access time 20 25 35 45 ns t o h a output hold time 2.5 6 8 10 ns t a c e ce access time 20 25 35 45 ns t d o e oe access time 8 12 15 20 ns t h z o e (2) oe to high-z output 0 8 0 8 0 10 0 15 ns t l z o e (2) oe to low-z output 0 0 0 0 ns t h z c e (2 ce to high-z output 0 8 0 8 0 10 0 15 ns t l z c e (2) ce to low-z output 3 10 10 10 ns notes: 1. test conditions assume signal transition times of 1.5 ns or less, timing reference levels of 1.25v, input pulse levels of 0.4v to v d d -0.3v and output loading specifed in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. not 100% tested.
integrated silicon solution, inc. www.issi.com 9 rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls data valid read1.eps previous data valid t aa t oha t oha t rc d out address t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid ce_rd2.eps address oe ce d out t hzce read cycle no. 2 (1,3) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe, ce = v i l . 3. address is valid prior to or coincident with ce low transitions. ac waveforms read cycle no. 1 (1,2)
10 integrated silicon solution, inc. www.issi.com rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls write cycle switching characteristics (1,3) (over operating range) -8 ns -10 ns -12 ns symbol parameter min. max. min. max. min. max. unit t w c write cycle time 8 10 12 ns t s c e ce to write end 7 7 8 ns t a w address setup time to 8 8 8 ns write end t h a address hold from 0 0 0 ns write end t s a address setup time 0 0 0 ns t p w e 1 (1) we pulse width (oe high) 7 7 8 ns t p w e 2 (2) we pulse width (oe low) 8 10 12 ns t s d data setup to write end 5 5 6 ns t h d data hold from write end 0 0 0 ns t h z w e (2) we low to high-z output 4 5 6 ns t l z w e (2) we high to low-z output 3 3 3 ns notes: 1. test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v and output loading specifed in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. write cycle switching characteristics (1,2) (over operating range) -20 ns -25 ns -35 ns -45ns symbol parameter min. max. min. max. min. max. min. max. unit t w c write cycle time 20 25 35 45 ns t s c e ce to write end 12 18 25 35 ns t a w address setup time 12 15 25 35 ns to write end t h a address hold from write end 0 0 0 0 ns t s a address setup time 0 0 0 0 ns t p w e 1 we pulse width (oe = high) 12 18 30 35 ns t p w e 2 we pulse width (oe = low) 17 20 30 35 ns t s d data setup to write end 9 12 15 20 ns t h d data hold from write end 0 0 0 0 ns t h z w e (3) we low to high-z output 9 12 20 20 ns t l z w e (3) we high to low-z output 3 5 5 5 ns notes: 1. tes t conditions for is61wv6416ll assume signal transition times of 1.5ns or less, timing reference levels of 1.25v, input pulse levels of 0.4v to v d d -0.3v and output loading specifed in figure 1a. 2. tested with the load in figure 1b. transition is measured 500 mv from steady-state voltage. not 100% tested. 3. the internal write time is defned by the overlap of ce low and ub or lb, and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write.
integrated silicon solution, inc. www.issi.com 11 rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls ac waveforms write cycle no. 1 (1,2 (ce controlled, oe = high or low) data undefined t wc valid address t sce t pwe1 t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in data in valid t lzwe t sd ce_wr1.eps
12 integrated silicon solution, inc. www.issi.com rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls ac waveforms write cycle no. 2 (1) (we controlled, oe = high during write cycle) write cycle no. 3 (we controlled: oe is low during write cycle) notes: 1. the internal write time is defned by the overlap of ce low and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that terminates the write. 2. i/o will assume the high-z state if oe > v i h . data undefined low t wc valid address t pwe1 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr2.eps data undefined t wc valid address low low t pwe2 t aw t ha high-z t hd t sa t hzwe address ce we d out d in oe data in valid t lzwe t sd ce_wr3.eps
integrated silicon solution, inc. www.issi.com 13 rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls data retention waveform (ce controlled) high speed (is63/4wv1288dall/dbll) data retention switching characteristics (2.4v-3.6v) symbol parameter test condition options min. typ. (1) max. unit v d r v d d for data retention see data retention waveform 2.0 3.6 v i d r data retention current v d d = 2.0v, ce v d d C 0.2v com. 4 40 a ind. 55 auto. 90 t s d r data retention setup time see data retention waveform 0 ns t r d r recovery time see data retention waveform t r c ns note 1: typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode data retention switching characteristics (1.65v-2.2v) symbol parameter test condition options min. typ. (1) max. unit v d r v d d for data retention see data retention waveform 1.2 3.6 v i d r data retention current v d d = 1.2v, ce v d d C 0.2v com. 4 40 a ind. 55 auto. 90 t s d r data retention setup time see data retention waveform 0 ns t r d r recovery time see data retention waveform t r c ns note 1: typical values are measured at v d d = 1.8v, t a = 25 o c and not 100% tested.
14 integrated silicon solution, inc. www.issi.com rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls data retention waveform (ce controlled) low power (is63/4wv1288dals/dbls) data retention switching characteristics (2.4v-3.6v) symbol parameter test condition options min. typ. (1) max. unit v d r v d d for data retention see data retention waveform 2.0 3.6 v i d r data retention current v d d = 2.0v, ce v d d C 0.2v com. 4 40 a ind. 50 auto. 75 t s d r data retention setup time see data retention waveform 0 ns t r d r recovery time see data retention waveform t r c ns note 1: typical values are measured at v d d = 3.0v, t a = 25 o c and not 100% tested. v dd ce v dd - 0.2v t sdr t rdr v dr ce gnd data retention mode data retention switching characteristics (1.65v-2.2v) symbol parameter test condition options min. typ. (1) max. unit v d r v d d for data retention see data retention waveform 1.2 3.6 v i d r data retention current v d d = 1.2v, ce v d d C 0.2v com. 4 40 a ind. 50 auto. 75 t s d r data retention setup time see data retention waveform 0 ns t r d r recovery time see data retention waveform t r c ns note 1: typical values are measured at v d d = 1.8v, t a = 25 o c and not 100% tested.
integrated silicon solution, inc. www.issi.com 15 rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls ordering information industrial range: C40c to +85c speed (ns) order part no. packag e 8 is63wv1288dbll-8ti 32-pin tsop (type ii) is63wv1288dbll-8tli 32-pin tsop (type ii), lead-free is63wv1288dbll-8hi stsop (type i) (8mm x13.4mm) is63wv1288dbll-8hli stsop (type i) (8mm x13.4mm), lead-free is63wv1288dbll-8ji 32-pin soj (300-mil) is63wv1288dbll-8jli 32-pin soj (300-mil), lead-free 10 is63wv1288dbll-10ti 32-pin tsop (type ii) is63wv1288dbll-10tli 32-pin tsop (type ii), lead-free IS63WV1288DBLL-10HI stsop (type i) (8mm x13.4mm) is63wv1288dbll-10hli stsop (type i) (8mm x13.4mm), lead-free is63wv1288dbll-10ji 32-pin soj (300-mil) is63wv1288dbll-10jli 32-pin soj (300-mil), lead-free automotive range (a3): C40c to +125c s peed (ns) order part no. packa ge 10(8*) is64wv1288dbll-10ta3 32-pin tsop (type ii) is64wv1288dbll-10tla3 32-pin tsop (type ii), lead-free is64wv1288dbll-10ha3 stsop (type i) (8mm x13.4mm) is64wv1288dbll-10hla3 stsop (type i) (8mm x13.4mm), lead-free note: 1. speed = 8ns for v d d = 3.3v + 5%. speed = 10ns for v d d = 2.4v-3.6v.
16 integrated silicon solution, inc. www.issi.com rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls
integrated silicon solution, inc. www.issi.com 17 rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls
18 integrated silicon solution, inc. www.issi.com rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls
integrated silicon solution, inc. www.issi.com 19 rev. 00b 02/10/2010 is63wv1288dall/dals is63wv1288dbll/dbls is64wv1288dbll/dbls 2. reference document : jedec mo-207 1. controlling dimension : mm . note : 08/12/2008 package outline

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