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scd5028-1 rev j features ? radiation performance - total dose: 1mrad (si) - sel immune: >100mev-cm 2 /mg ? +5vdc power only ? programmable: by using a few non critic al external resistors and capacitors - resolution: 10, 12, 14 or 16 bit resolution - bandwidth - tracking rate ? low power: +5v @ 20 ma typ ? 45 to 30,000 hz ca rrier frequency range ? accuracy to 5.3 arc minutes ? differential instrument am plifiers resolver input ? -55 to +125c operating temperature ? digital interface logic voltage of 3.3v to 5v ? packaging ? hermetic - 52 pin ceramic quad flat package (cqfp), .956" sq x .10"ht max - weight: 5.0g max ? evaluation board available for test and evalua tion. see aeroflex app lication note an5028-1 ? standard microcircuit drawing (smd): 5962-0423501/02 note: aeroflex plainview does not currently have a dscc certified radiation hardened assurance program act5028b 16-bit monolithic tracking standard products rad tolerant resolver-to-digital converter applications this single chip resolver-to-digital conv erter (rdc) is used in shaft angle cont rol systems, and is suitable for space or other radiation environments that require >1mrad (si) to tal dose tolerance. the part is latchup free in heavy ion environments (e.g., geosynchronous orbits) and is estima ted to experience seu induce d errors of less than 15 minutes of arc at a rate of 1 per device per 2 years when operating dynamically. theory of operation the act5028b converter is a single cmos type ii tracki ng resolver to digital conv erter monolithic chip. it is implemented using precision analog ci rcuitry and digital logic. for flexib ility, the converter bandwidth, dynamics and velocity scaling are externally set with passive co mponents. refer to figure 1, act5028b block diagram. the converter is powered from +5vdc. analog signals ar e referenced to signal ground, which is nominally v cc /2. the converter consists of three main sections; the analog control transfor mer (ct), the analog error processor (ep) and the digital logic interface. the ct has two analog resolver inputs (sin and cos) that are buffered by high impedance input instrumentation type amplifiers and the 16 bit digital word which represents the ou tput digital angle. the ct performs the ratiometric trigonometric computation of: sin(a) sin(wt) cos(b) ? cos(a) sin(wt) sin(b) = sin(a-b) sin(wt) utilizing amplifiers, switches, logic a nd resistors in precision ratios. ?a? represents the resolver angle, ?b? represents the digital angle and sin(wt) repres ents the resolver reference carrier frequency. the error processor is configured as a critically damped type ii loop. the ac error, sin (a-b) sin (wt) is full wave demodulated using the reference squared off as its drive. this dc error is integr ated in an analog integrator yielding a velocity voltage which in turn drives a voltage controll ed oscillator (vco). this vco is an incremental integrator (constant voltage input to position rate output) which, together with the veloci ty integrator, forms a type ii loop. a lead is inserted to stabilize the loop and a lag is insert ed at a higher frequency to attenuate the carrier frequency ripple. the error processor drives the 16 bit digital output until it nulls out. then angle ?a? = ?b?. the digital output equals angle input to the accuracy of the precision control transformer. the various error processor settings are done with external resistors and capacitors so that the converter loop dynamics can be easily controlled by the user. the digital logic interface has a separate power line, vl i / o that sets the interface logic 1 level. it can be set anywhere from +3v to the +5v power supply. september 30, 2008 www.aeroflex.com/rdc
2 scd5028-1 rev j 9/30/08 aeroflex plainview - + - + g=2 - + g=2 - + error amp +2.25v internal analog ground hysteresis +sin -sin +cos -cos vl i / o data load bit 1 msb bit 16 lsb enable inh sc1 sc2 busy +5v agnd gnd d gnd +5va +5vd ac1 bpf2 ac2 bpf1 demod1 demod2 intin2 intin1 int1 int2 vcoin +ref -ref r5 +5v r6 c4 +2.5v r4 r4 c1 c1 r1 r1 c2 c3 +vel r2 -vel c3 c2 r2 r3 output data latch differential transformer control figure 1 ? act5028b block diagram act5028b signal gnd demod comp ripple 16 bit up/down counter vco & timing 2 1 28 44 45 47 48 3,19,23 26 4 27 50 49 22 21 25 24 52 14 13 15 16 11 12 17 18 6 8 9 10 5 51 cw/ccw
3 scd5028-1 rev j 9/30/08 aeroflex plainview pin descriptions signal direction pin signal description +sin -sin input 22 21 analog sine input from synchro or resolver. 1.3vrms nominal +cos -cos input 25 24 analog cosine input from synchro or resolver. 1.3vrms nominal +ref -ref input 11 12 analog reference input bit 1 (msb) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 (lsb) bidir 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43 44 digital angle data. parallel format . natural binary positive logic. bit 1, most significant bit = 180, bit 2 = 90, bit 3 = 45 and so on. in the 10 bit mode, bit 10 is the lsb. bits 11-16 are 0s. in the 12 bit mode, bit 12 is the lsb. bits 13-16 are 0s. in the 14 bit mode, bit 14 is the lsb. bits 15-16 are 0s. in the 16 bit mode, bit 16 is the lsb. sc1 sc2 input 49 48 digital input. sets the resolution. sc1 sc2 resolution 0 0 10 bit 0 1 12 bit 1 0 14 bit 1 1 16 bit enable * input 45 logic 0 enables digital angle output. otherwise it is high impedance. inh * input 47 logic 0 freezes the digital angle ou tput so that it can be safely read. data load * input 1 logic 0 enables the digital angle lines to be inputs to preset the angle. logic 1 is for normal digital angle output. busy output 50 a logic 1 pulse when th e digital angle changes by 1 lsb. cw/ccw output 51 for turns counting. logic 1 = counting up (cw), logic 0 = counting down (ccw). ripple * output 52 ripple clock for turns counting. a logic 0 pulse = a 0 transition in either direction. ac1 ac2 output 14 13 differential ac error output bpf1 bpf2 input 16 15 differential ac erro r input to demodulator demod1 demod2 output 17 18 differential dc error output intin1 intin2 input 8 6 differential dc input to differential velocity integrator int1 int 2 output 9 10 differential velocity output vcoin input 5 input to voltage controlled oscillator v cc v dd power 4 27 analog power in digital power in a gnd d gnd power 3, 19, 23 26 analog power ground digital power ground vl i / o power 2 digital input/output dc power supply. sets logic 1 level. +3v to +5v * indicates active low signal
4 scd5028-1 rev j 9/30/08 aeroflex plainview absolute maximum ratings * parameter va l u e operating temperature -55?c to +125?c storage temperature -65?c to +150?c positive power supply voltage (v cc = v dd ) -0.5 v to +7.0 v analog output current (output shorted to gnd) 32 ma max digital output current (output shorted to gnd) 18.6 ma max analog input voltage range -0.3 v to + (v cc +.3 v) digital input voltage range -0.3 v to + (v dd +.3 v) thermal resistance ? jc specification 1.25?c/w maximum junction temperature 135c * stresses greater than those listed under absolute maximum ratings may ca use permanent damage to the device. these are stress ratings only; func tional operation beyond these operating conditions is not recommended and extended exposure beyond these operating conditions may effect device reliability. operating conditions (t a = -55c to +125c) power supply parameter min typ max unit v dd = v cc operating voltage 4.5 5 5.5 v dc i dd + i cc operating current - 20 35 ma vl i / o interface voltage 3 3.3, 5 5.5 v dc electrical ch aracteristics 2,5,6 (t a = -55c to +125c) parameter conditions min typ max units accuracy 4 add 1 lsb for total error - 2 5 minutes repeatability - - 1 lsb resolution per lsb 10 bit mode 0.35 - - degrees 21.1 - - minutes 12 bit mode 0.09 - - degrees 5.27 - - minutes 14 bit mode 0.022 - - degrees 1.32 - - minutes 16 bit mode 0.0055 - - degrees 0.33 - - minutes max tracking rate sc1 sc2 bits used 10 bit mode 0 0 b1 - b10 1024 - - rps 12 bit mode 0 1 b1 - b12 256 - - rps 14 bit mode 1 0 b1 - b14 64 - - rps 16 bit mode 1 1 b1 - b16 16 - - rps vco frequency 1.05 - - mhz
5 scd5028-1 rev j 9/30/08 aeroflex plainview electrical speci fications 2,5,6 (t a = -55c to +125c) analog signal inputs sym parameter min typ max units sin, cos, ref, vcoin, intin1, intin2, bpf1, bpf2 v sin , v cos , v ref voltage measurement made between inputs 1.0 1.3 1.5 v rms f ref frequency 1 45 - 30k hz impedance 2.5 - - m capacitance 3 - 5 15 pf dc bias on -sin, -cos - v cc /2 - v dc bias current +25c -100 - +100 na +125c -1000 - +1000 na digital inputs enable , dataload sc2, sc1, inh see note 3 v il logic low 3 --0.8v dc v ih logic high 3 2--v dc i in leakage current +25c -200 - +200 na +125c -2000 - +2000 na impedance 2.5 - - m capacitance 3 - 5 15 pf digital outputs busy, ripple cw/ccw v ol logic low @ 1.6ma - - 0.3 v dc v oh logic high @ -1.6ma vl i / o - .8 - - v dc digital i/o b1 - b16 7 v il logic low 3 --0.8v dc v ih logic high 3 2--v dc v ol logic low @ 1.6ma - - 0.3 v dc v oh logic high @ -1.6ma vl i / o - .8 - - v dc i in leakage current +25c -200 - +200 na +125c -2000 - +2000 na i z high-z leakage current 3 +25c -200 - +200 na +125c -2000 - +2000 na
6 scd5028-1 rev j 9/30/08 aeroflex plainview timing specifications 6 (t a = 25c with 50pf load) digital output ? rise time / fall time sym comments min typ 2 max units busy t lh rise time -2085ns t hl fall time -2085ns cw/ccw, ripple, b1- b16 t lh rise time - 45 100 ns t hl fall time - 45 100 ns busy pulse width t bpw 300 400 600 ns busy to data stable t bds enable = low - - 350 ns ripple pulse width t rpw 160 200 300 ns busy to ripple t br - 100 150 ns read data ? enable & inh would normally be tied together, data load = logic hi enable low to data stable t elds --70ns enable high to data hi-z t ehz --70ns inh low to data stable t ilds - - 400 ns inh high to data change t ihz - - 150 ns writing data ? enable & inh = logic hi data load pulse width t dlpw transparent trailing edge latch 200 - - ns data setup to data load t wds 60 - - ns data hold t wdh 10 - - ns notes 1. @ 10 bits, f ref > 4 x bw cl @ 12 bits, f ref > 8 x bw cl @ 14 bits, f ref > 12 x bw cl @ 16 bits, f ref > 16 x bw cl 2. all typical values are measured at +25c. 3. characteristics are guaranteed by design, not production tested. 4. accuracy apply over the full operati ng power supply voltage range, full operating temperature range, reference frequency ra nge, 10% signal amplitude va riation and 10% reference harmonic distortion. 5. for esd protection the act5028b features limiting resistors in series with diodes. proper esd precautions are strongly recommended to avoid functional da mage or performance degradation. 6. all testing at nominal voltage. 7. all unused inputs shall be tied to ground. bit 1 is always the msb.
7 scd5028-1 rev j 9/30/08 aeroflex plainview data data load enable t dlpw t wdh hi read cycle data inh enable data load t ehz / t ihz t elds / t ilds hi inh hi t wds write cycle busy timing data busy t bpw t bds ripple t rpw t br act5028b timing diagrams data data data data + 1 en inh hi hi
8 scd5028-1 rev j 9/30/08 aeroflex plainview figure 2 ? act5028b fu nctional block diagram digital output resolver input h=1 ep g1 [(s/t)+1] s [(s/10t)+1] vco g2 s velocity + - figure 3 ? act5028b tran sfer function diagram - + - + error amp +ref -ref r5 +5v r6 c4 +2.5v c1 r1 r1 c2 c3 r2 c3 c2 r2 r3 +2.25v - + digital output 16 bit up/down counter g=2 ct resolver input cvco 20.5p threshold = 1.95v g=0.9 h=1 g=2 g=14 vco vco & timing hysteresis = 75na ac1 bpf2 ac2 bpf1 demod1 demod2 intin2 intin1 int1 int2 ct eg demod comp 100k r4 100k r4 .1f c1 .1f 14 13 15 16 11 18 12 17 8 69105
9 scd5028-1 rev j 9/30/08 aeroflex plainview -12db/oct g = 4 -6db/oct bw 2g g t (t = g/2) rad/sec 10t closed loop bandwidth (bwcl) (hz) = -12db/oct 2g -------------- figure 4 ? act5028b open loop bode plot transfer function and bode plot the dynamic performance of the converter can be det ermined from its functional block diagram, transfer function diagram and bode plots, as shown in figures 2, 3 and 4. procedure for selec ting rdc bandwidth components * input: carrier frequency (fc) in hz [47 to 30,000 hz] input: nominal resolver input level in vrms [1vrms min. to 1.5vrms max.] input: resolution in bits; 10, 12, 14 or 16 bits input: closed loop bandwidth (bwcl) in hz [10 bit; bwcl = fc/4 max.] [12 bit; bwcl = fc/8 max.] [14 bit; bwcl = fc/12 max.] [16 bit; bwcl = fc/16 max. ] input: maximum tracking rate in rps [16 bit; 16 rps max.] (rps = rotations per second) [14 bit, 64 rps max.] [12 bit; 256 rps max.] [10 bit, 1024 rps max.] input: hysteresis in lsbs. recommended is 1 lsb for 16 & 14 bits and 0.7 lsbs for 12 & 10 bits. eg = nominal resolver input level ? .0027 [16 bit] or eg = nominal resolver input level ? .011 [14 bit] or eg = nominal resolver input level ? .043 [12 bit] or eg = nominal resolver input level ? .17 [10 bit] g = 2.22 ? bwcl g 2 = eg ? 0.45 ? g1 ? g2 hysteresis recommended values hys = 0.7 [10 & 12 bit] or hys = 1 [14 & 16 bit] or r1 (ohms) = 6 ? 10 6 ? eg ? hys g2 = maximum tracking rate ? 2 15 [16 bit] or g2 = maximum tracking rate ? 2 13 [14 bit] or g2 = maximum tracking rate ? 2 11 [12 bit] or g2 = maximum tracking rate ? 2 9 [10 bit] r3 (ohms) = (25 ? 10 9 )/g2 g1 = g 2 /(eg ? .45 ? g2) bwcl
10 scd5028-1 rev j 9/30/08 aeroflex plainview c2 (farads) = 1/(g1 ? r1) c3 (farads) = c2/10 r2 (ohms) = 2/(g ? c2) act5028b example calculations carrier frequency = 800 hz nominal resolver input level = 1.3vrms resolution = 14 bits closed loop bandwidth (bwcl) = 20 hz maximum tracking rate in rps = 1 hysteresis = 1 lsb eg = nominal resolver input level ? .011 [14 bit] = 1.3 ? .011 = .014 g = 2.22 ? bwcl = 2.22 ? 20 = 44.4 hys = 1 [14 bit] r1 (ohms) = 6 ? 10 6 ? eg ? hys = 6 ? 10 6 ? .014 ? 1 = 84k. use closest standard resistor = 84.5k 1% g2 = maximum tracking rate ? 2 13 = 8192 [2 13 for 14 bits] r3 (ohms) = (25 ? 10 9 )/g2 = (25 ? 10 9 )/8192 = 3,050k. use closest standard resistor = 3.01m 1% or 3m 5% g 2 = eg ? 0.45 ? g1 ? g2 g1 = g 2 /(eg ? .45 ? g2) = 44.4 2 /(.014 ? .45 ? 8192) = 38.2 c2 (farads) = 1/(g1 ? r1) = 1/(38.2 ? 84.5k) = .31f. use closest standard capacitor = .33f 10% c3 = c2/10 (farads) = c2/10 = .33/10 = .033f r2 (ohms) = 2/(g ? c2) = 2/(44.4 ? .33) = 136.5k. use closest standard resistor = 137k 1% signal and reference input conditioning inputs to the converter should be 1.3 vrms nominal, resolver format referenced to v cc /2 nominal figure 5 shows various input configurations. reference conditioning most resolvers have a leading input to output phase shift. a simple c-r leading phase shift network (figure 5 ? reference conditioning) from the resolver reference to the rdc?s reference input will provide the compensating phase shift required to bring the si gnals in phase. if the resolver has a lagging input to output phase shift an r-c lagging phase shift network (low pass network) would be required. note the c-r phase lead circuit on the input to th e demodulator (bpf1 and bpf2) in figure 2 should be considered when calculating the total system phase compensation. the formula for calculating the phas e shift network is as follows: 1 phase angle = arctan 6.28 x (r7 + r8) x c f ref select a convenient capacitor value and perform the fo llowing calculation to determine the proper resistor value. r = 1 (tan (phase angle)) x f ref x 6.28 x c * software program sw5028-2 available at aeroflex web site.
11 scd5028-1 rev j 9/30/08 aeroflex plainview figure 5 ? act5028b resolver, synchro and reference input configurations x x +sin -sin +cos -cos v cc /2 x x y y +sin x +sin y -sin x -sin y +cos x +cos y -cos x -cos y s3 x +sin y x -sin y x/2 +cos z z = x (sq rt 3) -cos z s1 s2 x x 10k +5v 10k .1f r8 +ref -ref +ref +ref c5 +ref +ref -ref -ref direct resolver sing le ended resolver conditioning differential resolver conditioning synchro conditioning 2.5v dc single ended reference differe ntial reference conditioning (floating reference) +sin -sin +cos -cos +sin -sin +cos -cos +sin -sin +cos -cos conditioning v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 4.7f r7 r8 c5 r7 r8 c5 r7 +
12 scd5028-1 rev j 9/30/08 aeroflex plainview reading the act 5028b the busy signal is asynchronous to the read signal create d by the interface circuit th at reads it. because of the asynchronous nature of the system (inherent with other re solver to digital converters) the designer must be careful when reading the digital interface. the implementation of reading the rdc is accomplished in one of two ways , using a cpu/mpu or using an fpga. the best method for reading the counter may also depend on the rep rate of the counter clock that can vary from 0 to 1s. the busy pulse is instrumental in re ading stable data from the act5028. th e busy pulse will be present for the following two situations: 1) when ever data is incremented or decremented in the rdc counter. 2) directly after the trailing posi tive going edge of /inh (see a w ithin example 5 timing diagram). based on 1 above there are many methods that can be im plemented to synchronize the reading of data from the act5028, below are a few examples: example 1: if the only time a read will occur is after the rdc has stopped (0 rps) there will be no busy signal to contend with. example 2: knowing the busy rep rate an interrupt to a cpu or logic can be developed from the busy pulse for the system to read the rdc ch ip as long as the read is guar anteed to occur prior to the next busy pulse. example 3: as long as the resolver is rotating the busy pulse can be used to indicate stable data to be sampled on leading or trailing edge. example 4: ignore busy an d perform two reads back to back and co mpare, if they are equal you have good data. the designer should be aware of the rep rate of busy which is equal to the clock rate of the counter. in most cases the angular velocity is < 3 rps in which case with a 16 bit counter rep rate would be (1 / 2 16 * 3) 5s. in this situation the reads would like to be within 5s of each other and the lsb would be ignored. although this me thod would be easier to implement with a cpu it could also be done in an fpga. example 5: the circuit below ignores the busy signal but insures samplin g of stable data. the clock should be a least 10mhz, the /rd pulse should be a minimum of 1.2s (to insure minimum /inh pulse width of 400ns), the sampling of data should be taken on the rising edge of the signal /rd. the /rd signal is synced up with the clk such th at the sampling on the d latch occurs on the opposite edge of the /rd transition. /inh & /en busy q /q d ck clk q /q d ck /rd s s example 5 circuit
13 scd5028-1 rev j 9/30/08 aeroflex plainview clk busy /inh & /en /rd t bpw a clk busy /inh & /en /rd 100ns 1.2s - 50ns a 1.2 s 1.2 s 1.2s - t bpw - 50ns busy occurs around leading edge of /rd busy occurs @ positive edge of clk with /rd low 100ns example 5 circuit timing waveforms
14 scd5028-1 rev j 9/30/08 aeroflex plainview table i ? act5028b pin out descriptions (cqfp package) pin # function pin # function pin # function 1dataload 19 a gnd 37 bit 9 2 vl i/o 20 n/c 38 bit 10 3 a gnd 21 -sin 39 bit 11 4a+5v 22+sin 40bit 12 5 vcoin 23 a gnd 41 bit 13 6 intin2 24 -cos 42 bit 14 7 n/c 25 +cos 43 bit 15 8 intin1 26 d gnd 44 bit 16 (lsb) 9int1 27d+5v 45enable 10 int2 28 bit 1 (msb) 46 n/c 11 +ref 29 bit 2 47 inh 12 -ref 30 bit 3 48 sc2 13 ac2 31 bit 4 49 sc1 14 ac1 32 bit 5 50 busy 15 bpf2 33 n/c 51 cw/ccw 16 bpf1 34 bit 6 52 ripple 17 demod1 35 bit 7 18 demod2 36 bit 8
15 scd5028-1 rev j 9/30/08 aeroflex plainview .956 sq max .600 .005 .050 .023 typ typ .017 typ .250 .008 .005 .063 .007 .008 ref .100 max 34 46 47 1 7 8 33 21 20 +.02 -0 figure 6 ? 52 pin ceramic quad flat package (cqfp) outline
16 scd5028-1 rev j 9/30/08 aeroflex plainview errata information act5028-2-x-x this errata information represents th e known bugs, anomalies, and work-around s for the act5028 resolver to digital converter description of anomalies: anomaly #1: instability at 360 o and 180 o input angles anomaly #2: correcting for the integral n onlinearity error found in revision b silicon anomaly #3: precautionary note when power is first applied. effected parts: anomaly #1 problem description: this problem only occurs in the 16 b it mode when rotating in the clockwise (c w) direction and has been observed on 100% of the parts tested at 25c. it occurs 100% of the time at 360 o and approximately 76% at 180 o . at 360 o the problem occurs when the counter pa sses from ffff to 0000 then reverse ro tation (ccw) back to ffff. at 180 o the problem occurs when the counter passes from 7fff to 8000 then reverse rota tion (ccw) back to 7fff. two different failure modes have been observed: 1) the output latch locks to a value with the msb inverted giving the in dication that the rdc chip is 180 o out of phase, the rdc chip exhibits zero error. this cond ition remains indefinitely unti l the resolver rotates in either direction by one count. at which time the rdc chip re sponds to the 180 o error which takes less than 150ms to correct. 2) the rdc chip sees an immediate error of 180 o and begins to correct for this error which takes less than 150ms. in some cases it has been observed that the msb is ok but the next bit gets inverted which provides a 90 o error. in this case the time required for the rdc chip to correct its self is less than 75 ms. recommended actions: 1) use the 14, 12 or 10 bit mode where this problem doesn?t exist. 2) insure a hysteresis of at least one bit to prevent this anomaly when rotating very slowly. 3) avoid reversing direction at 360 o and 180 o when rotating in the cw direction. 4) if the resolver stops within two counts of 360 o or 180 o wait 150ms after motion re sumes before reading the rdc output. model anomaly anomaly anomaly act5028-2-1-x 1 2a 3 act5028-2-2-x 1 2b 3
17 scd5028-1 rev j 9/30/08 aeroflex plainview anomaly #2 problem description and recommended action: this errata information is to address the constant integral nonlinearity (inl) that exists at each angle of the act5028b resolver to digital converter (rdc). this error is repeatable from chip to chip and provides a look up table of offsets that must be added to the output of the resolver to digital converter to get the correct angle. figure 7 shows the error in minutes that exists at 2 o increments for the full 360 o . note that the inl error from 0 o to 180 o is basically the same as the error between 180 o and 360 o . table ii has the angle and correction factor (in minutes) that must be added to zero out the inl error. a simple calculation can be performed to derive a correction factor for angles that fall between the angles listed in table ii herein. al = larger angle as = smaller angle cl = correction factor associated with larger angle cs = correction factor associated with smaller angle na = new angle ncf = new correction factor formula: ncf = cs + (((na - as) / (al - as)) * (cl - cs)) example: require the correction factor @ 15 o ncf = 10.17114258 + (((15 ? 14) / (16 ? 14)) * (11.113769 53 - 10.17114258)) ncf = 10.17114258 + (((1 ) / (2)) * .94262695) ncf = 10.17114258 + (.5 * .94262695) ncf = 10.17114258 + .471313475 ncf = 10.64245606 minutes
18 scd5028-1 rev j 9/30/08 aeroflex plainview -15 -12 -9 -6 -3 0 3 6 9 12 15 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 an g l e mi n u te s figure 7 ? anomaly #2a angle error chart
19 scd5028-1 rev j 9/30/08 aeroflex plainview -9 -7 -5 -3 -1 1 3 5 7 9 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 angle minutes figure 7 ? anomaly #2b angle error chart
20 scd5028-1 rev j 9/30/08 aeroflex plainview angle correction factor angle correction factor angle correction factor angle correction factor 0 0.125244141 90 0.415283203 180 0.145019531 270 0.474609375 2 1.911621094 92 1.153564453 182 1.997314453 272 1.206298828 4 4.073730469 94 1.977539062 184 3.981445312 274 1.970947266 6 5.715087891 96 2.537841797 186 5.754638672 276 2.577392578 8 6.868652344 98 2.814697266 188 6.822509766 278 2.649902344 10 8.411132812 100 3.071777344 190 8.411132813 280 3.150878906 12 9.241699219 102 2.735595703 192 9.221923828 282 2.794921875 14 10.17114258 104 2.656494141 194 10.19750977 284 2.682861328 16 11.11376953 106 2.478515625 196 11.09399414 286 2.564208984 18 11.54882812 108 1.885253906 198 11.44995117 288 1.858886719 20 11.94433594 110 1.285400391 200 11.97729492 290 1.562255859 22 11.99707031 112 0.837158203 202 12.01025391 292 0.626220703 24 11.91137695 114 -0.243896484 204 11.88500977 294 -0.171386719 26 12.26733398 116 -0.626220703 206 12.19482422 296 -0.652587891 28 11.85205078 118 -1.621582031 208 12.10913086 298 -1.496337891 30 11.77954102 120 -2.168701172 210 11.82568359 300 -2.083007812 32 11.97070312 122 -2.814697266 212 11.92456055 302 -2.649902344 34 11.64770508 124 -3.460693359 214 11.64111328 304 -3.618896484 36 11.26538086 126 -4.548339844 216 11.22583008 306 -4.403320313 38 10.90942383 128 -4.871337891 218 10.89624023 308 -4.95703125 40 10.16455078 130 -5.945800781 220 10.13818359 310 -5.879882812 42 9.683349609 132 -6.842285156 222 9.650390625 312 -6.723632813 44 9.030761719 134 -7.48828125 224 8.984619141 314 -7.461914063 46 8.002441406 136 -8.582519531 226 7.969482422 316 -8.450683594 48 7.237792969 138 -9.043945313 228 7.218017578 318 -8.918701172 50 6.545654297 140 -9.887695313 230 6.492919922 320 -9.755859375 52 5.6953125 142 -10.31616211 232 5.682128906 322 -10.29638672 54 5.174560547 144 -10.73144531 234 5.174560547 324 -10.81054687 56 4.198974609 146 -11.15332031 236 4.185791016 326 -11.29174805 58 3.487060547 148 -11.43017578 238 3.520019531 328 -11.3972168 60 2.939941406 150 -11.32470703 240 2.887207031 330 -11.44995117 62 2.241210938 152 -11.64770508 242 2.181884766 332 -11.57519531 64 1.614990234 154 -11.70043945 244 1.588623047 334 -11.65429688 66 1.087646484 156 -11.71362305 246 1.114013672 336 -11.62792969 68 0.131835938 158 -11.5949707 248 0.171386719 338 -11.62792969 70 -0.547119141 160 -11.58837891 250 -0.573486328 340 -11.56201172 72 -1.0546875 162 -11.1862793 252 -1.074462891 342 -11.12036133 74 -1.549072266 164 -10.79077148 254 -1.502929687 344 -10.81713867 76 -1.641357422 166 -9.861328125 256 -1.628173828 346 -9.834960938 78 -1.977539063 168 -8.971435547 258 -1.984130859 348 -8.978027344 80 -1.944580078 170 -7.929931641 260 -1.957763672 350 -7.883789063 82 -1.766601563 172 -6.512695313 262 -1.713867188 352 -6.473144531 84 -1.753417969 174 -5.510742187 264 -1.694091797 354 -5.444824219 86 -1.0546875 176 -3.697998047 266 -1.034912109 356 -3.684814453 88 -0.250488281 178 -1.680908203 268 -0.283447266 358 -1.654541016 table ii ? anomaly #2a correction factor (minutes)
21 scd5028-1 rev j 9/30/08 aeroflex plainview angle correction factor angle correction factor angle correction factor angle correction factor 0 0.203780402 90 0.388943965 180 0.192649156 270 0.149467633 2 1.201123493 92 0.425014547 182 1.302393729 272 0.466394333 4 2.70465535 94 1.029048142 184 2.654324654 274 1.024646311 6 3.789635076 96 1.054983614 186 3.541737941 276 1.138295364 8 4.421013418 98 0.985566018 188 4.412445369 278 1.15876717 10 5.215566619 100 1.304993369 190 5.203491983 280 1.099923444 12 5.834478943 102 0.905201887 192 5.803723899 282 0.694276061 14 6.365571511 104 0.618766526 194 6.389561265 284 0.634835761 16 6.955572794 106 0.339237225 196 6.917655625 286 0.445449797 18 7.215013746 108 -0.175559243 198 7.108442088 288 -0.177214754 20 7.668033013 110 -0.406551233 200 7.718946308 290 -0.454718209 22 8.020721684 112 -0.99953425 202 8.027522848 292 -0.889492647 24 7.933794161 114 -1.499164395 204 7.888002744 294 -1.403421394 26 8.232306488 116 -1.844624191 206 8.144939892 296 -1.843684976 28 8.178317924 118 -2.397679189 208 8.138785463 298 -2.293495361 30 8.045994542 120 -2.881543541 210 8.080969999 300 -3.028744943 32 8.36259965 122 -3.236345202 212 8.292840379 302 -3.324410371 34 8.165615526 124 -3.826772691 214 8.137597002 304 -3.95622932 36 7.853648573 126 -4.402200107 216 7.853112414 306 -4.509103327 38 7.801531535 128 -4.684869835 218 7.773708404 308 -4.688703638 40 7.335965753 130 -5.328598278 220 7.275534799 310 -5.187045539 42 7.221900549 132 -5.670542709 222 7.201587126 312 -5.509262725 44 7.082034482 134 -5.97411451 224 7.004955442 314 -5.888379652 46 6.460299345 136 -6.658819257 226 6.398031462 316 -6.48066597 48 6.09360404 138 -6.661897423 228 6.026752907 318 -6.814284697 50 5.627097169 140 -7.094021917 230 5.558449327 320 -6.980523747 52 5.225444131 142 -7.603145351 232 5.165559731 322 -7.525344389 54 4.799049593 144 -7.4361178 234 4.774337917 324 -7.475305746 56 4.331451914 146 -7.735451293 236 4.300501478 326 -7.830463169 58 3.692843475 148 -7.941762029 238 3.67712898 328 -7.845085267 60 3.461690092 150 -7.955998624 240 3.376174401 330 -7.737209372 62 2.917592224 152 -8.046982441 242 2.842718999 332 -7.950106111 64 2.396542424 154 -7.80890584 244 2.361198081 334 -8.023122068 66 2.206561334 156 -7.518632897 246 2.219187977 336 -7.690545974 68 1.553478755 158 -7.694354839 248 1.317468789 338 -7.71908654 70 1.049330378 160 -7.452276395 250 1.026060671 340 -7.438013668 72 0.597675735 162 -6.973083459 252 0.584687534 342 -6.895998369 74 0.206092961 164 -6.72826432 254 0.257365342 344 -6.759761311 76 0.019981548 166 -6.191360248 256 0.024375455 346 -6.141721479 78 -0.219060483 168 -5.698378367 258 -0.199283218 348 -5.697087991 80 -0.546519868 170 -5.196077543 260 -0.576187854 350 -5.132956339 82 -0.576407731 172 -4.228528382 262 -0.534840477 352 -4.20309308 84 -0.614729518 174 -3.402853297 264 -0.531974122 354 -3.335120298 86 -0.399630686 176 -2.508137965 266 -0.387924935 356 -2.453570836 88 0.180584177 178 -1.065912708 268 0.143590373 358 -1.041202907 table ii ? anomaly #2b corr ection factor (minutes)
22 scd5028-1 rev j 9/30/08 aeroflex plainview anomaly #3 precautionary note: the act5028 rdc converter can provide incorrect data output if a unit step of 180 (starting at any angle) is introduced to the sin / cos input. this anomaly is difficult to reproduce since a resolv er will never provide a unit step function to the rdc chip. the only time this would be a concern is during powe r up, if the resolver is set to 180. the rdc will initialize its internal counter to 00 00h which simulates the unit step f unction mentioned above. in practice this error condition during power up is difficult to pro duce because of the dynamics associated with all the variables when power is first applied. if the system designer does nothing to accommodate this pote ntial problem the system could see an error at power on, however, this error will be self co rrected once the resolver begins to rotate.
scd5028-1 rev j 9/30/08 23 plainview, new york toll free: 800-the-1553 fax: 516-694-6715 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com aeroflex microelectronic solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. all parameters must be validated for each customer's application by engineering. no liability is assumed as a result of use of this product. no patent licenses are implied. our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused export control: export warning: this product is controlled for expor t under the international traffic in arms regulations (itar). a license from the u.s. department of state is required prior to the export of this product from the united states. aeroflex?s military and space pr oducts are controlled for export under the international traffic in arms regulations (itar) and may not be sold or proposed or offered for sale to certain countries. (see itar 126.1 for complete information.) ordering information 3 aeroflex part # desc smd # screening package act5028-201-1s act5028-201-2s 5962-0423501kxc 5962-0423501kxa dscc smd 5962-04235, rev. b silicon 2 cqfp act5028-202-1s act5028-202-2s 5962-0423502kxc 5962-0423502kxa ACT5028-2-1-S 1 - class k , rev. b silicon 2 act5028-2-1-7 1 class c, rev. b silicon 2 act5028-2-1-i 1 class i, rev. b silicon 2 act5028-2-2-s 1 - class k , rev. b silicon 2 act5028-2-2-7 1 class c, rev. b silicon 2 act5028-2-2-i 1 class i, rev. b silicon 2 act5028, evaluation board 3 4 --- notes 1. dash #?s: the first dash number indi cates the revision of silicon: -1 = rev. a -2 = rev. b the second dash number indicates the wafer lot run. the last dash number indicate s the testing level of the part: 7 = class c = commercial flow, commercial temp. range, 0 o c to +70 o c testing i = class i = commercial flow, industrial temp. range, -40 o c to +85 o c testing s = mil-prf-38534 class k flow, -55 o c to +125 o c testing (rev. b silicon) 2. see errata informati on anomaly #1, 2 & 3 within this data sheet. 3. contact factory for av ailability and pricing. 4. see application note an5028-1

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