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description the 4518 group is a 4-bit single-chip microcomputer designed with cmos technology. its cpu is that of the 4500 series using a simple, high-speed instruction set. the computer is equipped with serial i/o, four 8-bit timers (each timer has one or two reload regis- ter), a 10-bit a-d converter, interrupts, and oscillation circuit switch function. the various microcomputers in the 4518 group include variations of the built-in memory size as shown in the table below. features minimum instruction execution time .................................. 0.5 s (at 6 mhz oscillation frequency, in x in through-mode) supply voltage mask rom version ...................................................... 1.8 to 5.5 v one time prom version ............................................. 2.5 to 5.5 v (it depends on operation source clock, oscillation frequency and op- eration mode) timers timer 1 ...................................... 8-bit timer with a reload register timer 2 ...................................... 8-bit timer with a reload register timer 3 ...................................... 8-bit timer with a reload register timer 3 ................................. 8-bit timer with two reload registers product m34518m2-xxxfp m34518m2-xxxsp m34518m4-xxxfp m34518m4-xxxsp m34518m6-xxxfp m34518m8-xxxfp m34518e8fp ( note ) m34518e8sp ( note ) rom type mask rom mask rom mask rom mask rom mask rom mask rom one time prom one time prom package 32p6u-a 32p4b 32p6u-a 32p4b 32p6u-a 32p6u-a 32p6u-a 32p4b ram size ( ? 4 bits) 256 words 256 words 256 words 256 words 384 words 384 words 384 words 384 words rom (prom) size ( ? 10 bits) 2048 words 2048 words 4096 words 4096 words 6144 words 8192 words 8192 words 8192 words interrupt ........................................................................ 8 sources key-on wakeup function pins ................................................... 10 serial i/o ....................................................................... 8 bits ? 1 a-d converter ...... 10-bit successive approximation method, 4ch voltage drop detection circuit reset occurrence .................................... typ. 3.5 v (ta = 25 ?) reset release .......................................... typ. 3.7 v (ta = 25 ?) watchdog timer clock generating circuit (ceramic resonator/rc oscillation/quartz-crystal oscillation/inter- nal ring oscillator) led drive directly enabled (port d) application electrical household appliance, consumer electronic products, of- fice automation equipment, etc. note: shipped in blank. rev.2.00 2003.04.15 page 1 of 156 4518 group single-chip 4-bit cmos microcomputer rej03b0008-0200z rev.2.00 2003.04.15 preliminary notice: this is not a final specification. some parametric limits are subject to change.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 2 of 156 4518 group pin configuration pin configuration (top view) (4518 group) outline 32p6u-a 2 1 345678 23 24 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 d 3 d 4 d 5 d 6 /cntr0 d 7 /cntr1 p2 0 /s ck p2 1 /s out p2 2 /s in p0 2 p0 1 p0 0 p6 3 /a in3 p6 2 /a in2 p6 1 /a in1 p6 0 /a in0 p3 1 /int1 p3 0 /int0 vdce v dd v ss x in x out cnv ss reset p0 3 p1 0 p1 1 p1 2 p1 3 d 0 d 1 d 2 m34518mx-xxxfp m34518e8fp 8 7 10 9 12 11 14 15 16 13 6 5 4 3 2 m34518mx-xxxsp m34518e8sp 1 25 26 23 24 21 22 19 18 17 20 27 28 29 30 31 32 d 0 d 1 d 2 d 3 d 4 d 5 d 6 /cntr0 d 7 /cntr1 p2 0 /s ck p2 1 /s out p2 2 /s in reset cnv ss x out x in v ss p1 3 p1 2 p1 1 p1 0 p0 3 p0 2 p0 1 p0 0 p6 3 /a in3 p6 2 /a in2 p6 1 /a in1 p6 0 /a in0 p3 1 /int1 p3 0 /int0 vdce v dd pin configuration (top view) (4518 group) outline 32p4b
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 3 of 156 4518 group block diagram (4518 group) 4 4 3 2 4 8 r a m r o m m e m o r y i / o p o r t i n t e r n a l p e r i p h e r a l f u n c t i o n s t i m e r t i m e r 1 ( 8 b i t s ) s y s t e m c l o c k g e n e r a t i o n c i r c u i t t i m e r 2 ( 8 b i t s ) 2 5 6 , 3 8 4 w o r d s ? 4 b i t s 2 0 4 8 , 4 0 9 6 , 6 1 4 4 , 8 1 9 2 w o r d s ? 1 0 b i t s 4 5 0 0 s e r i e s c p u c o r e r e g i s t e r b ( 4 b i t s ) r e g i s t e r a ( 4 b i t s ) r e g i s t e r d ( 3 b i t s ) r e g i s t e r e ( 8 b i t s ) s t a c k r e g i s t e r s k ( 8 l e v e l s ) i n t e r r u p t s t a c k r e g i s t e r s d p ( 1 l e v e l ) a l u ( 4 b i t s ) w a t c h d o g t i m e r ( 1 6 b i t s ) p o r t p 0 p o r t p 1 p o r t p 2 v o l t a g e d r o p d e t e c t i o n c i r c u i t t i m e r 3 ( 8 b i t s ) t i m e r 4 ( 8 b i t s ) x i n - x o u t ( c e r a m i c / q u a r t z - c r y s t a l / r c ) b u i l t - i n r i n g o s c i l l a t o r p o r t p 3 p o r t d p o r t p 6 s e r i a l i / o ( 8 b i t s ? 1 ) a - d c o n v e r t e r ( 1 0 b i t s ? 4 c h )
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 4 of 156 4518 group performance overview function 148 0.5 s (at 6.0 mhz oscillation frequency, in x in through-mode) 2048 words ? 10 bits 4096 words ? 10 bits 6144 words ? 10 bits 8192 words ? 10 bits 256 words ? 4 bits 384 words ? 4 bits eight independent i/o ports; ports d 6 and d 7 are also used as cntr0 and cntr1, respectively. the output structure is switched by software. 4-bit i/o port; a pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit i/o port; a pull-up function, a key-on wakeup function and output structure can be switched by software. 3-bit i/o port; ports p2 0 , p2 1 and p2 2 are also used as s ck , s out and s in , respectively. 2-bit i/o port ; ports p3 0 and p3 1 are also used as int0 and int1, respectively. 4-bit i/o port ; ports p6 0 p6 3 are also used as a in0 a in3 , respectively. 8-bit timer with a reload register is also used as an event counter. also, this is equipped with a period/pulse width measurement function. 8-bit timer with a reload register. 8-bit timer with a reload register is also used as an event counter. 8-bit timer with two reload registers and pwm output function. 10-bit wide ? 4 ch, this is equipped with an 8-bit comparator function. 8-bit ? 1 8 (two for external, four for timer, one for a-d, and one for serial i/o) 1 level 8 levels cmos silicon gate 32-pin plastic molded lqfp (32p6u-a)/sdip (32p4b) 20 c to 85 c 1.8 v to 5.5 v (it depends on operation source clock, oscillation frequency and operating mode.) 2.5 v to 5.5 v (it depends on operation source clock, oscillation frequency and operating mode.) 2.8 ma (v dd =5v, f(x in )=6 mhz, f(stck)=f(x in ), ring oscillator stop) 70 a (v dd =5v, f(x in )=32 khz, f(stck)=f(x in ), ring oscillator stop) 150 a (v dd =5v, ring oscillator is used, f(stck)=f(ring), f(x in ) stop) 0.1 a (at room temperature, v dd = 5 v, output transistors in the cut-off state) parameter number of basic instructions minimum instruction execution time memory sizes input/output ports timers a-d converter serial i/o interrupt subroutine nesting device structure package operating temperature range supply voltage power dissipation (typical value) rom ram d 0 d 7 p0 0 p0 3 p1 0 p1 3 p2 0 p2 2 p3 0 , p3 1 p6 0 p6 3 timer 1 timer 2 timer 3 timer 4 sources nesting mask rom version one time prom version active mode ram back-up mode i/o (input is examined by skip decision) i/o i/o i/o i/o i/o m34518m2 m34518m4 m34518m6 m34518m8/e8 m34518m2/m4 m34518m6/m8/e8
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 5 of 156 4518 group pin description name power supply ground cnv ss voltage drop detection circuit enable reset input/output main clock input pin v dd v ss cnv ss vdce reset x in input/output input i/o input function connected to a plus power supply. connected to a 0 v power supply. connect cnv ss to v ss and apply l (0v) to cnv ss certainly. this pin is used to operate/stop the voltage drop detection circuit. when h level is input to this pin, the circuit starts operating. when l level is input to this pin, the circuit stops operating. an n-channel open-drain i/o pin for a system reset. when the srst instruction, watchdog timer or the voltage drop detection circuit cause the system to be reset, the reset pin outputs l level. i/o pins of the main clock generating circuit. when using a ceramic resonator, connect it between pins x in and x out . when using a 32 khz quartz-crystal oscillator, connect it between pins x in and x out . a feedback resistor is built-in between them. when using the rc oscillation, connect a resistor and a capacitor to x in , and leave x out pin open. x out main clock output output d 0 d 7 p0 0 p0 3 p1 0 p1 3 p2 0 p2 3 p3 0 p3 3 p6 0 p6 3 cntr0, cntr1 int0, int1 a in0 a in3 s ck s out s in i/o port d input is examined by skip decision. i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o port p6 timer input/output interrupt input analog input serial i/o data i/o serial i/o data output serial i/o clock input i/o i/o i/o i/o i/o i/o i/o input input i/o output input each pin of port d has an independent 1-bit wide i/o function. the output structure can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to 1 and select the n-channel open-drain. ports d 6 , d 7 is also used as cntr0 pin and cntr1 pin, respectively. p ort p0 serves as a 4-bit i/o port. the output structure can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to 1 and select the n-channel open-drain. port p0 has a key-on wakeup function and a pull-up function. both functions can be switched by software. p ort p1 serves as a 4-bit i/o port. the output structure can be switched to n-channel open-drain or cmos by software. for input use, set the latch of the specified bit to 1 and select the n-channel open-drain. port p1 has a key-on wakeup function and a pull-up function. both functions can be switched by software. p ort p2 serves as a 3-bit i/o port. the output structure is n-channel open-drain. for input use, set the latch of the specified bit to 1 . ports p2 0 p2 2 are also used as s ck , s out , s in , respectively. p ort p3 serves as a 2-bit i/o port. the output structure is n-channel open-drain. for input use, set the latch of the specified bit to 1 . ports p3 0 and p3 1 are also used as int0 pin and int1 pin, respectively. p ort p6 serves as a 4-bit i/o port. the output structure can be switched to n-channel open-drain. for input use, set the latch of the specified bit to 1 . ports p6 0 p6 3 are also used as a in0 a in3 , respectively. cntr0 pin has the function to input the clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. cntr1 pin has the function to input the clock for the timer 3 event counter, and to output the pwm signal generated by timer 4.cntr0 pin and cntr1 pin are also used as ports d 6 and d 7 , respectively. int0 pin and int1 pin accept external interrupts. they have the key-on wakeup func- tion which can be switched by software. int0 pin and int1 pin are also used as ports p3 0 and p3 1 , respectively. a-d converter analog input pins. a in0 a in3 are also used as ports p6 0 p6 3 , respec- tively. serial i/o data transfer synchronous clock i/o pin. s ck pin is also used as port p2 0. . serial i/o data output pin. s out pin is also used as port p2 1 . serial i/o data input pin. s in pin is also used as port p2 2 .
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 6 of 156 4518 group definition of clock and cycle operation source clock the operation source clock is the source clock to operate this product. in this product, the following clocks are used. clock (f(x in )) by the external ceramic resonator clock (f(x in )) by the external rc oscillation clock (f(x in )) by the external input clock (f(ring)) of the ring oscillator which is the internal oscil- lator clock (f(x in )) by the external quartz-crystal oscillation register mr system clock f(stck) = f(x in ) f(stck) = f(ring) f(stck) = f(x in )/2 f(stck) = f(ring)/2 f(stck) = f(x in )/4 f(stck) = f(ring)/4 f(stck) = f(x in )/8 f(stck) = f(ring)/8 table selection of system clock ? : 0 or 1 note: the f(ring)/8 is selected after system is released from reset. when ring oscillator clock is selected for main clock, set the ring oscillator to be operating state. mr 2 0 1 0 1 mr 3 0 0 1 1 operation mode x in through mode ring through mode x in divided by 2 mode ring divided by 2 mode x in divided by 4 mode ring divided by 4 mode x in divided by 8 mode ring divided by 8 mode system clock (stck) the system clock is the basic clock for controlling this product. the system clock is selected by the clock control register mr shown as the table below. instruction clock (instck) the instruction clock is the basic clock for controlling cpu. the instruction clock (instck) is a signal derived by dividing the system clock (stck) by 3. the one instruction clock cycle gen- erates the one machine cycle. machine cycle the machine cycle is the standard cycle required to execute the instruction. mr 0 0 1 0 1 0 1 0 1 mr 1 0 ? 0 ? 0 ? 0 ? notes 1: pins except above have just single function. 2: the input/output of p3 0 and p3 1 can be used even when int0 and int1 are selected. 3: the input of ports p2 0 p2 2 can be used even when s in , s out and s ck are selected. 4: the input/output of d 6 can be used even when cntr0 (input) is selected. 5: the input of d 6 can be used even when cntr0 (output) is selected. 6: the input/output of d 7 can be used even when cntr1 (input) is selected. 7: the input of d 7 can be used even when cntr1 (output) is selected. pin d 6 d 7 p2 0 p2 1 p2 2 p3 0 p3 1 multifunction cntr0 cntr1 s ck s out s in int0 int1 multifunction pin cntr0 cntr1 s ck s out s in int0 int1 multifunction d 6 d 7 p2 0 p2 1 p2 2 p3 0 p3 1 pin p6 0 p6 1 p6 2 p6 3 multifunction a in0 a in1 a in2 a in3 pin a in0 a in1 a in2 a in3 multifunction p6 0 p6 1 p6 2 p6 3
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 7 of 156 4518 group port function port port d port p0 port p1 port p2 port p3 port p6 i/o unit 1 4 4 3 2 4 control instructions sd, rd szd cld op0a iap0 op1a iap1 op2a iap2 op3a iap3 op6a iap6 control registers fr1, fr2 w6 w4 fr0 pu0 k0, k1 fr0 pu1 k0 j1 i1, i2 k2 q2 q1 output structure n-channel open-drain/ cmos n-channel open-drain/ cmos n-channel open-drain/ cmos n-channel open-drain n-channel open-drain n-channel open-drain input output i/o (8) i/o (4) i/o (4) i/o (3) i/o (2) i/o (4) remark pin d 0 d 5 d 6 /cntr0 d 7 /cntr1 p0 0 p0 3 p1 0 p1 3 p2 0 /s ck , p2 1 /s out p2 2 /s in p3 0 /int0, p3 1 /int1 p6 0 /a in0 p6 3 /a in3 output structure selection function (programmable) built-in programmable pull-up functions, key-on wakeup functions and output structure selection functions built-in programmable pull-up functions, key-on wakeup functions and output structure selection functions
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 8 of 156 4518 group connections of unused pins connection open. open. open. connect to v ss . open. connect to v ss . open. connect to v ss . open. connect to v ss . open. connect to v ss . open. connect to v ss . open. connect to v ss . open. connect to v ss . open. connect to vss. open. connect to vss. open. connect to vss. pin x in x out d 0 d 5 d 6 /cntr0 d 7 /cntr1 p0 0 p0 3 p1 0 p1 3 p2 0 /s ck p2 1 /s out p2 2 /s in p3 0 /int0 p3 1 /int1 p6 0 /a in0 p6 3 /a in3 usage condition internal oscillator is selected. (note 1) internal oscillator is selected. (note 1) rc oscillator is selected. (note 2) external clock input is selected for main clock. (note 3) n-channel open-drain is selected for the output structure. (note 4) cntr0 input is not selected for timer 1 count source. n-channel open-drain is selected for the output structure. (note 4) cntr1 input is not selected for timer 3 count source. n-channel open-drain is selected for the output structure. (note 4) the key-on wakeup function is not selected. (note 6) n-channel open-drain is selected for the output structure. (note 5) the pull-up function is not selected. (note 4) the key-on wakeup function is not selected. (note 6) the key-on wakeup function is not selected. (note 7) n-channel open-drain is selected for the output structure. (note 5) the pull-up function is not selected. (note 4) the key-on wakeup function is not selected. (note 7) s ck pin is not selected. s in pin is not selected. 0 is set to output latch. 0 is set to output latch. notes 1: after system is released from reset, the internal oscillation (ring oscillator) is selected for main clock (rg 0 =0, mr 0 =1). 2: when the crck instruction is executed, the rc oscillation circuit becomes valid. be careful that the swich of system clock is n ot executed only by the crck instruction execution. in order to start oscillation, setting the main clock f(x in ) oscillation to be valid (mr 1 =0) is required. (if necessary, generate the oscillation stabilizing wait time by software.) also, when the main clock (f(x in )) is selected as system clock, set the main clock f(x in ) oscillation (mr 1 =0) to be valid, and select main clock f(x in ) (mr 0 =0). be careful that the switch of system clock cannot be executed at the same time when main clock oscillation is started. 3: in order to use the external clock input for the main clock, select the ceramic resonance by executing the cmck instruction at the beggining of soft- ware, and then set the main clock (f(x in )) oscillation to be valid (mr 1 =0). until the main clock (f(x in )) oscillation becomes valid (mr 1 =0) after ceramic resonance becomes valid, x in pin is fixed to h . when an external clock is used, insert a 1 k ? resistor to x in pin in series for limits of current . 4: be sure to select the output structure of ports d 0 d 5 and the pull-up function of p0 0 p0 3 and p1 0 p1 3 with every one port. set the corresponding bits of registers for each port. 5: be sure to select the output structure of ports p0 0 p0 3 and p1 0 p1 3 with every two ports. if only one of the two pins is used, leave another one open. 6: the key-on wakeup function is selected with every two bits. when only one of key-on wakeup function is used, considering tha t the value of key-on wake-up control register k1, set the unused 1-bit to h input (turn pull-up transistor on and open) or l input (connect to v ss , or open and set the output latch to 0 ). 7: the key-on wakeup function is selected with every two bits. when one of key-on wakeup function is used, turn pull-up transis tor of the unused one on and open. (note when connecting to v ss and v dd ) connect the unused pins to v ss and v dd using the thickest wire at the shortest distance against noise.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 9 of 156 4518 group port block diagrams port block diagram (1) d 0 d 3 s rq fr1 i t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : a p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e v d d o r l e s s . 3 : i r e p r e s e n t s b i t s 0 t o 3 . n o t e s 1 : r e g i s t e r yd e c o d e r s d i n s t r u c t i o n r d i n s t r u c t i o n skip decision c l d i n s t r u c t i o n (note 1) (note 2) (note 1) (note 3) s z d i n s t r u c t i o n d 4 s rq fr2 0 r e g i s t e r y d e c o d e r s d i n s t r u c t i o n r d i n s t r u c t i o n skip decision c l d i n s t r u c t i o n (note 1) (note 2) (note 1) szd instruction d 5 s rq fr2 1 r e g i s t e r y d e c o d e r s d i n s t r u c t i o n r d i n s t r u c t i o n skip decision cld instruction (note 1) (note 2) (note 1) szd instruction
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 10 of 156 4518 group port block diagram (2) this symbol represents a parasitic diode on the port. 2: applied potential to these ports must be v dd or less. notes 1: w1 0 w1 1 s rq fr2 2 w6 0 0 1 d 6 /cntr0 register y decoder sd instruction rd instruction skip decision cld instruction (note 1) (note 2) timer 1 underflow signal w2 3 0 1 1/2 1/2 timer 2 underflow signal w6 2 0 1 clock (input) for timer 1 event count or period measurement signal input w5 0 w5 1 w3 0 w3 1 s rq fr2 3 w4 3 0 1 d 7 /cntr1 register y decoder sd instruction rd instruction skip decision cld instruction (note 1) (note 2) w6 3 0 1 clock (input) for timer 3 event count pwmod szd instruction szd instruction
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 11 of 156 4518 group port block diagram (3) p0 0 , p0 1 op0a instruction register a a j a j d (note 2) (note 1) fr0 0 iap0 instruction pu0 j pull-up transistor tq this symbol represents a parasitic diode on the port. 2: applied potential to these ports must be v dd or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. notes 1: (note 1) k0 0 key-on wakeup level detection circuit edge detection circuit 0 1 k1 1 0 1 k1 0 (note 3) p0 2 , p0 3 op0a instruction register a a k a k d (note 2) (note 1) fr0 1 iap0 instruction pu0 k pull-up transistor tq (note 1) k0 1 key-on wakeup level detection circuit edge detection circuit 0 1 k1 3 0 1 k1 2 (note 4) p1 0 , p1 1 op1a instruction register a a j a j d (note 2) (note 1) fr0 2 iap1 instruction pu1 j pull-up transistor tq (note 1) k0 2 (note 3) p1 2 , p1 3 op1a instruction register a a k a k d (note 2) (note 1) fr0 3 iap1 instruction pu1 k pull-up transistor tq (note 1) k0 3 key-on wakeup level detection circuit (note 4) (note 3) (note 4) (note 3) (note 4) key-on wakeup level detection circuit
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 12 of 156 4518 group port block diagram (4) j 1 0 0 1 t h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t . 2 : a p p l i e d p o t e n t i a l t o t h e s e p o r t s m u s t b e v d d o r l e s s . n o t e s 1 : p 2 0 / s c k s y n c h r o n o u s c l o c k ( o u t p u t ) f o r s e r i a l d a t a t r a n s f e r (note 1) ( n o t e 2 ) s y n c h r o n o u s c l o c k ( i n p u t ) f o r s e r i a l d a t a t r a n s f e r r e g i s t e r a a 0 a 0 iap2 instruction j1 0 j1 1 j1 2 j1 3 d t q o p2 a i n s t r u c t i o n p 2 1 / s o u t (note 1) (note 2) r e g i s t e r a a 1 a 1 iap2 instruction o p2 a i n s t r u c t i o n d t q s e r i a l d a t a o u t p u t p 2 2 / s i n (note 1) (note 2) r e g i s t e r a a 2 a 2 iap2 instruction o p2 a i n s t r u c t i o n d t q s e r i a l d a t a i n p u t j1 1
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 13 of 156 4518 group port block diagram (5) this symbol represents a parasitic diode on the port. 2: applied potential to these ports must be v dd or less. 3: as for details, refer to the external interrupt circuit structure. notes 1: p3 0 /int0 (note 1) (note 2) register a a 0 a 0 iap3 instruction op3a instruction d t q external 0 interrupt circuit external 0 interrupt key-on wakeup input timer 1 count start synchronous circuit input period measurement circuit input p3 1 /int1 (note 1) (note 2) register a a 1 a 1 iap3 instruction op3a instruction d t q external 1 interrupt circuit external 1 interrupt key-on wakeup input timer 3 count start synchronous circuit input (note 3) (note 3)
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 14 of 156 4518 group port block diagram (6) p 6 0 / a i n 0 , p 6 1/ a i n 1 decoder o p 6 a i n s t r u c t i o n r e g i s t e r a a j a j d a n a l o g i n p u t t q i a p 6 i n s t r u c t i o n q 2 j q 1 ( n o t e 3 ) ( n o t e 1 ) ( n o t e 2 ) this symbol represents a parasitic diode on the port. 2: applied potential to these ports must be v dd or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3. notes 1: p 6 2/ a i n 2 , p 6 3/ a i n 3 decoder op6a instruction register a a k a k d a n a l o g i n p u t t q i a p 6 i n s t r u c t i o n q2 2 q1 ( n o t e 4 ) (note 1) ( n o t e 2 ) ( n o t e 3 )
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 15 of 156 4518 group port block diagram (7) rising falling one-sided edge detection circuit key-on wakeup external 1 interrupt timer 3 count start synchronous circuit level detection circuit edge detection circuit skip decision (snzi1 instruction) both edges detection circuit 0 1 i2 2 0 1 exf1 i2 1 p3 1 /int1 k2 2 i2 3 0 1 k2 3 rising 0 1 falling i1 2 one-sided edge detection circuit key-on wakeup 0 1 exf0 external 0 interrupt i1 1 p3 0 /int0 k2 0 timer 1 count start synchronous circuit i1 3 (note 1) level detection circuit edge detection circuit 0 1 k2 1 skip decision (snzi0 instruction) both edges detection circuit this symbol represents a parasitic diode on the port. notes 1: (note 2) (note 3) (note 1) (note 2) (note 3) 2: i1 2 (i2 2 ) = 0: l level detected i1 2 (i2 2 ) = 1: h level detected 3: i1 2 (i2 2 ) = 0: falling edge detected i1 2 (i2 2 ) = 1: rising edge detected
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 16 of 156 4518 group function block operations cpu (1) arithmetic logic unit (alu) the arithmetic logic unit alu performs 4-bit arithmetic such as 4- bit data addition, comparison, and operation, or operation, and bit manipulation. (2) register a and carry flag register a is a 4-bit register used for arithmetic, transfer, ex- change, and i/o operation. carry flag cy is a 1-bit flag that is set to 1 when there is a carry with the amc instruction (figure 1). it is unchanged with both a n instruction and am instruction. the value of a 0 is stored in carry flag cy with the rar instruction (fig- ure 2). carry flag cy can be set to 1 with the sc instruction and cleared to 0 with the rc instruction. (3) registers b and e register b is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register a. register e is an 8-bit register. it can be used for 8-bit data transfer with register b used as the high-order 4 bits and register a as the low-order 4 bits (figure 3). register e is undefined after system is released from reset and re- turned from the ram back-up. accordingly, set the initial value. (4) register d register d is a 3-bit register. it is used to store a 7-bit rom address together with register a and is used as a pointer within the specified page when the tabp p, bla p, or bmla p instruction is executed. also, when the tabp p instruction is executed, the high-order 2 bits of the reference data in rom is stored to the low-order 2 bits of register d, and the con- tents of the high-order 1 bit of register d is 0. (figure 4). register d is undefined after system is released from reset and re- turned from the ram back-up. accordingly, set the initial value. fig. 1 amc instruction execution example fig. 2 rar instruction execution example fig. 3 registers a, b and register e fig. 4 tabp p instruction execution example ( c y ) ( m ( d p ) ) ( a ) a d d i t i o n a l u < c a r r y > < r e s u l t > c y a 3 a 2 a 1 a 0 a 0 c y a 3 a 2 a 1 < r o t a t i o n > r a r i n s t r u c t i o n < s e t > s c i n s t r u c t i o n < c l e a r > r c i n s t r u c t i o n a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 e 7 e 6 e 5 e 4 e 3 e 2 e 1 e 0 a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 t a b i n s t r u c t i o n t e a b i n s t r u c t i o n t a b e i n s t r u c t i o n t b a i n s t r u c t i o n r e g i s t e r b r e g i s t e r a r e g i s t e r b r e g i s t e r a r e g i s t e r e specifying address tabp p instruction p 6 p 5 p 4 p 3 p 2 p 1 p 0 pc h dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 pc l immediate field value p the contents of register d rom 84 0 middle-order 4 bits low-order 4bits register a (4) register b (4) the contents of register a high-order 2 bits register d (3) high-order 1 bit of register d is 0.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 17 of 156 4518 group (5) stack registers (sk s ) and stack pointer (sp) stack registers (sks) are used to temporarily store the contents of program counter (pc) just before branching until returning to the original routine when; branching to an interrupt service routine (referred to as an inter- rupt service routine), performing a subroutine call, or executing the table reference instruction (tabp p). stack registers (sks) are eight identical registers, so that subrou- tines can be nested up to 8 levels. however, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. accordingly, be care- ful not to over the stack when performing these operations together. the contents of registers sks are destroyed when 8 lev- els are exceeded. the register sk nesting level is pointed automatically by 3-bit stack pointer (sp). the contents of the stack pointer (sp) can be transferred to register a with the tasp instruction. figure 5 shows the stack registers (sks) structure. figure 6 shows the example of operation at subroutine call. (6) interrupt stack register (sdp) interrupt stack register (sdp) is a 1-stage register. when an inter- rupt occurs, this register (sdp) is used to temporarily store the contents of data pointer, carry flag, skip flag, register a, and regis- ter b just before an interrupt until returning to the original routine. unlike the stack registers (sks), this register (sdp) is not used when executing the subroutine call instruction and the table refer- ence instruction. (7) skip flag skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. when an interrupt oc- curs, the contents of skip flag is stored automatically in the interrupt stack register (sdp) and the skip condition is retained. fig. 5 stack registers (sks) structure fig. 6 example of operation at subroutine call s k 0 s k 1 s k 2 s k 3 s k 4 s k 5 s k 6 s k 7 ( s p ) = 0 ( s p ) = 1 ( s p ) = 2 ( s p ) = 3 ( s p ) = 4 ( s p ) = 5 ( s p ) = 6 ( s p ) = 7 p r o g r a m c o u n t e r ( p c ) e x e c u t i n g r t i n s t r u c t i o n e x e c u t i n g b m i n s t r u c t i o n s t a c k p o i n t e r ( s p ) p o i n t s 7 a t r e s e t o r r e t u r n i n g f r o m r a m b a c k - u p m o d e . i t p o i n t s 0 b y e x e c u t i n g t h e f i r s t b m i n s t r u c t i o n , a n d t h e c o n t e n t s o f p r o g r a m c o u n t e r i s s t o r e d i n s k 0 . w h e n t h e b m i n s t r u c t i o n i s e x e c u t e d a f t e r e i g h t s t a c k r e g i s t e r s a r e u s e d ( ( s p ) = 7 ) , ( s p ) = 0 a n d t h e c o n t e n t s o f s k 0 i s d e s t r o y e d . r e t u r n i n g t o t h e b m i n s t r u c t i o n e x e c u t i o n a d d r e s s w i t h t h e r t i n s t r u c t i o n , a n d t h e b m i n s t r u c t i o n b e c o m e s t h e n o p i n s t r u c t i o n . ( s p ) n o t e :
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 18 of 156 4518 group (8) program counter (pc) program counter (pc) is used to specify a rom address (page and address). it determines a sequence in which instructions stored in rom are read. it is a binary counter that increments the number of instruction bytes each time an instruction is executed. however, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table refer- ence instruction (tabp p) is executed. program counter consists of pc h (most significant bit to bit 7) which specifies to a rom page and pc l (bits 6 to 0) which speci- fies an address within a page. after it reaches the last address (address 127) of a page, it specifies address 0 of the next page (figure 7). make sure that the pc h does not specify after the last page of the built-in rom. (9) data pointer (dp) data pointer (dp) is used to specify a ram address and consists of registers z, x, and y. register z specifies a ram file group, reg- ister x specifies a file, and register y specifies a ram digit (figure 8). register y is also used to specify the port d bit position. when using port d, set the port d bit position to register y certainly and execute the sd, rd, or szd instruction (figure 9). note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in the ram back-up. after system is returned from the ram back-up, set these registers. fig. 7 program counter (pc) structure fig. 8 data pointer (dp) structure fig. 9 sd instruction execution example p 5 p 4 p 3 p 2 p 1 p 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 p r o g r a m c o u n t e r p c h s p e c i f y i n g p a g e p c l s p e c i f y i n g a d d r e s s p 6 z 1 z 0 x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 d a t a p o i n t e r ( d p ) r e g i s t e r z ( 2 ) r e g i s t e r x ( 4 ) r e g i s t e r y ( 4 ) s p e c i f y i n g r a m d i g i t s p e c i f y i n g r a m f i l e s p e c i f y i n g r a m f i l e g r o u p 0 0 1 1 s e t s p e c i f y i n g b i t p o s i t i o n p o r t d o u t p u t l a t c h r e g i s t e r y ( 4 ) d 2 d 3 d 1 d 0 0
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 19 of 156 4518 group program memory (rom) the program memory is a mask rom. 1 word of rom is composed of 10 bits. rom is separated every 128 words by the unit of page (addresses 0 to 127). table 1 shows the rom size and pages. fig- ure 10 shows the rom map of m34518m8/e8. table 1 rom size and pages product m34518m2 m34518m4 m34518m6 m34518m8/e8 rom (prom) size ( ? fig. 10 rom map of m34518m8/e8 fig. 11 page 1 (addresses 0080 16 to 00ff 16 ) structure 90 87 654 321 interrupt address page 0 000 16 0080 16 017 f 16 subroutine special page 0 07 f 16 00 ff 16 0100 16 1 fff 16 0180 16 page 1 page 2 page 0 page 3 page 63 9 0 8765 432 1 external 0 interrupt address 0080 16 0082 16 0084 16 timer 1 interrupt address timer 2 interrupt address 0086 16 0088 16 008a 16 008c 16 008e 16 00ff 16 a-d interrupt address external 1 interrupt address timer 3 interrupt address timer 4 interrupt address serial i/o interrupt address
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 20 of 156 4518 group data memory (ram) 1 word of ram is composed of 4 bits, but 1-bit manipulation (with the sb j, rb j, and szb j instructions) is enabled for the entire memory area. a ram address is specified by a data pointer. the data pointer consists of registers z, x, and y. set a value to the data pointer certainly when executing an instruction to access ram (also, set a value after system returns from ram back-up). ram includes the area for lcd. when writing 1 to a bit corresponding to displayed segment, the segment is turned on. table 2 shows the ram size. figure 12 shows the ram map. note register z of data pointer is undefined after system is released from reset. also, registers z, x and y are undefined in the ram back-up. after system is returned from the ram back-up, set these registers. fig. 12 ram map table 2 ram size product m34518m2/m4 m34518m6/m8/e8 ram size 256 words ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 21 of 156 4518 group interrupt function the interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. an interrupt occurs when the following 3 conditions are satisfied. an interrupt activated condition is satisfied (request flag = 1) interrupt enable bit is enabled (1) interrupt enable flag is enabled (inte = 1) table 3 shows interrupt sources. (refer to each interrupt request flag for details of activated conditions.) (1) interrupt enable flag (inte) the interrupt enable flag (inte) controls whether the every inter- rupt enable/disable. interrupts are enabled when inte flag is set to 1 with the ei instruction and disabled when inte flag is cleared to 0 with the di instruction. when any interrupt occurs, the inte flag is automatically cleared to 0, so that other interrupts are disabled until the ei instruction is executed. (2) interrupt enable bit use an interrupt enable bit of interrupt control registers v1 and v2 to select the corresponding interrupt or skip instruction. table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. table 5 shows the interrupt enable bit function. (3) interrupt request flag when the activated condition for each interrupt is satisfied, the cor- responding interrupt request flag is set to 1. each interrupt request flag is cleared to 0 when either; an interrupt occurs, or the next instruction is skipped with a skip instruction. each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the inte flag or its in- terrupt enable bit. once set, the interrupt request flag retains set until a clear condition is satisfied. accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. if more than one interrupt request flag is set when the interrupt dis- able state is released, the interrupt priority level is as follows shown in table 3. table 3 interrupt sources activated condition level change of int0 pin level change of int1 pin timer 1 underflow timer 2 underflow timer 3 underflow timer 4 underflow completion of a-d conversion completion of serial i/o transmit/receive priority level 1 2 3 4 5 6 7 8 interrupt name external 0 interrupt external 1 interrupt timer 1 interrupt timer 2 interrupt timer 3 interrupt timer 4 interrupt a-d interrupt serial i/o interrupt request flag exf0 exf1 t1f t2f t3f t4f adf siof interrupt name external 0 interrupt external 1 interrupt timer 1 interrupt timer 2 interrupt timer 3 interrupt timer 4 interrupt a-d interrupt serial i/o interrupt table 5 interrupt enable bit function occurrence of interrupt enabled disabled skip instruction invalid valid interrupt enable bit 1 0 interrupt address address 0 in page 1 address 2 in page 1 address 4 in page 1 address 6 in page 1 address 8 in page 1 address a in page 1 address c in page 1 address e in page 1 table 4 interrupt request flag, interrupt enable bit and skip in- struction skip instruction snz0 snz1 snzt1 snzt2 snzt3 snzt4 snzad snzsi enable bit v1 0 v1 1 v1 2 v1 3 v2 0 v2 1 v2 2 v2 3
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 22 of 156 4518 group (4) internal state during an interrupt the internal state of the microcomputer during an interrupt is as fol- lows (figure 14). program counter (pc) an interrupt address is set in program counter. the address to be executed when returning to the main routine is automatically stored in the stack register (sk). interrupt enable flag (inte) inte flag is cleared to 0 so that interrupts are disabled. interrupt request flag only the request flag for the current interrupt source is cleared to 0. data pointer, carry flag, skip flag, registers a and b the contents of these registers and flags are stored automatically in the interrupt stack register (sdp). (5) interrupt processing when an interrupt occurs, a program at an interrupt address is ex- ecuted after branching a data store sequence to stack register. write the branch instruction to an interrupt service routine at an in- terrupt address. use the rti instruction to return from an interrupt service routine. interrupt enabled by executing the ei instruction is performed after executing 1 instruction (just after the next instruction is executed). accordingly, when the ei instruction is executed just before the rti instruction, interrupts are enabled after returning the main routine. (refer to figure 13) fig. 13 program example of interrupt processing program counter (pc) ............................................................... each interrupt address stack register (sk) .................................................................................................... interrupt enable flag (inte) .................................................................. 0 (interrupt disabled) interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 data pointer, carry flag, registers a and b, skip flag ........ stored in the interrupt stack register (sdp) automatically the address of main routine to be executed when returning fig. 15 interrupt system diagram fig. 14 internal state when interrupt occurs e i r t i i n t e r r u p t s e r v i c e r o u t i n e i n t e r r u p t o c c u r s i n t e r r u p t i s e n a b l e d m a i n r o u t i n e : i n t e r r u p t e n a b l e d s t a t e : i n t e r r u p t d i s a b l e d s t a t e v1 1 exf0 v1 0 address 2 in page 1 address 4 in page 1 address 0 in page 1 timer 1 underflow timer 2 underflow t1f v1 2 request flag (state retained) enable bit enable flag activated condition v1 3 address 6 in page 1 a-d conversion completed inte adf t2f v2 0 t3f v2 1 siof v2 3 t4f v2 2 int0 pin interrupt waveform input timer 3 underflow timer 4 underflow serial i/o transmit/ receive completed int1 pin interrupt waveform input exf1 address 8 in page 1 address a in page 1 address c in page 1 address e in page 1
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 23 of 156 4518 group (6) interrupt control registers interrupt control register v1 interrupt enable bits of external 0, timer 1 and timer 2 are as- signed to register v1. set the contents of this register through register a with the tv1a instruction. the tav1 instruction can be used to transfer the contents of register v1 to register a. interrupt control register v2 the timer 3, timer 4, a-d and serial i/o interrupt enable bit is as- signed to register v2. set the contents of this register through register a with the tv2a instruction. the tav2 instruction can be used to transfer the contents of register v2 to register a. table 6 interrupt control registers note: r represents read enabled, and w represents write enabled. (7) interrupt sequence interrupts only occur when the respective inte flag, interrupt en- able bits (v1 0 ev1 3 , v2 0 ev2 3 ), and interrupt request flag are 1. the interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. the interrupt occurs after 3 machine cycles only when the three interrupt conditions are sat- isfied on execution of other than one-cycle instructions (refer to figure 16). interrupt disabled (snzsi instruction is valid) interrupt enabled (snzsi instruction is invalid) interrupt disabled (snzad instruction is valid) interrupt enabled (snzad instruction is invalid) interrupt disabled (snzt4 instruction is valid) interrupt enabled (snzt4 instruction is invalid) interrupt disabled (snzt3 instruction is valid) interrupt enabled (snzt3 instruction is invalid) v1 3 v1 2 v1 1 v1 0 v2 3 v2 2 v2 1 v2 0 serial i/o interrupt enable bit a-d interrupt enable bit timer 4 interrupt enable bit timer 3 interrupt enable bit interrupt control register v2 at ram back-up : 0000 2 at reset : 0000 2 0 1 0 1 0 1 0 1 interrupt control register v1 timer 2 interrupt enable bit timer 1 interrupt enable bit external 1 interrupt enable bit external 0 interrupt enable bit interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) interrupt disabled (snz1 instruction is valid) interrupt enabled (snz1 instruction is invalid) interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) 0 1 0 1 0 1 0 1 at ram back-up : 0000 2 at reset : 0000 2 r/w tav1/tv1a r/w tav2/tv2a
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 24 of 156 4518 group fig. 16 interrupt sequence t1f,t2f,t3f,t4f, adf,siof int0,int1 exf0,exf1 t 1 t 2 t 3 t 1 t 2 t 3 t 2 t 3 t 1 t 1 t 2 t 3 t 1 t 2
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 25 of 156 4518 group table 7 external interrupt activated conditions name external 0 interrupt external 1 interrupt input pin p3 0 /int0 p3 1 /int1 activated condition when the next waveform is input to p3 0 /int0 pin ?falling waveform (? fig. 17 external interrupt circuit structure external interrupts the 4518 group has the external 0 interrupt and external 1 inter- rupt. an external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). the external interrupt can be controlled with the interrupt control registers i1 and i2. rising falling one-sided edge detection circuit key-on wakeup external 1 interrupt timer 3 count start synchronous circuit level detection circuit edge detection circuit skip decision (snzi1 instruction) both edges detection circuit 0 1 i2 2 0 1 exf1 i2 1 p 3 1 /int1 k2 2 i2 3 0 1 k2 3 rising 0 1 falling i1 2 one-sided edge detection circuit key-on wakeup 0 1 exf0 external 0 interrupt i1 1 p 3 0 /int0 k2 0 timer 1 count start synchronous circuit i1 3 (note 1) level detection circuit edge detection circuit 0 1 k2 1 skip decision (snzi0 instruction) both edges detection circuit this symbol represents a parasitic diode on the port. notes 1: (note 2) (note 3) (note 1) (note 2) (note 3) 2: i1 2 (i2 2 ) = 0: ??level detected i1 2 (i2 2 ) = 1: ??level detected 3: i1 2 (i2 2 ) = 0: falling edge detected i1 2 (i2 2 ) = 1: rising edge detected
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 26 of 156 4518 group (1) external 0 interrupt request flag (exf0) external 0 interrupt request flag (exf0) is set to ??when a valid waveform is input to p3 0 /int0 pin. the valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (refer to figure 16). the state of exf0 flag can be examined with the skip instruction (snz0). use the interrupt control register v1 to select the interrupt or the skip instruction. the exf0 flag is cleared to ??when an in- terrupt occurs or when the next instruction is skipped with the skip instruction. ?external 0 interrupt activated condition external 0 interrupt activated condition is satisfied when a valid waveform is input to p3 0 /int0 pin. the valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. an example of how to use the external 0 interrupt is as follows. ? ? ? ? ? (2) external 1 interrupt request flag (exf1) external 1 interrupt request flag (exf1) is set to ??when a valid waveform is input to p3 1 /int1 pin. the valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (refer to figure 16). the state of exf1 flag can be examined with the skip instruction (snz1). use the interrupt control register v1 to select the interrupt or the skip instruction. the exf1 flag is cleared to ??when an in- terrupt occurs or when the next instruction is skipped with the skip instruction. ?external 1 interrupt activated condition external 1 interrupt activated condition is satisfied when a valid waveform is input to p3 1 /int1 pin. the valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. an example of how to use the external 1 interrupt is as follows. ? ? ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 27 of 156 4518 group (3) external interrupt control registers ?interrupt control register i1 register i1 controls the valid waveform for the external 0 inter- rupt. set the contents of this register through register a with the ti1a instruction. the tai1 instruction can be used to transfer the contents of register i1 to register a. table 8 external interrupt control register ?interrupt control register i2 register i2 controls the valid waveform for the external 1 inter- rupt. set the contents of this register through register a with the ti2a instruction. the tai2 instruction can be used to transfer the contents of register i2 to register a. i1 3 i1 2 i1 1 i1 0 int0 pin input control bit interrupt valid waveform for int0 pin/ return level selection bit int0 pin edge detection circuit control bit int0 pin timer 1 count start synchronous circuit selection bit interrupt control register i1 r/w tai1/ti1a at ram back-up : state retained at reset : 0000 2 int0 pin input disabled int0 pin input enabled falling waveform/??level (??level is recognized with the snzi0 instruction) rising waveform/??level (??level is recognized with the snzi0 instruction) one-sided edge detected both edges detected timer 1 count start synchronous circuit not selected timer 1 count start synchronous circuit selected 0 1 0 1 0 1 0 1 i2 3 i2 2 i2 1 i2 0 int1 pin input control bit (note 2) interrupt valid waveform for int1 pin/ return level selection bit (note 2) int1 pin edge detection circuit control bit int1 pin timer 3 count start synchronous circuit selection bit interrupt control register i2 r/w tai2/ti2a at ram back-up : state retained at reset : 0000 2 int1 pin input disabled int1 pin input enabled falling waveform/??level (??level is recognized with the snzi1 instruction) rising waveform/??level (??level is recognized with the snzi1 instruction) one-sided edge detected both edges detected timer 3 count start synchronous circuit not selected timer 3 count start synchronous circuit selected 0 1 0 1 0 1 0 1 notes 1: ??represents read enabled, and ??represents write enabled. 2: when the contents of i1 2 , i1 3 i2 2 and i2 3 are changed, the external interrupt request flag (exf0, exf1) may be set.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 28 of 156 4518 group (4) notes on external 0 interrupt ? ? ? ? ??? ? ??? ? ? ? fig. 18 external 0 interrupt program example-1 ? ? ??? ? ? fig. 19 external 0 interrupt program example-2 ? ? ? ? ??? ? ? ? ? fig. 20 external 0 interrupt program example-3
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 29 of 156 4518 group (5) notes on external 1 interrupt ? ? ? ? ?? ? ? ??? ? ? ? fig. 21 external 1 interrupt program example-1 ? ? ? ?? ? ? fig. 22 external 1 interrupt program example-2 ? ? ? ? ?? ? ? ? ? ? fig. 23 external 1 interrupt program example-3
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 30 of 156 4518 group timers the 4518 group has the following timers. programmable timer the programmable timer has a reload register and enables the frequency dividing ratio to be set. it is decremented from a set- ting value n. when it underflows (count to n + 1), a timer interrupt request flag is set to ?,?new data is loaded from the reload reg- ister, and count continues (auto-reload function). fixed dividing frequency timer the fixed dividing frequency timer has the fixed frequency divid- ing ratio (n). an interrupt request flag is set to ??after every n count of a count pulse. fig. 24 auto-reload function the 4518 group timer consists of the following circuits. prescaler : 8-bit programmable timer timer 1 : 8-bit programmable timer timer 2 : 8-bit programmable timer timer 3 : 8-bit programmable timer timer 4 : 8-bit programmable timer watchdog timer : 16-bit fixed dividing frequency timer (timers 1, 2, 3, and 4 have the interrupt function, respectively) prescaler and timers 1, 2, 3, and 4 can be controlled with the timer control registers pa, w1 to w6. the watchdog timer is a free counter which is not controlled with the control register. each function is described below. f f 1 6 n 0 0 1 6 n : c o u n t e r i n i t i a l v a l u e c o u n t s t a r t s r e l o a d r e l o a d 1 s t u n d e r f l o w 2 n d u n d e r f l o w n + 1 c o u n t n + 1 c o u n t t i m e a n i n t e r r u p t o c c u r s o r a s k i p i n s t r u c t i o n i s e x e c u t e d . t i m e r i n t e r r u p t r e q u e s t f l a g t h e c o n t e n t s o f c o u n t e r 1 0
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 31 of 156 4518 group count source ?instruction clock (instck) ?instruction clock (instck) ?prescaler output (orclk) ?x in input ?cntr0 input ?system clock (stck) ?prescaler output (orclk) ?timer 1 underflow (t1udf) ?pwm output (pwmout) ?pwm output (pwmout) ?prescaler output (orclk) ?timer 2 underflow (t2udf) ?cntr1 input ?x in input ?prescaler output (orclk) ?instruction clock (instck) structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to int0 input) (period/pulse width measurement function) 8-bit programmable binary down counter 8-bit programmable binary down counter (link to int1 input) 8-bit programmable binary down counter (pwm output function) 16-bit fixed dividing frequency circuit prescaler timer 1 timer 2 timer 3 timer 4 watchdog timer use of output signal ?timer 1, 2, 3, amd 4 count sources ?timer 2 count source ?cntr0 output ?timer 1 interrupt ?timer 3 count source ?cntr0 output ?timer 2 interrupt ?cntr1 output control ?timer 3 interrupt ?timer 2, 3 count source ?cntr1 output ?timer 4 interrupt ?system reset (count twice) ?wdf flag decision frequency dividing ratio 1 to 256 1 to 256 1 to 256 1 to 256 1 to 256 65534 control register pa w1 w2 w5 w2 w3 w4 table 9 function related timers
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 32 of 156 4518 group fig. 25 timer structure (1) division circuit system clock (stck) instruction clock (instck) multi- plexer (cmck, crck, cyck) (note 1) mr 0 1 0 orclk reload register rps (8) prescaler (8) register b register a (tabps) (tabps) (tpsab) pa 0 mr 3 , mr 2 01 00 10 11 instck w1 1 , w1 0 (note 3) 10 11 01 00 orclk x in t1f (tab1) (tab1) (t1ab) (t1ab) (t1ab) (tpsab) (tpsab) ring oscillator x in ceramic resonance rc oscillation timer 1 (8) timer 1 interrupt reload register r1 (8) register b register a timer 1 underflow signal ( t1udf) internal clock generating circuit (divided by 3) quartz-crystal oscillation w1 2 stck w2 1 , w2 0 10 11 01 00 orclk t1udf pwmout t2f (tab2) (tab2) (t2ab) (t2ab) (t2ab) timer 2 interrupt timer 2 underflow signal (t2udf) timer 2 (8) reload register r2 (8) register b register a w2 2 0 1 w5 2 0 1 i1 2 0 1 p3 0 /int0 w1 3 t1udf i1 0 i1 3 i1 1 one-sided edge detection circuit both edges detection circuit 0 1 i1 0 s r q w5 1 , w5 0 10 11 01 00 w5 2 one-period generation circuit 1/16 ring oscillator 0 1 w6 2 d 6 /cntr0 0 1 w6 0 port d 6 output 0 1 w2 3 1/2 t1udf 1/2 t2udf (note 2) (tr1ab) tr1ab: pwmout: this instruction is used to transfer the contents of register a and register b to only reload register r1. pwm output signal (from timer 4 output unit) data is set automatically from each reload register when timer underflows (auto-reload function). notes 1: when cmck instruction is executed, ceramic resonance is selected. when crck instruction is executed, rc oscillation is selected. when cyck instruction is executed, quartz-crystal oscillator is selected. 2: timer 1 count start synchronous circuit is set by the valid edge of p3 0 /int0 pin selected by bits 1 (i1 1 ) and 2 (i1 2 ) of register i1. 3: x in cannot be used for the count source when bit 1 (mr 1 ) of register mr is set to ??and f(x in ) oscillation is stopped. 0 1 w5 2 divided by 2 divided by 4 divided by 8
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 33 of 156 4518 group fig. 26 timer structure (2) 1 - - - - - - - - - - - - - - 16 watchdog timer instck q r s wdf1 wrst instruction q r s wef dwdt instruction + wrst instruction reset signal q t d r reset signal watchdog reset signal pwmout 0 1 i2 2 0 1 p3 1 /int1 w3 3 t3udf i2 0 i2 3 i2 1 w3 1 , w3 0 10 11 01 00 orclk t2udf t3f (tab3) (tab3) (t3ab) (t3ab) (t3ab) timer 3 (8) timer 3 interrup t reload register r3 (8) register b register a timer 3 underflow signal (t3udf) one-sided edge detection circuit both edges detection circuit w3 2 1 0 w6 3 0 1 i2 0 s r q 1 0 w4 3 pwmod q r d t w3 2 w6 1 t3udf port d 7 output d 7 /cntr1 register b register a reload register r4h (8) (tab4) (tab4) (t4ab) (t4ab) (t4ab) timer 4 (8) reload register r4l (8) register b register a reload control circuit w4 1 1 0 w4 0 1/2 orclk x in ??interval expansion 0 1 w4 2 t4f r q t w4 3 pwmou t (t4hab) (t4r4l) timer 4 interrupt (note 4) (tr3ab) (note 3) (note 5) (note 6) tr3ab: t4r4l: instck: orclk: this instruction is used to transfer the contents of register a and register b to only reload register r3. this instruction is used to transfer the contents of reload register r4l to timer 4. instruction clock (system clock divided by 3) prescaler output (instruction clock divided by 1 to 256) data is set automatically from each reload register when timer underflows (auto-reload function). notes 3: x in cannot be used for the count source when bit 1 (mr 1 ) of register mr is set to ??and f(x in ) oscillation is stopped. 4: timer 3 count start synchronous circuit is set by the valid edge of p3 1 /int1 pin selected by bits 1 (i2 1 ) and 2 (i2 2 ) of register i2. 5: flag wdf1 is cleared to ??and the next instruction is skipped when the wrst instruction is executed while flag wdf1 = ?? the next instruction is not skipped even when the wrst instruction is executed while flag wdf1 = ?? 6: flag wef is cleared to ??and watchdog timer reset does not occur when the dwdt instruction and wrst instruction are executed continuously.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 34 of 156 4518 group notes 1: ??represents read enabled, and ??represents write enabled. 2: this function is valid only when the timer 1 count start synchronous circuit is selected (i1 0 =??. 3: this function is valid only when the timer 3 count start synchronous circuit is selected (i2 0 =??. table 10 timer related registers w2 1 0 0 1 1 timer 1 underflow signal divided by 2 output timer 2 underflow signal divided by 2 output stop (state retained) operating count source system clock (stck) prescaler output (orclk) timer 1 underflow signal (t1udf) pwm signal (pwmout) cntr0 output signal selection bit timer 2 control bit timer 2 count source selection bits 0 1 0 1 w2 0 0 1 0 1 timer control register w2 at ram back-up : state retained at reset : 0000 2 w2 3 w2 2 w2 1 w2 0 w1 1 0 0 1 1 timer 1 count auto-stop circuit not selected timer 1 count auto-stop circuit selected stop (state retained) operating count source instruction clock (instck) prescaler output (orclk) x in input cntr0 input timer 1 count auto-stop circuit selection bit timer 1 control bit timer 1 count source selection bits 0 1 0 1 w1 0 0 1 0 1 timer control register w1 r/w taw1/tw1a at ram back-up : state retained at reset : 0000 2 w1 3 w1 2 w1 1 w1 0 r/w taw2/tw2a w3 1 0 0 1 1 timer 3 count auto-stop circuit not selected timer 3 count auto-stop circuit selected stop (state retained) operating count source pwm signal (pwmout) prescaler output (orclk) timer 2 underflow signal (t2udf) cntr1 input timer 3 count auto-stop circuit selection bit (note 2) timer 3 control bit timer 3 count source selection bits 0 1 0 1 w3 0 0 1 0 1 timer control register w3 at ram back-up : state retained at reset : 0000 2 w3 3 w3 2 w3 1 w3 0 r/w taw3/tw3a 0 1 stop (state initialized) operating prescaler control bit timer control register pa w tpaa at ram back-up : 0 2 at reset : 0 2 pa 0
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 35 of 156 4518 group falling edge rising edge falling edge rising edge cntr1 output auto-control circuit not selected cntr1 output auto-control circuit selected d 6 (i/o) / cntr0 (input) cntr0 (i/o) /d 6 (input) cntr1 pin input count edge selection bit cntr0 pin input count edge selection bit cntr1 output auto-control circuit selection bit d 6 /cntr0 pin function selection bit 0 1 0 1 0 1 0 1 timer control register w6 at ram back-up : state retained at reset : 0000 2 w6 3 w6 2 w6 1 w6 0 d 7 (i/o) / cntr1 (input) cntr1 (i/o) / d 7 (input) pwm signal ??interval expansion function invalid pwm signal ??interval expansion function valid stop (state retained) operating x in input prescaler output (orclk) divided by 2 d 7 /cntr1 pin function selection bit pwm signal ??interval expansion function control bit timer 4 control bit timer 4 count source selection bit 0 1 0 1 0 1 0 1 w4 3 w4 2 w4 1 w4 0 w5 1 0 0 1 1 not used period measurement circuit control bit signal for period measurement selection bits 0 1 0 1 w5 0 0 1 0 1 timer control register w5 at ram back-up : state retained at reset : 0000 2 w5 3 w5 2 w5 1 w5 0 this bit has no function, but read/write is enabled. stop operating count value ring oscillator (f(ring/16)) cntr 0 pin input int0 pin input not available r/w taw4/tw4a timer control register w4 at ram back-up : 0000 2 at reset : 0000 2 r/w taw5/tw5a r/w taw6/tw6a note: ??represents read enabled, and ??represents write enabled.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 36 of 156 4518 group (1) timer control registers timer control register pa register pa controls the count operation of prescaler. set the contents of this register through register a with the tpaa instruc- tion. timer control register w1 register w1 controls the selection of timer 1 count auto-stop cir- cuit, and the count operation and count source of timer 1. set the contents of this register through register a with the tw1a instruc- tion. the taw1 instruction can be used to transfer the contents of register w1 to register a. timer control register w2 register w2 controls the selection of cntr0 output, and the count operation and count source of timer 2. set the contents of this register through register a with the tw2a instruction. the taw2 instruction can be used to transfer the contents of register w2 to register a. timer control register w3 register w3 controls the selection of the count operation and count source of timer 3 count auto-stop circuit. set the contents of this register through register a with the tw3a instruction. the taw3 instruction can be used to transfer the contents of register w3 to register a. timer control register w4 register w4 controls the d 7 /cntr1 output, the expansion of ? interval of pwm output, and the count operation and count source of timer 4. set the contents of this register through regis- ter a with the tw4a instruction. the taw4 instruction can be used to transfer the contents of register w4 to register a. timer control register w5 register w5 controls the period measurement circuit and target signal for period measurement. set the contents of this register through register a with the tw5a instruction. the taw5 instruc- tion can be used to transfer the contents of register w5 to register a. timer control register w6 register w6 controls the count edges of cntr0 pin and cntr1 pin, selection of cntr1 output auto-control circuit and the d 6 / cntr0 pin function. set the contents of this register through reg- ister a with the tw6a instruction. the taw6 instruction can be used to transfer the contents of register w6 to register a.. (2) prescaler prescaler is an 8-bit binary down counter with the prescaler reload register prs. data can be set simultaneously in prescaler and the reload register rps with the tpsab instruction. data can be read from reload register rps with the tabps instruction. stop counting and then execute the tpsab or tabps instruction to read or set prescaler data. prescaler starts counting after the following process; ? ? (3) timer 1 (interrupt function) timer 1 is an 8-bit binary down counter with the timer 1 reload reg- ister (r1). data can be set simultaneously in timer 1 and the reload register (r1) with the t1ab instruction. data can be written to re- load register (r1) with the tr1ab instruction. data can be read from timer 1 with the tab1 instruction. stop counting and then execute the t1ab or tab1 instruction to read or set timer 1 data. when executing the tr1ab instruction to set data to reload regis- ter r1 while timer 1 is operating, avoid a timing when timer 1 underflows. timer 1 starts counting after the following process; ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 37 of 156 4518 group (4) timer 2 (interrupt function) timer 2 is an 8-bit binary down counter with the timer 2 reload reg- ister (r2). data can be set simultaneously in timer 2 and the reload register (r2) with the t2ab instruction. data can be read from timer 2 with the tab2 instruction. stop counting and then execute the t2ab or tab2 instruction to read or set timer 2 data. timer 2 starts counting after the following process; ? ? ? (5) timer 3 (interrupt function) timer 3 is an 8-bit binary down counter with the timer 3 reload reg- ister (r3). data can be set simultaneously in timer 3 and the reload register (r3) with the t3ab instruction. data can be written to re- load register (r3) with the tr3ab instruction. data can be read from timer 3 with the tab3 instruction. stop counting and then execute the t3ab or tab3 instruction to read or set timer 3 data. when executing the tr3ab instruction to set data to reload regis- ter r3 while timer 3 is operating, avoid a timing when timer 3 underflows. timer 3 starts counting after the following process; ? ? ? (6) timer 4 (interrupt function) timer 4 is an 8-bit binary down counter with two timer 4 reload reg- isters (r4l, r4h). data can be set simultaneously in timer 4 and the reload register r4l with the t4ab instruction. data can be set in the reload register r4h with the t4hab instruction. the contents of reload register r4l set with the t4ab instruction can be set to timer 4 again with the t4r4l instruction. data can be read from timer 4 with the tab4 instruction. stop counting and then execute the t4ab or tab4 instruction to read or set timer 4 data. when executing the t4hab instruction to set data to reload regis- ter r4h while timer 4 is operating, avoid a timing when timer 4 underflows. timer 4 starts counting after the following process; ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 38 of 156 4518 group la 0 ; ( ? ?? ? ? ?? ? ? ? fig. 27 period measurement circuit program example (7) period measurement function (timer 1, period measurement circuit) timer 1 has the period measurement circuit which performs timer count operation synchronizing with one cycle of the signal di- vided by 16 of a built-in ring oscillator, d 6 /cntr0 pin input, or p3 0 /int0 pin input (one cycle, ?? or ??pulse width at the case of a p3 0 /int0 pin input). when the target signal for period measurement is set by bits 0 and 1 of register w5, a period measurement circuit is started by setting the bit 2 of register w5 to ?? then, if a x in input is set as the count source of a timer 1 and the bit 2 of register w1 is set to ?? timer 1 starts operation. timer 1 starts operation synchronizing with the falling edge of the target signal for period measurement, and stops count operation synchronizing with the next falling edge (one-period generation circuit). when selecting d 6 /cntr0 pin input as target signal for period measurement, the period measurement synchronous edge can be changed into a rising edge by setting the bit 2 of register w6 to ?? when selecting p3 0 /int0 pin input as target signal for period measurement, period measurement synchronous edge can be changed into a rising edge by setting the bit 2 of register i1 to ?? a timer 1 interrupt request flag (t1f) is set to ??after completing measurement operation. when a period measurement circuit is set to be operating, timer 1 interrupt request flag (t1f) is not set by timer 1 underflow sig- nal, but turns into a flag which detects the completion of period measurement. in addition, a timer 1 underflow signal can be used as timer 2 count source. once period measurement operation is completed, even if period measurement valid edge is input next, timer 1 is in a stop state and measurement data is held. when a period measurement circuit is used again, stop a period measurement circuit at once by setting the bit 2 of register w5 to ?? and change a period measurement circuit into a state of op- eration by setting the bit 2 of register w5 to ??again. when a period measurement circuit is used, clear bit 0 of regis- ter i1 to ?? and set a timer 1 count start synchronous circuit to be ?ot selected? start timer operation immediately after operation of a period measurement circuit is started. when the target edge for measurement is input until timer opera- tion is started from the operation of period measurement circuit is started, the count operation is not executed until the timer opera- tion becomes valid. accordingly, be careful of count data. when data is read from timer, stop the timer and clear bit 2 of register w5 to ??to stop the period measurement circuit, and then execute the data read instruction. depending on the state of timer 1, the timer 1 interrupt request flag (t1f) may be set to ??when the period measurement cir- cuit is stopped by clearing bit 2 of register w5 to ?? in order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register v1 to ??(refer to figure 27 ? ? ? (8) pulse width measurement function (timer 1, period measurement circuit) a period measurement circuit can measure ??pulse width (from rising to falling) or ??pulse width (from falling to rising) of p3 0 / int0 pin input (pulse width measurement function) when the fol- lowing is set; ?set the bit 0 of register w5 to ?? and set a bit 1 to ??(target for period measurement circuit: 3 0 /int0 pin input). ?set the bit 1 of register i1 to ??(int0 pin edge detection circuit: both edges detection) the measurement pulse width (??or ?? is decided by the pe- riod measurement circuit and the p3 0 /int0 pin input level at the start time of timer operation. at the time of the start of a period measurement circuit and timer operation, ??pulse width (from falling to rising) when the input level of p3 0 /int0 pin is ??or ??pulse width (from rising to fall- ing) when its level is ??is measured. when the input of p3 0 /int0 pin is selected as the target for mea- surement, set the bit 3 of register i1 to ?? and set the input of int0 pin to be enabled.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 39 of 156 4518 group (11) timer input/output pin (d 6 /cntr0 pin, d 7 /cntr1 pin) cntr0 pin is used to input the timer 1 count source and output the timer 1 and timer 2 underflow signal divided by 2. cntr1 pin is used to input the timer 3 count source and output the pwm signal generated by timer 4. the d 6 /cntr0 pin function can be selected by bit 0 of register w6. the selection of d 7 /cntr1 output signal can be controlled by bit 3 of register w4. when the cntr0 input is selected for timer 1 count source, timer 1 counts the rising or falling waveform of cntr0 input. the count edge is selected by the bit 2 of register w6. when the cntr1 input is selected for timer 3 count source, timer 3 counts the rising or falling waveform of cntr1 input. the count edge is selected by the bit 3 of register w6. (12) pwm output function (d 7 /cntr1, timer 3, timer 4) when bit 3 of register w4 is set to ?? timer 4 reloads data from re- load register r4l and r4h alternately each underflow. timer 4 generates the pwm signal (pwmout) of the ??interval set as reload register r4l, and the ??interval set as reload regis- ter r4h. the pwm signal (pwmout) is output from cntr1 pin. when bit 2 of register w4 is set to ??at this time, the interval (pwm signal ??interval) set to reload register r4h for the counter of timer 4 is extended for a half period of count source. in this case, when a value set in reload register r4h is n, timer 4 divides the count source signal by n + 1.5 (n = 1 to 255). when this function is used, set ??or more to reload register r4h. when bit 1 of register w6 is set to ?? the pwm signal output to cntr1 pin is switched to valid/invalid each timer 3 underflow. however, when timer 3 is stopped (bit 2 of register w3 is cleared to ??, this function is canceled. even when bit 1 of a register w4 is cleared to ??in the ??interval of pwm signal, timer 4 does not stop until it next timer 4 underflow. when clearing bit 1 of register w4 to ??to stop timer 4, avoid a timing when timer 4 underflows. (9) count start synchronization circuit (timer 1, timer 3) timer 1 and timer 3 have the count start synchronous circuit which synchronizes the input of int0 pin and int1 pin, and can start the timer count operation. timer 1 count start synchronous circuit function is selected by set- ting the bit 0 of register i1 to ??and the control by int0 pin input can be performed. timer 3 count start synchronous circuit function is selected by set- ting the bit 0 of register i2 to ??and the control by int1 pin input can be performed. when timer 1 or timer 3 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to int0 pin or int1 pin. the valid waveform of int0 pin or int1 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. once set, the count start synchronous circuit is cleared by clearing the bit i1 0 or i2 0 to ??or reset. however, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 or timer 3 underflow. (10) count auto-stop circuit (timer 1, timer 3) timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start syn- chronous circuit is used. the count auto-stop cicuit is valid by setting the bit 3 of register w1 to ?? it is cleared by the timer 1 underflow and the count source to timer 1 is stopped. this function is valid only when the timer 1 count start synchronous circuit is selected. timer 3 has the count auto-stop circuit which is used to stop timer 3 automatically by the timer 3 underflow when the count start syn- chronous circuit is used. the count auto-stop cicuit is valid by setting the bit 3 of register w3 to ?? it is cleared by the timer 3 underflow and the count source to timer 3 is stopped. this function is valid only when the timer 3 count start synchronous circuit is selected.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 40 of 156 4518 group (13) timer interrupt request flags (t1f, t2f, t3f, t4f) each timer interrupt request flag is set to ??when each timer underflows. the state of these flags can be examined with the skip instructions (snzt1, snzt2, snzt3, snzt4). use the interrupt control register v1, v2 to select an interrupt or a skip instruction. an interrupt request flag is cleared to ??when an interrupt occurs or when the next instruction is skipped with a skip instruction. the timer 1 interrupt request flag (t1f) is not set by the timer 1 under- flow signal, it is the flag for detecting the completion of period measurement. (14) precautions note the following for the use of timers. prescaler stop counting and then execute the tabps instruction to read from prescaler data. stop counting and then execute the tpsab instruction to set prescaler data. timer count source stop timer 1, 2, 3 and 4 counting to change its count source. reading the count value stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (tab1, tab2, tab3, tab4) to read its data. writing to the timer stop timer 1, 2, 3 or 4 counting and then execute the data write instruction (t1ab, t2ab, t3ab, t4ab) to write its data. writing to reload register r1, r3, r4h when writing data to reload register r1, reload register r3 or re- load regiser r4h while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows. timer 4 avoid a timing when timer 4 underflows to stop timer 4. when ??interval extension function of the pwm signal is set to be ?alid? set ??or more to reload register r4h. ?period measurement function when a period measurement circuit is used, clear bit 0 of regis- ter i1 to ?? and set a timer 1 count start synchronous circuit to be ?ot selected? start timer operation immediately after operation of a period measurement circuit is started. when the target edge for measurement is input until timer opera- tion is started from the operation of period measurement circuit is started, the count operation is not executed until the timer opera- tion becomes valid. accordingly, be careful of count data. when data is read from timer, stop the timer and clear bit 2 of register w5 to ??to stop the period measurement circuit, and then execute the data read instruction. depending on the state of timer 1, the timer 1 interrupt request flag (t1f) may be set to ??when the period measurement cir- cuit is stopped by clearing bit 2 of register w5 to ?? in order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register v1 to ??(refer to figure 28 ? ? ? ? ?? ? ? ?? ? ? ? fig. 28 period measurement circuit program example while a period measurement circuit is operating, the timer 1 in- terrupt request flag (t1f) is not set by the timer 1 underflow signal, it is the flag for detecting the completion of period mea- surement. when a period measurement circuit is used, select the suffi- ciently higher-speed frequency than the signal for measurement for the count source of a timer 1. when the target signal for period measurement is d 6 /cntr0 pin input, do not select d 6 /cntr0 pin input as timer 1 count source. (the x in input is recommended as timer 1 count source at the time of period measurement circuit use.) when the input of p3 0 /int0 pin is selected for measurement, set the bit 3 of a register i1 to ?? and set the input of int0 pin to be enabled.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 41 of 156 4518 group fig. 29 timer 4 operation (reload register r4l: ?3 16 ? r4h: ?2 16 ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 42 of 156 4518 group fig. 30 cntr1 output auto-control function by timer 3 c ntr1 output auto-control circuit by timer 3 is selected. cntr1 output register w6 1 when the cntr1 output auto-control function is set to be invalid while the cntr1 output is invalid, the cntr1 output invalid state is retained. when the cntr1 output auto-control function is set to be invalid while the cntr1 output is valid, the cntr1 output valid state is retained. when timer 3 is stopped, the cntr1 output auto-control function becomes invalid. ? ? ? ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 43 of 156 4518 group fig. 31 timer 4 count start/stop timing (r4l) (r4h) (r4l) timer 4 count start timing waveform extension function of cntr1 output ??interval: invalid (w4 2 = ??, cntr1 output: valid (w4 3 = ??, count source: x in input selected (w4 0 = ??, reload register r4l: ?3 16 reload register r4h: ?2 16 timer 4 count start timing tw4a instruction execution cycle (w4 1 )
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 44 of 156 4518 group watchdog timer watchdog timer provides a method to reset the system when a pro- gram run-away occurs. watchdog timer consists of timer wdt(16-bit binary counter), watchdog timer enable flag (wef), and watchdog timer flags (wdf1, wdf2). the timer wdt downcounts the instruction clocks as the count source from ?fff 16 ?after system is released from reset. after the count is started, when the timer wdt underflow occurs (after the count value of timer wdt reaches ?000 16 ,?the next count pulse is input), the wdf1 flag is set to ?. if the wrst instruction is never executed until the timer wdt un- derflow occurs (until timer wdt counts 65534), wdf2 flag is set to ?,?and the reset pin outputs ??level to reset the microcom- puter. execute the wrst instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. when the wef flag is set to ??after system is released from reset, the watchdog timer function is valid. when the dwdt instruction and the wrst instruction are ex- ecuted continuously, the wef flag is cleared to ??and the watchdog timer function is invalid. however, in order to set the wef flag to ??again once it has cleared to ?? execute system reset. the wrst instruction has the skip function. when the wrst in- struction is executed while the wdf1 flag is ?? the wdf1 flag is cleared to ??and the next instruction is skipped. when the wrst instruction is executed while the wdf1 flag is ?? the next instruction is not skipped. the skip function of the wrst instruction can be used even when the watchdog timer function is invalid. fig. 32 watchdog timer function 6 5 5 3 4 c o u n t ( n o t e ) v a l u e o f 1 6 - b i t t i m e r ( w d t ) w d f 1 f l a g ? ? ? ? ? ? ? ? ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 45 of 156 4518 group fig. 33 program example to start/stop watchdog timer fig. 34 program example to enter the mode when using the watchdog timer wrst ; wdf1 flag cleared dwdt ; w atchdog timer function enabled/disabled wrst ; wef and wdf1 flags cleared wrst ; wdf1 flag cleared nop di ; interrupt disabled epof ; pof instruction enabled pof
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 46 of 156 4518 group v ss v dd iap6 (p6 0 p6 3 ) op6a (p6 0 p6 3 ) tabad q1 3 q2 1 q2 0 q2 2 tadab q1 2 q1 1 q1 0 0 1 4 4 4 4 8 8 8 01 1 8 10 q1 3 q1 3 0 1 q1 3 8 8 2 tala q1 3 q2 3 taq2 tq2a taq1 tq1a adf (1) p 6 0 /a in0 3 1 0 10 p 6 1 /a in1 p 6 2 /a in2 p 6 3 /a in3 4 4 q3 1 q3 0 q3 2 q3 3 taq3 tq3a 4 da converter (note 1) register a (4) register b (4) dac operation signal comparator 4-channel multi-plexed analog switch instruction clock a-d control circuit successive comparison register (ad) (10) a-d interrup t comparator register (8) notes 1: this switch is turned on only when a-d converter is operating and generates the comparison voltage. 2: writing/reading data to the comparator register is possible only in the comparator mode (q1 3 =1). the value of the comparator register is retained even when the mode is switched to the a-d conversion mode (q1 3 =0) because it is separated from the successive comparison register (ad). also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. (note 2) 11 q3 1 , q3 0 10 01 00 0 1 q3 2 ring oscillator clock a-d conversion clock (adck) division circuit divided by 48 divided by 24 divided by 12 divided by 6 a-d converter (comparator) the 4518 group has a built-in a-d conversion circuit that performs conversion by 10-bit successive comparison method. table 11 shows the characteristics of this a-d converter. this a-d converter can also be used as an 8-bit comparator to compare analog volt- ages input from the analog input pin with preset values. table 11 a-d converter characteristics characteristics successive comparison method 10 bits linearity error: ?lsb (2.7 v fig. 35 a-d conversion circuit structure
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 47 of 156 4518 group table 12 a-d control registers q1 2 0 0 0 0 1 1 1 1 a-d operation mode selection bit analog input pin selection bits q1 1 0 0 1 1 0 0 1 1 a-d control register q1 at ram back-up : state retained at reset : 0000 2 q1 3 a-d conversion mode comparator mode r/w taq1/tq1a q1 0 0 1 0 1 0 1 0 1 q1 2 q1 1 q1 0 analog input pins a in0 a in1 a in2 a in3 not available not available not available not available this bit has no function, but read/write is enabled. p6 2 , p6 3 a in2 , a in3 p6 1 a in1 p6 0 a in0 not used p6 2 /a in2 , p6 3 /a in3 pin function selection bit p6 1 /a in1 pin function selection bit p6 0 /a in0 pin function selection bit 0 1 0 1 0 1 0 1 q2 3 q2 2 q2 1 q2 0 r/w taq2/tq2a a-d control register q2 at ram back-up : state retained at reset : 0000 2 note: ??represents read enabled, and ??represents write enabled. not used a-d converter operation clock selection bit a-d converter operation clock division ratio selection bits a-d control register q3 q3 3 q3 2 q3 1 q3 0 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 q3 1 0 0 1 1 q3 0 0 1 0 1 division ratio frequency divided by 6 frequency divided by 12 frequency divided by 24 frequency divided by 48 this bit has no function, but read/write is enabled. instruction clock (instck) ring oscillator (f(ring)) r/w taq3/tq3a
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 48 of 156 4518 group (1) a-d control register a-d control register q1 register q1 controls the selection of a-d operation mode and the selection of analog input pins. set the contents of this register through register a with the tq1a instruction. the taq1 instruc- tion can be used to transfer the contents of register q1 to register a. a-d control register q2 register q2 controls the selection of p6 0 /a in0 ?6 3 /a in3 . set the contents of this register through register a with the tq2a instruc- tion. the taq2 instruction can be used to transfer the contents of register q2 to register a. a-d control register q3 register q3 controls the selection of a-d converter operation clock . set the contents of this register through register a with the tq3a instruction. the taq3 instruction can be used to transfer the contents of register q3 to register a. (2) operating at a-d conversion mode the a-d conversion mode is set by setting the bit 3 of register q1 to ?. (3) successive comparison register ad register ad stores the a-d conversion result of an analog input in 10-bit digital data format. the contents of the high-order 8 bits of this register can be stored in register b and register a with the tabad instruction. the contents of the low-order 2 bits of this reg- ister can be stored into the high-order 2 bits of register a with the tala instruction. however, do not execute these instructions dur- ing a-d conversion. when the contents of register ad is n, the logic value of the com- parison voltage v ref generated from the built-in da converter can be obtained with the reference voltage v dd by the following for- mula: logic value of comparison voltage v ref v ref = ? (4) a-d conversion completion flag (adf) a-d conversion completion flag (adf) is set to ??when a-d con- version completes. the state of adf flag can be examined with the skip instruction (snzad). use the interrupt control register v2 to select the interrupt or the skip instruction. the adf flag is cleared to ??when the interrupt occurs or when the next instruction is skipped with the skip instruction. (5) a-d conversion start instruction (adst) a-d conversion starts when the adst instruction is executed. the conversion result is automatically stored in the register ad. (6) operation description a-d conversion is started with the a-d conversion start instruction (adst). the internal operation during a-d conversion is as follows: ? ? ? table 13 change of successive comparison register ad during a-d conversion comparison voltage (v ref ) value change of successive comparison register ad at starting conversion ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 49 of 156 4518 group fig. 37 setting registers a-d control register q2 a in0 pin function selected ??? (7) a-d conversion timing chart figure 36 shows the a-d conversion timing chart. fig. 36 a-d conversion timing chart (8) how to use a-d conversion how to use a-d conversion is explained using as example in which the analog input from p6 0 /a in0 pin is a-d converted, and the high- order 4 bits of the converted data are stored in address m(z, x, y) = (0, 0, 0), the middle-order 4 bits in address m(z, x, y) = (0, 0, 1), and the low-order 2 bits in address m(z, x, y) = (0, 0, 2) of ram. the a-d interrupt is not used in this example. instruction clock/6 is selected as the a-d converter operation clock. ? ? ? ? ? ? ? ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 50 of 156 4518 group (9) operation at comparator mode the a-d converter is set to comparator mode by setting bit 3 of the register q1 to ?. below, the operation at comparator mode is described. (10) comparator register in comparator mode, the built-in da comparator is connected to the 8-bit comparator register as a register for setting comparison volt- ages. the contents of register b is stored in the high-order 4 bits of the comparator register and the contents of register a is stored in the low-order 4 bits of the comparator register with the tadab in- struction. when changing from a-d conversion mode to comparator mode, the result of a-d conversion (register ad) is undefined. however, because the comparator register is separated from regis- ter ad, the value is retained even when changing from comparator mode to a-d conversion mode. note that the comparator register can be written and read at only comparator mode. if the value in the comparator register is n, the logic value of com- parison voltage v ref generated by the built-in da converter can be determined from the following formula: (11) comparison result store flag (adf) in comparator mode, the adf flag, which shows completion of a-d conversion, stores the results of comparing the analog input volt- age with the comparison voltage. when the analog input voltage is lower than the comparison voltage, the adf flag is set to ?.?the state of adf flag can be examined with the skip instruction (snzad). use the interrupt control register v2 to select the inter- rupt or the skip instruction. the adf flag is cleared to ??when the interrupt occurs or when the next instruction is skipped with the skip instruction. (12) comparator operation start instruction (adst instruction) in comparator mode, executing adst starts the comparator oper- ating. the comparator stops 2 machine cycles + a-d conversion clock f(adck) 1 clock after it has started (4 (13) notes for the use of a-d conversion tala instruction when the tala instruction is executed, the low-order 2 bits of register ad is transferred to the high-order 2 bits of register a, si- multaneously, the low-order 2 bits of register a is ?. ?operation mode of a-d converter do not change the operating mode (both a-d conversion mode and comparator mode) of a-d converter with the bit 3 of register q1 while the a-d converter is operating. clear the bit 2 of register v2 to ??to change the operating mode of the a-d converter from the comparator mode to a-d conver- sion mode. the a-d conversion completion flag (adf) may be set when the operating mode of the a-d converter is changed from the com- parator mode to the a-d conversion mode. accordingly, set a value to the register q1, and execute the snzad instruction to clear the adf flag. logic value of comparison voltage v ref v ref = ? fig. 38 comparator operation timing chart v dd 256 adst instruction comparison result store flag(adf) 2 machine cycles + 1/f(adck) dac operation signal comparator operation completed . (the value of adf is determined)
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 51 of 156 4518 group (14) definition of a-d converter accuracy the a-d conversion accuracy is defined below (refer to figure 39). relative accuracy ? ? ? ? fig. 39 definition of a-d conversion accuracy v fst ? 0t 1022 v dd 1024 vn: analog input voltage when the output data changes from ??to ?+1?(n = 0 to 1022) ?1lsb at relative accuracy
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 52 of 156 4518 group serial i/o the 4518 group has a built-in clock synchronous serial i/o which can serially transmit or receive 8-bit data. serial i/o consists of; ?serial i/o register si ?serial i/o control register j1 ?serial i/o transmit/receive completion flag (siof) ?serial i/o counter registers a and b are used to perform data transfer with internal cpu, and the serial i/o pins are used for external data transfer. the pin functions of the serial i/o pins can be set with the register j1. table 14 serial i/o pins pin p2 0 /s ck p2 1 /s out p2 2 /s in pin function when selecting serial i/o clock i/o (s ck ) serial data output (s out ) serial data input (s in ) fig. 40 serial i/o structure table 15 serial i/o control register note: ??represents read enabled, and ??represents write enabled. note: even when the s ck , s out , s in pin functions are used, the input of p2 0 , p2 1 , p2 2 are valid. 1/8 1/4 1/2 00 01 10 11 synchronous circuit serial i/o counter (3) siof serial i/o interrupt instck p2 0 /s ck s ck qs r msb serial i/o register (8) lsb s in j1 1 j1 0 j1 3 j1 2 register b (4) register a (4) tsiab tabsi tabsi s out p2 1 /s out p2 2 /s in sst instruction internal reset signal j1 3 0 0 1 1 j1 1 0 0 1 1 serial i/o synchronous clock selection bits serial i/o port function selection bits j1 2 0 1 0 1 j1 0 0 1 0 1 serial i/o control register j1 at ram back-up : state retained at reset : 0000 2 j1 3 j1 2 j1 1 j1 0 synchronous clock instruction clock (instck) divided by 8 instruction clock (instck) divided by 4 instruction clock (instck) divided by 2 external clock (s ck input) port function p2 0 , p2 1 ,p2 2 selected/s ck , s out , s in not selected s ck , s out , p2 2 selected/p2 0 , p2 1 , s in not selected s ck , p2 1 , s in selected/p2 0 , s out , p2 2 not selected s ck , s out , s in selected/p2 0 , p2 1 ,p2 2 not selected r/w taj1/tj1a
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 53 of 156 4518 group fig. 41 serial i/o register state when transferring (1) serial i/o register si serial i/o register si is the 8-bit data transfer serial/parallel conver- sion register. data can be set to register si through registers a and b with the tsiab instruction. the contents of register a is transmit- ted to the low-order 4 bits of register si, and the contents of register b is transmitted to the high-order 4 bits of register si. during transmission, each bit data is transmitted lsb first from the lowermost bit (bit 0) of register si, and during reception, each bit data is received lsb first to register si starting from the topmost bit (bit 7). when register si is used as a work register without using serial i/o, do not select the s ck pin. (2) serial i/o transmit/receive completion flag (siof) serial i/o transmit/receive completion flag (siof) is set to ??when serial data transmission or reception completes. the state of siof flag can be examined with the skip instruction (snzsi). use the in- terrupt control register v2 to select the interrupt or the skip instruction. the siof flag is cleared to ??when the interrupt occurs or when the next instruction is skipped with the skip instruction. (3) serial i/o start instruction (sst) when the sst instruction is executed, the siof flag is cleared to ??and then serial i/o transmission/reception is started. (4) serial i/o control register j1 register j1 controls the synchronous clock, p2 0 /s ck , p2 1 /s out and p2 2 /s in pin function. set the contents of this register through register a with the tj1a instruction. the taj1 instruction can be used to transfer the contents of register j1 to register a. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a t t r a n s m i t ( d 7 d 0 : t r a n s f e r d a t a ) a t r e c e i v e d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 s i n p i n s o u t p i n s o u t p i n s i n p i n s e r i a l i / o r e g i s t e r ( s i ) s e r i a l i / o r e g i s t e r ( s i ) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 * d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 7 d 6 d 5 d 4 d 3 d 2 d 0 d 1 d 0 t r a n s f e r d a t a s e t t r a n s f e r s t a r t t r a n s f e r c o m p l e t e * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 54 of 156 4518 group (5) how to use serial i/o figure 42 shows the serial i/o connection example. serial i/o inter- rupt is not used in this example. in the actual wiring, pull up the wiring between each pin with a resistor. figure 42 shows the data transfer timing and table 16 shows the data transfer sequence. fig. 42 serial i/o connection example s o u t s r d y s i g n a l s c k s i n d 3 s c k s o u t s i n d 3 m a s t e r ( c l o c k c o n t r o l ) s e r i a l i / o i n t e r r u p t e n a b l e b i t ( s n z s i i n s t r u c t i o n v a l i d ) i n t e r r u p t c o n t r o l r e g i s t e r v 2 s e r i a l i / o c o n t r o l r e g i s t e r j 1 s e r i a l i / o p o r t s c k , s o u t , s i n i n s t r u c t i o n c l o c k / 8 s e l e c t e d a s s y n c h r o n o u s c l o c k s l a v e ( e x t e r n a l c l o c k ) s e r i a l i / o i n t e r r u p t e n a b l e b i t ( s n z s i i n s t r u c t i o n v a l i d ) ? ? ? ? ?? ? fig. 43 timing of serial i/o data transfer m 0 m 7 : c o n t e n t s o f m a s t e r s e r i a l i / o r e g i s t e r s 0 s 7 : c o n t e n t s o f s l a v e s e r i a l i / o r e g i s t e r r i s i n g o f s c k : s e r i a l i n p u t f a l l i n g o f s c k : s e r i a l o u t p u t s i n s o u t m a s t e r s l a v e s c k s s t i n s t r u c t i o n s o u t s i n s 0 s 7 s 1 s 2 s 3 s 4 s 5 s 6 s 7 s s t i n s t r u c t i o n s r d y s i g n a l s 0 s 7 s 1 s 3 s 4 s 5 s 6 s 7 m 0 m 7 m 1 m 2 m 3 m 4 m 5 m 6 m 7 m 0 m 7 m 1 m 2 m 3 m 4 m 5 m 6 m 7 s 2
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 55 of 156 4518 group table 16 processing sequence of data transfer from master to slave 1-byte data is serially transferred on this process. subsequently, data can be transferred continuously by repeating the process from *. when an external clock is selected as a synchronous clock, the clock is not controlled internally. control the clock externally be- cause serial transfer is performed as long as clock is externally input. (unlike an internal clock, an external clock is not stopped when serial transfer is completed.) however, the siof flag is set to ??when the clock is counted 8 times after executing the sst in- struction. be sure to set the initial level of the external clock to ?. master (transmission) [initial setting] ?setting the serial i/o mode register j1 and inter- rupt control register v2 shown in figure 42. tj1a and tv2a instructions ?setting the port received the reception enable signal (s rdy ) to the input mode. (port d 3 is used in this example) sd instruction * [transmission enable state] ?storing transmission data to serial i/o register si. tsiab instruction [transmission] ?heck port d 3 is ??level. szd instruction ?erial transfer starts. sst instruction ?heck transmission completes. snzsi instruction ?ait (timing when continuously transferring) slave (reception) [initial setting] ?setting serial i/o mode register j1, and interrupt control register v2 shown in figure 42. tj1a and tv2a instructions ?setting the port transmitted the reception enable signal (s rdy ) and outputting ??level (reception impossible). (port d 3 is used in this example) sd instruction *[reception enable state] ?the siof flag is cleared to ?. sst instruction ???level (reception possible) is output from port d 3 . rd instruction [reception] ?check reception completes. snzsi instruction ???level is output from port d 3 . sd instruction [data processing]
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 56 of 156 4518 group reset function system reset is performed by applying ??level to reset pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. then when ??level is applied to reset pin, software starts from address 0 in page 0. fig. 44 reset release timing fig. 45 reset pin input waveform and reset operation f(ring) reset program starts (address 0 in page 0) ring oscillator (internal oscillator) is counted 120 to 144 times. note: the number of clock cycles depends on the internal state of the microcomputer when reset is performed. reset 0.3v dd 0 .85v dd ( note ) note: keep the value of supply voltage to the minimum value or more of the recommended operating conditions. reset input 1 machine cycle or more = program starts (address 0 in page 0) ring oscillator (internal oscillator) is counted 120 to 144 times.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 57 of 156 4518 group fig. 46 structure of reset pin and its peripherals,, and power-on reset operation name d 0 ? 5 d 6 /cntr0 d 7 /cntr1 p0 0 ?0 3 p1 0 ?1 3 p2 0 /s ck , p2 1 /s out , p2 2 /s in p3 0 /int0, p3 1 /int1 p6 0 /a in0 ?6 3 /a in3 notes 1: output latch is set to ?. 2: output structure is n-channel open-drain. 3: pull-up transistor is turned off. function d 0 ? 5 d 6 d 7 p0 0 ?0 3 p1 0 ?1 3 p2 0 ?2 2 p3 0 , p3 1 p6 0 ?6 3 state high-impedance (notes 1, 2) high-impedance (notes 1, 2) high-impedance (notes 1, 2) high-impedance (notes 1, 2, 3) high-impedance (notes 1, 2, 3) high-impedance (note 1) high-impedance (note 1) high-impedance (note 1) (1) power-on reset reset can be automatically performed at power on (power-on re- set) by the built-in power-on reset circuit. when the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 v until the value of supply voltage reaches the minimum operating voltage must be set to 100 table 1 port state at reset r eset pin wef watchdog reset signal (note 1) pull-up transistor (note 1) power-on reset circuit voltage drop detection circuit v dd (note 3) 100 notes 1: this symbol represents a parasitic diode. 2: applied potential to reset pin must be v dd or less. 3: keep the value of supply voltage to the minimum value or more of the recommended operating conditions. power-on reset circuit output
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 58 of 156 4518 group ?program counter (pc) ......................................................................................................... . address 0 in page 0 is set to program counter. ?interrupt enable flag (inte) .................................................................................................. ?power down flag (p) .......................................................................................................... ... ?external 0 interrupt request flag (exf0) .............................................................................. ?external 1 interrupt request flag (exf1) .............................................................................. ?interrupt control register v1 ................................................................................................ .. ?interrupt control register v2 ................................................................................................ .. ?interrupt control register i1 ................................................................................................ ... ?interrupt control register i2 ................................................................................................ ... ?timer 1 interrupt request flag (t1f) ..................................................................................... ?timer 2 interrupt request flag (t2f) ..................................................................................... ?timer 3 interrupt request flag (t3f) ..................................................................................... ?timer 4 interrupt request flag (t4f) ..................................................................................... ?watchdog timer flags (wdf1, wdf2) .................................................................................. ?watchdog timer enable flag (wef) ...................................................................................... ?timer control register pa .................................................................................................... .. ?timer control register w1 .................................................................................................... . ?timer control register w2 .................................................................................................... . ?timer control register w3 .................................................................................................... . ?timer control register w4 .................................................................................................... . ?timer control register w5 .................................................................................................... . ?timer control register w6 .................................................................................................... . ?clock control register mr .................................................................................................... . ?clock control register rg .................................................................................................... . ?serial i/o transmit/receive completion flag (siof) .............................................................. ?serial i/o mode register j1 .................................................................................................. ?serial i/o register si ....................................................................................................... ...... ?a-d conversion completion flag (adf) ................................................................................. ?a-d control register q1 ...................................................................................................... ... ?a-d control register q2 ...................................................................................................... ... ?a-d control register q3 ...................................................................................................... ... ?successive approximation register ad ................................................................................ ?comparator register .......................................................................................................... .... ?key-on wakeup control register k0 ...................................................................................... ?key-on wakeup control register k1 ...................................................................................... ?key-on wakeup control register k2 ...................................................................................... ?pull-up control register pu0 ................................................................................................. ?pull-up control register pu1 ................................................................................................. ? fig. 47 internal state at reset 1 (2) internal state at reset figure 47 and 48 show internal state at reset (they are the same af- ter system is released from reset). the contents of timers, registers, flags and ram except shown in figure are undefined, so set the initial value to them. 00000000000000 0 (interrupt disabled) 0 0 0 0 0 0 0 (interrupt disabled) 0 0 0 0 (interrupt disabled) 0000 0000 0 0 0 0 0 1 0 (prescaler stopped) 0 0 0 0 (timer 1 stopped) 0 0 0 0 (timer 2 stopped) 0 0 0 0 (timer 3 stopped) 0 0 0 0 (timer 4 stopped) 0000( period measurement circuit stopped ) 0000 1111 0 (ring oscillator operating) 0 0 0 0 0 (external clock selected, serial i/o port not selected) ?????? ?????? ?????? ?? ? ??? ??
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 59 of 156 4518 group ?port output structure control register fr0 ........................................................................... ?port output structure control register fr1 ........................................................................... ?port output structure control register fr2 ........................................................................... ?carry flag (cy) .............................................................................................................. ........ ?register a ................................................................................................................... .......... ?register b ................................................................................................................... .......... ?register d ............................................................................................................................. ?register e ................................................................................................................... .......... ?register x ................................................................................................................... .......... ?register y ................................................................................................................... .......... ?register z ................................................................................................................... .......... ?stack pointer (sp) ........................................................................................................... ..... ?operation source clock ............................................................... ring oscillator (operating) ?ceramic resonator circuit .............................................................................................. stop ?rc oscillation circuit ...................................................................................................... stop ?quartz-crystal oscillation circuit .................................................................................... stop ? fig. 48 internal state at reset 2 ?? ??? ?????? ??
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 60 of 156 4518 group voltage drop detection circuit the built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. fig. 49 voltage drop detection reset circuit fig. 50 voltage drop detection circuit operation waveform table 17 voltage drop detection circuit operation state vdce pin l h at cpu operating invalid valid at ram back-up invalid valid + e v rst v rst + - vdce voltage drop detection circuit reset signal voltage drop detection circuit v rst (reset release voltage) + - v dd voltage drop detection circuit reset signal microcomupter starts operation after ring oscillator (internal oscillator) clock is counted 120 to 144 times. v rst (reset voltage) reset pin note: detection voltage hysteresis of voltage drop detection circuit is 0.2 v (typ).
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 61 of 156 4518 group ram back-up mode the 4518 group has the ram back-up mode. when the epof and pof instructions are executed continuously, system enters the ram back-up state. the pof instruction is equal to the nop instruction when the epof instruction is not ex- ecuted before the pof instruction. as oscillation stops retaining ram, the function of reset circuit and states at ram back-up mode, current dissipation can be reduced without losing the contents of ram. table 18 shows the function and states retained at ram back-up. figure 51 shows the state transition. (1) identification of the start condition warm start (return from the ram back-up state) or cold start (re- turn from the normal reset state) can be identified by examining the state of the ram back-up flag (p) with the snzp instruction. (2) warm start condition when the external wakeup signal is input after the system enters the ram back-up state by executing the epof and pof instruc- tions continuously, the cpu starts executing the program from address 0 in page 0. in this case, the p flag is 1. (3) cold start condition the cpu starts executing the program from address 0 in page 0 when; reset pulse is input to reset pin, or reset by watchdog timer is performed, or voltage drop detection circuit detects the voltage drop, or srst instruction is executed. in this case, the p flag is 0. table 18 functions and states retained at ram back-up function program counter (pc), registers a, b, carry flag (cy), stack pointer (sp) (note 2) contents of ram interrupt control registers v1, v2 interrupt control registers i1, i2 selection of oscillation circuit clock control register mr timer 1 function timer 2 function timer 3 function timer 4 function watchdog timer function timer control register pa, w4 timer control registers w1 to w3, w5, w6 serial i/o function serial i/o mode register j1 a-d conversion function a-d control registers q1 to q3 voltage drop detection circuit port level key-on wakeup control register k0 to k2 pull-up control registers pu0, pu1 port output direction registers fr0 to fr2 external 0 interrupt request flag (exf0) external 1 interrupt request flag (exf1) timer 1 interrupt request flag (t1f) timer 2 interrupt request flag (t2f) timer 3 interrupt request flag (t3f) timer 4 interrupt request flag (t4f) a-d conversion completion flag (adf) serial i/o transmission/reception completion flag (siof) interrupt enable flag (inte) watchdog timer flags (wdf1, wdf2) watchdog timer enable flag (wef) ram back-up ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 62 of 156 4518 group (4) return signal an external wakeup signal is used to return from the ram back-up mode because the oscillation is stopped. table 19 shows the return condition for each return source. (5) related registers key-on wakeup control register k0 register k0 controls the ports p0 and p1 key-on wakeup func- tion. set the contents of this register through register a with the tk0a instruction. in addition, the tak0 instruction can be used to transfer the contents of register k0 to register a. key-on wakeup control register k1 register k1 controls the return condition and valid waveform/ level selection for port p0. set the contents of this register through register a with the tk1a instruction. in addition, the tak1 instruction can be used to transfer the contents of register k1 to register a. key-on wakeup control register k2 register k2 controls the int0 and int1 key-on wakeup functions and return condition function. set the contents of this register through register a with the tk2a instruction. in addition, the tak2 instruction can be used to transfer the contents of register k2 to register a. table 19 return source and return condition remarks the key-on wakeup function can be selected with 2 port units. select the re- turn level (l level or h level), and return condition (return by level or edge) with the register k1 according to the external state before going into the ram back-up state. the key-on wakeup function can be selected with 2 port units. set the port using the key-on wakeup function to h level before going into the ram back-up state. select the return level (l level or h level) with the registers i1 and i2 ac- cording to the external state, and return condition (return by level or edge) with the register k2 before going into the ram back-up state. return condition return by an external h level or l level input, or rising edge (l
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 63 of 156 4518 group fig. 51 state transition fig. 52 set source and clear source of the p flag fig. 53 start condition identified example using the snzp in- struction a operation state operation source clock: f(ring) f(x in ): stop key-on wakeup pof instruction execution e ram back-up mode d operation source clock: f(x in ) f(ring): stop pof instruction execution operation state notes 1: microcomputer starts its operation after counting f(ring) 120 to 144 times. c pof instruction execution operation state operation source clock: f(x in ) f(ring): operating b pof instruction execution operation state operation source clock: f(ring) f(x in ): operating f(ring): stop f(x in ): stop mr 1
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 64 of 156 4518 group table 20 key-on wakeup control register, pull-up control register k0 3 k0 2 k0 1 k0 0 key-on wakeup control register k0 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used pins p1 2 and p1 3 key-on wakeup control bit pins p1 0 and p1 1 key-on wakeup control bit pins p0 2 and p0 3 key-on wakeup control bit pins p0 0 and p0 1 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w tak0/tk0a note: r represents read enabled, and w represents write enabled. k1 3 k1 2 k1 1 k1 0 key-on wakeup control register k1 return by level return by edge falling waveform/l level rising waveform/h level return by level return by edge falling waveform/l level rising waveform/h level ports p0 2 and p0 3 return condition selection bit ports p0 2 and p0 3 valid waveform/ level selection bit ports p0 1 and p0 0 return condition selection bit ports p0 1 and p0 0 valid waveform/ level selection bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w tak1/tk1a k2 3 k2 2 k2 1 k2 0 key-on wakeup control register k2 return by level return by edge key-on wakeup not used key-on wakeup used return by level return by edge key-on wakeup not used key-on wakeup used int1 pin return condition selection bit int1 pin key-on wakeup contro bit int0 pin return condition selection bit int0 pin key-on wakeup contro bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w tak2/tk2a
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 65 of 156 4518 group table 21 key-on wakeup control register, pull-up control register pu0 3 pu0 2 pu0 1 pu0 0 pull-up control register pu0 pu1 3 pu1 2 pu1 1 pu1 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on p0 3 pin pull-up transistor control bit p0 2 pin pull-up transistor control bit p0 1 pin pull-up transistor control bit p0 0 pin pull-up transistor control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on p1 3 pin pull-up transistor control bit p1 2 pin pull-up transistor control bit p1 1 pin pull-up transistor control bit p1 0 pin pull-up transistor control bit r/w tapu0/ tpu0a pull-up control register pu1 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w tapu1/ tpu1a note: r represents read enabled, and w represents write enabled.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 66 of 156 4518 group clock control the clock control circuit consists of the following circuits. ring oscillator (internal oscillator) ceramic resonator rc oscillation circuit quartz-crystal oscillation circuit multi-plexer (clock selection circuit) frequency divider internal clock generating circuit the system clock and the instruction clock are generated as the source clock for operation by these circuits. figure 54 shows the structure of the clock control circuit. the 4518 group operates by the ring oscillator clock (f(ring)) which is the internal oscillator after system is released from reset. also, the ceramic resonator, the rc oscillation or quartz-crystal os- cillator can be used for the main clock (f(x in )) of the 4518 group. the cmck instruction, crck instruction or cyck instruction is ex- ecuted to select the ceramic resonator, rc oscillator or quartz-crystal oscillator respectively. fig. 54 clock control circuit structure mr 3, mr 2 00 01 10 11 cmck instruction qs r internal reset signal key-on wakeup signal epof instruction pof instruction + qs r 0 mr 0 1 division circuit system clock (stck) instruction clock (instck) multi- plexer quartz-crystal oscillation ring oscillator (internal oscillator) x out x in ceramic resonance rc oscillation internal clock generating circuit (divided by 3) rg 0 mr 1 qs r qs r q s r crck instruction cyck instruction divided by 2 divided by 4 divided by 8 the cmck, crck, and cyck instructions can be used only to se- lect main clock (f(x in )). in this time, the start of oscillation and the swich of system clock are not performed. the oscillation start/stop of main clock f(x in ) is controlled by bit 1 of register mr. the system clock is selected by bit 0 of register mr. the oscillation start/stop of ring oscillator is controlled by reg- ister rg. the oscillation circuit by the cmck, crck or cyck instruction can be selected only at once. the oscillation circuit corresponding to the first executed one of these instructions is valid. execute the main clock (f(x in )) selection instruction (cmck, crck or cyck instruction) in the initial setting routine of program (ex- ecuting it in address 0 in page 0 is recommended). when the cmck, crck, and cyck instructions are never ex- ecuted, main clock (f(x in )) cannot be used and system can be operated only by ring oscillator. the no operated clock source (f(ring)) or (f(x in )) cannot be used for the sytem clock. also, the clock source (f(ring) or f(x in )) se- lected for the system clock cannot be stopped.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 67 of 156 4518 group fig. 55 switch to ceramic resonance/rc oscillation/quartz-crystal oscillation reset ring oscillator operation cmck instruction crckinstruction main clock: ceramic resonance ring oscillator: operating system clock: ring oscillator clock cyck instruction set the main clock (f(x in )) oscillation by bit 1 of register mr. switch the system clock by bit 0 of register mr. also, when system clock is switched after main clock oscillation is started, generate the oscillation stabilizing wait time by program if necessary. set the ring oscillator clock oscillation by register rg. main clock: rc oscillation circuit ring oscillator: operating system clock: ring oscillator clock main clock: quartz-crystal circuit ring oscillator: operating system clock: ring oscillator clock (1) main clock generating circuit (f(x in )) the ceramic resonator, rc oscillation or quartz-crystal oscillator can be used for the main clock of this mcu. after system is released from reset, the mcu starts operation by the clock output from the ring oscillator which is the internal oscilla- tor. when the ceramic resonator is used, execute the cmck instruc- tion. when the rc oscillation is used, execute the crck instruction. when the quartz-crystal oscillator is used, execute the cyck instruction. the oscillation start/stop of main clock f(x in ) is controlled by bit 1 of register mr. the system clock is selected by bit 0 of register mr. the oscillation circuit by the cmck, crck or cyck instruction can be selected only at once. the oscillation cir- cuit corresponding to the first executed one of these instructions is valid. other oscillation circuit and the ring oscillator stop. execute the cmck, crck or cyck instruction in the initial setting routine of program (executing it in address 0 in page 0 is recom- mended). also, when the cmck, crck or cyck instruction is not executed in program, this mcu operates by the ring oscillator.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 68 of 156 4518 group fig. 60 external clock input circuit fig. 59 external quartz-crystal circuit note: externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the quartz-crystal manu- facturer?s recommended value because constants such as ca- pacitance depend on the resonator. fig. 56 handling of x in and x out when operating ring oscillator fig. 57 ceramic resonator external circuit fig. 58 external rc oscillation circuit execute the cmck instruc- tion in program. note: externally connect a damping resistor rd depending on the oscillation frequency. (a feedback resistor is built-in.) use the resonator manu- facturer?s recommended value because constants such as ca- pacitance depend on the resonator. * m34518 x in x out * do not use the cmck, crck and cyck instructions in program. open open m34518 x in x out rd c in c ou t m34518 x in x out r c * execute the crck instruction in program. open m34518 x in x out rd c in c ou t execute the cyck instruction in program. * m34518 x in x out external oscillation circuit v dd v ss r 1k ? (2) ring oscillator operation when the mcu operates by the ring oscillator as the main clock (f(x in )) without using the ceramic resonator, rc oscillator or quartz-crystal oscillation, leave x in pin and x out pin open (figure 56). the clock frequency of the ring oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies when designing application products. (3) ceramic resonator when the ceramic resonator is used as the main clock (f(x in )), connect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. then, execute the cmck in- struction. a feedback resistor is built in between pins x in and x out (figure 57). (4) rc oscillation when the rc oscillation is used as the main clock (f(x in )), connect the x in pin to the external circuit of resistor r and the capacitor c at the shortest distance and leave x out pin open. then, execute the crck instruction (figure 58). the frequency is affected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. (5) quartz-crystal oscillator when a quartz-crystal oscillator is used as the main clock (f(x in )), connect this external circuit and a quartz-crystal oscillator to pins x in and x out at the shortest distance. then, execute the cyck in- struction. a feedback resistor is built in between pins x in and x out (figure 59). (6) external clock when the external clock signal for the main clock (f(x in )) is used, connect the clock source to x in pin and x out pin open. in program, after the cmck instruction is executed, set main clock (f(x in )) os- cillation start to be enabled (mr 1 =0). for this product, when ram back-up mode and main clock (f(x in )) stop (mr 1 =1), x in pin is fixed to h in order to avoid the through current by floating of internal logic. the x in pin is fixed to h until main clock (f(x in )) oscillation starts to be valid (mr 1 =0) by the cmck instruction from reset state. accordingly, when an external clock is used, connect a 1 k ? *
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 69 of 156 4518 group rom ordering method 1.mask rom order confirmation form ? ? ? (7) clock control register mr register mr controls system clock. set the contents of this register through register a with the tmra instruction. in addition, the tamr instruction can be used to transfer the contents of register mr to register a. table 22 clock control registers note: r represents read enabled, and w represents write enabled. mr 3 clock control register mr operation mode through mode (frequency not divided) frequency divided by 2 mode frequency divided by 4 mode frequency divided by 8 mode main clock (f(x in )) oscillation enabled main clock (f(x in )) oscillation stop main clock (f(x in )) main clock (f(ring)) at reset : 1111 2 at ram back-up : 1111 2 mr 3 0 0 1 1 r/w tamr/ tmra main clock f(x in ) oscillation circuit control bit system clock oscillation source selection bit operation mode selection bits 0 1 0 1 mr 2 0 1 0 1 mr 1 mr 0 mr 2 0 1 ring oscillator (f(ring)) oscillation enabled ring oscillator (f(ring)) oscillation stop ring oscillator (f(ring)) control bit clock control register rg w trga at ram back-up : 0 2 at reset : 0 2 rg 0 (8) clock control register rg register rg controls start/stop of ring oscillator. set the contents of this register through register a with the trga instruction.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 70 of 156 4518 group ? ? ? ? ? ? list of precautions ? ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 71 of 156 4518 group la 0 ; ( ? ?? ? ? ?? ? ? ? fig. 61 period measurement circuit program example 13 period measurement circuit when a period measurement circuit is used, clear bit 0 of regis- ter i1 to 0, and set a timer 1 count start synchronous circuit to be not selected. start timer operation immediately after operation of a period measurement circuit is started. when the edge for measurement is input until timer operation is started from the operation of period measurement circuit is started, the count operation is not executed until the timer opera- tion becomes valid. accordingly, be careful of count data. when data is read from timer, stop the timer and clear bit 2 of register w5 to 0 to stop the period measurement circuit, and then execute the data read instruction. depending on the state of timer 1, the timer 1 interrupt request flag (t1f) may be set to 1 when the period measurement cir- cuit is stopped by clearing bit 2 of register w5 to 0. in order to avoid the occurrence of an unexpected interrupt, clear the bit 2 of register v1 to 0 (refer to figure 61 ? ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 72 of 156 4518 group p3 0 /int0 pin ? ? ? ? ??? ? ??? ? ? ? ? ? ??? ? ? fig. 63 external 0 interrupt program example-2 ? ? ? ? ??? ? ? ? ? fig. 64 external 0 interrupt program example-3 14 fig. 62 external 0 interrupt program example-1
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 73 of 156 4518 group p3 1 /int1 pin ? ? ? ? ?? ? ? ??? ? ? ? fig. 65 external 1 interrupt program example-1 ? ? ? ?? ? ? fig. 66 external 1 interrupt program example-2 ? ? ? ? ?? ? ? ? ? ? fig. 67 external 1 interrupt program example-3 15
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 74 of 156 4518 group pof instruction when the pof instruction is executed continuously after the epof instruction, system enters the ram back-up state. note that system cannot enter the ram back-up state when ex- ecuting only the pof instruction. be sure to disable interrupts by executing the di instruction be- fore executing the epof instruction and the pof instruction continuously. program counter make sure that the pc does not specify after the last page of the built-in rom. power-on reset when the built-in power-on reset circuit is used, the time for the supply voltage to rise from 0 v to the value of supply voltage or more must be set to 100 ? ?? ? ??? ? fig. 68 a-d converter program example-3 fig. 69 analog input external circuit example-1 a-d converter-2 each analog input pin is equipped with a capacitor which is used to compare the analog voltage. accordingly, when the analog volt- age is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient a-d accuracy may not be obtained. therefore, reduce the impedance or, connect a capacitor (0.01 ? fig. 70 analog input external circuit example-2 19
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 75 of 156 4518 group external clock when the external clock signal for the main clock (f(x in )) is used, connect the clock source to x in pin and x out pin open. in pro- gram, after the cmck instruction is executed, set main clock (f(x in )) oscillation start to be enabled (mr 1 =0). for this product, when ram back-up mode and main clock (f(x in )) stop (mr 1 =1), x in pin is fixed to h in order to avoid the through current by floating of internal logic. the x in pin is fixed to h until main clock (f(x in )) oscillation start to be valid (mr 1 =0) by the cmck instruction from reset state. accordingly, when an external clock is used, connect a 1 k ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 76 of 156 4518 group control registers i1 3 i1 2 i1 1 i1 0 int0 pin input control bit interrupt valid waveform for int0 pin/ return level selection bit int0 pin edge detection circuit control bit int0 pin timer 1 count start synchronous circuit selection bit interrupt control register i1 r/w tai1/ti1a at ram back-up : state retained at reset : 0000 2 int0 pin input disabled int0 pin input enabled falling waveform/l level (l level is recognized with the snzi0 instruction) rising waveform/h level (h level is recognized with the snzi0 instruction) one-sided edge detected both edges detected timer 1 count start synchronous circuit not selected timer 1 count start synchronous circuit selected 0 1 0 1 0 1 0 1 interrupt disabled (snzsi instruction is valid) interrupt enabled (snzsi instruction is invalid) interrupt disabled (snzad instruction is valid) interrupt enabled (snzad instruction is invalid) interrupt disabled (snzt4 instruction is valid) interrupt enabled (snzt4 instruction is invalid) interrupt disabled (snzt3 instruction is valid) interrupt enabled (snzt3 instruction is invalid) v1 3 v1 2 v1 1 v1 0 v2 3 v2 2 v2 1 v2 0 serial i/o interrupt enable bit a-d interrupt enable bit timer 4 interrupt enable bit timer 3 interrupt enable bit interrupt control register v2 at ram back-up : 0000 2 at reset : 0000 2 0 1 0 1 0 1 0 1 interrupt control register v1 timer 2 interrupt enable bit timer 1 interrupt enable bit external 1 interrupt enable bit external 0 interrupt enable bit interrupt disabled (snzt2 instruction is valid) interrupt enabled (snzt2 instruction is invalid) interrupt disabled (snzt1 instruction is valid) interrupt enabled (snzt1 instruction is invalid) interrupt disabled (snz1 instruction is valid) interrupt enabled (snz1 instruction is invalid) interrupt disabled (snz0 instruction is valid) interrupt enabled (snz0 instruction is invalid) 0 1 0 1 0 1 0 1 at ram back-up : 0000 2 at reset : 0000 2 r/w tav1/tv1a i2 3 i2 2 i2 1 i2 0 int1 pin input control bit (note 2) interrupt valid waveform for int1 pin/ return level selection bit (note 2) int1 pin edge detection circuit control bit int1 pin timer 3 count start synchronous circuit selection bit interrupt control register i2 r/w tai2/ti2a at ram back-up : state retained at reset : 0000 2 int1 pin input disabled int1 pin input enabled falling waveform/l level (l level is recognized with the snzi1 instruction) rising waveform/h level (h level is recognized with the snzi1 instruction) one-sided edge detected both edges detected timer 3 count start synchronous circuit not selected timer 3 count start synchronous circuit selected 0 1 0 1 0 1 0 1 notes 1: r represents read enabled, and w represents write enabled. 2: when the contents of i1 2 , i1 3 i2 2 and i2 3 are changed, the external interrupt request flag (exf0, exf1) may be set. r/w tav2/tv2a
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 77 of 156 4518 group w2 1 0 0 1 1 timer 1 underflow signal divided by 2 output timer 2 underflow signal divided by 2 output stop (state retained) operating count source system clock (stck) prescaler output (orclk) timer 1 underflow signal (t1udf) pwm signal (pwmout) cntr0 output signal selection bit timer 2 control bit timer 2 count source selection bits 0 1 0 1 w2 0 0 1 0 1 timer control register w2 at ram back-up : state retained at reset : 0000 2 note: r represents read enabled, and w represents write enabled. w2 3 w2 2 w2 1 w2 0 mr 3 clock control register mr operation mode through mode (frequency not divided) frequency divided by 2 mode frequency divided by 4 mode frequency divided by 8 mode main clock (f(x in )) oscillation enabled main clock (f(x in )) oscillation stop main clock (f(x in )) main clock (f(ring)) at reset : 1111 2 at ram back-up : 1111 2 mr 3 0 0 1 1 r/w tamr/ tmra main clock f(x in ) oscillation circuit control bit system clock oscillation source selection bit operation mode selection bits 0 1 0 1 mr 2 0 1 0 1 mr 1 mr 0 mr 2 0 1 ring oscillator (f(ring)) oscillation enabled ring oscillator (f(ring)) oscillation stop ring oscillator (f(ring)) control bit clock control register rg w trga at ram back-up : 0 2 at reset : 0 2 rg 0 w1 1 0 0 1 1 timer 1 count auto-stop circuit not selected timer 1 count auto-stop circuit selected stop (state retained) operating count source instruction clock (instck) prescaler output (orclk) x in input cntr0 input timer 1 count auto-stop circuit selection bit timer 1 control bit timer 1 count source selection bits 0 1 0 1 w1 0 0 1 0 1 timer control register w1 r/w taw1/tw1a at ram back-up : state retained at reset : 0000 2 w1 3 w1 2 w1 1 w1 0 r/w taw2/tw2a 0 1 stop (state initialized) operating prescaler control bit timer control register pa w tpaa at ram back-up : 0 2 at reset : 0 2 pa 0
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 78 of 156 4518 group falling edge rising edge falling edge rising edge cntr1 output auto-control circuit not selected cntr1 output auto-control circuit selected d 6 (i/o) / cntr0 (input) cntr0 (i/o) /d 6 (input) cntr1 pin input count edge selection bit cntr0 pin input count edge selection bit cntr1 output auto-control circuit selection bit d 6 /cntr0 pin function selection bit 0 1 0 1 0 1 0 1 timer control register w6 at ram back-up : state retained at reset : 0000 2 w6 3 w6 2 w6 1 w6 0 d 7 (i/o) / cntr1 (input) cntr1 (i/o) / d 7 (input) pwm signal h interval expansion function invalid pwm signal h interval expansion function valid stop (state retained) operating x in input prescaler output (orclk) divided by 2 d 7 /cntr1 pin function selection bit pwm signal h interval expansion function control bit timer 4 control bit timer 4 count source selection bit 0 1 0 1 0 1 0 1 w4 3 w4 2 w4 1 w4 0 w5 1 0 0 1 1 not used period measurement circuit control bit signal for period measurement selection bits 0 1 0 1 w5 0 0 1 0 1 timer control register w5 at ram back-up : state retained at reset : 0000 2 w5 3 w5 2 w5 1 w5 0 this bit has no function, but read/write is enabled. stop operating count value ring oscillator (f(ring/16)) cntr 0 pin input int0 pin input not available r/w taw4/tw4a timer control register w4 at ram back-up : 0000 2 at reset : 0000 2 r/w taw5/tw5a r/w taw6/tw6a w3 1 0 0 1 1 timer 3 count auto-stop circuit not selected timer 3 count auto-stop circuit selected stop (state retained) operating count source pwm signal (pwmout) prescaler output (orclk) timer 2 underflow signal (t2udf) cntr1 input timer 3 count auto-stop circuit selection bit (note 2) timer 3 control bit timer 3 count source selection bits 0 1 0 1 w3 0 0 1 0 1 timer control register w3 at ram back-up : state retained at reset : 0000 2 w3 3 w3 2 w3 1 w3 0 r/w taw3/tw3a notes 1: r represents read enabled, and w represents write enabled. 2: this function is valid only when the timer 3 count start synchronous circuit is selected (i2 0 =1).
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 79 of 156 4518 group j1 3 0 0 1 1 j1 1 0 0 1 1 serial i/o synchronous clock selection bits serial i/o port function selection bits j1 2 0 1 0 1 j1 0 0 1 0 1 serial i/o control register j1 at ram back-up : state retained at reset : 0000 2 j1 3 j1 2 j1 1 j1 0 synchronous clock instruction clock (instck) divided by 8 instruction clock (instck) divided by 4 instruction clock (instck) divided by 2 external clock (s ck input) port function p2 0 , p2 1 ,p2 2 selected/s ck , s out , s in not selected s ck , s out , p2 2 selected/p2 0 , p2 1 , s in not selected s ck , p2 1 , s in selected/p2 0 , s out , p2 2 not selected s ck , s out , s in selected/p2 0 , p2 1 ,p2 2 not selected r/w taj1/tj1a q1 2 0 0 0 0 1 1 1 1 a-d operation mode selection bit analog input pin selection bits q1 1 0 0 1 1 0 0 1 1 a-d control register q1 at ram back-up : state retained at reset : 0000 2 q1 3 a-d conversion mode comparator mode r/w taq1/tq1a q1 0 0 1 0 1 0 1 0 1 q1 2 q1 1 q1 0 analog input pins a in0 a in1 a in2 a in3 not available not available not available not available this bit has no function, but read/write is enabled. p6 2 , p6 3 a in2 , a in3 p6 1 a in1 p6 0 a in0 not used p6 2 /a in2 , p6 3 /a in3 pin function selection bit p6 1 /a in1 pin function selection bit p6 0 /a in0 pin function selection bit 0 1 0 1 0 1 0 1 q2 3 q2 2 q2 1 q2 0 r/w taq2/tq2a a-d control register q2 at ram back-up : state retained at reset : 0000 2 note: r represents read enabled, and w represents write enabled. not used a-d converter operation clock selection bit a-d converter operation clock division ratio selection bits a-d control register q3 q3 3 q3 2 q3 1 q3 0 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 q3 1 0 0 1 1 q3 0 0 1 0 1 division ratio frequency divided by 6 frequency divided by 12 frequency divided by 24 frequency divided by 48 this bit has no function, but read/write is enabled. instruction clock (instck) ring oscillator (f(ring)) r/w taq3/tq3a
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 80 of 156 4518 group k0 3 k0 2 k0 1 k0 0 key-on wakeup control register k0 key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used key-on wakeup not used key-on wakeup used pins p1 2 and p1 3 key-on wakeup control bit pins p1 0 and p1 1 key-on wakeup control bit pins p0 2 and p0 3 key-on wakeup control bit pins p0 0 and p0 1 key-on wakeup control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w tak0/tk0a note: r represents read enabled, and w represents write enabled. k1 3 k1 2 k1 1 k1 0 key-on wakeup control register k1 return by level return by edge falling waveform/l level rising waveform/h level return by level return by edge falling waveform/l level rising waveform/h level ports p0 2 and p0 3 return condition selection bit ports p0 2 and p0 3 valid waveform/ level selection bit ports p0 1 and p0 0 return condition selection bit ports p0 1 and p0 0 valid waveform/ level selection bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w tak1/tk1a k2 3 k2 2 k2 1 k2 0 key-on wakeup control register k2 return by level return by edge key-on wakeup not used key-on wakeup used return by level return by edge key-on wakeup not used key-on wakeup used int1 pin return condition selection bit int1 pin key-on wakeup contro bit int0 pin return condition selection bit int0 pin key-on wakeup contro bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w tak2/tk2a
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 81 of 156 4518 group pu0 3 pu0 2 pu0 1 pu0 0 pull-up control register pu0 pu1 3 pu1 2 pu1 1 pu1 0 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on p0 3 pin pull-up transistor control bit p0 2 pin pull-up transistor control bit p0 1 pin pull-up transistor control bit p0 0 pin pull-up transistor control bit at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on pull-up transistor off pull-up transistor on p1 3 pin pull-up transistor control bit p1 2 pin pull-up transistor control bit p1 1 pin pull-up transistor control bit p1 0 pin pull-up transistor control bit r/w tapu0/ tpu0a pull-up control register pu1 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 r/w tapu1/ tpu1a note: r represents read enabled, and w represents write enabled.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 82 of 156 4518 group fr0 3 fr0 2 fr0 1 fr0 0 n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output ports p1 2 , p1 3 output structure selection bit ports p1 0 , p1 1 output structure selection bit ports p0 2 , p0 3 output structure selection bit ports p0 0 , p0 1 output structure selection bit port output structure control register fr0 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 fr1 3 fr1 2 fr1 1 fr1 0 n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output port d 3 output structure selection bit port d 2 output structure selection bit port d 1 output structure selection bit port d 0 output structure selection bit port output structure control register fr1 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 fr2 3 fr2 2 fr2 1 fr2 0 n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output n-channel open-drain output cmos output port d 7 /cntr1 output structure selection bit port d 6 /cntr0 output structure selection bit port d 5 output structure selection bit port d 4 output structure selection bit port output structure control register fr2 at reset : 0000 2 at ram back-up : state retained 0 1 0 1 0 1 0 1 note: r represents read enabled, and w represents write enabled. w tfr0a w tfr1a w tfr2a
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 83 of 156 4518 group symbol a b dr e v1 v2 i1 i2 mr rg pa w1 w2 w3 w4 w5 w6 j1 q1 q2 q3 pu0 pu1 fr0 fr1 fr2 k0 k1 k2 x y z dp pc pc h pc l sk sp cy rps r1 r2 r3 r4l r4h contents register a (4 bits) register b (4 bits) register dr (3 bits) register e (8 bits) interrupt control register v1 (4 bits) interrupt control register v2 (4 bits) interrupt control register i1 (4 bits) interrupt control register i2 (4 bits) clock control register mr (4 bits) clock control register rg (1 bit) timer control register pa (1 bit) timer control register w1 (4 bits) timer control register w2 (4 bits) timer control register w3 (4 bits) timer control register w4 (4 bits) timer control register w5 (4 bits) timer control register w6 (4 bits) serial i/o control register j1 (4 bits) a-d control register q1 (4 bits) a-d control register q2 (4 bits) a-d control register q3 (4 bits) pull-up control register pu0 (4 bits) pull-up control register pu1 (4 bits) port output format control register fr0 (4 bits) port output format control register fr1 (4 bits) port output format control register fr2 (4 bits) key-on wakeup control register k0 (4 bits) key-on wakeup control register k1 (4 bits) key-on wakeup control register k2 (4 bits) register x (4 bits) register y (4 bits) register z (2 bits) data pointer (10 bits) (it consists of registers x, y, and z) program counter (14 bits) high-order 7 bits of program counter low-order 7 bits of program counter stack register (14 bits ? ? instructions the 4518 group has the 148 instructions. each instruction is de- scribed as follows; (1) index list of instruction function (2) machine instructions (index by alphabet) (3) machine instructions (index by function) (4) instruction code table note : some instructions of the 4518 group has the skip function to unexecute the next described instruction. the 4518 group jus t invalidates the next instruc- tion when a skip is performed. the contents of program counter is not increased by 2. accordingly, the number of cycles does no t change even if skip is not performed. however, the cycle count becomes 1 if the tabp p, rt, or rts instruction is skipped. symbol the symbols shown below are used in the following list of instruc- tion function and the machine instructions.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 84 of 156 4518 group index list of instruction function group- ing ram addresses mnemonic xami j tma j la n tabp p am amc a n and or sc rc szc cma rar function (a)
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 85 of 156 4518 group index list of instruction function (continued) group- ing function (mj(dp))
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 86 of 156 4518 group index list of instruction function (continued) group- ing group- ing function (a)
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 87 of 156 4518 group index list of instruction function (continued) group- ing group- ing page 91, 138 99, 138 100, 138 105, 138 112, 138 120, 138 112, 138 120, 138 110, 138 118, 138 111, 138 119, 138 111, 138 119, 138 117, 138 117, 138 117, 138 92, 138 92, 138 92, 138 122, 138 112, 138 119, 138 page 109, 138 122, 138 104, 138 103, 138 110, 138 118, 138 108, 140 111, 140 109, 140 89, 140 102, 140 112, 140 121, 140 113, 140 121, 140 113, 140 121, 140 a-d operation serial i/o operation input/output operation function (d)
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 88 of 156 4518 group mnemonic nop pof epof snzp dwdt wrst srst function (pc) index list of instruction function (continued) group- ing page 96, 140 98, 140 94, 140 102, 140 93, 140 125, 140 104, 140
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 89 of 156 4518 group machine instructions (index by alphabet) a n (add n and accumulator) 000110nnnn 06n 11 overflow = 0 grouping: arithmetic operation description: adds the value n in the immediate field to register a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instruction when there is overflow as the result of operation. operation: (a) (a) + n n = 0 to 15 adst (a-d conversion start) 1010011111 29f 11 grouping: a-d conversion operation description: clears (0) to a-d conversion completion flag adf, and the a-d conversion at the a-d conversion mode (q1 3 = 0) or the compara- tor operation at the comparator mode (q1 3 = 1) is started. operation: (adf) 0 q1 3 = 0: a-d conversion starting q1 3 = 1: comparator operation starting (q1 3 : bit 3 of a-d control register q1) am (add accumulator and memory) 0000001010 00a 11 grouping: arithmetic operation description: adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy remains unchanged. operation: (a) (a) + (m(dp)) amc (add accumulator, memory and carry) 0000001011 00b 11 0/1 grouping: arithmetic operation description: adds the contents of m(dp) and carry flag cy to register a. stores the result in regis- ter a and carry flag cy. operation: (a) (a) + (m(dp)) + (cy) (cy) carry
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 90 of 156 4518 group and (logical and between accumulator and memory) 0000011000 018 11 grouping: arithmetic operation description: takes the and operation between the con- tents of register a and the contents of m(dp), and stores the result in register a. operation: (a) (a) and (m(dp)) b a (branch to address a) 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 1a 11 grouping: branch operation description: branch within a page : branches to address a in the identical page. note: specify the branch address within the page including this instruction. operation: (pc l ) a 6 to a 0 bl p, a (branch long to address a in page p) 00111p 4 p 3 p 2 p 1 p 0 0p 22 grouping: branch operation description: branch out of a page : branches to address a in page p. note: p is 0 to 15 for m34518m2, p is 0 to 31 for m34518m4, p is 0 to 47 for m34518m6 and p is 0 to 63 for m34518m8e8. operation: (pc h ) p (pc l ) a 6 to a 0 bla p (branch long to address (d) + (a) in page p) 0000010000 010 22 grouping: branch operation description: branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. note: p is 0 to 15 for m34518m2, p is 0 to 31 for m34518m4, p is 0 to 47 for m34518m6 and p is 0 to 63 for m34518m8e8. 8 +a 2 16 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 2a e +p operation: (pc h ) p (pc l ) (dr 2 ?r 0 , a 3 ? 0 ) 2 16 10p 5 p 4 00p 3 p 2 p 1 p 0 2pp machine instructions (index by alphabet) (continued) p +a
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 91 of 156 4518 group bm a (branch and mark to address a in page 2) 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 1aa 11 grouping: subroutine call operation description: call the subroutine in page 2 : calls the subroutine at address a in page 2. note: subroutine extending from page 2 to an- other page can also be called with the bm instruction when it starts on page 2. be careful not to over the stack because the maximum level of subroutine nesting is 8. operation: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) 2 (pc l ) a 6 ? 0 bml p, a (branch and mark long to address a in page p) 00110p 4 p 3 p 2 p 1 p 0 0p 22 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address a in page p. note: p is 0 to 15 for m34518m2, p is 0 to 31 for m34518m4, p is 0 to 47 for m34518m6 and p is 0 to 63 for m34518m8e8. be careful not to over the stack because the maximum level of subroutine nesting is 8. operation: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) a 6 ? 0 bmla p (branch and mark long to address (d) + (a) in page p) 0000110000 030 22 grouping: subroutine call operation description: call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 speci- fied by registers d and a in page p. note: p is 0 to 15 for m34518m2, p is 0 to 31 for m34518m4, p is 0 to 47 for m34518m6 and p is 0 to 63 for m34518m8e8. be careful not to over the stack because the maximum level of subroutine nesting is 8. cld (clear port d) 0000010001 011 11 grouping: input/output operation description: sets (1) to port d. operation: (d) 1 2 16 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 2a c +p operation: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) (dr 2 ?r 0 , a 3 ? 0 ) 2 16 10p 5 p 4 00p 3 p 2 p 1 p 0 2pp machine instructions (index by alphabet) (continued) p +a
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 92 of 156 4518 group cma (complement of accumulator) 0000011100 01c 11 grouping: arithmetic operation description: stores the ones complement for register as contents in register a. operation: (a) (a) cmck (clock select: ceramic oscillation clock) 1010011010 29a 11 grouping: clock control operation description: selects the ceramic oscillation circuit for main clock f(x in ). operation: ceramic oscillation circuit selected crck (clock select: rc oscillation clock) 1010011011 29b 11 grouping: clock control operation description: selects the rc oscillation circuit for main clock f(x in ). operation: rc oscillation circuit selected machine instructions (index by alphabet) (continued) cyck (clock select: crystal oscillation clock) 1010011101 29d 11 grouping: clock control operation description: selects the quartz-crystal oscillation circuit for main clock f(x in ). operation: quartz-crystal oscillation circuit selected
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 93 of 156 4518 group di (disable interrupt) 0000000100 004 11 grouping: interrupt control operation description: clears (0) to interrupt enable flag inte, and disables the interrupt. note: interrupt is disabled by executing the di in- struction after executing 1 machine cycle. operation: (inte) 0 dwdt (disable watchdog timer) 1010011100 29c 11 grouping: other operation description: stops the watchdog timer function by the wrst instruction after executing the dwdt instruction. operation: stop of watchdog timer function enabled ei (enable interrupt) 0000000101 005 11 grouping: interrupt control operation description: sets (1) to interrupt enable flag inte, and enables the interrupt. note: interrupt is enabled by executing the ei in- struction after executing 1 machine cycle. operation: (inte) 1 machine instructions (index by alphabet) (continued) 0000010111 017 11 (y) = 15 grouping: ram addresses description: subtracts 1 from the contents of register y. as a result of subtraction, when the con- tents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. operation: (y) (y) ?1 dey (decrement register y)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 94 of 156 4518 group iap0 (input accumulator from port p0) 1001100000 260 11 grouping: input/output operation description: transfers the input of port p0 to register a. iap1 (input accumulator from port p1) 1001100001 261 11 grouping: input/output operation description: transfers the input of port p1 to register a. operation: (a) (p1) iap2 (input accumulator from port p2) 1001100010 262 11 grouping: input/output operation description: transfers the input of port p2 to register a. operation: (a 2 ? 0 ) (p2 2 ?2 0 ) (a 3 ) 0 operation: (a) (p0) machine instructions (index by alphabet) (continued) 0001011011 05b 11 grouping: other operation description: makes the immediate after pof instruction valid by executing the epof instruction. operation: pof instruction valid epof (enable pof instruction)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 95 of 156 4518 group machine instructions (index by alphabet) (continued) iap3 (input accumulator from port p3) 1001100011 263 11 grouping: input/output operation description: transfers the input of port p3 to register a. operation: (a) (p3) iap6 (input accumulator from port p6) 1001100110 266 11 grouping: input/output operation description: transfers the input of port p6 to register a. operation: (a) (p6) iny (increment register y) 0000010011 013 11 (y) = 0 grouping: ram addresses description: adds 1 to the contents of register y. as a re- sult of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of register y is not 0, the next instruction is executed. operation: (y) (y) + 1 la n (load n in accumulator) 000111nnnn 07n 11 continuous description grouping: arithmetic operation description: loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la in- struction is executed and other la instructions coded continuously are skipped. operation: (a) n n = 0 to 15
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 96 of 156 4518 group lz z (load register z with z) 00010010z 1 z 0 04 11 grouping: ram addresses description: loads the value z in the immediate field to register z. operation: (z) z z = 0 to 3 8 +z machine instructions (index by alphabet) (continued) 11x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 3xy 11 continuous description grouping: ram addresses description: loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instruc- tions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continu- ously are skipped. operation: (x) x x = 0 to 15 (y) y y = 0 to 15 lxy x, y (load register x and y with x and y) nop (no operation) 0000000000 000 11 grouping: other operation description: no operation; adds 1 to program counter value, and others remain unchanged. operation: (pc) (pc) + 1 op0a (output port p0 from accumulator) 1000100000 220 11 grouping: input/output operation description: outputs the contents of register a to port p0. operation: (p0) (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 97 of 156 4518 group op3a (output port p3 from accumulator) 1000100011 223 11 grouping: input/output operation description: outputs the contents of register a to port p3. operation: (p3) (a) machine instructions (index by alphabet) (continued) op1a (output port p1 from accumulator) 1000100001 221 11 grouping: input/output operation description: outputs the contents of register a to port p1. operation: (p1) (a) op2a (output port p2 from accumulator) 1000100010 222 11 grouping: input/output operation description: outputs the contents of register a to port p2. operation: (p2) (a) op6a (output port p6 from accumulator) 1000100110 226 11 grouping: input/output operation description: outputs the contents of register a to port p6. operation: (p6) (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 98 of 156 4518 group pof (power off) 0000000010 002 11 grouping: other operation description: puts the system in ram back-up state by executing the pof instruction after execut- ing the epof instruction. note: if the epof instruction is not executed before executing this instruction, this instruction is equivalent to the nop instruction. operation: transition to ram back-up mode rar (rotate accumulator right) 0000011101 01d 1 1 0/1 grouping: arithmetic operation description: rotates 1 bit of the contents of register a in- cluding the contents of carry flag cy to the right. operation: cy a 3 a 2 a 1 a 0 rb j (reset bit) 00010011j j 04 11 grouping: bit operation description: clears (0) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). operation: (mj(dp)) 0 j = 0 to 3 c +j machine instructions (index by alphabet) (continued) 0000011001 019 11 grouping: arithmetic operation description: takes the or operation between the con- tents of register a and the contents of m(dp), and stores the result in register a. operation: (a) (a) or (m(dp)) or (logical or between accumulator and memory)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 99 of 156 4518 group rd (reset port d specified by register y) 0000010100 014 11 grouping: input/output operation description: clears (0) to a bit of port d specified by reg- ister y. operation: (d(y)) 0 however, (y) = 0 to 9 rc (reset carry flag) 0000000110 006 11 0 grouping: arithmetic operation description: clears (0) to carry flag cy. operation: (cy) 0 rti (return from interrupt) 0001000110 046 11 grouping: return operation description: returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous description of the la/lxy in- struction, register a and register b to the states just before interrupt. operation: (pc) (sk(sp)) (sp) (sp) ?1 rt (return from subroutine) 0001000100 044 12 grouping: return operation description: returns from subroutine to the routine called the subroutine. operation: (pc) (sk(sp)) (sp) (sp) ?1 machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 100 of 156 4518 group sd (set port d specified by register y) 0000010101 015 11 grouping: input/output operation description: sets (1) to a bit of port d specified by regis- ter y. operation: (d(y)) 1 (y) = 0 to 9 sc (set carry flag) 0000000111 007 11 1 grouping: arithmetic operation description: sets (1) to carry flag cy. operation: (cy) 1 rts (return from subroutine and skip) 0001000101 045 12 skip at uncondition grouping: return operation description: returns from subroutine to the routine called the subroutine, and skips the next in- struction at uncondition. operation: (pc) (sk(sp)) (sp) (sp) ?1 sb j (set bit) 00010111j j 05 11 grouping: bit operation description: sets (1) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). operation: (mj(dp)) 1 j = 0 to 3 c +j machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 101 of 156 4518 group snz0 (skip if non zero condition of external 0 interrupt request flag) 0000111000 038 11 v1 0 = 0: (exf0) = 1 grouping: interrupt operation description: when v1 0 = 0 : skips the next instruction when external 0 interrupt request flag exf0 is ?.?after skipping, clears (0) to the exf0 flag. when the exf0 flag is ?,?executes the next instruction. when v1 0 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 0 = 0: (exf0) = 1 ? after skipping, (exf0) 0 v1 0 = 1: snz0 = nop (v1 0 : bit 0 of the interrupt control register v1) machine instructions (index by alphabet) (continued) sea n (skip equal, accumulator with immediate data n) 0000100101 025 22 (a) = n grouping: comparison operation description: skips the next instruction when the con- tents of register a is equal to the value n in the immediate field. executes the next instruction when the con- tents of register a is not equal to the value n in the immediate field. operation: (a) = n ? n = 0 to 15 2 16 000111nnnn 07n seam (skip equal, accumulator with memory) 0000100110 026 11 (a) = (m(dp)) grouping: comparison operation description: skips the next instruction when the con- tents of register a is equal to the contents of m(dp). executes the next instruction when the con- tents of register a is not equal to the contents of m(dp). operation: (a) = (m(dp)) ? snz1 (skip if non zero condition of external 1 interrupt request flag) 0000111001 039 11 v1 1 = 0: (exf1) = 1 grouping: interrupt operation description: when v1 1 = 0 : skips the next instruction when external 1 interrupt request flag exf1 is ?.?after skipping, clears (0) to the exf1 flag. when the exf1 flag is ?,?executes the next instruction. when v1 1 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 1 = 0: (exf1) = 1 ? after skipping, (exf1) 0 v1 1 = 1: snz1 = nop (v1 1 : bit 1 of the interrupt control register v1)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 102 of 156 4518 group snzp (skip if non zero condition of power down flag) 0000000011 003 11 (p) = 1 grouping: other operation description: skips the next instruction when the p flag is ?? after skipping, the p flag remains un- changed. executes the next instruction when the p flag is ?. operation: (p) = 1 ? snzad (skip if non zero condition of a-d conversion completion flag) 1010000111 287 11 v2 2 = 0: (adf) = 1 grouping: a-d conversion operation description: when v2 2 = 0 : skips the next instruction when a-d conversion completion flag adf is ?.?after skipping, clears (0) to the adf flag. when the adf flag is ?,?executes the next instruction. when v2 2 = 1 : this instruction is equiva- lent to the nop instruction. operation: v2 2 = 0: (adf) = 1 ? after skipping, (adf) 0 v2 2 = 1: snzad = nop (v2 2 : bit 2 of the interrupt control register v2) snzi0 (skip if non zero condition of external 0 interrupt input pin) 0000111010 03a 11 i1 2 = 0 : (int0) = ? i1 2 = 1 : (int0) = ? grouping: interrupt operation description: when i1 2 = 0 : skips the next instruction when the level of int0 pin is ?.?executes the next instruction when the level of int0 pin is ?. when i1 2 = 1 : skips the next instruction when the level of int0 pin is ?.?executes the next instruction when the level of int0 pin is ?. operation: i1 2 = 0 : (int0) = ??? i1 2 = 1 : (int0) = ??? (i1 2 : bit 2 of the interrupt control register i1) snzi1 (skip if non zero condition of external 1 interrupt input pin) 0000111011 03b 11 i2 2 = 0 : (int1) = ? i2 2 = 1 : (int1) = ? grouping: interrupt operation description: when i2 2 = 0 : skips the next instruction when the level of int1 pin is ?.?executes the next instruction when the level of int1 pin is ?. when i2 2 = 1 : skips the next instruction when the level of int1 pin is ?.?executes the next instruction when the level of int1 pin is ?. operation: i2 2 = 0 : (int1) = ??? i2 2 = 1 : (int1) = ??? (i2 2 : bit 2 of the interrupt control register i2) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 103 of 156 4518 group snzt1 (skip if non zero condition of timer 1 interrupt request flag) 1010000000 280 11 v1 2 = 0: (t1f) = 1 grouping: timer operation description: when v1 2 = 0 : skips the next instruction when timer 1 interrupt request flag t1f is ?.?after skipping, clears (0) to the t1f flag. when the t1f flag is ?,?executes the next instruction. when v1 2 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 2 = 0: (t1f) = 1 ? after skipping, (t1f) 0 v1 2 = 1: snzt1 = nop (v1 2 = bit 2 of interrupt control register v1) snzt2 (skip if non zero condition of timer 2 interrupt request flag) 1010000001 281 11 v1 3 = 0: (t2f) = 1 grouping: timer operation description: when v1 3 = 0 : skips the next instruction when timer 2 interrupt request flag t2f is ?.?after skipping, clears (0) to the t2f flag. when the t2f flag is ?,?executes the next instruction. when v1 3 = 1 : this instruction is equiva- lent to the nop instruction. operation: v1 3 = 0: (t2f) = 1 ? after skipping, (t2f) 0 v1 3 = 1: snzt2 = nop (v1 3 = bit 3 of interrupt control register v1) machine instructions (index by alphabet) (continued) snzsi (skip if non zero condition of serial i/o interrupt request flag) snzt3 (skip if non zero condition of timer 3 interrupt request flag) 1010000010 282 11 v2 0 = 0: (t3f) = 1 grouping: timer operation description: when v2 0 = 0 : skips the next instruction when timer 3 interrupt request flag t3f is ?.?after skipping, clears (0) to the t3f flag. when the t3f flag is ?,?executes the next instruction. when v2 0 = 1 : this instruction is equiva- lent to the nop instruction. operation: v2 0 = 0: (t3f) = 1 ? after skipping, (t3f) 0 v2 0 = 1: snzt3 = nop (v2 0 = bit 0 of interrupt control register v2) 1010001000 288 11 v2 3 = 0: (siof) = 1 grouping: serial i/o operation description: when v2 3 = 0 : skips the next instruction when serial i/o interrupt request flag siof is ?.?after skipping, clears (0) to the siof flag. when the siof flag is ?,?executes the next instruction. when v2 3 = 1 : this instruction is equiva- lent to the nop instruction. operation: v2 3 = 0: (siof) = 1 ? after skipping, (siof) 0 v2 3 = 1: snzsi = nop (v2 3 = bit 3 of interrupt control register v2)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 104 of 156 4518 group snzt4 (skip if non zero condition of timer 4 inerrupt request flag) srst (system reset) sst (serial i/o transmission/reception start) 1010000011 283 11 v2 1 = 0: (t4f) = 1 grouping: timer operation description: when v2 1 = 0 : skips the next instruction when timer 4 interrupt request flag t4f is ?.?after skipping, clears (0) to the t4f flag. when the t4f flag is ?,?executes the next instruction. when v2 1 = 1 : this instruction is equiva- lent to the nop instruction. operation: v2 1 = 0: (t4f) = 1 ? after skipping, (t4f) 0 v2 1 = 1: snzt4 = nop (v2 1 = bit 1 of interrupt control register v2) 0000000001 001 11 grouping: other operation description: system reset occurs. operation: system reset occurrence 1010011110 29e 11 grouping: serial i/o operation description: clears (0) to siof flag and starts serial i/o. operation: (siof) 0 serial i/o transmission/reception start machine instructions (index by alphabet) (continued) szb j (skip if zero, bit) 00001000j j 02j 11 (mj(dp)) = 0 j = 0 to 3 grouping: bit operation description: skips the next instruction when the con- tents of bit j (bit specified by the value j in the immediate field) of m(dp) is ?. executes the next instruction when the con- tents of bit j of m(dp) is ?. operation: (mj(dp)) = 0 ? j = 0 to 3
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 105 of 156 4518 group machine instructions (index by alphabet) (continued) szc (skip if zero, carry flag) 0000101111 02f 11 (cy) = 0 grouping: arithmetic operation description: skips the next instruction when the con- tents of carry flag cy is ?. after skipping, the cy flag remains un- changed. executes the next instruction when the con- tents of the cy flag is ?. operation: (cy) = 0 ? szd (skip if zero, port d specified by register y) 0000100100 024 22 (d(y)) = 0 (y) = 0 to 7 grouping: input/output operation description: skips the next instruction when a bit of port d specified by register y is ?.?executes the next instruction when the bit is ?. t1ab (transfer data to timer 1 and register r1 from accumulator and register b) 1000110000 230 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 1 and timer 1 re- load register r1. transfers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1. operation: (t1 7 ?1 4 ) (b) (r1 7 ?1 4 ) (b) (t1 3 ?1 0 ) (a) (r1 3 ?1 0 ) (a) operation: (d(y)) = 0 ? (y) = 0 to 7 2 16 0000101011 02b t2ab (transfer data to timer 2 and register r2 from accumulator and register b) 1000110001 231 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 2 and timer 2 re- load register r2. transfers the contents of register a to the low-order 4 bits of timer 2 and timer 2 reload register r2. operation: (t2 7 ?2 4 ) (b) (r2 7 ?2 4 ) (b) (t2 3 ?2 0 ) (a) (r2 3 ?2 0 ) (a)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 106 of 156 4518 group t3ab (transfer data to timer 3 and register r3 from accumulator and register b) t4ab (transfer data to timer 4 and register r4l from accumulator and register b) t4hab (transfer data to register r4h from accumulator and register b) 1000110010 232 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 3 and timer 3 re- load register r3. transfers the contents of register a to the low-order 4 bits of timer 3 and timer 3 reload register r3. operation: (t3 7 ?3 4 ) (b) (r3 7 ?3 4 ) (b) (t3 3 ?3 0 ) (a) (r3 3 ?3 0 ) (a) 1000110011 233 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 4 and timer 4 re- load register r4l. transfers the contents of register a to the low-order 4 bits of timer 4 and timer 4 reload register r4l. operation: (t4 7 ?4 4 ) (b) (r4l 7 ?4l 4 ) (b) (t4 3 ?4 0 ) (a) (r4l 3 ?4l 0 ) (a) 1000110111 237 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of timer 4 and timer 4 re- load register r4h. transfers the contents of register a to the low-order 4 bits of timer 4 and timer 4 reload register r4h. operation: (r4h 7 ?4h 4 ) (b) (r4h 3 ?4h 0 ) (a) machine instructions (index by alphabet) (continued) t4r4l (transfer data to timer 4 from register r4l) 1010010111 297 11 grouping: timer operation description: transfers the contents of reload register r4l to timer 4. operation: (t4 7 ?4 4 ) (r4l 7 ?4l 4 ) (t4 3 ?4 0 ) (r4l 3 ?4l 0 )
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 107 of 156 4518 group tab (transfer data to accumulator from register b) 0000011110 01e 11 grouping: register to register transfer description: transfers the contents of register b to reg- ister a. tab1 (transfer data to accumulator and register b from timer 1) 1001110000 270 11 grouping: timer operation description: transfers the high-order 4 bits (t1 7 ?1 4 ) of timer 1 to register b. transfers the low-order 4 bits (t1 3 ?1 0 ) of timer 1 to register a. operation: (b) (t1 7 ?1 4 ) (a) (t1 3 ?1 0 ) tab2 (transfer data to accumulator and register b from timer 2) 1001110001 271 11 grouping: timer operation description: transfers the high-order 4 bits (t2 7 ?2 4 ) of timer 2 to register b. transfers the low-order 4 bits (t2 3 ?2 0 ) of timer 2 to register a. operation: (b) (t2 7 ?2 4 ) (a) (t2 3 ?2 0 ) operation: (a) (b) machine instructions (index by alphabet) (continued) tab3 (transfer data to accumulator and register b from timer 3) 1001110010 272 11 grouping: timer operation description: transfers the high-order 4 bits (t3 7 ?3 4 ) of timer 3 to register b. transfers the low-order 4 bits (t3 3 ?3 0 ) of timer 3 to register a. operation: (b) (t3 7 ?3 4 ) (a) (t3 3 ?3 0 )
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 108 of 156 4518 group tabp p (transfer data to accumulator and register b from program memory in page p) 0010p 5 p 4 p 3 p 2 p 1 p 0 0p 13 grouping: arithmetic operation operation: (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (pc l ) (dr 2 ?r 0 , a 3 ? 0 ) (dr 2 ) 0 (dr 1 , dr 0 ) (rom(pc)) 9, 8 (b) (rom(pc)) 7? (a) (rom(pc)) 3? (pc) (sk(sp)) (sp) (sp) ?1 8 +p description: transfers bits 9 and 8 to register d, bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in ad- dress (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in page p. note: p is 0 to 15 for m34518m2, and p is 0 to 31 for m34518m6, p is 0 to 47 for m34518m6, and p is 0 to 63 for m34518m8e8. when this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. tabe (transfer data to accumulator and register b from register e) 0000101010 02a 11 grouping: register to register transfer description: transfers the high-order 4 bits (e 7 ? 4 ) of register e to register b, and low-order 4 bits of register e to register a. operation: (b) (e 7 ? 4 ) (a) (e 3 ? 0 ) tabad (transfer data to accumulator and register b from register ad) 1001111001 279 11 grouping: a-d conversion operation description: in the a-d conversion mode (q1 3 = 0), trans- fers the high-order 4 bits (ad 9 ?d 6 ) of register ad to register b, and the middle-or- der 4 bits (ad 5 ?d 2 ) of register ad to register a. in the comparator mode (q1 3 = 1), transfers the middle-order 4 bits (ad 7 ?d 4 ) of register ad to register b, and the low-order 4 bits (ad 3 ?d 0 ) of register ad to register a. operation: in a-d conversion mode (q1 3 = 0), (b) (ad 9 ?d 6 ) (a) (ad 5 ?d 2 ) in comparator mode (q1 3 = 1), (b) (ad 7 ?d 4 ) (a) (ad 3 ?d 0 ) (q1 3 : bit 3 of a-d control register q1) tab4 (transfer data to accumulator and register b from timer 4) 1001110011 273 11 grouping: timer operation description: transfers the high-order 4 bits (t4 7 ?4 4 ) of timer 4 to register b. transfers the low-order 4 bits (t4 3 ?4 0 ) of timer 4 to register a. operation: (b) (t4 7 ?4 4 ) (a) (t4 3 ?4 0 ) machine instructions (index by alphabet) (continued)
skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 skip condition number of cycles number of words instruction code d 9 d 0 flag cy 2 16 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 109 of 156 4518 group tad (transfer data to accumulator from register d) 0001010001 051 11 grouping: register to register transfer description: transfers the contents of register d to the low-order 3 bits (a 2 ? 0 ) of register a. note: when this instruction is executed, ??is stored to the bit 3 (a 3 ) of register a. operation: (a 2 ? 0 ) (dr 2 ?r 0 ) (a 3 ) 0 machine instructions (index by alphabet) (continued) tabps (transfer data to accumulator and register b from prescaler) tabsi (transfer data to accumulator and register b from register si) 1001111000 278 11 grouping: serial i/o operation description: transfers the high-order 4 bits (si 7 ?i 4 ) of serial i/o register si to register b, and transfers the low-order 4 bits (si 3 ?i 0 ) of serial i/o register si to register a. operation: (b) (si 7 ?i 4 ) (a) (si 3 ?i 0 ) 1001110101 275 11 grouping: timer operation description: transfers the high-order 4 bits (tps 7 tps 4 ) of prescaler to register b, and transfers the low-order 4 bits (tps 3 ?ps 0 ) of prescaler to register a. operation: (b) (tps 7 ?ps 4 ) (a) (tps 3 ?ps 0 ) tadab (transfer data to register ad from accumulator from register b) 1000111001 239 11 grouping: a-d conversion operation description: in the a-d conversion mode (q1 3 = 0), this in- struction is equivalent to the nop instruction. in the comparator mode (q1 3 = 1), trans- fers the contents of register b to the high-order 4 bits (ad 7 ?d 4 ) of comparator register, and the contents of register a to the low-order 4 bits (ad 3 ?d 0 ) of compara- tor register. (q1 3 = bit 3 of a-d control register q1) operation: (ad 7 ?d 4 ) (b) (ad 3 ?d 0 ) (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 110 of 156 4518 group tai1 (transfer data to accumulator from register i1) 1001010011 253 11 grouping: interrupt operation description: transfers the contents of interrupt control register i1 to register a. operation: (a) (i1) tai2 (transfer data to accumulator from register i2) 1001010100 254 11 grouping: interrupt operation description: transfers the contents of interrupt control register i2 to register a. operation: (a) (i2) machine instructions (index by alphabet) (continued) tak0 (transfer data to accumulator from register k0) 1001010110 256 11 grouping: input/output operation description: transfers the contents of key-on wakeup control register k0 to register a. operation: (a) (k0) taj1 (transfer data to accumulator from register j1) 1001000010 242 11 grouping: serial i/o operation description: transfers the contents of serial i/o control register j1 to register a. operation: (a) (j1)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 111 of 156 4518 group tak1 (transfer data to accumulator from register k1) 1001011001 259 11 grouping: input/output operation description: transfers the contents of key-on wakeup control register k1 to register a. operation: (a) (k1) tak2 (transfer data to accumulator from register k2) 1001011010 25a 11 grouping: input/output operation description: transfers the contents of key-on wakeup control register k2 to register a. operation: (a) (k2) machine instructions (index by alphabet) (continued) tala (transfer data to accumulator from register la) 1001001001 249 11 grouping: a-d conversion operation description: transfers the low-order 2 bits (ad 1 , ad 0 ) of register ad to the high-order 2 bits (a 3 , a 2 ) of register a. note: after this instruction is executed, ??is stored to the low-order 2 bits (a 1 , a 0 ) of register a. operation: (a 3 , a 2 ) (ad 1 , ad 0 ) (a 1 , a 0 ) 0 tam j (transfer data to accumulator from memory) 101100 jjjj 2cj 11 grouping: ram to register transfer description: after transferring the contents of m(dp) to register a, an exclusive or operation is performed between register x and the value j in the immediate field, and stores the re- sult in register x. operation: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 112 of 156 4518 group taq1 (transfer data to accumulator from register q1) 1001000100 244 11 grouping: a-d conversion operation description: transfers the contents of a-d control regis- ter q1 to register a. operation: (a) (q1) tapu1 (transfer data to accumulator from register pu1) tapu0 (transfer data to accumulator from register pu0) 1001010111 257 11 grouping: input/output operation description: transfers the contents of pull-up control register pu0 to register a. operation: (a) (pu0) 1001011110 25e 11 grouping: input/output operation description: transfers the contents of pull-up control register pu1 to register a. operation: (a) (pu1) machine instructions (index by alphabet) (continued) 1001010010 252 11 grouping: clock operation description: transfers the contents of clock control reg- ister mr to register a. operation: (a) (mr) tamr (transfer data to accumulator from register mr)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 113 of 156 4518 group tasp (transfer data to accumulator from stack pointer) 0001010000 050 11 grouping: register to register transfer description: transfers the contents of stack pointer (sp) to the low-order 3 bits (a 2 ? 0 ) of register a. note: after this instruction is executed, ??is stored to the bit 3 (a 3 ) of register a. tav1 (transfer data to accumulator from register v1) 0001010100 054 11 grouping: interrupt operation description: transfers the contents of interrupt control register v1 to register a. operation: (a) (v1) operation: (a 2 ? 0 ) (sp 2 ?p 0 ) (a 3 ) 0 machine instructions (index by alphabet) (continued) taq3 (transfer data to accumulator from register q3) 1001000110 246 11 grouping: a-d conversion operation description: transfers the contents of a-d control regis- ter q3 to register a. operation: (a) (q3) taq2 (transfer data to accumulator from register q2) 1001000101 245 11 grouping: a-d conversion operation description: transfers the contents of a-d control regis- ter q2 to register a. operation: (a) (q2)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 114 of 156 4518 group taw2 (transfer data to accumulator from register w2) 1001001100 24c 11 grouping: timer operation description: transfers the contents of timer control reg- ister w2 to register a. operation: (a) (w2) machine instructions (index by alphabet) (continued) taw1 (transfer data to accumulator from register w1) 1001001011 24b 11 grouping: timer operation description: transfers the contents of timer control reg- ister w1 to register a. operation: (a) (w1) taw3 (transfer data to accumulator from register w3) 1001001101 24d 11 grouping: timer operation description: transfers the contents of timer control reg- ister w3 to register a. operation: (a) (w3) tav2 (transfer data to accumulator from register v2) 0001010101 055 11 grouping: interrupt operation description: transfers the contents of interrupt control register v2 to register a. operation: (a) (v2)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 115 of 156 4518 group taw5 (transfer data to accumulator from register w5) taw6 (transfer data to accumulator from register w6) 1001010000 250 11 grouping: timer operation description: transfers the contents of timer control reg- ister w6 to register a. tax (transfer data to accumulator from register x) 0001010010 052 11 grouping: register to register transfer description: transfers the contents of register x to reg- ister a. operation: (a) (x) operation: (a) (w6) 1001001111 24f 11 grouping: timer operation description: transfers the contents of timer control reg- ister w5 to register a. operation: (a) (w5) machine instructions (index by alphabet) (continued) taw4 (transfer data to accumulator from register w4) 1001001110 24e 11 grouping: timer operation description: transfers the contents of timer control reg- ister w4 to register a. operation: (a) (w4)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 116 of 156 4518 group tba (transfer data to register b from accumulator) 0000001110 00e 11 grouping: register to register transfer description: transfers the contents of register a to regis- ter b. tda (transfer data to register d from accumulator) 0000101001 029 11 grouping: register to register transfer description: transfers the contents of the low-order 3 bits (a 2 ? 0 ) of register a to register d. operation: (dr 2 ?r 0 ) (a 2 ? 0 ) operation: (b) (a) taz (transfer data to accumulator from register z) 0001010011 053 11 grouping: register to register transfer description: transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. note: after this instruction is executed, ??is stored to the high-order 2 bits (a 3 , a 2 ) of register a. operation: (a 1 , a 0 ) (z 1 , z 0 ) (a 3 , a 2 ) 0 machine instructions (index by alphabet) (continued) tay (transfer data to accumulator from register y) 0000011111 01f 11 grouping: register to register transfer description: transfers the contents of register y to regis- ter a. operation: (a) (y)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 117 of 156 4518 group tfr2a (transfer data to register fr2 from accumulator) tfr1a (transfer data to register fr1 from accumulator) tfr0a (transfer data to register fr0 from accumulator) 1000101000 228 11 grouping: input/output operation description: transfers the contents of register a to the port output structure control register fr0. operation: (fr0) (a) 1000101001 229 11 grouping: input/output operation description: transfers the contents of register a to the port output structure control register fr1. operation: (fr1) (a) 1000101010 22a 11 grouping: input/output operation description: transfers the contents of register a to the port output structure control register fr2. operation: (fr2) (a) machine instructions (index by alphabet) (continued) teab (transfer data to register e from accumulator and register b) 0000011010 01a 11 grouping: register to register transfer description: transfers the contents of register b to the high-order 4 bits (e 7 ? 4 ) of register e, and the contents of register a to the low-order 4 bits (e 3 ? 0 ) of register e. operation: (e 7 ? 4 ) (b) (e 3 ? 0 ) (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 118 of 156 4518 group ti1a (transfer data to register i1 from accumulator) 1000010111 217 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register i1. operation: (i1) (a) machine instructions (index by alphabet) (continued) ti2a (transfer data to register i2 from accumulator) tj1a (transfer data to register j1 from accumulator) 1000011000 218 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register i2. operation: (i2) (a) 1000000010 202 11 grouping: serial i/o operation description: transfers the contents of register a to serial i/o control register j1. operation: (j1) (a) tk0a (transfer data to register k0 from accumulator) 1000011011 21b 11 grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k0. operation: (k0) (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 119 of 156 4518 group tk1a (transfer data to register k1 from accumulator) 1000010100 214 11 grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k1. tk2a (transfer data to register k2 from accumulator) 1000010101 215 11 grouping: input/output operation description: transfers the contents of register a to key- on wakeup control register k2. operation: (k2) (a) operation: (k1) (a) machine instructions (index by alphabet) (continued) tma j (transfer data to memory from accumulator) 101011 jjjj 2bj 11 grouping: ram to register transfer description: after transferring the contents of register a to m(dp), an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. operation: (m(dp)) (a) (x) (x)exor(j) j = 0 to 15 tmra (transfer data to register mr from accumulator) 1000010110 216 11 grouping: other operation description: transfers the contents of register a to clock control register mr. operation: (mr) (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 120 of 156 4518 group tpu0a (transfer data to register pu0 from accumulator) 1000101101 22d 11 grouping: input/output operation description: transfers the contents of register a to pull- up control register pu0. operation: (pu0) (a) machine instructions (index by alphabet) (continued) tpaa (transfer data to register pa from accumulator) tpsab (transfer data to pre-scaler from accumulator and register b) 1010101010 2aa 11 grouping: timer operation description: transfers the contents of lowermost bit (a 0 ) register a to timer control register pa. operation: (pa 0 ) (a 0 ) 1000110101 235 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits of prescaler and prescaler reload register rps, and transfers the con- tents of register a to the low-order 4 bits of prescaler and prescaler reload register rps. operation: (rps 7 ?ps 4 ) (b) (tps 7 ?ps 4 ) (b) (rps 3 ?ps 0 ) (a) (tps 3 ?ps 0 ) (a) tpu1a (transfer data to register pu1 from accumulator) 1000101110 22e 11 grouping: input/output operation description: transfers the contents of register a to pull- up control register pu1. operation: (pu1) (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 121 of 156 4518 group tq2a (transfer data to register q2 from accumulator) machine instructions (index by alphabet) (continued) tq1a (transfer data to register q1 from accumulator) 1000000100 204 11 grouping: a-d conversion operation description: transfers the contents of register a to a-d control register q1. operation: (q1) (a) tq3a (transfer data to register q3 from accumulator) 1000000101 205 11 grouping: a-d conversion operation description: transfers the contents of register a to a-d control register q2. operation: (q2) (a) 1000000110 206 11 grouping: a-d conversion operation description: transfers the contents of register a to a-d control register q3. operation: (q3) (a) tr1ab (transfer data to register r1 from accumulator and register b) 1000111111 23f 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits (r1 7 ?1 4 ) of reload regis- ter r1, and the contents of register a to the low-order 4 bits (r1 3 ?1 0 ) of reload regis- ter r1. operation: (r1 7 ?1 4 ) (b) (r1 3 ?1 0 ) (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 122 of 156 4518 group machine instructions (index by alphabet) (continued) tr3ab (transfer data to register r3 from accumulator and register b) tsiab (transfer data to register si from accumulator and register b) 1000111011 23b 11 grouping: timer operation description: transfers the contents of register b to the high-order 4 bits (r3 7 ?3 4 ) of reload regis- ter r3, and the contents of register a to the low-order 4 bits (r3 3 ?3 0 ) of reload regis- ter r3. operation: (r3 7 ?3 4 ) (b) (r3 3 ?3 0 ) (a) 1000111000 238 11 grouping: serial i/o operation description: transfers the contents of register b to the high-order 4 bits (si 7 ?i 4 ) of serial i/o reg- ister si, and transfers the contents of register a to the low-order 4 bits (si 3 ?i 0 ) of serial i/o register si. operation: (si 7 ?i 4 ) (b) (si 3 ?i 0 ) (a) trga (transfer data to register rg from accumulator) 1000001001 209 11 grouping: clock control operation description: transfers the contents of register a to regis- ter rg. operation: (rg 0 ) (a 0 ) tv1a (transfer data to register v1 from accumulator) 0000111111 03f 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register v1. operation: (v1) (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 123 of 156 4518 group tw1a (transfer data to register w1 from accumulator) 1000001110 20e 11 grouping: timer operation description: transfers the contents of register a to timer control register w1. operation: (w1) (a) tw2a (transfer data to register w2 from accumulator) 1000001111 20f 11 grouping: timer operation description: transfers the contents of register a to timer control register w2. operation: (w2) (a) machine instructions (index by alphabet) (continued) 0000111110 03e 11 grouping: interrupt operation description: transfers the contents of register a to inter- rupt control register v2. operation: (v2) (a) tv2a (transfer data to register v2 from accumulator) tw3a (transfer data to register w3 from accumulator) 1000010000 210 11 grouping: timer operation description: transfers the contents of register a to timer control register w3. operation: (w3) (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 124 of 156 4518 group machine instructions (index by alphabet) (continued) tw5a (transfer data to register w5 from accumulator) tw6a (transfer data to register w6 from accumulator) 1000010011 213 11 grouping: timer operation description: transfers the contents of register a to timer control register w6. operation: (w6) (a) 1000010010 212 11 grouping: timer operation description: transfers the contents of register a to timer control register w5. operation: (w5) (a) grouping: timer operation description: transfers the contents of register a to timer control register w4. tw4a (transfer data to register w4 from accumulator) 1000010001 211 11 operation: (w4) (a) tya (transfer data to register y from accumulator) 0000001100 00c 11 grouping: register to register transfer description: transfers the contents of register a to regis- ter y. operation: (y) (a)
skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 skip condition number of cycles number of words instruction code flag cy 2 16 d 9 d 0 d 9 d 0 d 9 d 0 d 9 d 0 preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 125 of 156 4518 group wrst (watchdog timer reset) 1010100000 2a0 11 (wdf1) = 1 grouping: other operation description: skips the next instruction when watchdog timer flag wdf1 is ?.?after skipping, clears (0) to the wdf1 flag. when the wdf1 flag is ?,?executes the next instruction. also, stops the watchdog timer function when ex- ecuting the wrst instruction immediately after the dwdt instruction. operation: (wdf1) = 1 ? after skipping, (wdf1) 0 xam j (exchange accumulator and memory data) 101101 jjjj 2dj 11 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. operation: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 xamd j (exchange accumulator and memory data and decrement register y and skip) 101111 jjjj 2fj 11 (y) = 15 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the con- tents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. operation: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) ?1 machine instructions (index by alphabet) (continued) xami j (exchange accumulator and memory data and increment register y and skip) 101110 jjjj 2ej 11 (y) = 0 grouping: ram to register transfer description: after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is performed between regis- ter x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a re- sult of addition, when the contents of register y is 0, the next instruction is skipped. when the contents of register y is not 0, the next instruction is executed. operation: (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) + 1 2 16
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 126 of 156 4518 group (a) (b) (b) (a) (a) (y) (y) (a) (e 7 ? 4 ) (b) (e 3 ? 0 ) (a) (b) (e 7 ? 4 ) (a) (e 3 ? 0 ) (dr 2 ?r 0 ) (a 2 ? 0 ) (a 2 ? 0 ) (dr 2 ?r 0 ) (a 3 ) 0 (a 1 , a 0 ) (z 1 , z 0 ) (a 3 , a 2 ) 0 (a) (x) (a 2 ? 0 ) (sp 2 ?p 0 ) (a 3 ) 0 (x) x x = 0 to 15 (y) y y = 0 to 15 (z) z z = 0 to 3 (y) (y) + 1 (y) (y) ?1 (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) ?1 (a) (m(dp)) (x) (x)exor(j) j = 0 to 15 (y) (y) + 1 (m(dp)) (a) (x) (x)exor(j) j = 0 to 15 tab tba tay tya teab tabe tda tad taz tax tasp lxy x, y lz z iny dey tam j xam j xamd j xami j tma j machine instructions (index by types) 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 00010010z 1 z 0 0000010011 0000010111 101100 jjjj 101101 jjjj 101111 jjjj 101110 jjjj 101011 jjjj 01e 00e 01f 00c 01a 02a 029 051 053 052 050 3xy 048 +z 013 017 2cj 2dj 2fj 2ej 2bj 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ram addresses ram to register transfer register to register transfer
skip condition datailed description carry flag cy preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 127 of 156 4518 group continuous description (y) = 0 (y) = 15 (y) = 15 (y) = 0 transfers the contents of register b to register a. transfers the contents of register a to register b. transfers the contents of register y to register a. transfers the contents of register a to register y. transfers the contents of register b to the high-order 4 bits (e 7 ? 4 ) of register e, and the contents of regis- ter a to the low-order 4 bits (e 3 ? 0 ) of register e. transfers the high-order 4 bits (e 7 ? 4 ) of register e to register b, and low-order 4 bits (e 3 ? 0 ) of register e to register a. transfers the contents of the low-order 3 bits (a 2 ? 0 ) of register a to register d. transfers the contents of register d to the low-order 3 bits (a 2 ? 0 ) of register a. transfers the contents of register z to the low-order 2 bits (a 1 , a 0 ) of register a. transfers the contents of register x to register a. transfers the contents of stack pointer (sp) to the low-order 3 bits (a 2 ? 0 ) of register a. loads the value x in the immediate field to register x, and the value y in the immediate field to register y. when the lxy instructions are continuously coded and executed, only the first lxy instruction is executed and other lxy instructions coded continuously are skipped. loads the value z in the immediate field to register z. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next in- struction is skipped. when the contents of register y is not 0, the next instruction is executed. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. after transferring the contents of m(dp) to register a, an exclusive or operation is performed between reg- ister x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. subtracts 1 from the contents of register y. as a result of subtraction, when the contents of register y is 15, the next instruction is skipped. when the contents of register y is not 15, the next instruction is executed. after exchanging the contents of m(dp) with the contents of register a, an exclusive or operation is per- formed between register x and the value j in the immediate field, and stores the result in register x. adds 1 to the contents of register y. as a result of addition, when the contents of register y is 0, the next in- struction is skipped. when the contents of register y is not 0, the next instruction is executed. after transferring the contents of register a to m(dp), an exclusive or operation is performed between reg- ister x and the value j in the immediate field, and stores the result in register x.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 128 of 156 4518 group machine instructions (index by types) (continued) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 07n 08p +p 00a 00b 06n 018 019 007 006 02f 01c 01d 05c +j 04c +j 02j 026 025 07n 000111nnnn 0010p 5 p 4 p 3 p 2 p 1 p 0 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn la n tabp p am amc a n and or sc rc szc cma rar sb j rb j szb j seam sea n 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 arithmetic operation comparison operation bit operation (a) n n = 0 to 15 (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (note) (pc l ) (dr 2 ?r 0 , a 3 ? 0 ) (dr 2 ) 0 (dr 1 , dr 0 ) (rom(pc)) 9, 8 (b) (rom(pc)) 7 4 (a) (rom(pc)) 3 0 (sk(sp)) (pc) (sp) (sp) ?1 (a) (a) + (m(dp)) (a) (a) + (m(dp)) +(cy) (cy) carry (a) (a) + n n = 0 to 15 (a) (a) and (m(dp)) (a) (a) or (m(dp)) (cy) 1 (cy) 0 (cy) = 0 ? (a) (a) cy a 3 a 2 a 1 a 0 (mj(dp)) 1 j = 0 to 3 (mj(dp)) 0 j = 0 to 3 (mj(dp)) = 0 ? j = 0 to 3 (a) = (m(dp)) ? (a) = n ? note: p is 0 to 15 for m34518m2, p is 0 to 31 for m34518m4, p is 0 to 47 for m34518m6, p is 0 to 63 for m34518m8/e8.
skip condition datailed description carry flag cy preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 129 of 156 4518 group continuous description overflow = 0 (cy) = 0 (mj(dp)) = 0 j = 0 to 3 (a) = (m(dp)) (a) = n 0/1 1 0 0/1 loads the value n in the immediate field to register a. when the la instructions are continuously coded and executed, only the first la instruction is executed and other la instructions coded continuously are skipped. transfers bits 9 and 8 to register d, bits 7 to 4 to register b and bits 3 to 0 to register a. these bits 7 to 0 are the rom pattern in ad-dress (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers a and d in page p. when this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. adds the contents of m(dp) to register a. stores the result in register a. the contents of carry flag cy re- mains unchanged. adds the contents of m(dp) and carry flag cy to register a. stores the result in register a and carry flag cy. adds the value n in the immediate field to register a, and stores a result in register a. the contents of carry flag cy remains unchanged. skips the next instruction when there is no overflow as the result of operation. executes the next instruction when there is overflow as the result of operation. takes the and operation between the contents of register a and the contents of m(dp), and stores the re- sult in register a. takes the or operation between the contents of register a and the contents of m(dp), and stores the result in register a. sets (1) to carry flag cy. clears (0) to carry flag cy. skips the next instruction when the contents of carry flag cy is ?. stores the ones complement for register as contents in register a. rotates 1 bit of the contents of register a including the contents of carry flag cy to the right. sets (1) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). clears (0) the contents of bit j (bit specified by the value j in the immediate field) of m(dp). skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of m(dp) is ?. executes the next instruction when the contents of bit j of m(dp) is ?. skips the next instruction when the contents of register a is equal to the contents of m(dp). executes the next instruction when the contents of register a is not equal to the contents of m(dp). skips the next instruction when the contents of register a is equal to the value n in the immediate field. executes the next instruction when the contents of register a is not equal to the value n in the immediate field.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 130 of 156 4518 group b a bl p, a bla p bm a bml p, a bmla p rti rt rts 011a 6 a 5 a 4 a 3 a 2 a 1 a 0 00111p 4 p 3 p 2 p 1 p 0 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000010000 10p 5 p 4 00p 3 p 2 p 1 p 0 010a 6 a 5 a 4 a 3 a 2 a 1 a 0 00110p 4 p 3 p 2 p 1 p 0 10p 5 a 6 a 5 a 4 a 3 a 2 a 1 a 0 0000110000 10p 5 p 4 00p 3 p 2 p 1 p 0 0001000110 0001000100 0001000101 18a +a 0ep +p 2pa +a 010 2pp 1aa 0cp +p 2pa +a 030 2pp 046 044 045 1 2 2 1 2 2 1 1 1 1 2 2 1 2 2 1 2 2 subroutine operation return operation machine instructions (continued) n = 0 to 15 (pc l ) a 6 ? 0 (pc h ) p (note) (pc l ) a 6 ? 0 (pc h ) p (note) (pc l ) (dr 2 ?r 0 , a 3 ? 0 ) (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) 2 (pc l ) a 6 ? 0 (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (note) (pc l ) a 6 ? 0 (sp) (sp) + 1 (sk(sp)) (pc) (pc h ) p (note) (pc l ) (dr 2 ?r 0 ,a 3 ? 0 ) (pc) (sk(sp)) (sp) (sp) ?1 (pc) (sk(sp)) (sp) (sp) ?1 (pc) (sk(sp)) (sp) (sp) ?1 branch operation note: p is 0 to 15 for m34518m2, p is 0 to 31 for m34518m4, p is 0 to 47 for m34518m6, p is 0 to 63 for m34518m8/e8.
skip condition datailed description carry flag cy preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 131 of 156 4518 group skip at uncondition branch within a page : branches to address a in the identical page. branch out of a page : branches to address a in page p. branch out of a page : branches to address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. call the subroutine in page 2 : calls the subroutine at address a in page 2. call the subroutine : calls the subroutine at address a in page p. call the subroutine : calls the subroutine at address (dr 2 dr 1 dr 0 a 3 a 2 a 1 a 0 ) 2 specified by registers d and a in page p. returns from interrupt service routine to main routine. returns each value of data pointer (x, y, z), carry flag, skip status, nop mode status by the continuous de- scription of the la/lxy instruction, register a and register b to the states just before interrupt. returns from subroutine to the routine called the subroutine. returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
di ei snz0 snz1 snzi0 snzi1 tav1 tv1a tav2 tv2a tai1 ti1a tai2 ti2a tpaa taw1 tw1a taw2 tw2a taw3 tw3a taw4 tw4a (inte) 0 (inte) 1 v1 0 = 0: (exf0) = 1 ? after skipping, (exf0) 0 v1 0 = 1: snz0 = nop v1 1 = 0: (exf1) = 1 ? after skipping, (exf1) 0 v1 1 = 1: snz1 = nop i1 2 = 1 : (int0) = ??? i1 2 = 0 : (int0) = ?? ? i2 2 = 1 : (int1) = ??? i2 2 = 0 : (int1) = ?? ? (a) (v1) (v1) (a) (a) (v2) (v2) (a) (a) (i1) (i1) (a) (a) (i2) (i2) (a) (pa 0 ) (a 0 ) (a) (w1) (w1) (a) (a) (w2) (w2) (a) (a) (w3) (w3) (a) (a) (w4) (w4) (a) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 004 005 038 039 03a 03b 054 03f 055 03e 253 217 254 218 2aa 24b 20e 24c 20f 24d 210 24e 211 0000000100 0000000101 0000111000 0000111001 0000111010 0000111011 0001010100 0000111111 0001010101 0000111110 1001010011 1000010111 1001010100 1000011000 1010101010 1001001011 1000001110 1001001100 1000001111 1001001101 1000010000 1001001110 1000010001 interrupt operation timer operation parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation machine instructions (index by types) (continued) preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 132 of 156 4518 group
v1 0 = 0: (exf0) = 1 v1 1 = 0: (exf1) = 1 (int0) = ? however, i1 2 = 1 (int0) = ? however, i1 2 = 0 (int1) = ? however, i2 2 = 1 (int1) = ? however, i2 2 = 0 skip condition datailed description carry flag cy clears (0) to interrupt enable flag inte, and disables the interrupt. sets (1) to interrupt enable flag inte, and enables the interrupt. when v1 0 = 0 : skips the next instruction when external 0 interrupt request flag exf0 is ?.?after skipping, clears (0) to the exf0 flag. when the exf0 flag is ?,?executes the next instruction. when v1 0 = 1 : this instruction is equivalent to the nop instruction. (v1 0 : bit 0 of interrupt control register v1) when v1 1 = 0 : skips the next instruction when external 1 interrupt request flag exf1 is ?.?after skipping, clears (0) to the exf1 flag. when the exf1 flag is ?,?executes the next instruction. when v1 1 = 1 : this instruction is equivalent to the nop instruction. (v1 1 : bit 1 of interrupt control register v1) when i1 2 = 1 : skips the next instruction when the level of int0 pin is ?.?(i1 2 : bit 2 of interrupt control reg- ister i1) when i1 2 = 0 : skips the next instruction when the level of int0 pin is ?. when i2 2 = 1 : skips the next instruction when the level of int1 pin is ?.?(i2 2 : bit 2 of interrupt control reg- ister i2) when i2 2 = 0 : skips the next instruction when the level of int1 pin is ?. transfers the contents of interrupt control register v1 to register a. transfers the contents of register a to interrupt control register v1. transfers the contents of interrupt control register v2 to register a. transfers the contents of register a to interrupt control register v2. transfers the contents of interrupt control register i1 to register a. transfers the contents of register a to interrupt control register i1. transfers the contents of interrupt control register i2 to register a. transfers the contents of register a to interrupt control register i2. transfers the contents of register a to timer control register pa. transfers the contents of timer control register w1 to register a. transfers the contents of register a to timer control register w1. transfers the contents of timer control register w2 to register a. transfers the contents of register a to timer control register w2. transfers the contents of timer control register w3 to register a. transfers the contents of register a to timer control register w3. transfers the contents of timer control register w4 to register a. transfers the contents of register a to timer control register w4. preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 133 of 156 4518 group
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 134 of 156 4518 group 1001001111 1000010010 1001010000 1000010011 1001110101 1000110101 1001110000 1000110000 1001110001 1000110001 1001110010 1000110010 1001110011 1000110011 1000110111 1000111111 1000111011 1010010111 24f 212 250 213 275 235 270 230 271 231 272 232 273 233 237 23f 23b 297 (a) (w5) (w5) (a) (a) (w6) (w6) (a) (b) (tps 7 ?ps 4 ) (a) (tps 3 ?ps 0 ) (rps 7 ?ps 4 ) (b) (tps 7 ?ps 4 ) (b) (rps 3 ?ps 0 ) (a) (tps 3 ?ps 0 ) (a) (b) (t1 7 ?1 4 ) (a) (t1 3 ?1 0 ) (r1 7 ?1 4 ) (b) (t1 7 ?1 4 ) (b) (r1 3 ?1 0 ) (a) (t1 3 ?1 0 ) (a) (b) (t2 7 ?2 4 ) (a) (t2 3 ?2 0 ) (r2 7 ?2 4 ) (b) (t2 7 ?2 4 ) (b) (r2 3 ?2 0 ) (a) (t2 3 ?2 0 ) (a) (b) (t3 7 ?3 4 ) (a) (t3 3 ?3 0 ) (r3 7 ?3 4 ) (b) (t3 7 ?3 4 ) (b) (r3 3 ?3 0 ) (a) (t3 3 ?3 0 ) (a) (b) (t4 7 ?4 4 ) (a) (t4 3 ?4 0 ) (r4l 7 ?4l 4 ) (b) (t4 7 ?4 4 ) (b) (r4l 3 ?4l 0 ) (a) (t4 3 ?4 0 ) (a) (r4h 7 ?4h 4 ) (b) (r4h 3 ?4h 0 ) (a) (r1 7 ?1 4 ) (b) (r1 3 ?1 0 ) (a) (r3 7 ?3 4 ) (b) (r3 3 ?3 0 ) (a) (t4 7 ?4 0 ) (r4l 7 ?4l 0 ) taw5 tw5a taw6 tw6a tabps tpsab tab1 t1ab tab2 t2ab tab3 t3ab tab4 t4ab t4hab tr1ab tr3ab t4r4l 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 timer operation
skip condition datailed description carry flag cy preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 135 of 156 4518 group transfers the contents of timer control register w5 to register a. transfers the contents of register a to timer control register w5. transfers the contents of timer control register w6 to register a. transfers the contents of register a to timer control register w6. transfers the high-order 4 bits of prescaler to register b, and transfers the low-order 4 bits of prescaler to register a. transfers the contents of register b to the high-order 4 bits of prescaler and prescaler reload register rps, and transfers the contents of register a to the low-order 4 bits of prescaler and prescaler reload register rps. transfers the high-order 4 bits of timer 1 to register b, and transfers the low-order 4 bits of timer 1 to regis- ter a. transfers the contents of register b to the high-order 4 bits of timer 1 and timer 1 reload register r1, and transfers the contents of register a to the low-order 4 bits of timer 1 and timer 1 reload register r1. transfers the high-order 4 bits of timer 2 to register b, and transfers the low-order 4 bits of timer 2 to regis- ter a. transfers the contents of register b to the high-order 4 bits of timer 2 and timer 2 reload register r2, and transfers the contents of register a to the low-order 4 bits of timer 2 and timer 2 reload register r2. transfers the high-order 4 bits of timer 3 to register b, and transfers the low-order 4 bits of timer 3 to regis- ter a. transfers the contents of register b to the high-order 4 bits of timer 3 and timer 3 reload register r3, and transfers the contents of register a to the low-order 4 bits of timer 3 and timer 3 reload register r3. transfers the high-order 4 bits of timer 4 to register b, and transfers the low-order 4 bits of timer 4 to regis- ter a. transfers the contents of register b to the high-order 4 bits of timer 4 and timer 4 reload register r4l, and transfers the contents of register a to the low-order 4 bits of timer 4 and timer 4 reload register r4l. transfers the contents of register b to the high-order 4 bits of timer 4 reload register r4h, and transfers the contents of register a to the low-order 4 bits of timer 4 reload register r4h. transfers the contents of register b to the high-order 4 bits of timer 1 reload register r1, and transfers the contents of register a to the low-order 4 bits of timer 1 reload register r1. transfers the contents of register b to the high-order 4 bits of timer 3 reload register r3, and transfers the contents of register a to the low-order 4 bits of timer 3 reload register r3. transfers the contents of timer 4 reload register r4l to timer 4.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 136 of 156 4518 group 1010000000 1010000001 1010000010 1010000011 1001100000 1000100000 1001100001 1000100001 1001100010 1000100010 1001100011 1000100011 1001100110 1000100110 0000010001 0000010100 0000010101 0000100100 0000101011 1001010111 1000101101 1001011110 1000101110 280 281 282 283 260 220 261 221 262 222 263 223 266 226 011 014 015 024 02b 257 22d 25e 22e 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 snzt1 snzt2 snzt3 snzt4 iap0 op0a iap1 op1a iap2 op2a iap3 op3a iap6 op6a cld rd sd szd tapu0 tpu0a tapu1 tpu1a v1 2 = 0: (t1f) = 1 ? after skipping, (t1f) 0 v1 2 = 0: nop v1 3 = 0: (t2f) = 1 ? after skipping, (t2f) 0 v1 3 = 0: nop v2 0 = 0: (t3f) = 1 ? after skipping, (t3f) 0 v2 0 = 0: nop v2 1 = 0: (t4f) = 1 ? after skipping, (t4f) 0 v2 1 = 0: nop (a) (p0) (p0) (a) (a) (p1) (p1) (a) (a 2 ? 0 ) (p2 2 ?2 0 ) (a 3 ) 0 (p2 2 ?2 0 ) (a 2 ? 0 ) (a 1 , a 0 ) (p3 1 , p3 0 ) (p3 1 , p3 0 ) (a 1 , a 0 ) (a) (p6) (p6) (a) (d) 1 (d(y)) 0 (y) = 0 to 7 (d(y)) 1 (y) = 0 to 7 (d(y)) = 0 ? (y) = 0 to 7 (a) (pu0) (pu0) (a) (a) (pu1) (pu1) (a) input/output operation timer operation
skip condition datailed description carry flag cy preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 137 of 156 4518 group skips the next instruction when the contents of bit 2 (v1 2 ) of interrupt control register v1 is ??and the con- tents of t1f flag is ?.?after skipping, clears (0) to t1f flag. skips the next instruction when the contents of bit 3 (v1 3 ) of interrupt control register v1 is ??and the con- tents of t2f flag is ?.?after skipping, clears (0) to t2f flag. skips the next instruction when the contents of bit 0 (v2 0 ) of interrupt control register v2 is ??and the con- tents of t3f flag is ?.?after skipping, clears (0) to t3f flag. skips the next instruction when the contents of bit 1 (v2 1 ) of interrupt control register v2 is ??and the con- tents of t4f flag is ?.?after skipping, clears (0) to t4f flag. transfers the input of port p0 to register a. outputs the contents of register a to port p0. transfers the input of port p1 to register a. outputs the contents of register a to port p1. transfers the input of port p2 to register a. outputs the contents of register a to port p2. transfers the input of port p3 to register a. outputs the contents of register a to port p3. transfers the input of port p6 to register a. outputs the contents of register a to port p6. sets (1) to all port d. clears (0) to a bit of port d specified by register y. sets (1) to a bit of port d specified by register y. skips the next instruction when a bit of port d specified by register y is ?.?executes the next instruction when a bit of port d specified by register y is ?. transfers the contents of pull-up control register pu0 to register a. transfers the contents of register a to pull-up control register pu0. transfers the contents of pull-up control register pu1 to register a. transfers the contents of register a to pull-up control register pu1. v1 2 = 0: (t1f) = 1 v1 3 = 0: (t2f) =1 v2 0 = 0: (t3f) = 1 v2 1 = 0: (t4f) =1 (d(y)) = 0 however, (y)=0 to 7
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 138 of 156 4518 group tak0 tk0a tak1 tk1a tak2 tk2a tfr0a tfr1a tfr2a tabsi tsiab sst snzsi taj1 tj1a cmck crck cyck trga tamr tmra 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 256 21b 259 214 25a 215 228 229 22a 278 238 29e 288 242 202 29a 29b 29d 209 252 216 1001010110 1000011011 1001011001 1000010100 1001011010 1000010101 1000101000 1000101001 1000101010 1001111000 1000111000 1010011110 1010001000 1001000010 1000000010 1010011010 1010011011 1010011101 1000001001 1001010010 1000010110 input/output operation (a) (k0) (k0) (a) (a) (k1) (k1) (a) (a) (k2) (k2) (a) (fr0) (a) (fr1) (a) (fr2) (a) (b) (si 7 ?i 4 ) (a) (si 3 ?i 0 ) (si 7 ?i 4 ) (b) (si 3 ?i 0 ) (a) (siof) 0 serial i/o starting v2 3 =0: (siof)=1? after skipping, (siof) 0 v2 3 = 1: nop (a) (j1) (j1) (a) ceramic resonator selected rc oscillator selected quartz-crystal oscillator selected (rg 0 ) (a 0 ) (a) (mr) (mr) (a) machine instructions (index by types) (continued) serial i/o operation clock operation
skip condition datailed description carry flag cy preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 139 of 156 4518 group v2 3 = 0: (siof) = 1 transfers the contents of key-on wakeup control register k0 to register a. transfers the contents of register a to key-on wakeup control register k0 . transfers the contents of key-on wakeup control register k1 to register a. transfers the contents of register a to key-on wakeup control register k1. transfers the contents of key-on wakeup control register k2 to register a. transfers the contents of register a to key-on wakeup control register k2. transferts the contents of register a to port output format control register fr0. transferts the contents of register a to port output format control register fr1. transferts the contents of register a to port output format control register fr2. transfers the high-order 4 bits of serial i/o register si to register b, and transfers the low-order 4 bits of se- rial i/o register si to register a. transfers the contents of register b to the high-order 4 bits of serial i/o register si, and transfers the con- tents of register a to the low-order 4 bits of serial i/o register si. clears (0) to siof flag and starts serial i/o. skips the next instruction when the contents of bit 3 (v2 3 ) of interrupt control register v2 is ??and contents of siof flag is ?.?after skipping, clears (0) to siof flag. transfers the contents of serial i/o control register j1 to register a. transfers the contents of register a to serial i/o control register j1. selects the ceramic resonator for main clock f(x in ). selects the rc oscillation circuit for main clock f(x in ). selects the quartz-crystal oscillation circuit for main clock f(x in ). transfers the contents of clock control regiser rg to register a. transfers the contents of clock control regiser mr to register a. transfers the contents of register a to clock control register mr.
parameter instruction code function number of cycles number of words mnemonic type of instructions d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 hexadecimal notation preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 140 of 156 4518 group 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 279 249 239 29f 287 244 204 245 205 246 206 000 002 05b 003 2a0 29c 001 1001111001 1001001001 1000111001 1010011111 1010000111 1001000100 1000000100 1001000101 1000000101 1001000110 1000000110 0000000000 0000000010 0001011011 0000000011 1010100000 1010011100 0000000001 a-d conversion operation other operation machine instructions (index by types) (continued) tabad tala tadab adst snzad taq1 tq1a taq2 tq2a taq3 tq3a nop pof epof snzp wrst dwdt srst q1 3 = 0: (b) (ad 9 ?d 6 ) (a) (ad 5 ?d 2 ) q1 3 = 1: (b) (ad 7 ?d 4 ) (a) (ad 3 ?d 0 ) (a 3 , a 2 ) (ad 1 , ad 0 ) (a 1 , a 0 ) 0 (ad 7 ?d 4 ) (b) (ad 3 ?d 0 ) (a) (adf) 0 a-d conversion starting v2 1 = 0: (adf) = 1 ? after skipping, (adf) 0 v2 2 = 1: nop (a) (q1) (q1) (a) (a) (q2) (q2) (a) (a) (q3) (q3) (a) (pc) (pc) + 1 transition to ram back-up mode pof instruction valid (p) = 1 ? (wdf1) = 1 ? after skipping, (wdf1) 0 stop of watchdog timer function enabled system reset occurrence
skip condition datailed description carry flag cy preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 141 of 156 4518 group v2 2 = 0: (adf) = 1 (p) = 1 (wdf1) = 1 in the a-d conversion mode (q1 3 = 0), transfers the high-order 4 bits (ad 9 ?d 6 ) of register ad to register b, and the middle-order 4 bits (ad 5 ?d 2 ) of register ad to register a. in the comparator mode (q1 3 = 1), transfers the middle-order 4 bits (ad 7 ?d 4 ) of register ad to register b, and the low-order 4 bits (ad 3 ?d 0 ) of register ad to register a. (q1 3 : bit 3 of a-d control register q1) transfers the low-order 2 bits (ad 1 , ad 0 ) of register ad to the high-order 2 bits (ad 3 , ad 2 ) of register a. in the comparator mode (q1 3 = 1), transfers the contents of register b to the high-order 4 bits (ad 7 ?d 4 ) of comparator register, and the contents of register a to the low-order 4 bits (ad 3 ?d 0 ) of comparator register. (q1 3 = bit 3 of a-d control register q1) clears (0) to a-d conversion completion flag adf, and the a-d conversion at the a-d conversion mode (q1 3 = 0) or the comparator operation at the comparator mode (q1 3 = 1) is started. (q1 3 = bit 3 of a-d control register q1) when v2 2 = 0 : skips the next instruction when a-d conversion completion flag adf is ?.?after skipping, clears (0) to the adf flag. when the adf flag is ?,?executes the next instruction. (v2 2 : bit 2 of interrupt con- trol register v2) transfers the contents of a-d control register q1 to register a. transfers the contents of register a to a-d control register q1. transfers the contents of a-d control register q2 to register a. transfers the contents of register a to a-d control register q2. transfers the contents of a-d control register q3 to register a. transfers the contents of register a to a-d control register q3. no operation; adds 1 to program counter value, and others remain unchanged. puts the system in ram back-up state by executing the pof instruction after executing the epof instruction. makes the immediate after pof instruction valid by executing the epof instruction. skips the next instruction when the p flag is ?? after skipping, the p flag remains unchanged. skips the next instruction when watchdog timer flag wdf1 is ?.?after skipping, clears (0) to the wdf1 flag. also, stops the watchdog timer function when executing the wrst instruction immediately after the dwdt instruction. stops the watchdog timer function by the wrst instruction after executing the dwdt instruction. system reset occurs.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 142 of 156 4518 group instruction code table d 3 ed 0 hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f d 9 ed 4 00 nop srst pof snzp di ei rc sc e e am amc tya e tba e 000001 01 bla cld e iny rd sd e dey and or teab e cma rar tab tay 000010 02 szb 0 szb 1 szb 2 szb 3 szd sean seam e e tda tabe e e e e szc 000011 03 bmla e e e e e e e snz0 snz1 snzi0 snzi1 e e tv2a tv1a 000100 04 e e e e rt rts rti e lz 0 lz 1 lz 2 lz 3 rb 0 rb 1 rb 2 rb 3 000101 05 tasp tad tax taz tav1 tav2 e e e e e epof sb 0 sb 1 sb 2 sb 3 000110 06 a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 000111 07 la 0 la 1 la 2 la 3 la 4 la 5 la 6 la 7 la 8 la 9 la 10 la 11 la 12 la 13 la 14 la 15 001000 08 tabp 0 tabp 1 tabp 2 tabp 3 tabp 4 tabp 5 tabp 6 tabp 7 tabp 8 tabp 9 tabp 10 tabp 11 tabp 12 tabp 13 tabp 14 tabp 15 001001 09 tabp 16*** tabp 17*** tabp 18*** tabp 19*** tabp 20*** tabp 21*** tabp 22*** tabp 23*** tabp 24*** tabp 25*** tabp 26*** tabp 27*** tabp 28*** tabp 29*** tabp 30*** tabp 31*** 001010 tabp 32** tabp 33** tabp 34** tabp 35** tabp 36** tabp 37** tabp 38** tabp 39** tabp 40** tabp 41** tabp 42** tabp 43** tabp 44** tabp 45** tabp 46** tabp 47** 001011 001100 0c 001101 0d 001110 0e 001111 0f bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml*** bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bml bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl*** bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bl bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm bm 010000 010111 011000 011111 18e1f b b b b b b b b b b b b b b b b bl bml bla bmla sea szd the second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 *, **, *** cannot be used in the m34518m2. *, ** cannot be used in the m34518m4. * cannot be used in the m34518m6. 10e17 000000 the above table shows the relationship between machine language codes and machine language instructions. d 3 ed 0 show the low-order 4 bits of the machine language code, and d 9 ed 4 show the high-order 6 bits of the machine language code. the hexadecimal representa- tion of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each i nstruction is shown. do not use code marked e. the codes for the second word of a two-word instruction are described below. 0a tabp 48* tabp 49* tabp 50* tabp 51* tabp 52* tabp 53* tabp 54* tabp 55* tabp 56* tabp 57* tabp 58* tabp 59* tabp 60* tabp 61* tabp 62* tabp 63* 0b
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 143 of 156 4518 group instruction code table (continued) e e tj1a e tq1a tq2a tq3a e e trga e e e e tw1a tw2a tw3a tw4a tw5a tw6a tk1a tk2a tmra ti1a ti2a e e tk0a e e e e t1ab t2ab t3ab t4ab e tpsab e t4hab tsiab tadab e tr3ab e e e tr1ab e e taj1 e taq1 taq2 taq3 e e tala e taw1 taw2 taw3 taw4 taw5 taw6 e tamr tai1 tai2 e tak0 tapu0 e tak1 tak2 e e e tapu1 e iap0 iap1 iap2 iap3 e e iap6 e e e e e e e e e tab1 tab2 tab3 tab4 e tabps e e tabsi tabad e e e e e e snzt1 snzt2 snzt3 snzt4 e e e snzad snzsi e e e e e e e e e e e e e e t4r4l e e cmck crck dwdt cyck sst adst wrst e e e e e e e e e tpaa e e e e e tam 0 tam 1 tam 2 tam 3 tam 4 tam 5 tam 6 tam 7 tam 8 tam 9 tam 10 tam 11 tam 12 tam 13 tam 14 tam 15 xam 0 xam 1 xam 2 xam 3 xam 4 xam 5 xam 6 xam 7 xam 8 xam 9 xam 10 xam 11 xam 12 xam 13 xam 14 xam 15 xami 0 xami 1 xami 2 xami 3 xami 4 xami 5 xami 6 xami 7 xami 8 xami 9 xami 10 xami 11 xami 12 xami 13 xami 14 xami 15 xamd 0 xamd 1 xamd 2 xamd 3 xamd 4 xamd 5 xamd 6 xamd 7 xamd 8 xamd 9 xamd 10 xamd 11 xamd 12 xamd 13 xamd 14 xamd 15 lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy lxy tma 0 tma 1 tma 2 tma 3 tma 4 tma 5 tma 6 tma 7 tma 8 tma 9 tma 10 tma 11 tma 12 tma 13 tma 14 tma 15 bl bml bla bmla sea szd the second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 op0a op1a op2a op3a e e op6a e tfr0a tfr1a tfr2a e e tpu0a tpu1a e d 3 ed 0 hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 a b c d e f d 9 ed 4 20 100001 21 100010 22 100011 23 100100 24 100101 25 100110 26 100111 27 101000 28 101001 29 101010 2a 101011 2b 101100 2c 101101 2d 101110 2e 101111 2f 110000 111111 30e3f 100000 the above table shows the relationship between machine language codes and machine language instructions. d 3 ed 0 show the low- order 4 bits of the machine language code, and d 9 ed 4 show the high-order 6 bits of the machine language code. the hexadecimal representation of the code is also provided. there are one-word instructions and two-word instructions, but only the first word of each instruction is shown. do not use code marked e. the codes for the second word of a two-word instruction are described below.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 144 of 156 4518 group parameter supply voltage input voltage p0, p1, p2, p3, p6, d 0 ed 7 , reset, x in , vdce input voltage s ck , s in , cntr0, cntr1, int0, int1 input voltage a in0 ea in3 output voltage p0, p1, p2, p3, p6, d 0 ed 7 , reset output voltage s ck , s out , cntr0, cntr1 output voltage x out power dissipation operating temperature range storage temperature range conditions output transistors in cut-off state output transistors in cut-off state ta = 25 ?c 32p6u-a 32p4b symbol v dd v i v i v i v o v o v o p d topr tstg unit v v v v v v v mw ?c ?c ratings e0.3 to 6.5 e0.3 to v dd +0.3 e0.3 to v dd +0.3 e0.3 to v dd +0.3 e0.3 to v dd +0.3 e0.3 to v dd +0.3 e0.3 to v dd +0.3 300 1100 e20 to 85 e40 to 125 absolute maximum raings
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 145 of 156 4518 group recommended operating conditions 1 (mask rom version: ta = e20 ?c to 85 ?c, v dd = 1.8 to 5.5 v, unless otherwise noted) (one time prom version: ta = e20 ?c to 85 ?c, v dd = 2.5 to 5.5 v, unless otherwise noted) symbol v dd v dd v dd v ram v ss v ih v ih v ih v il v il v il i oh (peak) i oh (avg) i ol (peak) i ol (peak) i ol (peak) i ol (peak) i ol (avg) i ol (avg) i ol (avg) i ol (avg)
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 146 of 156 4518 group f(x in ) f(x in ) f(x in ) oscillation frequency (with a ceramic resonator) oscillation frequency (at rc oscillation) (note) oscillation frequency (with a ceramic resonator selected, external clock input) conditions mhz mhz mhz max. 6.0 4.4 2.2 1.1 6.0 4.4 2.2 6.0 4.4 6.0 4.4 2.2 6.0 4.4 6.0 4.4 4.8 3.2 1.6 0.8 4.8 3.2 1.6 4.8 3.2 4.8 3.2 1.6 4.8 3.2 4.8 limits mask rom version one time prom version v dd = 2.7 to 5.5 v mask rom version one time prom version min. typ. recommended operating conditions 2 (mask rom version: ta = e20 ?c to 85 ?c, v dd = 1.8 to 5.5 v, unless otherwise noted) (one time prom version: ta = e20 ?c to 85 ?c, v dd = 2.5 to 5.5 v, unless otherwise noted) parameter symbol unit note: the frequency is affected by a capacitor, a resistor and a microcomputer. so, set the constants within the range of the f requency limits. v dd = 4.0 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.0 to 5.5 v v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.0 to 5.5 v v dd = 1.8 to 5.5 v v dd = 2.0 to 5.5 v v dd = 1.8 to 5.5 v v dd = 4.0 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.5 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.5 to 5.5 v v dd = 2.5 to 5.5 v v dd = 4.0 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.0 to 5.5 v v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.0 to 5.5 v v dd = 1.8 to 5.5 v v dd = 2.0 to 5.5 v v dd = 1.8 to 5.5 v v dd = 4.0 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.5 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.5 to 5.5 v v dd = 2.5 to 5.5 v through mode frequency/2 mode frequency/4, 8 mode through mode frequency/2 mode frequency/4, 8 mode through mode frequency/2 mode frequency/4, 8 mode through mode frequency/2 mode frequency/4, 8 mode 6 4 .4 2 (2.5) 2.7 4 1.8 5.5 v dd [v] 2 .2 1.1 f(stck) [mhz] 3.2 4.8 2 (2.5) 2.7 4 1.8 5.5 v dd 1.6 0.8 when external clock is used when rc oscillation is used when ceramic resonance is used f(stck) [mhz] 4.4 2.7 5.5 v dd [v] f(stck) [mhz] ( ): one time prom version recommended operating operation recommended operating operation recommended operating operation
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 147 of 156 4518 group conditions limits parameter symbol unit mask rom version one time prom version cntr0, cntr1 cntr0, cntr1 s ck s ck mask rom version one time prom version oscillation frequency (with a quartz-crystal oscillator) timer external input frequency timer external input period (h and l pulse width) serial i/o external input frequency serial i/o external input frequency (h and l pulse width) power-on reset circuit valid supply voltage rising time f(x in ) f(cntr) tw(cntr) f(s ck ) tw(s ck ) tpon khz hz s hz s recommended operating conditions 3 (mask rom version: ta = e20 ?c to 85 ?c, v dd = 1.8 to 5.5 v, unless otherwise noted) (one time prom version: ta = e20 ?c to 85 ?c, v dd = 2.5 to 5.5 v, unless otherwise noted)
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 148 of 156 4518 group electrical characteristics 1 (mask rom version: ta = e20 ?c to 85 ?c, v dd = 1.8 to 5.5 v, unless otherwise noted) (one time prom version: ta = e20 ?c to 85 ?c, v dd = 2.5 to 5.5 v, unless otherwise noted) v oh v ol v ol v ol v ol i ih i il r pu v t+ e v te v t+ e v te f(ring) ? ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 149 of 156 4518 group electrical characteristics 2 (mask rom version: ta = e20 ?c to 85 ?c, v dd = 1.8 to 5.5 v, unless otherwise noted) (one time prom version: ta = e20 ?c to 85 ?c, v dd = 2.5 to 5.5 v, unless otherwise noted) i dd supply current at active mode (with a ceramic resonator, ring oscillator stop) at active mode (with a quartz-crystal oscillator, ring oscillator stop) at active mode (with a ring oscillator, f(x in ) stop) at ram back-up mode (pof instruction execution) ma ma ma
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 150 of 156 4518 group a-d converter recommended operating conditions (comparator mode included, ta = e20 ?c to 85 ?c, unless otherwise noted) symbol v dd v ia f(adck) parameter supply voltage analog input voltage a-d conversion clock frequency (note) conditions unit v v khz mask rom version one time prom version mask rom version one time prom version min. 2.0 3.0 0 0.8 0.8 0.8 0.8 0.8 0.8 typ. max. 5.5 5.5 v dd 334 245 3.9 1.8 334 123 limits v dd = 4.0 to 5.5 v v dd = 2.7 to 5.5 v v dd = 2.2 to 5.5 v v dd = 2.0 to 5.5 v v dd = 4.0 to 5.5 v v dd = 3.0 to 5.5 v note: definition of a-d conversion clock (adck) 11 10 01 00 0 1 instruction clock (instck) ring oscillator clock(ring) a-d conversion clock (adck) division circuit system clock (stck) instruction clock (instck) multi- plexer (cmck, crck, cyck) mr 0 1 0 mr 3 , mr 2 01 00 10 11 ring oscillator x in ceramic resonance rc oscillation internal clock generating circuit (divided by 3) quartz-crystal oscillation ring oscillator clock (ring) q3 1 , q3 0 q3 2 divided by 2 divided by 4 divided by 8 division circuit divided by 12 divided by 24 divided by 48 divided by 6 334 245 (123) 2.2 ( ): one time prom version 2.7 (3.0) 4 2 5.5 v dd [ v] 3.9 ( 15.3) 1.8 0.8 f(adck) [khz] recommended operating operation
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 151 of 156 4518 group a-d converter characteristics (ta = e20 ?c to 85 ?c, unless otherwise noted) symbol e e e v 0t v fst e ia dd t conv e e e parameter resolution linearity error differential non-linearity error zero transition voltage full-scale transition voltage absolute accuracy (quantization error excluded) aed operating current (note 1) a-d conversion time comparator resolution comparator error (note 2) comparator comparison time test conditions unit 2.7(3.0) v < < ?
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 152 of 156 4518 group basic timing diagram voltage drop detection circuit characteristics (ta = e20 ?c to 85 ?c, unless otherwise noted) test conditions ta = 25 ?c mask rom version one time prom version ta = 25 ?c mask rom version one time prom version v dd = 5 v v dd = 3 v v dd
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 153 of 156 4518 group table 23 product of built-in prom version prom size ( ? ? built-in prom version in addition to the mask rom versions, the 4518 group has the one time prom versions whose proms can only be written to and not be erased. the built-in prom version has functions similar to those of the mask rom versions, but it has prom mode that enables writing to built-in prom. rom type package product fig. 72 pin configuration of built-in prom version pin configuration (top view) 8 7 10 9 12 11 14 15 16 13 6 5 4 3 2 m34518e8sp 1 25 26 23 24 21 22 19 18 17 20 27 28 29 30 31 32 d 0 d 1 d 2 d 3 d 4 d 5 d 6 /cntr0 d 7 /cntr1 p2 0 /s ck p2 1 /s out p2 2 /s in reset cnv ss x out x in v ss p1 3 p1 2 p1 1 p1 0 p0 3 p0 2 p0 1 p0 0 p6 3 /a in3 p6 2 /a in2 p6 1 /a in1 p6 0 /a in0 p3 1 /int 1 p3 0 /int 0 vdce v dd 2 1 345678 23 24 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 d 3 d 4 d 5 d 6 /cntr0 d 7 /cntr1 p2 0 /s ck p2 1 /s out p2 2 /s in p0 2 p0 1 p0 0 p6 3 /a in3 p6 2 /a in2 p6 1 /a in1 p6 0 /a in0 p3 1 /int 1 p3 0 /int 0 vdce v dd v ss x in x out cnv ss reset p 0 3 p 1 0 p 1 1 p 1 2 p 1 3 d 0 d 1 d 2 m34518e8fp table 23 shows the product of built-in prom version. figure 73 shows the pin configurations of built-in prom versions. the one time prom version has pin-compatibility with the mask rom version.
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 154 of 156 4518 group (1) prom mode the built-in prom version has a prom mode in addition to a nor- mal operation mode. the prom mode is used to write to and read from the built-in prom. in the prom mode, the programming adapter can be used with a general-purpose prom programmer to write to or read from the built-in prom as if it were m5m27c256k. programming adapter is listed in table 24. contact addresses at the end of this data sheet for the appropriate prom programmer. writing and reading of built-in prom programming voltage is 12.5 v. write the program in the prom of the built-in prom version as shown in figure 73. (2) notes on handling ? ? fig. 73 prom memory map fig. 74 flow of writing and test of the product shipped in blank microcomputer m34518e8fp m34518e8sp name of programming adapter pca7442fp pca7442sp table 24 programming adapter a d d r e s s 0 0 0 0 1 6 3 f f f 1 6 7 f f f 1 6 1 1 1 d 4 d 3 d 2 d 1 d 0 h i g h - o r d e r 5 b i t s 1 1 1 d 4 d 3 d 2 d 1 d 0 l o w - o r d e r 5 b i t s 4 0 0 0 1 6 w r i t i n g w i t h p r o m p r o g r a m m e r s c r e e n i n g ( l e a v e a t 1 5 0 n o t e ) v e r i f y t e s t w i t h p r o m p r o g r a m m e r f u n c t i o n t e s t i n t a r g e t d e v i c e s i n c e t h e s c r e e n i n g t e m p e r a t u r e i s h i g h e r t h a n s t o r a g e t e m p e r a t u r e , n e v e r e x p o s e t h e m i c r o c o m p u t e r t o 1 5 0 n o t e :
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 155 of 156 4518 group package outline sdip32-p-400-1.78 weight(g) 2.2 jedec code eiaj package code lead material alloy 42/cu alloy 32p4b plastic 32pin 400mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ?.8 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 1.778 10.16 3.0 0 ?5 5.08 e e 1 32 17 16 1 e c e 1 a 2 a 1 b 2 b b 1 e la seating plane d mmp lqfp32-p-0707-0.80 weight(g) jedec code eiaj package code lead material cu alloy 3 2p6u-a plastic 32pin 7 ? 7mm body lqf p e 0.1 e ee 0.2 e e ee e e e e e symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 e e i 2 1.0 e e m d e e m e 10
preliminary notice: this is not a final specification. some parametric limits are subject to change. rev.2.00 2003.04.15 page 156 of 156 4518 group keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but ther e is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation p roduct best suited to the customer?s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporat ion or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party?s rights, origin ating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reas ons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest produ ct information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracie s or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas te chnology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp oration assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used un der circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor wh en considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or u ndersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com copyright ? 2003. renesas technology corporation, all rights reserved. printed in japan.
revision history rev. date description page summary (1/1) 4518 group data sheet 1.00 jan. 14, 2003 2.00 apr. 15, 2003 first edition issued some values of the following table are revised. recommended operating conditions 1; ?supply voltage (when quartz-crystal oscillator is used) ?ram back voltage recommended operating conditions 3; ?oscillation frequency (with a quartz-crystal oscillator) a-d converter recommended operating conditions; ?supply voltage ?a-d conversion clock frequency a-d converter characteristcs; ?linearity error ?differential non-linearity error ?zero transition voltage ?full-scale transition voltage ?comparator error voltage drop detection circuit; ?detection voltage (reset occurs) ?etection voltage (reset release) 145 147 150 151 152

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