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x24001 1 obsolete product 128 bit x24001 16 x 8 bit identi prom ?xicor, inc. 1991, 1995, 1996 patents pending characteristics subject to change without notice 3830-1.5 6/10/96 t2/c1/d0 ns features 2.7v to 5.5v power supply 128 bit serial e 2 prom low power cmos ?ctive current less than 1ma ?tandby current less than 50 a internally organized 16 x 8 2 wire serial interface high voltage programmable only ? pgm , 12v to 15v push/pull output high reliability ?ata retention: 100 years available packages ?-lead msop ?-lead pdip ?-lead soic description the x24001 is a cmos 128 bit serial e 2 prom, inter- nally organized as 16 x 8. the x24001 features a serial interface and software protocol allowing operation on a simple two wire bus. the x24001 is ideally suited for identification applica- tions such as serial numbers or device revision numbers which need to be stored and retrieved electronically. v pgm is used to enable writes to the device. this provides full protection of the data in the user? environ- ment where v pgm is not available. xicor e 2 proms are designed and tested for applica- tions requiring extended endurance. inherent data re- tention is greater than 100 years. the x24001 is fabricated with xicor? advanced cmos floating gate technology. identi prom is a trademark of xicor, inc. functional diagram control logic input/ output buffer scl sda command/address register shift register memory array 3830 fhd f01 pin configuration v cc nc scl sda 3830 fhd f02.1 nc nc nc v ss 1 2 3 4 8 7 6 5 x24001 msop/dip/soic
2 x24001 obsolete product pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it is a push/pull output and does not require the use of a pull-up resistor. during the program- ming operation, sda is an input. pin names symbol description nc no connect v ss ground v cc supply voltage sda serial data scl serial clock 3830 pgm t01 device operation the x24001 supports a bidirectional bus oriented proto- col. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. there- fore, the x24001 will be considered a slave in all appli- cations. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are re- served for indicating start and stop conditions. refer to figures 1 and 2. start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the x24001 continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. a start may be issued to terminate the input of a control word or the input of data to be written. this will reset the device and leave it ready to begin a new read or write command. because of the push/pull output, a start cannot be generated while the part is outputting data. starts are also inhibited while a write is in progress. stop condition the stop condition is a low to high transition of sda when scl is high. the stop condition is used to reset the device during a command or data input sequence and will leave the device in the standby mode. as with starts, stops are inhibited when outputting data and while a write is in progress.
x24001 3 obsolete product figure 1. data validity scl sda data stable data change 3830 fhd f03 figure 2. definition of start and stop conditions scl sda start condition stop condition 3830 fhd f04
4 x24001 obsolete product programming operation programming of the x24001 is performed one byte at a time. after each byte is written, a delay equal to the write cycle time of 5ms must be observed before initiating the next write cycle. the sequence of operations is: first raise the scl pin to v pgm and generate a high to low transition of sda (programming mode start). this is followed by eight bits of data containing the program command bits, four address bits and two don? care bits, immediately fol- lowed by the 8-bit data byte. the timing of the operation conforms to the standard a.c. timing requirements and follows the sequence shown below. after generating the programming mode start condition the scl high level can be either v ih or v pgm . factory programming service the x24001 can be programmed with customer specific data prior to shipment. the data programmed can be in two forms: static data pattern where there is no change in the data in a group of devices or sequential data, such as a base number incremented by one for each device tested and shipped. customers requiring one of these services should con- tact their local sales office for ordering procedures and service charges. figure 3. programming sequence v pgm v ih sda 01a3 a2 a1 a0 xx xx d7 d6 d5 d4 d3 d2 d1 d0 s t a r t scl 3830 fhd f05.1
x24001 5 obsolete product read operation the byte read operation is initiated with a start condition. the start condition is followed by an eight-bit control byte which consists of a two-bit read command (1,0), four address bits, and two ?on? care?bits. after receipt of the control byte, the x24001 will enter the read mode and transfer data into the shift register from the array. this data is shifted out of the device on the next eight scl clocks. at the end of the read, all counters are reset and the x24001 will enter the standby mode. as with a write, the read operation can be interrupted by a start or stop condition while the command or address is being clocked in. while clocking data out, starts or stops cannot be generated. during the second don? care clock cycle, starts and stops are ignored. the master must free the bus prior to the end of this clock cycle to allow the x24001 to begin outputting data (figures 4 and 5). 3830 fhd f07 figure 4. read sequence 3830 fhd f06 figure 5. read cycle timing 6781 sda in sck sda out a0 xx xx d7 d6 start 1 0 a3 a2 a1 a0 xx xx d7 d6 d5 d4 d3 d2 d1 d0 symbol table wa veform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
6 x24001 obsolete product *comment stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. capacitance t a = +25 c, f = 1mhz, v cc = 5v symbol parameter max. units test conditions c i/o (2) input/output capacitance (sda) 8 pf v i/o = 0v c in (2) input capacitance (scl) 6 pf v in = 0v 3830 pgm t05.1 notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. absolute maximum ratings* temperature under bias x24001 ...................................... ?5 c to +135 c storage temperature ....................... ?5 c to +150 c voltage on any pin with respect to v ss ............................................ ?v to +7v voltage on scl with respect to v ss .......................................... ?v to +17v d.c. output current ............................................. 5ma lead temperature (soldering, 10 seconds) .............................. 300 c d.c. operating characteristics (over recommended operating conditions unless otherwise specified.) limits symbol parameter min. max. units test conditions l cc1 v cc supply current read 1 ma scl = v cc x 0.1/v cc x 0.9 levels @ 1mhz, sda = open i sb1 v cc standby current 100 a scl = sda = v cc v cc = 5v 10% i sb2 v cc standby current 50 a scl = sda = v cc v cc = 3v i li input leakage current 10 av in = v ss to v cc i lo output leakage current 10 av out = v ss to v cc v ll (1) input low voltage ?.0 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 2.1ma v oh output high voltage v cc ?0.8 v i oh = 1ma v pgm program enable voltage 12 15 v 3830 pgm t04.3 supply voltage limits x24001 5v 10% x24001-3 3v to 5.5v x24001-2.7 2.7v to 5.5v 3830 pgm t03.1 recommended operating conditions temperature min. max. commercial 0 c +70 c industrial ?0 c +85 c military ?5 c +125 c 3830 pgm t02.1
x24001 7 obsolete product power-up timing symbol parameter max. units t pur (3) power-up to read operation 2 ms t puw (3) power-up to write operation 5 ms 3830 pgm t06 a.c. conditions of test input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 3830 pgm t07.1 equivalent a.c. load circuit symbol parameter min. max. units f scl scl clock frequency 0 1 mhz t aa scl low to sda data out valid 350 ns t buf time the bus must be free before a 500 ns new transmission can start t hd:sta start condition hold time 250 ns t low clock low period 500 ns t high clock high period 500 ns t su:sta start condition setup time 250 ns t hd:dat data in hold time 0 s t su:dat data in setup time 250 ns t r sda and scl rise time 1 s t f sda and scl fall time 300 ns t su:sto stop condition setup time 250 ns t dh data out hold time 50 ns 3830 pgm t08.1 a.c. characteristics (over the recommended operating conditions unless otherwise specified.) read & write cycle limits 3830 fhd f08.2 5v 2.16k ? 100pf output 3.07k ?
8 x24001 obsolete product bus timing t su:sta t hd:sta t hd:dat t su:dat t low t su:sto t r t buf scl sda in sda out t dh t aa t f t high 3830 fhd f09 write cycle limits symbol parameter min. max. units t wr (4) write cycle time 5 ms 3830 pgm t09 write cycle timing note: (3) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. these parameters are periodically sampled and not 100% tested. (4) the write cycle time is the time from the initiation of a write sequence to the end of the internal erase/program cycle. dur ing the write cycle, the x24001 bus interface circuits are disabled, sda is high impedance, and the device does not respond to start conditions. 3830 ill f10.1 sda t wr scl d0 start condtion x24001 address
x24001 9 obsolete product packaging information 0.118 0.002 (3.00 0.05) 0.040 0.002 (1.02 0.05) 0.150 (3.81) ref. 0.193 (4.90) ref. 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7 typ r 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ 8-lead miniature small outline gull wing package type m note: 1. all dimensions in inches and (millimeters) 3926 ill f49
10 x24001 obsolete product note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.110 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref. pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ. 0.010 (0.25) 0 15 8-lead plastic dual in-line package type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62) packaging information
x24001 11 obsolete product packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 3926 fhd f22.1 8-lead plastic small outline gull wing package type s note: all dimensions in inches (in parentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
12 x24001 obsolete product limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale on ly. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness tor any purpose. xicor, inc. rese rves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. us. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874, 967; 4,883,976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicor? products are not authorized for use as critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reaso nably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness. x24001 x x blank = 8-lead soic p = 8-lead plastic dip blank = 5v 10%, 0 c to +70 c i = 5v 10%, ?0 c to +85 c m = 5v 10%, ?5 c to +85 c d = 3v to 5.5v, 0 c to +70 c e = 3v to 5.5v, ?0 c to +85 c f = 2.7v to 5.5v, 0 c to +70 c g = 2.7v to 5.5v, ?0 c to +85 c ordering information device x24001 x x -x v cc range blank = 5v 10% 3 = 3v to 5.5v 2.7 = 2.7v to 5.5v temperature range blank = 0 c to +70 c i = ?0 c to +85 c m = ?5 c to +125 c package m = 8-lead msop p = 8-lead plastic dip s = 8-lead soic part mark convention

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