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november 2008 1 m9999- 111108 mic9130 micrel, inc. mic9130 high-voltage, high-speed telecom dc-to-dc controller general description the mic9130 is a current-mode pwm controller that ef ciently converts ?48v telecom voltages to logic levels. the mic9130 features a high voltage start-up circuit that allows the device to be connected to input voltages as high as 180v. the high input voltage capability protects the mic9130 from line transients that are common in telecom systems. the start-up circuitry also saves valuable board space and simpli es designs by integrating several external components. the mic9130 is capable of high speed operation. typically the mic9130 can control a sub-25ns pulse width on the gate out pin. its internal oscillator can operate over 2.5mhz, with even higher frequencies available through synchronisation. the high speed operation of the mic9130 is made safe by the very fast, 34ns response from current sense to output, minimizing power dissipation in a fault condition. the mic9130 allows for the designs of high ef ciency power supplies. it can achieve ef ciencies over 90% at high output currents. its low 1.3ma quiescent current allows high ef ciency even at light loads. the mic9130 has a maximum duty cycle of 50%. for de- signs requiring a high duty cycle, refer to the mic9131. the mic9130 is available in a 16-pin sop and 16-pin qsop package options. the rated junction temperature range is from ?40c to +125c. typical application out slope compensation isns fb vbias en sync cpwr agnd pgnd ss uvlo vcc line osc rbias comp 2 1 13 10 5 12 4 16 14 7 6 8 3 9 11 15 mic9130 vout 3.3v @ 4a vin 36v to 72v 12v opto feedback t1 si4884dy si4800dy b330 2.5 h 330 f (x2) 6.3v fqd10n20 0.2 200v 0.2 1w 332k 47pf 4.75k 332k 10nf 0.1 f 1m 38.3k mbr0540 40v/0.5a 1 f 16v 20 0.1 f 1.21k 20k n = 4 n = 20 n = 5 1.5mhz dsl power supply features ? input voltages up to 180v ? internal oscillator capable of >2.5mhz operation ? synchronisation capability to 4mhz ? current sense delay of 34ns ? minimum pulse width <25ns ? 90% ef ciency ? 1.3ma quiescent current ? 1 a shutdown current ? soft-start ? resistor programmable current sense threshold ? selectable soft-start retry ? 4 sink, 12 source output driver ? programmable under-voltage lockout ? constant-frequency pwm current-mode control ? 16-pin soic and 16-pin qsop applications ? telecom power supplies ? line cards ? isdn network terminators ? micro- and pico-cell base stations ? low power (< 30w) dc-dc converters micrel, inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel + 1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.mic rel.com
mic9130 micrel, inc. m9999- 111108 2 november 2008 pin description pin number pin name pin function 1 line line (input): 180vdc maximum supply input. may be oated if unused. 2 vcc supply (input): mic9130 internal supply input. 3 rbias bias resistor (external component): connect 562k to ground. 4 osc oscillator rc network (external components): connect external resistor- capacitor network to set oscillator frequency. 5 sync synchronization (input): external oscillator input for slave operation of controller. see osc. do not oat. 6 comp compensation (external components): error ampli er output for external compensation network connection. 7 fb feedback (input): error ampli er inverting input. 8 cpwr current limit selection (input): when cpwr is high, an over-current condition at the isns input will terminate the gate drive and reset the soft-start latch. if the cpwr pin is low, an over-current condition at the isns input will terminate the gate drive signal, but will not cause a reset of the soft-start circuit. 9 vbias reference (output): internal 5v supply. will source 5ma maximum. 10 en enable (input): logic level enable/shutdown input; logic high = enabled (on), logic low = shutdown (off). 11 agnd analog ground (return) 12 ss soft-start (external components): connect external capacitor to slowly ramp up duty cycle during startup and over-current conditions. 13 uvlo undervoltage lockout (external components): connect to unbiased resistive divider network to set controller?s minimum operating voltage. connect to vbias if not needed. 14 isns current sense (input): connect between external switching mosfet source and switch current sense resistor. 15 pgnd power ground (return) 16 out switch drive output (output): connect to gate of external switching mosfet. pin con guration 2 vcc 3 rbias 4 osc 5 sync 6 comp 7 fb 1 line 8 cpwr out 16 pgnd 15 isns 14 uvlo 13 ss 12 agnd 11 10 9 vbias en 16-pin sop (m) 16-pin qsop (qs) ordering information part number max. duty cycle junction temp. range package standard pb-free mic9130bm mic9130ym 50% -40c to +125c 16-pin sop mic9130bqs mic9130yqs 50% -40c to +125c 16-pin qsop
november 2008 3 m9999- 111108 mic9130 micrel, inc. absolute maximum ratings (note 1) line input voltage (v line ).......................................... +190v v cc input voltage (v cc ) .............................................. +19v current sense input voltage (v isns ) .............. ?0.3 to +5.3v enable voltage (v en )............................. ?0.3 to v cc + 0.3v feedback input voltage (v fb ) ........................ ?0.3 to +5.3v sync input voltage (v sync ) ............................ ?0.3 to +5.3v soft-start voltage (v ss ) .................................. ?0.3 to +5.3v uvlo voltage (v uvlo ) ................................... ?0.3 to +5.3v storage temperature (t s ) ........................ ?65c to +150c power dissipation (p d ) 16-pin sop ...................................400mw @ t a = +85c 16-pin qsop ................................245mw @ t a = +85c esd rating, note 3 operating ratings (note 2) line input voltage (v line )..................v cc to +180v, note 4 v cc input voltage (v cc ) .................................. +9v to +18v junction temperature range (t j ) ............ ?40c to +125c package thermal resistance 16-pin sop ( ja ) .............................................. 100c/w 16-pin qsop ( ja ) ............................................ 163c/w electrical characteristics t a = 25c, v line = 48v, v cc = 10v, r t = 9.47k , c t = 470pf, r bias = 562k , v en = 10v, v isns = 0v, v uvlo = 2v , v sync = 0v, unless otherwise noted. bold values indicate ?40 c t j +125c. parameter condition min typ max units bias regulator output voltage i vbias = 0ma; v osc = 0v (oscillator off) 4.7 4.85 5.0 v 4.6 5.1 v line regulation 9v v cc 18v, i vbias = 0ma; v osc = 0v 24 40 mv load regulation 0ma i vbias 5ma; v osc = 0v 5 30 mv oscillator section initial accuracy (f osc ) r t = 9.47k , c t = 470pf 180 200 220 khz oscillator output frequency f osc/2 khz maximum duty cycle 50 % voltage stability ( f/f) 9v v cc 18v 2.5 % temperature stability ?40c t j 125c 100 ppm/c maximum sync frequency note 5 4 mhz sync threshold level 2.5 v sync hysteresis 0.7 v sync minimum pulse width 50 ns error amp section fb voltage v comp = v fb 2.475 2.5 2.525 v 2.45 2.55 open loop voltage gain, a vol 90 db unity gain bandwidth 4 mhz psrr 9v v cc 18v 60 db comp sink current v fb = 2.7v; v comp = 5v 80 100 a comp source current v fb = 2.3v; v comp = 0v 1 2.5 ma v comp low v fb = 2.7v; i comp = ?50 a 115 300 mv v comp high v fb = 2.3v; i comp = +500 a 3.5 4 v input bias current (i fb ) v fb = v comp 160 na slew rate sink 1.5 v/ s source 1.5 v/ s
mic9130 micrel, inc. m9999- 111108 4 november 2008 parameter condition min typ max units preregulator input leakage current v line = 180v, v cc = 10v 0.1 10 a v cc gate lockout (v glo(on) ) v line = 48v 7.2 7.5 v v cc gate lockout hysteresis v line = 48v 700 800 mv ( v glo ) v cc pre-regulator off (v pr(off) ) v line = 48v v glo(on) v 7.7 +0.5v v cc pre-regulator hysteresis v line = 48v 500 700 mv ( v pr ) start-up current v line = 48v, v cc = 7.5v, note 4 9 12 ma supply supply current, i vcc pin 16 (out) = open 1.3 1.5 ma enable input current v en = 0v ,10v; v line = 48v ?10 0.1 10 a shutdown supply current v en = 0v ; v cc = 18v 0.1 10 a protection and control current limit threshold voltage 0.772 0.83 0.888 v current limit delay to output v isns = 0v to 5v 34 ns current limit source current v isns = 0v 30 40 50 a enable input threshold (turn-on) 1 1.6 2.2 v enable input hysteresis 150 mv cpwr input current v cpwr = 5v, 0v ?1 +1 a cpwr threshold 1.6 v soft-start current v ss = 0v 2.5 4 6 a line uvlo threshold (turn-on) 1.16 1.22 1.28 v line uvlo threshold hysteresis 140 mv thermal shutdown 145 c thermal shutdown hysteresis 25 c mosfet driver output minimum on-time v isns = 5v 21 ns output driver impedance source ; i source = 200ma 8 12 sink ; i sink = 200ma 4 6 rise time c out = 500pf 12 ns fall time c out = 500pf 8 ns note 1. exceeding the absolute maximum rating may damage the device. note 2. the device is not guaranteed to function outside its operating rating. note 3. devices are esd sensitive. handling precautions recommended. note 4. if a substained dc voltage >150v is applied to the line pin, a current-limiting 1.8k resistor should be used in series with the line pin. this condition does not apply for transient conditions over 150v. note 5. for oscillator frequencies above 2.5mhz it may be necessary to power to vbias pin from an external power source due to the cur rent limita- tions of the internal 5v regulator. see applications information for details
november 2008 5 m9999- 111108 mic9130 micrel, inc. typical characteristics -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 8 9 10 11 12 13 14 15 16 17 18 osc freq. variation (%) v cc (v) oscillator frequency vs. v cc voltage f osc(nom) =200khz r t =9.47k c t =470pf -5 -4 -3 -2 -1 0 1 2 3 4 5 -40 0 40 80 120 160 osc freq. variation (%) temperature (c) oscillator frequency vs. temperature v cc =10v r bias = 560k r t =9.47k c t = 470pf 2.499 2.500 2.501 2.502 8 9 10 11 12 13 14 15 16 17 18 reference voltage (v) v cc (v) error amp reference voltage vs. v cc voltage r bias = 560k 2.480 2.485 2.490 2.495 2.500 2.505 2.510 -40 -20 0 20 40 60 80 100120140 reference voltage (v) temperature (c) error amp reference voltage vs. temperature v cc =10v r bias = 560k 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 8 9 10 11 12 13 14 15 16 17 18 threshold (v) vcc (v) line uvlo threshold vs. v cc 1.18 1.19 1.2 1.21 1.22 1.23 1.24 -40 0 40 80 120 160 uvlo threshold (v) temperature (c) line uvlo threshold vs. temperature v cc =10v r bias =560k 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 8 1012141618 quiescent current (ma) v cc (v) quiescent current vs. v cc voltage r bias = 560k r t =9.47k c t = 470pf 1.3 1.31 1.32 1.33 1.34 1.35 1.36 1.37 1.38 1.39 1.4 -40 -20 0 20 40 60 80 100120140 quiescent current (ma) temperature (c) quiescent current vs. temperature v cc =10v r bias = 560k r t =9.47k c t = 470pf 0 1 2 3 4 5 6 7 8 9 10 0 200 400 600 800 1000 quiescent current (ma) gate drive frequency (khz) quiescent current vs. frequency c t = 120pf c t = 470pf 1 1.5 2 2.5 3 3.5 0 200 400 600 800 1000 1200 quiescent current (ma) r bias (k ) quiescent current vs. r bias v cc =10v r t =9.53k c t = 470pf f osc = 200khz 0 10 20 30 40 50 60 70 80 90 0 200 400 600 800 1000 1200 delay (ns) r bias (k ) isns to gate output delay vs. r bias 0 50 100 150 200 250 300 350 0 200 400 600 800 1000 1200 1400 1600 1800 2000 delay (ns) overdrive (mv) isns to gate output delay vs. overdrive r bias =160k r bias =560k r bias =360k
mic9130 micrel, inc. m9999- 111108 6 november 2008 4.94 4.96 4.98 5 5.02 5.04 5.06 -40 -20 0 20 40 60 80 100120140 bias voltage (v) temperature (c) 5v v bias voltage vs. temperature v cc = 10v r bias = 560k r t = 9.47k c t = 470pf 4.94 4.95 4.96 4.97 4.98 4.99 5 0 bias voltage (v) ibias (ma) bias voltage load regulation v cc =10v 12345 6.4 6.6 6.8 7 7.2 7.4 7.6 7.8 -40 -20 0 20 40 60 80 100120140 threshold (v) temperature (c) v cc turn on/off thresholds vs. temperature vcc g lo on vcc g lo off v cc =10v r bias =560k 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 8 9 10 11 12 13 14 15 16 17 18 sink/source current (a) v cc (v) gate drive current vs. v cc sink source 40 45 50 55 60 65 70 75 80 -40 0 40 80 120 160 short circuit current (ma) temperature (c) peak short circuit depletion fet current vs. temperature 48v line 180vline v cc =0v 40 45 50 55 60 65 70 75 80 0 40 80 120 160 200 short circuit current (ma) v line (v) peak short circuit depletion fet current vs. v line ?40c 25c 125c v cc =0v 818.0 818.5 819.0 819.5 820.0 820.5 821.0 821.5 822.0 8 9 10 11 12 13 14 15 16 17 18 threshold (mv) v cc (v) isns current limit threshold vs. v cc voltage r bias =560k 815 820 825 830 835 840 -40 0 40 80 120 160 threshold (mv) temperature (c) isns current limit threshold vs. temperature v cc = 10v r bias = 560k 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 8 9 10 11 12 13 14 15 16 17 18 threshold voltage (v) v cc (v) enable threshold vs. v cc 4.990 4.992 4.994 4.996 4.998 5.000 5.002 5.004 5.006 5.008 5.010 8 9 10 11 12 13 14 15 16 17 18 vbias (v) vcc (v) v bias vs. v cc r bias = 560k 0 2 4 6 8 10 12 0 40 80 120 160 current (ma) v line (v) depletion fet current vs. v line ?40c 25c 125c v cc =7.5v 0 1 2 3 4 5 6 7 8 9 10 7 7.5 8 8.5 9 9.5 10 current (ma) v line (v) depletion fet current vs. low v line voltage ?40c 125c 25c
november 2008 7 m9999- 111108 mic9130 micrel, inc. 35 36 37 38 39 40 41 42 43 44 45 -40 -20 0 20 40 60 80 100120140 isns current ( a) temperature (c) isns pin source current vs. temperature r bias =560k v cc =10v 38 38.5 39 39.5 40 40.5 41 41.5 42 8 1012141618 isns current ( a) v cc (v) isns pin source current vs. v cc r bias =560k
mic9130 micrel, inc. m9999- 111108 8 november 2008 functional block diagram rbias 1.21v out r s1 s2 q sr latch 2 oscillator sync osc 1.2v pwm comp r1 r2 s q peak current limit max. duty cycle 4 a 5v fb vcc pgnd 5v isns ss 2.5v vbias en vcc undervoltage lockou t thermal shutdown uvlo agnd bias reg 0.82v maximum dut y cycle vcc uvlo line uvlo line error amplifier 1-shot 5v cpwr current limit selection 40 a 14 7 64 5 16 15 11 13 9 12 8 2 1 10 3 figure 1 1000 10000 100000 1000000 10000 100000 1000000 10000000 resistor value ( ) frequency (hz) oscillator frequency vs. rc values 47pf 100 p f 220 p f 470 p f 680 p f 1000 p f 2200 p f *see applications section for higher switching frequencies
november 2008 9 m9999- 111108 mic9130 micrel, inc. functional description micrel?s mic9130 is a high voltage, high speed current mode switching power supply controller. it uses a bic/dmos pro- cess to achieve a high voltage input, low quiescent current and very fast internal delay times. the mic9130 is designed to drive an external low side n-channel mosfet, which makes it suitable for controlling boost, flyback and forward converter topologies. the high voltage startup pin eliminates the requirement for an external start up circuit. this makes it ideal for use with telecom converters. a block diagram of the mic9130 is shown in figure 1. the de- scription of the controller is divided into 6 basic functions: ? power and bias circuitry ? high voltage start-up circuit ? v cc and bias supplies ? enable and undervoltage monitoring circuits ? v cc and v in uvlo ? enable ? oscillator and sync circuitry ? soft-start and soft-start reset circuits ? mosfet gate drive circuits ? control loop operation ? current sensing & overcurrent protection ? slope compensation ? error ampli er high voltage start up circuit many conventional off-line and telecom power supplies use an external bias resistor and zener diode to supply the initial start-up voltage for the control ic. the control ic gets its supply voltage from a bias winding once the power sup- ply is running. this method has the disadvantages of extra components (diode and power resistor), continuous power dissipation in the resistor and a large bias capacitor, used to supply the ic until the bias winding takes over. the mic9130 eliminates these problems by using an internal depletion mode mosfet as a pre-regulator to provide the start-up bias voltage from the high voltage input of the power supply. this approach eliminates the need for external start up components and reduces the size of the controller?s bias supply capacitor. the mosfet is turned off once the external bias winding takes over, which eliminates power dissipation in the start-up circuit. in some cases, the mic9130 may be run directly from the input voltage rail, eliminating the need for an external bias winding. transformer bias winding v in 180v depletion fet internal circuitry mic9130 vcc 2 line 1 thermal shutdown 1.21v vcc uvlo ? v pr v pr(off) depletion fet pre-regultor turn-off threshold depletion fet turn-on threshold ? v glo v cc gate lockout hysteresis v cc voltage when powered from v line v glo(on) v cc gate lockout turn on threshold figure 2
mic9130 micrel, inc. m9999- 111108 10 november 2008 start-up circuit operation is illustrated in figure 2. v in is ap- plied and the depletion fet, which is normally enabled allows current from v in to charge the v cc bias capacitor. once the v cc voltage reaches the v cc enable threshold, v glo (on) , the gate drive is enabled and the mic9130 starts switching. v cc continues to increase until the pre-regulator turn-off threshold, (v pr (off)), is reached and the depletion fet is turned off. the v cc voltage decreases as energy from the bias capacitor is used to supply the controller. the deple- tion fet is turned back on when the pre-regulator turn-on threshold is reached. a bias winding derived supply voltage, set higher than the fet turn-off threshold, v pr (off), raises the v cc voltage over the threshold and prevents the fet from turning on. in certain designs the mic9130 may be powered directly from the line voltage, eliminating the need for an extra transformer bias winding. when operating in this fashion the designer must insure the power dissipation in the ic does not cause the die temperature to exceed the 125c maximum. power dissipation is calculated by: pvvi diss in cc vcc = ? () where : v in is the line input voltage v cc is the average v cc voltage (typically 8.5v) i vcc is the total current drawn by the ic i vcc is the sum of the operating current of the mic9130 at a given frequency and the average current required to drive the external switching mosfet. a plot of typical operating current vs. frequency is given in figure 3. the average mos- fet gate drive current is calculated in the ?mosfet gate drive? section of this speci cation. 0 1 2 3 4 5 6 7 8 9 10 0 200 400 600 800 1000 quiescent current (ma) gate drive frequency (khz) quiescent current vs. frequency c t = 120pf c t = 470pf figure 3 the die junction temperature is calculated by ttp ja diss ja =+ ja is the junction to ambient thermal resistance of the mic9130 (listed in the operating ratings section of the speci cation. when powered directly from the line voltage, the v cc volt- age will vary between the upper and lower pre-regulator thresholds. the amplitude of the output gate drive voltage will vary with the v cc voltage. this should not be a problem for most topologies since the variation is small (equal to the v pr hysteresis). the bias regulator in the mic9130 buffers the internal circuits from v cc variations. the pre-regulator fet is protected by a thermal shutdown circuit, which turns the mosfet off if its temperature exceeds approximately 150 degrees c. when operating at input voltages greater than 150v, a fast input voltage risetime during turn-on (which may occur during a hot plug operation) may cause a high peak current to ow through the depletion fet, damaging the mic9130. a 1.8k resistor in series between the input voltage and the line pin (pin 1) is recommended when operating at input voltages greater than 150v. this resistor limits the maximum peak current to 100ma (at 180v in ) and protects the part. the depletion mode mosfet contains an internal parasitic diode. the v in pin voltage must be greater than the v cc voltage or the v cc voltage will be clamped to a diode drop greater than the v in voltage. excessive power dissipation in the parasitic diode will destroy the ic. v cc and bias supplies the power for the controller and gate drive circuitry is sup- plied through the v cc pin. the gate drive current is returned to ground through the power ground pin (pgnd). the rest of the supply current is returned to ground through the analog ground pin (agnd). the two ground pins must be connected together through the pcb ground plane. high frequency decoupling is provided at the v cc pin to sup- ply the gate drive?s peak current requirements. turn-on of the external mosfet causes a voltage glitch on the v cc pin. if the glitch is excessive, this disruption can appear as noise or jitter in the oscillator circuit or the gate drive waveform. the decoupling capacitor must be able to supply the mosfet gate with the charge required to turn it on. a 0.1 f ceramic capacitor is usually suf cient for most mosfets. larger fets, with a higher gate charge requirement may require a 0.22 f ceramic capacitor or a ceramic capacitor paralleled with a 2.2 f tantalum or 4.7uf aluminum electrolytic. it is recommend that if v line is greater than 150v dc than the maximum capacitor recommended on v cc is 2.2 f.the ca- pacitor must be located next to the v cc pin of the mic9130. the ground end of the capacitor should be connected to the ground plane, making a low impedance connection to the power ground pin (pin 15). the internal bias regulator block provides several internal and external bias voltages. referring to figure 1, a 2.5v refer- ence is used for the internal error ampli er, a 0.82v bias is used by the current limit comparator and a 1.21v reference is used by the line uvlo circuit. an external 5v bias volt- age (v bias ) powers the oscillator circuit and may be used as a reference voltage for other external components. the v bias pin requires a minimum 0.1 f capacitor to ground for decoupling. enable and undervoltage monitoring circuits the two undervoltage lockout circuits in the mic9130 are shown in figure 4. one monitors the v cc voltage and the other monitors the input line voltage. these signals are or?d together and either one can disable the gate drive pin and discharge the voltage on the soft start capacitor.
november 2008 11 m9999- 111108 mic9130 micrel, inc. v cc undervoltage lockout the v cc voltage is internally divided down and compared to a 1.21v internal bandgap reference. as v cc rises above the turn-on threshold, it disables the vcc undervoltage lockout circuit. once above the turn-on threshold, hysteresis prevents the lockout circuit from disabling the ic until the v cc voltage falls below the lower threshold. line undervoltage circuit (uvlo) the line voltage is monitored by an external resistor divider and fed into the negative input of the line uvlo comparator. as the comparator trip point is exceeded, the line uvlo circuit is disabled. hysteresis built into the comparator prevents the circuit from toggling on an off in the presence of noise or a high input line impedance. the line voltage turn-on trip point is: vv r2 r1 r2 line_on threshold = + where: v threshold is the voltage level of the internal comparator reference, typically 1.21v. the line hysteresis is equal to: vv r1 r2 r2 hysteresis hyst = + where: v hyst is the internal hysteresis level, typically 75mv. v hysteresis is the hysteresis of the line input voltage the mic9130 will be disabled when the line voltage drops back down to: vvv vv r2 r1 r2 line_off line_on hyteresis threshold hyst = ? = ? () + enable a low level on the enable pin turns off all the functions of the mic9130 and places it in a low quiescent current state. the output driver is in a low state. when the enable pin is pulled high, the mic9130 goes through its normal start up sequence including undervoltage lock out and soft start. when not used, the pin should be connected to v cc . oscillator block an external resistor and capacitor set the oscillator frequency. the mic9130 contains an internal divide-by-two circuit that limits the maximum duty cycle at the gate drive to 50%. the oscillator frequency for the mic9130 is twice the output switching frequency. oscillator pin the operation of the oscillator is shown in figure 5. the volt- age waveform at the osc pin is a sawtooth whose amplitude increases as capacitor cosc is charged up through r osc from the 5v bias. when the osc pin voltage reaches the internal comparator upper threshold, c osc is quickly discharged to zero volts by an internal mosfet. after a brief delay, typi- cally 75ns, the internal mosfet is turned off and the c osc charges, repeating the cycle. figure 5 show the relationship between the oscillator and gate drive waveforms. the delays in the ic force the duty cycle of the gate drive signal to be slightly less than 50% duty cycle (typically 48%). for v bias = 5v and a peak oscillator waveform voltage of 3v, the design equations simplify to: charging t charge tt rc = 092 . discharging tc discharge t 40 mic9130 s set reset r q /q line uvlo vcc uvlo v cc a gnd v in uvlo uvlo r1 1.21v r2 2 11 13 pgnd 15 out 16 ss 4 a 5v 12 figure 4: uvlo and soft start circuits
mic9130 micrel, inc. m9999- 111108 12 november 2008 tttt where t p_oscillator charge discharge delay delay =+ + =75ns f t s oscillator p oscillator _ _ = 1 ff s outpu s oscillator __ = 1 4 the timing capacitor, c osc , should be an npo ceramic or a temperature stable lm capacitor. care must be taken when using capacitor values less than 47pf. the high impedance of a small value capacitor makes the osc pin more susceptible to switching noise. also, the input capacitance of the osc pin and the stray capacitance of the board will have a noticeable effect on the oscillator frequency. 75ns 1-shot 3v sync vbias osc r osc c osc agnd v osc gate drive (pin 16) t on t period 4 9 5 11 figure 5a higher switching frequencies the mic9130 is capable of very high switching frequencies. one of the limitations on the maximum frequency is the cur- rent capability of the 5v regulator supplying the oscillator and v bias . by powering v bias with an external source, e.g. linear regulator much higher switching frequencies can be achieved. a simple way of using an external current source is to set an npn as an emitter follower. figure 5b shows the mic9130 oscillator frequency set to 4mhz using an external npn. the emitter followerj circuit allows the current to be supplied by v cc while the voltage is regulated to a diode drop below v bias . this con guration is quite stable over temperature and voltage variations. 75ns 1-shot 3v sync vbias osc r osc 1.6k c osc 33pf agnd 4 9 5 11 vcc 2 1 f 4.7 f 4.7 f 2n3904 figure 5b oscillator synchronization the switching frequency of the mic9130 can be synchronized to an external oscillator or frequency source. figure 6 shows the relationship between the sync input, oscillator waveform and gate drive output. the external frequency should be set at least 15% greater than the free running oscillator frequency to account for tolerances in the oscillator circuit and external components. the positive edge of the sync signal resets the oscillator. the sync pulse frequency, like the oscillator, is twice the gate drive frequency. when an external sync signal is applied, the peak amplitude of the oscillator signal (pin 4) is less than when it is free running because the oscillator signal is terminated before it reaches its 3v (typical) amplitude. when not used, the sync pin should be connected to ground to prevent noise from erroneously resetting the oscillator. time (500ns/div) sync input (pin 5) gate drive (pin 16) oscillator waveform (pin 4) figure 6. sync waveform soft start circuit the soft start is programmed by a capacitor on the soft start pin. a 4 a current source charges up the capacitor. at power up, the ss pin is discharged. once the uvlo and enable functions release the soft start circuit, the voltage of the ca- pacitor increases. the active voltage range of the soft start pin is from typically from 0.9v to 1.7v. the internal current source increases the voltage on the soft start capacitor to approximately 4v. the soft start pin and the current sense voltage are connected to a comparator in t? pmic9130. the voltage from the soft start pin effectively limits the peak current through the current sense resistor by prematurely terminating the on-time of the gate drive output. referring to figure 1, with the soft start voltage low, the duty cycle of the output is at a minimum. as the soft start voltage increases, the duty cycle of the gate drive output increases
november 2008 13 m9999- 111108 mic9130 micrel, inc. until the error ampli er takes control of the duty cycle. the soft start capacitor is discharged by an internal mosfet in the mic9130. the soft start circuit is activated by the following events: 1. line undervoltage pin less than the 1.21v threshold 2. v cc becomes less than the pre-regulator voltage turn .................................................................off threshold. 3. the current limit comparator threshold is exceeded. this can be disabled with a low level on the cpwr pin. 4. a low level on the enable pin. calculating the soft capacitor depends on many parameters such as the current limit of the circuit input voltage, output power and output loading. a starting value of capacitor should be chosen and the value can be adjusted later in the design. recommended starting values of soft start capacitance is typically 10nf to 100nf. values below 1nf may be ineffective in slowing the output voltage turn on time. cpwr current limit selection this pin controls whether the soft start circuit is reset if the voltage on the isns pin exceeds the overcurrent threshold. when the cpwr pin is high, an overcurrent condition at the isns pin will terminate the on-time of the gate drive pulse and discharge the soft start capacitor to zero volts. this delay in start up contributes to a reduction in the average output current during an overcurrent or short circuit condition. a smaller mosfet may be used since the power dissipation in the mosfet is minimized under short circuit or overcur- rent conditions. if the cpwr pin is low an overcurrent or short circuit condi- tions will not trip the soft start circuit. the pulse-by-pulse current limit, inherent in current mode control, provides a ?brick wall? or constant current limit. with the power supply operating in this mode, a smaller soft start capacitor can be used to increase the turn on speed of the supply. if the cpwr in is held low during the initial turn on at power up and then raised high, the power supply can maximize the turn-on time at start up and still provide a high level of overcurrent and short circuit protection. the circuit shown in figure 7 performs this function. v ref cpwr r1 d1 c1 agnd mic9130 figure 7 mosfet gate drive output the mic9130 has the capability to directly drive the gate of a mosfet. the output driver consists of a complimentary p-channel and n-channel pair. the typical switching time of the output is dependent on the ic supply voltage and the gate charge required to turn the mosfet on and off. a resistor placed in series with the gate drive output attenu- ates ringing in the etch connection between the mic9130 and the mosfet. figure 8 shows a single resistor in series between the driver output and the gate of the mosfet. the zener value should be greater than the gate drive voltage to prevent excessive power dissipation, but less than the maximum gate to source voltage rating. gate drive output gnd figure 8 the circuitry shown in gure 9 allow different rise and fall times. r1 and the input capacitance of the mosfet determine the rise-time of the gate voltage and therefore the turn-on time of the mosfet. the diode, d1 is reversed biased, which removes r2 from the circuit. at turn-off, d1 is forward biased and the parallel combination of r1 and r2 controls the turn-off time of the mosfet. the turn on-time is slower, which reduces switching noise and ringing during turn-on. the turn-off time is faster, which minimizes switching losses during turn-off and improves ef ciency. if the turn-on time is to be faster than the turn-off time, the diode should be reversed. gate drive output gnd r2 d1 r1 figure 9 a gate drive transformer is used where an increase in drive voltage, isolation and/or voltage level shifting are required. gate drive transformers can have multiple windings and drive multiple mosfets, including mosfets that require a drive signal 180 degrees out of phase with the ics drive signal. figure 10 shows a gate drive transformer circuit. the ca- pacitor, c1 removes dc from the drive circuit and prevents transformer saturation. r1 provides damping to eliminate ringing in the circuit. r1 is usually in the 5 to 20 range, depending on the amount of damping necessary. d1 and d2 form a clamp circuit, which prevents the voltage from exceeding the v gmax level. if the gate drive is well damped, the diodes may be removed r2 is used to allow the trans- former to reset properly.
mic9130 micrel, inc. m9999- 111108 14 november 2008 gate drive output gnd t1 1:n r1 r2 d2 d1 c1 figure 10 the gate impedance of a mosfet is capacitive and the power required to drive the gate is proportional to the charge required to turn on the mosfet, the peak gate voltage and the switching frequency. assuming the total gate charge for turn on and turn off is equal, the power used to switch the mosfet on and off is: pqvf drive ggss = where: q g is the total gate charge at v gs v gs is the gate to source voltage of the mosfet usually equal to v cc f s is the output switching frequency the power required to drive the mosfet is dissipated in the drive circuitry of the mic9130. this power must not cause the die temperature to exceed the maximum rated junction temperature of 125 degrees c. mosfet driver ic?s are used when the drive requirement for the mosfets is greater than the capability of the mic9130 gate drive output. while the peak current of the mic9130 gate drive is typically 1.2a at v in =12v, a gate driver ics will sink or source between 1.2a and 12a of peak current. the higher peak current allows faster rise and fall times for larger mosfets. the drive requirements for selecting a mosfet driver are determined using the following equation: i q t pk g = 2 where: q g is the total gate charge required to turn on the mosfet at a speci ed i d , v g and v ds . this information is usually given in the mosfet speci cation sheet. t is the gate voltage transition time (risetime or fall time) i pk is the peak current requirement of the mosfet driver ic. for example, if a mosfet is chosen with a q g of 60nc and it is desired to have a 50ns gate to source risetime/falltime, the peak current requirement of the mosfet driver is: i nc ns a pk = = 260 50 24 . a driver such as the mic4424 will meet this requirement. for more information on choosing a mosfet driver, see the micrel application note an-24, ? designing with low side mosfet drivers .? current sense circuit the current sense input of the mic9130 has three unique features, which are advantageous in a high speed, high ef- ciency power supply. 1. the overcurrent threshold is nominally 0.82v instead of the typical 1.0v found in most switching control ics. 2. the current sense pin sources a nominal 40 a of current out of the pin. this is used to raise the current limit threshold of the pin, which allows a smaller current sense resistor to be used. this improves the ef ciency of the power supply, especially in lower current applications. 3. the delay from the current sense input to the output is typically 50ns. the current limit threshold of the isns pin was set at 0.82v, allowing the use of a smaller current sense resistor. a stable, bandgap derived 40 a current is sourced from the isns pin. a voltage drop across a series resistor placed between the pin and the current sense resistor level increases the current sense signal at the isns pin. this allows the use of a smaller current sense resistor if the full 0.82v peak to peak current signal is not required. decreasing the value of the current sense resistor decreases the power dissipation in the resistor, which improves the ef ciency of the power supply. the delay between the input of the overcurrent comparator and the output gate drive is nominally 50ns. this very fast response time allows the mic9130 to operate at higher fre- quencies and still have adequate overcurrent protection. the operation of the current sense input is as follows. the sensed current in the power supply is converted to a volt- age by a resistor or current sense transformer. referring to figure 1, this voltage is compared to the output of the error ampli er, which sets the duty cycle of the gate drive output. the current signal is also connected to an imax comparator. comparing the current sense signal to the reference voltage sets a maximum current limit. if the maximum amplitude of the current sense signal exceeds the reference, the comparator terminates the gate drive output pulse. it aslo discharges the soft start capacitor when the cpwr pin is high. leading edge current spike the current signal in a power circuit will often have a leading edge spike caused by leakage inductance, parasitic induc- tance and capacitance, diode reverse recovery effects and snubbers. these spikes can cause premature termination of the switching cycle if they are not eliminated. a resistor may be added in series between the current sense resistor and the isns input. the input and board trace ca- pacitance of the isns pin (pin 14) is approximately 25pf. a 1k resistor is a good choice, since it attenuates most of the ripple without distorting the current sense waveform. it has a minimal effect on level, offsetting the current sense signal by only 40mv. a typical rule of thumb is the bandwidth of the rc lter should be at least 6 times the switching frequency. this avoids distorting the current sense waveform and adding excessive delays in the current loop that will interfering with overcurrent protection. for a 100khz switcher, the maximum
november 2008 15 m9999- 111108 mic9130 micrel, inc. series resistance is 10k, for a 500khz switcher, the maximum series resistance is 2k. sensing current with a resistor the fast transition times of the current signal prohibit the use of inductive resistors. standard wire wound power resistors will not work. carbon composition or metal lm resistors or low inductance power resistors may be used. the overcurrent range of the power supply and component tolerances must be considered when selecting the current sense resistor value. the power supply speci cation may call for an overcurrent limit, which must be accounted for when selecting the cur- rent sense resistor value. the relationship between the peak primary current and the current sense resistor is: vir ir isns p isense isns f = + where: ip is the current in the sense resistor r isense is the current sense resistance i isns is the current sourced from the isns pin (40 a) r f is the series resistor between the isns pin and the current sense resistor. the current sense resistor must not be too small or the cur- rent sense signal will be susceptible to noise. if noise is a problem, the current signal level should be increased. an example is illustrated below. the maximum peak current, i pmax = 1a at 120% overcurrent and minimum input voltage the maximum rms current, i rms =0.65a the desired current sense signal amplitude is 500mv at 1a output current. the current sense resistor value and power dissipation is: r v i 0.5 1 0.5 sense sense sense === , non inductive resistor with at least a 1/2w rating should be selected. the series resistor is calculated to allow the 500mv-peak signal to reach 0.82v. r vir ia k f isns p isense isns ? () = ? () = 082 1 05 40 10 25 .. . the next lower value of 10k is selected. the bandwidth of the 10k resistor and the 25pf input capaci- tance is calculated. the resistor value must be lowered if the bandwidth is too low for the switching frequency. bw kpf khz = = 1 21025 630 sensing current with a current sense transformer at higher power levels, the power dissipation in a current sense resistor is excessive. a current sense transformer can be used to sense the current while minimizing power dissipation. see figure 11. the schematic shows the circuitry necessary when using a current sense transformer. the resistor, r1, provides a path to reset the current sense transformer. the resistor, r2, converts the scaled down current to a voltage, which is sent to the isns pin. out (pin 16) i sns (pin 14) mic9130 r2 r1 rf i pri v in current sense transformer figure 11 the voltage at the isns pin is calculated by: v i n ri r isns p isns f = + 2 where: i p is the current in the primary of the current sense transformer r2 is the current sense resistance at the secondary of the current sense transformer n is the turns ratio of the current sense transformer (n=nsec/npri) i isns is the current sourced from the isns pin (40 a) r f is the series resistor between the isns pin and the current sense resistor. current transformer example: the maximum peak current, i pmax = 5a at 120% overcur- rent and minimum input voltage the maximum rms current, i rms = 3.25a the full 0.82v peak signal a the isns input can be used since very little power is dissipation in the secondary side sense resistor. the maximum peak to peak volt- age at the sense pin (pin 14) is 0.82v at the 5a maximum output current. the current sense resistor value and power dissipation is: r vn i sense p 2 0 82 100 5 16 4 = = = . . p i n rmw diss prms = ? ? ? ? ? ? = ? ? ? ? ? ? = 2 2 2 325 100 16 4 17 4 . ..
mic9130 micrel, inc. m9999- 111108 16 november 2008 a 16.2 ohm, 1%, non inductive resistor with at least a 50mw rating should be selected. a good choice would be an 0805 size metal lm or a 1/8 watt leaded metal lm resistor. a series resistor between the current sense transformer and the isns input is not necessary unless it is used for low pass ltering. if the current sense transformer were not used, the sense resistor would dissipate 1.7 watts. r v i sense sense sense === 082 5 0 164 . . pir w diss rms sense = = = 2 2 325 0164 17 ... slope compensation power supplies using peak current mode control techniques require slope compensation when they are operating in continuous mode and have a duty cycle greater than 50%. without slope compensation, the duty cycle of the power sup- ply will alternate wide and narrow pulses commonly referred to as subharmonic oscillations. even though the mic9130 operates below a 50% duty cycle, slope compensation adds the bene ts of improved transient response and greater noise immunity in the current sense loop (especially when the current ramp is shallow). slope compensation can be implemented by adding an optimum 1/2 of the inductor cur- rent downslope, re ected back to the current sense input. in real world applications, 2/3 of the inductor current downslope is used to allow for component tolerances. slope compensation at the isns input may be implemented by using a resistor and capacitor as shown in figure 12. the rectangular waveshape of the gate drive output is integrated by the resistor/capacitor lter, which results in a ramp used for the slope compensation signal. when the gate drive and the current signal at the sense resistor goes low, the capaci- tor is discharged to 0v. gate drive (pin 16) i sns (pin 14) mic9130 r2 r1 c1 r sense figure 12 the procedure outlined below demonstrates how to calculate the component values. compute the inductor current downslope as seen at the cur- rent sense input. for a yback, buck or forward mode topology the inductor downslope is equal to: m di dt vv l o d 2= = + where : v o is the output voltage v d is the forward voltage drop of the recti er diode l is the inductance of the output inductor (or the secondary windin g inductance for the yback topology) m2 is the inductor current downslope for a boost topology, the inductor downslope is: m di dt vvv l out in d 2= = ? + in a transformer isolated topology, the downslope must be re ected back to the primary by the turns ratio of the trans- former. the re ected downslope is: mm ns np reflected 22 = where : ns/np is the turns ratio of the secondary winding to the primary winding. m2 reflected is the inductor curent downslope re ected to the secondary side of the current sense transformer. the re ected downslope is multiplied by the current sense resistor to obtain the downslope at the current sense input pin (isns). im r sns slope reflected s _ = 2 where rs is the value of the current sense resistor. the required downslope of the compensation ramp at the isns input is: mi sns slope 3067 = _ . r1 is know if a value for the resistor between the current sense resistor and the isns pin, has already been selected. if not chose a value of 1k, which will minimize any offset and signal degradation at the isns pin. select a value of c1 to minimize signal degradation from the cutoff frequency of r1/c1. the bandwidth should be at least six times the switching frequency. c fr s 1 1 21 =
november 2008 17 m9999- 111108 mic9130 micrel, inc. error ampli er the error ampli er is part of the voltage control loop of the power supply. the fb pin is the inverting input to the error ampli er. the non-inverting input is internally connected to a 2.5v reference. the output of the error ampli er, comp, is connected to the pwm comparator. the error ampli er provides the reference to limit and control the peak current of the power supply. there is a 1.2v level shift between the output of the error ampli er and the pwm comparator. this allows the output of the error ampli er to operate in a linear region and prevents loading on the comp pin from interfering with proper control of the current signal.
mic9130 micrel, inc. m9999- 111108 18 november 2008 package information 16-lead soic (m) 16-lead qsop (qs)
november 2008 19 m9999- 111108 mic9130 micrel, inc. micrel inc. 2180 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 474-1000 web http://www.micrel.com this information furnished by micrel in this data sheet is believed to be accurate and reliable. however no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and speci cations at any time without noti cation to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signi cant injury to the user. a purchaser's use or sale of micrel products for use in life support appliances, devices or systems is a purchaser's own risk and purchaser a grees to fully indemnify micrel for any damages resulting from such use or sale. ? 2001 micrel incorporated

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