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| rev.2.10 jun 24, 2005 page 1 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) single-chip 16-bit cmos microcomputer rej03b0004-0210 rev.2.10 jun 24, 2005 under development this document is under development and its contents are subject to change specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. 1. overview the m16c/6n group (m16c/6n5) of single-chip microcomputers are built using the high-performance silicon gate cmos process using an m16c/60 series cpu core and are packaged in 100-pin plastic molded qfp and lqfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1 mbyte of address space, they are capable of executing instructions at high speed. being equipped with one can (controller area network) module in m16c/6n group (m16c/6n5), the microcomputer is suited to drive automotive and industrial control systems. the can module complies with the 2.0b specification. in addition, this microcomputer contains a multiplier and dmac which combined with fast instruction processing capability, makes it suitable for control of various oa, communication, and industrial equipment which requires high-speed arithmetic/logic operations. 1.1 applications automotive, industrial control systems and other automobile, other
rev.2.10 jun 24, 2005 page 2 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 1. overview under development this document is under development and its contents are subject to change. item performance normal-ver. t/v-ver. cpu number of basic instructions 91 instructions minimum instruction 41.7ns (f(bclk) = 24mhz, 50.0ns (f(bclk) = 20mhz, execution time 1/1 prescaler, without software wait) 1/1 prescaler, without software wait) operation mode single-chip, memory expansion and microprocessor modes address space 1 mbyte memory capacity see table 1.2 product list peripheral port input/output: 87 pins, input: 1 pin function mu ltifunction timer timer a: 16 bits ? 5 channels timer b: 16 bits ? 6 channels three-phase motor control circuit serial i/o 3 channels clock synchronous, uart, i 2 c-bus (1) , iebus (2) 1 channel clock synchronous a/d converter 10-bit a/d converter: 1 circuit, 26 channels d/a converter 8 bits ? 2 channels dmac 2 channels crc calculation circuit crc-ccitt can module 1 channel with 2.0b specification watchdog timer 15 bits ? 1 channel (with prescaler) interrupt i nternal: 29 sources, e xternal: 9 sources software: 4 sources, priority level: 7 l evels clock generating circuit 4 circuits ?main clock oscillation circuit (*) ?sub clock oscillation circuit (*) ?on-chip oscillator ?pll frequency synthesizer (*) equipped with a built-in feedback resistor oscillation stop detection main clock oscillation stop and re-oscillation detection function function electrical supply voltage vcc = 3.0 to 5.5v (f(bclk) = 24mhz, vcc = 4.2 to 5.5v (f(bclk) = 20mhz, characteristics 1/1 prescaler, without software wait) 1/1 prescaler, without software wait) power mask rom 18ma (f(bclk) = 24mhz, 16ma (f(bclk) = 20mhz, consumption pll operation, no division) pll operation, no division) flash memory 20ma (f(bclk) = 24mhz, 18ma (f(bclk) = 20mhz, pll operation, no division) pll operation, no division) mask rom 3? (f(bclk) = 32khz, wait mode, oscillation capacity low) flash memory 0.8? (stop mode, topr = 25?) flash memory program/erase supply voltage 3.0 ?0.3v or 5.0 ?0.5v 5.0 ?0.5v version program and erase endurance 100 times i/o i/o withstand voltage 5.0v characteristics output current 5ma operating ambient temperature -40 to 85? t version: -40 to 85? v version: -40 to 125? (option) device configuration cmos high performance silicon gate package 100-pin plastic mold qfp, lqfp 1.2 performance outline table 1.1 lists a performance outline of m16c/6n group (m16c/6n5). table 1.1 performance outline of m16c/6n group (m16c/6n5) notes: 1. i 2 c-bus is a registered trademark of koninklijke philips electronics n.v. 2. iebus is a registered trademark of nec electronics corporation. option: all options are on request basis. rev.2.10 jun 24, 2005 page 3 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 1. overview under development this document is under development and its contents are subject to change. 1.3 block diagram figure 1.1 shows a block diagram of m16c/6n group (m16c/6n5). figure 1.1 block diagram notes: 1: rom size depends on microcomputer type. 2: ram size depends on microcomputer type. timer (16 bits) output (timer a): 5 input (timer b): 6 three-phase motor control circuit internal peripheral functions watchdog timer (15 bits) a/d converter (10 bits ? 8 channels expandable up to 26 channels) uart or clock synchronous serial i/o (3 channels) system clock generating circuit xin-xout xcin-xcout pll frequency synthesizer on-chip oscillator port p0 8 port p1 8 port p2 8 8 8 8 port p6 8 8 7 8 8 port p10 port p9 port p8_5 port p8 port p7 port p5 port p4 port p3 crc arithmetic circuit (ccitt) (polynomial: x 16 +x 12 +x 5 +1) clock synchronous serial i/o (8 bits ? 1 channel) can module (1 channel) dmac (2 channels) d/a converter (8 bits ? 2 channels) memory m16c/60 series cpu core r0h r0l r1h r1l r2 r3 a0 a1 fb multiplier intb pc usp isp sb flg rom (1) ram (2) rev.2.10 jun 24, 2005 page 4 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 1. overview under development this document is under development and its contents are subject to change. 1.4 product list table 1.2 lists the m16c/6n group (m16c/6n5) products and figure 1.2 shows the type numbers, memory sizes and packages. table 1.2 product list type no. m30 6n 5 m c t - xxx fp package type: fp : package prqp0100jb-a gp: package plqp0100kb-a rom no. omitted on flash memory version characteristics (no) : normal-ver. t : t-ver. (automotive 85 c version) v : v-ver. (automotive 125 c version) rom capacity: c : 128 kbytes memory type: m: mask rom version f : flash memory version shows the number of can module, pin count, etc. 6n group m16c family figure 1.2 type no., memory size, and package as of jun. 2005 (d): under development type no. rom capacity ram capacity package type remarks m306n5fcfp (d) 128 k + 4 kbytes 5 kbytes prqp0100jb-a flash normal-ver. m306n5fcgp (d) plqp0100kb-a memory m306n5fctfp prqp0100jb-a version t-ver. m306n5fctgp (d) plqp0100kb-a m306n5fcvfp prqp0100jb-a v-ver. m306n5fcvgp (d) plqp0100kb-a m306n5mc-xxxgp (d) 128 kbytes 5 kbytes plqp0100kb-a mask normal-ver. m306n5mct-xxxfp prqp0100jb-a rom t-ver. m306n5mct-xxxgp (d) plqp0100kb-a version m306n5mcv-xxxfp prqp0100jb-a v-ver. m306n5mcv-xxxgp (d) plqp0100kb-a rev.2.10 jun 24, 2005 page 5 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 1. overview under development this document is under development and its contents are subject to change. 1.5 pin configuration figures 1.3 and 1.4 show the pin configuration (top view). pin configuration (top view) p4_4/cs0 p4_5/cs1 p4_6/cs2 p4_7/cs3 p5_0/wrl/wr p5_1/wrh/bhe p5_2/rd p5_3/bclk p5_4/hlda p5_5/hold p5_6/ale p5_7/rdy/clkout p6_0/cts0/rts0 p6_1/clk0 p6_2/rxd0/scl0 p6_3/txd0/sda0 p6_4/cts1/rts1/cts0/clks1 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p9_6/anex1/ctx0 p9_5/anex0/crx0 p9_4/da1/tb4in p9_3/da0/tb3in p9_2/tb2in/sout3 (1) p9_1/tb1in/sin3 p9_0/tb0in/clk3 byte cnvss p8_7/xcin p8_6/xcout reset xout vss xin vcc1 p8_5/nmi p8_4/int2/zp p8_3/int1 p8_2/int0 p8_1/ta4in/u p8_0/ta4out/u p7_7/ta3in p7_6/ta3out p7_5/ta2in/w p7_4/ta2out/w p7_3/cts2/rts2/ta1in/v p7_2/clk2/ta1out/v (1) p7_1/rxd2/scl2/ta0in/tb5in p7_0/txd2/sda2/ta0out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p0_7/an0_7/d7 p0_6/an0_6/d6 p0_5/an0_5/d5 p0_4/an0_4/d4 p0_3/an0_3/d3 p0_2/an0_2/d2 p0_1/an0_1/d1 p0_0/an0_0/d0 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 p10_3/an3 p10_2/an2 p10_1/an1 avss p10_0/an0 vref avcc p9_7/adtrg 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 10 0 p1_0/d8 p1_1/d9 p1_2/d10 p1_3/d11 p1_4/d12 p1_5/d13/int3 p1_6/d14/int4 p1_7/d15/int5 p2_0/an2_0/a0(/d0/-) p2_1/an2_1/a1(/d1/d0) p2_2/an2_2/a2(/d2/d1) p2_3/an2_3/a3(/d3/d2) p2_4/an2_4/a4(/d4/d3) p2_5/an2_5/a5(/d5/d4) p2_6/an2_6/a6(/d6/d5) p2_7/an2_7/a7(/d7/d6) vss p3_0/a8(/-/d7) vcc2 p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 m16c/6n group (m16c/6n5) figure 1.3 pin configuration (top view) (1) package: prqp0100jb-a note: 1. p7_1 and p9_1 are n channel open-drain pins. rev.2.10 jun 24, 2005 page 6 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 1. overview under development this document is under development and its contents are subject to change. pin configuration (top view) figure 1.4 pin configuration (top view) (2) 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p0_0/an0_0/d0 p0_1/an0_1/d1 p0_2/an0_2/d2 p0_3/an0_3/d3 p0_4/an0_4/d4 p0_5/an0_5/d5 p0_6/an0_6/d6 p0_7/an0_7/d7 p1_0/d8 p1_1/d9 p1_2/d10 p1_3/d11 p1_4/d12 vref avss vcc1 xin xout vss reset cnvss p8_7/xcin p8_6/xcout byte p2_0/an2_0/a0(/d0/-) p2_1/an2_1/a1(/d1/d0) p2_2/an2_2/a2(/d2/d1) p2_3/an2_3/a3(/d3/d2) p2_4/an2_4/a4(/d4/d3) p2_5/an2_5/a5(/d5/d4) p2_6/an2_6/a6(/d6/d5) p2_7/an2_7/a7(/d7/d6) p3_0/a8(/-/d7) p3_1/a9 p3_2/a10 p3_3/a11 p3_4/a12 p3_5/a13 p3_6/a14 p3_7/a15 p4_0/a16 p4_1/a17 p4_2/a18 p4_3/a19 p7_4/ta2out/w p7_6/ta3out p5_6/ale p7_7/ta3in p5_5/hold p5_4/hlda p5_3/bclk p5_2/rd vcc2 vss p5_7/rdy/clkout p4_5/cs1 p4_6/cs2 p4_7/cs3 avcc p6_3/txd0/sda0 p6_5/clk1 p6_6/rxd1/scl1 p6_7/txd1/sda1 p6_1/clk0 p6_2/rxd0/scl0 p10_0/an0 p10_1/an1 p10_2/an2 p10_3/an3 p9_3/da0/tb3in p9_4/da1/tb4in p9_5/anex0/crx0 p9_6/anex1/ctx0 (1) p9_1/tb1in/sin3 p9_2/tb2in/sout3 p8_0/ta4out/u p6_0/cts0/rts0 p6_4/cts1/rts1/cts0/clks1 p8_2/int0 p8_3/int1 p8_5/nmi p9_7/adtrg p4_4/cs0 p5_0/wrl/wr p5_1/wrh/bhe p9_0/tb0in/clk3 p8_4/int2/zp p7_2/clk2/ta1out/v p7_1/rxd2/scl2/ta0in/tb5in (1) p7_0/txd2/sda2/ta0out p7_5/ta2in/w p7_3/cts2/rts2/ta1in/v p1_5/d13/int3 p1_6/d14/int4 p1_7/d15/int5 p10_7/an7/ki3 p10_6/an6/ki2 p10_5/an5/ki1 p10_4/an4/ki0 p8_1/ta4in/u m16c/6n group (m16c/6n5) note: 1. p7_1 and p9_1 are n channel open-drain pins. package: plqp0100kb-a rev.2.10 jun 24, 2005 page 7 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 1. overview under development this document is under development and its contents are subject to change. 1.6 pin description tables 1.3 to 1.5 list the pin descriptions. table 1.3 pin description (1) i i i i i i/o i/o o i/o i/o o o o i o i vcc1, vcc2, vss avcc, avss _____________ reset cnvss byte d0 to d7 d8 to d15 a0 to a19 a0/d0 to a7/d7 a1/d0 to a8/d7 _______ _______ cs0 to cs3 _________ ______ wrl/wr _________ ________ wrh/bhe ______ rd ale __________ hold __________ hlda ________ rdy power supply input analog power supply input reset input cnvss external data bus width select input bus control pins apply 4.2 to 5.5v to the vcc1 and vcc2 pins and 0v to the vss pin. the vcc apply condition is that vcc2 = vcc1 (1) . applies the power supply for the a/d converter. connect the avcc pin to vcc1. connect the avss pin to vss. the microcomputer is in a reset state when applying l to the this pin. switches processor mode. connect this pin to vss to when after a reset to start up in single-chip mode. connect this pin to vcc1 to start up in microprocessor mode. switches the data bus in external memory space. the data bus is 16-bit long when the this pin is held l and 8-bit long when the this pin is held h . set it to either one. connect this pin to vss when an single-chip mode. inputs and outputs data (d0 to d7) when these pins are set as the separate bus. inputs and outputs data (d8 to d15) when external 16-bit data bus is set as the separate bus. output address bits (a0 to a19). input and output data (d0 to d7) and output address bits (a0 to a7) by time-sharing when external 8-bit data bus are set as the multiplexed bus. input and output data (d0 to d7) and output address bits (a1 to a8) by time-sharing when external 16-bit data bus are set as the multiplexed bus. _______ _______ _______ _______ output cs0 to cs3 signals. cs0 to cs3 are chip-select signals to specify an external space. ________ _________ ______ ________ _____ ________ _________ output wrl, wrh, (wr, bhe), rd signals. wrl and wrh or ________ ______ bhe and wr can be switched by program. ________ _________ _____ wrl, wrh and rd are selected ________ the wrl signal becomes l by writing data to an even address in an external memory space. _________ the wrh signal becomes l by writing data to an odd address in an external memory space. _____ the rd pin signal becomes l by reading data in an external memory space. ______ ________ _____ wr, bhe and rd are selected ______ the wr signal becomes l by writing data in an external memory space. _____ the rd signal becomes l by reading data in an external memory space. ________ the bhe signal becomes l by accessing an odd address. ______ ________ _____ select wr, bhe and rd for an external 8-bit data bus. ale is a signal to latch the address. __________ while the hold pin is held l , the microcomputer is placed in a hold state. __________ in a hold state, hlda outputs a l signal. ________ while applying a l signal to the rdy pin, the microcomputer is placed in a wait state. signal name pin name i/o type description i: input o: output i/o: input/output note: 1. in this manual, hereafter, vcc refers to vcc1 unless otherwise noted. rev.2.10 jun 24, 2005 page 8 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 1. overview under development this document is under development and its contents are subject to change. table 1.4 pin description (2) i o i o o o i i i i/o i i i o i o i/o i i o o o i/o i/o i i i i/o i o i o xin xout xcin xcout bclk clkout ________ ________ int0 to int5 ________ nmi ______ ______ ki0 to ki3 ta0out to ta4out ta0in to ta4in zp tb0in to tb5in ___ ___ ____ u, u, v, v, w, w __________ __________ cts0 to cts2 __________ __________ rts0 to rts2 clk0 to clk3 rxd0 to rxd2 sin3 txd0 to txd2 sout3 clks1 sda0 to sda2 scl0 to scl2 vref an0 to an7 an0_0 to an0_7 an2_0 to an2_7 _____________ adtrg anex0 anex1 da0, da1 crx0 ctx0 main clock input main clock output sub clock input sub clock output bclk output clock output int interrupt input _______ nmi interrupt input key input interrupt input timer a timer b three-phase motor control output serial i/o i 2 c mode reference voltage input a/d converter d/a converter can module i/o pins for the main clock oscillation circuit. connect a ceramic resonator or crystal oscillator between xin and xout (1) . to use the external clock, input the clock from xin and leave xout open. i/o pins for a sub clock oscillation circuit. connect a crystal oscillator between xcin and xcout (1) . to use the external clock, input the clock from xcin and leave xcout open. outputs the bclk signal. the clock of the same cycle as fc, f8, or f32 is output. ______ input pins for the int interrupt. _______ input pin for the nmi interrupt. input pins for the key input interrupt. these are timer a0 to timer a4 i/o pins. these are timer a0 to timer a4 input pins. input pin for the z-phase. these are timer b0 to timer b5 input pins. these are three-phase motor control output pins. these are send control input pins. these are receive control output pins. these are transfer clock i/o pins. these are serial data input pins. these are serial data input pins. these are serial data output pins. these are serial data output pins. this is output pin for transfer clock output from multiple pins function. these are serial data i/o pins. these are transfer clock i/o pins. (except scl2 for the n-channel open drain output.) applies the reference voltage for the a/d converter and d/a converter. analog input pins for the a/d converter. this is an a/d trigger input pin. this is the extended analog input pin for the a/d converter, and is the output in external op-amp connection mode. this is the extended analog input pin for the a/d converter. these are the output pins for the d/a converter. this is the input pin for the can module. this is the output pin for the can module. signal name pin name i/o type description i: input o: output i/o: input/output note: 1. ask the oscillator maker the oscillation characteristic. rev.2.10 jun 24, 2005 page 9 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 1. overview under development this document is under development and its contents are subject to change. table 1.5 pin description (3) 8-bit i/o ports in cmos, having a direction register to select an input or output. each pin is set as an input port or output port. an input port can be set for a pull-up or for no pull-up in 4-bit unit by program. (except p7_1 and p9_1 for the n-channel open drain output.) _______ input pin for the nmi interrupt. pin states can be read by the p8_5 bit in the p8 register. i/o port input port p0_0 to p0_7 p1_0 to p1_7 p2_0 to p2_7 p3_0 to p3_7 p4_0 to p4_7 p5_0 to p5_7 p6_0 to p6_7 p7_0 to p7_7 p8_0 to p8_4 p8_6, p8_7 p9_0 to p9_7 p10_0 to p10_7 p8_5 i/o i signal name pin name i/o type description i: input o: output i/o: input/output rev.2.10 jun 24, 2005 page 10 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 2. central processing unit (cpu) under development this document is under development and its contents are subject to change. figure 2.1 cpu registers 2.1 data registers (r0, r1, r2, and r3) the r0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. r1 to r3 are the same as r0. the r0 register can be separated between high (r0h) and low (r0l) for use as two 8-bit data registers. r1h and r1l are the same as r0h and r0l. conversely r2 and r0 can be combined for use as a 32-bit data register (r2r0). r3r1 is the same as r2r0. 2.2 address registers (a0 and a1) the a0 register consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. they also are used for transfers and arithmetic/logic operations. a1 is the same as a0. in some instructions, a1 and a0 can be combined for use as a 32-bit address register (a1a0). 2. central processing unit (cpu) figure 2.1 shows the cpu registers. the cpu has 13 registers. of these, r0, r1, r2, r3, a0, a1 and fb comprise a register bank. there are two register banks. sb usp isp b15 b0 static base register user stack pointer interrupt stack pointer b19 b15 intbl intbh the upper 4 bits of intb are intbh and the lower 16 bits of intb are intbl. b0 interrupt table register b19 pc b0 program counter r0h (r0's high bits) r0l (r0's low bits) r1h (r1's high bits) r1l (r1's low bits) r2 r3 b31 b15 b8 b7 b0 r2 r3 a0 a1 fb data registers (1) address registers (1) frame base registers (1) note: 1. these registers comprise a register bank. there are two register banks. b15 b0 carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level reserved area b15 b0 flg flag register ipl u i o b s z d c b7 b8 rev.2.10 jun 24, 2005 page 11 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 2. central processing unit (cpu) under development this document is under development and its contents are subject to change. 2.3 frame base register (fb) fb is configured with 16 bits, and is used for fb relative addressing. 2.4 interrupt table register (intb) intb is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 program counter (pc) pc is configured with 20 bits, indicating the address of an instruction to be executed. 2.6 user stack pointer (usp), interrupt stack pointer (isp) stack pointer (sp) comes in two types: usp and isp, each configured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by the u flag of flg. 2.7 static base register (sb) sb is configured with 16 bits, and is used for sb relative addressing. 2.8 flag register (flg) flg consists of 11 bits, indicating the cpu status. 2.8.1 carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. 2.8.2 debug flag (d flag) this flag is used exclusively for debugging purpose. during normal use, it must be set to 0 . 2.8.3 zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0 . 2.8.4 sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0 . 2.8.5 register bank select flag (b flag) register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1 . 2.8.6 overflow flag (o flag) this flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0 . 2.8.7 interrupt enable flag (i flag) this flag enables a maskable interrupt. maskable interrupts are disabled when the i flag is 0 , and are enabled when the i flag is 1 . the i flag is set to 0 when the interrupt request is accepted. 2.8.8 stack pointer select flag (u flag) isp is selected when the u flag is 0 ; usp is selected when the u flag is 1 . the u flag is set to 0 when a hardware interrupt request is accepted or an int instruction for software interrupt nos. 0 to 31 is executed. 2.8.9 processor interrupt priority level (ipl) ipl is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than ipl, the interrupt request is enabled. 2.8.10 reserved area when white to this bit, write 0 . when read, its content is indeterminate. rev.2.10 jun 24, 2005 page 12 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 3. memory under development this document is under development and its contents are subject to change. 3. memory figure 3.1 shows a memory map of the m16c/6n group (m16c/6n5). the address space extends the 1 mbyte from address 00000h to fffffh. the internal rom is allocated in a lower address direction beginning with address fffffh. for example, a 128-kbyte internal rom is allocated to the addresses from e0000h to fffffh. as for the flash memory version, 4-kbyte space (block a) exists in 0f000h to 0ffffh. 4-kbyte space is mainly for storing data. in addition to storing data, 4-kbyte space also can store programs. the fixed interrupt vector table is allocated to the addresses from fffdch to fffffh. therefore, store the start address of each interrupt routine here. the internal ram is allocated in an upper address direction beginning with address 00400h. for example, a 5-kbyte internal ram is allocated to the addresses from 00400h to 017ffh. in addition to storing data, the internal ram also stores the stack used when calling subroutines and when interrupts are generated. the sfr is allocated to the addresses from 00000h to 003ffh. peripheral function control registers are located here. of the sfr, any area which has no functions allocated is reserved for future use and cannot be used by users. the special page vector table is allocated to the addresses from ffe00h to fffdbh. this vector is used by the jmps or jsrs instruction. for details, refer to m16c/60 and m16c/20 series software manual . in memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users. figure 3.1 memory map 00000h yyyyy h fffffh 00400h 0ffffh 10000h 0f000h 27000h 28000h 80000h xxxxx h internal rom (data area) (3) internal rom (program area) (4) sfr internal ram reserved area external area reserved area (2) external area ffe00h fffdch fffffh notes: 1. during memory expansion mode or microprocessor mode, cannot be used. 2. in memory expansion mode, cannot be used. 3. as for the flash memory version, 4-kbyte space (block a) exists. 4. when using the masked rom version, write nothing to internal rom area. 5. shown here is a memory map for the case where the pm10 bit in the pm1 register is "1" (block a enable) . m16c/6n group (m16c/6n5) has no device model expanded over 192 kbytes of the internal rom. accordingly, set the pm13 bit to "0". undefined instruction overflow brk instruction address match single step oscillation stop and re-oscillation detection / watchdog timer reset special page vector table dbc nmi address xxxxx h capacity internal ram 5 kbytes 017ff h address yyyyy h capacity internal rom (3) 128 kbytes e0000 h reserved area (1) rev.2.10 jun 24, 2005 page 13 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. 4. special function register (sfr) sfr (special function register) is the control register of peripheral functions. tables 4.1 to 4.12 list the sfr information. table 4.1 sfr information (1) 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000ah 000bh 000ch 000dh 000eh 000fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001ah 001bh 001ch 001dh 001eh 001fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002ah 002bh 002ch 002dh 002eh 002fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003ah 003bh 003ch 003dh 003eh 003fh processor mode register 0 (1) processor mode register 1 system clock control register 0 system clock control register 1 chip select control register address match interrupt enable register protect register oscillation stop detection register (2) watchdog timer start register watchdog timer control register address match interrupt register 0 address match interrupt register 1 chip select expansion control register pll control register 0 processor mode register 2 dma0 source pointer dma0 destination pointer dma0 transfer counter dma0 control register dma1 source pointer dma1 destination pointer dma1 transfer counter dma1 control register pm0 pm1 cm0 cm1 csr aier prcr cm2 wdts wdc rmad0 rmad1 cse plc0 pm2 sar0 dar0 tcr0 dm0con sar1 dar1 tcr1 dm1con x: undefined notes: 1. the pm00 and pm01 bits in the pm0 register do not change at software reset, watchdog timer reset and oscillation stop detect ion reset. 2. the cm20, cm21, and cm27 bits in the cm2 register do not change at oscillation stop detection reset. 3. the blank areas are reserved and cannot be accessed by users. address register symbol after reset 00000000b (cnvss pin is "l") 00000011b (cnvss pin is "h") 00001000b 01001000b 00100000b 00000001b xxxxxx00b xx000000b 0x000000b xxh 00xxxxxxb 00h 00h x0h 00h 00h x0h 00h 0001x010b xxx00000b xxh xxh xxh xxh xxh xxh xxh xxh 00000x00b xxh xxh xxh xxh xxh xxh xxh xxh 00000x00b rev.2.10 jun 24, 2005 page 14 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. table 4.2 sfr information (2) x: undefined note: 1. the blank area is reserved and cannot be accessed by users. xxxxx000b xxxxx000b xxxxx000b xx00x000b xxxxx000b xxxxx000b xxxxx000b xx00x000b xx00x000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xx00x000b xx00x000b xx00x000b xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh can0 wake-up interrupt control register can0 successful reception interrupt control register can0 successful transmission interrupt control register int3 interrupt control register timer b5 interrupt control register timer b4 interrupt control register uart1 bus collision detection interrupt control register timer b3 interrupt control register uart0 bus collision detection interrupt control register int5 interrupt control register si/o3 interrupt control register int4 interrupt control register uart2 bus collision detection interrupt control register dma0 interrupt control register dma1 interrupt control register can0 error interrupt control register a/d conversion interrupt control register key input interrupt control register uart2 transmit interrupt control register uart2 receive interrupt control register uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int0 interrupt control register int1 interrupt control register int2 interrupt control register can0 message box 0: identifier / dlc can0 message box 0: data field can0 message box 0: time stamp can0 message box 1: identifier / dlc can0 message box 1: data field can0 message box 1: time stamp 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004ah 004bh 004ch 004dh 004eh 004fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005ah 005bh 005ch 005dh 005eh 005fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006ah 006bh 006ch 006dh 006eh 006fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007ah 007bh 007ch 007dh 007eh 007fh c01wkic c0recic c0trmic int3ic tb5ic tb4ic u1bcnic tb3ic u0bcnic int5ic s3ic int4ic u2bcnic dm0ic dm1ic c01erric adic kupic s2tic s2ric s0tic s0ric s1tic s1ric ta0ic ta1ic ta2ic ta3ic ta4ic tb0ic tb1ic tb2ic int0ic int1ic int2ic address register symbol after reset rev.2.10 jun 24, 2005 page 15 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. table 4.3 sfr information (3) x: undefined 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008ah 008bh 008ch 008dh 008eh 008fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009ah 009bh 009ch 009dh 009eh 009fh 00a0h 00a1h 00a2h 00a3h 00a4h 00a5h 00a6h 00a7h 00a8h 00a9h 00aah 00abh 00ach 00adh 00aeh 00afh 00b0h 00b1h 00b2h 00b3h 00b4h 00b5h 00b6h 00b7h 00b8h 00b9h 00bah 00bbh 00bch 00bdh 00beh 00bfh can0 message box 2: identifier / dlc can0 message box 2: data field can0 message box 2: time stamp can0 message box 3: identifier / dlc can0 message box 3: data field can0 message box 3: time stamp can0 message box 4: identifier / dlc can0 message box 4: data field can0 message box 4: time stamp can0 message box 5: identifier / dlc can0 message box 5: data field can0 message box 5: time stamp address register symbol after reset xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh rev.2.10 jun 24, 2005 page 16 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. table 4.4 sfr information (4) x: undefined 00c0h 00c1h 00c2h 00c3h 00c4h 00c5h 00c6h 00c7h 00c8h 00c9h 00cah 00cbh 00cch 00cdh 00ceh 00cfh 00d0h 00d1h 00d2h 00d3h 00d4h 00d5h 00d6h 00d7h 00d8h 00d9h 00dah 00dbh 00dch 00ddh 00deh 00dfh 00e0h 00e1h 00e2h 00e3h 00e4h 00e5h 00e6h 00e7h 00e8h 00e9h 00eah 00ebh 00ech 00edh 00eeh 00efh 00f0h 00f1h 00f2h 00f3h 00f4h 00f5h 00f6h 00f7h 00f8h 00f9h 00fah 00fbh 00fch 00fdh 00feh 00ffh can0 message box 6: identifier / dlc can0 message box 6: data field can0 message box 6: time stamp can0 message box 7: identifier / dlc can0 message box 7: data field can0 message box 7: time stamp can0 message box 8: identifier / dlc can0 message box 8: data field can0 message box 8: time stamp can0 message box 9: identifier / dlc can0 message box 9: data field can0 message box 9: time stamp address register symbol after reset xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh rev.2.10 jun 24, 2005 page 17 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. table 4.5 sfr information (5) x: undefined 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010ah 010bh 010ch 010dh 010eh 010fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011ah 011bh 011ch 011dh 011eh 011fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012ah 012bh 012ch 012dh 012eh 012fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013ah 013bh 013ch 013dh 013eh 013fh can0 message box 10: identifier / dlc can0 message box 10: data field can0 message box 10: time stamp can0 message box 11: identifier / dlc can0 message box 11: data field can0 message box 11: time stamp can0 message box 12: identifier / dlc can0 message box 12: data field can0 message box 12: time stamp can0 message box 13: identifier / dlc can0 message box 13: data field can0 message box 13: time stamp address register symbol after reset xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh rev.2.10 jun 24, 2005 page 18 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. table 4.6 sfr information (6) x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014ah 014bh 014ch 014dh 014eh 014fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015ah 015bh 015ch 015dh 015eh 015fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016ah 016bh 016ch 016dh 016eh 016fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017ah 017bh 017ch 017dh 017eh 017fh can0 message box 14: identifier /dlc can0 message box 14: data field can0 message box 14: time stamp can0 message box 15: identifier /dlc can0 message box 15: data field can0 message box 15: time stamp can0 global mask register can0 local mask a register can0 local mask b register address register symbol after reset xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh c0gmr c0lmar c0lmbr rev.2.10 jun 24, 2005 page 19 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. table 4.7 sfr information (7) x: undefined notes: 1. these registers are included in the flash memory version. cannot be accessed by users in the mask rom version. 2. the blank areas are reserved and cannot be accessed by users. 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018ah 018bh 018ch 018dh 018eh 018fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019ah 019bh 019ch 019dh 019eh 019fh 01a0h 01a1h 01a2h 01a3h 01a4h 01a5h 01a6h 01a7h 01a8h 01a9h 01aah 01abh 01ach 01adh 01aeh 01afh 01b0h 01b1h 01b2h 01b3h 01b4h 01b5h 01b6h 01b7h 01b8h 01b9h 01bah 01bbh 01bch 01bdh 01beh 01bfh flash memory control register 1 (1) flash memory control register 0 (1) address match interrupt register 2 address match interrupt enable register 2 address match interrupt register 3 fmr1 fmr0 rmad2 aier2 rmad3 address register symbol after reset 0x00xx0xb 00000001b 00h 00h x0h xxxxxx00b 00h 00h x0h rev.2.10 jun 24, 2005 page 20 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. table 4.8 sfr information (8) timer b3, b4, b5 count start flag timer a1-1 register timer a2-1 register timer a4-1 register three-phase pwm control register 0 three-phase pwm control register 1 three-phase output buffer register 0 three-phase output buffer register 1 dead time timer timer b2 interrupt occurrence frequency set counter timer b3 register timer b4 register timer b5 register timer b3 mode register timer b4 mode register timer b5 mode register interrupt cause select register 0 interrupt cause select register 1 si/o3 transmit/receive register si/o3 control register si/o3 bit rate generator uart0 special mode register 4 uart0 special mode register 3 uart0 special mode register 2 uart0 special mode register uart1 special mode register 4 uart1 special mode register 3 uart1 special mode register 2 uart1 special mode register uart2 special mode register 4 uart2 special mode register 3 uart2 special mode register 2 uart2 special mode register uart2 transmit/receive mode register uart2 bit rate generator uart2 transmit buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 receive buffer register 01c0h 01c1h 01c2h 01c3h 01c4h 01c5h 01c6h 01c7h 01c8h 01c9h 01cah 01cbh 01cch 01cdh 01ceh 01cfh 01d0h 01d1h 01d2h 01d3h 01d4h 01d5h 01d6h 01d7h 01d8h 01d9h 01dah 01dbh 01dch 01ddh 01deh 01dfh 01e0h 01e1h 01e2h 01e3h 01e4h 01e5h 01e6h 01e7h 01e8h 01e9h 01eah 01ebh 01ech 01edh 01eeh 01efh 01f0h 01f1h 01f2h 01f3h 01f4h 01f5h 01f6h 01f7h 01f8h 01f9h 01fah 01fbh 01fch 01fdh 01feh 01ffh address register symbol after reset tbsr ta11 ta21 ta41 invc0 invc1 idb0 idb1 dtt ictb2 tb3 tb4 tb5 tb3mr tb4mr tb5mr ifsr0 ifsr1 s3trr s3c s3brg u0smr4 u0smr3 u0smr2 u0smr u1smr4 u1smr3 u1smr2 u1smr u2smr4 u2smr3 u2smr2 u2smr u2mr u2brg u2tb u2c0 u2c1 u2rb 000xxxxxb xxh xxh xxh xxh xxh xxh 00h 00h 00h 00h xxh xxh xxh xxh xxh xxh xxh xxh 00xx0000b 00xx0000b 00xx0000b 00xxx000b 00h xxh 01000000b xxh 00h 000x0x0xb x0000000b x0000000b 00h 000x0x0xb x0000000b x0000000b 00h 000x0x0xb x0000000b x0000000b 00h xxh xxh xxh 00001000b 00000010b xxh xxh x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. rev.2.10 jun 24, 2005 page 21 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020ah 020bh 020ch 020dh 020eh 020fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021ah 021bh 021ch 021dh 021eh 021fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022ah 022bh 022ch 022dh 022eh 022fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023ah 023bh 023ch 023dh 023eh 023fh can0 message control register 0 can0 message control register 1 can0 message control register 2 can0 message control register 3 can0 message control register 4 can0 message control register 5 can0 message control register 6 can0 message control register 7 can0 message control register 8 can0 message control register 9 can0 message control register 10 can0 message control register 11 can0 message control register 12 can0 message control register 13 can0 message control register 14 can0 message control register 15 can0 control register can0 status register can0 slot status register can0 interrupt control register can0 extended id register can0 configuration register can0 receive error count register can0 transmit error count register can0 time stamp register can1 control register c0mctl0 c0mctl1 c0mctl2 c0mctl3 c0mctl4 c0mctl5 c0mctl6 c0mctl7 c0mctl8 c0mctl9 c0mctl10 c0mctl11 c0mctl12 c0mctl13 c0mctl14 c0mctl15 c0ctlr c0str c0sstr c0icr c0idr c0conr c0recr c0tecr c0tsr c1ctlr address register symbol after reset 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h x0000001b xx0x0000b 00h x0000001b 00h 00h 00h 00h 00h 00h xxh xxh 00h 00h 00h 00h x0000001b xx0x0000b x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. table 4.9 sfr information (9) rev.2.10 jun 24, 2005 page 22 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. x: undefined note: 1. the blank areas are reserved and cannot be accessed by users. xxh xxh 00h 00h can0 acceptance filter support register peripheral clock select register can0 clock select register 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024ah 024bh 024ch 024dh 024eh 024fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025ah 025bh 025ch 025dh 025eh 025fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026ah 026bh 026ch 026dh 026eh 026fh 0270h to 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037ah 037bh 037ch 037dh 037eh 037fh c0afs pclkr cclkr address register symbol after reset table 4.10 sfr information (10) rev.2.10 jun 24, 2005 page 23 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. x: undefined notes: 1. the ta2p to ta4p bits in the udf register are set to "0" after reset. however, the contents in these bits are indeterminate when read. 2. the blank areas are reserved and cannot be accessed by users. 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038ah 038bh 038ch 038dh 038eh 038fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039ah 039bh 039ch 039dh 039eh 039fh 03a0h 03a1h 03a2h 03a3h 03a4h 03a5h 03a6h 03a7h 03a8h 03a9h 03aah 03abh 03ach 03adh 03aeh 03afh 03b0h 03b1h 03b2h 03b3h 03b4h 03b5h 03b6h 03b7h 03b8h 03b9h 03bah 03bbh 03bch 03bdh 03beh 03bfh count start flag clock prescaler reset flag one-shot start flag trigger select register up/down flag timer a0 register timer a1 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register timer b2 register timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register timer b2 special mode register uart0 transmit/receive mode register uart0 bit rate generator uart0 transmit buffer register uart0 transmit/receive control register 0 uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 bit rate generator uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 uart1 receive buffer register uart transmit/receive control register 2 dma0 request cause select register dma1 request cause select register crc data register crc input register tabsr cpsrf onsf trgsr udf ta0 ta1 ta2 ta3 ta4 tb0 tb1 tb2 ta0mr ta1mr ta2mr ta3mr ta4mr tb0mr tb1mr tb2mr tb2sc u0mr u0brg u0tb u0c0 u0c1 u0rb u1mr u1brg u1tb u1c0 u1c1 u1rb ucon dm0sl dm1sl crcd crcin address register symbol after reset 00h 0xxxxxxxb 00h 00h 00h xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh 00h 00h 00h 00h 00h 00xx0000b 00xx0000b 00xx0000b xxxxxx00b 00h xxh xxh xxh 00001000b 00xx0010b xxh xxh 00h xxh xxh xxh 00001000b 00xx0010b xxh xxh x0000000b 00h 00h xxh xxh xxh (1) table 4.11 sfr information (11) rev.2.10 jun 24, 2005 page 24 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 4. special function register (sfr) under development this document is under development and its contents are subject to change. x: undefined notes: 1. at hardware reset, the register is as follows: "00000000b" where "l" is input to the cnvss pin "00000010b" where "h" is input to the cnvss pin at software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows: "00000000b" where the pm01 to pm00 bits in the pm0 register are "00b" (single-chip mode) "00000010b" where the pm01 to pm00 bits in the pm0 register are "01b" (memory expansion mode) or "11b" (microprocessor mode) 2. the blank areas are reserved and cannot be accessed by users. 03c0h 03c1h 03c2h 03c3h 03c4h 03c5h 03c6h 03c7h 03c8h 03c9h 03cah 03cbh 03cch 03cdh 03ceh 03cfh 03d0h 03d1h 03d2h 03d3h 03d4h 03d5h 03d6h 03d7h 03d8h 03d9h 03dah 03dbh 03dch 03ddh 03deh 03dfh 03e0h 03e1h 03e2h 03e3h 03e4h 03e5h 03e6h 03e7h 03e8h 03e9h 03eah 03ebh 03ech 03edh 03eeh 03efh 03f0h 03f1h 03f2h 03f3h 03f4h 03f5h 03f6h 03f7h 03f8h 03f9h 03fah 03fbh 03fch 03fdh 03feh 03ffh a/d register 0 a/d register 1 a/d register 2 a/d register 3 a/d register 4 a/d register 5 a/d register 6 a/d register 7 a/d control register 2 a/d control register 0 a/d control register 1 d/a register 0 d/a register 1 d/a control register port p0 register port p1 register port p0 direction register port p1 direction register port p2 register port p3 register port p2 direction register port p3 direction register port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p9 register port p8 direction register port p9 direction register port p10 register port p10 direction register pull-up control register 0 pull-up control register 1 pull-up control register 2 port control register ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 adcon2 adcon0 adcon1 da0 da1 dacon p0 p1 pd0 pd1 p2 p3 pd2 pd3 p4 p5 pd4 pd5 p6 p7 pd6 pd7 p8 p9 pd8 pd9 p10 pd10 pur0 pur1 pur2 pcr address register symbol after reset xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh xxh 00h 00000xxxb 00h 00h 00h 00h xxh xxh 00h 00h xxh xxh 00h 00h xxh xxh 00h 00h xxh xxh 00h 00h xxh xxh 00x00000b 00h xxh 00h 00h 00000000b (1) 00000010b 00h 00h table 4.12 sfr information (12) rev.2.10 jun 24, 2005 page 25 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. 5. electrical characteristics table 5.1 absolute maximum ratings option: all options are on request basis. v cc av cc v i v o p d t opr t stg v v v v v v mw c c unit supply voltage (vcc1 = vcc2) analog supply voltage input voltage output voltage power dissipation operating ambient when the microcomputer is temperature operating flash program erase storage temperature symbol parameter _____________ reset, cnvss, byte, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, vref, xin p7_1, p9_1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7, xout p7_1, p9_1 rated value 0.3 to 6.5 0.3 to 6.5 0.3 to vcc+0.3 0.3 to 6.5 0.3 to vcc+0.3 0.3 to 6.5 700 t version: 40 to 85 v version: 40 to 125 (option) 0 to 60 65 to 150 condition vcc = avcc vcc = avcc topr = 25 c rev.2.10 jun 24, 2005 page 26 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. table 5.2 recommended operating conditions (1) (1) supply voltage (vcc1 = vcc2) analog supply voltage supply voltage analog supply voltage high input voltage low input voltage high peak output current high average output current low peak output current low average output current p3_1 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_7, p9_0, p9_2 to p9_7, _____________ p10_0 to p10_7, xin, reset, cnvss, byte p7_1, p9_1 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 (during single-chip mode) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 (data input during memory expansion and microprocessor modes) p3_1 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, _____________ xin, reset, cnvss, byte p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 (during single-chip mode) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 (data input during memory expansion and microprocessor modes) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 5.0 v cc 0 0 v v v v v v v v v v v ma ma ma ma 4.2 0.8v cc 0.8v cc 0.8v cc 0.5v cc 0 0 0 5.5 v cc 6.5 v cc v cc 0.2v cc 0.2v cc 0.16v cc 10.0 5.0 10.0 5.0 v cc av cc v ss av ss v ih v il i oh(peak) i oh(avg) i ol(peak) i ol(avg) parameter symbol typ. min. standard unit max. notes: 1. referenced to vcc = 4.2 to 5.5v at topr = 40 to 85 c unless otherwise specified. 2. the mean output current is the mean value within 100 ms. 3. the total i ol(peak) for ports p0, p1, p2, p8_6, p8_7, p9 and p10 must be 80ma max. the total i ol(peak) for ports p3, p4, p5, p6, p7 and p8_0 to p8_4 must be 80ma max. the total i oh(peak) for ports p0, p1, and p2 must be 40ma max. the total i oh(peak) for ports p3, p4 and p5 must be 40ma max. the total i oh(peak) for ports p6, p7 and p8_0 to p8_4 must be 40ma max. the total i oh(peak) for ports p8_6, p8_7, p9 and p10 must be 40ma max. rev.2.10 jun 24, 2005 page 27 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. table 5.3 recommended operating conditions (2) (1) main clock input oscillation no wait m ask rom version vcc = 4.2 to 5.5v frequency (2) (3) (4) flash memory version sub clock oscillation frequency on-chip oscillation frequency pll clock oscillation frequency cpu operation clock vcc = 4.2 to 5.5v pll frequency synthesizer stabilization wait time power supply ripple allowable frequency (vcc) power supply ripple allowable amplitude voltage vcc = 5v power supply ripple rising/falling gradient vcc = 5v 32.768 1 mhz khz mhz mhz mhz ms khz v v/ms 0 16 0 16 50 20 20 20 10 0.5 0.3 f(xin) f(xcin) f(ring) f(pll) f(bclk) t su(pll) f (ripple) v p-p(ripple) v cc(| ? v/ ? t|) parameter symbol typ. min. standard unit max. notes: 1. referenced to vcc = 4.2 to 5.5v at topr = 40 to 85 c unless otherwise specified. 2. relationship between main clock oscillation frequency and supply voltage is shown right. 3. execute program/erase of flash memory by vcc = 5.0 0.5 v. 4. when using over 16mhz, use pll clock. pll clock oscillation frequency which can be used is 16mhz or 20mhz. 0.0 16.0 5.5 4.2 vcc [v] (main clock: no division) main clock input oscillation frequency f(xin) operating maximum frequency [mhz] f (ripple) power supply ripple allowable frequency (vcc) v p-p(ripple) power supply ripple allowable amplitude voltage figure 5.1 timing of voltage fluctuation f (ripple) v p-p(ripple) vcc rev.2.10 jun 24, 2005 page 28 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. table 5.4 electrical characteristics (1) (1) v cc -2.0 v cc -0.3 3.0 3.0 0.2 0.2 0.2 30 2.0 2.5 1.6 0 0 50 1.5 15 high output voltage high output voltage high output voltage high output voltage low output voltage low output voltage low output voltage low output voltage hysteresis hysteresis hysteresis high input current low input current pull-up resistance feedback resistance feedback resistance ram retention voltage v oh v oh v oh v ol v ol v ol v t +-v t - v t +-v t - v t +-v t - i ih i il r pullup r fxin r fxcin v ram i oh = 5ma i oh = 200a i oh = 1ma i oh = 0.5ma with no load applied with no load applied i ol = 5ma i ol = 200a i ol = 1ma i ol = 0.5ma with no load applied with no load applied v i = 5v v i = 0v v i = 0v at stop mode v v v v v v v v v v v a a k ? m ? m ? v measuring condition standard min. unit v cc v cc v cc v cc 2.0 0.45 2.0 2.0 1.0 2.5 0.8 5.0 5.0 170 parameter symbol p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7 xout highpower lowpower xcout highpower lowpower p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0 to p9_7, p10_0 to p10_7 xout highpower lowpower xcout highpower lowpower _________ _______ hold, rdy, ta0in to ta4in, tb0in to tb5in, ________ ________ _______ _____________ _________ _________ int0 to int5, nmi, adtrg, cts0 to cts2, scl0 to scl2, sda0 to sda2, clk0 to clk3, _____ _____ ta0out to ta4out, ki0 to ki3, rxd0 to rxd2, sin3 _____________ reset xin p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, ____________ xin, reset, cnvss, byte p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_0 to p9_7, p10_0 to p10_7, ____________ xin, reset, cnvss, byte p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_0, p9_2 to p9_7, p10_0 to p10_7 xin xcin typ. max. notes: 1. referenced to vcc = 4.2 to 5.5v, vss = 0v at topr = 40 to 85 c, f(bclk) = 20mhz unless otherwise specified. rev.2.10 jun 24, 2005 page 29 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. table 5.5 electrical characteristics (2) (1) mask rom f(bclk) = 20mhz, pll operation, no division on-chip oscillation, no division flash memory f(bclk) = 20mhz, pll operation, no division on-chip oscillation, no division flash memory f(bclk) = 10mhz, program vcc = 5v flash memory f(bclk) = 10mhz, erase vcc = 5v mask rom f(bclk) = 32khz, low power dissipation mode, rom (2) flash memory f(bclk) = 32khz, low power dissipation mode, ram (2) f(bclk) = 32khz, low power dissipation mode, flash memory (2) mask rom on-chip oscillation, flash memory wait mode f(bclk) = 32khz, wait mode (3), oscillation capacity high f(bclk) = 32khz, wait mode (3), oscillation capacity low stop mode, topr = 25 c notes: 1. referenced to vcc = 4.2 to 5.5v, vss = 0v at topr = 40 to 85 c, f(bclk) = 20mhz unless otherwise specified. 2. this indicates the memory in which the program to be executed exists. 3. with one timer operated using fc32. 16 1 18 1.8 15 25 25 25 420 50 8.5 3.0 0.8 power supply current (vcc = 4.2 to 5.5v) i cc ma ma ma ma ma ma a a a a a a a measuring condition standard min. unit 28 30 3.0 parameter symbol output pins are open and other pins are vss. typ. max. rev.2.10 jun 24, 2005 page 30 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. table 5.6 a/d conversion characteristics (1) (note 2) 8 1.0 3 20 1.5 bits % s k ? ma resolution absolute accuracy setup time output resistance reference power supply input current t su r o i vref symbol parameter min. standard unit measuring condition 4 max. typ. 10 notes: 1. referenced to vcc = avcc = vref = 4.2 to 5.5v, vss = avss = 0v, 40 to 85 c unless otherwise specified. 2. ad frequency must be 10mhz or less. 3. when sample & hold function is disabled, ad frequency must be 250khz or more in addition to a limit of note 2. when sample & hold function is enabled, ad frequency must be 1mhz or more in addition to a limit of note 2. table 5.7 d/a conversion characteristics (1) notes: 1. referenced to vcc = avcc = vref = 4.2 to 5.5v, vss = avss = 0v, 40 to 85 c unless otherwise specified. 2. this applies when using one d/a converter, with the dai register (i = 0, 1) for the unused d/a converter set to 00h . the resistor ladder of the a/d converter is not included. also, the current i vref always flows even though vref may have been set to be unconnected by the adcon1 register. 10 3 7 2 3 7 2 1 3 3 40 v cc v ref bit lsb lsb lsb lsb lsb lsb lsb lsb lsb k ? s s s v v 10 3.3 2.8 0.3 2.0 0 vref = vcc vref = vcc = 5v vref = avcc = vcc = 5v vref = vcc = 5v vref = avcc = vcc = 5v vref = vcc vref = vcc = 5v, ad = 10mhz vref = vcc = 5v, ad = 10mhz anex0, anex1 input, an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input external operation amp connection mode anex0, anex1 input, an0 to an7 input, an0_0 to an0_7 input, an2_0 to an2_7 input external operation amp connection mode resolution integral 10 bits nonlinearity error 8 bits absolute 10 bits accuracy 8 bits differential nonlinearity error offset error gain error resistor ladder 10-bit conversion time, sample & hold function available 8-bit conversion time, sample & hold function available sampling time reference voltage analog input voltage inl dnl r ladder t conv t samp v ref v ia symbol parameter min. standard unit measuring condition max. typ. rev.2.10 jun 24, 2005 page 31 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. 2 150 150 ms s s time for internal power supply stabilization during powering-on stop release time low power dissipation mode wait mode release time t d(p-r) t d(r-s) t d(w-s) symbol parameter min. standard unit measuring condition max. typ. vcc = 4.2 to 5.5v table 5.8 power supply circuit timing c haracteristics cpu clock vcc t d(p-r) t d(p-r) time for internal power supply stabilization during powering-on t d(r-s) stop release time t d(w-s) low power dissipation mode wait mode release time cpu clock t d(w-s) t d(r-s) (b) (a) interrupt for (a) stop mode release or (b) wait mode release figure 5.2 power supply circuit timing diagram rev.2.10 jun 24, 2005 page 32 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. 15 15 ns ns ns ns ns external clock input cycle time external clock input high pulse width external clock input low pulse width external clock rise time external clock fall time symbol parameter min. standard unit max. 62.5 25 25 t c t w(h) t w(l) t r t f timing requirements (referenced to vcc = 5v, vss = 0v, at topr = ?0 to 85? unless otherwise specified) table 5.9 external clock input (xin input) table 5.10 memory expansion mode and microprocessor mode (note 1) (note 2) (note 3) ns ns ns ns ns ns ns ns ns data input access time (for setting with no wait) data input access time (for setting with wait) data input access time (when accessing multiplexed bus area) data input setup time ________ rdy input setup time __________ hold input setup time data input hold time ________ rdy input hold time __________ hold input hold time symbol parameter min. standard unit max. 40 30 40 0 0 0 t ac1(rd-db) t ac2(rd-db) t ac3(rd-db) t su(db-rd) t su(rdy-bclk) t su(hold-bclk) t h(rd-db) t h(bclk-rdy) t h(bclk-hold) notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 45 [ns] 2. calculated according to the bclk frequency as follows: (n 0.5) ? 10 9 f(bclk) 45 [ns] n is 2 for 1-wait setting, 3 for 2-wait setting and 4 for 3-wait setting. 3. calculated according to the bclk frequency as follows: (n 0.5) ? 10 9 f(bclk) 45 [ns] n is 2 for 2-wait setting, 3 for 3-wait setting. rev.2.10 jun 24, 2005 page 33 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. timing requirements (referenced to vcc = 5v, vss = 0v, at topr = 40 to 85 c unless otherwise specified) table 5.11 timer a input (counter input in event counter mode) ns ns ns taiin input cycle time taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 100 40 40 table 5.12 timer a input (gating input in timer mode) t c(ta) t w(tah) t w(tal) table 5.13 timer a input (external trigger input in one-shot timer mode) table 5.14 timer a input (external trigger input in pulse width modulation mode) table 5.15 timer a input (counter increment/decrement input in event counter mode) ns ns ns taiin input cycle time taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 400 200 200 t c(ta) t w(tah) t w(tal) ns ns ns taiin input cycle time taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 200 100 100 t c(ta) t w(tah) t w(tal) ns ns taiin input high pulse width taiin input low pulse width symbol parameter min. standard unit max. 100 100 t w(tah) t w(tal) ns ns ns ns ns taiout input cycle time taiout input high pulse width taiout input low pulse width taiout input setup time taiout input hold time symbol parameter min. standard unit max. 2000 1000 1000 400 400 t c(up) t w(uph) t w(upl) t su(up-tin) t h(tin-up) table 5.16 timer a input (two-phase pulse input in event counter mode) ns ns ns taiin input cycle time taiout input setup time taiin input setup time symbol parameter min. standard unit max. 800 200 200 t c(ta) t su(tain-taout) t su(taout-tain) rev.2.10 jun 24, 2005 page 34 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. ns ns ns ns ns ns tbiin input cycle time (counted on one edge) tbiin input high pulse width (counted on one edge) tbiin input low pulse width (counted on one edge) tbiin input cycle time (counted on both edges) tbiin input high pulse width (counted on both edges) tbiin input low pulse width (counted on both edges) symbol parameter min. standard unit max. 100 40 40 200 80 80 table 5.18 timer b input (pulse period measurement mode) t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timing requirements (referenced to vcc = 5v, vss = 0v, at topr = 40 to 85 c unless otherwise specified) table 5.17 timer b input (counter input in event counter mode) table 5.19 timer b input (pulse width measurement mode) table 5.20 a/d trigger input table 5.21 serial i/o ns ns ns tbiin input cycle time tbiin input high pulse width tbiin input low pulse width symbol parameter min. standard unit max. 400 200 200 t c(tb) t w(tbh) t w(tbl) ns ns ns tbiin input cycle time tbiin input high pulse width tbiin input low pulse width symbol parameter min. standard unit max. 400 200 200 t c(tb) t w(tbh) t w(tbl) ns ns _____________ adtrg input cycle time (trigger able minimum) _____________ adtrg input low pulse width symbol parameter min. standard unit max. 1000 125 t c(ad) t w(adl) 80 ns ns ns ns ns ns ns clki input cycle time clki input high pulse width clki input low pulse width txdi output delay time txdi hold time rxdi input setup time rxdi input hold time symbol parameter min. standard unit max. 200 100 100 0 70 90 t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) _______ table 5.22 external interrupt inti input ns ns _______ inti input high pulse width _______ inti input low pulse width symbol parameter min. standard unit max. 250 250 t w(inh) t w(inl) rev.2.10 jun 24, 2005 page 35 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. t d(bclk-ad) t h(bclk-ad) t h(rd-ad) t h(wr-ad) t d(bclk-cs) t h(bclk-cs) t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) t h(bclk-rd) t d(bclk-wr) t h(bclk-wr) t d(bclk-db) t h(bclk-db) t d(db-wr) t h(wr-db) t d(bclk-hlda) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns address output delay time address output hold time (refers to bclk) address output hold time (refers to rd) address output hold time (refers to wr) chip select output delay time chip select output hold time (refers to bclk) ale signal output delay time ale signal output hold time rd signal output delay time rd signal output hold time wr signal output delay time wr signal output hold time data output delay time (refers to bclk) data output hold time (refers to bclk) (3) data output delay time (refers to wr) data output hold time (refers to wr) (3) __________ hlda output delay time symbol parameter min. standard unit max. 4 0 (note 1) 4 4 0 0 4 (note 2) (note 1) switching characteristics (referenced to vcc = 5 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.23 memory expansion mode and microprocessor mode (for setting with no wait) 25 25 15 25 25 40 40 notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 10 [ns] 2. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 40 [ns] 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = cr ? ln (1 v ol / v cc ) by a circuit of the right figure. for example, when v ol = 0.2 v cc , c = 30 pf, r =1 k ? , hold time of output l level is t = 30 pf ? 1 k ? ? ln (1 0.2 v cc / v cc ) = 6.7 ns. figure 5.3 port p0 to p10 measurement circuit dbi r c 30pf p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 measuring condition figure 5.3 f(bclk) is 12.5 mhz or less. rev.2.10 jun 24, 2005 page 36 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. t d(bclk-ad) t h(bclk-ad) t h(rd-ad) t h(wr-ad) t d(bclk-cs) t h(bclk-cs) t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) t h(bclk-rd) t d(bclk-wr) t h(bclk-wr) t d(bclk-db) t h(bclk-db) t d(db-wr) t h(wr-db) t d(bclk-hlda) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns address output delay time address output hold time (refers to bclk) address output hold time (refers to rd) address output hold time (refers to wr) chip select output delay time chip select output hold time (refers to bclk) ale signal output delay time ale signal output hold time rd signal output delay time rd signal output hold time wr signal output delay time wr signal output hold time data output delay time (refers to bclk) data output hold time (refers to bclk) (3) data output delay time (refers to wr) data output hold time (refers to wr) (3) __________ hlda output delay time symbol parameter min. standard unit max. 4 0 (note 1) 4 4 0 0 4 (note 2) (note 1) switching characteristics (referenced to vcc = 5 v, vss = 0 v, at topr = 40 to 85 c unless otherwise specified) table 5.24 memory expansion mode and microprocessor mode (for 1- to 3-wait setting and external area access) 25 25 15 25 25 40 40 notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) 10 [ns] 2. calculated according to the bclk frequency as follows: (n 0.5) ? 10 9 n is 1 for 1-wait setting, 2 for 2-wait setting and 3 for 3-wait setting. f(bclk) 40 [ns] when n = 1, f(bclk) is 12.5 mhz or less. 3. this standard value shows the timing when the output is off, and does not show hold time of data bus. hold time of data bus varies with capacitor volume and pull-up (pull-down) resistance value. hold time of data bus is expressed in t = cr ? ln (1 v ol / v cc ) by a circuit of the right figure. for example, when v ol = 0.2 v cc , c = 30 pf, r =1 k ? , hold time of output l level is t = 30 pf ? 1 k ? ? ln (1 0.2 v cc / v cc ) = 6.7 ns.. dbi r c measuring condition figure 5.3 rev.2.10 jun 24, 2005 page 37 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. 4 (note 1) (note 1) 4 (note 1) (note 1) 0 0 4 (note 2) (note 1) ? (note 3) (note 4) 0 0 t d(bclk-ad) t h(bclk-ad) t h(rd-ad) t h(wr-ad) t d(bclk-cs) t h(bclk-cs) t h(rd-cs) t h(wr-cs) t d(bclk-rd) t h(bclk-rd) t d(bclk-wr) t h(bclk-wr) t d(bclk-db) t h(bclk-db) t d(db-wr) t h(wr-db) t d(bclk-hlda) t d(bclk-ale) t h(bclk-ale) t d(ad-ale) t h(ale-ad) t d(ad-rd) t d(ad-wr) t dz(rd-ad) ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns address output delay time address output hold time (refers to bclk) address output hold time (refers to rd) address output hold time (refers to wr) chip select output delay time chip select output hold time (refers to bclk) chip select output hold time (refers to rd) chip select output hold time (refers to wr) rd signal output delay time rd signal output hold time wr signal output delay time wr signal output hold time data output delay time (refers to bclk) data output hold time (refers to bclk) data output delay time (refers to wr) data output hold time (refers to wr) __________ hlda output delay time ale signal output delay time (refers to bclk) ale signal output hold time (refers to bclk) ale signal output delay time ( refers to address) ale signal output hold time (refers to address) rd signal output delay from the end of address wr signal output delay from the end of address address output floating start time symbol parameter min. standard unit max. switching characteristics (referenced to vcc = 5 v, vss = 0 v, at topr = ?0 to 85 c unless otherwise specified) table 5.25 memory expansion mode and microprocessor mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) 25 25 25 25 40 40 15 8 measuring condition figure 5.3 notes: 1. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) ?10 [ns] 2. calculated according to the bclk frequency as follows: (n ?.5) ? 10 9 f(bclk) ?40 [ns] n is ??for 2-wait setting, ??for 3-wait setting. 3. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) ?25 [ns] 4. calculated according to the bclk frequency as follows: 0.5 ? 10 9 f(bclk) ?15 [ns] rev.2.10 jun 24, 2005 page 38 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.4 timing diagram (1) t su(d c) clki txdi rxdi t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c q) t h(c d) t h(c q) inti input t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) adtrg input tbiin input two-phase pulse input in event counter mode t su(taout tain) t su(taout tain) t su(tain taout) t c(ta) t su(tain taout) taiin input taiout input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) taiin input taiout input during event counter mode taiin input (when count on falling edge is selected) taiin input (when count on rising edge is selected) taiout input (up/down input) t h(tin up) t su(up tin) t r t r t c t w(h) t w(l) xin input rev.2.10 jun 24, 2005 page 39 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.5 timing diagram (2) measuring conditions : vcc = 5 v input timing voltage : determined with v il = 1.0 v, v ih = 4.0 v output timing voltage: determined with v ol = 2.5 v, v oh = 2.5 v bclk hold input hlda output p0, p1, p2, p3, p4, p5_0 to p5_2 (1) note: 1. the above pins are set to high-impedance regardless of the input level of the byte pin, the pm06 bit in the pm0 register and the pm11 bit in the pm1 register. hi z rdy input bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus) t d(bclk hlda) t d(bclk hlda) t h(bclk hold) t su(hold bclk) tsu(rdy bclk) th(bclk rdy) memory expansion mode and microprocessor mode (effective for setting with wait) (common to setting with wait and setting without wait) rev.2.10 jun 24, 2005 page 40 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.6 timing diagram (3) bclk csi t d(bclk-cs) 25ns.max adi 25ns.max ale 25ns.max -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t h(rd-db) 0ns.min 0ns.min t h(rd-ad) bhe tcyc read timing t d(bclk-ad) t d(bclk-ale) t h(bclk-ale) t su(db-rd) t d(bclk-rd) 40ns.min t ac1(rd-db) memory expansion mode and microprocessor mode (for setting with no wait) wr,wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 ? tcyc-40)ns.min t h(wr-db) dbi write timing t d(bclk-wr) hi-z (0.5 ? tcyc-45)ns.max (0.5 ? tcyc-10)ns.min tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v (0.5 ? tcyc-10)ns.min rev.2.10 jun 24, 2005 page 41 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.7 timing diagram (4) bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min hi-z dbi t su(db-rd) 40ns.min t h(rd-db) 0ns.min tcyc bhe read timing wr,wrl, wrh 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t d(bclk-ale) t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) (0.5 ? tcyc-40)ns.min (0.5 ? tcyc-10)ns.min t h(wr-db) dbi write timing t d(bclk-ale) t d(bclk-rd) t d(bclk-wr) 0ns.min t h(rd-ad) t ac2(rd-db) hi-z memory expansion mode and microprocessor mode (for 1-wait setting and external area access) (1.5 ? tcyc-45)ns.max tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v (0.5 ? tcyc-10)ns.min rev.2.10 jun 24, 2005 page 42 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.8 timing diagram (5) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode and microprocessor mode (for 2-wait setting and external area access) bclk csi ale dbi adi bhe rd tcyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 ? tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (1.5 ? tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 ? tcyc-10)ns.min t ac2(rd-db) (2.5 ? tcyc-45)ns.max tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v rev.2.10 jun 24, 2005 page 43 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.9 timing diagram (6) read timing write timing bclk csi ale dbi adi bhe wr, wrl wrh memory expansion mode and microprocessor mode (for 3-wait setting and external area access) bclk csi ale dbi adi bhe rd tcyc t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max hi-z t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(bclk-rd) 0ns.min t h(rd-ad) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc hi-z t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-wr) 25ns.max t h(bclk-cs) 4ns.min t h(bclk-ad) 4ns.min t h(wr-ad) (0.5 ? tcyc-10)ns.min t h(bclk-wr) 0ns.min t d(bclk-db) 40ns.max t d(db-wr) (2.5 ? tcyc-40)ns.min t h(bclk-db) 4ns.min t h(wr-db) (0.5 ? tcyc-10)ns.min t ac2(rd-db) (3.5 ? tcyc-45)ns.max tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v rev.2.10 jun 24, 2005 page 44 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.10 timing diagram (7) memory expansion mode and microprocessor mode (for 1- or 2-wait setting, external area access and multiplexed bus selection) bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale t h(bclk-ale) -4ns.min rd 25ns.max t h(bclk-rd) 0ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(rd-cs) t h(rd-ad) bhe adi /dbi t h(rd-db) 0ns.min t d(ad-ale) read timing t d(bclk-wr) 25ns.max t h(bclk-wr) 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max ale 25ns.max t h(bclk-ale) -4ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min tcyc t h(wr-ad) bhe t d(bclk-db) 40ns.max 4ns.min t h(bclk-db) t d(db-wr) t h(wr-db) adi /dbi data output wr,wrl, wrh write timing address address data input 40ns.min (0.5 ? tcyc-10)ns.min t d(bclk-ale) t d(bclk-rd) t h(wr-cs) address t d(ad-ale) (0.5 ? tcyc-25)ns.min (1.5 ? tcyc-40)ns.min (0.5 ? tcyc-10)ns.min t d(bclk-ale) (0.5 ? tcyc-25)ns.min address 25ns.max t su(db-rd) t ac3(rd-db) (0.5 ? tcyc-10)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t d(ad-wr) 0ns.min t h(ale-ad) tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v (1.5 ? tcyc-45)ns.max (0.5 ? tcyc-10)ns.min (0.5 ? tcyc-10)ns.min (0.5 ? tcyc-15)ns.min rev.2.10 jun 24, 2005 page 45 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) 5. electric characteristics under development this document is under development and its contents are subject to change. figure 5.11 timing diagram (8) read timing write timing memory expansion mode and microprocessor mode (for 3-wait setting, external area access and multiplexed bus selection) bclk csi ale rd adi /dbi adi bhe bclk csi ale adi /dbi tcyc t d(bclk-ad) 25ns.max tcyc data output t h(bclk-cs) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ale) 25ns.max t h(bclk-ale) -4ns.min t d(bclk-rd) 25ns.max t h(bclk-rd) 0ns.min t su(db-rd) 40ns.min t h(rd-db) 0ns.min t h(rd-ad) (0.5 ? tcyc-10)ns.min t h(bclk-ad) 4ns.min t d(bclk-cs) 25ns.max t d(bclk-ad) 25ns.max t h(bclk-db) 4ns.min t h(bclk-wr) 0ns.min t h(wr-ad) (0.5 ? tcyc-10)ns.min t h(bclk-ad) 4ns.min t h(bclk-cs) 4ns.min t d(bclk-ale) 25ns.max t d(bclk-wr) 25ns.max t -4ns.min t h(wr-db) (0.5 ? tcyc-10)ns.min data input address address adi bhe wr, wrl wrh t d(ad-ale) (0.5 ? tcyc-25)ns.min t d(ad-rd) 0ns.min t dz(rd-ad) 8ns.max t ac3(rd-db) t d(bclk-db) 40ns.max (0.5 ? tcyc-10)ns.min t h(wr-cs) t d(ad-wr) 0ns.min t h(rd-cs) (0.5 ? tcyc-10)ns.min t d(ad-ale) (0.5 ? tcyc-25)ns.min (2.5 ? tcyc-45)ns.max (no multiplex) (no multiplex) tcyc = 1 f(bclk) measuring conditions : vcc = 5 v input timing voltage : v il = 0.8 v, v ih = 2.0 v output timing voltage : v ol = 0.4 v, v oh = 2.4 v t d(db-wr) (2.5 ? tcyc-40)ns.min h(bclk-ale) (0.5 ? tcyc-15)ns.min t h(ale-ad) rev.2.10 jun 24, 2005 page 46 of 46 rej03b0004-0210 m16c/6n group (m16c/6n5) appendix 1. package dimensions under development this document is under development and its contents are subject to change. appendix 1. package dimensions terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y0.08 e0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1. 4 e 13.914.014.1 d 13.914.014.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e 0.8 0.5 0.825 0.575 z e z d b p a 1 h e h d y 0.10 e 0.65 c 0 10 l0.40.60.8 0 0.1 0.2 a3.05 16.5 16.8 17.1 22.5 22.8 23.1 a 2 2.8 e 13.814.014.2 d 19.8 20.0 20.2 reference symbol dimension in millimeters min nom max 0.25 0.3 0.4 0.13 0.15 0.2 p-qfp100-14x20-0.65 1.6g mass[typ.] 100p6s-a prqp0100jb-a renesas code jeita package code previous code y index mark 100 81 80 51 50 31 30 1 f * 2 * 1 * 3 z e z d e b p a h d d e h e c detail f a 1 a 2 l include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. revision history m16c/6n group (m16c/6n5) data sheet rev. date description page summary a-1 1.00 jun. 30, 2003 2.00 nov. 10, 2004 first edition issued revised edition issued * words standardizes (on-chip oscillator) * 100p6q-a (100-pin version) is added. * revised parts and revised contents are as follows (except for change of a layout and an expressional change). 1 1. overview 3rd line: "and lqfp" is added. 2 table 1.1 performance outline of m16c/6n group (m16c/6n5) operation mode is added. address space is added. power consumption is revised. "lqfp" is added to package. 4 table 1.2 product list is revised. figure 1.2 type no., memory size, and package: "gp: package 100p6q-a" is added to package type. 5 figure 1.3 pin configuration (top view) (1): "zp" is added. 6 figure 1.4 pin configuration (top view) (2) is added. (100p6q-a) 8 table 1.4 pin description (2): "zp" is added to timer a. 12 3. memory 5th to 6th lines: the description about the flash memory version (block a) is added. figure 3.1 memory map ?interenal rom (data area) is added. notes 3, 4 are added and note 5 is revised. 13 table 4.1 sfr information (1) the value of after reset in pm1 register is revised. the value of after reset in cm2 register is revised. 19 table 4.7 sfr information (7) the value of after reset in fmr0 register is revised. 23 table 4.11 sfr information (11) the value of after reset in u0c1 register is revised. the value of after reset in u1c1 register is revised. note 1 is added. 24 table 4.12 sfr information (12) the value of after reset in da0, da1 registers are revised. 25 table 5.1 absolute maximum ratings "flash program erase" in operating ambient temperature is added. 27 table 5.3 recommended operating conditions (2) parameters of power supply ripple are added. note 4 is revised. figure 5.1 timing of voltage fluctuation is added. 28 table 5.4 electrical characteristics (1): hysteresis "clk4" is revised to "clk3", and "ta2out" is revised to "ta0out". ____________ max. of standard in reset is revised from "2.2" to "2.5". xin is added. revision history m16c/6n group (m16c/6n5) data sheet rev. date description page summary a-2 30 table 5.6 a/d conversion characteristics: "tolerance level impedance" is added. 31 table 5.8 power supply circuit timing characteristics: "t d(m-l) " is deleted. figure 5.2 power supply circuit timing diagram is added. 32 table 5.10 memory expansion mode and microprocessor mode: "t d(bclk-hlda) " is deleted. 34 table 5.21 serial i/o: min. of standard in t su(d-c) is revised from "30" to "70". 35 table 5.23 memory expansion mode and microprocessor mode (for setting with no wait) max. of standard in t d(bclk-ale) is revised from "25" to "15". t d(bclk-hlda) is added. 36 table 5.24 memory expansion mode and microprocessor mode (for 1- to 3-wait setting and external area access) ?max. of standard in t d(bclk-ale) is revised from "25" to "15". ?t d(bclk-hlda) is added. 37 table 5.25 memory expansion mode and microprocessor mode (for 2- to 3-wait setting, external area access and multiplexed bus selection) t d(bclk-hlda) is added. max. of standard in t d(bclk-ale) is revised from "25" to "15". 38 figure 5.4 timing diagram (1): "xin input" is added. 40, 41 figures 5.6 and 5.7 timing diagram (3) (4): "db" in read timing is revised to "dbi". 42, 43 figures 5.8 and 5.9 timing diagram (5) (6): "db" in write timing is revised to "dbi". 45 figure 5.11 timing diagram (8) "adi/db" in read/write timing is revised to "adi/dbi". 46 appendix 1. package dimensions: 100p6q-a is added. revised edition issued * the contents of product are revised. (normal-ver. is added.) * revised parts and revised contents are as follows (except for expressional change). 2 table 1.1 performance outline of m16c/6n group (m16c/6n5) ?performance outline of normal-ver. is added. 4 table 1.2 product list is revised. (normal-ver. is added.) figure 1.2 type no., memory size, and package: "(no): normal-ver." is added to characteristics. 19 figure 4.7 sfr information (7): note 1 is revised. 28 table 5.4 electrical characteristics (1) ?measuring condition of v ol is revised from ? ol = ?00??to ? ol = 200?? 29 table 5.5 electrical characteristics (2): mask rom (5th item) ??(xcin)?is changed to ?f(bclk)). 30 table 5.6 a/d conversion characteristics: ?olerance level impedance?is deleted. 2.00 nov. 10, 2004 2.10 jun. 24, 2005 keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. unit2607 ruijing building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> 2-796-3115, fax: <82> 2-796-2145 renesas technology malaysia sdn. bhd. unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 200 5. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon .3.0 |
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