cd-700 clock and data recovery products performance characteristics output frequency: (ordering option) out 1, 5v option 12.000 65.536 mhz out 1, 3.3v option 12.000 51.840 mhz supply voltage 1 :v dd +5.0 4.5 5.0 5.5 v +3.3 3.0 3.3 3.3 v supply current: i dd 63 ma output logic levels: output logic high v oh 2.5 v output logic low v ol 0.5 v output transition times: rise time 2 t r 5ns fall time 2 t f 5ns input logic levels: input logic high 2 v ih 2.0 v input logic low 2 v ol 0.5 v nominal frequency on loss of signal output 1 75 ppm output 2 75 ppm symmetry or duty cycle 2 out 1 sym1 40 60 % out 2 sym2 45 55 % rclk rclk 40 60 % absolute pull range apr 50, 80, 100 ppm (ordering option) over operating temp, aging, p.s. variations test conditions for apr (+5v option) v c 0.5 4.5 v test conditions for apr (+3.3v option) v c 0.3 3.0 v transfer function positive phase detector gain +5.0v option 0.53 rad/v +3.3v option 0.35 rad/v operating temperature (ordering option) 0/70 or -40/85 o c control voltage leakage current i vcxo + 1ua 1. a 0.01 uf capacitor should be located as close to the supply as possible (to ground) and a 0.1 uf is also recommended. 2. symmetry is defined as (on time/period) with v s = 1.4v for both 5v and 3.3v operation. description: vectron s cd-700 is a user-configurable crystal based pll integrated circuit. it includes a digital phase detector, op-amp, vcxo and additional integrated functions for use in digital synchronization applications features: 5 x 7.5mm, smallest vcxo pll available output frequencies to 65.536 mhz ? 5 or 3.3 vdc operation ? tri-state output ? loss of signal alarm vcxo with cmos outputs 0/70 or -40/85? temperature range ? hermetically sealed ceramic smd package parameter symbol min. typical max unit vectron international 267 lowell road, hudson, nh 03051 tel: 1-88-vectron-1 web: www.vectron.com 100 8798_aa's vectron 05/30/02 3:12 pm page 100
1 9 5 6 8 13 14 16 clafga b freq uency vi yww 2 3 4 7 10 11 12 15 clock and data recovery products cd-700 ordering information outline drawing pad layout pin symbol function 1 opout op-amp output 2 opn op-amp negative input 3 pho phase detector output 4 losin loss of signal input 5 datain phase detector input signal 6 clkin phase detector clock signal 7 gnd cover and electrical ground 8 los loss of signal indicator 9 rclk recovered clock 10 rdata recovered data 11 output 2 divided-down vcxo output, or no output 12 hiz input (this tri-states the outputs) 13 output 1 vcxo output 14 v dd power supply voltage (3.3v 10% or 5.0v 10%) 15 opp op-amp positive input 16 v c vcxo control voltage 12.000 12.288 12.352 16.000 16.384 19.440 24.576 24.704 24.960 25.000 27.000 30.000 30.720 32.768 34.368 35.328 38.880 39.3216 40.000 40.960 44.736 51.840 54.000 60.000 62.208 62.500 65.536 cd t emperature range c = 0 o c to +70 o c f = - 40 o c to +85 o c frequency 12.000 mhz to 65.536 mhz 700 a l f 44.736 product family cd = clock and data package 700 = 16 pin smd input k = 5.0 vdc + 10% l = 3.3 vdc + 10% output a = cmos mhz divide by a =2 f = 64 b =4 g = 128 c = 8 h = 256 d =16 k = disable e =32 absolute pull range g =+ 50 ppm n =+ 80 ppm h = + 100 ppm a g standard frequencies (mhz) pin out information vectron international 267 lowell road, hudson, nh 03051 tel: 1-88-vectron-1 web: www.vectron.com 101 b duty cycle b = 50/50 10% (out 1) consult datasheet on website. cdr 8798_aa's vectron 05/30/02 3:12 pm page 101
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