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| apu3146 200407061-1/28 data and specifications subject to change without notice. technology licensed from international rectifier description the apu3146 ic combines a dual synchronous buck controller, providing a cost-effective, high performance and flexible solution. the apu3146 can configured as 2- independent or as 2-phase controller. the 2-phase con- figuration is ideal for high current applications. the apu3146 features 180 out of phase operation which re- duces the required input/output capacitance and results to few number of capacitor quantity. other key features offered by this device include two independent program- mable soft starts, programmable switching frequency up to 500khz per phase, under voltage lockout function. the current limit is provided by sensing the lower mosfet's on-resistance for optimum cost and perfor- mance. dual synchronous controller with 180 out-of-phase configurable to 2-independent outputs or 2-phase single output current sharing using inductor's dcr current limit using mosfet's r ds(on) hiccup/latched current limit latched over-voltage protection vcc from 4.5v to 16v input programmable switching frequency up to 500khz two independent soft-starts/ shutdowns 0.8v precision reference voltage available power good output external frequency synchronization features dual synchronous pwm controller with current sharing circuitry and auto-restart figure 1 - typical application of apu3146 in 2-phase configuration with inductor current sensing package order information device package APU3146O(/m) 28-pin tssop(/soic wb) applications embedded computer systems telecom systems 2-phase power suppl y point of load power architectures ddr memory applications graphic card 12v pgood q5 l4 q4 c5 u1 1.8v @ 30a r8 c16 l3 c17 r9 r7 c10 r4 c9 r3 c8 c3 c4 c13 c11 pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood v ref ap u3146 q3 q2 c14 sync rt hiccup ss2 / sd pgnd2 ocset2 ocset1 v sen1 v sen2 r2 r1 r6 d1 c12 d2 bat54a c18 r5 c15 r11 r10
2/28 apu3146 electrical specifications unless otherwise specified, these specifications apply over vcc=12v, vch1=vch2=v cl =12v and t a =0 to 70c. typical values refer to t a =25c. low duty cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature. absolute maximum ratings vcc, v cl supply voltage .............................................. -0.5v to 16v vch1 and vch2 supply volt age ................................ -0.5v to 25v pgood................. ................................................... -0.5v to 16v storage temperature range ...................................... -40c to 125c operating junction temperature range ..................... -40c to 125c caution: stresses above those listed in absolute maximum ratings" may cause permanent damage to the device. package information 28-pin tssop (o) 28-pin soic wide body(m) parameter sym test condition min typ max units reference voltage section reference voltage voltage line regulation uvlo section uvlo threshold - vcc uvlo hysteresis - vcc uvlo threshold - vch1 uvlo hysteresis - vch1 uvlo threshold - vch2 uvlo hysteresis - vch2 supply current section vcc dynamic supply current vch1 & vch2 dynamic current v cl dynamic supply current vcc static supply current vch1/vch2 static current v cl static supply current 5 4/28 apu3146 pin descriptions pin# pin symbol pin description 1 2 3 4 5,23 6,22 7,21 8 20 9,19 10,18 11,17 12,16 13,15 14 24 25 pgood vcc v out3 rt v sen2 , v sen1 fb2,fb1 comp2, comp1 ss2 / sd ss1 / sd ocset2,ocset1 vch2, vch1 hdrv2, hdrv1 pgnd2, pgnd1 ldrv2, ldrv1 v cl sync hiccup power good pin. low when any of the outputs fall 10% below the set voltages. supply voltage for the internal blocks of the ic. output of the internal ldo. switching frequency setting resistor. (see figure 10 for selecting resistor values). sense pins for ovp and pgood. for 2-phase operation tie these pins together. inverting inputs to the error amplifiers. in current sharing mode, fb1 is connected to a resistor divider to set the output voltage and fb2 is connected to programming resistor to achieve current sharing. in independent 2-channel mode, these pins work as feedback inputs for each channel. compensation pins for the error amplifiers. these pins provide soft-start for the switching regulator. an internal current source charges external capacitors that are connected from these pins to ground which ramp up the output of the switching regulators, preventing them from overshooting as well as limiting the input current. the converter can be shutdown by pulling these pins below 0.3v. current limit resistor (r lim ) connection pins for output 1 and 2. the other ends of r lim s are connected to the corresponding switching nodes. supply voltage for the high side output drivers. these are connected to voltages that must be typically 6v higher than their bus voltages. a 1 e f high frequency capacitor must be connected from these pins to gnd to provide peak drive current capability. output drivers for the high side power mosfets. 1) these pins serve as the separate grounds for mosfet drivers and should be connected to the system?s ground plane. output drivers for the synchronous power mosfets. supply voltage for the low side output drivers. this pin should be high for normal operation the internal oscillator may be synchronized to an external clock via this pin. when pulled high, it puts the device current limit into a hiccup mode. when pulled low, the output latches off, after an overcurrent event. figure 2 - deadband time definition. t db(typ) =(deadband h_tol+deadband l_to -h)/2 deadband time 90% 10% 90% 10% high side driver hd low side driver ld tr tf deadband h_to_l deadband l_to_h tr tf 2v 2v apu3146 5/28 figure 3 - block diagram of apu3146. pin descriptions pin# pin symbol pin description 26 27 28 v p2 v ref gnd non-inverting input to the second error amplifier. in the current sharing mode, it is con- nected to the programming resistor. in independent 2-channel mode it is connected to v ref pin when fb2 is connected to the resistor divider to set the output voltage. reference voltage. the drive capability of this pin is about 2ua. analog ground for internal reference and control circuitry. connect to pgnd plane with a short trace. block diagram bias generator ldrv2 two phase oscillator 0.8v 3v ramp1 sync gnd hdrv2 vch2 ss1 / sd comp2 error amp2 pwm comp2 por v out3 25ua reset dom ldrv1 v cl hdrv1 vch1 fb1 comp1 error amp1 pwm comp1 reset dom set1 set2 ramp2 64ua max uvlo vch2 3.5v / 3.3v vch1 3.5v / 3.3v 4.2v / 4.0v fb2 pgnd2 vcc rt 0.8v ss2 / sd 20 22 21 6 28 3 12 13 11 15 17 18 v p2 v ref pgood / ovp pgood r s q 4 24 27 26 14 10 1 q s r 0.3v ss2 v sen1 v sen2 ocset2 9 ovp hdrv off / ldrv on 2 8 7 23 5 thermal shutdown pgnd1 16 ocset1 19 25ua 64ua 0.3v ss1 hiccup 25 hiccup control ss1 ss2 mode regulator mode control por mode 0.8v v p2 mode 20ua 20ua por 0.8v 3ua ss2 3ua ss1 1) these pins should not go negative (-0.5v), this may cause instability for the gate drive circuits. to prevent this, a low forward voltage drop diode is required between these pins and ground as shown in figure 1. 6/28 apu3146 functional description information for current sharing. the voltage drops across the current sense resistors (or dcr of inductors) are measured and their difference is amplified by the slave error amplifier and compared with the ramp signal to generate the pwm pulses to match the output current. in this mode the ss2 pin should be floating. introduction the apu3146 is versatile device for high performance buck figure 4 - loss-less inductive current sensing and current sharing. in the diagram, l1 and l2 are the output inductors. r l1 and r l2 are inherent inductor resistances. the resistor r1 and capacitor c1 are used to sense the average in- ductor current. the voltage across the capacitors c1 and c2 represent the average current flowing into resis- tance r l1 and r l2 . the time constant of the rc network should be equal or at most three times larger than the time constant l 1 /r l1 . l1 r l1 r1 l2 r l2 r2 c2 apu3146 comp 0.8v fb1 vp2 fb2 master e/a slave e/a pwm comp2 pwm comp1 c1 v out l1 r l1 r1 c1=(1~3) ---(1) figure 5 - 30a current sharing using inductor sensing (5a/div) converters. it is included of two synchronous buck con- trollers which can be operated both in two independent mode or in 2-phase mode. the timing of the ic is provided through an internal oscil- lator circuit. these are two out-of-phase oscillators that can be programmed up to 400khz per phase. supply voltage vcc is the supply voltage for internal controller. the op- erating range is from 4.5v to 16v. it also is fed to the internal ldo. when vcc is below under-voltage thresh- old, all mosfet drivers will be turned off. internal regulator the regulator powers directly from vcc and generates a regulated voltage (typ. 6.2v@50ma). the output is pro- tected for short circuit. this voltage can be used for charge pump circuitry as describe in figure12. input supplies undervoltage lockout the apu3146 uvlo block monitors three input voltages (vcc, vch1 and vch2) to ensure reliable start up. the mosfet driver output turn off when any of the supply voltages drops below set thresholds. normal operation resumes once the supply voltages rise above the set values. independent mode in this mode the apu3146 provides control to two inde- pendent output power supplies with either common or different input voltages. the output voltage of each indi- vidual channel is set and controlled by the output of the error amplifier, which is the amplified error signal from the sensed output voltage and the reference voltage. the error amplifier output voltage is compared to the ramp signal thus generating fixed frequency pulses of variable duty-cycle, which are applied to the fet drivers, fig- ure18 shows a typical schematic for such application. 2-phase mode this feature allows to connect both outputs together to increase current handling capability of the converter to support a common load. the current sharing can be done either using external resistors or sensing the dcr of inductors (see figure 4). in this mode, one control loop acts as a master and sets the output voltage as a regu- lar voltage mode buck controller and the other control loop acts as a slave and monitors the current apu3146 7/28 dual soft-start the apu3146 has programmable soft-start to control the output voltage rise and limit the inrush current during start-up. it provides a separate soft-start function for each outputs. this will enable to sequence the outputs by controlling the rise time of each output through selection of different value soft-start capacitors. the soft-start pins will be connected together for applications where, both outputs are required to ramp-up at the same time. to ensure correct start-up, the soft-start sequence ini- tiates when the vcc, vch1 and vch2 rise above their threshold (4.2v and 3.5v respectively) and generate the power on reset (por) signal. soft-start function oper- ates by sourcing an internal current to charge an exter- nal capacitor to about 3v. initially, the soft-start function clamps the e/a?s output of the pwm converter. during power up, the converter output starts at zero and thus the voltage at fb is about 0v. a current (64 e a) injects into the fb pin and generates a voltage about 1.6v (64 e a 25k) across the negative input of e/a and (see figure6). the magnitude of this current is inversely proportional to the voltage at soft-start pin. the 25 e a current source starts to charge up the external capacitor. in the mean time, the soft-start voltage ramps up, the current flowing into fb pin starts to decrease linearly and so does the voltage at negative input of e/a. ss1 / sd comp2 error amp2 por 25ua fb1 comp1 error amp1 64ua max fb2 0.8v ss2 / sd 20 22 21 6 v p2 26 8 7 25ua 64ua figure 6 -soft-start circuit for apu3146 when the soft-start capacitor is around 1v, the current flowing into the fb pin is approximately 32 e a. the volt- age at the positive input of the e/a is approximately: the e/a will start to operate and the output voltage starts to increase. as the soft-start capacitor voltage contin- ues to go up, the current flowing into the fb pin will keep decreasing. because the voltage at pin of e/a is regu- lated to reference voltage 0.8v, the voltage at the fb is: v fb = 0.8-(25k injected current) the feedback voltage increases linearly as the injecting current goes down. the injecting current drops to zero when soft-start voltage is around 2v and the output volt- age goes into steady state. figure 7 shows the theoreti- cal operational waveforms during soft-start. 32 e a 25k = 0.8v soft-start voltage voltage at negative input of error amp voltage at fb pin current flowing into fb pin 64ua 0ua 0v 0.8v ? ? ? 8/28 apu3146 l1 r set apu3146 ocset i ocset v out hiccup control q1 q2 figure 9 - diagram of the over current sensing. v ocset = i ocset r set -r ds(on) i l ---(2) v ocset = i ocset r set - r ds(on) i l = 0 the critical inductor current can be calculated by set- ting: i set = i l(critical) = ---(3) r set i ocset r ds(on) the internal current source develops a voltage across r set . when the low side switch is turned on, the induc- tor current flows through the q2 and results a voltage which is given by: the value of r set should be checked in an actual circuit to ensure that the over current protection circuit activates as expected. the apu3146 current limit is designed primarily as disaster preventing, "no blow up" circuit, and is not useful as a precision current regulator. in two independent mode, the output of each channel is protected independently which means if one output is under overload or short circuit condition, the other output will remain functional. the ocp set limit can be programmed to different levels by using the external resistors. this is valid for both hiccup mode and latch up mode. in 2-phase configuration, the ocp's output depends on any one channel, which means as soon as one channel goes to overload or short circuit condition the output will enter either hiccup or latch-up, dependes on status of hiccup pin. for a given start up time, the soft-start capacitor can be calculated by: c ss ? apu3146 can provide two different schemes for over- current protection (ocp). when the pin hiccup is pulled high, the ocp will operate in hiccup mode. in this mode, during overload or short circuit, the outputs enter hiccup mode and stay in that mode until the overload or short circuit is removed. the converter will automatically re- cover. when the hiccup pin is pulled low, the ocp scheme will be changed to the latch up type, in this mode the converter will be turned off during overcurrent or short circuit. the power needs to be recycled for normal operation. each phase has its own independent ocp circuitry. the ocp is performed by sensing current through the r ds(on) of low side mosfet. as shown in figure 9, an external resistor (r set ) is connected between ocset pin and the drain of low side mosfet (q2) which sets the current limit set point. the soft-start is part of over current protection scheme, during the overload or short circuit condition the external soft start capacitors will be charged and discharged in certain slope rate to achieve the hiccup mode function. out-of-phase operation the apu3146 drives its two output stages 180 out-of- phase. in 2-phase configuration, the two inductor ripple currents cancel each other and result in a reduction of the output current ripple and yield a smaller output ca- pacitor for the same ripple voltage requirement. in single input voltage applications, the input ripple cur- rent reduces. this result in much smaller input capacitor's rms current and reduces the input capacitor quantity. ss1 / sd 20 25ua 3ua hiccup if using one soft start capacitor in dual configuration for a precise power up the ocp needs to be set to latch mode. figure 8 - 3ua current source for discharging soft start-capacitor during hiccup mode apu3146 9/28 frequency synchronization the apu3146 is capable of accepting an external digital synchronization signal. synchronization will be enabled by the rising edge at an external clock. per-channel switch- ing frequency is set by external resistor (rt). the free running oscillator frequency is twice the per-channel fre- quency. during synchronization, rt is selected such that the free running frequency is 20% below the sync fre- quency. synchronization capability is provided for both 2- output and 2-phase configurations. when unused, the sync pin will remain floating and is noise immune. thermal shutdown temperature sensing is provided inside apu3146. the trip threshold is typically set to 140 c. when trip threshold is exceeded, thermal shutdown turns off both fets. ther- mal shutdown is not latched and automatic restart is ini- tiated when the sensed temperature drops to normal range. there is a 20 c hysteresis in the shutdown thresh- old. shutdown the outputs can be shutdown independently by pulling the respective soft-start pins below 0.3v. this can be easily done by using an external small signal transis- tor. during shutdown both mosfets will be turned off. during this mode the ldo will stay on. cycling soft- start pins will clear all fault latches and normal opera- tion will resume. low temperature start-up the controller is capable of starting at -40 c ambient temperature. operation frequency selection power good the apu3146 provides a power good signal. the power good signal should be available after both outputs have reached regulation. this pin needs to be externally pulled high. high state indicates that outputs are in regulation. power good will be low if either one of the output voltages is 10% below the set value. there is only one power good for both outputs. over-voltage protection ovp over-voltage is sensed through separate v out sense pins vsen1 and vsen2. a separate ovp circuit is provided for each output. upon over-voltage condition of either one of the outputs, the ovp forces a latched shutdown on both outputs. in this mode, the upper fet drivers turn-off and the lower fet drivers turn-on, thus crowbaring the out- puts. reset is performed by recycling either vcc. error amplifier the apu3146 is a voltage mode controller. the error am- plifiers are of transconductance type. in independent mode, each amplifier closes the loop around its own output volt- age. in current sharing mode, amplifier 1 becomes the master which regulates the common output voltage. am- plifier 2 performs the current sharing function. both am- plifiers are capable of operating with type iii compensa- tion control scheme. figure 10- switching frequency versus external resistor. the optimum operating frequency range for apu3146 is 300khz per phase, theoretically the apu3146 can be operated at higher switching frequency (e.g. 500khz). however the power dissipation for ic, which is function of applied voltage, gate drivers load and switching fre- quency, will result in higher junction temperature of de- vice. it may exceed absolute maximum rating of junc- tion temperature, figure 18 (page 16) shows case tem- perature versus switching frequency with different ca- pacitive loads. this should be considered when using apu3146 for such application. the below equation shows the relationship between ic's maximum power dissipation and junction temperature: where: tj: maximum operating junction temperature (125 10/28 apu3146 application information design example: the following example is a typical application for apu3146, the schematic is figure18 on page17. output voltage programming output voltage is programmed by reference voltage and external voltage divider. the fb1 pin is the inverting input of the error amplifier, which is referenced to the voltage on non-inverting pin of error amplifier. for this applica- tion, this pin (v p ) is connected to reference voltage (v ref ). the output voltage is defined by using the following equa- tion: when an external resistor divider is connected to the output as shown in figure 11. figure 11 - typical application of the apu3146 for programming the output voltage. equation (4) can be rewritten as: will result to: v out(2.5v) = 2.5v v ref = 0.8v r 9 = 2.14k, r 5 = 1k if the high value feedback resistors are used, the input bias current of the fb pin could cause a slight increase in output voltage. the output voltage can be set more accurately by using low value, precision resistors. for a start-up time of 4ms for both output, the soft-start capacitor will be 0.1 e f. connect ceramic capacitors at 0.1 e f from ss1 pin and ss2 pin to gnd. supply vch1 and vch2 to drive the high side switch, it is necessary to supply a gate voltage at least 4v grater than the bus voltage. this is achieved by using a charge pump configuration as shown in figure 12. this method is simple and inex- pensive. the operation of the circuit is as follows: when the lower mosfet is turned on, the capacitor (c1) charges up to v out3 , through the diode (d1). the bus voltage will be added to this voltage when upper mosfet turns on in next cycle, and providing supply voltage (vch1) through diode (d2). vc is approximately: capacitors in the range of 0.1 e f and 1 e f are generally adequate for most applications. the diode must be a fast recovery device to minimize the amount of charge fed back from the charge pump capacitor into v out3 . the diodes need to be able to block the full power rail voltage, which is seen when the high side mosfet is switched on. for low voltage application, schottky di- odes can be used to minimize forward drop across the diodes at start up. figure 12 - charge pump circuit. r 6 = r 5 - 1 v out v p ( ) fb apu3146 v out r 5 r 6 v ref v p vch1 ? ? apu31 46 d1 c1 vch1 hdrv regulator q1 q2 v out3 c2 v bus d2 c3 css ? ---(4) r 6 r 5 v p2 = v ref = 0.8v ( ) v out(1.8v) = 1.8v v ref = 0.8 r 7 = 1.24k, r 8 = 1k soft-start programming the soft-start timing can be programmed by selecting the soft-start capacitance value. the start-up time of the converter can be calculated by using: apu3146 11/28 for higher efficiency, low esr capacitors is recom- mended. choose two poscap from sanyo 16tpb47m (16v, 47 e f, 70m 1 ) with a maximum allowable ripple current of 1.4a for inputs of each channel. inductor selection the inductor is selected based on operating frequency, transient performance and allowable output voltage ripple. low inductor value results to faster response to step load (high i/ t) and smaller size but will cause larger output ripple due to increase of inductor ripple current. as a rule of thumb, select an inductor that produces a ripple current of 10-40% of full load dc. for the buck converter, the inductor value for desired operating ripple current can be determined using the fol- lowing relation: v in - v out = l ; t = d ; d = 1 f s v out v in i t l = (v in - v out ) ---(7) v out v in i f s where: v in = maximum input voltage v out = output voltage ? ? ? ????????????????????? ? ? apu3146 uses four n-channel mosfets. the se- lections criteria to meet power transfer requirements is based on maximum drain-source voltage (v dss ), gate- source drive voltage (v gs ), maximum output current, on- resistance r ds(on) and thermal management. the both control and synchronous mosfets must have a maximum operating voltage (v dss ) that exceeds the maximum input voltage (v in ). input capacitor selection the 180 0 out of phase will reduce the rms value of the ripple current seen by input capacitors. this reduces numbers of input capacitors. the input capacitors must be selected that can handle both the maximum ripple rms at highest ambient temperature as well as the maximum input voltage. the rms value of current ripple for duty cycles under 50% is expressed by: for i (2.5v) = 38%(i o(2.5v) ), then the output inductor will be: l 4 = 1.71 e h for i (1.8v) = 30%(i o(1.8v) ), then the output inductor will be: l 3 = 1.7 e h panasonic provides a range of inductors in different val- ues and low profile for large currents. output capacitor selection the criteria to select the output capacitor is normally based on the value of the effective series resistance (esr). in general, the output capacitor must have low enough esr to meet output ripple and load transient requirements, yet have high enough esr to satisfy sta- bility requirements. the esr of the output capacitor is calculated by the following relationship: i rms = (i 1 2 d 1 (1-d 1 )+i 2 2 d 2 (1-d 2 )-2i 1 i 2 d 1 d 2 ) --- (6) where: i rms is the rms value of the input capacitor current d 1 and d 2 are the duty cycle for each output i 1 and i 2 are the current for each output for this application the i rms =4.8a (esl, equivalent series inductance is neglected) choose etqp6f1r8bfa (1.71 e h, 14a, 3.3m 1 ) both for l 3 and l 4. for 2-phase application, equation (7) can be used for calculating the inductors value. in such case the induc- tor ripple current is usually chosen to be between 10- 40% of maximum phase current. 12/28 apu3146 choose irf7457 both for control and synchronous mosfet. this device provide low on-resistance in a com- pact soic 8-pin package. the mosfet have the following data: the total conduction losses for each output will be: the switching loss is more difficult to calculate, even though the switching transition is well understood. the reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turnoff delays and rise and fall times. the control mosfet contributes to the majority of the switch- ing losses in a synchronous buck converter. the syn- chronous mosfet turns on under zero voltage condi- tions, therefore, the switching losses for synchronous mosfet can be neglected. with a linear approxima- tion, the total switching loss can be expressed as: these values are taken under a certain condition test. for more details please refer to the irf7457 data sheet. by using equation (9), we can calculate the total switch- ing losses. programming the over-current limit the over-current threshold can be set by connecting a resistor (r set ) from drain of low side mosfet to the ocset pin. the resistor can be calculated by using equa- tion (3). the r ds(on) has a positive temperature coefficient and it should be considered for the worse case operation. p con(total, 2.5v) = p con(upper) + p con(lower) p con(total, 2.5v) = 1.0w p sw(total,2.5v) = 0.414w p sw(tot al,1.8v) = 0.414w irf7457 v dss = 20v i d = 15a r ds(on) = 7m 1 where: v ds(off) = drain to source voltage at off time t r = rise time t f = fall time t = switching period i load = load current p sw = i load ---(9) v ds(off) 2 t r + t f t irf7457 t r = 16ns t f = 7ns r ds(on) = 7m 1 1.5 = 10.5m 1 i set ? apu3146 13/28 the esr zero of the output capacitor is expressed as follows: figure 15 - compensation network without local feedback and its asymptotic gain plot. the transfer function (ve / v out ) is given by: the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: |h(s)| is the gain at zero cross frequency. first select the desired zero-crossover frequency (f o1 ): v out vp=v ref r 5 r 6 r 4 c 9 ve e/a f z h(s) db frequency gain(db) fb comp f esr = ---(10a) 1 2 h esr co h(s) = g m ---(11) ( ) r 5 r 6 + r 5 1 + sr 4 c 9 sc 9 f z = ---(13) 1 2 h r 4 c 9 |h(s=j 2 h f o )| = g m r 4 ---(12) r 5 r 6 +r 5 feedback compensation the apu3146 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. to achieve fast transient response and accurate output regulation, a compensa- tion circuit is necessary. the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency and adequate phase margin (greater than 45 ). the output lc filter introduces a double pole, ?40db/ decade gain slope above its corner resonant frequency, and a total phase lag of 180 (see figure 14). the reso- nant frequency of the lc filter is expressed as follows: where: lo is the output inductor for 2-phase application, the effective output inductance should be used co is the total output capacitor figure 14 shows gain and phase of the lc filter. since we already have 180 phase shift just from the output f lc = ---(10) 1 2 h l o c o gain f lc 0db phase 0 f lc -180 frequency frequency -40db/decade figure14 - gain and phase of lc filter the apu3146?s error amplifier is a differential-input transconductance amplifier. the output is available for dc gain control or ac phase compensation. the e/a can be compensated with or without the use of local feedback. when operated without local feedback, the transconductance properties of the e/a become evi- dent and can be used to cancel one of the output filter poles. this will be accomplished with a series rc circuit from comp pin to ground as shown in figure 15. note that this method requires the output capacitor to have enough esr to satisfy stability requirements. in general, the output capacitor?s esr generates a zero typically at 5khz to 50khz which is essential for an acceptable phase margin. f o1 > f esr and f o1 6 (1/5 ~ 1/10) f s 14/28 apu3146 where: v in = maximum input v olt age v osc = oscillator ramp v olt age f o1 = crossover frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter r 5 and r 6 = resistor dividers for output v oltage programming g m = error amplifier transconductance this results to r 4 =2.61k choose r 4 =2.61k t o cancel one of the lc filter poles, place the zero be- fore the lc filter resonant frequency pole: using equations (13) and (15) to calculate c 9 , we get: same calcuation for v 1.8v will result to: r 3 = 2.8k and c 8 = 22nf one more capacitor is sometimes added in parallel with c 9 and r 4 . this introduces one more pole which is mainly used to suppress the switching noise. the additional pole is given by: the pole sets to one half of switching frequency which results in the capacitor c pole: c 9 ? ?????????????????? ?????????????? ? ? ? (1+sr 8 c 10 ) (1+sr 7 c 11 ) [1+sc 10 (r 6 +r 8 )] [ ( )] 1 sr 6 (c 12 +c 11 ) c 12 c 11 c 12 +c 11 v out vp=v ref r 5 r 6 r 8 c 10 c 12 c 11 r 7 ve f z 1 f z 2 f p 2 f p 3 e/a z f z in frequency gain(db) h(s) db fb comp apu3146 15/28 cross over frequency: the stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. the consideration has been taken to satisfy condition (16) regarding transconduc- tance error amplifier. these design rules will give a crossover frequency ap- proximately one-tenth of the switching frequency. the higher the band width, the potentially faster the load tran- sient response. the dc gain will be large enough to pro- vide high dc-regulation accuracy (typically -5db to -12db). the phase margin should be greater than 45 for overall stability. based on the frequency of the zero generated by esr versus crossover frequency, the compensation type can be different. the table below shows the compensation type and location of crossover frequency. where: v in = maximum input voltage v osc = oscillator ramp voltage lo = output inductor co = total output capacitors f o = r 7 c 10 v in v osc 1 2 h lo co ---(17) f p1 = 0 1 2 h c 10 (r 6 + r 8 ) f z2 = ? ? ?? ?? 16/28 apu3146 from (20), r 2 can be express as: set the zero of compensator to be half of f lc(slave) , the compensator capacitor, c 2 , can be calculated as: when using the dcr of inductors as current sense ele- ment, replace r s1 in equation (21) with dcr value of in- ductor. h(fo) = g m r s1 r 2 =1 ---(20) v in - v out 2 h fo l 2 v osc r 2 = 2 h f o2 l 2 v osc v in - v out f lc(slave) = 1 2 h l 2 c out fz = f lc(slave) 2 c 2 = ---(22) 1 2 h r 2 fz layout consideration the layout is very important when designing high fre- quency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. start by placing the power components. make all the connections in the top layer with wide, copper filled ar- eas. the inductor, output capacitor and the mosfet should be as close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching. place input capacitor near to the drain of the high-side mosfet. the layout of driver section should be designed for a low resistance (a wide, short trace) and low inductance (a wide trace with ground return path directly beneath it), this directly affects the driver's performance. to reduce the esr, replace the one input capacitor with two parallel ones. the feedback part of the system should be kept away from the inductor and other noise sources and must be placed close to the ic. in multilayer pcb's, use one layer as power ground plane and have a sepa- rate control circuit ground (analog ground), to which all signals are referenced. the goal is to localize the high current paths to a separate loops that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. select a zero crossover frequency for control loop (f o2 ) 1.25 times larger than zero crossover frequency for volt- age loop (f o1 ): 1 g m r s1 ---(21) f o2 ? apu3146 17/28 12v pgood c1 47uf c2 47uf l1 q5 irf7457 l4 q4 irf7457 c5 1uf u1 1.8v @ 10a c16 4x 330uf, 40m 1 6tpb330m l3 r7 1.24k c10 0.1uf r4 c9 r3 c8 c3 1uf c4 1uf c13 1uf c11 0.1uf pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood v ref apu3146 q3 irf7457 q2 irf7457 c14 2x 47uf 16tpb47m sync rt hiccup ss2 / sd pgnd2 ocset2 ocset1 v sen1 r2 r1 r6 d1 bat54s 1uh 33k 20nf 2.8k 2.61k 18nf c12 1uf 7.8k 7.8k d2 bat54a 1.7uh 1.7uh c15 0.1uf 2.5v @ 10a r9 2.14k r5 1k r8 1k c18 2x 330uf, 40m 1 6tpb330m c17 2x 47uf 16tpb47m r20 1.24k r21 1k v sen1 v sen1 r22 2.24k r23 1k v sen2 v sen2 v sen2 figure 19 - typical application of apu3146. 12v input and two independent outputs. 18/28 apu3146 typical operating characteristics test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=300khz figure 20 - input supply ramps up. ch1: 1.8v, ch2: 2.5v, ch3: input supply figure 21 - input supply ramps up/down. ch1: 1.8v, ch2: 2.5v, ch3: input supply figure 22 - normal condition at no load. ch1: hdrv2, ch2: hdrv1, ch3 and ch4: inductor currents figure 23 - normal condition at 10a load. ch1: hdrv2, ch2: hdrv1, ch3 and ch4: inductor currents ch3:ch4: 5a/div ch3:ch4: 5a/div apu3146 19/28 figure 24 - soft_start. ch1: ss2, ch2: 1.8v, ch3: ss1, ch4: 2.5v figure 25 - soft_start. ch1: vin, ch2: vout3(ldo), ch3: ss2, ch4: ss2 figure 26 - deadband time (1.8v output). ch1: ldrv2, ch2: hdrv2, ch3: switching node figure 27 - deadband time (2.5v output). ch1: ldrv1, ch2: hdrv1, ch3: switching node typical operating characteristics test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=300khz 20/28 apu3146 figure 28 - shut down (pulling down the ss1 pin). ch1: hdrv1, ch2: ldrv1, ch3: ss1 figure 29 - shut down (pulling down the ss2 pin). ch1: hdrv2, ch2: ldrv2, ch3: ss2 figure 30 - high side and low side drivers peak current for 1.8v output ch1: hdrv2, ch2: ldrv2, ch3: high side peak current, ch4: low side peak current figure 31 - high side and low side drivers peak current for 2.5v output ch1: hdrv1, ch2: ldrv1, ch3: high side peak current, ch4: low side peak current ch3:ch4: 1a/div ch3:ch4: 1a/div typical operating characteristics test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=300khz apu3146 21/28 figure 32 - load transient response. ch2: 2.5v, ch4: step load (0-10a) figure 33 - load transient response. ch1: 1.8v, ch3: step load (0-10a) figure 35 - short circuit condition (hiccup mode). ch1: ss1 pin, ch2: ss2 pin, ch3 and ch4 : inductor currents ch3:ch4: 5a/div ch3:ch4: 5a/div ch3:ch4: 10a/div typical operating characteristics test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=300khz figure 34 - power good signal ch1: input supply, ch2: 2.5v output, ch3: 1.8v output, ch4 : power good signal 22/28 apu3146 figure 36 - 2-phase operation with inductor current sensing. 12v to 1.8v @ 30a output typical application 12v pgood c1 47uf c2 47uf l1 q5 irfr3711 l4 q4 irfr3706 c5 1uf u1 1.8v @ 30a r8 1k c16 8x 330uf, 40m 1 6tpb330m l3 c17 3x 47uf r9 r7 1.24k c10 0.1uf r4 c9 r3 c8 c3 1uf c4 1uf c13 1uf c11 0.1uf pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood v ref apu3146 q3 irfr3711 q2 irfr3706 c14 3x 47uf sync rt hiccup ss2 / sd pgnd2 ocset2 ocset1 v sen1 v sen2 r2 r1 r6 d1 bat54s 1uh 33k 22nf c6 120pf 2.2k 8k c7 82pf 12nf c12 1uf 12k 12k d2 bat54a 1uh, 2m 1 dcr c18 1uf r5 1k c15 1uf 1uh, 2m 1 dcr 1k r21 1k v sen r20 1.24k v sen apu3146 23/28 typical application 12v pgood c1 47uf c2 47uf l1 q5 irfr3711 l4 q4 irfr3706 c5 1uf u1 1.8v @ 30a r8 1k c16 8x 330uf, 40m 1 6tpb330m l3 c17 3x 47uf r5 r9 r7 1.24k c10 0.1uf r4 c9 r3 c8 c3 1uf c4 1uf c13 1uf c11 0.1uf pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood v ref apu3146 q3 irfr3711 q2 irfr3706 c14 3x 47uf sync rt hiccup ss2 / sd pgnd2 ocset2 ocset1 v sen1 v sen2 r2 r1 r6 d1 bat54s 1uh 33k 22nf c6 120pf 2.2k 8k c7 82pf 12nf c12 1uf 12k 1uh 2m 1 12k 2m 1 d2 bat54a 1uh r21 1k r20 1.24k v sen v sen figure 37 - 2-phase operation with resistor current sensing. 12v to 1.8v @ 30a output 24/28 apu3146 figure 38 - typical application of apu3146 using 5v and 12v supplies to generate single output voltage. 1.8v @ 30a using inductor sensing. typical application 12v pgood c1 47uf c2 47uf l1 irfr3711 l4 irfr3706 c5 1uf u1 1.8v @ 30a r8 1k c16 8x 330uf, 40m 1 6tpb330m l3 c17 3x 150uf r7 1.24k c10 0.1uf r4 c9 r3 c8 c3 1uf c4 1uf c13 1uf c11 0.1uf pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood v ref apu3146 q3 irfr3711 q2 irfr3706 c14 3x 47uf sync rt hiccup ss2 / sd pgnd2 ocset2 ocset1 v sen1 v sen2 r2 r1 r6 d1 bat54s 1uh 33k 22nf c6 120pf 2.2k 23k c7 27pf 4.7nf c12 1uf 12k r9 1k 12k r5 1k 1uh, 2m 1 dcr l2 1uh c18 150uf 5v c20 1uf c19 0.1uf d2 bat54a d3 bat54s c21 1uf c22 1uf q4 q5 1uh, 2m 1 dcr r21 1k r20 1.24k apu3146 25/28 figure 39 - typical application of apu3146. 1.8v @ 30a output with 5v and 12v input and different input current setting. (5v @ 5a and 12v @ 3a) typical application 12v pgood c1 47uf c2 47uf l1 q5 irfr3711 l4 q4 irfr3706 c5 1uf u1 1.8v @ 30a r8 1k c16 8x 330uf, 40m 1 6tpb330m l3 c17 3x 150uf r5 r9 r7 1.24k c10 0.1uf r4 c9 r3 c8 c3 1uf c4 1uf c13 1uf c11 0.1uf pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood v ref apu3146 q3 irfr3711 q2 irfr3706 c14 3x 47uf sync rt hiccup ss2 / sd pgnd2 ocset2 ocset1 v sen1 v sen2 r2 r1 r6 d1 bat54s 1uh 33k 22nf c6 120pf 2.2k 23k c7 27pf 4.7nf c12 1uf 15k 1uh 3m 1 10k 2m 1 1uh l2 1uh c18 150uf 5v c20 1uf c19 0.1uf d2 bat54a d3 bat54s r21 1k r20 1.24k 26/28 apu3146 typical application figure 40 - single 5v input and two independent outputs. 5v pgood c1 47uf c2 47uf l1 q5 1/2 irf7910 l4 q4 1/2 irf7910 c5 1uf u1 1.8v @ 10a c16 4x 330uf, 40m 1 6tpb330m l3 r7 1.24k c10 0.1uf r4 c9 r3 c8 c3 1uf c4 1uf c13 1uf c11 0.1uf pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood v ref apu3146 q3 irf7460 q2 irf7457 c14 3x 330uf 6tpb330m sync rt hiccup ss2 / sd pgnd2 ocset2 ocset1 v sen1 v sen2 r2 r1 r6 d1 bat54s 1uh 33k 8.2nf c6 47pf 6k 15k c7 27pf 4.7nf c12 1uf 10k 8.5k d2 bat54a 1uh 3.3uh c15 0.1uf 2.5v @ 5a r9 2.14k r5 1k r8 1k c18 2x 330uf, 40m 1 6tpb330m c17 3x 330uf 6tpb330m r22 2.14k r23 1k v sen2 r20 1.24k r21 1k v sen1 apu3146 27/28 typical application figure 41 - typical application of apu3146. 5v input, 12v drive and two independent outputs. 5v pgood c1 47uf c2 47uf l1 q5 irf7460 l4 q4 irf7457 c5 1uf u1 1.8v @ 10a c16 4x 330uf, 40m 1 6tpb330m l3 c17 3x 330uf 6tpb330m r7 1.24k c10 0.1uf r4 c9 r3 c8 c3 1uf c4 1uf c13 1uf pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood v ref apu3146 q3 irf7460 q2 irf7457 c14 3x 330uf 6tpb330m sync rt hiccup ss2 / sd pgnd2 ocset2 ocset1 v sen1 v sen2 r2 r1 r6 1uh 33k 8.2nf c6 47pf 6k 15k c7 27pf 4.7nf 10k 5.1k d2 bat54a 1uh 3.3uh c15 0.1uf 2.5v @ 5a r9 2.14k r5 1k r8 1k c18 2x 330uf, 40m 1 6tpb330m 12v r20 1.24k r21 1k v sen1 r22 2.14k r23 1k v sen2 28/28 apu3146 typical application figure 42 - typical application of apu3146. 5v to 2.5v and 3.3v to 1.8v inputs and two independent outputs. 5v pgood c1 47uf c2 47uf l1 q5 1/2 irf7910 l4 q4 1/2 irf7910 c5 1uf u1 2.5v @ 5a c16 2x 330uf, 40m 1 6tpb330m l3 c17 2x 330uf 6tpb330m r7 2.14k c10 0.1uf r4 c9 r3 c8 c3 1uf c4 1uf c13 1uf c11 0.1uf pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood v ref apu3146 q3 1/2 irf7910 q2 1/2 irf7910 c14 2x 330uf 6tpb330m sync rt hiccup ss2 / sd pgnd2 ocset2 ocset1 v sen1 v sen2 r2 r1 r6 d1 bat54s 1uh 33k 4.7nf c6 27pf 15k 8.2k c7 27pf 5.6nf c12 1uf 8.5k 8.5k d2 bat54a 3.3uh 2.2uh c15 0.1uf 1.8v @ 5a r9 1.24k r5 1k r8 1k c18 2x 330uf, 40m 1 6tpb330m 3.3v r22 1.24k r23 1k v sen2 r20 2.14k r21 1k v sen1 |
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