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3 msps, 12 - bit sar adc ad7482 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2002 C 2009 analog devices, inc. all rights reserved. features fast throughput r ate: 3 msps wide input b andwidth: 40 mhz no pipeline d elays with sar adc excellent dc accuracy p erformance 2 parallel interface m odes low p ower: 90 mw (full power) and 2.5 mw (nap m ode) standby m ode: 2 a m ax imum single 5 v supply o peration internal 2.5 v r eference full - scale overrange mode (using 13th b it) system offset removal via user access offset r egister nominal 0 v to 2.5 v input with shifted r ange c apability 14- bit pin compatible upgrade ad7484 a vailable functional block d iagram 2.5v reference nap mode2 buf t/h av dd agnd c bias dv dd dgnd refsel refout refin vin 12-bit algorithmic sar cs rd mode1 clip d0 stby d1 reset d2 d3 convst d4 d12 d11 d10 d9 d8 d7 d6 control logic and i/o registers d5 ad7482 v drive write busy 02638-001 figure 1. general description the ad7482 is a 12 - bit, high speed, low power, successive approximation adc. the part features a parallel interface with throughput rates up to 3 msps. the part contains a low noise, wide bandwidth track - and - hold that can handle input frequencies in excess of 40 mhz. the conversion process is a proprietary algorithmic successive approximation technique that results in no pipeline delays. the input signal is sampled, and a conversion is initia ted on the falling edge of the convst the part uses advanced design techniques to achieve very low power dissipation at high thr oughput rates. power consumption in the normal mode of operation is 90 mw . there are two power saving modes: a nap m ode , which keeps the reference circuitry alive for a quick power - up while consuming 2.5 mw, and a standby m ode that reduces power consumptio n to a mere 10 w . the ad7482 features an on - board 2.5 v reference but can also accommodate an externally provided 2.5 v reference source. the nominal analog input range is 0 v to 2.5 v, but an offset shift capability allows this nominal range to be offset by 200 mv . th is allows the user considerable flexibility in setting the bottom end reference point of the signal range, a useful feature when using single - supply op amps. the ad7482 also provides an 8% overrange capability via a 13th bit. th erefore , if the analog input range strays outside the nominal by up to 8%, the user can still accurately resolve the signal by using the 13th bit. the ad7482 is powered by a 4.75 v to 5.25 v supply. the part also provides a v drive p in that allows the user to set the voltage levels fo r the digital interface lines. the range for this v drive p in is 2.7 v to 5.25 v. the part is housed in a 48 - lead lqfp package and is specified over a ? 40c to +85c temperature range. signal. the conversion process is controlled via an internally trimmed oscillator. interfacing is via standard parallel signal lines, making the part directly compatible with microcontrollers and dsps . the ad7482 provides excellent ac and dc performance specifica - tions. factory trimming ensures high dc accuracy , resulting in very low inl, offset, and gain errors.
ad7482 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 terminology .................................................................................... 11 circuit description ......................................................................... 12 converter operation .................................................................. 12 analog input ............................................................................... 12 adc transfer function ............................................................. 13 power saving ............................................................................... 13 offset/overrange ........................................................................ 14 parallel interface ......................................................................... 15 board layout and grounding ................................................... 17 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 12/09 rev. a to rev. b changes to table 1 , power requirements section ....................... 4 changes to ordering guide .......................................................... 19 9 /08 rev. 0 to rev. a changes to table 4 ............................................................................ 7 changes to offset/overrange section ......................................... 14 changes to table 5, table 6, table 7 ............................................. 15 changes t o ordering guide .......................................................... 19 8/02 revision 0: initial version
ad7482 rev. b | page 3 of 20 specifications av dd / dv dd = 5 v 5%, agnd = dgnd = 0 v, v ref = e xternal, f sample = 3 msps; all specifications t min to t max and valid for v drive = 2.7 v to 5.25 v, unless otherwise noted. the operatin g temperature range is ?40c to +85c. table 1 . parameter min typ max unit test conditions/comments dynamic performance 1 , 2 signal - to - noise + distortion (sinad) 3 71 db f in = 1 mhz 72 db f in = 1 mhz 71 db f in = 1 mhz, i nternal r eference total harmonic distortion (thd) 3 ? 86 db ? 90 db ? 88 db internal r eference peak harmonic or spurious noise (sfdr) 3 ? 87 db intermodulation disto rtion (imd) 3 second order terms ? 96 db f in1 = 95.053 khz, f in2 = 105.329 khz third order terms ? 94 db aperture delay 10 ns full power bandwidth 40 mhz @ 3 db 3.5 mhz @ 0.1 db dc accuracy resolution 12 bits integral nonlinearity 3 0.5 lsb b grade 0.25 1 lsb a grade differential nonlinearity 3 0.25 0.5 lsb guaranteed n o m issed c odes to 12 b its offset error 3 1.5 lsb 0.036 %fsr gain error 3 1.5 lsb 0.036 %fsr analog input input voltage ? 200 mv +2.7 v dc leakage current 1 a v in from 0 v to 2.7 v 2 a v in = ? 200 mv input capacitance 4 35 pf reference input/output input voltage , v refin +2.5 v 1% for s pecified p erformance input dc leakage current , v refi n 1 a input capacitance , v refin 4 25 pf input current , v refin 220 a external r eference output voltage , v refout +2.5 v error @ 25c , v refout 50 mv error t min to t max , v refout 100 mv output impedanc e, v refout 1 ?
ad7482 rev. b | page 4 of 20 parameter min typ max unit test conditions/comments logic inputs input high voltage, v inh v drive ? 1 v input low voltage, v inl 0.4 v input current, i in 1 a input capacitance, c in 4 10 pf logic outputs output high voltage, v oh 0.7 v drive v output low voltage, v ol 0.4 v floating state leakage current 10 a floating state output capacitance 4 10 pf output coding straight (natural) binary conversion rate conversion time 300 ns track - and - hold acquisition time (t acq ) 70 ns sine w ave i nput 70 ns full -s cale s tep i nput throughput rate 2.5 msps parallel mode 1 3 msps parallel mode 2 power requirements av dd 5 v 5% dv dd 5 v 5% v drive 2.7 5.25 v i dd normal mode (static) 13 ma cs and rd = logic 1 normal mode (operational) 20 ma n ap mode 0.5 ma standby mode 0.5 2 a power dissipation normal mode (operational) 10 0 mw n ap mode 2.5 mw standby mode 5 10 w 1 sinad figures quoted include external analog input circuit noise contribution of approximately 1 db. 2 see the typical performance characteristics section for analog input circuits used. 3 see the terminology section. 4 sample tested @ 25c to ensure compliance. 5 digital input levels at d gnd or v drive .
ad7482 rev. b | page 5 of 20 t iming c haracteristics av dd / dv dd = 5 v 5%, agnd = dgnd = 0 v, v ref = e xternal; all specifications t min to t max and valid for v drive = 2.7 v to 5.25 v, unless otherwise noted. table 2 . parameter 1 symbol min typ max unit data read conversion time t conv 300 ns quiet time b efore conversion start t quiet 100 ns convst t 1 pulse w idth 5 100 ns convst falling edge to t 2 busy falling edge 20 ns cs falling edge to t 3 rd falling edge 0 ns data access time t 4 25 ns convst t 5 falling edge to new data valid 30 ns busy t 6 rising edge to new data valid 5 ns bus relinquish time t 7 10 ns rd rising edge to t 8 cs rising edge 0 ns cs t 14 pulse width 30 ns rd t 15 pulse width 30 ns data write write pulse w idth t 9 5 ns data setup time t 10 2 ns data hold time t 11 6 ns cs t 12 falling edge to write falling edge 5 ns write falling edge to cs t 13 rising edge 0 ns 1 all timing specifications given are with a 25 pf load capacitance. with a load capacitance greater than this value, a digital bu ffer or latch must be used.
ad7482 rev. b | page 6 of 20 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to a gnd ? 0.3 v to +7 v dv dd to d gnd ? 0.3 v to +7 v v drive to d gnd ? 0.3 v to +7 v analog input voltage to a gnd ? 0.3 v to av dd + 0.3 v digital input voltage to d gnd ? 0.3 v to v drive + 0.3 v refin to a gnd ? 0.3 v to av dd + 0.3 v input current to any pin e xcept suppl y pins 10 ma operating temperature rang e commercial ? 40c to +85c storage temperature range ? 65c to +150c junction temperature 150c thermal impedance , ja 50c/w thermal impedance , jc 10c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c esd 1 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of t his specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7482 rev. b | page 7 of 20 pin configuration and function descripti ons 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier d8 d7 d6 d5 v drive dgnd dgnd av dd c bias agnd agnd av dd agnd vin refout refin refsel agnd dv dd d4 d3 d2 ad7482 top view (not to scale) agnd d1 agnd agnd av dd clip mode1 mode2 reset convst d12 d11 d10 d9 av dd agnd agnd stby nap cs rd write busy r1 r2 d0 02638-002 figure 2. pin configuration ta ble 4 . pin function descriptions pin no. mnemonic description 1, 5, 13, 46 av dd positive power supply for analog circuitry . 2 c bias decoupling pin for internal bias voltage. a 1 nf capacitor should be placed between this pin and agnd. 3, 4, 6, 11, 12, 14, 15, 47, 48 agnd power supply ground for analog circuitry . 7 vin analog input. single ended analog input channel. 8 refout reference output. refout connects to the output of the internal 2.5 v reference buffer. a 470 nf capaci tor must be placed between this pin and agnd. 9 refin reference input. a 470 nf capacitor must be placed between this pin and agnd. when using an external voltage reference source, the reference voltage should be applied to this pin. 10 refsel reference decoupling pin. when using the internal reference, a 1 nf capacitor must be connected from this pin to agnd. when using an external reference source, this pin should be connected directly to agnd. 16 stby standby logic input. when this pin is logic high, the device is placed in s tandby m ode. see the p ower s aving section for further details. 17 nap n ap logic input. when this pin is logic high, the device is placed in a very low power mode. see the p ower s aving section for further details. 18 cs chip select logic input. this pin is used in conjunction with rd to access the conversion result. the data bus is brought out of three - state and the current contents of the outp ut register driven onto the data lines following the falling edge of both cs and rd . cs is also used in conjunction with write to perform a write to the offset register. cs can be hard wired permanently low. 19 rd read logic input. used in conjunction with cs to access the conversion result. 20 write write logic input. used in conjunction with cs to write data to the offset register. when the desired offset word has been placed on the data bus, the write line should be pulsed high. it is the falling edge of this pulse that latches the word into the offset register. 21 busy busy logic output. this pin indicates the status of the conversion process. the busy signal goes low after the falling edge of convst and stays low for the duration of the conversion. in parallel mode 1, the busy signal returns high when the co nversion result has been latched into the output register. in parallel mode 2, the busy signal returns high as soon as the conversion has been completed, but the conversion result does not get latched into the output register until the fa lling edge of the next convst pulse. 22, 23 r1, r2 no connect. these pins shoul d be pulled to ground via 100 k ? resistors. 24 to 28, 33 to 39 d0 to d11 data i/o bits. d11 is msb . these are three - state pins that are controlled by cs , rd , and write. the operating voltage level for these pins is determined by the v drive input. 29 dv dd positive power supply for digital circuitry .
ad7482 rev. b | page 8 of 20 pin no. mnemonic description 30, 31 dgnd ground reference for digital circuitry . 32 v drive logic power supply input. the voltage supplied at this pin determine s at what voltage the interface logic of the device operate s. 40 d12 data output bit for overranging. if the overrange feature is not used, this pin should be pulled to dgnd via a 100 k ? resistor. 41 convst convert start logic input. a conversion is initiated on the falling edge of the convst signal. the input track - an d- hold amplifier goes from track mode to hold mode , and the conversion process commences. 42 reset reset logic input. an active low reset pulse must be applied to this pin after power - up to ensure correct operation. a falling edge on this pin resets the internal state machine and terminates a conversion that may be in progress. the contents of the offset register are also cleared on this edge. holding this pin low keeps the part in a reset state. 43 mode2 operating mode logic input. see table 8 for details. 44 mode1 operating mode logic input. see table 8 for details. 45 clip logic input. a logic high on this pin enables output clipping. in this mode, a ny input voltage that is greater than positive full scale or less than negative ful l scale is clipped to all 1s or all 0s, respectively. further details are given in the o ffset /o verrange section.
ad7482 rev. b | page 9 of 20 typical performance characteris tics frequency (khz) 0 0 200 400 600 800 1400 (db) ?20 ?40 ?80 ?100 ?120 ?60 1000 1200 02638-003 f in = 10.7khz snr = 72.97db snr + d = 72.94db thd = ?91.5db figure 3. 64k fft plot with 10 khz input tone frequency (khz) 0 0 200 400 600 800 1400 (db) ?20 ?40 ?80 ?100 ?120 ?60 1000 1200 f in = 1.013mhz snr = 72.58db snr + d = 72.57db thd = ?94.0db 02638-004 figure 4. 64k fft plot with 1 mhz input tone adc (code) 0.5 0 1024 2048 4096 dnl (lsb) 0.4 0.1 ?0.3 ?0.4 ?0.5 ?0.2 3072 0.3 0 0.2 ?0.1 02638-005 figure 5. typical dnl adc (code) 0.5 0 1024 2048 4096 inl (lsb) 0.4 0.1 ?0.3 ?0.4 ?0.5 ?0.2 3072 0.3 0 0.2 ?0.1 02638-006 figure 6. typical inl input frequency (khz) 80 65 10 10000 100 sinad (db) 1000 70 75 02638-007 figure 7. sinad vs. input tone ( ad8021 input circuit) input frequency (khz) ?40 100 1000 thd (db) ?70 ?90 ?100 ?60 10000 ?50 ?80 100? 10? 0 ? 51? 200 ? 02638-008 figure 8. thd vs. input tone for different input resistances
ad7482 rev. b | page 10 of 20 frequency (khz) 0 10 100 psrr (db) ?30 ?50 ?60 ?20 1000 ?10 ?40 ?70 ?80 100mv p-p sine wave on supply pins 02638-009 figure 9. psrr w ithout decoupling temperature (c) 0.0004 ?55 ?25 5 35 95 125 refout (v) ?0.0004 ?0.0008 ?0.0012 ?0.0016 ?0.0020 0 65 02638-010 figure 10 . reference o ut error
ad7482 rev. b | page 11 of 20 terminology integral nonlinearity th e integral nonlinearity is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity th e differential nonlinearity is the difference between the m easured and ideal 1 lsb change between any two adjacent codes in the adc. offset error the offset error is the deviation o f the first code transition (00...000) to (00... 001) from the ideal, that is , agnd + 0.5 lsb. gain error th e gain error is the deviati on of the last code transition ( 111... 110) to (111... 111) from the ideal, that is , v ref ? 1.5 lsb after the offset error is adjusted out. track - and - hold acquisition time track - and - hold acquisition time is the time required for the output of the track - and - hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion (th e point at which the track - and - hold returns to track mode). signal -to - noise + distortion (sinad) ratio th e sinad r atio is the me asured ratio of signal -to - noise + distortion at the output of the adc . the signal is the rms amplitude of the fundamental. noise is the sum of all nonfunda - mental signals up to half the sampling frequency (f s /2), excluding dc . the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical sinad ratio for an ideal n - bit converter with a sine wave input is given by : signal- to - noise + distortion = (6.02 n +1.76) db th erefore , this is 74 db for a 12 - bit converter. total harmonic distortion (thd) the thd is the ratio of the rms sum of the harmon ics to the fundamental. i t is defined as 1 2 6 2 5 2 4 2 3 2 2 log20) db ( v vvvvv thd ++++ = where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise the p eak harmonic or spurious noise is the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental . t he value of this specification is usually determined by the largest harmonic in th e spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities create s distortion products at sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, and so on. intermodulation distortion terms are those for which neither m nor n is equal to zero. for example, the second order terms include (fa + fb) and (fa ? fb), wh ereas the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the ad7482 is tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually dista nced in frequency from the original sine waves, wh ereas the third order terms are usually at a frequency close to the input frequencies. as a result, the second order and third order terms are specified separately . the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs.
ad7482 rev. b | page 12 of 20 circuit description c onverter o peration the ad7482 is a 12 - bit alg orithmic successive approximation adc based around a capacitive dac. it provides the user with track - and - hold, reference, an adc , and versatile interface logic functions on a single chip. the normal analog input signal range that the ad7482 can convert is 0 v to 2.5 v. by using the offset and overrange features on the adc, the ad7482 can convert analog input signals from ? 200 mv to +2.7 v while operating from a single 5 v supply. the part requires a 2.5 v reference, which can be provided from the internal reference or an external reference source. figure 11 shows a simplified schematic of the adc. the control logic, sar, and capacitive dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back to a balanced condition. capacitive dac switches vin v ref sar control logic control inputs output data 12-bit parallel comparator 02638-013 figure 11 . simplified block diagram of the ad7482 conversion is initiated on the ad7482 by pulsing the convst input. on the falling edge of figure 12 convst , the track - and - hold goes from track mode to hold mode and the conversion sequence is started. conversion time for the part is 300 ns. shows the adc during conversio n. when conversion starts, sw2 open s and sw1 move s to position b, causing the comparator to become unbalanced. the adc then runs through its successive - approximation routine and brings the comparator back into a balanced condition. when the comparator is rebalanced, the conversion result is available in the sar register. capacitive dac comparator control logic + ? sw1 sw2 agnd vin a b 02638-014 figure 12 . adc conversion phase at the end of conversion, the track - and - hold returns to track mode and the acquisition time begins. the track - and - hold acquisition time is 40 ns. figure 13 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a. the comparator is held in a balanced condi tion and the sampling capacitor acquires the signal on v in . capacitive dac comparator control logic + ? sw1 sw2 agnd vin a b 02638-015 figure 13 . adc acquisition phase analog input 1 2 3 4 5 6 7 8 ad829 1k? 1k? 100? bias voltage ac signal 150? 220pf ?v s +v s ? + vin 02638-011 figure 14 . analog input circuit used for 10 khz input tone 220? bias voltage 1 2 3 4 5 6 7 8 ad8021 50? ac signal 220? 10pf ?v s +v s ? + vin 10pf 02638-012 figure 15 . analog input circuit used for 1 mhz input tone figure 14 shows the analog input circuit used to obtain the data for the fast fourier transfer ( fft ) plot shown in figure 3 . the circuit uses an ad829 op amp as the input buffer. a bipolar analog signal is applied and biased up with a stable, low noise dc voltage connected to the labeled terminal , as shown in figure 11 . a 220 pf compensation capacitor is connected between pin 5 and the ad829 and the analog ground plane. the ad829 is supplied with +12 v and ? 12 v supplies. the supply pins are decoupled as close to the device as possible with both a 0.1 f and a 10 f capacitor connected to each pin. in each case, 0.1 f capacitor should be the closer of the two caps to the device. more information on the ad829 is available at www.analog.com .
ad7482 rev . b | page 13 of 20 for higher input bandwidth applications, the ad8021 op amp (also available as a dual ad8022 op amp ) is the recommended choice to drive the ad7482. figure 15 shows the analog input circuit used to obtain the data for the fft plot shown in figure 4 . a bipolar analog sign al is applied to the terminal and biased up with a stable, low noise dc voltage connected , as shown in figure 12 . a 10 pf compensation capacitor is connected between pin 5 of the ad8021 and the negative supply. t he ad8021 is supplied with +12 v and ?12 v supplies. the supply pins are decoupled as close to the device as possible, with both a 0.1 f and a 10 f capacitor connec ted to each pin. in each case, the 0.1 f capacitor should be the closer of the two caps to the device. the ad8021 logic reference pin is tied to analog ground and the disable adc t ransfer f unction pin is tied to t he positive supply , as shown in figure 12. detailed information on the ad8021 is available at www.analog.com. the output coding of the ad7482 is straight binary. the designed code transitions occur midway between the successive integer lsb values, that is, 1/2 lsb, 3/2 lsb , and so on . the lsb size is v ref /4096. the nominal transfer characteristic for the ad7482 is sho wn in figure 16 . this transfer characteristic may be shifted as detailed in the o ffset /o verrange section. 000...000 0v adc code analog input 111...111 000...001 000...010 111...110 111...000 011...111 0.5lsb +v ref ? 1.5lsb 1lsb = v ref /4096 02638-016 figure 16 . ad7482 transfer characteristic p ower s aving the ad7482 uses advanced design techniques to achieve very low power dissipation at high throughput rates. in addition, the ad7482 features two power saving modes, nap and s tandby. these modes are selected by bringing either the nap pin or stby p in to a logic high, respec tively. when operating the ad7482 in normal fully powered mode, the current consumption is 18 ma during conversion and the quiescent current is 12 ma. operating at a throughput rate of 1 msps, the conversion time of 300 ns contributes 27 mw to the overall power dissipation. ( 300 ns /1 s ) (5 v 18 ma ) = 27 mw for the remaining 700 ns of the cycle, the ad7482 dissipates 42 mw of power. ( 700 ns /1 s ) (5 v 12 ma ) = 42 mw th erefore , the power dissipated during each cycle is 2 7 mw + 42 mw = 69 mw figure 17 shows the ad7482 conversion sequence operating in normal mode. convst busy 300ns 1s 700ns 02638-017 figure 17 . normal mode power dissipation in nap m ode, almost all the internal circuitry is powered down. in this mode, the power dissipation is reduced to 2.5 mw. whe n using an external reference, there must be a mini mum of 300 ns from exiting nap mode to initiating a conversion . this is necessary to allow the internal circuitry to settle after power - up and for the track - and - hold to properly acquire the analog input s ignal. the internal reference cannot be used in conjunction with the nap mode . if the ad7482 is put into nap mode after each conversion, the average power dissipation is reduced, but the throughput rate is limited by the power - up time. using the ad7482 wit h a through - put rate of 500 ksps while placing the part in nap mode after each conversion result s in average power dissipation as follows: the power - up phase contributes ( 300 ns /2 s ) (5 v 12 ma ) = 9 mw t he conversion phase contributes ( 300 ns /2 s ) (5 v 18 ma) = 13.5 ma while in nap m ode for the rest of the cycle, the ad7482 dissipates only 1.75 mw of power. ( 1400 ns /2 s ) (5 v 0.5 ma) = 1.75 mw th erefore , the power dis sipa ted during each cycle is 9 mw + 13.5 mw + 1.75 mw = 24.25 mw
ad7482 rev. b | page 14 of 20 figure 18 shows the ad7482 conversion sequence when the part is put into nap mo de after each conversion. 600ns nap 300ns 1400ns 2s convst busy 02638-018 figure 18 . nap mode power dissip ation figure 19 and figure 20 show a typical graphical representation of power vs . throughput for the ad7482 when in normal mode and nap mode , respectively. throughput (ksps) 60 0 3000 power (mw) 500 1000 1500 2000 2500 65 70 75 80 85 90 02638-019 figure 19 . normal mode, power vs. throughput throughput (ksps) 0 0 2000 250 power (mw) 750 1250 1500 1750 10 500 1000 20 30 40 50 60 70 80 90 02638-020 figure 20 . nap mode , power vs. throughput in s tandby m ode, all the internal circuitry is powered down and the power consumption of the ad7482 is reduced to 10 w. t h e power - up time necessary before a conv ersion can be initiated is longer because more of the internal circuitry has been powered down. in using the internal reference of the ad7482, the adc must be brought out of s tandby m ode 500 ms before a conversion is initiated. initiating a conversion befo re the required power - up time has elapsed result s in incorrect conversion data. if an external reference source is used and kept powered up while the ad7482 is in s tandby m ode, the power - up time required is reduced to 80 s. o ffset/o verrange the ad7482 pr ovides a 8% overrange capability as well as a programmable offset register. the overrange capability is achieved by the use of a 13th bit (d12) and the clip input. if the clip input is at logic high and the contents of the offset register are 0 , then the ad7482 operates as a normal 12 - bit adc. if the input voltage is greater than the full - scale voltage, the data output from the adc is all 1s. similarly, if the input voltage is lower than the zero -scale voltage, the data output from the adc is all 0s. in th is case, d12 acts as an overr ange indicator. it is set to 1 if the analog input voltage is outside the nominal 0 v to 2.5 v range . the default contents of the offset register are 0. if the offset register contains any value other tha n 0, the contents of th e register are added to the sar result at the end of conversion. this has the effect of shifting the transfer function of the adc as shown in figure 21 and figure 22. note that with the clip input set to logic high, the maximum and minimum codes that the ad7482 can output are 0xfff and 0x000, respectively. further details are given in table 5 and table 6 . figure 21 shows the effect of writing a positive value to the offset register. f or example , if the contents of the offset register contained the value 256, then the value of the analog input voltage for which the adc tra nsition s from reading all 0s to 000...001 (the bottom reference point) is 0.5 lsb ? ( 256 lsb ) = ? 155.944 mv in this example, t he analog input voltage for which the adc read s full - scale (0xfff) is 2.5 v ? 1.5 lsb ? (256 lsb ) = 2.3428 v analog input 0v 1lsb = v ref /4096 0.5lsb ?offset 000...000 adc code 111...111 000...001 000...010 111...110 111...000 011...111 +v ref ? 1.5lsb ?offset 02638-021 figure 21 . transfer characteristic with positive offset the effect of writing a negative value to the offset register is shown in figure 22 . if a value of ? 128 is written to the offset register, the bottom end reference point occur s at 0.5 lsb ? (? 128 lsb ) = 78.43 mv following this, the analog input voltage needed to produce a full - scale (0xfff) result from the adc is 2.5 v ? 1.5 lsb ? (? 128 lsb ) = 2.5772 v
ad7482 rev . b | page 15 of 20 000...000 0v adc code analog input 111...111 000...001 000...010 111...110 111...000 011...111 0.5lsb ?offset +v ref ? 1.5lsb ?offset 1lsb = v ref /4096 02638-022 figure 22 . transfer characteristic with negative offset table 5 shows the expected adc result for a given analog input voltage with different offset values and with clip tied to logic high. the combined advantages of the offset and overrange features of the ad7482 are shown in table 6 . table 6 shows the same range of analog input and offset values as table 5 but with the clipping feature disabled. table 5 . clipping enabled (clip = 1) offset v in 128 0 +256 d12 adc data, d0:11 ? 200 mv 0 0 0 1 1 1 ? 156.25 mv 0 0 0 1 1 0 0 v 0 0 256 1 0 0 +78.125 mv 0 128 384 0 0 0 +2.34 31 v 371 1 3839 4095 0 0 0 +2.5 v 3 967 4095 4095 0 0 1 +2.577 5 v 4095 4095 4095 0 1 1 +2.7 v 4095 4095 4095 1 1 1 table 6 . clipping disabled (clip = 0) offset v in 128 0 +256 adc data, d0:12 ? 200 mv ? 456 ? 328 ? 72 ? 156.25 mv ? 384 ? 256 0 0 v ? 128 0 256 +78.125 mv 0 128 384 +2.34 31 v 371 1 383 9 409 5 +2.5 v 396 7 409 5 435 1 +2.577 5 v 4095 4223 4479 +2.7 v 4 296 4 424 4 680 if the clip input is at logic low, the overrange indicator is disabled and the ad7482 is able to achieve output codes ou tside the nominal 12 - bi t range of 0 to 4095 ( s ee figure 6 ). d12 acts as an indicator that the adc is outside this nominal range. if the adc is outside this nominal range on the negative side, the adc output s a twos complement code and if the adc is outside the range on the po sitive side, the adc output s a straight binary code as normal. if d12 is l ogic 1, d11 indicates if the adc is out of range on the positive or negative side. if d11 is l ogic 1, the adc is outside the nominal range on the negative side and the output code is a 13- bit twos complement number (a negative number) . if d11 is l ogic 0, the adc is outside the nominal range on the positive s ide and the output code is a 13 - bit straight binary code, see table 7 . table 7 . db14, db13 d ecoding, clip = 0 db12 db11 output coding 0 0 straight b inary C inside nominal range 0 1 straight b inary C inside nominal range 1 0 straight b inary C outside nominal range 1 1 twos c omplement C outside nominal range value s from ? 327 to +327 can be written to the offset register. these values correspond to an offset of 200 mv. a write to the offset register is performed by writing a 13 - bit word to the part as detailed in the parallel interface section. the 10 lsbs of the 13- bit w ord contain the offset value, wh ereas the 3 msbs must be set to 0. failure to write 0 s to the 3 msbs may result in the incorrect operation of the device. p arallel i nterface the ad7482 features two parallel interfacing modes. these modes are selected by the mode pins (see table 8 ). table 8 . operating modes operating mode mode 2 mode 1 do not use 0 0 parallel mode 1 0 1 parallel mode 2 1 0 do not use 1 1 in parallel mode 1, the data in the o utput register is updated on the rising edge of busy at the end of a conversion and is available for reading almost immediately afterward. using this mode, throughput rates of up to 2.5 msps can be achieved. this mode is to be used if the conversion data is required immediately after the conversion is completed. an example where this may be of use is if the ad7482 i s operating at much lower throughput rates in conjunction with the nap m ode (for power saving reasons), and the input signal is being compared with set limits within the dsp or other controller. if the limits are exceeded, the adc is brought immediately into full power operation and commence s sampling at full speed. figure 31 shows a timi ng diagram for the ad7482 operating in parallel mode 1 with both cs and in parallel mode 2, the data in the output register is not updated until the next falling edge of rd tied low. convst . this mode c an be used where a single sample delay is not vital to the system operation , and conversion speeds of greater than 2.5 msps are desired. f or example , this may occur in a system where a large amount of samples are taken at high speed before a n fft is perfor med for frequency analysis of the input signal. figure 32 shows a timing diagram for the ad7482 operating in parallel mode 2 with both cs and rd tied low.
ad7482 rev. b | page 16 of 20 data must not be read from the ad7482 while a conversion is taking place. for this reason, if operating the ad7482 at through - put speeds greater than 2.5 msps, it is necessary to tie both the cs pin and rd p ins on the ad7482 low and use a buffer on the data lines. this situation may also arise in the case where a read operation cannot be completed in the time after the end of one conversion and the start of the quiet period before the next conversion. the maximum sle w rate at the input of the adc must be limi ted to 500 v/ s while busy is low to avoid corrupting the ongoing conversion. in any multiplexed application where the channel is switched during conversion, this is to happen as soon as possible after the reading data f rom t he ad7482 busy falling e dge. data is read from the part via a 13 - bit parallel data bus with the standard cs signal and rd signal . the cs signal and the data lines d0 to d12 leave their high impedance state when both the rd signal are internally gated to enable the conversion result onto the data bus. cs and rd are logic low. therefore, cs may be perma - nently tied logic low if re quired, and the figure 29 rd signal may be used to access the conversion result. shows a timing specifica - tion called t quiet . this is the amount of time that must be left after any data bus activity before the next conversion is initiated . writing to t he ad7482 the ad7482 features a user accessible offset register. this allows the bottom of the transfer function to be shifted by 200 mv. this feature is explained in more detail in the offset/overrange section. to write to the offset register, a 13 - bit word is written to the ad7482 with the 10 lsbs con taining the offset value in two s complement format . the 3 msbs must be set to 0. the offset value m ust be within the range ? 327 to +327, corresponding to an offset from ? 200 mv to +200 mv. the value written to the offset register is stored and used until power is removed from the device, or the device is reset. the value stored can be updated at any tim e between conversions by another write to the device. table 9 shows examples of offset register values and their effective offset voltage. figure 30 shows a timing diagram for writing to t he ad7482. table 9 . offset register examples code (dec imal ) d12 to d10 d9 to d0 (to s complement) offset (mv) ? 327 000 1010111001 ? 200 ? 128 000 1110000000 ? 78.12 +64 000 0001000000 +39.06 +327 000 0101000111 +200 driving t he convst to achieve the specified performance from the ad7482, the pin convst p in mus t be driven from a low jitter source. because the falling edge on the ( ) ( ) 2 2 1 log10 db j in itter tf snr = convst p in determines the sampling instant, any jitt er that may exist on this edge appear s as noise when the analog input signal contains high frequency components . the relationship between the analog input frequency ( f in ), timing jitter ( t j ), and resulti ng snr is given by for example, if the desired snr due to jitter was 100 db with a maximum full - scale analog input frequency of 1.5 mhz, ignorin g all other noise sources, the result is an allowable jitter on the convst falling edge of 1.06 ps. for a 12 - bit converter (ideal snr = 74 db), the allowable jitter is greater than 1.06 ps , but due consideration must be given to the desig n of the typical c onnection convst circuitry to achieve 12 - bit performance with large analog input frequencies. figure 23 shows a typical connection diagram for the ad7482 operating in parallel mode 1. conversion is initiated by a falling edge on convst . when convst goes low, the busy signal goes low, and at the end of conversion, the rising edge of busy is used to activate an interrupt service routine. the cs and in rd lines are then activated to read the 12 data bits (13 bits if using the overrange feature). figure 23 , the v drive p in is tied to dv dd , which results in logic output l evels being either 0 v or dv dd . the voltage applied to v drive controls the voltage value of the output logic signals. for example, if dv dd is supplied by a 5 v supply and v drive is supplied by a 3 v supply, the logic output levels are either 0 v or 3 v. th is feature allows the ad7482 to interface to 3 v devices, while still enabling the adc to process signals at a 5 v supply. microcontroller/ microprocessor reset parallel interface mode1 mode2 write clip nap stby d0 to d12 cs convst rd busy c bias refsel refin refout vin ad7482 adm809 v drive dv dd av dd 0.1f digital supply 4.75v to 5.25v 10f 1nf + 0.1f 0.1f + 47f analog supply 4.75v to 5.25v 0v to 2.5v 1nf 0.47f 0.47f ad780 2.5v reference 02638-023 figure 23 . typical connection diagram
ad7482 rev. b | page 17 of 20 board layout and grounding for optimum performance from the ad7482, it is recommended that a pcb with a minimum of three layers be used. one of these layers, preferably the middle layer, should be as complete a ground plane as possible to give the best shielding. the board should be designed in such a way that the analog and digital circuitry is separated and confined to certain areas of the board. this practice, along with not running digital and analog lines close together, helps to avoid coupling digital noise onto analog lines. the power supply lines to the ad7482 should be approximately 3 mm wide to provide low impedance paths and reduce the effects of glitches on the power supply lines. it is vital that good decoupling also be present. a combination of ferrites and decoupling capa- citors should be used as shown in figure 23. the decoupling capacitors are to be as close to the supply pins as possible. this is made easier by the use of multilayer boards. the signal traces from the ad7482 pins can be run on the top layer, while the decoupling capacitors and ferrites can be mounted on the bottom layer where the power traces exist. the ground plane between the top and bottom planes provides excellent shielding. figure 24 to figure 28 show a sample layout of the board area immediately surrounding the ad7482. pin 1 is the bottom left corner of the device. the black area in each figure indicates the ground plane present on the middle layer figure 24 shows the top layer where the ad7482 is mounted with vias to the bottom routing layer highlighted. figure 25 shows the bottom layer silkscreen where the decoupling components are soldered directly beneath the device. figure 26 shows the top and bottom routing layers overlaid figure 27 shows the bottom layer where the power routing is with the same vias highlighted. figure 28 shows the silkscreen overlaid on the solder pads for the decoupling components, which are c1 to c6: 100 nf, c7 to c8: 470 nf, c9: 1 nf, and l1 to l4: meggit-sigma chip ferrite beads (bmb2a0600rs2). 02638-024 figure 24. top layer routing 02638-026 figure 25. bottom layer silkscreen 02638-028 figure 26. top and bottom routing layers 02638-025 figure 27. bottom layer routing 0 2638-027 figure 28. silkscreen and bottom layer routing
ad7482 rev. b | page 18 of 20 busy write rd convst d[12:0] t 1 t 2 t 4 data valid t 3 t 7 t quiet t conv t acq t 14 t 15 t 8 02638-029 figure 29 . parallel mode r ead cycle convst cs rd d[12:0] offset data t 12 t 13 t 9 t 10 t 11 write 02638-030 figure 30 . parallel mode w rite cycle d[12:0] t 1 t 6 data n ? 1 data n t conv n + 1 n t 2 busy convst 02638-031 figure 31 . parallel mode 1 r ead cycle busy convst d[12:0] t 1 t 5 data n ? 1 data n t conv n n + 1 t 2 02638-032 figure 32 . parallel mode 2 r ead cycle
ad7482 rev . b | page 19 of 20 outline dimensions compliant t o jedec s t andards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706- a figure 33 . 48 - lead plastic quad flatpack [lqfp] (st - 48) dimensions shown in millimeters ordering guide model 1 temperature range integral nonlinearity (inl) package description package option ad7482ast z ? 40c to +85c 1 lsb max imum 48- lead plastic quad flatpack package ( lqfp ) st- 48 ad7482bst z ? 40c to +85c 0.5 lsb max imum 48- lead plastic quad flatpack package ( lqfp ) st- 48 eval - ad7482cb evaluation board 2 eval - controlbrd2z controller board 3 1 z = rohs compliant part. 2 this can be used either as a standalone evaluation board or in conjunction with the controller board for evaluation/demonstration purposes . 3 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators .
ad7482 rev. b | page 20 of 20 notes ? 2002 C 2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02638 -0- 12/09(b)

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