60 n-channel logic level enhancement mode field effect transistor feb. 2003 features 60v , 30a , r ds(on) =25m @v gs =10v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-251 & to-252 package. absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 20 v drain current-continuous @t j =125 c -pulsed i d 30 a i dm 120 a drain-source diode forward current i s 30 a maximum power dissipation p d w operating and storage temperature range t j ,t stg -55 to 175 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 3 50 /w c /w c ? ced6060r/ceu6060r @tc=25 c derate above 25 c 50 0.3 w/ c s g d ceu series to-252aa(d-pak) ced series to-251(l-pak) g g s s d d 6 6-42
ced6060r/ceu6060r electrical characteristics (t c =25 c unless otherwise noted) parameter symbol condition min typ max unit off characteristics drain-source breakdown voltage bv dss = v gs 0v, i d 250 a = 60 v zero gate voltage drain current i dss v ds 60v, v gs 0v == 25 a gate-body leakage i gss v gs 20v, v ds =0v = 100 na on characteristics a gate threshold voltage v gs(th) v ds v gs ,i d = 250 a = 24 v drain-source on-state resistance r ds(on) v gs = 10v, i d =24a 25 m ? on-state drain current i d(on) v gs = 10v, v ds =10v 60 20 a s forward transconductance fs g v ds = 10v, i d =24a switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f v dd =30v, i d = 30a, v gs =10v, r gen = 7.5 ? 15 20 ns ns ns ns 250 300 45 60 130 150 total gate charge gate-source charge gate-drain charge q g q gs q gd v ds =48v, i d =30a, v gs =10v 36 43 nc nc nc 9 19 fall time 6 drain-source avalanche rating a single pulse drain-source avalanche energy maximum drain-source avalanche current e as i as v dd 25v, = l25 h = 200 30 a mj 6-43 r g 25 = ?
ced6060r/ceu6060r parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. [ [ 6 figure 1. output characteristics figure 2. transfer characteristics v gs , gate-to-source voltage (v) v ds , drain-to-source voltage (v) i d , drain current(a) i d , drain current (a) dynamic characteristics b input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =25v, v gs =0v f =1.0mh z 1178 p f 428 p f p f 95 drain-source diode characteristics diode forward voltage v sd v gs = 0v, is =24a 0.9 1.3 v b 6-44 -55 c 40 30 20 10 0 23 456 78 25 c t j =125 c 40 35 30 25 20 15 10 5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 v gs =10,8,7v 6v v gs =5v 4v
ced6060r/ceu6060r 6 with temperature figure 6. breakdown voltage variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) figure 7. transconductance variation with drain current i ds , drain-source current (a) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) figure 5. gate threshold variation 1.15 1.10 1.05 1.0 0.95 0.90 0.85 0.80 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 3 a -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d =250 3 a 50 40 30 20 10 0 01020 3040 v ds =10v 100 10 1 0.4 0.6 0.8 1.0 1.2 1.4 ciss coss crss 1800 1500 1200 900 600 300 0 01015202530 25 c -55 c 3.0 2.5 2.0 1.5 1.0 0.5 0 0102030 50 40 v gs =10v tj=125 c figure 4. on-resistance variation with drain current and temperature figure 3. capacitance v ds , drain-to source voltage (v) i d , drain current(a) c, capacitance (pf) drain-source on-resistance r ds(on) , normalized 6-45
6 ced6060r/ceu6060r figure 11. switching test circuit figure 12. switching waveforms t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width inverted transient thermal impedance 2 1 0.1 0.01 0.01 0.1 1 10 100 1000 10000 p dm t 1 t 2 square wave pulse duration (msec) figure 13. normalized thermal transient impedance curve 1. r / ja (t)=r (t) * r / ja 2. r / ja =see datasheet 3. t jm- t a =p dm *r / ja (t) 4. duty cycle, d=t1/t2 r(t),normalized effective d=0.5 0.2 0.1 0.05 0.02 0.01 single pulse v dd r d v v r s v g gs in gen out l v gs , gate to source voltage (v) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) i d , drain current (a) 300 100 10 1 11060100 v gs =10v single pulse tc=25 c r d s (on )limit dc 10m s 100m s 1ms 100 3 s 10 3 s 15 12 9 6 3 0 0 6 12 18 24 30 36 42 48 v ds =48v i d =30a 6-46
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