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tmp88cs34/cp34 2006-07-06 88cs34-1 cmos 8-bit microcontroller tmp88cs34ng/fg, tmp88cp34ng/fg the tmp88cs34/cp34 is the high speed and high perf ormance 8-bit single chip microcomputers. this mcu contain cpu core, rom, ram, input/output ports, four multi-function timer/counters, serial bus interface, on-screen display, pwm output, 8-bit ad co nverter, and remote control signal preprocessor on chip. product no. rom ram package otp mcu tmp88cs34ng/fg 64 k 8-bit tmp88cp34ng/fg 48 k 8-bit 1.5 k 8-bit p-sdip42-600-1.78 p-qfp44-1414-0.80d tmp88ps34ng/fg features 8-bit single chip microc omputer tlcs-870/x series instruction execution time: 0.25 s (at 16 mhz) 842 basic instructions ? multiplication and division (8 bits 8 bits, 16 bits 8 bits, 16 bits/8 bits) ? bit manipulations (set/clear/complement/move/test/exclusive or) ? 16-bit data and 20-bit data operations ? 1-byte jump/subroutine-call (sho rt relative jump/vector call)
tmp88cs34cp34 2006-07-06 88cs34-2 i/o ports: maximum 33 (high current output: 4) 15 interrupt sources: external 6, internal 10 ? all sources have independent latches each, an d nested interrupt control is available. ? edge-selectable external interrupts with noise reject ? high-speed task switching by register bank changeover rom corrective function two 16-bit timer/counters: tc1, tc2 ? timer, event-counter, pulse width measuremen t, external trigger timer, window modes two 8-bit timer/counters: tc3, tc4 ? timer, event counter, capture (pulse width/duty measurement) mode time base timer (interrupt frequency: 0.95 hz to 31250 hz) watchdog timer ? interrupt source/reset output serial bus interface ? i 2 c bus, 8-bit sio mode (selectable two i/o channels) on-screen display circuit ? font rom characters: mono font 383 characters, color font 96 characters or mono font 447 characters, color font 64 characters ? characters display: 32 columns 12 lines ? composition: 16 18 dots ? size of character: 4 kinds (line by line) ? color of character: 8 or 27 ki nds (character by character) ? variable display position: horizontal 256 steps, vertical 625 steps ? fringing, smoothing, slant, underline , blinking function jitter elimination da conversion (pulse width modulation) outputs ? 14/12-bit resolution (2 channels) ? 12-bit resolution (2 channels) 8-bit successive approxim ate type ad converter with sample and hold high current output: 1 pin (typ. 20 ma) remote control signal preprocessor two power saving operating modes ? stop mode: oscillation stops. battery/capacito r back-up. port output hold/high-impedance. ? idle mode: cpu stops, and peripherals operate using high-frequency clock. release by interrupts. operating voltage: 4.5 to 5.5 v at 16 mhz emulation pod: bm88cs34n0a-m15
tmp88cs34cp34 2006-07-06 88cs34-3 1 vss ( 0 pwm ) p40 ( 1 pwm ) p41 ( 2 pwm ) p42 ( 3 pwm ) p43 p44 p45 p46 p47 (tc2/ 0 int ) p50 (si1/scl1) p51 (so1/sda1) p52 ( 0 kwu / 1 sck /int2/tc1/ain0) p53 ( 1 kwu /ain1) p54 ( 2 kwu /ain2) p55 ( 3 kwu /ain3) p56 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 vdd p33 (tc4) p32 vvss p35 (sda0) p34 (scl0) p31 (int4/tc3) p30 (int3/rxin) p20 ( 5 int / stop ) reset xout xin test osc2 osc1 p71 ( vd ) (gin) p62 (rin) p63 (i) p57 18 19 20 21 25 24 23 22 p67 (y/bl) p66 (b) p65 (g) p64 (r) 17 26 ( 5 kwu /bin/ain5) p61 ( 4 kwu /y/blin/ain4) p60 p70 ( hd ) pin assignments p-sdip42-600-1.78 p-qfp44-1414-0.80d 31 34 (sda0) p35 p30 (int3/rxin) p20 ( int5 / stop ) vvss p32 n.c. vdd vss ( 0 pwm ) p40 ( 1 pwm ) p41 ( 2 pwm ) p42 ( 3 pwm ) p43 35 36 37 38 39 40 41 42 43 44 30 33 p34 (scl0) p31 (int4/tc3) 32 27 xin test 26 29 reset xout 28 23 p71 ( vd ) 25 osc2 osc1 24 22 21 20 19 18 17 16 15 14 13 12 p70 ( hd ) p67 (y/bl) p66 (b) p65 (g) p64 (r) n.c. p57 p63 (rin) p62 (gin) p60 (y/blin/ain4/ 4 kwu ) 3 4 1 2 7 8 5 6 11 9 10 p46 p47 p44 p45 (so1/sda1) p52 ( kwu0 / sck1 /int2/tc1/ain0) p53 (tc2/i nt0 ) p50 (si1/ scl1 ) p51 ( kwu3 /ain3) p56 ( kwu1 /ain1) p54 ( kwu2 /ain2) p55 p61 (bin//ain5/ kwu5 ) (tc4) p33 p-sdip42-600-1.78 tmp88cs34ng tmp88cp34ng tmp88ps34ng package p-qfp44-1414-0.80d package tmp88cs34fg TMP88CP34FG tmp88ps34fg
tmp88cs34cp34 2006-07-06 88cs34-4 pin functions (1/2) pin name i/o function p20 ( int5 / stop ) i/o (input) 1-bit input/output port with latch. when used as an input port, the latch must be set to ?1?. external interrupt input 5 or stop mode release signal input p35 (sda0) i/o (input/output) i 2 c bus serial data input/output 0 p34 (scl0) i/o (input/output) i 2 c bus serial clock input/output 0 p33 (tc4) i/o (input) p32 i/o video signal input 1 or composite sync input p31 (int4/tc3) i/o (input) external interrupt input 4 or timer/counter input 3 p30 (int3/rxin) i/o (input) 6-bit programmable input/output port. each bit of these ports can be individually configured as an input or an output under software control. during reset, all bits are configured as inputs. when used as a serial bus interface input/output, the latch must be set to ?1?. external interrupt input 3 or remote control signal preprocessor input p47 i/o p46 i/o p45 i/o p44 i/o p43 ( pwm3 ) i/o (output) p42 ( pwm2 ) i/o (output) 12-bit da conversion (pwm) outputs p41 ( pwm1 ) i/o (output) p40 ( pwm0 ) i/o (output) 8-bit programmable input/output port. each bit of these ports can be individually configured as an input or an output under software control. during reset, all bits are configured as inputs. 14/12-bit da conversion (pwm) outputs p57 (i) i/o (output) translucent signal output p56 ( kwu3 /ain3) i/o (input) p55 ( kwu2 /ain2) i/o (input) p54 ( kwu1 /ain1) i/o (input) key on wake-up inputs or ad converter analog inputs p53 ( kwu0 /ain0/tc1 /int2/ sck1 ) i/o (input/input/input /input/output) key on wake-up input or ad converter analog input or timer/counter input 1 or external interrupt input 2 or sio serial clock input/output 1 p52 (sda1/so1) i/o (input/output/output) i 2 c bus serial data input/output 1 or sio serial data output 1 p51 (scl1/si1) i/o (input/output/input) i 2 c bus serial data input/output 1 or sio serial data input 1 p50 (tc2/ int0 ) i/o (input/input) 8-bit programmable input/output port. each bit of these ports can be individually configured as an input or an output under software control. during reset, all bits are configured as inputs. when used as a serial bus interface input/output, the latch must be set to ?1?. timer/counter input 2 or external interrupt input 0 p67 (y/bl) i/o (output) y or bl output p66 (b) i/o (output) p65 (g) i/o (output) p64 (r) i/o (output) r/g/b outputs p63 (rin) i/o (input) r input p62 (gin) i/o (input) g input p61 ( kwu5 /bin/ain5) i/o (input) key on wake-up input 5 or b input or ad converter analog input 5 p60 ( kwu4 /yblin/ain4) i/o (input) 8-bit programmable input/output port. (p67 to 61: tri-state, p60: high current output) each bit of these ports can be individually configured as an input or an output under software control. during reset, all bits are configured as inputs. when used p64 to p67 as port, each bit of the p6 port data selection register (bit 7 to 4 in orp6s) must be set to ?1?. p63 to p61 output 0 after a reset. when these dual-function pins are used as ports, be sure to set orp6s2 to ?1?. key on wake-up input 4 or y/bl input or ad converter analog input 4
tmp88cs34cp34 2006-07-06 88cs34-5 pin functions (2/2) pin name i/o function p71 ( vd ) i/o (input) vertical sy nchronous signal input p70 ( hd ) i/o (input) 2-bit programmable input/output port. each bit of these ports can be individually configured as an input or an output under software control. during reset, all bits are configured as inputs. horizontal synchr onous signal input xin, xout input, output resonator connecting pins. for inputti ng external clock, xin is used and xout is opened. reset i/o reset signal input or watchdog timer output/address-trap-reset output/system-clock-rest output test input test pin for out-going test. be tied to low. osc1, osc2 input, output resonator conne cting pins for on-screen display circuitry vdd, vss, vvss power supply + 5 v, 0 v (gnd)
tmp88cs34cp34 2006-07-06 88cs34-6 block diagram reset i/o test pin xin xout osc connecting pins for on-screen display resonator connecting pins osc1 osc2 p6 p7 p5 on-screen display circuit system controller standby controller timing generator clock generator interrupt controller time base timer watchdog timer 16-bit timer tc1 tc2 p30 to p35 p64 to p67 p70, 71 p57 display memory character rom jitter elimination i/o ports hd vd r, g, b, y/bl tlcs-870/x cpu core data memory (ram) rom corrective circuit program counter 8-bit timer/counter tc3 tc4 program memory (rom) inst. register inst. decoder serial bus interface p3 p6 key on wake up 8-bit ad p5 da converter (pwm) p4 p2 high frequency p60 to p63 p50 to p56 p40 to p47 p20 i/o ports power supply vdd vss vvss reset test y/blin rin gin bin remote control signal i
tmp88cs34/cp34 2006-07-06 88cs34-7 operational description 1. cpu core functions the cpu core consists of a cpu, a system cl ock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory , the data memory, the external memory interface, and the reset circuit. 1.1 memory address map the tmp88cs34/cp34 memory consists of four blocks: rom, ram, sfr (special function register), and dbr (data buffer register). they are all mapped to a 1-mbyte address space. figure 1.1.1 shows the tmp88cs34/cp34 memory address map. there are 16 banks of the general-purpose register. the register banks are also assigned to the ram address space. figure 1.1.1 memory address map rom: read only memory includes program memory, character data memory for osd ram: random access memory includes data memory, stack, general-purpose register banks sfr: special function register includes i/o ports, peripheral hardware control regi sters, peripheral hardware status registers system control registers, interrupt c ontrol registers, program status word dbr: data buffer register includes control register for on-screen display (osd) remote-control-receive control/status regi sters, rom correction control registers test video signal control registers 128 bytes 64 bytes 1536 bytes 128 bytes 64 bytes 128 bytes 64 bytes 128 bytes 65280 bytes 64 bytes tmp88cs34 00000h 0003fh 00040h 000bfh 000c0h 006bfh 00f80h 00fffh 04000h 13effh fff00h fff3fh fff40h fff7fh fff80h fffffh ram sfr dbr rom 128 bytes 128 bytes 1536 bytes 48896 bytes 64 bytes 64 bytes tmp88cp34 006bfh 00f80h 00fffh 04000h 0feffh 00000h 0003fh 00040h 000bfh 000c0h fff00h fff3fh fff40h fff7fh fff80h fffffh
tmp88cs34/cp34 2006-07-06 88cs34-8 1.2 program memory (rom) the tmp88cs34 contains a 64-kbyte progra m memory (mask rom) at addresses from 04000 to 13effh and fff00 to fffffh. the tmp88cp34 contains a 48-kbyte program memory (mask rom) at address from 04000 to 0feffh and fff00 to fffffh. addresses fff00 through fffffh in the program memory are also used for a particular purpose. 1.3 data memory (ram) the tmp88cs34/cp34 has a 1.5-kbyte data me mory (static ram) address from 0040 to 06bfh. the first 128 bytes (addresses 00040 through 000bf h) in the built-in ra m are also available as general-purpose register banks. the general-purpuse registers are mapped in the ram; therefore, do not clear ram at the current bank addresses. example: clears ram to ?00h? ex cept the bank 0 (tmp88cs34/cp34): ld hl, 0048h ; sets start address to hl register pair ld a, h ; sets initial data (00h) to a register ld bc, 0677h ; sets number of byte to bc register pair sramclr: ld (hl + ), a dec bc jrs f, sramclr note: the data memory contents become unstable wh en the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. note that the general-purpose registers are mapped in the ram; therefore, do not clear ram at the current bank addresses. 1.4 system clock controller the system clock controller consists of a clock generator, a timing generator, and a stand-by controller. figure 1.4.1 system clock controller 00036h timing generator control register 00038h fc xout xin system clocks timing generator high-frequency clock oscillator stand-by controller clock generator control system control registers syscr1 00039h syscr2 tbtcr clock generator
tmp88cs34/cp34 2006-07-06 88cs34-9 1.4.1 clock generator the clock generator generates the basic clock which provides the system clocks supplied to the cpu core and peripheral hardware. it contains oscillation circuit: one for the high-frequency clock. the high-frequency (fc) clock can be easily obtained by connecting a resonator between the xin/xout pin, respectively. clock input from an external oscillator is also possible. in this case, external clock is applied to xin pin with xout pin not connected. figure 1.4.2 examples of resonator connection note: accurate adjustment of the oscillation frequency: although hardware to externally and directly monitor the basic clock pulse is not provided, the oscillation frequency can be adjusted by making the program to output fixed frequency pulses to the port while disabling all interrupts and monitoring this pulse. with a system requiring adjustment of t he oscillation frequency, the adjusting program must be created beforehand. 1.4.2 timing generator the timing generator generates from the basic clock the various system clocks supplied to the cpu core and peripheral hardware. th e timing generator provides the following functions: 1. generation of ma in system clock 2. generation of source cloc ks for time base timer 3. generation of source cl ocks for watchdog timer 4. generation of internal source cloc ks for timer/counters tc1 to tc4 5. generation of warm-up clocks for releasing stop mode 6. generation of a clock for releasing reset output (1) configuration of timing generator the timing generator consists of a 21-stage di vider with a divided-by-3 prescaler, a main system clock generator, and machine cycle counters. during reset and at releasing stop mode, the prescaler and the divider are cleared to ?0?, however, the prescaler is not cleared. an input clock to the 7th stage of the divider depends on the operating mode. a divided-by-256 of high-frequency clock (fc/2 8 ) is input to the 7th stage of the divider. xout xin (open) xin (a) crystal/ceramic resonator (b) external oscillator high-frequency clock xout
tmp88cs34/cp34 2006-07-06 88cs34-10 figure 1.4.3 configurat ion of timing generator cgcr (00030h) ?0? ?0? dv1ck ?0? ?0? ?0? ?0? ?0? (initial value: 0000 0000) dv1ck selection of input clock to the 1?st stage of the divider. 0: fc/4 1: fc/8 r/w note 1: fc: high-frequency clock [hz] * : don?t care note 2: the all bits except dv1ck are cleared to ?0?. figure 1.4.4 divider control register fc8cr (00feeh) d1 d0 read/write (initial value: 0000 0010) d1 d0 fc8out 1 0 1/2 fc 0 0 1/1 fc figure 1.4.5 fc8 control register divider reset circuit prescaler fm fc divider watchdog timer machine cycle counters dv1ck stand-by controller timer/ counters time base timer 0 1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 s y b a high-frequency clock fc/2 8 machine cycles states mk8 mhz fc d1 d0 jitta fc8out
tmp88cs34/cp34 2006-07-06 88cs34-11 (2) machine cycle instruction execution and peripheral hardware operation are synchronized with the main system clock. the minimum instruction execution unit is called a ?machine cycle?. there are a total of 15 different types of instructions for the tlcs-870/x series: ranging from 1-cycle instructions which require on e machine cycle for execution to 15-cycle instructions which require 15 machine cycles for execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 1.4.6 machine cycle 1.4.3 stand-by controller the stand-by controller starts and stops the switches the main system clock. these modes are controlled by the system control registers (syscr1, syscr2). figure 1.4.7 shows the operating mode transition diagram and figure 1.4.8 shows the system control registers. single-clock mode in the single-clock mode, the machine cycle time is 4/fc [s] (0.25 s at fc = 16 mhz). 1. normal mode in this mode, both the cpu core and on-chip peripherals operate using the high-frequency clock. 2. idle mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however, on-chip peripherals remain active (operate using the high-frequency clock). idle mode is started by setting idle bit in the system control register 2 (syscr2), and idle mode is released to normal mode by an interrupt request from on-chip peripherals or external interrupt inputs. when imf (interrupt master enable flag) is ?1? (interrupt enable), the execution will resume upon acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. when imf is ?0? (interrupt disable), the execution will resume with the instruction which follows idle mode start instruction. 3. stop mode in this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. the internal status immediately prior to the halt is held with the lowest power consumption during this mode. stop mode is started by setting stop bit in the system control register 1 (syscr1), and stop mode is released by an input (either level-sensitive or edge-sensitive can be programmably selected) to the stop pin. after the warming-up period is completed, the execution resumes with the next instru ction which follows the stop mode start instruction. 1/fc main system clock fm state machine cycle (0.25 s at fc = 16 mhz) s3 s2 s1 s0 s3 s2 s1 s0
tmp88cs34/cp34 2006-07-06 88cs34-12 note: normal mode is generically called normal ; stop mode is called stop; and idle mode is called idle. frequency operating mode high-frequency low-frequency cpu core on-chip peripherals machine cycle time reset reset reset normal operate idle turning on oscillation operate 4/fc [s] single-clock stop turning off oscillation turning off oscillation halt halt ? figure 1.4.7 operating mode transition diagram (a) single-clock mode reset normal mode idle mode software stop pin input interrupt reset release software stop mode
tmp88cs34/cp34 2006-07-06 88cs34-13 system control register 1 7 6 5 4 3 2 1 0 syscr1 (00038h) stop relm ?0? ?1? wut (initial value: 0000 00 ** ) stop stop mode start 0: cpu core and peripherals remain active 1: cpu core and peripherals are halted (start stop mode) relm release method for stop mode 0: edge-sensitive re lease (rising edge) 1: level-sensitive release (?h? level) return to normal mode dv1ck = 0 dv1ck = 1 wut warming-up time at releasing stop mode 00 01 10 11 3 2 16 /fc 2 16 /fc reserved reserved 3 2 17 /fc 2 17 /fc reserved reserved r/w note 1: always set bit 5 in syscr1 to ?0?. note 2: when stop mode is released with reset pin input, a return is made to normal mode regardless of the retm contents. note 3: fc: high-frequency clock [hz] * : don?t care note 4: bits 1 and 0 in syscr1 are read in as undefined data when a read instruction is executed. note 5: always set bit 4 in syscr1 to ?1? when stop mode is started. system control register 2 7 6 5 4 3 2 1 0 syscr2 (00039h) ?1? ?0? ?0? idle (initial value: 1000 **** ) idle idle mode start 0: cpu and watchdog timer remain active 1: cpu and watchdog timer are stopped (start idle mode) r/w note 1: * : don?t care note 2: always set bit 7, 6 and 5 in syscr2 to ?100?. figure 1.4.8 system control registers
tmp88cs34/cp34 2006-07-06 88cs34-14 1.4.4 operating mode control (1) stop mode stop mode is controlled by the system control register 1 (syscr1) and the stop pin input. the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting stop (bit 7 in syscr1 ) to ?1?. during stop mode, the following status is maintained. 1. oscillations are turned off, and all internal operations are halted. 2. the data memory, registers and port output latches are all held in the status in effect before stop mode was entered. 3. the prescaler and the divider of the timing generator are cleared to ?0?. 4. the program counter holds the address of the instruction following the instruction which started the stop mode. stop mode includes a level-sensitive release mode and an edge-sensitive release mode, either of which can be selected with relm (bit 6 in syscr1). a. level-sensitive release mode (relm = 1) in this mode, stop mode is released by setting the stop pin high. this mode is used for capacitor back-up when the main power supply is cut off and long term battery back-up. when the stop pin input is high, executing an instruction which starts the stop mode will not place in stop mode but instead will immediately start the release sequence (warm-up). thus, to start stop mode in the level-sensitive release mode, it is necessary for the program to first confirm that the stop pin input is low. the following method can be used for confirmation: using an external interrupt input int5 ( int5 is a falling edge-sensitive input). example: starting stop mode with an int5 interrupt. pint5: test (p2) . 0 ; jrs f, sint5 to reject noise, the stop mode does not start if port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. set (syscr1) . 7 ; starts stop mode ldw (il), 1110011101010111b ; il 12, 11, 7, 5, 3 0 (clears interrupt latches) sint5: reti note 1: after warming up is started, when stop pin input is changed ?l? leve l, stop mode is not placed. note 2: when changing to the level-s ensitive release mode from the edge-s ensitive release mode, the release mode is not switched until a rising edge of the stop pin input is detected. figure 1.4.9 level-sensitive release mode stop pin xout pin normal operation confirm by program that the stop pin input is low and start stop mode. v ih stop mode is released by the hardware. always released if the stop pin input is high. normal operation stop operation warm-up
tmp88cs34/cp34 2006-07-06 88cs34-15 b. edge-sensitive release mode (relm = 0) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in applications where a relatively short program is executed repeatedly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high. example: starting stop mode from normal mode ld (syscr1), 10010000b ; starts after specified to the edge-sensitive mode figure 1.4.10 edge-sensitive release mode stop mode is released by the following sequence: 1. when returning to normal, clock oscillator is turned on. 2. a warming-up period is inserted to allow oscillation time to stabilize. during warm-up, all internal operations remain halted. two different warming-up times can be selected with wut (bits 2 and 3 in syscr1) as determined by the resonator characteristics. 3. when the warming-up time has elapsed, normal operation resumes with the instruction following the stop mode start instruction (e.g. [set (syscr1). 7]). the start is made after the divider of the timing generator is cleared to ?0?. table 1.4.1 warming-up time example warming-up time [ms] return to normal mode wut dv1ck = 0 dv1ck = 1 00 3 2 16 /fc (12.29) 3 2 17 /fc (24.58) 01 2 16 /fc (4.10) 2 17 /fc (8.20) 10 reserved ( - ) reserved ( - ) 11 reserved ( - ) reserved ( - ) note: the warming-up time is obtained by dividi ng the basic clock by t he divider: therefore, the warming-up time may include a certain am ount of error if ther e is any fluctuation of the oscillation frequency when stop mode is released. thus, the warming-up time must be considered an approximate value. stop pin normal operation stop mode started by the program. xout pin stop mode is released by the hardware at the rising edge of stop pin input. v ih warm-up normal o p eration stop operation stop operation
tmp88cs34/cp34 2006-07-06 88cs34-16 figure 1.4.11 stop mode start/release instruction at address a + 4 a + 6 3 instruction at address a + 3 2 a + 5 instruction at address a + 2 1 a + 4 (b) stop mode release count up 0 a + 3 turn on stop pin input oscillator circuit main system clock program counter instruction execution divider halt 0 turn off warming up oscillator circuit main system clock program counte r instruction execution divide r a + 2 n turn on (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) n + 1 set (syscr1). 7 n + 2 a + 3 n + 3 0 turn of f n + 4 halt
tmp88cs34/cp34 2006-07-06 88cs34-17 stop mode can also be released by setting the reset pin low, which immediately performs the normal reset operation. note: when stop mode is released with a low hold voltage, the following cautions must be observed. the power supply voltage must be at the operating voltage level before releasing stop mode. the reset pin input must also be high, rising together with the power supply voltage. in this case, if an external time constant circuit has been connected, the reset pin input voltage will increase at a slower rate than the power supply voltage. at this time, there is a danger that a reset may occur if input voltage level of the reset pin drops below the non-inverting high-level input voltage (hysteresis input). (2) idle mode idle mode is controlled by the system co ntrol register 2 and maskable interrupts. the following status is maintained during idle mode. 1. operation of the cpu and watchdog timer is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers and port output latches are all held in the status in effect before idle mode was entered. 3. the program counter holds the address of the instruction following the instruction which started idle mode. example: starting idle mode. set (syscr2) . 4 ; idle 1 figure 1.4.12 idle mode normal release mode no no reset yes (interrupt release mode) yes yes no (high) cpu, wdt are halted execution of the instruction which follows the idle mode start instruction interrupt processing imf = 1 interrupt request reset input starting idle mode b y instruction
tmp88cs34/cp34 2006-07-06 88cs34-18 idle mode includes a normal release mode and an interrupt release mode. selection is made with the interrupt master enable flag (imf). releasing the idle mode returns from idle to normal. a. normal rele ase mode (imf = ?0?) idle mode is released by any interrupt so urce enabled by the individual interrupt enable flag (ef) or an external interrupt 0 ( int0 pin) request. execution resumes with the instruction following the idle mode start instruction (e.g. [set (syscr2).4]). normally, il (interrupt latch) of interrupt source to release idle mode must be cleared by load instructions. b. interrupt release mode (imf = ?1?) idle mode is released and interrupt processing is started by any interrupt source enabled with the individual interrupt enable flag (ef) or an external interrupt 0 ( int0 pin) request. after the interrupt is processed, the execution resumes from the instruction following the instruction which started idle mode. note: when a watchdog timer interrupt is generated immediately before the idle mode is started, the watchdog timer interrupt w ill be processed but idle mode will not be started.
tmp88cs34/cp34 2006-07-06 88cs34-19 figure 1.4.13 idle mode start/release set (syscr2). 4 (a) idle mode start (example: starting with the set instruction located at address a) main system clock interrupt request program counte r instruction execution watchdog time r a + 2 operate a + 3 halt operate (i) normal release mode halt halt a + 4 instruction at address a + 2 a + 3 main system clock interrupt request program counte r instruction execution watchdog time r (b) idle mode release (ii) interrupt release mode operate halt halt acceptance of interrupt main system clock interrupt request program counte r instruction execution watchdog time r a + 3
tmp88cs34/cp34 2006-07-06 88cs34-20 idle mode can also be released by setting the reset pin low, which immediately performs the reset operation. after reset, the tmp88cs34/cp34 is placed in normal mode.
tmp88cs34/cp34 2006-07-06 88cs34-21 1.5 interrupt controller the tmp88cs34/cp34 has a total of 16 interrupt sources; 6 externals and 10 internals. multiple interrupts with priorities are also possible. two of the internal sources are pseudo non-maskable interrupts; the remainder are all maskable interrupts. interrupt sources are provided with interrupt la tches (il), which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by the generation of its interrupt request which requests the cpu to accept its interrupts. interrupts are enabled or disabled by software using the interrupt master enable flag (imf) and interrupt enable flag (ef). if more than one interrupts are generated simulaneously, interrupts are accepted in order which is dominated by hardware. however, there are no prioritized in terrupt factors among non-maskable interrupts. table 1.5.1 interrupt sources interrupt source enable condition interrupt latch vector table address priority internal/ external (reset) non-maskable ? ffffch high 0 internal intsw (software interrupt) ? ffff8h 1 internal intwdt (watchdog timer interrupt) pseudo non-maskable il 2 ffff4h 2 external int0 (external interrupt 0) imf ? ef 3 = 1, int0en = 1il 3 ffff0h 3 internal inttc1 (16-bit tc1 interrupt) imf ? ef 4 = 1 il 4 fffech 4 external intkwu (key-on-wake-up) imf ? ef 5 = 1 il 5 fffe8h 5 internal inttbt (time base timer interrupt) imf ? ef 6 = 1 il 6 fffe4h 6 external int2 (external interrupt 2) imf ? ef 7 = 1 il 7 fffe0h 7 internal inttc3 (8-bit tc3 interrupt) imf ? ef 8 = 1 il 8 fffdch 8 internal inttsbi (sbi interrupt) imf ? ef 9 = 1 il 9 fffd8h 9 internal inttc4 (8-bit tc4 interrupt) imf ? ef 10 = 1 il 10 fffd4h 10 external int3 (external interrupt 3) imf ? ef 11 = 1 il 11 fffd0h 11 external int4 (external interrupt 4) imf ? ef 12 = 1 il 12 fffcch 12 internal intadc (ad converter interrupt) imf ? ef 13 = 1 il 13 fffc8h 13 internal inttc2 (16-bit tc2 interrupt) imf ? ef 14 = 1 il 14 fffc4h 14 external int5 (external interrupt 5) imf ? ef 15 = 1 il 15 fffc0h 15 internal intosd (osd interrupt) imf ? ef 16 = 1 il 16 fffbch 16 reserved imf ? ef 17 = 1 il 17 fffb8h 17 reserved imf ? ef 18 = 1 il 18 fffb4h 18 reserved imf ? ef 19 = 1 il 19 fffb0h 19 reserved imf ? ef 20 = 1 il 20 fffach 20 reserved imf ? ef 21 = 1 il 21 fffa8h 21 reserved imf ? ef 22 = 1 il 22 fffa4h 22 reserved imf ? ef 23 = 1 il 23 fffa0h 23 reserved imf ? ef 24 = 1 il 24 fff9ch 24 reserved imf ? ef 25 = 1 il 25 fff98h 25 reserved imf ? ef 26 = 1 il 26 fff94h 26 reserved imf ? ef 27 = 1 il 27 fff90h 27 reserved imf ? ef 28 = 1 il 28 fff8ch 28 reserved imf ? ef 29 = 1 il 29 fff88h 29 reserved imf ? ef 30 = 1 il 30 fff84h 30 reserved imf ? ef 31 = 1 il 31 fff80h low 31 note : before you change each enable flag (ef) and/or each interrupt latch (il), be sure to clear the interrupt master enable flag (imf) to ?0? (to disable interrupts). 1. after a di instruction is executed. 2. when an interrupt is accepted, im f is autamatically cleared to ?0?. however, to enable nested interrupts change ef and/or il before setting imf to ?1? (to enable interrupts). if the individual enable flags (ef) and interrupts (il) are set under condition s other than the above, proper operation cannot be guararteed.
tmp88cs34/cp34 2006-07-06 88cs34-22 figure 1.5.1 interrupt controller block diagram intwdt intkow inttc1 int0 intsw int0en external interrupts control register write strobe for il internal reset interrupt enable flag instruction which clears imf to ?0? [di] instruction priority encoder & vector table address generator non-maskable interrupts request maskable interrupts re q uest interrupt request vector table address release idle mode request interrupt acceptance interrupt master enable flag [reti] instruction during maskable interrupt service [ei] instruction instruction which sets imf to ?1? imf q s r il 5 q s r il 4 q s r il 3 q s r il 2 q s r interrupt latch digital noise reject circuit intosd il 16 q s r il 16 to il 2 eintcr il 31 to 3 write data ef 31 to ef 3 [retn] instruction only when imf was set before interrupt was accepted
tmp88cs34/cp34 2006-07-06 88cs34-23 interrupt latches (il) that hold the interrupt requests are provided for interrupt sources. each interrupt vector is independent. the interrupt latch is set to ?1? when an inte rrupt request is generated, and requests the cpu to accept the interrupt. the acceptance of maskable interrupts can be selectively enabled and disabled by program using the interrupt master enable flag (imf) and the individual interrupt enable flags (ef). when two or more interrupts are generated simultaneously, the interrupt is accepted in the highest priori ty order as determined by the hardware. figure 1.5.1 shows the interrupt controller. (1) interrupt latches (il 31 to il 2 ) interrupt latches are provided for each source , except for a software interrupt. the latch is set to ?1? when an interrupt request is ge nerated, and requests the cpu to accept the interrupt. the latch is cleared to ?0? just after the interrupt is accepted. all interrupt latches are initialized to ?0? during reset. the interrupt latches are assigned to addresses 0003ch, 0003dh, 0002eh and 0002fh in the sfr. except for il 2 , each latch can be cleared to ?0? individually by an instruction; however, the read-modify-write instruction such as bit manipulation or operation instructions cannot be used. when interrupt occu rred during order execution, the reason is because interrupt request is cleared. thus , interrupt requests can be canceled and initialized by the program. note that request the interrupt latches cannot be set to ?1? by an instruction. for example, it may be that each latch is cleared even if an interrupt request is generated during instruction exection. the contents of interrupt latches can be read out by an instruction. therefore, testing interrupt request by software is possible. example 1: clears interrupt latches di ; disable interrupt ldw (ill), 1110100000111111b ; il 12 , il 10 to il 6 0 example 2: reads interrupt latches ld wa, (ill) ; w il h , a il l example 3: tests an interrupt latch test (ill). 7 ; if il 7 = 1 then jump jr f, sset (2) interrupt enable register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except for the pseudo non-maskable interrupts (software and watchdog timer interrupts). pseudo non-maskable interrupts are accepted regardless of the contents of the eir; however, the pseudo non-maskable interrupt cann ot be nested more than once at the same time. the eir consists of an interrupt master enab le flag (imf) and the individual interrupt enable flags (ef). these registers are assigned to addresses 0003ah, 0003bh, 0002ch and 0002dh in the sfr, and can be read and written by an instruction (including read-modify-write instruction such as bit manipulation instructions). note: do not use the read-modify-write instru ction for the eirl (address 0003ah) during pseudo non-maskable interrupt service task. if the read-modify-write instruction is used, the imf is not set to ?1? after retn.
tmp88cs34/cp34 2006-07-06 88cs34-24 1. interrupt master enable flag (imf) the interrupt master enable flag (imf) enables and disables the acceptance of all maskable interrupts. clearing this flag to ?0 ? disables the acceptance of all maskable interrupts. setting to ?1? enables the acceptance of interrupts. when an interrupt is accepted, this flag is cleared to ?0? to te mporarily disable the acceptance of other maskable interrupts. after execution of the interrupt service program, this flag is set to ?1? by the ma skable interrupt return instruction [reti] to again enable the acceptance of interrupts. if an interrupt request has already been occurred, interrupt service starts imme diately after execution of the [reti] instruction. pseudo non-maskable interrupts are returned by the [retn] instruction. in this case, the imf is set to ?1? only when pseudo non-maskable interrupt service is started with interrupt acceptance enabled (imf = 1). note that the imf remains ?0? when cleared by the interrupt service program. the imf is assigned to bit 0 at address 0003ah in the sfr, and can be read and written by an instruction. the imf is norm ally set and cleared by the [ei] and [di] instructions, and the imf is initialized to ?0? during reset. 2. individual interrupt enable flags (ef 16 to ef 3 ) these flags enable and disable the acceptance of individual maskable interrupts, except for an external interrupt 0. settin g the corresponding bit of an individual interrupt enable flag to ?1? enables acceptance of an interrupt, setting the bit to ?0? disables acceptance. example 1: sets ef for individual in terrupt enable, and sets imf to ?1?. di ; disable interrupt ld (eire), 00000001b ; ef 16 1 ldw (eirl), 1110100010100001b ef 15 to ef 13 , ef 11 , ef 7 , ef 5 , imf 1 example 2: sets an in dividual interrupt enable flag to ?1?. set (eirh). 4 ; ef 12 1
tmp88cs34/cp34 2006-07-06 88cs34-25 interrupt latches (il) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 il 31 il 30 il 29 il 28 il 27 il 26 il 25 il 24 il 23 il 22 il 21 il 20 il 19 il 18 il 17 il 16 il (0002e, 0002fh) il d (0002fh) il e (0002eh) (initial value: 00000000 00000000) il 15 il 14 il 13 il 12 il 11 il 10 il 9 il 8 il 7 il 6 il 5 il 4 il 3 il 2 inf il (0003c, 0003dh) il h (0003dh) il e (0003ch) (initial value: 00000000 000000 ** ) interrupt enable registers (eir) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ef 31 ef 30 ef 29 ef 28 ef 27 ef 26 ef 25 ef 24 ef 23 ef 22 ef 21 ef 20 ef 19 ef 18 ef 17 ef 16 eir (0002c, 0002dh) eir d (0002dh) eir e (0002ch) (initial value: 00000000 00000000) ef 15 ef 14 ef 13 ef 12 ef 11 ef 10 ef 9 ef 8 ef 7 ef 6 ef 5 ef 4 ef 3 imf eir (0003a, 0003bh) eir h (0003bh) eir l (0003ah) (initial value: 00000000 00000 ** 0) note 1: do not clear il with read-modify-w rite instructions such as bit operations. note 2: do not set imf to ?1? during non-maskable interrupt service program. note 3: bits 1 and 0 in il l are read in as undefined data when a read instruction is executed. note 4: * : don?t care note 5: do not clear il 2 to ?0? by an instruction. note 6: at tmp88cs34/cp34, il 17 to il 31 and if 17 to if 31 are not used. note 7: after imf is cleared, modify ef and il. figure 1.5.2 interrupt latches (il) and interrupt enable registers (eir) 1.5.1 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ?0? by a reset or an instruction. interrupt acceptance sequence requires 12 machine cycles (3 s at fc = 16 mhz in the normal mode) after the completion of the current instruction execution. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for pseudo non-maskable interrupts). figure 1.5.3 shows the timing chart of interrupt acceptance processing. (1) interrupt acceptance interrupt acceptance processing is as follows. 1. the interrupt master enable flag (imf) is cleared to ?0? to temporarily disable the acceptance of any following maskable inte rrupts. when a non-maskable interrupt is accepted, the acceptance of any follow ing interrupts is temporarily disabled. 2. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. 3. the contents of the program counter (pc) and the program status word (psw) are saved (pushed) on the stack in sequence of psw h , psw l , pc e , pc h , pc l . the stack pointer (sp) is decremented five times. 4. the entry address of the interrupt service program is read from the vector table, and set to the program counter.
tmp88cs34/cp34 2006-07-06 88cs34-26 5. the rbs control code is read from the vector table. the lower 4-bit of this code is added to the rbs. 6. the instruction stored at the entry address of the interrupt service program is executed. example: correspondence between vector table address for inttbt and the entry address of the interrupt service program. a maskable interrupt is not accepted until the imf is set to ?1? even if the maskable interrupt higher than the level of current servicing interrupt is occurred. when nested interrupt service is necessary, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt so urces are selectively enabled by the individual interrupt enable flags. note: do not use the read-modify-write instru ction for the eirl (address 0003ah) during pseudo non-maskable inte rrupt service task. 43h d2h 0ch 06h vecto r fffe5h fffe6h fffe7h rbs control fffe4h vector table address interrupt service program cd244h cd245h cd246h cd243h entry address
tmp88cs34/cp34 2006-07-06 88cs34-27 note1: a: return address, b: entry address, c: address which the reti instruction is stored note2: the maximum response time from when an il is se t until an interrupt acceptance processing starts is 62/fc [s] with interrupt enabled. figure 1.5.3 timing chart of interrupt acc eptance and interrupt return instruction n n ? 1n ? 2n ? 3n ? 4n ? 5 a a + 1 a b b + 2 b + 1 b + 3 b + 2 b + 1 b n ? 4 n ? 3 n ? 2 n ? 1 n fffe4 a + 1 a fffe5 fffe6 fffe7 k = i + (fffe7h). 3 ? 0 i instruction interrupt acceptance instruction (a) interrupt acceptance imf execution a ddress bus pc sp rbs il 6 il 15 inttbt int5 1-machine cycle interrupt service task inf a + 1 c c + 1n ? 4n ? 3n ? 2n ? 1n a n ? 5 n ? 4n ? 3n ? 2n ? 1n imf execution a ddress bus pc sp rbs (b) return from interrupt instruction a + 2 a c + 2 c + 1 c i k reti instruction a + 1 interru p t service task inf
tmp88cs34/cp34 2006-07-06 88cs34-28 (2) saving/restoring ge neral-purpose registers during interrupt acceptance processing, the program counter (pc) and the program status word (psw) are automatically saved on the stack, but not the accumulator and other registers. these registers ar e saved by the program if ne cessary. also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. the following method is used to save/restore the general-purpose registers. 1. general-purpose register save/restore by automatic register bank changeover the general-purpose registers can be saved at high-speed by switching to a register bank that is not in use. normally, the bank 0 is used for the main task and the banks 1 to 15 are assigned to interrupt service tasks. to increase the efficiency of data memory utilization, the same bank is assigned for interrupt sources which are not nested. the switched bank is automatically restored by executing an interrupt return instruction [reti] or [retn]. therefore, it is not necessary for a program to save the rbs. example: register bank changeover pintxx: interrupt processing reti c? vintxx: dp pintxx db 1 ; rbs rbs + 1 2. general-purpose register save/restore by register bank changeover the general-purpose registers can be saved at high-speed by switching to a register bank that is not in use. normally, the bank 0 is used for the main tank and the banks 1 to 15 are assigned to interrupt service tasks. example: register bank changeover pintxx: ld rbs, n interrupt processing reti ; restores bank and returns c? vintxx: dp pintxx ; interrupt service routine entry address db 0 figure 1.5.4 saving/restori ng general-purpose registers a cceptance of interrupt saving registers restoring registers interrupt service task interrupt return main task (b) saving/restoring using push/ pop or data transfer instructions m a cceptance of interrupt bank m n m m interrupt service task restore to bank m automatically by [reti]/[retn] interrupt return switch to bank n by ld, rbs and n instruction switch to bank n automatically main task (a) saving/restoring by register bank changeover time m
tmp88cs34/cp34 2006-07-06 88cs34-29 3. general-purpose registers save/restore using push and pop instructions to save only a specific register, and when the same interrupt source occurs more than once, the general-purpose registers can be saved/restored using the push/pop instructions. example: register save/restore using push and pop instructions pintxx: push wa ; save wa register pair interrupt processing pop wa ; restore wa register pair reti ; return address (example) sp 0023ah a 0023b sp w sp 0023c pc l pc l pc l 0023d pc h pc h pc h 0023e pc e pc e pc e 0023f psw l psw l psw l 00240 psw h psw h psw h sp 00241 at acceptance of an interrupt at execution of a push instruction at execution of a pop instruction at execution of an interrupt return instruction 4. general-purpose registers save/restore using data transfer instructions data transfer instruction can be used to sa ve only a specific general-purpose register during processing of single interrupt. example: saving/restoring a register using data transfer instructions pintxx: ld (gsava), a ; save a register interrupt processing ld a, (gsava) ; restore a register reti ; return
tmp88cs34/cp34 2006-07-06 88cs34-30 (3) interrupt return the interrupt return instructions [reti] /[retn] perform the following operations. [reti] maskable interrupt return [retn] non-mask able interrupt return 1. the contents of the program counter and the program status word are restored from the stack. 1. the contents of the program counter and program status word are restored from the stack. 2. the stack pointer is incremented 5 times. 2. the stack pointer is incremented 5 times. 3. the interrupt master enable flag is set to ?1?. 3. the interrupt master enable flag is set to ?1? only when a non-maskable interrupt is accepted in interrupt enable status. however, the interrupt master enable flag remains at ?0? when so clear by an interrupt service program. 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. 4. the interrupt nesting counter is decremented, and the interrupt nesting flag is changed. interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next interrupt can be accepted imme diately after the interrupt return instruction is executed. note: when the interrupt processing time is lo nger than the interrupt request generation time, the interrupt service task is performed but not the main task. 1.5.2 software interrupt (intsw) executing the [swi] instruction generates a software interrupt and immediately starts interrupt processing (intsw is highest prioriti zed interrupt). however, if processing of a non-maskable interrupt is already underway, executing the swi instruction will not generate a software interrupt but will result in the same operation as the [nop] instruction. use the [swi] instruction only for detection of the address error or for debugging. 1. address error detection ffh is read if for some cause such as nois e the cpu attempts to fetch an instruction from a non-existent memory address. code ffh is the swi instruction, so a software interrupt is generated and an address erro r is detected. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address-trap reset is generated in case that an instruction is fetched from ram, sfr or dbr areas. 2. debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 1.5.3 external interrupts the tmp88cs34/cp34 each have five external interrupt inputs ( int0 , int2, int3, int4, and int5 ). three of these are equipped with digital noise rejection circuits (pulse inputs of less than a certain time are eliminat ed as noise). edge sele ction is also possible with int2, int3 and int4. the int0 /p50 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise rejection control except int3 pin input and int0 /p50 pin function selection are performed by the external interru pt control register (eintcr). edge selecting and noise rejection control for int3 pin input are preformed by the remote control signal preprocessor control registers. (refer to the section of the remote control signal preprocessor.) when int0en = 0, the il 3 will not be set even if the falling edge of int0 pin input is detected.
tmp88cs34/cp34 2006-07-06 88cs34-31 table 1.5.1 external interrupts source pin secondary function pin enable conditions edge digital noise rejection int0 int0 p50/tc2 imf = 1, int0en = 1, ef 3 = 1 falling edge any pulse shorter than 2/fc [s] is regarded as noise and removed. pulses not shorter than 7/fc [s] are definitely regarded as signals. int2 int2 p53/tc1/ sck1 /ain0/ kwu0 imf ? ef 7 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses equal to or more than 25/fc [s] are regarded as signals. int3 int3 p30/rxin imf ? ef 11 = 1 falling edge, rising edge or falling/rising edge refer to the section of the remote control preprocessor int4 int4 p31/tc3 imf ? ef 12 = 1 falling edge or rising edge pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. int5 int5 p20/ stop imf ? ef 15 = 1 falling edge any pulse shorter than 2/fc [s] is regarded as noise and removed. pulse not shorter than 7/fc [s] are definitely regarded as signals. note 1: the noise rejection function is also affected for timer/counter input (tc1 pin). note 2: if a noiseless signal is input to the external interrupt pin in the normal or idle mode, the maximum time from the edge of input signal until the il is set is as follows: (1) int2, int4 pin 31/fc [s] (2) int3 pin refer to the section of the remote control preprocessor. note 3: if a dual-function pin is used as an output port, changing data or switching between input and output generates a pseudo interrupt request signal. to ignore this signal, it is necessary to reset the interrupt enable flag. note 4: if int0en = ?0?, detecting the falling edge of the int0 pin input does not set the interrupt latch il3.
tmp88cs34/cp34 2006-07-06 88cs34-32 7 6 5 4 3 2 1 0 eintcr (00037h) ?0? int0 en ? int4 es ? int2 es ?0? ? (initial value: 00 * 0 * 00 * ) int0en p50/ int0 pin configuration 0: p50 input/output port 1: int0 pin (port p50 should be set to an input mode) int4es int2es int4 and int2 edge select 0: rising edge 1: falling edge write only note 1: fc: high-frequency clock [hz], * : don?t care note 2: edge detection during switching edge selection is invalid. note 3: do not change eintcr only when imf = 1. after changing eintcr, interrupt latches of external interrupt inputs must be cleared to ?0? using load instruction. note 4: in order to change of external interrupt input by rewriting the contents of int2es and int4es during normal mode, clear interrupt latches of external in terrupt inputs (int2 and int4) after 8 machine cycles from the time of rewriting. note 5: in order to change an edge of timer counter input by rewritng the contents of int2es during normal mode, rewrite the contents after timer counter is stopped (tc * s = 0) , that is, interrupt disable state. then, clear a interrupt latch of external interrupt i nput (int2) after 8 machine cycles from the time of rewriting to change to interrupt enable state. finally, start timer counter. example: when changing tc1 pin inputs edge in exter nal trigger timer mode from rising edge falling edge. ld (tc1cr), 01001000b ; tc1s 00 (stops tc1) di ; imf 0 (disables interrupt service) ld (eintcr), 00000100b ; int2es 1 (change edge selection) nop to nop ld (ill), 01111111b ; il7 0 (clears interrupt latch) ei ; imf 1 (enables interrupt service) ld (tc1cr), 01111000b ; tc1s 11 (starts tc1) figure 1.5.5 external interrupt control register 8-machine cycles
tmp88cs34/cp34 2006-07-06 88cs34-33 1.6 reset circuit the tmp88cs34/cp34 has four types of reset gene ration procedures: an external reset input, an address trap reset output, a watchdog timer reset output and a system clock reset output. table 1.6.1 shows on-chip hardware initialization by reset action. the malfunction reset output circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. the reset pin can output level ?l? at the maximum 24/fc [s] (1.5 s at 16 mhz) when power is turned on. table 1.6.1 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (ffffeh to ffffch) stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l) not initialized prescaler and divider of timing generator 0 register bank selector (rbs) 0 jump status flag (jf) 1 watchdog timer enable zero flag (zf) not initialized carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 output latches of i/o ports refer to i/o port circuitry interrupt individual enable flags (ef) 0 interrupt latches (il) 0 control registers refer to each of control register ? ? ram not initialized 1.6.1 external reset input the reset pin contains a schmitt trigger (hysteresi s) with an internal pull-up resistor. when the reset pin is held at ?l? level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. when the reset pin input goes high, the reset operation is released and the program execution starts at the vector addre ss stored at addresses ffffch to ffffeh. figure 1.6.1 reset circuit sink open drain reset input reset vdd malfunction reset output circuit watchdog timer reset address trap reset system clock reset
tmp88cs34/cp34 2006-07-06 88cs34-34 1.6.2 address-trap-reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram, dbr or the sfr area, address-trap-reset will be generated. then, the reset pin output will go low. the reset time is about 8/fc to 24/fc [s] (0.5 to 1.5 s at 16 mhz). note 1: letter ?a? represents an address in the built-in ram, sfr, or dbr area. if the rom corrective function is enabled, no address trap occurs in a ram area of 002c0h to 06bfh. if the rom corrective function is disabled, an address trap occurs in the following area: 00000h a 00fffh if the rom corrective function is enabled, an address trap occurs in the following area: 00000h a 002bfh or 006c0h a 00fffh note 2: during reset release, reset vector ?r? is read out, and an instruction at address ?r? is fetched and decoded. figure 1.6.2 address-trap-reset 1.6.3 watchdog timer reset refer to section ?2.4 watchdog timer?. 1.6.4 system-clock-reset clearing bits 7 in syscr2 to ?0?, system clock stops and causes the microcomputer to deadlock. this can be prevented by automaticall y generating a reset signal whenever bits 7, 6 and 5 in syscr2 = 000 is detected to continue the oscillation. the reset pin output goes low from high-impedance. the reset time is about 8/fc to 24/fc [s] (0.5 to 1.5 s at 16 mhz). jp a instruction execution reset output reset release instruction at address a ddress-trap is occurred (?l? output) 8/fc to 24/fc [s] 4/fc to 12/fc [s] 20/fc [s] (high-z) (no wait)
tmp88cs34/cp34 2006-07-06 88cs34-35 1.7 rom corrective function the rom corrective function can patch the pa rt (s) of on-chip rom with some bugs. the rom corrective function have two modes. one is to replaced the instruction on a certain address in the rom with the jump instruction to branch into the ram area where the patched codes (program jump mode). the ot her is to replace a byte or a word (2 or 3 bytes) length data in the rom with the patched data (data replacement mode). four independent location can be patched. note 1: when use rom corrective circuit, it is necessary to contain a program which operates to load patched program and/or replacement data from external memory into an internal data ram in an initial routine. note 2: the address of an instruction for idle mode cannot be specificated as start address of corrective area. note 3: the bm88cs34n0a-m15 does not support the rom corrective circuit. use the tmp88ps34 to debug a program of this circuit. example: rom corrective circuit romcdr romcdr serial bus interface ram ? correction mode ? correction code ? patch program
tmp88cs34/cp34 2006-07-06 88cs34-36 1.7.1 configuration figure 1.7.1 rom corrective circuit register selection circuit 23 to 6 5 4 3 2 1 0 the lower the middle the upper compare address register the lower the middle the upper data register bank0 bank1 bank2 bank3 address compare circuit instruction fetch control circuit match signal address bus data bus to to cm 1 cm 0 cm 2 cm 3 cm3-0 wdc romcdr corrective mode signal 5 write data count register write signal rom corrective data register write data count register rom corrective control register
tmp88cs34/cp34 2006-07-06 88cs34-37 1.7.2 control the rom corrective function is controlled by rom corrective control register (romccr) and rom corrective data register (romcdr). rom corrective control register 7 6 5 4 3 2 1 0 romccr (00fe0h) ? ? ? ? cm3 cm2 cm1 cm0 (initial value: **** 0000) cm3 corrective mode setting (bank3) cm2 corrective mode setting (bank2) cm1 corrective mode setting (bank1) cm0 corrective mode setting (bank0) 0: program jump mode 1: data replacement mode r/w rom corrective status register 7 6 5 4 3 2 1 0 romcsr (00fe1h) ? ? ? wdc (initial value: *** 0 0000) wdc write data counter counting the number of the byte written in romcdr read only rom corrective data register 7 6 5 4 3 2 1 0 romcdr (00fe2h) (initial value: 0000 0000) romc rom corrective data register write only figure 1.7.2 rom corrective control register, st atus register and rom corrective data register (1) enable and disable the rom corrective function is disabled after releasing reset. it is enabled after setting the data for one bank into romcdr. and the address-trap-reset is not generated when fetching an instruction from the ram area except the address 02c0h to 06bfh. after the rom corrective function is enabled, it is neccesary to reset the micro controller in order to disable it. (2) data replacement mode the rom corrective function has the program jump mode and the data replacement mode. by setting cmx (x: 0 to 3) in romccr, the data replacement mode is selected. (3) the rom corrective data register writing the rom corrective data register has four banks corresponding to four independent locations to patch. the write data counter (wdc) points each bank set. (figure 1.7.2)
tmp88cs34/cp34 2006-07-06 88cs34-38 rom corrective data register romcdr (00fe2h) romc7 romc6 romc5 romc4 romc3 romc2 romc1 romc0 (initial value: 0000 0000) 00000 (initial value) the lower start address of the corrective area (8 bits) 00001 the middle start address of the corrective area (8 bits) 00010 the upper start address of the corrective area (4 bits) 00011 the lower 8 bit of the jump address/replacement data 00100 the middle 8 bit of the jump address/replacement data 00101 the upper 4 bit of the jump address/replacement data 00110 the lower start address of the corrective area (8 bits) 00111 the middle start address of the corrective area (8 bits) 01000 the upper start address of the corrective area (4 bits) 01001 the lower 8 bit of the jump address/replacement data 01010 the middle 8 bit of the jump address/replacement data 01011 the upper 4 bit of the jump address/replacement data 01100 the lower start address of the corrective area (8 bits) 01101 the middle start address of the corrective area (8 bits) 01110 the upper start address of the corrective area (4 bits) 01111 the lower 8 bit of the jump address/replacement data 10000 the middle 8 bit of the jump address/replacement data 10001 the upper 4 bit of the jump address/replacement data 10010 the lower start address of the corrective area (8 bits) 10011 the middle start address of the corrective area (8 bits) 10100 the upper start address of the corrective area (4 bits) 10101 the lower 8 bit of the jump address/replacement data 10110 the middle 8 bit of the jump address/replacement data 10111 the upper 4 bit of the jump address/replacement data 00000 note 1: wdc value equals to the number of the byte stored in romcdr. note 2: romcdr is set in order of the lower (8 bits), the middle (8 bits) and the upper (4 bits) start address of the corrective area, the lower (8 bits), the middle (8 bi ts) and the upper (4 bits) of the jump address/the replacement data. figure 1.7.3 banks and w dc value of the program corrective data register whenever romcdr is written, wdc is increment ed to indicate what data is writen via romcdr. during reset, wdc is intialized to ?0?. (1) the lower start address of the corrective area (8 bits) (2) the middle start address of the corrective area (8 bits) (3) the upper start address of the corrective area (4 bits) (4) the lower jump address/replacement data (8 bits) (5) the middle jump address/replacement data (8 bits) (6) the upper jump address (4 bits)/replacement data note 1: corrective addresses must hav e over five addresses each other. note 2: the address of an instruction for idle mode cannot be specificated as start address of corrective area. bank 0 bank 1 bank 2 bank 3 the value of wdc after writing a data to romcdr
tmp88cs34/cp34 2006-07-06 88cs34-39 1.7.3 functions the rom corrective function can correct maximum four rom areas with their corresponding four banks of rom corrective re gisters. either program jump mode or data replacement mode is selected for ea ch bank by cm0 to cm3 respectively. (1) program jump mode in the program jump mode, the system executes a jump instruction when the program execution reaches the instruction at the corrective rom address, skips from the instruction which would have been executed, and executes an instruction at a preset jump address. clearing romccr cmx (x: 0 to 3) to ?0? puts the system in the program jump mode. use romcdr to set the corrective rom address and jump address. when the start address of an erroneous progra m is a corrective rom address, and that of the patch program is a jump address, the bug in the erroneous program can be fixed. note that the patch program should end with a jump instruction, which causes a return to the built-in rom. note: for program jump mode, the address to be corrected must be the start address of the instruction. example 1: setting the program correction circuit with the initial routine using the initial routine program, which is executed right after reset, set the program correction circuit's register and stores the patch program into the built-in ram as follows. 1. read the flag, which indicates whether to use the program correction circuit, from the external memory. 2. if that circuit is not used, pe rform normal initial processing. 3. if it is used, clear cmx to 0 to establish the program jump mode. 4. read the corrective rom address and jump address from the external memory. 5. set the corrective rom address and jump address, which were read in step 4., in romcdr. 6. read the number of bytes for the patch program from the external memory. 7. read the program with a number of bytes, eq ual to the byte count read in step 6., from the external memory, and store that program into the built-in ram. 8. repeat steps 4. through 7. as many times as there are required banks. example 2: there is bugs on the locations from 0c020h to 0c085h the corrective address, the jump vector, the program patch codes and other information to patch the rom with the bugs must be read out from any of memory storage that holds them during initial program routine. cmn = 0 specifies the program jump mode. subsequently, the patch program codes are loaded into ram (00400h to 004efh). the start address (0c020h) of the rom necessary to patch is written to the corrective rom address registers, and the start address (00400h) of the ram area to patch is loaded onto the jump address registers. when the instruction at 0c020h is fetched, the instruction to jump into 00400h is unconditionally executed instead of the instruction at 0c020h, and the subsequent patch program codes are executed. the jump instruction at the end of the patch program codes returns to the rom at 0c086h.
tmp88cs34/cp34 2006-07-06 88cs34-40 note: corrective address must be assigned to 1st byte of instruction codes on the program jump mode. (2) data replacement mode in the data replacement mode, the system replaces reference data stored in the rom area with the new instead of correcting the data reference instruction when that reference data is changed. the program jump mode reduces the complexi ty of correcting the processing routine. however, when this mode is used, if there is a need to replace only the fixed data in rom, the instruction to reference this rom data sh ould be corrected. thus, a large amount of rom is required for the patch program. to av oid this, the system has the data replacement mode. with this mode, three consecutive bytes of data can be replaced for each bank. (for an instruction which accesses only one byte, on ly the first byte can be replaced. for an instruction which accesses only two bytes, the two consecutive bytes can be replaced.) setting romccr cmx (x: 0 to 3) to ?1? puts the system in the data replacement mode. specify the start address of rom data to be replaced as the corrective rom address. then, specify the new three-byte data as the patch data. note: for data replacement mode, the correc tive address should be t he address of fixed data (including a vector). (the operati on code and operand cannot be changed.) example 1: setting the program correction circuit with the initial routine using the initial routine program, which is executed right after reset, set the program correction circuit's register as follows. 1. read the flag, which indicates whether to use the program correction circuit, from the external memory. 2. if that circuit is not used, pe rform normal initial processing. 3. if it is used, set cmx to ?1? to establish the data replacement mode. 4. read the address of the data to be replaced and the patch data from the external memory. 5. set the address and patch data, which were read in step 4., in romcdr. 6. repeat steps 4. and 5. as many times as there are required banks. jp 0c086h dbr sfr ram 00000h 0003fh 00040h 006bfh 00f80h 00fffh 04000h fffffh rom bug area 0c020h 0c085h 0c086h patch program return 00400h 004efh 004f0h
tmp88cs34/cp34 2006-07-06 88cs34-41 example 2: repl acing data 55h at 0c020h with 33h using the initial routine program, which is executed right after reset, read the start address of the data to be replaced and the patch data from the external memory. set cmx (x: 0 to 3) to ?1? to change the corre ction mode to the data replacement mode. specify the start address (0c020h) of the data to be replaced as the corrective rom address. then, specify the new three-byte data (33h for 0c020h, cch for 0c021h, and c3h for 0c022h) as the patch data. note 1: corrective address must be assign ed to constant data area on the data replacement mode. (ope-code and ope-rand cannot be replaced by rom correction circuit.) note 2: instructions which includes ?(hl + )? or ?( ? hl) ? operation cannot be replaced by rom corrective circuit on the data replacement mode. dbr sfr ram 00000h 0003fh 00040h 006bfh 00f80h 00fffh 04000h fffffh rom 0c021h 55h aah a5h 0c020h 0c022h cch 33h 3ch replacement data 1. at hl = 0c020h, executing ld a, (hl) l oads 33h in a. (data replacement) 2. at hl = 0c021h, executing ld a, (hl) l oads aah in a. (no data replacement) 3. at hl = 0c020h, executing ld wa, (hl) l oads cc33h in wa. (data replacement) 4. at hl = 0c020h, executing ld ix, (hl) loads ccc33h in ix. (data replacement)
tmp88cs34/cp34 2006-07-06 88cs34-42 2. on-chip peripheral functions 2.1 special function registers (sfr ) and data buffer registers (dbr) the tlcs-870/x series uses the memory mapped i/o system and all peripheral control and data transfers are performed through the specia l function registers (sfr) and data buffer registers (dbr). the sfr are mapped to addresses 00000h to 0003fh, and dbr are mapped to address 00f80h to 00fffh. figure 2.1.1 shows the list of th e tmp88cs34/cp34 sfrs and-dbrs. address read write address read write 00000h reserved 00020h sbisra (sbi status a) sbicra (sbi control register a) 00001 reserved 00021 sbidbr (sbi data buffer) 00002 p2 port 00022 ? i 2 car (i 2 c bus address) 00003 p3 port 00023 sbisrb (sbi status b) sbicrb (sbi control register b) 00004 p4 port 00024 ? ordmal (osd control) 00005 p5 port 00025 ? ordmah (osd control) 00006 p6 port 00026 rcsr (tc3 status) rccr (tc3 control) 00007 p7 port 00027 pmpxcr (port control) 00008 ? p5cr1 (p5 port i/o control1) 00028 ? pwmcr1a (pwm control1a) 00009 ? p7cr (p7 port i/o control) 00029 ? pwmcr1b (pwm control1b) 0000a reserved 0002a ? pwmdbr1 (pwmdbr1) 0000b reserved 0002b ? p3cr1 (p3 i/o control) 0000c ? p4cr (p4 port i/o control) 0002c eire 0000d ? p6cr (p6 port i/o control) 0002d eird 0000e adccra (ad converter control a) 0002e ile 0000f adccrb (ad converter control b) 0002f ild 00010 tc1dral 00030 cgcr (divider control) 00011 tc1drah 00031 adcdr1 (ad conversion result) 00012 tc1drbl ? 00032 adcdr2 (ad conversion result) 00013 tc1drbh ? 00033 reserved 00014 tc1cr (tc1 control) 00034 ? wdtcr1 00015 ? tc2cr (tc2 control) 00035 ? wdtcr2 00016 ? tc2drl 00036 tbtcr (tbt/tg control) 00017 ? tc2drh 00037 ? eintcr (external interrupt control) 00018 tc3dra (timer register 3a) 00038 syscr1 00019 tc3drb (timer register 3b) ? 00039 syscr2 0001a ? tc3cr (tc3 control) 0003a eirl 0001b ? tc4dr (timer register 4) 0003b eirh 0001c ? tc4cr (tc4 control) 0003c ill 0001d ordsn (osd control) 0003d ilh 0001e orcral (osd control) 0003e pswl 0001f orcrah (osd control) 0003f pswh (a) special function registers note 1: do not access reserved areas by the program. note 2: ? : cannot be accessed. note 3: write-only registers and interrupt latches cannot us e the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical op eration instructions such as and, or, etc.). note 4: when defining address 0003fh with assembler symbols, use grbs. address 0003eh must be gpsw/gflag. figure 2.1.1 (a) sfr (timer register 1a) (timer register 1b) (timer register 2) (interrupt enable register) (interrupt latch) watch-dog timer control (system control) (interrupt enable register) (interrupt latch) (program status word)
tmp88cs34/cp34 2006-07-06 88cs34-43 address read write 00f80h ordon (osd control) 81h ? osd control register ? osd control register b9h orirc (osd display counter) or irc (osd interrupt control) ? osd control register ceh ? osd control register cfh reserved d0h idleinv (key-on wake-up status) idlecr (key-on wake-up control) d1h reserved reserved e0h romccr (rom corrective control) e1h romcc (data register count) ? e2h ? romcdr (rom corrective data) e3h reserved e4h jecr (jitter elimination control) e5h jesr (jitter elimination status) ? e6h reserved e7h reserved e8h rxcr1 (remote control receive control) e9h rxcr2 (remote control receive control) eah rxctr (remote control receive counter) ? ebh rxdbr (remote control receive data) ? ech rxsr (remote control receive status) ? edh reserved eeh ? fc8cr (frequency division circuit control) efh reserved f0h sccra (baud rate control a) ? f1h sccrb (baud rate control b) scsr (baud rate status) f2h reserved reserved feh ? pselcr (port3 and 5 output status control) ffh ? dgine (input control) (b) data buffer register note 1: do not access reserved areas by the program. note 2: ? : cannot be accessed. note 3: write-only registers cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). figure 2.1.1 (b) dbr
tmp88cs34/cp34 2006-07-06 88cs34-44 2.2 i/o ports the tmp88cs34/cp34 has 6 parallel input/output ports (33 pins) as follows: primary function secondary functions port p2 1-bit i/o port external interr upt input, and stop mode release signal input port p3 6-bit i/o port external interrupt i nput, remote control signal input, data slicer analog input, timer/counter input, seri al bus interface input/output port p4 8-bit i/o port pulse width modulation output port p5 8-bit i/o port external interrupt input, timer/counter input, key-on wake-up input, serial bus interface input/output, analog input and i output from osd circuitry. port p6 8-bit i/o port r, g, b and y/bl output from osd circuitry, r.g.b and y/bl input, analog input, and key-on wake-up input port p7 2-bit i/o port horizontal synchr onous pulse input and vert ical synchronous pulse input to osd circuitry each output port contains a latch, which holds the output data. all input ports do not have latches, so the external input data should either be held externally until read or reading should be performed several ti mes before processing. figure 2.2.1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing can not be recognized from outside, so that transient input such as chattering must be processed by the program. output data changes in the s2 state of the write cycle during execution of the instruction which writes to an i/o port. note: the positions of the read and write cycl es may vary, dispending on the instruction . figure 2.2.1 input/output timing (example) fetch cycle fetch cycle read cycle s 0 s 1 s 2 s 3 s 0 s 1 s 2 s 3 s 0 s 1 s 2 s 3 ex: ld a, (x) (a) input timing instruction execution cycle input strobe data input fetch cycle fetch cycle write cycle s 0 s 1 s 2 s 3 s 0 s 1 s 2 s 3 s 0 s 1 s 2 s 3 ex: ld (x), a instruction execution cycle output latch p ulse data output (b) output timing
tmp88cs34/cp34 2006-07-06 88cs34-45 when reading an i/o port except programmable i/o ports, whether the pin input data or the output latch contents are read depends on the instructions, as shown below: (1) instructions that read the output latch contents 1. xch r, (src) 2. set/clr/cpl (src).b 3. set/clr/cpl (pp).g 4. ld (src).b, cf 5. ld (pp).b, cf 6. add/addc/sub/subb/and/or/xor (src), n 7. (src) side of add/addc/sub/s ubb/and/or/xor (src), (hl) (2) instructions that read the pin input data 1. instructions other than the above (1) 2. (hl) side of add/addc/sub/s ubb/and/or/xor (src), (hl) 2.2.1 port p2 (p20) port p2 is a 1bit input/output port. it is also used as an external interrupt input, and a stop mode release signal input. when used as an input port, or a secondary function pin, the output latch should be set to ?1?. during reset, the output latch is initialized to ?1?. it is recommended that pin p20 should be used as an external interrupt input, a stop mode release signal input, or an input port. if used as an output port, the interrupt latch is set on the falling edge of the p20 output pulse. when a read instruction for port p2 is executed , bits 7 to 1 in p2 are read in as undefined data. 7 6 5 4 3 2 1 0 p2 (00002h) p20 int5 stop (initial value: **** *** 1) note: * : don?t care figure 2.2.2 port p2 data input set/clr/cpl/others d q stop outen data input control input output latch p20 ( int5 / stop )
tmp88cs34/cp34 2006-07-06 88cs34-46 2.2.2 port p3 (p35 to p30) port p3 is an 6-bit input/output port which can be configured as an input or an output in one-bit unit under software control. input/output mode is specified by the corresponding bit in the port p3 input/output control register 1 (p3cr1). port p3 is configured as an input if its corresponding p3cr1 bit is cleared to ?0?, and as an output if its corresponding p3cr1 bit is set to ?1?. during reset, p3cr1 is initia lized to ?0?, which configures port p3 as an input. the p3 output latches are also initialized to ?1?. data is written into the output latch regardless of the p3cr1 contents. therefore initial output data should be written into the output latch before setting p3cr1. port p3 is also used as an external interrupt input, remote-control signal input a timer/counter input, and serial bus interfac e input/output. when used as a secondary function input pin except i 2 c bus interface input/output, the input pins should be set to the input mode. when used as a secondary function output pin except i 2 c bus interface input/output, the output pins should be set to the output mode and beforehand the output latch should be set to ?1?. when p34 and p35 are used as i 2 c bus interface input/output, p3cr2 bits should be set to the sink open drain mode, the output latches should be set to ?1?, and the output pins should be set to the output mode. note: input mode port is read the state of inpu t pin. when input/output mode is used mixed, the contents of output latch setting input mode may be changed by executing bit manipulation instructions. example 1: outputs an immediate data 5ah to port p3 ld (p3), 5ah ; p3 5ah example 2: inverts the output of the lower 4 bits (p33 to p30) in port p3 xor (p3), 00001111b ; p33 to p30 p33 to 30 p
tmp88cs34/cp34 2006-07-06 88cs34-47 7 6 5 4 3 2 1 0 p3 (00003h) p35 sda0 p34 scl0 p33 tc4 p32 p31 int4 tc3 p30 int3 rxin (initial value: ** 11 1111) 7 6 5 4 3 2 1 0 p3cr1 (0002bh) p35cr1 p34cr1 p33cr1 p32cr1 p31cr1 p30cr1 (initial value: ** 00 0000) p3cr1 i/o control for p3 0: input mode 1: output mode write only 7 6 5 4 3 2 1 0 pselcr (0ffeh) ?0? ?0? p35cr2 p34cr2 ?0? p52cr2 p51cr2 ?0? (initial value: 0 * 00 * 00 * ) p3cr2 i/o control for p3 0: sink open drain 1: tri-state write only ( * 1) only p33, p31, p30 ( * 2) only p33, p32 note 1: * : don?t care, i = 5 to 4, j = 3 to 0 note 2: p3cr1 cannot used the read-modify-write instructions. (bit manipulation instructions such as set, clr, etc. and logical operation such as and, or, etc.) note 3: clear bit 7, 6, 3 and 0 to ?0? in pselcr. figure 2.2.3 port p3 and p3cr data output (b) p33 to p30 d q stop outen output latch p3j vin ( * 2) p3jcr1 data input control input ( * 1) data output (a) p35 to p34 stop outen output latch p3i control output data input control input p3icr2 d q p3jcr1
tmp88cs34/cp34 2006-07-06 88cs34-48 2.2.3 port p4 (p47 to p40) port p4 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. input/output mode is specified by the corresponding bit in the port p4 input/output control register (p4cr). port p4 is configured as an input if its corresponding p4cr bit is cleared to ?0?, an d as an output if its corresponding p4cr bit is set to ?1?. during reset, p4cr is initialized to ?0?, which configures port p4 as an input. the p4 output latches are also initialized to ?1?. data is written into the output latch regardless of the p4cr contents. therefore initial output data should be written into the output latch before setting p4cr. port p4 is also used as a pulse width modulation (pwm) output. when used as a pwm output pin, the output pins should be set to the output mode and beforehand the output latch should be set to ?1?. note: input mode port is read the state of inpu t pin. when input/output mode is used mixed, the contents of output latch setting input mode may be changed by executing bit manipulation instructions. 7 6 5 4 3 2 1 0 p4 (00004h) p47 p46 p45 p44 p43 3 pwm p42 2 pwm p41 1 pwm p40 0 pwm (initial value: 1111 1111) 7 6 5 4 3 2 1 0 p4cr (0000ch) p47cr p46cr p45cr p44cr p43cr p42cr p41cr p40cr (initial value: 0000 0000) p4cr i/o control for port p4 0: input mode 1: output mode write only note 1: i = 7 to 0 note 2: j = 3 to 0 note 3: p4cr cannot be used with the read-modify-write instructions. (bit manipulation instructions such as set, clr, etc. and logical operation such as and, or, etc.) figure 2.2.4 ports p4 and p4cr data output d q stop outen output latch p4i p4icr data input pwmj
tmp88cs34/cp34 2006-07-06 88cs34-49 2.2.4 port p5 (p57 to p50) port p5 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. input/output mode is specified by the corresponding bit in the port p5 input/output control register 1 (p5cr1). port p5 is configured as an input if its corresponding p5cr1 bit is cleared to ?0?, and as an output if its corresponding p5cr1 bit is set to ?1?. during reset, p5cr1 is initia lized to ?0?, which configures port p5 as an input. the p5 output latches are also initialized to ?1?. data is written into the output latch regardless of the p5cr1 contents. therefore initial output data should be written into the output latch before setting p5cr1. port p5 is also used as is also used as ad converter analog input, external interrupt input, timer/counter input, serial bus interface input/output, and an on screen display (osd) output (i signal). when used as a secondary function input pin except i 2 c bus interface input/output, the input pins should be set to the input mode. when used as a secondary function output pin except i 2 c bus interface input/output, the output pins should be set to the output mode and beforehand the output latch should be set to ?1?. when p52 and p51 are used as i 2 c bus interface input/output, p5cr2 bits should be set to the sink open drain mode, the output latches should be se t to ?1?, and the output pins should be set to the output mode. when p57 is used as an osd output pin, the output pin should be set to the output mode and beforehand the port 6 data selection register (pids) should be clear to ?0?. when used as port p5, the port 6 data se lection register (pids) should be set to ?1?. note: input mode port is read the state of inpu t pin. when input/output mode is used mixed, the contents of output latch setting input mode may be changed by executing bit manipulation instructions.
tmp88cs34/cp34 2006-07-06 88cs34-50 7 6 5 4 3 2 1 0 p5 (00005h) p57 i p56 ain3 p55 ain2 p54 ain1 p53 int2 tc1 sck1 ain0 p52 so1 sda1 p51 sl1 scl1 p50 int0 tc2 (initial value: 1111 1111) 7 6 5 4 3 2 1 0 p5cr1 (00008h) p57cr1 p56cr1 p55cr1 p54cr1 p53cr1 p52cr1 p51cr1 p50cr1 (initial value: 0000 0000) p5cr1 i/o control for p5 0: input mode 1: output mode write only 7 6 5 4 3 2 1 0 pselcr (00ffeh) ?0? ?0? p35cr2 p34cr2 ?0? p52 cr2 p51cr2 (initial value: 0 * 00 * 00 * ) p5cr2 i/o control for p5 0: sink open drain 1: tri-state write only figure 2.2.5 ports p5 (1/2) data input data output (b) p56 to p54 analog input output latch p5j ainds sain p5jcr1 stop outen d q dginex data output (a) p57 stop outen output latch p5i pids p5icr1 data input i d q b y a s (e) p50 data output stop outen output latch p5m p5mcr1 data input d q control output control input (c) p53 data input data output output latch p5k ainds sain p5kcr1 stop outen d q control output control input analog input dginex (d) p52 to p51 data output stop outen output latch p5l p5lcr1 data input d q control output control input p5lcr2
tmp88cs34/cp34 2006-07-06 88cs34-51 7 6 5 4 3 2 1 0 orp6s (00fbah) p67s p66s p65s p64s pids yblcs mpxs (initial value: 0000 0000) pids selection of the output data for port p57 0: the osd output (i) 1: port p57 output latch write only 7 6 5 4 3 2 1 0 dgine (00fffh) ? ? dgine5 dgine4 dgine3 dgine2 dg ine1 dgine0 (initial value: ** 11 1111) dgine0 0: p53 port input/tc1 input/s10 input/int2 input disable 1: p53 port input/tc1 input/s10 input/int2 input enable dgine1 0: p54 port input disable 1: p54 port input enable dgine2 0: p55 port input disable 1: p55 port input enable dgine3 input control register 0: p56 port input disable 1: p56 port input enable write only note 1: * : don?t care, i = 7, j = 6 to 4, k = 3, l = 2 to 1, m = 0 note 2: p5cr1 cannot be used with the read-modify-write instructions. (bit manipulation instructions such as set, clr, etc. and logical operation such as and, or, etc.) note 3: clear bit 7, 6 and 3 to ?0? in pselcr. figure 2.2.6 ports p5 (2/2) 2.2.5 port p6 (p67 to p60) port p6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. input/outp ut mode is selected by the corresponding bit in the port p6 input/output control register (p6cr). port p6 is configured as an input if its corresponding p6cr bit is cleared to ?0?, and as an output if its corresponding p6cr bit is set to ?1? and p6ns bit is set to ?1?. p63 to p60 are sink open drain ports. during reset, p6cr is initialized to ?0?, which configures port p6 as an input. the p6 output latches are also initialized to ?1?. data is written into the output latch regardless of the p6cr contents. therefore initial output data should be written into the output latch before setting p6cr. port p6 is used as an on screen display (osd) output (r, g, b, and y/bl signal)/input (rin, gin bin, y/blin signal), a test video si gnal output and ad converter analog input. when used as a secondary function input, the input pins should be set to the input mode. when used as an osd output pin, the output pins should be set to the output mode and beforehand the port p6 data selection register (p67s to p64s) should be clear to ?0?. when used as port p6, the signal control register (p67 to p64) should be set to ?1?. note1: input mode port is read the state of in put pin. when input/output mode is used mixed, the contents of output latch setting input mode may be changed by executing bit manipulation instructions. note2: p63 to p61 output ?0? after a reset. when these dual-function pins are used as ports, be sure to set orp6s2 to ?1? example: sets the lower 4 bits (p63 to p60) in port p6 to the output mode, and the other bit to the input mode. ld (p6cr), 0fh ; p6cr 00001111b
tmp88cs34/cp34 2006-07-06 88cs34-52 7 6 5 4 3 2 1 0 p6 (00006h) p67 y/bl p66 b p65 g p64 r p63 rin p62 gin p61 bin ain5 p60 y/blin ain4 (initial value: 1111 1111) 7 6 5 4 3 2 1 0 p6cr (0000dh) p67cr p66cr p65cr p64cr p63cr p62cr p61cr p60cr (initial value: 0000 0000) p6cr i/o control for port p6 0: input mode 1: output mode write only 7 6 5 4 3 2 1 0 orp6s (00fbah) p67s p66s p65s p64s pids yblcs mpxs (initial value: 0000 0000) p67s to p64s selection of the output data for port p6i 0: the osd output (r, g, b, y/bl) 1: port p6i output latch write only 7 6 5 4 3 2 1 0 dgine (00fffh) ? ? dgine5 dgine4 dgine3 dgine2 dg ine1 dgine0 (initial value: ** 11 1111) dgine4 0: p60 port input/yin/blin disable 1: p60 port input/yin/blin enable dgine5 input control register 0: p61 port input/bin disable 1: p61 port input/bin enable write only 7 6 5 4 3 2 1 0 orp6s2 (00fa1h) ? ? ? ? fixed at 1 fixed at 1 fixed at 1 ? (initial value: **** 000 * ) be sure to fix these bits to ?1?, using the initial routine. write only note 1: * : don?t care, i = 7 to 4, j = 1 to 0 note 2: p6cr and orp6s cannot be used with the read-modify-w rite instructions. (bit manipulations such as set, clr, etc. and logical operation such as and, or, etc.) note3: p63 to p61 output ?0? after a reset. when these dual-function pins are used as port, be sure to set orp6s2 to ?1?. figure 2.2.7 ports p6, p6cr, and p67s to p64s data output (a) p67 to p64 stop outen output latch p6i p6is p6icr data input r, g, b, y/bl a y b s (b) p63 to p62 data output stop outen output latch p6j p6jcr data input d q rin, gin data input data output (c) p61 to p60 analog input output latch p6k ainds sain p6kcr stop outen d q dginex bin, y/blin d q
tmp88cs34/cp34 2006-07-06 88cs34-53 2.2.6 port p7 (p71 to p70) port p7 is a 2bit input/output port, and is also used as a vertical synchronous signal ( vd ) input and a horizontal synchronous signal ( hd ) input for the on screen display (osd) circuitry. the output latches, are initialized to ?1? during reset. when used as an input port or a secondary function pin, the output latch should be set to ?1?. when a read instruction for port p7 is executed , bits 7 to 2 in p7 are read in as undefined data. 7 6 5 4 3 2 1 0 p7 (00007h) p71 vd p70 hd (initial value: **** ** 11) 7 6 5 4 3 2 1 0 p7cr (00009h) p71cr p70cr (initial value: **** ** 00) p7cr i/o control for p7 0: input mode 1: output mode write only note 1: i = 1 to 0, * : don?t care figure 2.2.8 ports p7 data output stop outen output latch p7i p7icr data input d q hd , vd
tmp88cs34/cp34 2006-07-06 88cs34-54 2.3 time base timer (tbt) the time base timer generates time base for key scanning, dynamic displa ying, etc. it also provides a time base timer interrupt (inttbt). the time base timer is controlled by a control register (tbtcr) shown in figure 2.3.1. an inttbt is generated on the first rising edge of source clock (the divider output of the timing generator) after the time base timer has b een enabled. the divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period. the interrupt frequency (tbtck) must be selected with the time base timer disabled (when the time base timer is changed from enabling to disabling, the interrupt frequency can?t be changed.) both frequency selection and enabling can be performe d simultaneously. example: sets the time base timer frequency to fc/2 16 [hz] and enables an inttbt interrupt. ld (tbtcr) , 00000010b ; tb tck="010" ld (tbtcr) , 00001010b ; tbten="1" set (eirl). 6 figure 2.3.1 time base timer (b) time base timer interrupt source clock tbten inttbt enable tbt interrupt period (a) configuration a b c d e f g h tbtcr tbtck 3 tbten time base timer control register source clock rising edge detector inttbt interrupt request fc/2 23 , fc/2 24 fc/2 21 , fc/2 22 fc/2 16 , fc/2 17 fc/2 14 , fc/2 15 fc/2 13 , fc/2 14 fc/2 12 , fc/2 13 fc/2 11 , fc/2 12 fc/2 9 , fc/2 10 s y mpx
tmp88cs34/cp34 2006-07-06 88cs34-55 7 6 5 4 3 2 1 0 tbtcr (00036h) ?0? ? ? ?0? tbten tbtck (initial value: 0 ** 0 0 *** ) tbten time base timer enable/disable 0: disable 1: enable normal, idle mode dv1ck = 0 dv1ck = 1 000 fc/2 23 [hz] fc/2 24 [hz] 001 fc/2 21 fc/2 22 010 fc/2 16 fc/2 17 011 fc/2 14 fc/2 15 100 fc/2 13 fc/2 14 101 fc/2 12 fc/2 13 110 fc/2 11 fc/2 12 tbtck time base timer interrupt frequency select 111 fc/2 9 fc/2 10 write only note 1: fc: high-frequency clock [hz], * : don?t care note 2: tbtcr is a write-only register and must not be used with any of read-modify-write instructions. note 3: set bit 7 and 4 in tbtcr to ?0?. figure 2.3.2 time base timer and divider output control register table 2.3.1 time base timer interrupt frequency (example: at fc = 16mhz) time base timer interrupt frequency [hz] normal, idle mode tbtck dv1ck = 0 dv1ck = 1 000 1.90 0.95 001 7.62 3.81 010 244.14 122.07 011 976.56 488.28 100 1953.12 976.56 101 3906.25 1953.12 110 7812.50 3906.25 111 31250 15625
tmp88cs34/cp34 2006-07-06 88cs34-56 2.4 watchdog timer (wdt) the watchdog timer is a fail-safe system to rapidly detect the cpu malfunctions such as endless looping caused by noise or the like, or deadlock and resume the cpu to the normal state. the watchdog timer signal for detecting malfunction can be selected either a reset output or a pseudo non-maskable interrupt request. however, se lection is possible only once after reset. at first the reset output is selected. when the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an inte rrupt at fixed intervals. 2.4.1 watchdog timer configuration figure 2.4.1 watchdog timer configuration 2.4.2 watchdog timer control figure 2.4.2 shows the watchdog timer co ntrol registers (wdt cr1, wdtcr2). the watchdog timer is automati cally enabled after reset. (1) malfunction detection methods using the watchdog timer the cpu malfunction is detected at follows. 1. setting the detection time, selecting ou tput, and clearing the binary counter. 2. repeatedly clearing the binary count er within the setting detection time. note: the watchdog timer consists of an internal divider and two-stage binary counter. writing the clear code (4eh) clears the bina ry counter, but not the internal divider. the minimum overflow time for the binar y counter might be three quarters of the wdtcr1 (wdtt) time setting depending on when the clear code (4eh) is written into the wdtcr2 register. so, write the clear code on a cycle which is shorter than that minimum overflow time. fc/2 23 , fc/2 24 fc/2 21 , fc/2 22 fc/2 19 , fc/2 20 fc/2 17 , fc/2 18 binary counters clock clear 12 overflow 2 wdt output reset release signal from t.g. reset output internal reset wdtt wdten q s r interrupt request reset intwdt r s q writing disable code writing clear code wdtout controller wdtcr1 00034h wdtcr2 00035h watchdog timer control registers mpx a b c d y s mpx: multiplexe r
tmp88cs34/cp34 2006-07-06 88cs34-57 if the cpu malfunctions such as endless lo oping or deadlock occur for any cause, the watchdog timer output will become active at the rising of an overflow from the binary counters unless the binary counters are cleared. at this time, when wdtout = 1 a reset is generated, which drivers the reset pin low to reset the internal hardware and the external circuit. when wdtout = 0, a watchdog timer interrupt (intwdt) is generated. the watchdog timer temporarily stops counting in stop mode including warm-up or idle mode, and automatically restarts (continues counting) when the stop/idle mode is released.
tmp88cs34/cp34 2006-07-06 88cs34-58 example: sets the watchdog timer detection time to 2 21 /fc [s] and resets the cpu malfunction. ld (wdtcr2), 4eh ; clears the binary counters ld (wdtcr1), 00001101b ; wdtt 10, wdtout 1 ld (wdtcr2), 4eh ; clears the binary counters (always clear immediately before and after changing wdtt) ld (wdtcr2), 4eh ; clears the binary counters ld (wdtcr2), 4eh ; clears the binary counters watchdog timer register 1 7 6 5 4 3 2 1 0 wdtcr1 (00034h) wdten wdtt wdtout (initial value: **** 1001) wdten watchdog timer enable/disable 0: disable (it is necessary to write the disable code to wdtcr2) 1: enable normal mode dv1ck = 0 dv1ck = 1 00 2 25 /fc 2 26 /fc 01 2 23 /fc 2 24 /fc 10 2 21 /fc 2 22 /fc wdtt watchdog timer detection time [s] 11 2 19 /fc 2 20 /fc wdtout watchdog timer output select 0: interrupt request 1: reset output write only note 1: wdtout cannot be set to ?1? by program after clearing wdtout to ?0?. note 2: fc: high-frequency clock [hz], * : don?t care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. note 4: the watchdog timer must be disabled or the coun ter must be cleared immediately before entering to the stop mode. when the counter is cleared, the counter must be cleared again immediately after releasing the stop mode. note 5: just right before disabling the watchdog timer, disable the acceptance of interrupts (di) and clear the watchdog timer. if the watchdog timer is disabled under conditions other than the abov e, the proper operation cannot be guaranteed. watchdog timer register 2 7 6 5 4 3 2 1 0 wdtcr2 (00035h) (initial value: **** **** ) wdtcr2 watchdog timer control code write register 4eh: watchdog timer binary c ounter clear (clear code) b1h: watchdog timer di sable (disable code) others: invalid write only note 1: the disable code is in valid unless written when wdten = 0. note 2: * : don?t care note 3: the binary counter of the watchdog timer must not be cleared by the interrupt task. note 4: clears the binary counter does not clear the source clock. it is recommended that the time to clear is set to 3/4 of the detecting time. note 5: the watchdog timer counter must be disabled by writing the disable code (b1h) to wdrcr2 after writing wdtcr2 to. ?4eh?. figure 2.4.2 watchdog ti mer control registers within 3/4 of wdt detection time within 3/4 of wdt detection time
tmp88cs34/cp34 2006-07-06 88cs34-59 (2) watchdog timer enable the watchdog timer is enabled by setting wdten (bit 3 in wdtcr1) to ?1?. wdten is initialized to ?1? during reset, so the watchd og timer operates immediately after reset is released. example: disables watchdog timer ldw (wdtcr1), 00001000b ; wdten 1 (3) watchdog timer disable to disable the watchdog timer, clear the interrupt mask enable flag (imf) to ?0? and write the clear code (4eh) into wdtcr2. then, clear wdten (bit 3 in wdtcr1) to ?0?. when wdten is ?0?, the watchdog timer is disabled by writing the disable code (b1h) into wdtcr2. if wdten is cleared to ?0? after the disable code has been written into wdtcr2, the watchdog timer is not disabled. while it is disabled, its binary counter is cleared. example: di ; disables interrupt acceptance. ld (wdtcr2), 4eh ; clears the watchdog timer. ldw (wdtcr1), b101h ; disables the watchdog timer. ei ; enables interrupt acceptance. table 2.4.1 watchdog timer detection time (example: fc = 16 mhz) watchdog timer detection time [s] normal mode wdtt dv1ck = 0 dv1ck = 1 00 2.097 4.194 01 524.288 m 1.048 10 131.072 m 262.1 m 11 32.768 m 65.5 m 2.4.3 watchdog timer interrupt (intwdt) this is a pseudo non-maskable interrupt which can be accepted regardless of the contents of the eir. if a watchdog timer in terrupt or a software interrupt is already accepted, however, the new watchdog timer interrupt waits until the previous interrupt processing is completed (the end of the [retn] instruction execution). the stack pointer (sp) should be initialized before using the watchdog timer output as an interrupt source with wdtout. example: watchdog timer interrupt setting up ld sp, 023fh ; sets the stack pointer ld (wdtcr1), 00001000b ; wdtout 0 2.4.4 watchdog timer reset if the watchdog timer output becomes active , a reset is generated, which drivers the reset pin (sink open drain input/output with pull-up) low to reset the internal hardware. the reset output time is about 8/fc to 24/fc [s] (0.5 to 1.5 s at fc = 16.0 mhz). note: if there is any fluctuation in the oscillation frequency at the start of clock oscillation, the reset time includes error. thus, regard the reset time as an approximate value.
tmp88cs34/cp34 2006-07-06 88cs34-60 figure 2.4.3 watchdog timer interrupt/reset clock binary counter overflow intwdt interrupt wdt reset output 1 2 3 0 1 2 3 0 (wdtt = 11b) (?l? output) (high-z) writes 4eh to wdtcr2 2 17 /fc 2 19 /fc [s]
tmp88cs34/cp34 2006-07-06 88cs34-61 2.5 16-bit timer/counter1 (tc1a) 2.5.1 configuration note: be sure to set the function of input/output pins correctl y. for details, see the section on i/o port control registers. figure 2.5.1 timer/counter 1 pulse width measurement mode timer/counter 1 control register capture tc1drb 16-bit timer re g iste r s 1a , 1b fc/2 11 , fc/2 12 fc/2 7 or fc/2 8 fc/2 3 or fc/2 4 2 tc1ck tc1cr tc1dra match cmp 16-bit up-counter s a b y mpx ext. trigge r ext. trigge r start decoder 2 tc1s mcap1 set q clea r rising falling mett1 b a s edge detector clock s y a b int2es inttc1 interrupt scap1 pulse width measurement mode cmp: comparato r mpx: multiplexe r clear y mpx mpx mpx command start tc1 pin window mode d a b y c s
tmp88cs34/cp34 2006-07-06 88cs34-62 2.5.2 control the timer/counter 1 is controlled by a time r/counter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc1dra (00010, 00011h) tc1drah (00011h) tc1dral (00010h) read/write tc1drb (00012, 00013h) tc1drbh (00013h) tc1drbl (00012h) read only 7 6 5 4 3 2 1 0 tc1cr (00014h) ?0? acpap1 mcap1 mett1 tc1s tc1ck tc1m read/write (initial value: 0000 0000) tc1m tc1 operating mode select 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: reserved normal, idle mode dv7ck = 0, dvck = 00 dv1ck = 0 dv1ck = 1 00 fc/2 11 fs/2 12 01 fc/2 7 fc/2 8 10 fc/2 3 fc/2 4 tc1ck tc1 source clock select [hz] 11 external clock (tc1 pin input) timer extend event window pulse ppg 00: stop and counter clear 01: command start 10: external trigger start at the rising edge tc1s tc1 start control 11: external trigger start at the falling edge acap1 auto capture control 0: auto-capture disable 1: auto-capture enable mcap1 pulse width measurement mode control 0: double edge capture 1: single edge capture mett1 external trigger timer mode control 0: trigger start 1: trigger start and stop r/w note 1: fc: high-frequency clock [hz] note 2: the timer register consists of tw o shift registers. a value set in the timer register is put in effect at the rising edge of the first source clock pulse that occurs after the upper data (tc1drah) are written. therefore, the lower byte must be written before the upper byte (it is recommended that a 16-bit access instruction be used in writing). writing only the lower data (tc1dral) does not put the setting of the timer register in effect. note 3: set the mode, source clock ppg control and timer f/f control when tc1 stops (tc1s = 00). note 4: auto-capture can be used in only timer, event counter, and window modes. note 5: values to be loaded to timer registers must satisfy the following condition. tc1dra > tc1drb, tc1dra > 1 note 6: always write ?0? to tff1 except ppg output mode. note 7: on entering stop mode, the tc1 start control (tc1 s) is cleared to ?00? automatically. so, the timer stops. once the stop mode has been released, to star t using the timer counter, set tc1s again. note 8: in the auto-capture function, when the capture va lue is read after stop and clear counter or auto-capture disable is executed by the tc1 start control (tc1s) , the correct capture value might not be able to be read.when using auto-capture function, set capture to enable. figure 2.5.2 timer register s and tc1 control register
tmp88cs34/cp34 2006-07-06 88cs34-63 2.5.3 function timer/counter 1 has five operat ing modes: timer, external tr igger timer, event counter, window, pulse width measurement. (1) timer mode in this mode, counting up is performed using the internal clock. the contents of tc1dra are compared with the contents of up-counter. if a match is found, an inttc1 interrupt is generated, and the counter is cleared to ?0?. counting up resumes after the counter is cleared. the current contents of up-counter can be transferred to tc1drb by setting acap1 (bit 6 in tc1cr) to ?1? (software capture function). (auto-capture function) table 2.5.1 source clock (internal cloc k) for timer/counter 1 (example: at fc = 16.0 mhz) normal, idle mode dv1ck = 0 dv1ck = 1 tc1ck resolution [ s] maximum time setting [s] resolution [ s] maximum time setting [s] 00 128.0 8.39 256.0 16.78 01 8.0 0.524 16.0 1.049 10 0.5 32.77 m 1.0 65.54 m example 1: sets the timer mode with source clock fc/2 11 [hz] and generates an interrupt 1 later (at fc = 16 mhz) ldw (tc1dra), 1e84h ; sets the timer register (1 s 2 11 /fc = 1e84h) di set (eirl). 4 ; enable inttc1 ei ld (tc1cr), 00000000b ; selects the source clock and mode ld (tc1cr), 00010000b ; starts tc1 example 2: auto-capture ld (tc1cr), 01010000b ; acap1 1 (capture) ld wa, (tc1drb) ; reads the capture value
tmp88cs34/cp34 2006-07-06 88cs34-64 figure 2.5.3 timer mode timing chart (2) external trigger timer mode in this mode, counting up is started by an exte rnal trigger. this trigger is the edge of the tc1 pin input. either the rising or falling edge can be selected with tc1s. source clock is an internal clock. the contents of tc1dra is co mpared with the contents of up-counter. if a match is found, an inttc1 interrupt is generated, and the counter is cleared to ?0? and halted. the counter is restarted by the selected edge of the tc1 pin input. when mett1 (bit 6 in tc1cr) is ?1?, inputting the edge to the reverse direction of the trigger edge to start counting clears the co unter, and the counter is stopped. inputting a constant pulse width can generate interrupts. when mett1 is ?0?, the reverse directive edge input is ignored. the tc1 pin input edge before a match detection is also ignored. the tc1 pin input has the noise rejection; therefore, pulses of 7/fc [s] or less are rejected as noise. a pulse width of 13/fc [s] or more is required for edge detection in normal or idle mode. example 1: detects rising edge in tc1 pin input and generates an interrupt 100 s later. (at fc = 16.0 mhz, dv1ck = 1) ldw (tc1dra), 0064h ; 100 s 2 4 /fc = 64h di set (eirl). 4 ; inttc1 interrupt enable ei ld (tc1cr), 00001000b ; selects the source clock and mode ld (tc1cr), 00101000b ; tc1 external trigger start, mett1 = 0 example 2: generates an interrupt, inputting ?l? level pulse (pulse width: 4 ms or more) to the tc1 pin. (at fc = 16.0 mhz, dv1ck = 1) ldw (tc1dra), 00fah ; 4 ms 2 8 /fc = fah di set (eirl). 4 ; inttc1 interrupt enable ei ld (tc1cr), 00000100b ; selects the source clock and mode ld (tc1cr), 01110100b ; tc1 external trigger start, mett1 = 1 (a) timer mode m ? 1m m ? 2 up-counter tc1drb a cap1 capture m + 1m + 2 (b) auto-capture n ? 1nn + 1 capture source clock tc1dra inttc1 interrupt count start 1 source clock up-counter 12 0 ? n n ? 1n 0 match detect counter clear 2 3 4 3 4 5 6 7 mm + 1 m ? 1 m + 2n ? 1n n + 1 ?
tmp88cs34/cp34 2006-07-06 88cs34-65 figure 2.5.4 external trigger timer mode timing chart (3) event counter mode in this mode, events are counted at the edge of the tc1 pin input and bit 4 or 5 in tc1cr. either the rising or falling edge can be selected with the external trigger. the contents of tc1dra are compared with the contents of up-counter. if a match is found, an inttc1 interrupt is generated, and the counter is cleared. match detect is executed on other edge of count-up. a match can not be detected and inttc1 is not generated when the pulse is still in same state. setting acap1 to ?1? transfers the current contents of up-counter to tc1drb (auto-capture function). figure 2.5.5 event counter mode timing chart inttc1 interrupt up-counter tc1 pin input tc1dra tc1s = 10 at the falling edge 1 2 n ? 1 2 count start 0 match detect counter clea r n 0 1 ? n internal clock (a) trigger start (mett1 = 0) tc1 pin input (b) trigger start and stop (mett1 = 1) note: m < n tc1dra inttc1 interrupt count start 1 up-counter 0 n n ? 1 n 0 match detect counter clear 1 tc1s = 10 at the rising edge internal clock tc1 pin input tc1dra inttc1 interrupt count start 1 up-counter 0 n m ? 1 m 0 match detect counter clear tc1s = 10 at the rising edge 2 3 4 2 3 2 3 1 n ? 1 n 2 3 0 count start count clear count start
tmp88cs34/cp34 2006-07-06 88cs34-66 table 2.5.2 input pulse width for timer/counter 1 minimum pulse width [s] normal/idle ?h? width 2 3 /fc ?l? width 2 3 /fc (4) window mode counting up is performed on the rising edge of the pulse that is the logical and-ed product of the tc1 pin input (window pulse) and an internal clock. the contents of tc1dra are compared with the contents of up-counter. if a match is found, an inttc1 interrupt is generated, and the counter is cleare d. positive or negative logic for the tc1 pin input can be selected with bit4 or 5 in tc1cr. it is necessary that the maximum applied fr equency be such that the counter value can be analyzed by the program. that is; the freq uency must be considerably slower than the selected internal clock. figure 2.5.6 window mode timing chart (5) pulse width measurement mode in this mode, counting is started by the extern al trigger (set to exte rnal trigger start by tc1cr). the trigger can be selected either the rising or falling edge of the tc1 pin input. the source clock is used an internal clock. on the next falling (rising) edge, the counter contents are transferred to tc1drb and an in ttc1 interrupt is generated. the counter is cleared when the single edge capture mode is set. when double edge capture is set, the counter continues and, at the next rising (fa lling) edge, the counter contents are again transferred to tc1drb. if a falling (rising) edge capture value is required, it is necessary to read out tc1drb contents until a rising (falling) edge is detected. falling or rising edge is selected with the external trigger tc1s (bit4 or 5 in tc1cr), and single edge or double edge is selected with mcap1 (bit 6 in tc1cr). 1 2 3 4 1 2 3 7 0 ? 7 match detect counter clear (a) positive logic (at tc1s = 10) command start count start count stop count start 56 0 1 2 3 4 7 8 9 tc1dra inttc1 interrupt internal clock up-counter 0 ? 9 match detect counter clear (b) negative logic (at tc1s = 11) command start count start tc1 pin input count stop count start 5 6 0 1 tc1dra inttc1interrupt internal clock up-counter tc1 pin input
tmp88cs34/cp34 2006-07-06 88cs34-67 note 1: be sure to read the captured val ue from tc1drb before the next trigger edge is detected. if fail to read it, it becomes undef ined. it is recommended that a 16-bit access instruction be used to read from tc1drb. note 2: if either the falling or rising edge is us ed in capturing values, the counter stops at ?1? after a value has been captured until the next edge is detected. so, the value captured next will become ?1? larger than the value captured right after capturing starts. note 3: in the pulse width measurement mode, the capture value of the first time after the timer starts might not be a correct value. t hus, execute the dummy read once. example: duty measurement (resolution fc/2 7 [hz] dv1ck = 0) clr (inttc1sw). 0 ; inttc1 service switch initial setting: clears bit 0 of inttc1sw. this bit is inverted by cpl instruction before inttc1 is generated. ld (tc1cr), 00000110b ; sets the tc1 mode and source clock di set (eirl). 4 ; enables inttc1 ei ld . . . (tc1cr), 00100110b ; starts tc1 with an external trigger at mcap1 = 0 . . . pinttc1: cpl (inttc1sw). 0 ; complements inttc1 service switch jrs f, sinttc1 ld wa, (tc1drbl) ; reads tc1drb (?h? level pulse width) lower address in tc1drbl: tc1drb ld (hpulse), wa reti sinttc1: ld ld wa, (tc1drbl) (width), wa ; reads tc1drb (period) . . . reti ; duty calculation . . . vinttc1: dw pinttc1 ; sets inttc1 hpulse width tc1 pin inttc1 inttc1sw
tmp88cs34/cp34 2006-07-06 88cs34-68 figure 2.5.7 pulse width measurement mode timing chart 1 0 m m ? 1 4 3 2 1 0 n n ? 1 4 3 2 1 0 capture capture n m internal clock up-counte r tc1drb tc1 pin input count start count start trigger (a) single edge capture (mcap1 = 1) inttc1 interrupt [application] high or low pulse width measurement n? ? 1 3 2 1 n n ? 1 4 3 2 1 0 capture capture n n? internal clock up-counte r tc1drb tc1 pin input count start count start (b) double edge capture (mcap1 = 0) inttc1 interrupt [application] (1) period/frequency measurement (2) duty measurement n + 1 n + 2 0 m ? 1 m n? n? + 1 n? + 2 m capture
tmp88cs34/cp34 2006-07-06 88cs34-69 2.6 16-bit timer/counter 2 (tc2a) 2.6.1 configuration note: propagation of control input/output requires the correct i/o port setting. for details, see the section on i/o ports. figure 2.6.1 timer/counter 2 (tc2) tc2s tc2m source clock timer/ event counter window fc/2 23 or fc/2 24 fc/2 13 or fc/2 14 fc/2 8 or fc/2 9 fc/2 3 or fc/2 4 tc2 pin clear 16-bit timer register 2 tc2 control register tc2s tc2ck inttc2 interrupt 16-bit up-counter 3 s tc2dr tc2cr h a b c y d s b a y mpx: multiplexer cmp: comparator cmp port (note)
tmp88cs34/cp34 2006-07-06 88cs34-70 2.6.2 control the timer/counter 2 is controlled by a time r/counter 2 control register (tc2cr) and a 16-bit timer register 2 (tc2dr). reset does not affect tc2dr. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc2drh (00017h) tc2drl (00016h) tc2dr (00016, 00017h) read/write 7 6 5 4 3 2 1 0 tc2cr (00015h) tc2s tc2ck tc2m (initial value: ** 00 00 * 0) tc2m tc2 operating mode select 0: timer/event counter mode 1: window mode normal1/2, idle1/2 mode dv1ck = 0 dv1ck = 1 000 fc/2 23 fc/2 24 001 fc/2 13 fc/2 14 010 fc/2 8 fc/2 9 011 fc/2 3 fc/2 4 100 reserved reserved 101 reserved reserved 110 reserved tc2ck tc2 source clock select [hz] 111 external clock (tc2 pin input) tc2s tc2 start control 0: stop and counter clear 1: start write only note 1: fc: high-frequency clock [hz], * : don?t care note 2: writing to the lower byte of timer register 2 (tc2drl), the comparison is inhibited until the upper byte (tc2drh) is written. after writing to the upper by te, any match during 1 machine cycle (instruction execution cycle) is ignored. note 3: set the mode and source clock when the tc2 stops (tc2s = 0). note 4: values to be loaded to timer register must satisfy the following condition. tc2dr > 1 note 5: tc2cr are write-only registers and must not be used with any of the read-modify-write instructions. note 6: when stop mode is started, timer counter is stopped and cleared. set tc2s to ?1? after stop mode is released for restarting timer counter. figure 2.6.2 timer register 2 and tc2 control register
tmp88cs34/cp34 2006-07-06 88cs34-71 2.6.3 function the timer/counter 2 has three operating modes: timer, event counter and window modes. (1) timer mode in this mode, the internal clock is used for counting up. the contents of tc2dr are compared with the contents of up-counter. if a match is found, a timer/counter 2 interrupt (inttc2) is generated, and the counter is cleared. counting up is resumed after the counter is cleared. table 2.6.1 source clock (internal clock) for timer/counter 2 (at fc = 16.0 mhz) normal, idle mode dv1ck = 0 dv1ck = 1 tc2ck resolution maximum time setting resolution maximum time setting 000 524.3 [ms] 9.54 [h] 1.05 [s] 19.1 [h] 001 512.0 [ s] 33.6 [s] 1.02 [ms] 1.12 [min] 010 16.0 [ s] 1.05 [s] 32.0 [ s] 2.09 [s] 011 0.5 [ s] 32.8 [ms] 1.0 [ s] 65.5 [ms] 100 reserved reserved reserved reserved 101 reserved reserved reserved reserved example: sets the source clock fc/2 4 [hz] and generates an interrupt event 25 ms (at fc = 16 mhz, dv1ck = 1) ldw (tc2dr), 61a8h ; sets tc2dr (25 ms 2 4 /fc = 61a8h) di set (eirh).6 ; enab le inttc2 interrupt ei ld (tc2cr), 00001100b ; selects tc2 source clock ld (tc2cr), 00101100b ; starts tc2 figure 2.6.3 timer mode timing chart timer register inttc2 interrupt source clock up-counter n 1 2 1 2 3 n 0 match detect counter clear n ? 1 0 3 4 count start
tmp88cs34/cp34 2006-07-06 88cs34-72 (2) event counter mode in this mode, events are counted on the rising edge of the tc2 pin input. the contents of tc2dr are compared with the contents of the up-counter. if a match is found, an inttc2 interrupt is generated, and the counter is cl eared. the minimum pulse width to the tc2 pin is shown in table 2.6.2. two or more machine cycles are required for both the ?h? and ?l? levels of the pulse width. match detect is executed on the falling edge of the tc2 pin. a match can not be detected and inttc2 is not generated when the pulse is still in a falling state. example: sets the event counter mode an d generates an inttc2 interrupt 640 counts later. ldw (tc2dr), 640 ; sets tc2dr di set (eirh). 6 ; enab les inttc2 interrupt ei ld (tc2cr), 00011100b ; selects tc2 source clock ld (tc2cr), 00111100b ; starts tc2 table 2.6.2 timer/counter 2 external clock source minimum pulse width [s] normal, idle mode ?h? width 2 3 /fc ?l? width 2 3 /fc figure 2.6.4 event counter mode timing chart 1 2 3 1 2 3 n timer register inttc2 interrupt tc2 pin input up-counter 0 n match detect counter clear count start 0 n ? 1
tmp88cs34/cp34 2006-07-06 88cs34-73 (3) window mode in this mode, counting up performed on the rising edge of an internal clock during tc2 external pin input (window pulse) is ?h? leve l. the contents of tc2dr are compared with the contents of up-counter. if a match found, an inttc2 interrupt is generated, and the up-counter is cleared. the maximum applied frequency (tc2 input) must be considerably slower than the selected internal clock. example: generates an interrupt, inputting ?h? level pulse width of 120 ms or more. (at fc = 16.0 mhz, dv1ck = 1) ldw (tc2dr), 0075h ; sets tc2dr (120 ms 2 14 /fc = 0075h) di set (eirh). 6 ; enab les inttc2 interrupt ei ld (tc2cr), 00000101b ; selects tc2 source clock ld (tc2cr), 00100101b ; starts tc2 figure 2.6.5 window mode timing chart 12 n ? 31 2 3 n tc2dr inttc2 interrupt internal clock up-counter 0 n match detect counter clear tc2 pin input n ? 2 n ? 1 0
tmp88cs34/cp34 2006-07-06 88cs34-74 2.7 8-bit timer/counter3 (tc3b) 2.7.1 configuration note: propagation of control input/output requires the correct i/o port setting. for details, see the section on i/o pots. figure 2.7.1 timer/counter 3 (tc3) tc3es overflow tc3ck fc/2 13 or fc/2 14 fc/2 12 or fc/2 13 fc/2 11 or fc/2 12 fc/2 10 or fc/2 11 fc/2 9 or fc/2 10 fc/2 8 or fc/2 9 fc/2 7 or fc/2 8 source clock clear tc3s tc3s h a b c d e f g s 8-bit timer register tc3 control register 3 y 8-bit up-counter tc3dra tc3cr a y b tc3 pin edge detector rising falling a y b s tc3s match detect tc3drb acap capture inttc3 interrupt capture tc3m comparator
tmp88cs34/cp34 2006-07-06 88cs34-75 2.7.2 control the timer/counter 3 is controlled by a time r/counter 3 control register (tc3cr) and two 8-bit timer registers (tc3dra and tc3drb ) and port multiplex control register (pmpxcr). 7 6 5 4 3 2 1 0 tc3dra (0018h) read/write (initial value: 1111 1111) tc3drb (0019h) read only (initial value: 1111 1111) 7 6 5 4 3 2 1 0 tc3cr (001ah) acap tc3s tc3k tc3m (initial value: * 0 * 0 0000) tc3m tc3 operating mode set 0: timer/event counter 1: capture normal, idle mode dv1ck = 0 dv1ck = 1 000 fc/2 13 fc/2 14 001 fc/2 12 fc/2 13 010 fc/2 11 fc/2 12 011 fc/2 10 fc/2 11 100 fc/2 9 fc/2 10 101 fc/2 8 fc/2 9 110 fc/2 7 fc/2 8 tc3ck tc3 source clock select [hz] 111 external clock (tc3 pin input) tc3s tc3 start control 0: stop and clear 1: start acap auto-capture control 0: ? 1: auto-capture enable write only note 1: fc: high-frequency clock [hz], * : don?t care note 2: set the mode and the source clock when the tc3 stops (tc3s = 0). note 3: values to be loaded to timer regist er 3a must satisfy the following condition. tc3dra > 0 (in the timer and event counter mode) note 4: auto-capture can be used only in the timer and event counter mode. note 5: before setting tc3dra or switching the operating mode, stop the tc3 (tc3s = 0). note 6: when stop mode is started, timer counter is stopped and tc3 start control (tc3s) is cleared to ?0? automatically. set tc3s to ?1? after stop m ode is released for restarting timer counter. note 7: tc3cr, tcescr is a write-only register and must not be used with any of read-modify-write instructions. 7 6 5 4 3 2 1 0 pmpxcr (0027h) ?0? chs tc4es tc3es (initial value: 00 ** ** 00) tc3es tc3 input control 0: normal 1: invert write only note 8: always write ?0? to bit 7 in pmpxcr. figure 2.7.2 timer register 3 and tc3 control register
tmp88cs34/cp34 2006-07-06 88cs34-76 2.7.3 function the timer/counter 3 has three operating modes: timer, event counter, and capture mode. when it is used in the capture mode, the noise rejection time of tc3 pin input can be set by remote control receive control register. (1) timer mode in this mode, the internal clock is used for counting up. the contents of tc3dra are compared with the contents of up-counter. if a match is found, a timer/counter 3 interrupt (inttc3) is generated, and the up-counter is cleared. the current contents of up-counter are loaded into tc3drb by setting acap (bit6 in tc3cr) to ?1? (auto-capture function). the contents of up-counter can be easily confirmed by executing the read instruction (rd instruction) of tc3drb. loading the contents of up-counter is not synchronized with counting up. the contents of over flow (ffh) and 00h can not be loaded correctly. it is necessary to consider the count cycle. table 2.7.1 source clock (internal clock) for timer/counter 3 (example: at fc = 16.0 mhz) normal, idle mode dv1ck = 0 dv1ck = 1 tc3ck resolution [ s] maximum setting time [ms] resolution [ s] maximum setting time [ms] 000 512 130.6 1024 261.1 001 256 65.3 512 130.6 010 128 32.6 256 65.3 011 64 16.3 128 32.6 100 32 8.2 64 16.3 101 16 4.1 32 8.2 110 8 2.0 16 4.1 fe ff 00 01 fe ff/00 01 counter clock tc3drb
tmp88cs34/cp34 2006-07-06 88cs34-77 figure 2.7.3 timer mode timing chart (2) event counter mode in this mode, the tc3 pin input pulses are used for counting up either the rising on falling edge can be selected with tc3es (bit 0 in pmpxcr). the contents of tc3dra are compared with the contents of the up-counter. if a match is found, an inttc3 interrupt is generated and the counter is cleared. match detect is executed on the falling edge of the tc3 pin. a match can not be detected, and inttc3 is not generated when the pulse is still in a falling state. the maximum applied frequency is shown in table 2.7.2. two or more machine cycles are required for both the high and low levels of the pulse width. the current contents of up-counter are loaded into tc3drb by setting acap (bit 6 in tc3cr) to ?1? (auto-capture funcion). the contents of up-counter can be easily confirmed by executing the read instruction (rd instruction) of tc3drb. loading the contents of up-counter is not synchronized with counting up. the contents of over flow (ffh) and 00h can not be loaded correctly. it is necessary to consider the count cycle. example: generates an interrupt every 0.5 s, inputting 50 hz pulses to the tc3 pin. ld (tc3cr), 00001110b ; sets tc3 mode and source clock ld (tc3dra), 19h ; 0.5 s 1/50 = 25 = 19h ld (tc3cr), 00011100b ; starts tc3 table 2.7.2 source clock (ext ernal clock) for timer/counter minimum applied frequency [hz] normal, idle mode "h" width 2 2 /fc "l" width 2 2 /fc m m m ? 2 up-counter timer register b a cap1 capture m + 1m + 2 (b) auto-capture timer register b inttc3 interrupt n ? 1n n + 1 capture count start source clock up-counter source clock 0 ? n n ? 1 n 0 match detect counter clear (a) timer mode ? m ? 1 m + 1m + 2 1 2 3 4 1 2 3 4 5 6 7 m ? 1 n n ? 1 n + 1
tmp88cs34/cp34 2006-07-06 88cs34-78 figure 2.7.4 event counter mode timing chart (3) capture mode in this mode, the pulse width, period and duty of the tc3 pin input are measured in this mode, which can be used in decoding the remo te control signals or distinguishing ac 50/60 hz, etc. the tc3 pin input can have its pola rity changed between normal and inverse by using the tc3es register. a. if tc3es = ?0? (non-inverting input) once command operation has started, the counter free-runs on an internal source clock. when the falling edge of the tc3 pin input is detected, the counter value is loaded into tc3drb. when the rising edge is detected, the counter value is loaded into tc3dra, and the counter is cleared, generating an inttc3 interrupt. if the rising edge is detected right after command operation has started, no capture to tc3drb and an inttc3 interrupt occurs only on capture to tc3dra. if a read instruction is executed for tc3drb, the value that exists at the end of the previous capture (immediately after a reset, ?ff?) is read. b. if tc3es = ?1? (inverse input) once command operation has started, the counter free-runs on an internal clock. when the rising edge of the tc3 pin input is detected, the counter value is loaded into tc3drb. when the falling edge is detected, the counter value is loaded into tc3dra, and the counter is cleared, generating an inttc3 interrupt. if the falling edge is detected right after command operation has started, the counter value is not captured into tc3drb and an inttc3 interrupt occurs only on capture to tc3dra. if a read instruction is executed for tc3drb, the value that exists at end of the previous capture (immediately after a reset, ?ff?) is read. the minimum acceptable input pulse width is equal to the length of one source clock period selected by tc3cr . table 2.7.3 tc3inv-based capture input edges tc3es capture into tc3drb captur e into tc3dra inttc3 interrupt ?0? (non-inverting input) falling edge rising edge ?1? (inverting input) rising edge falling edge note: capture of the tc3 pin input requires at least 1 cycle of the selected source clock. 1 2 3 1 2 3 n timer register inttc3 interrupt tc3 pin input up-counter 0 n match detect counter clear count start 0 n ? 1
tmp88cs34/cp34 2006-07-06 88cs34-79 figure 2.7.5 capture mode timing chart 0 1 i ? 1 i i + 1 k ? 1 k 0 m ? 1 1 m m + 1 n ? 1 n 0 1 2 3 fe ff 1 2 3 ff (overflow) n k fe m i capture overflow ca p ture command start inttc3 interrupt reading tc3dra tc3drb tc3dra internal waveform (normal) tc3 pin input up-counter source clock tc3s a) in case of tc3es = ?0? (normal) n ? 2 k 2 m ca p ture when tc3dra is not read, capture and overflow detection are sto pp ed. ca p ture command start inttc3 interrupt reading tc3dra tc3drb tc3dra internal waveform (invert) tc3 pin input up-counter source clock tc3s i n ca p ture b) in case of tc3es = ?1? (invert) 0 1 i ? 1 i k ? 1 k m ? 1 k + 1 m n ? 3 n0 fe ff 1 2 3 command start 01 0 1 n ? 2 n ? 1 1
tmp88cs34/cp34 2006-07-06 88cs34-80 the edge of tc3 pin input is detected in th e remote control receive circuit with noize rejection. the remote control receive circuit is controlled by the remote control receive control register (rccr). the romote control re ceive status register (rcsr) can monitor the porality selection and noize rejection circuit. figure 2.7.6 remote control receiving circuit fc/2 8 or fc/2 9 tc3 source clock polarity select noise reject circuit (5-bit up-down counter) edge detector rising falling capture control tc3in a b y s mpx rpols 5 rcnc rccr/rcsr rcovf remote control receive control/status register rncm mpx: multiplexer rcnf rcsck
tmp88cs34/cp34 2006-07-06 88cs34-81 rccr (00026h) rcen rpols rcsck rcnc (initial value: 0001 1111) rcnc noise reject time select 02h rcnc 1fh (source clock) (rcnc ? 1) [s] write only normal, idle mode dv1ck = 0 dv1ck = 1 0 2 8 /fc 2 9 /fc rcsck noise reject circuit source clock select 1 tc3ck note 2 rpols remote control signal polarity select 0: positive 1: negative r/w rcen remote control receive circuit operation control 0: disable 1: enable write only note 1: set rpols and rcsck when the timer/counter stops (tc3s = 0) note 2: source clock of timer/counter 3 note 3: fc: high-frequency clock [hz], * : don?t care note 4: rccr includes a write-only register and must not be used with any of read-modify-write instructions. note 5: values to be loaded to rcnc must satisfy the following condition. 02 rcnc 1f rcsr (00026h) rcnf rpols rcsck rcovf rncm (initial value: 0000 0 *** ) rncm remote control signal monitor after noise rejecter 0: low level 1: high level rcovf noise reject circuit overflow flag 0: signal and definition by overwriting the noise reject time rcnc 1: overflow read only normal, idle mode dv1ck = 0 dv1ck = 1 0 2 8 /fc 2 9 /fc rcsck noise reject circuit source clock select 1 tc3ck note 2 rpols remote control signal polarity select 0: positive 1: negative r/w rcnf remote control signal monitor after noise rejecter 0: without noise 1: with noise read only note 1: reading out the register rcsr resets rcnf and rcovf. note 2: source clock of timer/counter 3 note 3: when a 5-bit up-down counter counts down to ?0? after counting up, the rcnf defines to be noise. note 4: fc: high-frequency clock [hz], * : don?t care figure 2.7.7 remote control rece ive control register and remote control receive status register table 2.7.4 combination between th e polarity and the edge selection rpols tc3 pin input pulse (interrupt occurrence is shown as allow.) measurement 0 1 note: when tc3ck is used in rcsck, do not select an external clock to the tc3ck.
tmp88cs34/cp34 2006-07-06 88cs34-82 figure 2.7.8 remote control receive circuit timing chart tc3 pin input 0 1 2 3 0 1 2 1 0 source clock up-down counter rncm rcovf rcnf reading rcsr reset (a) noise (rpols = 0, rcnc = 03h) tc3 pin input 0 1 2 3 0 1 2 1 0 source clock up-down counter rncm rcovf rcnf reading rcsr (b) noise rejection circ uit overflow flag (rpols = 1, rcnc = 08h to 03h) writing rccr 4 reset 03h 08h rcnc
tmp88cs34/cp34 2006-07-06 88cs34-83 2.8 8-bit timer/counter 4 (tc4) 2.8.1 configuration note: set the input/output control correctly for the substitu tive input/output pins. for details, see the description of the input/output port control register. figure 2.8.1 timer/counter 4 (tc4) overflow detect tc4ck match detect fc/2 11 or fc/2 10 fc/2 7 or fc/2 8 fc/2 5 or fc/2 6 fc/2 3 or fc/2 4 source clock clear tc4s tc4s tc4m a b c d h 8-bit timer register 4 timer/counter 4 control register 3 2 y inttc4 interrupt request signal 8-bit up-counter tc4dr tc4cr a s y b tc4 pin tc4es comparator s
tmp88cs34/cp34 2006-07-06 88cs34-84 2.8.2 control the timer/counter 4 is controlled by a timer/counter 4 control register (tc4cr) and an 8-bit timer register 4 (tc4dr). 7 6 5 4 3 2 1 0 tc4dr (0001bh) write only (initial value: 1111 1111) 7 6 5 4 3 2 1 0 tc4cr (0001ch) tc4s tc4ck tc4m write only (initial value: ** 00 0000) tc4s tc4 start control 00: timer/event counter mode 01: reserved 10: reserved 11: reserved normal, idle mode dv1ck = 0 dv1ck = 1 000 fc/2 11 fs/2 12 ? 001 fc/2 7 fs/2 8 ? 010 fc/2 5 fs/2 6 ? 011 fc/2 3 fs/2 4 ? 100 reserved reserved ? 101 reserved reserved ? 110 reserved reserved ? tc4ck tc4 source clock select [hz] (note 4) 111 external clock (tc4 pin input) tc4m tc4 operating mode select 00: timer/event counter mode 01: reserved 10: reserved 11: reserved r/w note 1: fc: high-frequency clock [hz], * ; don?t care note 2: values to be loaded to the timer regi ster must satisfy the following condition. 1 tc4dr 255 note 3: when the tc4 is started (tc4s = 0 1) or disabled (tc4s = 1 0) or while the tc4 is operating (tc4s = 1 1), do not write to tc4m and tc4ck in tc4cr. if these registers are selected/changed during these operations, counting up is not performed properly. note 4: when stop mode is started, timer counter is stopped and cleared. set tc4s to ?1? after stop mode is released for restarting timer counter. note 5: undefined values are read from bits 6 and 7 of tc4cr. note 6: do not change tc4dr while the tc4 is operating. 7 6 5 4 3 2 1 0 pmpxcr (00027h) ?0? chs tc4es (tc3es) (initial value: 00 ** ** 00) tc4es tc4 edge select 0: rising edge 1: falling edge write only note 1: tc4cr, tc4dr and pmpxcr are write only register and must not be used with any of the read-modify-write instructions such as set, clr, etc. figure 2.8.2 timer register 4 and tc4 control register
tmp88cs34/cp34 2006-07-06 88cs34-85 2.8.3 function the timer/counter 4 has two operating modes: timer, event counter mode. (1) timer mode in this mode, the internal clock is used for counting up. the contents of tc4dr are compared with the contents of up-counter. if a match is found, an inttc4 interrupt is generated and the up-counter is cleared to ?0?. counting up resumes after the up-counter is cleared. table 2.8.1 source clock (internal cloc k) for timer/counter 4 (example: at fc = 16.0 mhz) normal, idle mode dv1ck = 0 dv1ck = 1 tc4ck resolution [ s] maximum setting time [ms] resolution [ s] maximum setting time [ms] 000 128.0 32.6 256.0 65.3 001 8.0 2.0 16.0 4.1 010 2.0 0.510 4.0 1.0 100 0.5 0.128 1.0 0.255 (2) event counter mode in this mode, the tc4 pin input (external clock) pulse is used for counting up. either the rising or falling edge can be selected with tc4es (bit 1 pmpxcr). the contents of tc4dr are compared with the contents of the up-co unter. if a match is found, an inttc4 interrupt is generated and the counter is cleared. the maximum applied frequency is shown table 2.8.2. two or more machine cycles are required for both the high and low level of the pulse width. note: the event counter mode can only be used in normal or idle mode. table 2.8.2 timer/counter 4 external clock source minimum input pulse width [s] normal1, idle1 mode ?h? width 2 3 /fc ?l? width 2 3 /fc
tmp88cs34/cp34 2006-07-06 88cs34-86 2.9 serial bus interface (sbi-ver. d) the tmp88cs34/cp34 has a 1-channel serial bus interface which employs a clocked-synchronous 8-bit serial bus interface and an i 2 c bus (a bus system by philips). the serial bus interface pins are selectively used as either channel 0 or channel 1. the serial interface is connected to external devices through p35 (sda0)/p52 (sda1) and p34 (scl0)/p51 (scl1) in the i 2 c bus mode; and through p53 ( sck1 ), p52 (so1) and p51 (si1) in the clocked-synchronous 8-bit sio mode. the serial bus interface pins are also used for the p3/p5 port. when used for serial bus interface pins, set the p3/p5 output latches of th ese pins to ?1?. when not used as serial bus interface pins, the p3/p5 port is used as a normal i/o port. note 1: when p3 and p5 is used as serial bus interface pins, p35, p34, p51 and p50 should be set as a sink open drain output by clearing pselcr to ?0?. note 2: the i 2 c of tmp88cs34/cp34 can be used only in the standard mode of i 2 c. the fast mode and the high speed mode can not be used. 2.9.1 configuration figure 2.9.1 serial bus interface (sbi) intsbi interrupt request sio clock control sio data control transfer control circuit i 2 c bus clock sync. + control shift register i 2 c bus data control scl input/ output control so fc/2 sbicrb/ sbisr sbidbr sbicra sbi control register b/ sbi status register i 2 c bus a ddress register sbi data buffer register sbi control register a si sda p52 p34 (sda1/so1) (sda0) (scl0) p35 divider noise canceller noise canceller i2car source clock generator fc/4 sck p53 ( sck ) p51 (scl1/si1)
tmp88cs34/cp34 2006-07-06 88cs34-87 2.9.2 control the following registers are used for contro l the serial bus interface and monitor the operation status. ? serial bus interface control register a (sbicra) ? serial bus interface control register b (sbicrb) ? serial bus interface data buffer register (sbidbr) ? i 2 c bus address register (i2car) ? serial bus interface status register a (sbisra) ? serial bus interface status register b (sbisrb) ? serial clock source co ntrol register (sccrb) ? serial clock control status register (scsr) the above registers differ depending on a mode to be used. refer to section ?2.9.7 i 2 c bus mode control? and ?2.9.9 clocked-synchronous 8-bit sio mode control?. 2.9.3 serial clock source control a serial bus interface circuit can reduce the power consumption by st opping a serial clock generater. serial clock source control register 7 6 5 4 3 2 1 0 sccrb ( 00ff1h ) scen (initial value: 0 *** **** ) scen serial clock source control 0: do not generate source clock 1: generate source clock write only note: when scrq and scen are ?1?, scen cannot be cleared to ?0?. when scrq is ?0?, scen is cleared to ?0?. serial clock control status register 7 6 5 4 3 2 1 0 scsr ( 00ff1h ) scrq (initial value: 0 *** **** ) scrq serial clock source request 0: no source clock request from serial bus interface 1: source clock request from serial bus interface read only figure 2.9.2 serial clock source clock generation ?1? scen write data except ?00? to sbim write data ?00? to sbim ?0? scen source clock scen scrq
tmp88cs34/cp34 2006-07-06 88cs34-88 2.9.4 channel select a serial bus interface circuit ca n select i/o pin when a serial bus interface is used for i 2 c bus mode. port switching register 7 6 5 4 3 2 1 0 pmpxcr (00027h) ?0? chs (tc4es) (tc3es) (initial value: 00 ** ** 00) chs i 2 c bus channel select 0: channel 0 1: channel 1 r/w note 1: when sio mode, don?t use channel 0. therefore, set to ?1? in pmpxcr at sio mode. note 2: always write ?0? to bit 7 in pmpxcr. note 3: * : don?t care figure 2.9.3 channel select 2.9.5 software reset a serial bus interface circuit has a software reset function, when a serial bus interface circuit is locked by an external noise, etc. to occur software reset, write ?01?, ?10? into the swrst (bit 1, 0 in sbicrb). during software reset, the swrmon (bit 0 in sbisra) is clear to ?0?. 2.9.6 the data format in the i 2 c bus mode the data format when using the tmp88cs34/cp34 in the i 2 c bus mode are shown in as below. notes: s: start condition r/ w : direction bit ack: acknowledge bit p: stop condition figure 2.9.4 data format in i 2 c bus mode 1 1 or more 1 or more 1 or more 1 a c k a c k a c k a c k a c k data 1 1 slave address a c k a c k r / w r / w r / w p p p a c k a c k a c k s s s s (a) addressing format (b) addressing format (with restart) (c) free data format data 8 bits 1 to 8 bits 1 or more 1 data 1 to 8 bits slave address slave address data data data data 8 bits 8 bits 1 to 8 bits 1 to 8 bits 1 to 8 bits 8 bits 1 to 8 bits 1 1 1 1 1 1 1 1 1
tmp88cs34/cp34 2006-07-06 88cs34-89 2.9.7 i 2 c bus mode control the following registers are used to control the serial bus interface (sbi) and monitor the operation status in the i 2 c bus mode. serial bus interface control register a 7 6 5 4 3 2 1 0 sbicra (00020h) bc ack sck (initial value: 0000 * 000) ack = 0 ack = 1 bc number of clock bits number of clock bits 000 8 8 9 8 001 1 1 2 1 010 2 2 3 2 011 3 3 4 3 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 bc number of transferred bits 111 7 7 8 7 write only ack master mode slave mode 0 not generate a clock pulse for an acknowledgement. not count a clock pulse for an acknowledgement. ack acknowledgement mode specification 1 generate a clock pulse for an acknowledgement. count a clock pulse for an acknowledgement. r/w dv1ck = 0 dv1ck = 1 sck serial clock selection (at fc = 16 mhz, output on scl pin) 000: reserved (note 3) 001: reserved (note 3) 010: reserved (note 3) 011: 60.6 khz 100: 30.7 khz 101: 15.5 khz 110: 7.8 khz 111 : reserved 000: reserved (note 3) 001: reserved (note 3) 010: 58.8 khz 011: 30.3 khz 100: 15.4 khz 101: 7.7 khz 110: 3.9 khz 111 : reserved write only note 1: set the bc to ?000? before switching to 8-bit sio bus mode. note 2: sbicra cannot be used with any of read-modify-w rite instructions such as bit manipulation, etc. note 3: this i2c bus circuit does not support the fast mode. it supports the standard mode only. although the i2c bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the i2c specification is not guaranteed in that case. serial bus interface data buffer registe r 7 6 5 4 3 2 1 0 sbidbr (00021h) (initial value: **** **** ) r/w note 1: for writing transmitted data, start from the msb (bit 7). note 2: the data which was written into sbidbr cannot be read, since a write data buffer and a read buffer are independent in sbidbr. therefore, sbidbr cannot be used with any of read-modify-write instructions such as bit manipulation, etc. i 2 c bus address register 7 6 5 4 3 2 1 0 slave address i2car (00022h) sa6 sa5 sa4 sa3 sa2 sa1 sa0 als (initial value: 0000 0000) sa slave address selection als address recognition mode specification 0: slave address recognition 1: non slave address recognition write only note 1: i2car is write-only register and cannot be used wi th any of read-modify-write instruction such as bit manipulation, etc. note 2: do not set i2car to ?00h? to avoid the incorrect response of acknowledgment in slave mode. if ?00h? is set to i2car as the slave address and received ?01h ? in slave mode, the device might transmit the acknowledgement incorrectly. figure 2.9.5 serial bus interface control register a, serial bus interface data buffer register and i 2 c bus address register in the i 2 c bus mode
tmp88cs34/cp34 2006-07-06 88cs34-90 serial bus interface control register b 7 6 5 4 3 2 1 0 sbicrb (00023h) mst trx bb pin sbim swrst1 s wrst0 (initial value: 0001 0000) mst master/slave selection 0: slave 1: master trx transmitter/receiver selection 0: receiver 1: transmitter bb start/stop generation 0: generate a stop condition when mst, trx and pin are ?1?. 1: generate a start condition when mst, trx and pin are ?1?. pin cancel interrupt service request 0: ? 1: cancel interrupt service request sbim serial bus interface operating mode selection 00: port mode (serial bus interface output disable) 01: clocked synchronous 8-bit sio mode 10: i 2 c bus mode 11: reserved swrst1 swrst0 software reset start bit software reset starts by first writing ?10? and next writing ?01?. write only note 1: switch a mode to port after confirming that the bus is free. note 2: switch a mode to i 2 c bus mode or clock synchronous 8-bit sio mode after confirming that the port is high-level. note 3: sbicrb has write-only register and must not be used wi th any of read-modify-write instructions such as bit manipulation, etc. note 4: when the swrst (bit 1, 0 in sbicrb) is written to ?01?, ?10?, software reset (four machine cycles) is occurred. this time, control the serial bus in terface and monitor the operation status registers except the sbim (bit 3, 2 in sbicrb) and the chs (bit 6 in pmpxcr) are reseted. control the serial bus interface and monitor the op eration status registers are sbicra, sbicrb, sbidbr, i2car, sbisra, sbisrb, sccra and scsr. serial bus interface status register a 7 6 5 4 3 2 1 0 sbisra (00020h) ack swr mon (initial value: **** *** 1) swrmon software reset monitor 0: during software reset 1: ? (initial) read only note 1: * : don?t care serial bus interface status register b 7 6 5 4 3 2 1 0 sbisrb (00023h) mst trx bb pin al aas ad0 lrb (initial value: 0001 0000) mst master/slave selection status monitor 0: slave 1: master trx transmitter/receiver selection status monitor 0: receiver 1: transmitter bb bus status monitor 0: bus free 1: bus busy pin interrupt service requests status monitor 0: requesting interrupt service 1: releasing interrupt service request al arbitration lost detection monitor 0: ? 1: arbitration lost detected aas slave address match detection monitor 0: not detect slave address match or ?general call? 1: detect slave address match or ?general call? ad0 ?general call? detection monitor 0: not detect ?general call? 1: detect ?general call? lrb last received bit monitor 0: last receive bit is ?0? 1: last receive bit is ?1? read only figure 2.9.6 serial bus interface contro l register b and serial bus interface status register a/b in the i 2 c bus mode
tmp88cs34/cp34 2006-07-06 88cs34-91 (1) acknowledgement mode specification a. acknowledgement mode (ack = ?1?) to set the device as an acknowledgement mode, the ack (bit4 in sbicra) should be set to ?1?. when a serial bus interface circu it is a master mode, an additional clock pulse is generated for an acknowledge signal. in a slave mode, a clock is counted for the acknowledge signal. in the master transmitter mode, the sda pin is released in order to receive an acknowledge signal from the receiver during additional clock pulse cycle. in the master receiver mode, the sda pin is set to low level generation an acknowledge signal during additional clock pulse cycle. in a slave mode, when a received slave ad dress matches to a sl ave address which is set to the i2car or when a ?general call? is received, the sda pin is set to low level generating an acknowledge signal. af ter the matching of slave address or the detection of ?general call?, in the transmitter the sda pin is released in order to receive an acknowledge signal from the receiver during additional clock pulse cycle. in a receiver, the sda pin is set to low level generation an acknowledge signal during additional clock pulse cycle after the matching of slave address or the detection of ?general call?. the table 2.9.1 shows the scl and sda pins status in acknowledgement mode. table 2.9.1 scl and sda pins status in acknowledgement mode mode pin transmitter receiver scl an additional clock pulse is generated. master sda released in order to receive and acknowledge signal. set to low level generating an acknowledge signal. scl a clock is counted for the acknowledge signal. when slave address matches or a general call is detected ? set to low level generating an acknowledge signal. slave sda after matching of slave address or general call released in order to receive an acknowledge signal. set to low level generating an acknowledge signal. b. non-acknowledgement mode (ack = ?0?) to set the device as a non-acknowledgement mode, the ack should be cleared to ?0?. in the master mode, a clock pulse for an acknowledge signal is not generated. in the slave mode, a clock for a acknow ledge signal is not counted. (2) number of transfer bits the bc (bits 7 to 5 in sbicra) is used to select a number of bits for next transmitting and receiving data. since the bc is cleared to ?000? as a start condition, a slave address and direction bit transmissions are always executed in 8 bits. other than these, the bc retains a specified value.
tmp88cs34/cp34 2006-07-06 88cs34-92 (3) serial clock a. clock source the sck (bits 2 to 0 in sbicra) is used to select a maximum transfer frequency output from the scl pin in the master mode. set a communication baud rate that meets the i2c bus specification, such as the shortest pulse width of tlow, based on the equations shown below. four or more machine cycles are required for both high and low levels of pulse width in the external clock which is input from scl pin. note: since the i2c of tmp88cs34/cp34 can not be used as the fast mode and the high speed mode, do not set sck as the frequency that is over 100 khz. figure 2.9.7 clock source b. clock synchronization in the i 2 c bus mode, in order to drive a bus with a wired and, a master device which pulls down a clock pulse to low will, in th e first place, invalidate a clock pulse of another master device which gene rates a high-level clock pulse. the serial bus interface circuit has a clock synchronization function. this function ensures normal transfer even if there are two or more masters on the same bus. the example explains clock synchronization procedures when two masters simultaneously exist on a bus. figure 2.9.8 clock synchronization as master 1 pulls down the scl pin to the low level at point ?a?, the scl line of the bus becomes the low level. after detecting this situation, master 2 resets counting a clock pulse in the high level and sets the scl pin to the low level. master 1 finishes counting a clock pulse in the low level at point ?b? and sets the scl 1/fscl t low = 2 n /fc t high = 2 n /fc + 8/fc fscl = 1/(t low + t high ) note: fc: high-frequency clock n sck (bits 2 to 0 in the sbicra) dv1ck = 0 dv1ck = 1 000 001 010 011 100 101 110 4 5 6 7 8 9 10 5 6 7 8 9 10 11 t high t low t sckl t sckh t sckl , t sckh > 4 tcyc note: tcyc = 4/fc (in normal mode, idle mode) scl pin (master 1) scl pin (master 2) scl (bus) wait count start count reset a b c count reset
tmp88cs34/cp34 2006-07-06 88cs34-93 pin to the high level. since master 2 holds the scl line of the bus at the low level, master 1 waits for counting a clock pulse in the high level. after master 2 sets a clock pulse to the high level at point ?c? and detects the scl line of the bus at the high level, master 1 starts counting a clock pulse in the high level. then, the master, which has finished the counting a clock pulse in the high level, pulls down the scl pin to the low level. the clock pulse on the bus is deteminded by the master device with the shortest high-level period and the master device wi th the longest low-leve l period from among those master devices connected to the bus. (4) slave address and address re cognition mode specification when the serial bus interface circuit is used with an addressing format to recognize the slave address, clear the als (bit 0 in i2car) to ?0?, and set the sa (bits 7 to 1 in i2car) to the slave address. when the serial bus interfac circuit is used with a free data format not to recognize the slave address, set the als to ?1?. with a free data format, the slave address and the direction bit are not recognized, and they are processed as data from immediately after start condition. (5) master/slave selection to set a master device, the mst (bit 7 in sbic rb) should be set to ?1?. to set a slave device, the mst should be cleared to ?0?. when a stop condition on the bus or an arbitr ation lost is detected, the mst is cleared to ?0? by the hardware. (6) transmitter/receiver selection to set the device as a transmitter, the trx (bit 6 in sbicrb) should be set to ?1?. to set the device as a receiver, the trx should be cl eared to ?0?. when data with an addressing format is transferred in the slave mode, the trx is set to ?1? by a hardware if the direction bit (r/ w ) sent from the master device is ?1?, and is cleared to ?0? by a hardware if the bit is ?0. in the master mode, after an acknowledge signal is returned from the slave device, the trx is cleared to ?0? by a hardware if a transmit ted direction bit is ?1?, and is set to ?1? by a hardware if it is ?0?. when an acknowledge si gnal is not returned, the current condition is maintained. when a stop condition on the bus or an arbitration lost is detected, the trx is cleared to ?0? by the hardware. the following table show trx changing conditions in each mode and trx value after changing. mode direction bit conditions trx after changing ?0? ?0? slave mode ?1? a received slave address is the same value set to i2car ?1? ?0? ?1? master mode ?1? ack signal is returned ?0? when a serial bus interface circuit operates in the free data format, a slave address and a direction bit are not recognized. they are handled as data just after generating a start condition. the trx is not changed by a hardware.
tmp88cs34/cp34 2006-07-06 88cs34-94 (7) start/stop condition generation when the bb (bit 5 in sbicrb) is ?0?, a slave address and a direction bit which are set to the sbidbr are output on a bus after generating a start condition by writing ?1? to the mst, trx, bb and pin. it is necessary to se t transmitted data to the sbidbr and set ?1? to ack beforehand. figure 2.9.9 start condition generation and slave address generation when the bb is ?1?, sequence of generating a stop condition is started by writeng ?1? to the mst, trx and pin, and ?0? to the bb. do not modify the contents of mst, trx, bb and pin until a stop condition is generated on a bus. figure 2.9.10 stop condition generation when a stop condition is generated and the scl line on a bus is pulled-down to low level by another device, a stop condition is generated after releasing the scl line. the bus condition can be indicated by reading the contents of the bb (bit 5 in sbisrb). the bb is set to ?1? when a start condition on a bus is detected and is cleared to ?0? when a stop condition is detected. (8) interrupt service request and cancel when a serial bus interface circuit is in th e master mode and transferring a number of clocks set by the bc and the ack is complete, a serial bus interface interrupt request (intsbi) is generated. in the slave mode, the conditions of generating intsbi are follows: ? at the end of acknowledge signal when the received slave address matches to the value set by the i2car ? at the end of acknowledge signal when a ?general call? is received ? at the end of transferring or receiving after matching of slave address or receiving of ?genral call? when a serial bus interface interrupt request occurs, the pin (bit 4 in sbisr) is cleared to ?0?. during the time that the pin is ?0?, the scl pin is pulled-down to low level. either writing data to sbidbr or reading data from the sbidbr sets the pin to ?1?. the time from the pin being set to ?1? until the scl pin is released takes t low . although the pin (bit 4 in sbicrb) can be set to ?1? by the program, the pin can not be cleared to ?0? by the program. note: if the arbitration lost occurs, when the sl ave address does not match, the pin is not cleared to ?0? even thought intsbi is generated. scl pin sda pin start condition slave address and the direction bit a cknowledge si g nal 1 2 345678 9 a6 a5 a4 a3 a2 a1 a0 r/ w sda pin scl pin stop condition
tmp88cs34/cp34 2006-07-06 88cs34-95 (9) serial bus interface operating mode selection the sbim (bit 3 and 2 in sbicrb) is used to specify a serial bus interface operation mode. set the sbim to ?10? in order to change a operation mode to i 2 c bus mode. before changing operation mode, confirm serial bus in terface pins in a high level. and switch a mode to port after confirming that a bus is free. (10) arbitration lost detection monitor since more than one master device can exist simultaneously on a bus in the i 2 c bus mode, a bus arbitration procedure is implemented in order to guarantee the contents of transferred data. data on the sda line is used for bus arbitration of the i 2 c bus. the following shows an example of a bus arbitration procedure when two master devices exist simultaneously on a bus. master 1 and master 2 output the same data until point ? a?. after master 1 outputs ?1? and master 2, ?0?, the sda line of a bus is wired and and the sda line is pulled-down to the low level by master 2. when the scl line of a bus is pulled-up at point ?b?, the slave device reads data on the sda line, that is data in master 2. data transmitted from master 1 becomes invalid. the state in master 1 is called ?arbitration lost?. a master device which loses arbitration releases the sda pin and the scl pin in order not to effect data transmitte d from other masters with arbitration. when more than one master sends the same data at the first word, arbitration occurs continuously after the second word. figure 2.9.11 arbitration lost sda (bus) sda pin becomes ?1? after losing arbitration. a b scl (bus) sda pin (master 2) sda pin (master 1)
tmp88cs34/cp34 2006-07-06 88cs34-96 the serial bus interface circuit compares levels of a sda line of a bus with its those sda pin at the rising edge of the scl line. if the levels are unmatched, arbitration is lost and the al (bit 3 in sbisrb) is set to ?1?. when the al is set to ?1?, the mst and trx are cleared to ?0? and the mode is switched to a slave receiver mode. the al is cleared to ?0? by writing or reading data to or from the sbidbr or writing data to the sbicrb. figure 2.9.12 example of when a serial bus interface circuit is a master b (11) slave address match detection monitor in the slave mode, the aas (bit 2 in sbisr) is set to ?1? when the received data is ?general call? or the received data matches the slave address setting by i2car with an address recognition mode (als = 0). when a serial bus interface circuit operates in the free data format (als = 1), the aas is set to ?1? after receiving the first 1-word of data. the aas is cleared to ?0? by writing data to the sbidbr or reading data from the sbidbr. (12) general call detection monitor the ad0 (bit 1 in sbisr) is set to ?1? when all 8-bit received data is ?0? immediately after a start condition in a slave mode. the ad0 is cleared to ?0? when a start or stop condition is detected on a bus. (13) last received bit monitor the sda value stored at the rising edge of the scl is set to the lrb (bit0 in sbisrb). in the acknowledge mode, immediately after an intsbi interrupt request is generated, an acknowledge signal is read by reading the contents of the lrb. releasing sda pin and scl pin to hi gh level as losing arbitration. 1 2 3 4 5 6 7 8 9 1 2 3 d7a d6a d5a d4a d3a d2a d1a d0a d7a? d6a? d5a? d7b d6b scl pin sda pin scl pin sda pin a l mst trx a ccessed to sbidbr or sbicrb master a master b 1 2 3 4 56789 stop clock output intsbi
tmp88cs34/cp34 2006-07-06 88cs34-97 2.9.8 data transfer of i 2 c bus (1) device initialization for initialization of device, set the ack in sbicra to ?1? and the bc to ?000?. specify the data length to 8 bits to count clocks for an acknowledge signal. set a transfer frequency to the sck in sbicra. next, set the slave address to the sa in i2car and clear the als to ?0? to set an addressing format. after confirming that the serial bus interface pin is high-level, for specifying the default setting to a slave receiver mode , clear ?0? to the mst, trx and bb in sbicrb, set ?1? to the pin, ?10? to the sbim, and ?00? to bits swrst1 and swrst0. note: the initialization of a serial bus interface ci rcuit must be complete within the time from all devices which are connected to a bus have initialized to and device does not generate a start condition. if not, the data can not be re ceived correctly because the other device starts transferring before an end of the init ialization of a serial bus interface circuit. (2) start condition and slave address generation confirm a bus free status (when bb = 0). set the ack to ?1? and specify a slave address and a direction bit to be transmitted to the sbidbr. by writing ?1? to the mst, trx, bb and pin, the start condition is generated on a bus and then, the slave address and the direction bi t which are set to the sbidbr are output. an intsbi interrupt request occurs at the 9t h falling edge of a scl clock cycle, and the pin is cleared to ?0?. the scl pin is pulled- down to the low level while the pin is ?0?. when an interrupt request occurs the trx changes by the hardware according to the direction bits only when an acknowledge signal is returned from the slave device. note 1: do not write a slave address to be output to the sbidbr while data is transferred. if data is written to the sbidbr, data to been outputting may be destroyed. note 2: the bus free must be confirmed by software within 98.0 s (the shortest transmitting time according to the i 2 c bus standard) after setting of the slave address to be output. only when the bus free is confirmed, set ?1? to the mst, trx, bb, and pin doesn?t finish within 98.0 s, the other masters may start the transferring and the slave address data written in sbidbr may be broken. figure 2.9.13 start condition generation and slave address transfer a cknowledge signal from a slave device scl pin sda pin start condition slave address + direction bit 1 2 345678 9 a6 a5 a4 a3 a2 a1 a0 r/ w pin intsbi interrupt request
tmp88cs34/cp34 2006-07-06 88cs34-98 (3) 1-word data transfer check the mst by the intsbi interrupt process after an 1-word data transfer is completed, and determine whether the mode is a master or slave. a. when the mst is ?1? (master mode) check the trx and determine whether the mode is a transmitter or receiver. 1. when the trx is ?1? (transmitter mode) test the lrb. when the lrb is ?1?, a rece iver does not request data. implement the process to generate a stop condition (des cribed later) and terminate data transfer. when the lrb is ?0?, the receiver reques ts next data. when the next transmitted data is other than 8 bits, set the bc, set the ack to ?1?, and write the transmitted data to the sbidbr. after writing the data, the pin becomes ?1?, a serial clock pulse is generated for transferring a next 1-word of data from the scl pin, and then the 1-word data is transmitted. after the data is transmitted, and an intsbi interrupt request occurs. the pin become ?0? and the scl pin is set to low level. if the data to be transferred is more than one word in length, repeat the procedure from the lrb test above. figure 2.9.14 example of when bc = ?000?, ack = ?1? 2. when the trx is ?0? (receiver mode) when the next transmitted data is other than of 8 bits, set the bc again. set the ack to ?1? and read the received data from the sbidbr (reading data is undefined immediately after a slave address is sent). af ter the data is read, the pin becomes ?1?. a serial bus interface circuit outputs a serial clock pulse to the scl to transfer next 1-word of data and sets the sda pin to ?0? at the acknowledge signal timing. an intsbi interrupt request occurs and the pin becomes ?0?. then a serial bus interface circuit outputs a clock pulse for 1-word of data transfer and the acknowledge signal each time that received data is read from the sbidbr. figure 2.9.15 example of when bc = ?000?, ack = ?1? scl pin sda pin a cknowledge signal from a receiver 1 2 3456789 d7 d6 d5 d4 d3 d2 d1 pin intsbi interrupt request d0 write to sbidbr scl pin sda pin a cknowledge signal to a transmitter 1 2 3456789 d7 d6 d5 d4 d3 d2 d1 pin intsbi interrupt d0 read to sbidbr new d7
tmp88cs34/cp34 2006-07-06 88cs34-99 to make the transmitter terminate transm it, clear the ack to ?0? before reading data which is 1-word before the last data to be received. a serial bus interface circuit does not generate a clock pulse for the acknowledge signal by clearing ack. in the interrupt routine of end of transmission, when the bc is set to ?001? and read the data, pin is set to ?1? and generates a clock pulse fo r a 1-bit data transfer. in this case, since the master device is a receiver, the sda line on a bus keeps the high-level. the transmitter receives the high-level signal as an ack signal. the receiver indicates to the transmitter that data transfer is complete. after 1-bit data is received and an interru pt request has occurred, generates the stop condition to terminate data transter. figure 2.9.16 termination of data transfer in master receiver mode b. when the mst is ?0? (slave mode) in the slave mode, a serial bus interface circuit operates either in normal slave mode or in slave mode after losing arbitration. in the slave mode, the conditions of generating intsbi are follows: ? when the received slave address matches to the value set by the i2car ? when a ?general call? is received ? at the end of transferring or receiving after matching of slave address or receiving of ?general call? a serial bus interface circuit ch anges to a slave mode if arbitration is lost in the master mode. and an intsbi interrupt request occurs when word data transfer terminates after losing arbitration. the behavior of intsbi and pin after losing arbitration are shown in table 2.9.2. table 2.9.2 the behavior of int sbi and pin after losing arbitration when the arbitration o ccurs during transmission of slave address as a master when the arbitration o ccurs during transmission of data as a master transmit mode intsbi intsib is generated at the terminatin of word data. pin when the slave address matches the value set by i2car, the pin is cleared to ?0? by generating of intsbi. when the slave address doesn?t match the value set by i2car, the pin keeps ?1?. pin keeps ?1?. check the al (bit 3 in the sbisr), the trx (bit 6 in the sbisr), the aas (bit 2 in the sbisr), and the ad0 (bit 1 in the sbisr) and implements processes according to conditions listed in table 2.9.3. scl pin sda pin a cknowledge signal sent to a transmitter 1 2 345678 1 d7 d6 d5 d4 d3 d2 d1 pin intsbi interrupt request d0 ?0? ack read sbidbr ?001? bc read sbidbr
tmp88cs34/cp34 2006-07-06 88cs34-100 table 2.9.3 operation in the slave mode trx al aas ad0 conditions process 1 1 0 a serial bus interfac e circuit loses arbitration when transmitting a slave address. and receives a slave address of which the value of the direction bit sent from another master is ?1?. 1 0 in the slave receiver mode, a serial bus interface circuit receives a slave address of which the value of the direction bit sent from the master is ?1?. set the number of bits in 1 word to the bc and write transmitted data to the sbidbr. 1 0 0 0 in the slave transmitter mode, 1-word data is transmitted. test the lrb. if the lrb is set to ?1?, set the pin to ?1? since the receiver does not request next data. then, clear the trx to ?0? release the bus. if the lrb is set to ?0?, set the number of bits in 1-word to the bc and write transmitted data to the sbidbr since the receiver requests next data. 1 1/0 a serial bus interfac e circuit loses arbitration when transmitting a slave address. and receives a slave address of which the value of the direction bit sent from another master is ?0? or receives a ?general call?. read the sbidbr for setting the pin to ?1? (reading dummy data) or write ?1? to the pin. 1 0 0 a serial bus interface circuit loses arbitration when transmitting a slave address or data. and terminates transferring word data. a serial bus interface circuit is changed to slave mode. to clear al to ?0?, read the sbidbr or write the data to sbidbr. 1 1/0 in the slave receiver mode, a serial bus interface circuit receives a slave address of which the value of the direction bit sent from the master is ?0? or receives ?general call?. read the sbidbr for setting the pin to ?1? (reading dummy data) or write ?1? to the pin. 0 0 0 1/0 in the slave receiver mode, a serial bus interface circuit term inates receiving of 1-word data. set the number of bits in 1-word to the bc and read received data from the sbidbr. note: in the slave mode, if the slave address set in i2 car is ?00000000b?, the trx changes to ?1? by receiving the start byte data ?00000001b?. (4) stop condition generation when the bb is ?1?, a sequence of generating a stop condition is started by setting ?1? to the mst, trx, and pin, and clear ?0? to the bb. do not modify the contents of the mst, trx, bb, pin until a stop condition is generated on a bus. when a scl line on a bus is pulled-down by other devices, a serial bus interface circuit generates a stop condition af ter they release a scl line. figure 2.9.17 stop condition generation ?1? mst ?1? trx ?0? bb ?1? pin scl pin stop condition sda pin bb (read) pin
tmp88cs34/cp34 2006-07-06 88cs34-101 (5) restart restart is used to change the direction of data transfer between a master device and a slave device during transferring data. the fo llowing explains how to restart a serial bus interface circuit. clear ?0? to the mst, trx and bb and set ?1? to the pin. the sda pin retains the high-level and the scl pin is released. since a stop condition is not generated on a bus, a bus is assumed to be in a busy state from ot her devices. test the bb until it becomes ?0? to check that the scl pin a serial bus interface circuit is released. test the lrb until it becomes ?1? to check that the scl line on a bu s is not pulled-down to the low-level by other devices. after confirming that a bus stays in a free state, generate a start condition with procedure (2). in order to meet setup time when restarting, take at least 4.7 s of waiting time by software from the time of restarting to confirm that a bus is free until the time to generate a start condition. note: when restarting after receiving in master receiver mode, because the divice doesn?t send an acknowledgement as a last data, t he level of scl line can not be conrirmied by reading lrb. therefore, co nfirm the status of scl line by reading p5prd register. figure 2.9.18 timing diagram when restarting start condition sda (pin) scl (pin) ?0? mst ?0? trx ?0? bb ?1? pin scl (bus) lrb bb pin ?1? mst ?1? trx ?1? bb ?1? pin 4.7 s (min)
tmp88cs34/cp34 2006-07-06 88cs34-102 2.9.9 clocked-synchronous 8-bit sio mode control the following registers are used to control the serial bus interface (sbi) and monitor the operation in the clocked-synchronous 8-bit sio mode. serial bus interface control register a 7 6 5 4 3 2 1 0 sbicra (00020h) sios sioinh siom ?0? sck (initial value: 0000 * 000) sios indicate transfer start/stop 0: stop 1: start sioinh continue/abort transfer 0: continue transfer 1: abort transfer (automatically cleared after abort) siom transfer mode select 00: 8-bit transmit mode 01: reserved 10: 8-bit transmit/receive mode 11: 8-bit receive mode dv1ck = 0 dv1ck = 1 sck serial clock selection (at fc = 16 mhz, output on sck pin) 000: 1000.0 khz 001: 500.0 khz 010: 250.0 khz 011: 125.0 khz 100: 62.5 khz 101: 31.2 khz 110: 15.6 khz 111: external clock (input from sck pin) 000: 500.0 khz 001: 250.0 khz 010: 125.0 khz 011: 62.5 khz 100: 31.2 khz 101: 15.6 khz 110: 7.8 khz 111: external clock (input from sck pin) write only note 1: fc: high-frequency clock [hz], * : don?t care note 2: clear the sios to ?0? and set the sioinh to ?1? when setting the transfer mode and serial clock. note 3: sbicra is write-only register and cannot be used wi th any of read-modify-write instructions such as bit manipulation, etc. serial bus interface data register 7 6 5 4 3 2 1 0 sbidbr (00021h) (initial value: **** **** ) r/w note1 : the data which was written into sbidbr cannot be read, since a write buffer and a read buffer are independent in sbidbr. therefore, sbidbr cannot be used with any of read-modify-write instructions such as bit manipulation, etc. note 2: * : don?t care serial bus interface control register b 7 6 5 4 3 2 1 0 sbicrb (00023h) ?0? ?0? ?0? ?1? sbim swrst1 swrst0 (initial value: **** 0000) sbim serial bus interface operation mode selection 00: port mode (serial bus interface output disable) 01: sio mode 10: i 2 c bus mode 11: reserved swrst1 swrst0 software reset start bit software reset starts by first writing ?10? and next writing ?01? write only note 1: * : don?t care note 2: switch a mode to port after data transfer is complete. note 3: switch a mode to i 2 c bus mode or clock synchronous 8-bit sio mode after confirming that the port is high-level. note 4: sbicrb is a write-only register and cannot be used wi th any of read-modify-write instructions such as bit manipulation, etc. note 5: clear bit 7 to 5 in sbicrb to ?0?, and set bit 4 to ?1?. note 6: when the swrst (bit 1, 0 in sbicrb) is wr itten to ?01?, ?10?, software reset is occurred. this time, control the serial bus in terface and monitor the operation status registers except the sbim (bit 3, 2 in sbicrb) and the chs (bit 6 in pmpxcr) are reseted. control the serial bus interface and monitor the op eration status registers are sbicra, sbicrb, sbidbr, i2car, sbisra, sbisrb, sccra, sccrb and scsr. figure 2.9.19 control register/data buffer register/status regist er in sio mode (1)
tmp88cs34/cp34 2006-07-06 88cs34-103 serial bus interface status register a 7 6 5 4 3 2 1 0 sbisra (00020h) swr mon (initial value: **** *** 1) swrmon software reset monitor 0: during software reset 1: ? (initial) read only serial bus interface status register b 7 6 5 4 3 2 1 0 sbisrb (00023h) ?1? ?1? ?1? ?1? siof sef ?1? ?1? siof serial transfer operating status monitor 0: transfer terminated 1: transfer in process sef shift operating status monitor 0: shift operation terminated 1: shift operation in process read only note: set bit 7 to 4, bit 1 and bit 0 in sbisrb to ?1?. figure 2.9.20 control register/data buffer register/status regist er in sio mode (2) (1) serial clock a. clock source the sck (bits 2 to 0 in sbicra) is used to select the following functions. 1. internal clock in an internal clock mode, any of seven fr equencies can be selected. the serial clock is output to the outside on the sck pin. the sck pin becomes a high-level when data transfer starts. when writing (in the transmit mode) or reading (in the receive mode) data cannot follow the serial clock rate, an automatic-wait function is executed to stop the serial clock automatically and hold the next shift operation until reading or writing is complete. figure 2.9.21 automatic wait function 2. external (sck = ?111?) an external clock supplied to the sck pin is used as the serial clock. in order to ensure shift operation, a pulse width of at least 4-machine cycles is required for both high and low levels in the serial clock. the maximum data transfer frequency is 500 khz (fc = 16.0 mhz). figure 2.9.22 the maximum data transfer frequency in the external clock input c 2 c 1 c 0 b 7 b 6 b 5 b 0 a 6 a 7 a 2 a 5 a 1 a 0 automatic-wait function sck pin output so pin output write transmitted data 1 2 3 7 8 1 2 6 7 8 1 2 3 c b a b 1 b 4 sck pin t sckl t sckh t sckl , t sckh > 4 tcyc note: tcyc = 4/fc (in normal mode, idle mode)
tmp88cs34/cp34 2006-07-06 88cs34-104 b. shift edge the leading edge is used to transmit data, and the trailing edge is used to receive data. 1. leading edge data is shifted on the leading edge of the serial clock (at a falling edge of the sck pin input/output). 2. trailing edge data is shifted on the trailing edge of the serial clock (at a rising edge of the sck pin input/output). * : don?t care figure 2.9.23 shift edge (2) transfer mode the siom (bits 5 and 4 in sbicra) is us ed to select a tran smit, receive, or transmit/receive mode. a. 8-bit transmit mode set a control register to a transmit mode and write transmit data to the sbidbr. after the transmit data is written, set the sios to ?1? to start data transfer. the transmitted data is transferred from the sbid br to the shift register and output to the so pin in synchronous with the serial clock, starting from the least significant bit (lsb). when the transmit data is tran sferred to the shift register, the sbidbr becomes empty. the intsbi (buffer empty) interrupt request is generated to request new data. when the internal clock is used, the serial clock will stop and automatic-wait function will be initiated if new data is not loaded to the data buffer register after the specified 8-bit data is transmitted. when tr ansmit new data is written, automatic-wait function is canceled. when the external clock is used, data should be written to the sbidbr before new data is shifted. the so pin is ?1? from the time transmission starts until the first data bit is sent. when siof becomes ?0?, the shift register is cleared. so, output of an undefined value is not prevented at the start of the next transmission. the transfer speed is determined by the maximum delay time between the time when an interrupt request is generated and the time when data is written to the sbidbr by the interrupt service program. sck pin so pin shift register bit 0 (a) leading edge sck pin si pin shift register bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 76543210 * 7654321 ** 765432 *** 76543 **** 7654 ***** 765 ****** 76 ******* 7 bit 0 (b) trailing edge bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ******** 0 ******* 10 ****** 210 ***** 3210 **** 43210 *** 543210 ** 6543210 * 76543210
tmp88cs34/cp34 2006-07-06 88cs34-105 transmitting data is ended by cleaning the sios to ?0? by the buffer empty interrupt service program or setting the sioinh to ?1?. when the sios is cleared, the transmitted mode ends when all data is output. in order to confirm if data is surely transmitted by the program, set the siof (bit 3 in the sbisrb) to be sensed. the siof is cleared to ?0? when transmitting is comp lete. when the sioinh is set, transmitting data stops. the siof turns ?0?. when the external clock is used, it is also necessary to clear the sios to ?0? before new data is shifted; otherwise, dummy data is transmitted and operation ends. figure 2.9.24 transfer mode a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a b intsbi interrupt request sbidbr siof sck pin (output) so pin sios sef clear sios write transmitted data (a) internal clock a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a b intsbi interrupt request sbidbr siof sck pin (input) so pin sios sef clear sios write transmitted data (b) external clock
tmp88cs34/cp34 2006-07-06 88cs34-106 example: program to stop transmitting data. (when external clock is used) stest1: test (sbisrb) . sef ; if sef = 1 then loop jrs f, stest1 stest2: test (p5) . 3 ; if sck = 0 then loop jrs t, stest2 ld (sbicra) , 00000111b ; sios 0 figure 2.9.25 transmitted data hold time at end of transmit b. 8-bit receive mode set a control register to a receive mode and the sios to ?1? for switching to a receive mode. data is received from the si pin to the shift register in synchronous with the serial clock, starting from the least signific ant bit (lsb). when the 8-bit data is received, the data is transferred from the shift register to the sbidbr. the intsbi (buffer full) interrupt request is generated to request of reading th e received data. the data is read from the sbidbr by the interrupt service program. when the external clock is used, since shift operation is synchronized with the clock pulse provided externally, the received data should be read from sbidbr before next serial clock is input. if the received data is not re ad, further data to be received is canceled. when the internal clock is used, the automatic wait function is executed until received data is read from sbidbr. the maximum transfer speed when the external clock is used is determined by the delay time between the time when an interrupt requ est is generated and the time when received data is read. received data disappears if this data is not completely read before reception of the next data terminates. in this case, th e next data received is read. receiving data is ended by clearing the sios to ?0? by the buffer full interrupt service program or setting the sioinh to ?1?. when the sios is cleared, received data is transferred to the sbidbr in complete blocks. the received mode ends when the transfer is complete. in order to confirm if data is surely received by the program, set the siof (bit 3 in sbidbr) to be sensed. the siof is cleared to ?0? when receiving is complete. after confirming that receiving has ended, the last data is read. when the sioinh is set, receiving data stops. the siof turns ?0? (the received data becomes invalid, therefore no need to read it). note: when the transfer mode is switched, t he sbidbr contents are lost. in case that the mode needs to be switched, receiving data is concluded by clearing the sios to ?0?, read the last data, and then switch the mode. siof sck pin so pin bit 6 bit 7 t sodh = min 3.5/fc [s] (in normal mode, idle mode)
tmp88cs34/cp34 2006-07-06 88cs34-107 figure 2.9.26 receive mode (example: internal clock) a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 ab intsbi interrupt request sbidbr siof sck pin (output) si pin sios sef clear sios read received data read received data
tmp88cs34/cp34 2006-07-06 88cs34-108 c. 8-bit transmit/receive mode set a control register to a transmit/receive mode and write data to the sbidbr. after the data is written, set the sios to ?1? to star t transmitting/receiving. when transmitting, the data is output from the so pin on the leading edges in synchronous with the serial clock, starting from the least significant bit (lsb). wh en receiving, the data is input to the si pin on the trailing edges of the serial clock. 8-bit data is transferred from the shift register to the sbidbr, and the intsbi interrupt requ est occurs. the interrupt service program reads the received data from the data buffer re gister and writes data to be transmitted. the sbidbr is used for both transmitting and receiving. transmitted data should always be written after received data is read. when the internal clock is used, automatic-wait function is initiated until received data is read and next data is written. when the external clock is used, since the shift operation is synchronized with the external clock, received data is read and transmitted data is written before new shift operation is executed. the maximum transfer speed when the external clock is used is determined by the delay time between the time when an interrupt request is generated and the time when received data is read and transmitted data is written. when transmission starts, a value which is the same as the last bit of previously transmitted data is output from the time si of is set to ?1? until the falling edge of sck occurs. transmitting/receiving data is ended by cleaning the sios to ?0? by the intsbi interrupt service program or setting the sionh to ?1?. when the sios is cleared, received data is transferred to the sbidbr in complete blocks. the transmit/receive mode ends when the transfer is complete. in order to confirm if data is surely transmitted/received by the program, set the siof (bit 3 in sbisrb) to be sensed. the siof becomes ?0? after transmitting/receiving is complete. when the sionh is set, transmitting/receiving data stops. the siof turns ?0?. note: when the transfer mode is switched, t he sbidbr contents are lost. in case that the mode needs to be switched, conclude transmitting/receiving data by clearing the sios to ?0?, read the last data, and then switch the transfer mode. figure 2.9.27 transmit/receive mode (example: internal clock) a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 a c intsbi interrupt request sbidbr siof sck pin ( out p ut ) si pin sios sef clear sios write transmitted data (a) c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 bd read received data (c) write transmitted data (b) read received data (d) so pin
tmp88cs34/cp34 2006-07-06 88cs34-109 figure 2.9.28 transmitted data hold time at end of transmit/receive siof sck pin so pin bit 6 bit 7 in last transmitted word t sodh = min 4/fc [s] (in normal mode, idle mode)
tmp88cs34/cp34 2006-07-06 88cs34-110 2.10 remote control signal preprocesso r/external interrupt 3 input pin the remote control signal wavefo rm can be determined by inputting the remote control signal waveform from which the carrier wave was eliminated by the receive circuit to p30 (int3/rxin) pin. when the remote control signal preprocessor/external interrupt 3 pin is also used as the p30 port, set the p30 port output latc h to ?1?. when it is not used as the remote control signal preprocessor/external interrupt 3 input pin, it can be used for normal port. 2.10.1 configuration figure 2.10.1 remote control signal preprocessor 2.10.2 remote control signal preprocessor control when the remote control signal preprocessor is used, operating states are controlled and monitored by the following registers. interrupt requests also use the remote control signal preprocessor/external interrupt 3 input pin. remote control receive co ntrol register 1 (rxcr1) remote control receive co ntrol register 2 (rxcr2) remote control receive counter register (rxctr) remote control receive data buffer register (rxdbr) remote control receive status register (rxsr) when this pin is used for the external inte rrupt 3 input, set eint in rxcr1 to other than ?11?. receive bit counter value monitor ( rbctm ) crega fc/2 11 fc/2 10 fc/2 8 fc/2 7 fc/2 6 fc/2 5 fc/2 2 rnc int3 interrupt request int3/rxin polarity select remote control receive counter register (rxctr) selector noise canceller to rxcr1 interrupt select rncm receive bit counter int. 8-bit up- counter selector fc/2 6 fc/2 8 fc/2 10 fc/2 12 rcck rxcr2 measurement width select shift register match detect rpols 2 3 2 2 4 rmm remote control receive data buffer register (rxdbr) srm remote control receive control register 2 remote control receive control register 1 eint rcs
tmp88cs34/cp34 2006-07-06 88cs34-111 remote control receive control register 1 7 6 5 4 3 2 1 0 rxcr1 (00fe8h) rcck rpols eint rnc (initial value: 0000 0000) rcck 8-bit up-counter source clock select 00: fc/2 6 (hz) 01: fc/2 8 10: fc/2 10 11: fc/2 12 rpols remote control signal polarity select 0: positive 1: negative eint interrupt source select 00: rising edge 01: falling edge (at rpols = 0) 10: rising/falling edge 11: 8-bit receive end rnc noise canceler noise eliminating time select 001: 2 2 /fc 7 ? 1/fc (s) 010: 2 5 /fc 7 ? 1/fc 011: 2 6 /fc 7 ? 1/fc 100: 2 7 /fc 7 ? 1/fc 101: 2 8 /fc 7 ? 1/fc 110: 2 10 /fc 7 ? 1/fc 111: 2 11 /fc 7 ? 1/fc 000: noise canceler disable r/w note 1: fc: high-frequency clock [hz] note 2: after reset, rpols do not change the set value in t he receiving remote control signal. for setting interrupt edge and measurement data, use eint and rmm. remote control receive control register 2 7 6 5 4 3 2 1 0 rxcr2 (00fe9h) crega rcs rmcen rmm (initial value: 0000 0000) crega setting of detect time for match with 8-bit up-counter upper 4 bits match detect time (tth) = 16 crega/rcck [s] crega = 0h to fh example: crega = 2h, rcck = fc/2 6 [hz], at fc = 16 mhz, dv1ck = 0 tth = 128 [ s] rcs 8-bit up-counter start control 0: stop and counter clear 1: start rmcen remote control signal preprocesser enable/disable 0: disable 1: enable rmm measurement mode select (invalid when eint = ?10?) 00: 01: 10: 11: r/w note 1: fc: high-frequency clock [hz] note 2: when an interrupt source is set for rising/fa lling edge, low and high widths are forcibly measured separately. note 3: set crega (0h to fh) before eint sets to 8-bit receive end. figure 2.10.2 remote control receive control register 1, 2 refer to table 2.10.1
tmp88cs34/cp34 2006-07-06 88cs34-112 remote control receive counter register 7 6 5 4 3 2 1 0 rxctr (00feah) read only (initial value: 0000 0000) remote control receive data buffer register 7 6 5 4 3 2 1 0 rxdbr (00febh) read only (initial value: 0000 0000) remote control receive status register 7 6 5 4 3 2 1 0 rxsr (00fech) rbctm ovff srm rncm read only (initial value: 0000 * 000) rbctm receive bit counter value monitor ovff 8-bit up-counter overflow flag 0: no overflow 1: overflow srm data buffer register input monitor 0: upper 4 bits of 8-bit up-counter < crega 1: upper 4 bits of 8-bit up-counter crega rncm remote control signal monitor after passing through noise canceler read only note 1: * : don?t care figure 2.10.3 remote control receive counter r egister, data buffer register, status register
tmp88cs34/cp34 2006-07-06 88cs34-113 table 2.10.1 combination of interrupt source and measurement mode rpols eint rmm interrupt source measurement mode 00 10 00 11 01 10 01 11 10 ? 00 0 11 10 receive end 00 10 00 11 01 10 01 11 10 ? 00 1 11 10 receive end
tmp88cs34/cp34 2006-07-06 88cs34-114 2.10.3 noise elimination time setting the remote control receive circuit has a noise canceler. by setting rnc in rxcr1, input signals shorter than the fixed time can be eliminated as noise. table 2.10.2 noise elimination time setting (fc = 16 mhz) rnc minimum signal pulse width maximum noise width to be eliminated 000 ? ? 001 (2 5 + 5)/fc (2.31 s) (2 2 7 ? 1)/fc (1.69 s) 010 (2 8 + 5)/fc (16.31 s) (2 5 7 ? 1)/fc (13.88 s) 011 (2 9 + 5)/fc (32.31 s) (2 6 7 ? 1)/fc (27.88 s) 100 (2 10 + 5)/fc (64.31 s) (2 7 7 ? 1)/fc (55.88 s) 101 (2 11 + 5)/fc (128.3 s) (2 8 7 ? 1)/fc (111.9 s) 110 (2 13 + 5)/fc (512.3 s) (2 10 7 ? 1)/fc (447.9 s) 111 (2 14 + 5)/fc (1.024 ms) (2 11 7 ? 1)/fc (895.9 s) 2.10.4 operation (1) interrupts at rising, falling, or ri sing/falling edge, and measurement modes first set eint and rmm. next, set rcs to ?1?; the 8-bit up-counter is counted up by the internal clock. after measurement, the 8-bit up-counter value is saved in rxctr. then, the 8-bit up-counter is cleared, an int3 request is generated, and the 8-bit up-counter resumes counting. if the 8-bit up-counter overflows (ffh) before measurement is completed, an int3 request is generated and the overflow flag (ovff) is set to ?1?. then, the 8-bit up-counter is cleared. an overflow can be detected by reading ovff by the interrupt processing. to restart the 8-bit up-counter, set rcs to ?1?. setting rcs to ?1? zero-clears ovff.
tmp88cs34/cp34 2006-07-06 88cs34-115 figure 2.10.4 rising edge interrupt timing chart (rpols = 0) 8-bit up-counter value rxctr (b) rising edge cycle measurement (c) high width measurement rcck i ? 3 i ? 2 i ? 1 i 1 2 3 m ? 2 m ? 1 m n ? 2 n ? 1 n n i 8-bit up-counter value int3 request rncm rxctr (a) low width measurement 1 2 3 1 2 3 i ? 3 i ? 2 i ? 1 i 1 2 3 i m ? 4 m ? 3 m m 1 2 3 4 5 6 7 8 m ? 2 m ? 1 8-bit up-counter value rxctr i ? 3 i ? 2 i ? 1 i 1 2 3 m ? 2 m ? 1 m n ? 2 n ? 1 n m 1 2 3 1 2 3
tmp88cs34/cp34 2006-07-06 88cs34-116 figure 2.10.5 falling edge interrupt timing chart (rpols = 0) rcck i ? 3 i ? 2 i ? 1 i 1 2 3 m ? 2 m ? 1 m n ? 2 n ? 1 n n i 8-bit up-counter value int3 request rncm rxctr (a) high width measurement 8-bit up-counter value rxctr (b) falling edge cycle measurement (c) low width measurement 1 2 3 1 2 3 i ? 3 i ? 2 i ? 1 i 1 2 3 i m ? 4 m ? 3 m m 1 2 3 4 5 6 7 8 m ? 2 m ? 1 8-bit up-counter value rxctr i ? 3 i ? 2 i ? 1 i 1 2 3 m ? 2 m ? 1 m n ? 2 n ? 1 n m 1 2 3 1 2 3
tmp88cs34/cp34 2006-07-06 88cs34-117 figure 2.10.6 rising/falling edge interrupt timing chart rcck i ? 3 i ? 2 i ? 1 i 1 2 3 m ? 2 m ? 1 m n ? 2 n ? 1 n n i 8-bit up-counter value int3 request rncm rxctr (a) high and low width measurement 1 2 3 1 2 3 m
tmp88cs34/cp34 2006-07-06 88cs34-118 (2) 8-bit receive end interrupts and measurement modes by determining one-cycle remote control signal as one-bit data set to ?0? or one-pulse width remote control signal as one-bit data se t to ?1?, an int3 request is generated after 8-bit data is received. when ?0? is determined , this means the upper four bits in the 8-bit up-counter have not reached the crega value. when ?1? is determined, this means the upper four bits in the 8-bit up-counter have reached or exceeded the crega value. the 8-bit up-counter value is saved in rxctr after one bit is determined. the determined data is saved, bit by bit, in rxdbr at the rising edge of the remote control signal (when rpols = 1, falling edge). the number of bits saved in rxdbr is counted by the receive bit counter and saved in rbctm. rbctm is set to ?0001b? at the rising edge of the input (when rpols = 1, falling edge) after the int3 request is generated. note: * : valid only when 8 bits are received. figure 2.10.7 overflow interrupt timing chart fe ff 1 n ? 1 n rbctm * int3 request ovff 8-bit up-counte r value rcck rncm n ? 1 n rcs receive bit counter value * set to ?1? by command
tmp88cs34/cp34 2006-07-06 88cs34-119 figure 2.10.8 8-bit receive end interrupt timing chart (rpols = 0) crega (a) rising edge cycle measurement 01 8-bit up-counter value 80h 1 [application] low width measurement 8 7 receive bit counte r value int3 request srm rxdbr 6 1 0 8-bit receive end interrupt setting rncm 03 02 04 06 05 07 01 02 07 02 01 03 05 04 06 08 07 09 0b 0a 0c 0e 0d 0f 11 10 02 01 1
tmp88cs34/cp34 2006-07-06 88cs34-120 table 2.10.3 count clock for remote control preprocessor circuit (at fc = 16 mhz) count clock (rcck) resolution [ s] maximum setting time [ms] 00 4 1.024 01 16 4.096 10 64 16.38 11 256 65.53
tmp88cs34/cp34 2006-07-06 88cs34-121 2.11 8-bit ad converter (adc) the tmp88cs34/cp34 has a 8-bit successive approximation type ad converter. figure 2.11.1 shows the circuit configuration of the ad converter. the ad converter includes control registers adccra and adccrb, conversion result registers adcdr1 and adcdr2, a da converter, a sample hold circuit, a comparator, and sequential transducer circuit. to use p5 and p6 as analog inputs, clear the output latch for p5 and p6 to ?0?. also, clear the input/output control registers (p5cr1 and p6cr) to ?0?. p63 to p61 output ?0? after a reset. when these dual-function pins are used as ports, be sure to set orp6s2 to ?1?. 2.11.1 configuration figure 2.11.1 ad converter (adc) 2.11.2 control register the following register are used foe ad converter. ? ad converter control register 1 (adccra) ? ad converter control register 2 (adccrb) ? ad conversion result register (adcdr1/adcdr2) (1) ad converter control register 1 (adccra) adccra control ad conversion start, ad op eration mode select, analog input control and analog input channel select. (2) ad converter control register 2 (adccrb) adccrb control ad conversion time select. (3) ad conversion resu lt register (adcdr1) ad conversion result is stored after end of conversion. (4) ad conversion resu lt register (adcdr2) for monitoring stat us of conversion. figure 2.11.2 and figure 2.11.3 show ad converter control register. shift clock reference voltage a nalog comparator a nalog input multiplexer amd 8 vss a in0 y en 8 6 vdd da converter successive approximate circuit p5cr, p6cr control circuit a b en a in1 a in4 e f a in5 s a ds sample hold circuit a d8trg external trigger signal p5, p6 port input/output control register adccra adrs adccrb 2 ack 3 adcdr1, adcdr2 eocf adbf intadc sain ainds ad converter control register ad conversion result register 3
tmp88cs34/cp34 2006-07-06 88cs34-122 ad converter control register 1 7 6 5 4 3 2 1 0 adccra (0000eh) adrs amd ainds ?0? sain (initial value: 0001 0000) adrs ad conversion start the adrs bit is automatically cl eared after starting ad conversion. during ad conversion, setting adrs to ?1? initializes the adrs bit and resets conversion. 0: ? 1: ad conversion restart amd ad operating mode select 00: stop mode 01: software start mode 10: trigger start mode 11: reserved ainds analog input control 0: analog input enable 1: analog input disable sain analog input channel select 000: selects ain0 001: selects ain1 010: selects ain2 011: selects ain3 100: selects ain4 101: selects ain5 110: ? 111: ? r/w note 1: select analog input when ad converter stops. note 2: when the analog input is all use di sabling, the ainds should be set to ?1?. note 3: during conversion, do not perform output instru ction to maintain a precision for all of the pins. and port near to analog input, do not i nput intense signaling of change. note 4: the adrs is automatically cl eared to ?0? after starting conversion. note 5: always set bit 3 in adccra to ?0?. note 6: do not set adrs (bit 7 in adccra) to ?1? during ad conversion. re-set it after confirming with eocf (bit 5 in adcdr2) that the conversion is completed or a fter generating an interrupt signal (intadc) (by the interrupt processing routine or the like). note 7 in the trigger mode, the system does not accept the second and subsequent trigger s after accepting the first trigger for starting ad conversion. to restart ad c onversion by a trigger, set amd (bits 6 and 5 in adccra) to ?00? and then put the system in trigger start mode again (with amd = ?10?). note 8: when the system enters stop mode, ad conv erter control register 1 (adccra) is initialized. re-set this register after the system reenters normal mode. ad converter control register 2 7 6 5 4 3 2 1 0 adccrb (0000fh) ?0? ?1? ack ?0? (initial value: ** 0 * 000 * ) dv1ck = 0 dv1ck = 1 ack conversion time fc = 16 mhz fc = 8 mhz fc = 16 mhz fc = 8 mhz 000 001 010 reserved 011 156/fc [s] ? 19.5 ? 39 100 312/fc [s] 19.5 39.0 39 78 101 624/fc [s] 39.0 78.0 78 156 110 1248/fc [s] 78.0 ? 156 ? ack ad conversion time select 111 reserved r/w note 1: do not use setting except the above list. note 2: set conversion time by analog reference voltage (v dd ) as follows. v dd = 4.5 to 5.5 v (15.6 or more) note 3: always set bit 0 and bit 5 in adccrb to ?0? and set bit 4 in adccrb to ?1?. note 4: when a read instruction for adccrb, bit 6 to 7 in adccrb read in as undefined data. note 5: fc: high-frequency clock [hz] note 6: when the system enters stop mode, ad conv erter control register 2 (adccra) is initialized. re-set this register after the system reenters normal mode. figure 2.11.2 ad converter control register
tmp88cs34/cp34 2006-07-06 88cs34-123 ad conversion result register 7 6 5 4 3 2 1 0 adcdr1 (00031h) ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 (initial value: 0000 0000) 7 6 5 4 3 2 1 0 adcdr2 (00032h) ? ? eocf adbf ? ? ? ? (initial value: ** 00 **** ) eocf ad conversion end flag 0: under conversion or before conversion 1: end of conversion adbf ad conversion busy flag 0: during stop of ad conversion 1: during ad conversion read only note 1: the eocf is cleared to ?0? when reading the adcdr1. therefore, the ad conversion result shoul d be read to adcdr1 more first than adcdr2. note 2: adbf is set to ?1? by starting ad conversion and cleared to ?0? by end of ad conversion. additionally, adbf is cleared to ?0? by setting amd = ?00? in adccr2 or entering to the stop mode. note 3: if the pin is used as an analog input pin, reset th e dgine register to ?0? to disable all inputs other than analog inputs. figure 2.11.3 ad converter result register 2.11.3 ad converter operation the high side of an analog reference voltag e is applied to vdd, and the low side is applied to vss pin. dividing a reference voltage between vdd and vss to the voltage corresponding to a bit by a rudder resistance and comparing it with the analog input voltage converts the ad. table 2.11.1 ad converter operation mode mode function ad converter disable mode ad converter stop mode. this mo de is always used to change modes. software start mode single ad conversi on of 1 channel which specifies input. trigger start mode single ad conversi on of 1 channel which specifies input (ad8trg) from key-on-wake- up circuit as a trigger. 2.11.4 interrupt interrupt request signal occur at the timing when the eocf bit is set to ?1?.
tmp88cs34/cp34 2006-07-06 88cs34-124 2.11.5 ad converter operation modes when the mcu places in the stop mode during the ad conversion, the conversion is stopped and the adcdr2 content becomes indefinite. after returning from the stop mode, the eocf and intadc does not occur. therefore, the ad conversion must be restarted after returning from the stop mode. figure 2.11.4 ad conversion timing chart (1) ad conversion in stop mode when the ad converter stop mode is specified during ad conversion, the ad conversion is stopped immediately. the ad conversion is not implemented, so the undefined value is not written to the ad conversion result register. the ad conversion start commands which occur is the ad converter stop mode are ignored. this mode is automatically selected by reset. this mode is used to change the ad converter operation mode. (2) single mode when the amd (bit 6, 5 to in adccra) set to ?01?, the ad conversion signal mode. this mode does ad conversion of single channel, and conversion result is stored in adcdr1. the eocf (bit 5 in adcdr2) is set to ?1? at end of one conversion, and an intcrrupt request signal occurs. the eocf is cleared to ?0? by read ing the ad conversion registers. but when the ad conversion is restarted before the adcdr is read, the eocf is cleared to ?0? and the last ad conversion result is maintained till next conversion end. do not set adrs (bit 7 in adccra) during ad conversion. again set it after confirming with eocf (bit 5 in adcdr2) that the conversion is completed or after generating an interrupt signal (intadc) (by the interrupt processing routine or the like). figure 2.11.5 single mode read start read start start invalid result result invalid invalid a ds a dcdr2 eocf processing invalid a d conversion r esult a ds a dcdr2 eocf conversion time (reference to adccrb register) a dbf start read
tmp88cs34/cp34 2006-07-06 88cs34-125 example: the ad conver sion starts after 19.5 s (at fc = 16 mhz) and ain4 pin are selected as the conversion time and the analog input channel. confirming the eocf, the converted value is read out, and the 8 bits data is stored to address 009eh in ram. the operation mode is a signal mode. ; ain select ld (p5), 00000000b ld (p5cr1), 00000000b ld (p6), 00000000b ld (p6cr), 00000000b ld (adccra), 00100100b ; selects ain4, selects the software start mode ld (adccrb), 00011000b ; selects the conversion time and the operation mode. ; ad convert start set (adccra) . 7 ; adrs = 1 sloop: test (adccr2) . 5 ; eocf = 1 ? jrs t, sloop ; result data read ld (9eh), (adcdr1) (3) trigger start mode the ad conversion of a specified single channel is executed when input (ad8trg) from key-on-wake-up circuit is set as trigger, the conversion result is stored in the adcdr1. the eocf (bit 5 in adcdr2) is set to ?1? at end of one conversion, and an interrupt request signal occurs. it needs to be set the stop mode by bit 5 to 6 in adccra before the ad conversion is executed again. 2.11.6 analog input voltage and ad conversion result the analog input voltage is corresponded to the 8-bit digital value converted by the ad as shown in figure 2.11.6. figure 2.11.6 analog input voltage and ad conversion result (typ.) 0 1 2 3 253 254 255 256 01h 02h 03h fdh feh ffh a d conversion result v dd ? v ss 256 analog input voltage
tmp88cs34/cp34 2006-07-06 88cs34-126 2.11.7 stop modes during ad conversion when standby mode (stop mode) is entered forcibly during ad conversion, the ad convert operation is suspended and the ad converter is initialized. (adccra and adccrb are initialized to initial value.) also, the conversion result is indeterminate. (conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering standby mode.) when restored from standby mode, ad conversion is not automatically restarted, so it is necessary to restart ad conversion after setting adccra and adccrb. note that since the analog reference voltage is automatically disconnected, there is no possibility of current flowing into the analog reference voltage. 2.11.8 notice of ad converter (1) analog input voltage range voltage range of analog input (ain0 to ain5) must be forced from v ss to v dd . if input voltage of which out of range is forced to analog input pin, ad conversion result to unknown. also, this cause other analog input pin unstable. (2) i/o port with analog input analog input pins (ain0 to ain5) are also i/o port. during ad conversion using any analog input pin, don?t operate other i/o port with analog input. because, ad accuracy would be worse. also, other electrically swinging port without analog input may cause noise to near analog input pin. (3) reduce to noise figure 2.11.7 is shown as internal eq uivalent circuit of analog input pin. increasing output impedance of analog input supply, cause noise or other non-good condition. therefore, output impedance of analog input supply must be less than 5k . and we recommend to connect capacitance to analog input pin. figure 2.11.7 analog input equivalent circuit and analog input pin a nalog input supply impedance 5 k (max.) internal capacitance c = 22 pf (typ.) internal resistance r = 5 k ( t yp . ) a nalog converte r ainx da converter
tmp88cs34/cp34 2006-07-06 88cs34-127 2.12 key-on-wake-up in this mcu the idle mode is also released by low active port inputs. the low input voltage is regulated higher than the other normal ports. therefore the ports can be enabled by analog input level. 2.12.1 configuration figure 2.12.1 key-on-wake-up control circuit 2.12.2 control p53 to p56 and p60, p61 ports can be contro lled by idle control register (idlecr). it can be configured as enable/disable in one-bit unit. when those pins are used by idle mode release, those pins must be set input mode (p5cr1, p5 , p6cr, p6, adccra). idle mode is controlled by system control register 2 (syscr2) an d maskable interrupts. after the individual enable flag (ef5) is se t to ?1?, the idle mode must starts. when enabled port input generates intkwu interrupt, the idle mode is released. low level input voltage in those ports is regulated to less than vdd 0.65 (v). idle port monitorring register (idlein) can be used to check state of ports. intaden can enable to generate ad8trg, which is used as trigger of ad converter trigger start mode. noise reject circuit eliminate noise, which is less than 24 s period. ad converter vil vdd 0.65 port p53 port p54 port p55 port p56 port p60 port p61 a in1 a in2 a in3 a in4 a in5 noise reject circuit intkwu idle0 in idle1 in idle2 in idle3 in * * idle4 in idle5 in idle0 en idle1 en idle2 en idle3 en intad en * idle4 en idle5 en ad8trg ain0 1 kwu 2 kwu 3 kwu 4 kwu 5 kwu 0 kwu idlecr (00fd0h) idlein (00fd0h)
tmp88cs34/cp34 2006-07-06 88cs34-128 idle control register 7 6 5 4 3 2 1 0 idlecr (00fd0h) intad en * idle5 en idle4 en idle3 en idle2 en idle1 en idle0 en (initial value: 0 * 00 0000) intaden generation of ad8trg 0: disable 1: enable idle5en release idle mode by 5 kwu 0: disable 1: enable idle4en release idle mode by 4 kwu 0: disable 1: enable idle3en release idle mode by 3 kwu 0: disable 1: enable idle2en release idle mode by 2 kwu 0: disable 1: enable idle1en release idle mode by 1 kwu 0: disable 1: enable idle0en release idle mode by 0 kwu 0: disable 1: enable write only note : * : don?t care idle port monitorring register 7 6 5 4 3 2 1 0 idlein (00fd0h) * * idle5 in idle4 in idle3 in idle2 in idle1 in idle0 in (initial value: ** 00 0000) idle5in input level of 5 kwu 0: ?0? detect 1: ?1? detect idle4in input level of 4 kwu 0: ?0? detect 1: ?1? detect idle3in input level of 3 kwu 0: ?0? detect 1: ?1? detect idle2in input level of 2 kwu 0: ?0? detect 1: ?1? detect idle1in input level of 1 kwu 0: ?0? detect 1: ?1? detect idle0in input level of 0 kwu 0: ?0? detect 1: ?1? detect read only note : * : don?t care figure 2.12.2 key-on-wake-up control register
tmp88cs34/cp34 2006-07-06 88cs34-129 2.13 pulse width modulat ion circuit output the tmp88cs34/cp34 has four 12-bit resolution pwm output channels including two 14-bit resolution selectable. da converter output can easily be obtained by connecting an external low-pass filter. pwm outputs are multiplexed with general purpose i/o ports as; p40 ( pwm0 ) to p43 ( pwm3 ). pwm output is negative logic. when these ports are used pwm outputs, the corresponding bits of p4, p5 output latches and input/output control latches should be set to ?1?. in stop mode, pwm output pin keeps high-lev el. when operation mode is changed from stop mode to normal mode, pwm control register (pwmcr1a, pwmcr1b) are initialized. 2.13.1 configuration 12-bit resolution pwm output figure 2.13.1 pwm output circuit 14 13 12 11 10 9 8 7 6 543 21 clock internal counter (1) internal counter (2) (fc/2 or fc/2 2 ) 0 pwm 1 pwm 3 pwm 2 pwm additional pulse generate circuit 13 8 pwm data latch 7 0 pwmdbr1 5 0 transfer buffer (the upper) 7 0 pwm data latch 7 0 transfer buffer (the lower) 2 0 pwmcr1b 60 pwmcr1a pwm control register 1b pwm control register 1a s r compare circuit all ?0?
tmp88cs34/cp34 2006-07-06 88cs34-130 2.13.2 pwm output wave form (1) pwm0 to pwm1 outputs pwm0 and pwm1 output can be selected 12-bit or 14-bit resolution pwm outputs. 1. 12-bit resolution pwm output when these are used as 12-bit pwm output, one period is t m = 2 13 /fc [s] (when dv1ck = 0) and t m = 2 14 /fc [s] (when dv1ck = 1) and sub-period is t s = t m /16. the lower 8-bit of the pwm data latch controls the low level pulse width with a cycle of t s . the lower 8-bit of the pwm data latch is n (n = 1 to 255), the low level pulse width with a cycle becomes n x t 0 [s] (t 0 = 2/fc [s] when dv1ck = 0, t 0 = 4/fc [s] when dv1ck = 1). the upper 4-bit of the pwm data latch controls a position to output the additional pulses. when the upper 4-bit of the pwm data latch is m, the additional pulses are generated in each of m periods ou t of 16 periods contained in a t m period. the relationship between the 4-bit data and the position of t s period where the additional pulses are generated is shown in table 2.13.1. table 2.13.1 the addition pulse (12 bit mode) bit position of the lower 4 bits of pwmdrxh bit 11 bit 10 bit 9 bit 8 relative position of t s in t m period where the additional pulse is generated. (number of t s (i) is listed) a) 0 0 0 0 no additional pulse b) 0 0 0 1 8 c) 0 0 1 0 4, 12 d) 0 1 0 0 2, 6, 10, 14 e) 1 0 0 0 1, 3, 5, 7, 9, 11, 13, 15 note 1: the bit positions of a) to e) can be combined. note 2: if the low order eight bits for the pwm data latch are set to ?ffh?, be sure to set the high order four bits for this latch to ?00h?. 2. 14-bit resolution pwm output when these are used as 14-bit pwm output, one period is t m = 2 15 /fc [s] (when dv1ck = 0) and t m = 2 16 /fc [s] (when dv1ck = 1) and sub-period is t s = t m /64. the lower 8-bit of the pwm data latch controls the low level pulse width with a cycle of t s . the lower 8-bit of the pwm data latch is n (n = 1 to 255), the low level pulse width with a cycle becomes n x t 0 [s] (t 0 = 2/fc [s] when dv1ck = 0, t 0 = 4/fc [s] when dv1ck = 1). the upper 6-bit of the pwm data latch controls a position to output the additional pulses. when the upper 6-bit of the pwm data latch is m, the additional pulses are generated in each of m periods ou t of 64 periods contained in a t m period. the relationship between the 6-bit data and the position of t s period where the additional pulses are generated is shown in table 2.13.2. table 2.13.2 the addition pulse (14 bit mode) bit position of the lower 6 bits of pwmdrxh bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 relative position of t s in t m period where the additional pulse is generated. (number of t s (i) is listed) a) 0 0 0 0 0 0 no additional pulse b) 0 0 0 0 0 1 32 c) 0 0 0 0 1 0 16, 48 d) 0 0 0 1 0 0 8, 24, 40, 56 e) 0 0 1 0 0 0 4, 12, 20, 28, 36, 44, 52, 60 f) 0 1 0 0 0 0 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 g) 1 0 0 0 0 0 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63 note 1: the bit positions of a) to g) can be combined. note 2: if the low order eight bits for the pwm data latch are set to ?ffh?, be sure to set the high order six bits for this latch to ?00h?.
tmp88cs34/cp34 2006-07-06 88cs34-131 (2) pwm2 to pwm3 outputs pwm2 and pwm3 output are 12-bit resolution pwm outputs. one period is t m = 2 13 /fc [s] (when dv1ck = 0) and t m = 2 14 /fc [s] (when dv1ck = 1) and sub-period is t s = t m /16. the lower 8-bit of the pwm data latch controls the low level pulse width with a cycle of t s . the lower 8-bit of the pwm data latch is n (n = 1 to 255), the low level pulse width with a cycle becomes n x t 0 [s] (t 0 = 2/fc [s] when dv1ck = 0, t 0 = 4/fc [s] when dv1ck = 1). the upper 4-bit of the pwm data latch controls a position to output the additional pulses. when the upper 4-bit of the pwm data latch is m, the additional pulses are generated in each of m periods ou t of 16 periods contained in a t m period. the relationship between the 4-bit data and the position of t s period where the additional pulses are generated is shown in table 2.13.1. 14-bit resolution pwm mode: the additional pulse ts (1) and ts (63) 12-bit resolution pwm mode: the additional pulse ts (1) and ts (15) note 1: if the pulse width is set to ?00h?, pw m will not operate. its output will remain high. note 2: if the pulse width is set to ?ffh?, settings fo r additional pulses cannot be made. be sure to set the pulse width to ?00h?. figure 2.13.2 pwm output wave form t s (63) t 0 t 0 t s (1) t s (0) t m = 64 t s n t 0 pulse width = n t 0 pulse width = (n + 1) t 0 0 pwm to 1 pwm 2 pwm to 3 pwm t s (15) t 0 t 0 t s (1) t s (0) n t 0 pulse width = n t 0 pulse width = (n + 1) t 0
tmp88cs34/cp34 2006-07-06 88cs34-132 2.13.3 control pwm output is controlled by pwm control register (pwmcr1a, pwmcr1b) and pwm data buffer register (pwmdbr1). pwm control register 1a 7 6 5 4 3 2 1 0 resolution pwmcr1a (00028h) ? abort1 start3 start2 start1 start0 1 0 (initial value: * 000 0000) abort1 abort pwm operation of channel 3 to 0 0: operation 1: pwm abort (pwm outputs are fixed to a high-level.) start3 start channel 3 0: stop 3 pwm 1: start 3 pwm start2 start channel 2 0: stop 2 pwm 1: start 2 pwm start1 start channel 1 0: stop 1 pwm 1: start 1 pwm start0 start channel 0 0: stop 0 pwm 1: start 0 pwm resolution1 select channel 1 resolution 0: 14-bit resolution 1: 12-bit resolution resolution2 select channel 0 resolution 0: 14-bit resolution 1: 12-bit resolution write only note 1: * : don?t care note 2 after set the abort1 to ?1?, the abort1 is cleared to ?0? automatically. note 3: pwmcr1a is write-only register and cannot be used with any of the read-modify-write instructions such as set, clr, etc. pwm control register 1b 7 6 5 4 3 2 1 0 pwmchs1 pwmcr1b (00029h) pwmhl (initial value: **** * 000) pwmchs1 select the pwm data latch of 12-bit pwm channels 00: channel 0 01: channel 1 10: channel 2 11: channel 3 pwmhl select upper or lower data transfer buffer (pwmdbr1) 0: lower 8-bit 1: upper 4-bit or 6-bit write only note 1: * : don?t care note 2: pwmcr1b is write-only register and cannot be used with any of the read-modify-write instructions such as set, clr, etc. pwm data buffer register 1 7 6 5 4 3 2 1 0 pwmdbr1 (0002ah) write only (initial value: 0000 0000) note 1: pwmdbr1 is write-only register and cannot be used with any of the read-modify-write instructions such as set, clr, etc. note 2: when operation mode is changed from stop mode to normal mode, pwmcr1a, pwmcr1b are initialized. figure 2.13.3 pwm control register 1a /1b and pwm data buffer register 1
tmp88cs34/cp34 2006-07-06 88cs34-133 binary counter control register 7 6 5 4 3 2 1 0 cgcr (00030h) ?0? ?0? dv1ck ?0? ?0? ?0? ?0? ?0? (initial value: 0000 0000) dv1ck select of input clock to 1st divider 0: fc/4 1: fc/8 r/w note 1: * : don?t care note 2: the all bits except dv1ck are cleared to ?0?. figure 2.13.4 divider control register (1) internal counter the internal counter of pwm outputs is a free running counter. the all bits of counter are set to ?1? and are not counted up at one of the following conditions. 1. during reset 2. the operation mode is changed to stop mode. 3. setting abort1 to ?1?. 4. the start3 to 0 are ?0? in 12-bit pwm outputs. 5. the lower 8-bit of pwm data latch in 12-bit pwm outputs is ?00h?. the pwm data latch in 7-bit pwm outputs is ?00h?. (2) outputs control and programming of pwm data the pwm outputs are fixed to a high-level im mediately when the abort1 is set to ?1?. the pwm outputs starts the operation when the startx (x: 0 to 3) is set to ?1?. the data from the transfer buffer to a pwm da ta latch is transferred when the all bits of internal counter are set to ?1?. therefore, the data is transferred to a pwm data latch immediately when the internal counter is initialized. and the data is transferred to a pwm data latch at the beginning of the next cycle wh en all bits of the internal counter are not set to ?1?. the sequence of writing the output data to pwm data latches is shown as follows; 1. pwm0 to pwm1 a. write the channel number of pwm data latch to pwmchs1 (bit 2 and 1 in pwmcr1b) and clear pwmhl (bit 0 in pwmcr1b) to ?0?. b. write the lower 8-bit pwm output data to pwmdbr1. c. write the channel number of pwm data latch to pwmchs1 and set pwmhl to ?1?. d. write the upper 4-bit or 6-bit pwm output data to pwmdbr1. e. select the resolution of pwm output to resolutionx (x: 0, 1) (bit 0 and 1 in pwmcr1a) and set startx (x: 0, 1) (bit 2 and 3 in pwmcr1b) to ?1?. note: pwm output data must be write to pwmd br1 in the order of the lower 8-bit pwm output data, the upper 4-bit (or 6-bit) pwm output data. if the upper 4-bit (or 6-bit) pwm output data is write to pwmdbr1, the lower 8-bit pwm output data is not changed (except when lower 8-bit pwm output data is ?00h?.).
tmp88cs34/cp34 2006-07-06 88cs34-134 2. pwm2 to pwm3 a. write the channel number of pwm data latch to pwmchs1 and clear pwmhl to ?0?. b. write the lower 8-bit pwm output data to pwmdbr1. c. write the channel number of pwm data latch to pwmchs1 and set pwmhl to ?1?. d. write the upper 4-bit pwm output data to pwmdbr1. e. set startx (x: 2, 3) to ?1?. 1) data transfer timing and stop/abort timing (x: 0 to 3) 2) restart timing when operating for 1ch or more 3) restart timing after all channels stop figure 2.13.5 wave form of pwm0 to pwm3 note: pwm output data must be write to pwmdbr1 in the order of the lower 8-bit pwm output data, the upper 4-bit (or 6-bit) pwm output data. if the upper 4-bit (or 6-bit) pwm output data is write to pwmdbr1, the lower 8-bit pwm output data is not changed (except when lower 8-bit pwm output data is ?00h?.). t s t s t m t m m t 0 n t 0 writing pwmdbr1 ( data m to n ) t s startx = 0 or the lower 8-bit of pwm data latch = 00h t s a bort1 = 1 or stop mode pwmx pwmx pwmx restarting pwm1 restarts after one cycle. 0 pwm 1 pwm t m t m start command t m t m
tmp88cs34/cp34 2006-07-06 88cs34-135 example: at fc = 16 mhz, dv1ck = 0 pwm0 pin outputs a 14-bit resolution pwm wave form with a low-level of 32 s width and no additional pulse. pwm1 pin outputs a 12-bit resolution pwm wave form with a low-level of 16 s width and no additional pulse. ld (cgcr), 00h ; dv1ck = 0 ld (pwmcr1b),00h ; select the lower 8-bit of pwm0 output data latch ld (pwmdbr1),80h ; 32 s 4/fc = 80h ld (pwmcr1b),01h ; select the upper 6-bit of pwm0 output data latch ld (pwmdbr1),00h ; no additional pulse = 00h ld (pwmcr1b),02h ; select the lower 8-bit of pwm0 output data latch ld (pwmdbr1),40h ; 16 s 4/fc = 40h ld (pwmcr1b),03h ; select the upper 4-bit of pwm0 output data latch ld (pwmdbr1),01h ; additional pulse (ts (8) ) = 01h ld (pwmcr1a),0dh ; start pwm0 and pwm1 , pwm0 : 14-bit resolution, pwm1 : 12-bit resolution
tmp88cs34/cp34 2006-07-06 88cs34-136 2.14 on-screen display (osd) circuit the tmp88cs34/cp34 features a bu ilt-in on-screen display circui t used to display characters and symbols on the tv screen. there are 383 charac ters of mono font and 96 characters of color font (447 characters of mono font and 64 charac ters of color font) and any characters can be displayed in an area of 32 columns 12 lines (include 2 columns for solid space). with an osd interrupt, additional lines can be displayed. osd circuit functions are as follows : (1) number of character fonts : mo no font 383 and color font 96 mono font 447 and color font 64 (2) number of display characters : 384 (32 columns 12 lines). (3) composition of character : horizontal 16 vertical 18 dots (4) character sizes : 3 kinds for larg e, middle and small characters (selectable line by line) (5) character ornamentation function fringing function : mono font smoothing function : mono font slant function (italics) : mono font blinking function underline (6) solid space (7) area plane function : 2 planes (8) full-raster blanking function (9) display colors character colors : 8 or 27 colors (s electable character by character) fringe color : 8 or 27 colors (selectable page by page) background color : 8 or 27 colo rs (selectable page by page) area plane color : 8 or 27 colors (selectable each of 2 planes) raster color : 8 or 27 colors (selectable page by page) (10) display position : 256 horizontal steps and 625 vertical steps for code plane : 512 horizontal steps and 625 vertical steps for area plane (11) window function : 625 vertical steps (12) half transparency output function (13) 27 colors display function (14) color palette (15) pal100/ntsc120 display note: the function of the osd circuit don?t meet the requirements of on-screen display functions of closed caption decoders based on fcc standards.
tmp88cs34/cp34 2006-07-06 88cs34-137 the tmp88cs34/cp34 outputs osd through 3 planes; code, area, and raster. 3 planes function independently. in addition, they are displayed simultaneously. there is the priority among these 3 planes, so they are displayed on a screen according to the priority. these 3 planes have the priority such as code > area > raster. 1. code plane osd character is displayed on the code plane. the code plane consists of 32 characters 1 row and a total of 12 planes. the 12 planes have the priority such as code 1 > code 2 > ??? > code 11 > code 12. on the code plane, characters of 16 18 dots is displayed. these fonts are called characters, and read from character rom and display memory through the character code on the display memory. 2. area plane the area on a screen is displayed on the area plane. the area plane can display 2 square areas of any size by specifying coordinates. the 2 planes have the priority such as area plane 1 > area plane 2.
tmp88cs34/cp34 2006-07-06 88cs34-138 2.14.1 osd configuration shown below is the block diagram of the osd circuit. figure 2.14.1 osc block diamgram 2.14.2 monochrome and color fonts the tmp88cs34 can display both monochrome and color fonts. the monochrome font is intended for monoch romic display. each character in the font consists of 18 vertical 16 horizontal dots. for the color font, each display dot in each character can be specified separately for r (red), g (green), and b (blue). each character consists of 18 vertical 16 horizontal dots. the monochrome and color fonts ca n be mixed on one display row. jitter elimina- tion circuit p70 ( hd ) horizontal position decoder vertical position counter vertical position decoder horizontal position counter lc oscillation control display ram 32 12 16 bits 6 kbytes caracter rom 384 16 18 bits 96 16 18 3 bits 24 kbyte (mono) + 18kbyte osd control output signal selecter b y/bl i r g interrupt control circuit tlcs-870/x cpu rom: 64 kbytes ram: 1.5 kbytes clock generator xin xout oscillator for osd osc1 osc2 b y/bl i r g p71 ( vd ) to the lower row (a) display output control output timing synchronization circuit p57 (i) p67 (y/bl) p66 (b) p65 (g) p64 (r) color palette circuit intermediate-value enable signal data signal osd control b y/bl i r g (a) osd interrupt
tmp88cs34/cp34 2006-07-06 88cs34-139 2.14.3 character rom and display memory (1) character rom the character rom incorporates 383 different monochrome font character data items and 96 different color font character data item s (447 different monochrome font character data items and 64 different color font characte r data items). users can define font data. each monochrome character rom data item consists of 16 18 dots. each monochrome font dot corresponds to one character rom bit. a value of ?1? represents a display state, and a value of ?0? represents a non-display state. each color font character rom data item consists of 16 18 dots for red, 16 18 dots for green, and 16 18 dots for blue. each color font do t corresponds to three character rom bits (with each bit correspondin g to red, green, or blue). the character rom start address for each character code is calculated as listed in table 2.14.1. table 2.14.1 number of character patterns and character codes number of usable character patterns usable character codes monochrome font color font monochrome font color font register for switching number o f fonts, romach (bit 4 in ordon) 383 96 1 to 17fh 180h to 1dfh 0 447 64 1 to 17fh, 1c0h to 1ffh 180h to 1bfh 1 table 2.14.2 monochrome/color f ont character rom start address romach character rom start address 0 monochrome font (cra = 1 to 17fh) character rom start address = cra 40h + 20000h color font (cra = 180h to 1dfh) character rom start address for red = cra 40h + 26000h character rom start address for green = cra 40h + 27800h character rom start address for blue = cra 40h + 29000h 1 monochrome font character rom start address = cra 40h + 20000h (cra = 1 to 17fh) character rom start address = cra 40h + 27000h (cra = 1c0h to 1dfh) character rom start address = cra 40h + 28c00h (cra = 1e0h to 1efh) character rom start address = cra 40h + 2a400h (cra = 1f0h to 1ffh) color font (cra=180h to 1bfh) character rom start address for red = cra 40h + 26000h character rom start address for green = cra 40h + 27800h character rom start address for blue = cra 40h + 29000h figure 2.14.2 (a) shows an example of config uring a character font (character code 001h) as well as monochrome font rom addresses and the related data. figure 2.14.2 (b) shows a character rom dump list for this char acter font (character code 001h). figure 2.14.3 (a) shows an example of config uring a character font (character code 180h) as well as color font rom addresses and the related data. figure 2.14.4 (b) shows a character rom dump list for this character font.
tmp88cs34/cp34 2006-07-06 88cs34-140 note 1: a data cannot be read from character rom by software. note 2: when ordering a mask, load the data to character rom at addresses 20000h to 2a7ffh. and the data in unused are of character rom are must be specified to ffh. note 3: do not use character code 000h 20000/ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20010/ 00 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff 20020/ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20030/ 00 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff 20040/ 3f 7f e0 c0 00 00 00 01 03 07 0e 1c 38 70 ff ff 20050/ 00 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff 20060/ c0 e0 70 30 30 70 e0 c0 80 00 00 00 00 00 f0 f0 20070/ 00 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff note: shaded portions indicate unused data. figure 2.14.2 character font c onfiguration and rom dump list (a) character font configuration of mono font (character code 001h) 20040 20041 20042 20043 20044 20045 20046 20047 20048 20049 2004a 2004b 2004c 2004d 2004e 2004f 20050 20051 3f 7f e0 c0 00 00 00 01 03 07 0e 1c 38 70 ff ff 00 00 address ( hex ) data ( hex ) 20060 20061 20062 20063 20064 20065 20066 20067 20068 20069 2006a 2006b 2006c 2006d 2006e 2006f 20070 20071 c0 e0 70 30 30 70 e0 c0 80 00 00 00 00 00 f0 f0 00 00 address ( hex ) data ( hex ) 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit (b) rom dump list of mono font
tmp88cs34/cp34 2006-07-06 88cs34-141 note 1: specifying primary color outputs by color palette spec ification causes the rom-spec ified color to be displayed. . figure 2.14.3 (1/2) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 26000 26001 26002 26003 26004 26005 26006 26007 26008 26009 2600a 2600b 2600c 2600d 2600e 2600f 26010 26011 00 3f 3f 30 30 30 30 30 3f 3f 37 33 31 30 30 30 30 00 address ( hex ) data ( hex ) 26020 26021 26022 26023 26024 26025 26026 26027 26028 26029 2602a 2602b 2602c 2602d 2602e 2602f 26030 26031 00 f0 f8 1c 0c 0c 0c 1c f8 f0 00 80 c0 e0 70 38 1c 00 address ( hex ) data ( hex ) (character code 180h) 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit (a) example of configuring a color font character pattern (cra = 180h) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27800 27801 27802 27803 27804 27805 27806 27807 27808 27809 2780a 2780b 2780c 2780d 2780e 2780f 27810 27811 00 0f 1f 38 30 30 30 30 30 30 30 30 30 30 38 1f 0f 00 address ( hex ) data ( hex ) 27820 27821 27822 27823 27824 27825 27826 27827 27828 27829 2782a 2782b 2782c 2782d 2782e 2782f 27830 27831 00 f0 f8 1c 0c 0c 00 00 00 7c 7c 0c 0c 0c 1c f8 f0 00 address ( hex ) data ( hex ) (character code 180h) 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29000 29001 29002 29003 29004 29005 29006 29007 29008 29009 2900a 2900b 2900c 2900d 2900e 2900f 29010 29011 00 3f 3f 30 30 30 30 3f 3f 30 30 30 30 30 30 3f 3f 00 address ( hex ) data ( hex ) 29020 29021 29022 29023 29024 29025 29026 29027 29028 29029 2902a 2902b 2902c 2902d 2902e 2902f 29030 29031 00 e0 f0 18 0c 0c 1c f0 f8 1c 0c 0c 0c 0c 1c f8 f0 00 address ( hex ) data ( hex ) (character code 180h) 7 6 5 4 3 2 1 0 bit 7 6 5 4 3 2 1 0 bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r data g data b data (character code 180h) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 5 7 7 7 7 7 7 7 7 7 7 7 7 5 5 0 0 5 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5 0 0 7 7 2 0 0 0 1 5 4 0 0 0 0 2 3 3 0 0 7 7 0 0 0 0 1 5 4 4 0 0 0 0 3 3 0 0 7 7 0 0 0 0 1 5 4 4 4 0 0 0 3 3 0 0 7 7 0 0 0 0 1 5 4 4 4 4 0 0 3 3 0 0 7 7 0 0 0 0 1 5 4 0 4 4 4 0 3 3 0 0 7 7 0 0 0 0 1 5 6 2 0 4 4 4 3 3 0 0 7 7 1 0 0 1 1 5 6 2 0 0 4 4 7 3 0 0 6 7 7 1 1 1 5 5 7 2 0 0 0 7 7 7 0 0 0 6 7 7 7 5 4 5 3 3 3 3 3 3 7 4 0 0 0 0 6 6 6 4 4 0 3 3 3 3 3 3 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 synthesized data used for color font display r g b color 0 : 0 0 0 transparent or black 1 : 0 0 1 blue 2 : 0 1 0 green 3 : 0 1 1 cyan 4 : 1 0 0 red 5 : 1 0 1 magenta 6 : 1 1 0 yellow 7 : 1 1 1 white
tmp88cs34/cp34 2006-07-06 88cs34-142 26000/ 00 3f 3f 30 30 30 30 30 3f 3f 37 33 31 30 30 30 26010/ 30 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff 26020/ 00 f0 f8 1c 0c 0c 0c 1c f8 f0 00 80 c0 e0 70 38 26030/ 1c 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff 27800/ 00 0f 1f 38 30 30 30 30 30 30 30 30 30 30 38 1f 27810/ 0f 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff 27820/ 00 f0 f8 1c 0c 0c 00 00 00 7c 7c 0c 0c 0c 1c f8 27830/ f0 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff 29000/ 00 3f 3f 30 30 30 30 3f 3f 30 30 30 30 30 30 3f 29010/ 3f 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff 29020/ 00 e0 f0 18 0c 0c 1c f0 f8 1c 0c 0c 0c 0c 1c f8 29030/ f0 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff note: shading indicates data in unused areas. figure 2.14.4 (2/2) (b) color font rom dump list (cra = 180h)
tmp88cs34/cp34 2006-07-06 88cs34-143 (2) display memory each character of the 384 characters displayed in 32 columns 12 lines consists of 16 bits in the display memory. five data items are written to the display memory: character code, color data, blinking specification, underline enable, and slant enable. there are two modes for writing display data to the display memory. one mode is used for writing all display data (character code, color data, blinking specification, underline enable, and slant enable) simultaneously. the other mode is used for changing either character codes or the remaining data items (color data, blinking specification, underline enable, and slant enable). how to write display data to the display memory is described in section 2.14.6.7 (1). note: the display memory is in an unknown state at reset. display memory configuration ? character code specification regi ster (9 bits) ........... cra8 to cra0 ? color data specification register (4 bits) ................... idt/rdt/gdt/bdt ? blinking specification register (1 bit)........................ blf ? underline enable regi ster (1 bit) ............................... eul ? slant enable regist er (1 bit) ....................................... slnt ? flag (1 bit) for specifying whether to turn on or off the character-specific background ..... ecbkd ? if echdsn = 0 slnt eul blf ecbkd rdt gdt bdt cra8 cra7 cra6 cra5 cra4 cra3 cra2 cra1 cra0 ? if echdsn = 1 rbdt gbdt blf ecbkd rdt gdt bdt cra8 cra7 cra6 cra5 cra4 cra3 cra2 cra1 cra0 figure 2.14.5 display memory bit configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 000 001 002 003 004 005 006 007 008 009 00a 00b 00c 00d 00e 00f 010 011 012 013 014 015 016 017 018 019 01a 01b 01c 01d 01e 01f 2 020 021 022 023 024 025 026 027 028 029 02a 02b 02c 02d 02e 02f 030 031 032 033 034 035 036 037 038 039 03a 03b 03c 03d 03e 03f 3 040 4 060 5 080 6 0a0 7 0c0 8 0e0 9 100 10 120 11 140 12 160 17f note: numerals in the table indicate (hexadecimal) addresses in the display memory. figure 2.14.6 display memo ry address configuration column line character color blinking specification register underline enable register slant enable register character code specification register fla g for specif y in g whether to turn on or off the characte r -specific back g round character color blinking specification flag character-specific background color of red character-specific background color of green character code fla g for specif y in g whether to turn on or off the characte r -specific back g round
tmp88cs34/cp34 2006-07-06 88cs34-144 (3) color palette the color palette can contain eight colors ou t of 27 colors and the display colors are specified by the color palette registers (orc pt0-7). the color palett e registers (orcpt0-7) are assigned by the rgb setting register for each display mode (character, background, fringe,area, raster). ? rgb setting register values and their corresponding color palette registers rgb = 000b orcpt0 rgb = 001b orcpt1 rgb = 010b orcpt2 rgb = 011b orcpt3 rgb = 100b orcpt4 rgb = 101b orcpt5 rgb = 110b orcpt6 rgb = 111b orcpt7 ? configuration of the color palette registers bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name address r g b orcpt0 00fc6 cpt1md1 0 (fixed) cpt0r1 cpt0r0 cpt0g1 cpt0g0 cpt0b1 cpt0b0 color palette composition register 0 cpt1md1: osd color select register (x = 1, 2) cpt1md1 = 0: 8 ? color mode cpt1md1 = 1: 27 ? color mode orcpt1 00fc7 ? ? cpt1r1 cpt1r0 cpt1g1 cpt1g0 cpt1b1 cpt1b0 color palette composition register 1 orcpt2 00fc8 ? ? cpt2r1 cpt2r0 cpt2g1 cpt2g0 cpt2b1 cpt2b0 color palette composition register 2 orcpt3 00fc9 ? ? cpt3r1 cpt3r0 cpt3g1 cpt3g0 cpt3b1 cpt3b0 color palette composition register 3 orcpt4 00fca ? ? cpt4r1 cpt4r0 cpt4g1 cpt4g0 cpt4b1 cpt4b0 color palette composition register 4 orcpt5 00fcb ? ? cpt5r1 cpt5r0 cpt5g1 cpt5g0 cpt5b1 cpt5b0 color palette composition register 5 orcpt6 00fcc ? ? cpt6r1 cpt6r0 cpt6g1 cpt6g0 cpt6b1 cpt6b0 color palette composition register 6 orcpt7 00fcd ? ? cpt7r1 cpt7r0 cpt7g1 cpt7g0 cpt7b1 cpt7b0 color palette composition register 7 ? color palette setting and output colors 27-color mode (cpt1md1 = 1) 3-value output n = 0 to 7 x = r x = g x = b cptnx1/cptnx0 = 1/1 bright red bright green bright blue cptnx1/cptnx0 = 1/0 or 0/1 dark red dark green dark blue cptnx1/cptnx0 = 0/0 no output no output no output 8-color mode (cpt1md1 = 0) 2-value output n = 0 to 7 x = r x = g x = b cptnx1/cptnx0 = 1/1 bright red bright green bright blue cptnx1/cptnx0 = 1/0 or 0/1 bright red bright green bright blue cptnx1/cptnx0 = 0/0 no output no output no output ? setting the display colors the color palette registers are assigned by setting rgb data for each display mode. the display colors are then specified in the color palette registers. setting the character color to bright red and the background color to dark blue for the code plane. ? setting character color: after setting the character code, set ordsn (rdt = 0, gdt = 1, bdt = 0). (assign a color palette register .) rgb-010b corresponds to color palette register orcpt2. to set the character color to bright red, set orcpt2=00110000b. (set the display color in color palette register .) ? setting background color: set background setting register orbk (0fa5h) (rbdt = 0, gbdt = 0, bbdt = 1). (assign a color palette register. ) rgb = 001b corresponds to color palette register orcpt1. to set the background color to dark blue, set orcpt1 = 00000001b. (set the display color in color palette register. )
tmp88cs34/cp34 2006-07-06 88cs34-145 (4) color font for the color font, the display color (r, g, b) can be specified on a dot-by-dot basis. the size of the color font is 18 dots long by 16 dots wide, which is the same as the size of the normal font (mono font). a dot of the color fo nt is comprised of three bits. font data is combination of three bits (r, g, b) and they are arranged in the order of r (upper), g (middle), b (lower). the color palette registers are assigned by combining these three bits of data. figure 2.14.7 ? assignment of the color palett e registers for the color font rgb data color palette register rgb = 000b 0 orcpt0 rgb = 001b 1 orcpt1 rgb = 010b 2 orcpt2 rgb = 011b 3 orcpt3 rgb = 100b 4 orcpt4 rgb = 101b 5 orcpt5 rgb = 110b 6 orcpt6 rgb = 111b 7 orcpt7 m 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 l 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 k 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 j 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 i 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 h 0 1 1 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 g 0 1 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 f 0 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 e 0 1 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 d 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 c 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 m 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 l 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 k 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 j 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 i 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 h 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 g 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 f 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 e 0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 d 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 0 0 c 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 m 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 l 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 k 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 j 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 i 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 h 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 g 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 f 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 e 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 d 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 c 0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 0 0 0 b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r data (upper) g data (middle) b data (lower) p 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n 0 5 5 7 7 7 7 7 7 7 7 7 7 7 7 5 5 0 m 0 5 7 7 7 7 7 7 7 7 7 7 7 7 7 7 5 0 l 0 7 7 2 0 0 0 1 5 4 0 0 0 0 2 3 3 0 k 0 7 7 0 0 0 0 1 5 4 4 0 0 0 0 3 3 0 j 0 7 7 0 0 0 0 1 5 4 4 4 0 0 0 3 3 0 i 0 7 7 0 0 0 0 1 5 4 4 4 4 0 0 3 3 0 h 0 7 7 0 0 0 0 1 5 4 0 4 4 4 0 3 3 0 g 0 7 7 0 0 0 0 1 5 6 2 0 4 4 4 3 3 0 f 0 7 7 1 0 0 1 1 5 6 2 0 0 4 4 7 3 0 e 0 6 7 7 1 1 1 5 5 7 2 0 0 0 7 7 7 0 d 0 0 6 7 7 7 5 4 5 3 3 3 3 3 3 7 4 0 c 0 0 0 6 6 6 4 4 0 3 3 3 3 3 3 0 4 0 b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 a 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 combined data 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
tmp88cs34/cp34 2006-07-06 88cs34-146 the following shows how the color font shown on the preceding page is displayed by setting the color palette registers. p o n m l k j i h g f e d c b a 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 0 0 5 5 7 7 7 7 7 7 7 6 0 0 0 0 16 0 0 5 7 7 7 7 7 7 7 7 7 6 0 0 0 15 0 0 7 7 2 0 0 0 0 0 1 7 7 6 0 0 14 0 0 7 7 0 0 0 0 0 0 0 1 7 6 0 0 13 0 0 7 7 0 0 0 0 0 0 0 1 7 6 0 0 12 0 0 7 7 0 0 0 0 0 0 1 1 5 4 0 0 11 0 0 7 7 1 1 1 1 1 1 1 5 4 4 0 0 10 0 0 7 7 5 5 5 5 5 5 5 5 5 0 0 0 9 0 0 7 7 4 4 4 4 4 6 6 7 3 3 0 0 8 0 0 7 7 0 4 4 4 0 2 2 2 3 3 0 0 7 0 0 7 7 0 0 4 4 4 0 0 0 3 3 0 0 6 0 0 7 7 0 0 0 4 4 4 0 0 3 3 0 0 5 0 0 7 7 0 0 0 0 4 4 4 0 3 3 0 0 4 0 0 7 7 2 0 0 0 0 4 4 7 3 3 0 0 3 0 0 5 7 3 3 3 3 3 3 7 7 7 0 0 0 2 0 0 5 5 3 3 3 3 3 3 3 7 4 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 color palette setting output color orcpt0 = 00000000b black orcpt1 = 00000011b blue orcpt2 = 00001100b green orcpt3 = 00110000b red orcpt4 = 00001111b cyan orcpt5 = 00111100b yellow orcpt6 = 00110011b magenta orcpt7 = 00111111b white when background = off, dots in which is written are displayed in black. when background = on, dots in which is written show no osd display. however, if area-plane data and raste data exist in the background of the display these colors are displayed. osd output waveform when display line 9 figure 2.14.8 r g b y y * background = on * background = off
tmp88cs34/cp34 2006-07-06 88cs34-147 note: do not use the color font in the first characte r display position. the color font can be used in the second and subsequent character display positions. if you want to use a color font character in the first character display position as counted from the left side of the tv screen, display a transparent character in the first character display position, and use the color font in the second character display position. prepare a monochrome font characte r with no dot as a transparent character. it is recommended that character code cra = 0x20h be prepared as a transparent character. example of display first character display position: transparent character. second character displa y position: color font first character display position transparent character second character display position color font
tmp88cs34/cp34 2006-07-06 88cs34-148 (5) dark color setting function the dark color setting function is intended to control osd intermediate-value outputs, using high, high-z, and low outputs. setting cpt1md1 (bit 7 in orcp1) to ?1? enables this function. producing 3-value outputs requires installing an external circuit. note: the resistor and capacitor values used in the external circuit vary depending on the voltage potential you want to generate. please make adjustments for yourself. figure 2.14.9 example of an external circui t for creating colors between primary colors r3 c2 r2 r1 c1 microcontroller?s rgb outputs to vcd ic
tmp88cs34/cp34 2006-07-06 88cs34-149 (6) switching the osd rom area when the tmp88cs34 is initialized, it is co nfigured for 383 characters of mono font and 96 characters of color font. by setting romach (bit 5 of ordon) to 1, this configuration can be changed to 447 characters of mono font and 64 characters of color font, as shown below. note: do not cra code 000h at 88cx34. figure 2.14.10 mono font data 384 characters cra color font r data color font g data color font b data 96 characters 000h 17fh 1 80 h 1dfh mcu mode a ddress 20000h 25fffh 2 6000 h 2a7ffh 277ffh 27 800 h 28fffh 2 9 000 h eprom mode a ddress 05800h 0b7ffh 0 b 800 h 0ffffh 0cfffh 0 d 000 h 0e7ffh 0 e 800 h mono font data 384 characters cra 64 characters 000h 17fh 1 80 h 1ffh mcu mode a ddress 20000h 25fffh 2 6000 h 2a7ffh 287ffh 2 9000 h 277ffh 2 8c00 h eprom mode a ddress 05800h 0b7ffh 0 b 800 h 0ffffh 0dfffh 0 e 800 h 0cfffh 0 e4 00 h color font r data color font g data color font b data mono font data 32 characters mono font data 16 characters mono font data 16 characters 1bfh 1 c0 h 1dfh 1e 0 h 1efh 1f 0 h 26fffh 27 8 00 h 29fffh 27 000 h 28fffh 2a4 00 h 0c7ffh 0 d 000 h 0e7ffh 0c800 h 0e7ffh 0 f c00 h in character colde order romach = 0romach = 1 mono font data 384 characters cra color font r data color font g data color font b data 96 characters 000h 17fh 1 80 h 1dfh mcu mode a ddress 20000h 25fffh 2 6000 h 2a7ffh 277ffh 27 800 h 28fffh 2 9000 h eprom mode a ddress 05800h 0b7ffh 0 b 800 h 0ffffh 0cfffh 0 d 000 h 0e7ffh 0 e 800 h mono font data 384 characters cra 000h 17fh 1 80 h 1ffh mcu mode a ddress 20000h 25fffh 2 6000 h 2a7ffh 277ffh 27 800 h 28fffh 2 9000 h eprom mode a ddress 05800h 0b7ffh 0 b 800 h 0ffffh 0cfffh 0 d 000 h 0e7ffh 0 e 800 h color font r data 64 characters/3 mono font data 32 characters color font g data 64 characters/3 mono font data 16 characters color font b data 64 characters/3 mono font data 16 characters 1bfh 1e 0 h 1efh 1 80 h 1bfh 1f 0 h 26fffh 27 000 h 287ffh 2 8c00 h 29fffh 2a4 00 h 0c7ffh 0c800 h 0dfffh 0 e4 00 h 0f7ffh 0 f c00 h in rom address order romach = 0romach = 1 1bfh 1 c0 h 1dfh 1 80 h
tmp88cs34/cp34 2006-07-06 88cs34-150 2.14.4 osd circuit control the osd circuit performs control functions us ing the osd control registers which reside in addreses 0001dh to 0001fh and 00024h to 00025h in the special function registers (sfr), and in addresses 00f80h to 00fceh in the data buffer register (dbr). section 2.14.6.8 shows the osd control registers. the os d control registers are used to set display start position, display character designs (that is, fringing, smoothing, color data, character size, and etc.), display memory addresses, and character codes. setting the display on-off control bit, don, (bit 0 in ordon) to ?1? enables display (starts display). setting don to ?0? disables display (halts display). 2.14.5 osd control register write there is a list of the osd control registers on pages 199 to 201. when data is written into a shaded register, the data is transferred to the osd circuit, and then the data becomes valid. after data is written into an unshaded register, the data is transferred to the osd circuit, and then the data becomes valid. to transfer the contents of a control register to the osd circuit, use data transfer request register rgwr (bit 2 in ordon). setting ?1? in the rgwr register outputs the transfer request signal to the osd circuit. three instruction cycles later, transfer of th e written data to the osd circuit starts. while the data is being transferred, data transfer st atus monitoring flag rgwr (bit 2 in ordon) is ?1?. when this transfer is completed, the flag is cleared to ?0?. written data transfer register (1 bit) rgwr (bit 2 in ordon) ?0? initialized state ?1? transfers written data to osd circuit. (after transfer, rgwr is reset to 0.) note: don?t write ?0? to rgwr.
tmp88cs34/cp34 2006-07-06 88cs34-151 (1) rgwr system figure 2.14.11 rgwr system (2) transfer timing 1. no display area when having set rgwr to ?1? during no display area, the timing osd register can be transferred is at the falling edge of hd signal. figure 2.14.12 data transfer timing in no display area 2. display area (including any lines spec ified as display off by character size) when having set rgwr to ?1? during display area, the timing osd register can be transferred is at the falling edge of hd signal when the di splay line has been finished. figure 2.14.13 data transfer timing in display area osd circuit q d le transfer pulse by rgwr = 1 register specified by rgwr set rgwr register to ?1? clear rgwr transfer the contents of osd registe r s into osd circuit data transfer pulse rgwr register hd set rgwr register to ?1? clear rgwr transfer the contents of osd registe r s into osd circuit data transfer pulse rgwr register hd display line
tmp88cs34/cp34 2006-07-06 88cs34-152 2.14.6 osd function 2.14.6.1 signal control (port i/o) (1) p6 port output select function this function is used to select whether the contents of port p57, p67 to p64 will be output or i, r, g, b, y/bl signals of the osd circuit will be output on pins p57, p67 to p64. p57 port output select registers (1 bits): pids (bit 3 in orp6s) pids = 0 pids = 1 p57 i port p67 to p64 port output select registers (4 bits): p67s, p66s, p65s, p64s, (bit 7 to 4 in orp6s) p6ns = 0 p6ns = 1 p64 r p65 g p66 b p67 y/bl port note: be sure to write ?0eh? to the orp6s2 register (0x0fa1h). (2) osd pin output polarity control function this function is used to select the polarity of the osd outputs for rgb, i and y/bl. output polarity control register (4 bits) bliv, yiv, rgbiv, iiv (bit 3 to 0 in oriv) ?0? active high ?1? active low (3) osd pin input polarity control input polarity control input polarity control register of rin/gin/bin/y/blin (2 bits) for y/blin yblii (bit 5 in oriv) for rin, gin, and bin rgbii (bit 4 in oriv) input polarity control rgbii ?0? active high ?1? active low input polarity control register of hd / vd (2 bits) for vd vdpol (bit 7 in oriv) for hd hdpol (bit 6 in oriv) input polarity control vdpol, hdpol ?0? not invert input signal ?1? invert input signal note: to direct p64 (r), p 65 (g), and p66 (b) to produce three-value outputs (high, high-z, and low), be sure to write ?0? to the output polarity control register (4 bits).
tmp88cs34/cp34 2006-07-06 88cs34-153 figure 2.14.14 vd / hd input and vdpol/hdpol (4) y/bl signal select function this function is used to select either y or bl signal output from the y/bl pin. y/bl signal select register (1 bit) yblcs (bit 7 in orp6s) ?0? y signal output ?1? bl signal output y signal output in all osd areas (logical or for r, g, b, character data, fringing data, area data, etc.) bl signal when exbl is ?0?: output in all display character areas when exbl is ?1?: output in the whole page (5) i signal f unction select when pids (bit 3 in orp6s) is set to ?0?, port 57 (i pin) can be used as half transparency/half tone through an extra circuit. the i-pin output is made high only for the area planes. if you want to make the i-pin output high for area plane 1, set pisel1 (bit 3 in the oracl register) to ?1?. if you want to make the i-pin output high for area plane 2, set pisel2 (bit 7 in the oracl register) to ?1?. (6) r, g, b, y/bl internal/external signal select. selects either r, g, b, and y/bl signal s from the internal osd circuit, or rin, gin, bin, and y/blin signals from external input. r, g, b, y/bl signal select registers (2 bits) mpxs1/mpxs0 (bits 1 and 0 in orp6s) ?00? simultaneous output (signal from the osd circuit has higher priority.) ?01? output of signal from internal osd circuit ?10? output of signal from external input ?11? simultaneous output (external input signal has higher priority.) p71 ( vd ) register setting for the following waveform input waveform to p70, p71 vdpol = 0 hdpol = 0 p70 ( hd ) p71 ( vd ) vdpol = 1 hdpol = 0 p70 ( hd ) p71 ( vd ) vdpol = 0 hdpol = 1 p70 ( hd ) p71 ( vd ) vdpol = 1 hdpol = 1 p70 ( hd )
tmp88cs34/cp34 2006-07-06 88cs34-154 2.14.6.2 osd data output format control (1) scan mode the double scan mode is used to hand le non-interlaced scanning tv. when double scan mode is enabled, the vertical display counter increases every 2 scan lines and a vertical size of a dot is double. this function is enabled by setting vdsmd (bit 7 in oretc) in the osd control register to ?1?. scan mode select register (1 bit) vdsmd (bit 7 in oretc) ?0? normal mode ?1? double scan mode note 1: the data written to those control regi ster is transferred to the osd circuit and become valid when the data is written. note 2: when osd circuit is used on an interlace scanning tv, a jitter elimination circuit must be enabled and set afld to ?1? in jecr. table 2.14.3 the difference of 2 types of scan mode normal mode double scan mode specification unit of vertical display start position one scanning line two scanning lines 1 dot height ? normal mode height 2 figure 2.14.15 scan mode normal mode double scan mode interlace scanning normal mode double scan mode non-interlace scanning
tmp88cs34/cp34 2006-07-06 88cs34-155 2.14.6.3 display position control (1) code display position setting 1. horizontal display start position the horizontal display start position can be set in 256 steps by writing to osd control registers hs17 to hs10 (bit 7 to 0 in orhs1). the value is in common with all lines. specification unit: 2 t osc specification steps: 256 specification horizontal display start position: line 1 to 12: hs17 to hs10 (orhs1) hs1 = (hs17 to hs10) h 2t osc + 22t osc (line1 to 12) note 1: t osc ; one cycle of osd oscillation. note 2: the data written to these control registers is transmitted to osd circuit by setting rgwr (bit 2 in ordon) to ?1?. 2. vertical display start position the vertical display start position can be specified for each display line using 625 steps by writing to vsn9 to vsn0 (in orvsn (n; 1 to 12)). specification unit: 1 scan line specification steps: 512 specification vertical display start position: line1: vs19 to vs10 (orvs 1) line2: vs29 to vs20 (orvs 2) . . . line12: vs129 to vs120 (orvs 12) line n: vsn = (vsn9 to vsn0) h 1t hd (n; 1 to 12) note 1: t hd ; one cycle of hd signal. note 2: the data written to these control registers is transmitted to osd circuit by setting rgwr (bit 2 in ordon) to ?1?. note 3: if display lines are overlapped each other, pr evious display line is enabled and next line is disabled. if vertical display start positions of two or more lines are set on same value, high priority line is enabled. lines of osd (vs1 to vs12) are fixed priority levels as follows: vs1 > vs2 > vs3 > > vs12 set the vertical display start position not to overlap display lines. note 4: the line which is displayed off is managed as a small size character line. note 5: transfer the contents of vertical display start position registers into osd ci rcuit before the position of the scanning line coincides with their own vertical display start position. vs5 (display on, small character) vs2 (display canceled, middle character) vs3 (display on, small character) occasion of overlapping
tmp88cs34/cp34 2006-07-06 88cs34-156 (2) area display position setting the planes have the priority such as code plane > area plane 1 > area plane 2 > raster plane. 1. horizontal displa y start position the horizontal display start position can be set in 512 steps by writing to osd control registers ahsn8 to ahsn0 (bit 8 to 0 in orahsn). and also display stop position is correspond to ahen8 to ahen0 (bit 8 to 0 in orahen). (n; 1 to 2) horizontal displa y start position ahsn = (ahsn8 to ahsn0)h 2t osc horizontal display end position ahen = (ahen8 to ahen0)h 2t osc note 1: t osc : one cycle of osd oscillation. note 2: if the horizontal display start position for characters is the same as that for areas, the two positions are not displa yed at the same time. the horizontal display start position for characters is displayed 16 t osc (corresponding to a register value of 8) later than that for areas. 2. vertical display start position the vertical display start position can be set in 625 steps by writing to osd control registers avsn9to avsn0 (bit 9 to 0 oravsn). and also display stop position is correspond to aven9 to aven 0 (bit 9 to 0 in oraven). (n; 1 to 2) vertical display start position av s n = (avsn9 to avsn0)h t hd vertical display end position av e n = (aven9 to aven0)h t hd note: t hd : one cycle of hd signal. figure 2.14.16 tv scan image 1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ss ss 1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ss ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ss ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ss ss hs1 a hs2 a he2 code plane 12 code plane 11 code plane 10 code plane 9 code plane 1 code plane 2 a rea plane 2 a rea plane 1 a he1 ave1 avs1 vs2 vs1 ave2 avs2 hs1 a hs1 hd vd
tmp88cs34/cp34 2006-07-06 88cs34-157 2.14.6.4 character ornamentation control (1) character sizes character size can be selected line by line from 4 sizes. and display on/off also can be set line by line. small, middle, la rge and double height character size and display on/off can be set with osd control registers csn (n = 1 to 12, orcs4, orcs8, orcs12) in the osd control registers. character sizes: 4 sizes (small, middle, large and double height) character size and display on/off specification unit: line character size select/display on/off register (2 bits 12) line 1: cs1 line 2: cs2 : : line 12: cs12 table 2.14.4 character size and display on/off specifications (n = 1 to 12 and m = 1 to 12) csn (high-order bit) csn (low-order bit) character size dcscn (double-height specification) display on/off 1 1 small-size character 0 on 1 0 medium-size character 0 on 0 1 large-size character 0 on 1 0 double-height character 1 on 0 0 ? 0 off note 1: to display a double-height character, write ?10? and ?1?, respectively, to csn (medium-size character specificatio n) and dcscm (double-height display specification). if dcscm and csn are, respectively, ?0? and ?10?, medium-size characters are displayed. note 2: if the character size specification (c sn) is ?11? or ?01?, no double-height character can be displayed. note 3: do not specify to modify double-hei ght characters (such as fringing, smoothing, and slanting) because such specifications hamper normal display. note 4: the display off line operates like the wi dth of small character size line thought the character is not displayed. note 5: the data written to these control regi sters is transmitted to osd circuit by setting rgwr (bit 2 in ordon) to ?1?. note 6: when osd circuit is used on an inte rlace scanning tv, a jitter elimination circuit must be enabled and set afld to ?1? in jecr. note 7: when vdsmd and afld are ?0?, only character of even display dot is displayed. (refer to 2.16 a jitter elimination circuit)
tmp88cs34/cp34 2006-07-06 88cs34-158 table 2.14.5 dot size and character size vdsmd = 0 (normal mode) vdsmd = 1 (double-scan mode) dot size character size dot size character size small-size character 1t osc 0.5t hd 16t osc 9t hd 1t osc 1t hd 16t osc 18t hd medium-size character 2t osc 1t hd 32t osc 18t hd 2t osc 2t hd 32t osc 36t hd large-size character 4t osc 2t hd 64t osc 36t hd 4t osc 4t hd 64t osc 72t hd eulan = 0 (underline off) double-height character 1t osc 1t hd 16t osc 18t hd 1t osc 2t hd 16t osc 36t hd small-size character 1t osc 0.5t hd 16t osc 12t hd 1t osc 1t hd 16t osc 24t hd medium-size character 2t osc 1t hd 32t osc 24t hd 2t osc 2t hd 32t osc 48t hd large-size character 4t osc 2t hd 64t osc 48t hd 4t osc 4t hd 64t osc 72t hd eulan = 1 (underline on) double-height character 1t osc 1t hd 16t osc 24t hd 1t osc 2t hd 16t osc 48t hd note: t osc = one osd oscillation cycle. t hd = one hd signal cycle.
tmp88cs34/cp34 2006-07-06 88cs34-159 figure 2.14.17 character size (2) smoothing function the smoothing function is used to make characters look smooth. enabling smoothing displays 1/4 dot between two dots connecting corner to corner within a character. small size character and colo r font can not be enabled smoothing. smoothing is enabled by setting esmz (bit 4 in oretc) in the osd control register to ?1?. smoothing specification unit: display page smoothing specification register (1 bit) esmz (bit 4 in oretc) ?0? disable smoothing ?1? enable smoothing note 1: data of the register is tran sferred to the osd circuit and become valid when the data is written. note 2: the smoothing function is invalid for the color font. figure 2.14.18 available form and invalid form for smoothing small middle large double height before after before after available form for smoothing invalid form for smoothing
tmp88cs34/cp34 2006-07-06 88cs34-160 figure 2.14.19 smoothing example (3) fringing function the fringing function is used to display a character with a fringe width is 1 dot in a different color from that of the char acter. when a character is displayed with the maximum of 18 vertical dots and 16 horizontal dots, the fringe exceeds right and left of the character display area. no vertical fringing is displayed out of the character display area. if there is an adjacent character that outer dot is active, then this dot will overrule the fringe in the horizontal direction. underlines are not fringed. fringing is enabled for each line by setting efr1 to efr8 (orefr8) and efr9 to efr12 (orefr12) in the osd control register to ?1?. a color for fringe is specified common to all lines using osd control registers, rfdt, gfdt, and bfdt (bit 2 to 0 in orbk). fringing specification unit: line fringing enable register (1 bit 12) efrn (n; 1 to 8) (orefr8), efrn (n; 9 to 12) (orefr12) ?0? disable fringing ?1? enable fringing fringe colors: 8 or 27 fringe color specification unit: display page fringe color register (3 bits) rfdt, gfdt, bfdt (bit 2 to 0 in orbk) note 1: the fringe of 1st column charac ter does not exceed left, and the fringe of 32th character does not exceed right. note 2: do not specify fringing for the color font. note 3: do not specify fringing for characters for which double-height display is specified. original character smoothing
tmp88cs34/cp34 2006-07-06 88cs34-161 table 2.14.6 fringe color rfdt gfdt bfdt figure color 0 0 0 setting color of orcpt0 0 0 1 setting color of orcpt1 0 1 0 setting color of orcpt2 0 1 1 setting color of orcpt3 1 0 0 setting color of orcpt4 1 0 1 setting color of orcpt5 1 1 0 setting color of orcpt6 1 1 1 setting color of orcpt7 figure 2.14.20 (a) fringing example after fringing before fringing vertical indicate area 18 dots disable underline after fringing before fringing vertical indicate area 24 dots enable underline a) small character, normal mode
tmp88cs34/cp34 2006-07-06 88cs34-162 figure 2.14.21 ( ) fringing example after fringing before fringing vertical indicate area 24 dots enable underline b) small character, double scan mode after fringing before fringing vertical indicate area 18 dots disable underline
tmp88cs34/cp34 2006-07-06 88cs34-163 figure 2.14.22 ( ) fringing example after fringing before fringing vertical indicate area 18 dots disable underline after fringing before fringing vertical indicate area 24 dots enable underline c) middle/large character, normal mode
tmp88cs34/cp34 2006-07-06 88cs34-164 figure 2.14.23 ( ) fringing example after fringing before fringing vertical indicate area 18 dots disable underline after fringing before fringing vertical indicate area 24 dots enable underline d) middle/large character, double scan mode
tmp88cs34/cp34 2006-07-06 88cs34-165 (4) double-height display function it is possible to display a character havi ng the same horizontal size as for the small-size character and the same vertical size as for the medium-size character. this function can be realized by specif ying medium-size character display for the character size and setting up the double-height display setting register (ordcsc). its specification unit is the row. double-height display enable unit: row double-height display enable register (1 bit 12): dcscn (n = 1 to 12) (ordcsc register) character size specification: ?10? is set in csn (n = 1 to 12; orcs4, orcs8, and orcs12). figure 2.14.24 double-height character display note: do not specify the fringing, smoothing, or slanting character modification function for a row where double-height display is specified. medium-size charac ter double-height character small-size character
tmp88cs34/cp34 2006-07-06 88cs34-166 (5) displaying a small-size character cons isting of 26 vertical and 18 horizontal dots it is possible to display smal l-size characters at vertical intervals of 26 scanning lines. this function is realized by specifying small-size character display and setting up the 26-dot vertical display setting register orccd. this specification can be made in line units. 26-dot vertical display enable unit: row 26-dot vertical display enable register (1 bit 12): ccdn (n = 1 to 12) (orccd register) character size specification: ?11? is set in csn (n = 1 to 12; orcs4, orcs8, and orcs12). figure 2.14.25 26-dot vertical display (6) background function the background color is the color of all backgrounds including the background of the character area (see table 2.14.5). the background function is specified in screen units by setting the ebkgd osd control register (bit 7 in the orrcl register) to ?1?. using the ecbkd osd control register (bit 3 in the ordsn register) can enable/disable the char acter-specific background color. the background color is specified, using the rbdt, gbdt, and bbdt osd control registers (bits 6 to 4 in the or bk register). setting the echdsn osd control register (bit 3 in the ordon register) to ?1? specifies slnt (bit 6 in the ordsn register) and eul (bit 5 in the ordsn register), respectively, as rbdt and gbdt. a background color different from that of the screen can be set up as a character-specific background. background color enable units: screen and character background enable register (2 bits) screen unit: ebkgd (bit 7 in the orrcl register) character unit: ecbkd (bit 3 in the ordsn register) background color specification units: screen and character background color specification register if echdsn = 0: rbdt, gbdt, and bbdt (bits 6 to 4 in the orbk register) if echdsn = 1: rbdt, gbdt (bits 6 to 4 in the orbk register), slnt (corresponding to rbdt), and eul (corresponding to gbdt) small-size character 26-dot vertical display
tmp88cs34/cp34 2006-07-06 88cs34-167 table 2.14.7 background color control osd control register ebkgd ecbkd display status 0 0 no background is displayed. 0 1 no background is displayed. 1 0 no background is displayed. 1 1 a background is displayed. table 2.14.8 character-specific background color setting function character-specific background color setting (echdsn) register name function 0 1 slnt slanting rbdt (background color of red) eul underlining gbdt (background color of green) blf blanking character modification specification register ecbke character-specific background enable note1: when the echdsn is set to "1", the background color is specified by rbdt (red) and gbdt (green) bits.in this case, orcpt0,orcpt2, orcpt4 and orcpt6 are available for color pallet. note 2: osd output isn't done, and a video signal is indicated in the background area in case of ebkgd=0, ecbkd=0 and ebkgd=1, ecbkd=0.a background area becomes transparent in case of ebkgd=0 and ecbkd=1. that color is indicated when it is piled up and indicated with the area plane. the background color spec ified in case of ebkgd=1 and ecbkd=1 is indicated. table 2.14.9 background color rbdt gbdt bbdt background color 0 0 0 setting color of orcpt0 0 0 1 setting color of orcpt1 0 1 0 setting color of orcpt2 0 1 1 setting color of orcpt3 1 0 0 setting color of orcpt4 1 0 1 setting color of orcpt5 1 1 0 setting color of orcpt6 1 1 1 setting color of orcpt7
tmp88cs34/cp34 2006-07-06 88cs34-168 figure 2.14.26 background function note: when the background function is enabled, the line enable the fringing function should not start with a blank character. if it starts with a blank character, a fringe is displayed to the left of the blank character. character color : cyan background color : yellow scanning line r bl y b g 1) disable background scanning line 2) enable background r bl y b g
tmp88cs34/cp34 2006-07-06 88cs34-169 2.14 2.14.6.5 osd display screen control (1) display on/off this function is used to display characters specified for on/off display. display on/off specification unit: display page display on/off specification register (1 bit) don (bit 0 in ordon) ?0? disable display ?1? enable display note: do not start stop mode during display is enable. (2) window function this function is used to set upper and lower limit of display page. window upper limit is specified by wvsh (orwvsh). window lower limit is specified by wvsl (orwvsl). this function is enabled by setting ewdw (bit 1 in ordon ) in the osd control register to 1. window specification unit: display page window function enable specification register (1 bit) ewdw (bit 1 in ordon) ?0? disable window function ?1? enable window function window upper limit specification register (10 bits) wvsh9 to 0 (orwvsh) window lower limit specification register (10 bits) wvsl9 to 0 (orwvsl) window upper and lower limit position when vdsmd is ?0? (normal mode): wvsh = (wvsh9 to wvsh0) h t hd wvsl = (wvsl9 to wvsl0) h t hd when vdsmd is ?1? ( double scan mode): wvsh = (wvsh9 to wvsh0) h 2t hd wvsl = (wvsl9 to wvsl0) h 2t hd note 1: t hd ; one cycle of hd signal note 2: wvsl > wvsh ?1? note 3: modify the value of window upper and lower limit register and the value of ewdw during vd signal is low. note 4: it is recommendable that the window function is always enabled (ewdw = ?1?) and set wvsh to ?01h?, wvsl to ?1feh?. note 5: characters and symbols at scanning line specified by wvsl are not displayed.
tmp88cs34/cp34 2006-07-06 88cs34-170 note: window display: on, area plane display: on, back ground color display: on, raster plane display: on figure 2.14.27 display example figure 2.14.28 if wvsh is on a code plane display of f display wvsh background color hd vd wvsl a hs1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ss ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ss ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ss ss area plane color picture picture wvsh raster color
tmp88cs34/cp34 2006-07-06 88cs34-171 (3) full-raster blanking function full-raster blanking function is used to color the entire background for the display area (tv screen). when using the full-raster blanking function, set yblcs (bit 2 in orp6s) to ?1?, output bl signal from y/bl pin, because y signal cannot delete whole display page from video signal. this function is specified for each display page by setting exbl (bit 6 in orrcl) in the osd register to ?1?. full-raster blanking specification unit: display page full-raster blanking enable register (1 bit) exbl (bit 6 in orrcl) ?0? disable full-raster blanking ?1? enable full-raster blanking full-raster blanking color specification registers (3 bits) rclr, rclg, rclb (bit 2 to 0 in orrcl) table 2.14.10 raster plane color rclr rclg rclb raster plane color 0 0 0 setting color or orcpt0 0 0 1 setting color or orcpt1 0 1 0 setting color or orcpt2 0 1 1 setting color or orcpt3 1 0 0 setting color or orcpt4 1 0 1 setting color or orcpt5 1 1 0 setting color or orcpt6 1 1 1 setting color or orcpt7
tmp88cs34/cp34 2006-07-06 88cs34-172 (4) area plane function area plane function is used to display square area to two points on a screen. two planes operate independently. they are displayed according to the priority (area plane 1 > area plane 2). see area plane display position setting in section 2.14.6.3 (2) how to set display positions for each area. each area plane is set to on or off by aon2 and aon1 (bit 5 and bit 4 in orrcl). area plane colors are set by aclrx, aclgx, aclbx (bit 6 to bit 4 and bit 2 to bit 0 in oracl, x = 1, 2). area plane colors: 8 or 27 area plane specification unit: plane area plane color specification register (6 bit) area plane 1: aclr1/aclg1/aclb1 (bit 2 to 0 in oracl) area plane 2: aclr2/aclg2/aclb2 (bit 6 to 4 in oracl) table 2.14.11 area plane color aclrx aclgx aclbx area plane color 0 0 0 setting color of orcpt0 0 0 1 setting color of orcpt1 0 1 0 setting color of orcpt2 0 1 1 setting color of orcpt3 1 0 0 setting color of orcpt4 1 0 1 setting color of orcpt5 1 1 0 setting color of orcpt6 1 1 1 setting color of orcpt7 (x: 1, 2) (5) i-pin function the i-pin output becomes valid only for area planes. resetting the pids osd control register (bit 3 in the orp6s register) to ?0? causes p57 to work for i-pin output. if you want to produce an i-pin output for area plane 1, set the pisel1 osd control register (bit 3 in the oracl re gister) to ?1?. if you want to produce an i-pin output for area plane 2, set the pisel2 osd control register (bit 7 in the oracl register) to ?1?. the i-pin output depends on the display priority of the area planes.
tmp88cs34/cp34 2006-07-06 88cs34-173 (6) examples of osd outputs figure 2.14.29 osd output examples (a) area 1 area 2 halftone a b c d pisel1 = 0 pisel2 = 1 a rea where any of font colors r, g, and b is high character display area ? example 1 area 1 halftone a rea 2 a b c d pisel1 = 1 pisel2 = 0 ? example 2 area 1 halftone area 2 halftone a b c d pisel1 = 1 pisel2 = 1 ? example 3 d o t d o t d o t i y bl a i y bl b i y bl c i y bl d i y bl a i y bl b i y bl c i y bl d i y bl a i y bl b i y bl c i y bl d
tmp88cs34/cp34 2006-07-06 88cs34-174 figure 2.14.30 osd output examples (b) area 1 area 2 halftone a b c d pisel1 = 1 pisel2 = 0 a rea where any of font colors r, g, and b is high character display area ? example 4 d o t area 1 halftone area 2 pisel1 = 0 pisel2 = 1 ? example 5 d o t area 1 halftone a rea 2 halftone pisel1 = 1 pisel2 = 1 ? example 6 d o t raste r a b c d raste r a b c d raste r i y bl a, d i y bl b, c i y bl a, b, c, d i y bl a, d i y bl b, c
tmp88cs34/cp34 2006-07-06 88cs34-175 figure 2.14.31 osd output examples (c) area 1 area 2 halftone a b c d pisel1 = 0 pisel2 = 1 a rea where any of font colors r, g, and b is high character display area ? example 7 area 1 halftone a rea 2 a b c d pisel1 = 1 pisel2 = 0 ? example 8 area 1 halftone area 2 halftone a b c d pisel1 = 1 pisel2 = 1 ? example 9 d o t d o t d o t in examples 7, 8 and 9, area plane 1, rather than area plane 2, is displayed. in patterns 1, 2 and 3, area plane 1, rather than area plane 2, is displayed. in patterns 1, 2 and 3, area plane 1, rather than area plane 2, is displayed. i bl a , b, c, d, e i bl a, b, c, d, e i bl a, b, c, d, e
tmp88cs34/cp34 2006-07-06 88cs34-176 figure 2.14.32 osd output examples (d) area 1 area 2 halftone a b c d pisel1 = 0 pisel2 = 1 a rea where any of font colors r, g, and b is high character display area ? example 10 d o t area 1 halftone a rea 2 pisel1 = 1 pisel2 = 0 ? example 11 d o t area 1 halftone area 2 halftone pisel1 = 1 pisel2 = 1 ? example 12 d o t raste r a b c d raste r a b c d raste r in patterns 1, 2 and 3, area plane 1, rather than area plane 2, is displayed. i bl a, b, c, d, e i bl a, b, c, d, e i bl a , b, c, d, e
tmp88cs34/cp34 2006-07-06 88cs34-177 2.14.6.6 interrupt control (1) display line counter the display line counter indicates number of display line (s) by osd circuit on the tv screen. the display line counter is a 4-bit counter which is initialized to ?0? by the falling edge of the vd signal and which increments when last scanning of each display line is completed (falling edge of the hd signal). it is necessary to be read out display line counte r several times, because it does not synchronize cpu clock. display line counter register (4 bits) dctr (bit 3 to 0 in orirc) ?0000? no display line is completed. ?0001? 1st display line is completed. ?0010? 2nd display line is completed. to to ?1111? 15th display line is completed. note 1: the display line counter also increments when a line with all blank characters or a line with display off is specified. note 2: when display lines are overlapped each other, pr evious display line is enabl ed and next line is disabled. at this time, the display line counter does not increment for disabled line. figure 2.14.33 display line counter display line counter vd signal 12 4th display line with all blank characters 3rd display line 2nd display line 1st display line 10th display line 11th display line 12th display line display on 11 10 9 4 3 2 1 m display on display on display on display on display off display on 0 : :
tmp88cs34/cp34 2006-07-06 88cs34-178 (2) interrupt generator circuit an interrupt request is generated when a falling edge of vd signal or when line counter (dctr) is counted to the certain value specified by isdc. interrupt source select register (1 bit): svd (bit 4 in orirc) ?0? interrupt request generated when the display line counter (dctr) is counted to the certain value which is specified by isdc. ?1? interrupt request is generated when a falling edge of vd signal. interrupt generation line specification register (4 bits) isdc (bit 3 to 0 in orirc) ?0000? interrupt request generate d when the display line counter is cleared. ?0001? interrupt request generated at end points of the last scanning line of the first display line ?0010? interrupt request generated at end points of the last scanning line of the 2?nd display line to ?1111? interrupt request generated at end points of the last scanning line of the 15?th display line 2.14.6.7 display memory access (1) display memory the display memory is accessed for two purposes, one for writing data to the display memory, and one for reading data from the display memory. display memory address specification registers (9 bits) dma8 to mda0 (ordma) display memory data write registers character code write register (9 bits) cra8 to cra0 (orcra) character ornamentation data write registers (6 bits) slnt, eul, blf, rdt, gdt, and bdt (ordsn) character-specific background on/off specification register (1 bit) ecbkd (ordsn register) display memory bank select register mbk (bit 1 in oretc) ?0? when writing either character code or character ornamentation data ?1? when writing both character code and character ornamentation data note 1: these control registers have a charac teristic that immediately when a value is written to the register, the c ontent of the register is tran sferred as valid data to the osd circuit/display memory. note 2: the data written to the display memory takes effect at the same time it is written. when character code or character ornamentation data is written to the display memory while it is displaying some character, the character may not be displayed correctly. when writing data to the display memory, make sure no character is being displayed in the memory location where you are going to write data. note 3: when writing data to or reading data from the display memory, do not use two-byte transfer instructions such as ?ldw(hl),mn ld rr, (pp).? otherwise, erroneous data may be written to the display memory or data may be written to an incorrect address. note 4: allow for at least two instruction cycles between a display memory address write instruction and a data write or read instruct ion. also, when continuous writing data to or reading data from the display memory, allow for at least two instruction cycles between one write or read instruction an d the next. otherwise, erroneous data may be written to the display memory or data may be written to an incorrect address. note 5: when setting display memory addresses, always be sure to write all of 9 address bits sequentially in order of dma8 and dma7 to dma0.
tmp88cs34/cp34 2006-07-06 88cs34-179 1. normal mode in normal mode, the display memory addresses are automatically incremented each time data is read from or written to the memory. because addresses are automatically incremented, this mode may be used for reading from or writing data to multiple continuous addresses simultaneously. (a) when writing either character code or character ornamentation data (1) set mfywr, mbk, and rdwrv all to 0. (2) write the most significant address bit of the display memory to dma8. go on and write the 8 low-order address bits of the display memory to dma7 to dma0. (3) writing character code or character ornamentation data ? writing character code write the most significant bit of character code to cra8. go on and write the 8 low-order bits of character code to cra7 through cra0. at this point in time, the 9 bits of character code written are transf erred to the display memory, and dma8 to dma0 are automatically incremented. ? writing character ornamentation data write character ornamentation data to slnt, eul, blf, ecbkd, rdt, gdt, and bdt. at this point in time, the character ornamentation data written are transferred to the display memory, and dma8 to dma0 are automatically incremented. (4) to write data (character code or character ornamentation data) to continuous addresses, repeat step (3). (b) when writing character code and character ornamentation data at a time (1) set mfywr to 0, mbk to 1, and rdwrv to 0. (2) write the most significant address bit of the display memory to dma8. go on and write the 8 low-order address bits of the display memory to dma7 to dma0. (3) write character ornamentation data to slnt, eul, blf, ecbkd, rdt, gdt, and bdt. at this point in time, the character ornamentation written are transferred to the display memory. (4) write the most significant bit of character code to cra8. go on and write the 8 low-order bits of character code to cra7 to cra0. at this point in time, the 9 bits of character code written and the character or namentation data written in step (3) are transferred to the display memory, an d dma8 to dma0 are automatically incremented. (5) to write data to continuous addresses, repeat steps (3) and (4).
tmp88cs34/cp34 2006-07-06 88cs34-180 (a) when reading either character code or character ornamentation data (1) set mfywr to 0, mbk to 0, and rdwrv to 1. (2) write the most significant address bit of the display memory to dma8. go on and write the 8 low-order address bits of the display memory to dma7 to dma0. (3) reading character code or character ornamentation data ? reading character code read the most significant bit of characte r code to cra8. go on and read the 8 low-order bits of character code to cra7 to cra0. at this point in time, dma8 to dma0 are automatically incremented. ? reading character ornamentation data read character ornamentation data slnt, eul, blf, ecbkd, rdt, gdt, and bdt. at this point in time, dma8 through dma0 are automatically incremented. (4) to read data (character code or char acter ornamentation data) from continuous addresses, repeat step (3). (b) when reading character code and character ornamentation data at a time (1) set mfywr to 0, mbk to 1, and rdwrv to 1. (2) write the most significant address bit of the display memory to dma8. go on and write the 8 low-order address bits of the display memory to dma7 to dma0. (3) read character ornamentation data slnt, eul, blf, ecbkd, rdt, gdt, and bdt. (4) read the most significant bit of character code to cra8. read the 8 low-order bits of character code to cra7 to cra0. at this point in time, dma8 to dma0 are automatically incremented. (5) to read data from continuous addresses, repeat steps (3) and (4). 2. read-modify-write mode when writing data in read-modify-write mode, the display memory addresses are automatically incremented as in normal mode, but when reading data in this mode, the memory addresses are not automatically incremented. therefore, immediately after executing a read from some display memory address, you can execute a write to the same display memory address. after executing a write, the display memory addresses are automatically incremented. (a) reading/writing either character code or character ornamentation data in read-modify-write mode (1) set mfywr to 1 and mbk to 0, and rdwrv to 1. (2) write the most significant address bit of the display memory to dma8. go on and write the 8 low-order address bits of the display memory to dma7 to dma0. (3) reading character code or character ornamentation data ? reading character code read the most significant bit of charac ter code to cra8. read the 8 low-order bits of character code to cra7 to cra0. dma8 to dma0 are not incremented. ? reading character ornamentation data read character ornamentation data slnt, eul, blf, ecbkd, rdt, gdt, and bdt. dma8 to dma0 are not incremented.
tmp88cs34/cp34 2006-07-06 88cs34-181 (4) writing character code or character ornamentation data ? set rdwrv to ?0?. ? writing character code write the most significant bit of character code to cra8. go on and write the 8 low-order bits of character co de to cra7 to cra0. at this point in time, the 9 bits of character code written are transferred to the display memory, and dma8 to dma0 are automatically incremented. ? writing character ornamentation data write character ornamentation data to slnt, eul, blf, ecbkd, rdt, gdt, and bdt. at this point in time, the character ornamentation data written are transferred to the display memory, and dma8 to dma0 are automatically incremented. (5) to continue executing read-modify-write operations, repeat steps (1) to (4). to read/write data (character code or char acter ornamentation data). to continue executing read modify-write mode from continuous addresses, repeat steps (3) and (4). (b) reading/writing both character code and character ornamentation data in read-modify-write mode (1) set mfywr to 1, mbk to 1 and rdwrv to 1. (2) write the most significant address bit of the display memory to dma8. go on and write the 8 low-order address bits of the display memory to dma7 to dma0. (3) read character ornamentation data slnt, eul, blf, ecbkd, rdt, gdt, and bdt. at this point in time, dma8 to dma0 are not incremented. (4) read the most significant bit of character code to cra8. read the 8 low-order bits of character code to cra7 to cra0. at this point in time, dma8 to dma0 are not incremented. (5) set rdwrv to ?0?. (6) write character ornamentation data to slnt, eul, blf, ecbkd, rdt, gdt, and bdt. at this point in time, the character ornamentation data written is transferred to the display memory. (7) write the most significant bit of character code to cra8. go on and write the 8 low-order bits of character code to cra7 to cra0. at this point in time, the 9 bits of character code written and the character or namentation data written in step (6) are transferred to the display memory, an d dma8 to dma0 are automatically incremented. (8) to continue executing read-modify-write operations, repeat steps (1) to (7). (to read/write data to and from continuous a ddresses in read-modify-write mode, repeat steps (3) to (7).)
tmp88cs34/cp34 2006-07-06 88cs34-182 table 2.14.12 address increment rd(rdwrv =1) wr(rdwrv=0) character ornamentation character code character ornamentation character code mbk = 0 inc inc inc inc mfywr = 0 mbk = 1 ? inc ? inc mbk = 0 ? ? inc inc mfywr = 1 mbk = 1 ? ? ? inc inc: automatic address increment at read or write. ? : no address change at data read or write. example: setting a character code (020h) to the display memory (address: 120h) and setting a character ornamentation (001h) for character code 020h and display memory address 120h. 1. mbk = 0 ; set display memory address ld (0x25), 0x01 ; ordma ld (0x24), 0x20 ; ordma ; set character code ld (0x1f), 0x00 ; orcra ld (0x1e), 0x20 ; orcra ; set display me mory address again ld (0x25), 0x01 ld (0x24), 0x20 ; set character ornamentation ld (0x1d), 0x01 ; ordsn 2. mbk = 1 ; set display memory address ld (0x25), 0x01 ld (0x24), 0x20 ; set character ornamentation ld (0x1d), 0x01 ; set character code ld (0x1f), 0x00 ld (0x1e), 0x20 note 1: to write character data into the display memory, first write into register cra8 and then write into registers cra7 to cra0. when data is written into registers cra7 to cra0, dma is incremented. it is impossible to write into the display memory for cra7 to cra0 alone. if no data is written into register cra8 while data is written into registers cra7 to cra0, the value previously written into regi ster cra8 is written into the associated display memory. note 2: to read data from the display memory, first read from register cra8, and then read from registers cra7 to cra0. when data is read from registers cra7 to cra0, dma8 to dma0 is incremented. note 3: there should be a time interval of at least two machine cycles between a dma set instruction and a data write/read instruction. there should be a time interval of at least two machine cycles between a data write instruction and a data read instruction.
tmp88cs34/cp34 2006-07-06 88cs34-183 (2) characters ? if romach (bit 5 in ordon) = 0 characters: 383 monochrome font charac ters and 96 color font characters character specification register (9 bits): cra8 to cra0 (bits 8 to 0 in the orcra register) character codes: user-programmable in character rom monochrome font codes ?001h? to ?17fh? color font codes ?180h? to ?1dfh? ? if romach (bit 5 in ordon) = 1 characters: 447 monochrome font charac ters and 64 color font characters character specification register (9 bits): cra8 to cra0 (bits 8 to 0 in the orcra register) character codes: user-programmable in character rom monochrome font codes ?001h? to ?17fh?, ?1c0h? to ?1dfh?, ?1f0h? to ?1ffh? color font codes ?180h? to ?1bfh? (3) character color character colors: 8 or 27 character color specification unit: character character color specification register (3 bits): rdt/gdt/bdt (bit2 to 0 in ordsn) table 2.14.13 character color rdt gdt bdt character color 0 0 0 setting color of orcpt0 0 0 1 setting color of orcpt1 0 1 0 setting color of orcpt2 0 1 1 setting color of orcpt3 1 0 0 setting color of orcpt4 1 0 1 setting color of orcpt5 1 1 0 setting color of orcpt6 1 1 1 setting color of orcpt7 (4) blinking function blinking function is used to blink display characters. when bkmf is ?1?, characters specified for blinking by blf are not displayed. (if the background color function is used, the background color is not disappeared.) blinking specification unit: character blinking specification register (1 bit) blf (bit 4 in ordsn) ?0? no blinking ?1? blinking blinking master specification register (1 bit) bkmf (bit 5 in oretc) ?0? disable blinking ?1? enable blinking (characters whose blf are set to ?1? are not displayed.) note: regarding the extra dot of the left and/or right character by fringing function, it is not enabled as blink.
tmp88cs34/cp34 2006-07-06 88cs34-184 (5) underline function underline function is used to add a line und er a display character. the underline is same color as that of character. underline specification unit: character/line underline enable register (character unit) (1 bit) eul (bit 5 in ordsn) ?0? no underline ?1? underline underline enable register (line unit) (1 bit 12) eulan (n: 1 to 8) (oreula8), eulan (n: 9 to 12) (oreula12) underline colors: 8 or 27 underline color specification registers (3 bits) rdt, gdt, bdt (bit 2 to 0 in ordsn) (refer to table 2.15.10) note 1: to use the underline function, set both the underline enable register for underlining text in characters and that for underlining text in lines . if the former register (eul) only is set, an underline is not displayed. note 2: a color font underline can be display ed in colors set up using rdt, gdt, and rdt. figure 2.14.34 underline underline display area 6 18 24 16 character displa y area eul = 0 eul = 1
tmp88cs34/cp34 2006-07-06 88cs34-185 (6) solid space control solid space control is used to display one column of solid space to the left and right of 32 columns. solid space control is used to delete the video signal in the areas where solid spaces are located in the original display page, then add color (raster color) to them. solid space specification unit: line solid space specification register (24 bits) for line 1 sol11 and sol10 (bits 1 and 0 in orsol4) for line 2 sol21 and sol20 (bits 3 and 2 in orsol4) . . . . . . for line 12 sol121 and sol120 (bits 7 and 6 in orsol12) solid space specification the solid space control functions as follows: solx1/solx0 (x = 1 to 12) ?00? no solid space display ?01? solid space display left for 32 columns ?10? solid space display right for 32 columns ?11? solid space display left and right for 32 columns solid space color specific ation registers (3 bits) rbdt, gbdt, bbdt (bits 2 to 0 in orbk) (same color as that of background) figure 2.14.35 solid space solid space (right) 32 columns solid space (left)
tmp88cs34/cp34 2006-07-06 88cs34-186 (7) slant function slant function is used to slant characters for italics. slant specification unit: character slant enable register (1 bit) slnt (bit 6 in ordsn) ?0? no slant ?1? slant note 1: slant function is enabled each characte rs, and therefore, in case of using background function, this color of the background is enabl e as slant. regarding the extra dots of the left and/or right character by fringing function, it is not enabled as slant. note 2: when a character is slanted in an area, which overlaps with the character field, the overlap is also slanted. note 3: if slanting a character causes part of the character to get into the character field to the immediate right of the character, then this part is not displayed. note 4: r, g, b, and y are all slanted. thus, if the y signal is selected, a video signal is displayed above and to the left of the slant character. if the specified background color is black, setting yblcs to 1 prevents the upper-left video signal for a slant character from being displayed. note 5: when a character is slanted, the dot data to the immediate left of the character is also slanted. note 6: do not specify slanting for the color font. figure 2.14.36 slant the same color as that of the dot on the left is displayed. when an entire character field (including its back g round ) contains dots: when the character field on the right does not contain a dot:
tmp88cs34/cp34 2006-07-06 88cs34-187 (8) functions supporting pal100/ntsc120 this lsi package supports the pal (phase alternating lines) 100 and ntsc (national television system community ) 120 broadcasting systems. figure 2.14.35 schematically shows the supported screen scanning method. figure 2.14.37 pal100/ntsc120 image sc anning lines (schematic diagram) pal100 support enable unit: screen pal100 support enable register (1 bit): epal100 (bit 5 in the ordon register) pal100 screen display start enable register (1 bit): paltrg (bit 0 in the orstrg register) to support pal100/ntsc120, follow this procedure. (a) to use pal100/ntsc120, set the epal100 osd control register (bit 5 in the ordon register) to ?1?. (b) read the phase detection results, pdf0 to pdf2, of the horizontal sync signal (hd) and the vertical sync signal (vd) (bits 6, 5, and 0 in the jesr jitter elimination status register) each time a vd interrupt occurs. (c) by reading the phase detection results pdf0 to pdf2, the phase of screen scanning is determined according to the detected field (1st or 2nd field). (d) write paltrg (bit 0 in the orstrg register) during the second cycle of the 2nd field (2nd field 2). once paltrg has been written, it becomes possible to support pal100/ntsc120 for osd display in the next field (1st field). note 1: use software to determi ne the write timing for paltrg. note 2: it is impossible to normally display the screen on the field of which paltrg is written. note 3: to read the phase detection results pdf0 to pdf2, write ?1? to the jeen jitter elimination control register (bit 2 in the jecr register) to enable the jitter elimination circuit. a a a a 1st field 1 2nd field 1 1st field 2 2nd field 2
tmp88cs34/cp34 2006-07-06 88cs34-188 2.14.6.8 osd control registers can not access all osd control registers in any of read-modify-write instructions such as bit operation, etc. 7 6 5 4 3 2 1 0 0rhs1 (00f81h) hs17 hs16 hs15 hs14 hs13 hs12 hs11 hs10 (initial value: 0000 0000) horizontal display star t position specification write only 7 6 5 4 3 2 1 0 orvs1 (00f82h) vs17 vs16 vs15 vs14 vs13 vs12 vs11 vs10 (initial value: 0000 0000) (00f83h) ? ? ? ? ? ? vs19 vs18 (initial value: **** ** 00) orvs2 (00f84h) vs27 vs26 vs25 vs24 vs23 vs22 vs21 vs20 (initial value: 0000 0000) (00f85h) ? ? ? ? ? ? vs29 vs28 (initial value: **** ** 00) orvs3 (00f86h) vs37 vs36 vs35 vs34 vs33 vs32 vs31 vs30 (initial value: 0000 0000) (00f87h) ? ? ? ? ? ? vs39 vs38 (initial value: **** ** 00) orvs4 (00f88h) vs47 vs46 vs45 vs44 vs43 vs42 vs41 vs40 (initial value: 0000 0000) (00f89h) ? ? ? ? ? ? vs49 vs48 (initial value: **** ** 00) orvs5 (00f8ah) vs57 vs56 vs55 vs54 vs53 vs52 vs51 vs50 (initial value: 0000 0000) (00f8bh) ? ? ? ? ? ? vs59 vs58 (initial value: **** ** 00) orvs6 (00f8ch) vs67 vs66 vs65 vs64 vs63 vs62 vs61 vs60 (initial value: 0000 0000) (00f8dh) ? ? ? ? ? ? vs69 vs68 (initial value: **** ** 00) orvs7 (00f8eh) vs77 vs76 vs75 vs74 vs73 vs72 vs71 vs70 (initial value: 0000 0000) (00f8fh) ? ? ? ? ? ? vs79 vs78 (initial value: **** ** 00) orvs8 (00f90h) vs87 vs86 vs85 vs84 vs83 vs82 vs81 vs80 (initial value: 0000 0000) (00f91h) ? ? ? ? ? ? vs89 vs88 (initial value: **** ** 00) orvs9 (00f92h) vs97 vs96 vs95 vs94 vs93 vs92 vs91 vs90 (initial value: 0000 0000) (00f93h) ? ? ? ? ? ? vs99 vs98 (initial value: **** ** 00) orvs10 (00f94h) vs107 vs106 vs105 vs104 vs103 vs102 vs101 vs 100 (initial value: 0000 0000) (00f95h) ? ? ? ? ? ? vs109 vs108 (initial value: **** ** 00) orvs11 (00f96h) vs117 vs116 vs115 vs114 vs113 vs112 vs 111 vs110 (initial value: 0000 0000) (00f97h) ? ? ? ? ? ? vs119 vs118 (initial value: **** ** 00) orvs12 (00f98h) vs127 vs126 vs125 vs124 vs123 vs122 vs 121 vs120 (initial value: 0000 0000) (00f99h) ? ? ? ? ? ? vs129 vs128 (initial value: **** ** 00) vsn8 to 0 vertical display start position for line n write only (n: 1 to 12) note 1: if display lines are overlapped each other, previ ous display line is enabled and ne xt line is disabled. set the vertical display start positi on not to overlap display lines. note 2: transfer the contents of vertical display start pos ition registers into osd circuit before a position of the scanning line coincides with their own vertical display start position.
tmp88cs34/cp34 2006-07-06 88cs34-189 7 6 5 4 3 2 1 0 orcs4 (00f9ah) cs4 cs3 cs2 cs1 (initial value: 0000 0000) orcs8 (00f9bh) cs8 cs7 cs6 cs5 (initial value: 0000 0000) orcs12 (00f9ch) cs12 cs11 cs10 cs9 (initial value: 0000 0000) csn character size and display on/off for line n 00: display off 01: large size 10: middle size 11: small size write only (n: 1 to 12) eula8 eula7 eula6 eula5 eula4 eula3 eula2 eula1 (initial value: 0000 0000) oreula8 (00f9dh) oreula12 (00f9eh) ? ? ? ? eula12 eula11 eula10 eula9 (initial value: **** 0000) eulan underline for display line for line n 0: display off 1: display on (n: 1 to 12) 7 6 5 4 3 2 1 0 efr8 efr7 efr6 efr5 efr4 efr3 efr2 efr1 (initial value: 0000 0000) orefr8 (00f9fh) orefr12 (00fa0h) ? ? ? ? efr12 efr11 efr10 efr9 (initial value: **** 0000) efrn fringing enable specification register for line n 0: disable fringing 1: enable fringing write only (n: 1 to 12) orslo4 (00fa2h) slo4 slo3 slo2 slo1 (initial value: 0000 0000) orslo8 (00fa3h) slo8 slo7 slo6 slo5 (initial value: 0000 0000) orslo12 (00fa4h) slo12 slo11 slo10 slo9 (initial value: 0000 0000) slon solid space for line n 00: no solid space display 01: solid space display left 10: solid space display right 11: solid space display left and right write only (n: 0 to 12)
tmp88cs34/cp34 2006-07-06 88cs34-190 7 6 5 4 3 2 1 0 orbk (00fa5h) ? rbdt gbdt bbdt ? rfdt gfdt bfdt (initial value: 0000 0000) rbdt/ gbdt/ bbdt background color select 000: setting color of orcpt0 001: setting color of orcpt1 010: setting color of orcpt2 011: setting color of orcpt3 000: setting color of orcpt4 101: setting color of orcpt5 110: setting color of orcpt6 111: setting color of orcpt7 rfdt/ gfdt/ bfdt fringing color select 000: setting color of orcpt0 001: setting color of orcpt1 010: setting color of orcpt2 011: setting color of orcpt3 000: setting color of orcpt4 101: setting color of orcpt5 110: setting color of orcpt6 111: setting color of orcpt7 write only
tmp88cs34/cp34 2006-07-06 88cs34-191 7 6 5 4 3 2 1 0 oracl (00fa6h) pisel2 aclr2 aclg2 aclb2 pisel1 aclr1 aclg1 aclb1 (initial value: 0000 0000) aclr2/ aclg2/ aclb2 area 2 plane color select 000: setting color of orcpt0 001: setting color of orcpt1 010: setting color of orcpt2 011: setting color of orcpt3 000: setting color of orcpt4 101: setting color of orcpt5 110: setting color of orcpt6 111: setting color of orcpt7 aclr1/ aclg1/ aclb1 area 1 plane color select 000: setting color of orcpt0 001: setting color of orcpt1 010: setting color of orcpt2 011: setting color of orcpt3 000: setting color of orcpt4 101: setting color of orcpt5 110: setting color of orcpt6 111: setting color of orcpt7 pisel2 0: not assign half transparency for area 2 plane 1: assign half transparency for area 2 plane pisel1 0: not assign half transparency for area 1 plane 1: assign half transparency for area 1 plane write only
tmp88cs34/cp34 2006-07-06 88cs34-192 7 6 5 4 3 2 1 0 oriv (00fbbh) vdpol hdpol yblii rgbii yiv bliv rgbiv iiv (initial value: 0000 0000) vdpol vd input polarity select 0: non-invert input signal 1: invert input signal hdpol hd input polarity select 0: non-invert input signal 1: invert input signal yblii y/blin input polarity select 0: active high 1: active low rgbii rin, gin, bin input polarity select 0: active high 1: active low yiv y output polarity select 0: active high 1: active low bliv bl output polarity select 0: active high 1: active low rgbiv r, g, b output polarity select 0: active high 1: active low iiv i output polarity select 0: active high 1: active low write only 7 6 5 4 3 2 1 0 ordma (00024h) dma7 dma6 dma5 dma4 dma3 dma2 dma1 dma0 (initial value: 0000 0000) (00025h) ? ? ? ? ? ? ? dma8 (initial value: **** *** 0) dman display memory address write only (n: 0 to 8) note: it is necessary to write all bits of disp lay memory address, writng dma7 to dma0 after dma8, when writing display address. 7 6 5 4 3 2 1 0 ordsn (0001dh) ? slnt eul blf ecbkd rdt gdt bdt (initial value: **** **** ) slnt slant enable specification register 0: disable slant 1: enable slant eul underline enable specification register 0: disable underline 1: enable underline blf blinking enable specification register 0: disable blinking 1: enable blinking ecbkd character-specific background on/off specification 0: disable backgournd color display 1: enable backgournd color display rdt/ gdt/ bdt character color select 000: setting color of orcpt0 001: setting color of orcpt1 010: setting color of orcpt2 011: setting color of orcpt3 000: setting color of orcpt4 101: setting color of orcpt5 110: setting color of orcpt6 111: setting color of orcpt7 read/ write note: to display a background color, write "1" to ebkgd (bit 7 in the orrcl register) to enable the background function enable r egister for the entire screen.
tmp88cs34/cp34 2006-07-06 88cs34-193 7 6 5 4 3 2 1 0 orcra (0001eh) cra7 cra6 cra5 cra4 cra3 cra2 cra1 cra0 (initial value: **** **** ) (0001fh) ? ? ? ? ? ? ? cra8 (initial value: **** **** ) cran character code read/ write (n: 0 to 8) note: write or read cra7 to cra0 after write or read cra8. 7 6 5 4 3 2 1 0 orwvsh (00fbch) wvsh7 wvsh6 wvsh5 wvsh4 wvsh3 w vsh2 wvsh1 wvsh0 (initial value: 0000 0000) (00fbdh) ? ? ? ? ? ? wvsh9 wvsh8 (initial value: **** ** 00) wvsln window upper limit position write only (n: 0 to 9) 7 6 5 4 3 2 1 0 orwvsl (00fbeh) wvsl7 wvsl6 wvsl5 wvsl4 wvsl3 wvsl2 wvsl1 wvsl0 (initial value: 0000 0000) (00fbfh) ? ? ? ? ? ? wvsl9 wvsl8 (initial value: **** ** 00) wvsln window lower limit position write only (n: 0 to 9) 7 6 5 4 3 2 1 0 ordon (00f80h) ? ? epal100 romach echdsn rgwr ewdw don (initial value: ** 00 0000) epal100 pal100 mode specification register 0: pal100 mode disable 1: pal100 mode enable romach monochrome/color font area switching register 0: 383 monochrome font characters 96 color font characters 1: 447 monochrome font characters 64 color font characters echdsn character-specific background color setting on/off specification register 0: character-specific background color setting off 1: character-specific background color setting on rgwr data transfer control osd register 0: (initial setting) 1: written data is transferred to the osd circuit (cleared to "0" after the transfer). ewdw window enable specification register 0: window specification off 1: window specification on don display on/off specification register 0: display off 1: display on read/ write note 1: * : don?t care note 2: all osd control registers cannot use the read-modify-write instruct ions. (bit manipulation instructions such as set, clr, etc. and logical operation such as and, or, etc.)
tmp88cs34/cp34 2006-07-06 88cs34-194 7 6 5 4 3 2 1 0 orrcl (00fa7h) ebkgd exbl aon2 aon1 ? rclr rclg rclb (initial value: 0000 * 000) ebkgd background function enable specification register 0: no background function 1: background function enable exbl full-raster blanking enable specification register 0: no full-raster blanking 1: full-raster blanking aon2 area 2 plane display enable specification register 0: no area 2 plane display 1: area 2 plane display enable aon1 area 1 plane display enable specification register 0: no area 1 plane display 1: area 1 plane display enable rclr/ rclg/ rclb raster plane color select 000: setting color of orcpt0 001: setting color of orcpt1 010: setting color of orcpt2 011: setting color of orcpt3 000: setting color of orcpt4 101: setting color of orcpt5 110: setting color of orcpt6 111: setting color of orcpt7 write only
tmp88cs34/cp34 2006-07-06 88cs34-195 7 6 5 4 3 2 1 0 orahs1 (00fa8h) ahs17 ahs16 ahs15 ahs14 ahs13 ahs12 ahs11 ahs10 (initial value: 0000 0000) (00fa9h) ? ? ? ? ? ? ? ahs18 (initial value: **** *** 0) orahe1 (00faah) ahe17 ahe16 ahe15 ahe14 ahe13 ahe12 ahe11 ahe10 (initial value: 0000 0000) (00fabh) ? ? ? ? ? ? ? ahe18 (initial value: **** *** 0) ahs1n horizontal start point for area 1 plane ahe1n horizontal end point for area 1 plane write only (n: 0 to 8) oravs1 (00fach) avs17 avs16 avs15 avs14 avs13 avs12 avs11 avs10 (initial value: 0000 0000) (00fadh) ? ? ? ? ? ? avs19 avs18 (initial value: **** ** 00) orave1 (00faeh) ave17 ave16 ave15 ave14 ave13 ave12 ave11 ave10 (initial value: 0000 0000) (00fafh) ? ? ? ? ? ? ave19 ave18 (initial value: **** ** 00) avs1n vertical start point for area 1 plane ave1n vertical end point for area 1 plane write only (n: 0 to 9) orahs2 (00fb0h) ahs27 ahs26 ahs25 ahs24 ahs23 ahs22 ahs21 ahs20 (00fb1h) ? ? ? ? ? ? ? ahs28 orahe2 (00fb2h) ahe27 ahe26 ahe25 ahe24 ahe23 ahe22 ahe21 ahe20 (initial value: 0000 0000) (00fb3h) ? ? ? ? ? ? ? ahe28 (initial value: **** *** 0) ahs2n horizontal start point for area 2 plane ahe2n horizontal end point for area 2 plane write only (n: 0 to 8) oravs2 (00fb4h) avs27 avs26 avs25 avs24 avs23 avs22 avs21 avs20 (initial value: 0000 0000) (00fb5h) ? ? ? ? ? ? avs29 avs28 (initial value: **** ** 00) orave2 (00fb6h) ave27 ave26 ave25 ave24 ave23 ave22 ave21 ave20 (initial value: 0000 0000) (00fb7h) ? ? ? ? ? ? ave29 ave28 (initial value: **** ** 00) avs2n vertical start point for area 2 plane ave2n vertical end point for area 2 plane write only (n: 0 to 9)
tmp88cs34/cp34 2006-07-06 88cs34-196 7 6 5 4 3 2 1 0 orp6s (00fbah) p67s p66s p65s p64s pids yblcs mpxs (initial value: 0000 0000) p67s to p64s p6 port output select 0: r, g, b, y/bl signal output 1: port contents output pids i pin output select 0: i signal output 1: port contents output yblcs y/bl signal select 0: y signal output 1: bl signal output mpxs r, g, b, y/bl signal select 00: simultaneous output (signal from the osd circuit has higher priority.) 01: output of signal from internal osd circuit 10: output of signal from externally input 11: simultaneous output (externally input signal has higher priority.) write only 7 6 5 4 3 2 1 0 oretc (00fb8h) vdsmd ?0? bkmf esmz ?0? mfywr mbk rdwrv (initial value: 0000 0000) vdsmd scan mode select 0: normal mode 1: double scan mode bkmf blinking master 0: double blinking 1: enable blinking esmz smoothing enable specification register 0: disable smoothing 1: enable smoothing mfywr display memory read mode select 0: normal mode 1: read-modify-write-mode mbk display memory bank switching 0: access to either character code or character display options 1: access both character code and character display option rdwrv read/write mode select at normal mode 0: data write mode for display memory 1: data read mode for display memory write only note: clear ?0? to bit 6 and 3 in oretc.
tmp88cs34/cp34 2006-07-06 88cs34-197 7 6 5 4 3 2 1 0 orirc (00fb9h) ? ? ? sdv isdc (initial value: *** 0 0000) svd interrupt source select 0: interrupt request by isdc value 1: interrupt request at falling edge of vd signal isdc interrupt generation line select when the line display of the isdc value ends (with the falling edge of hd signal) while svd = 0, interrupt request is generated. 0000: request interrupt when display of low-order 4 bits ?0000? of dctr ends. 0001: low-order 4 bits ?0001? of dctr 0010: low-order 4 bits ?0010? of dctr 0011: low-order 4 bits ?0011? of dctr 0100: low-order 4 bits ?0100? of dctr 0101: low-order 4 bits ?0101? of dctr 0110: low-order 4 bits ?0110? of dctr 0111: low-order 4 bits ?0111? of dctr 1000: low-order 4 bits ?1000? of dctr 1001: low-order 4 bits ?1001? of dctr 1010: low-order 4 bits ?1010? of dctr 1011: low-order 4 bits ?1011? of dctr 1100: low-order 4 bits ?1100? of dctr 1101: low-order 4 bits ?1101? of dctr 1110: low-order 4 bits ?1110? of dctr 1111: low-order 4 bits ?1111? of dctr write only orirc (00fb9h) ? ? ? ? dctr (initial value: **** 0000) dctr display line counter 0000: no line display or when the display of the 16th line ends. 0001: 1st line display ends. 0010: 2nd line display ends. 0011: 3rd line display ends. 0100: 4th line display ends. 0101: 5th line display ends. 0110: 6th line display ends. 0111: 7th line display ends. 1000: 8th line display ends. 1001: 9th line display ends. 1010: 10th line display ends. 1011: 11th line display ends. 1100: 12th line display ends. 1101: 13th line display ends. 1110: 14th line display ends. 1111: 15th line display ends. read only note: the display line counter also increments when a line with all blank data or a line with display off is specified. if display lines are overlapped each other, previous display line is enabled and next line is disabled. at this time, the display line counter also increments.
tmp88cs34/cp34 2006-07-06 88cs34-198 7 6 5 4 3 2 1 0 dcsc8 dcsc7 dcsc6 dcsc5 dcsc4 dcsc3 dcs c2 dcsc1 (initial value: 0000 0000) ordcsc (00fc4h) (00fc5h) ? ? ? ? dcsc12 cdsc11 cdsc10 cdsc9 (initial value: **** 0000) dcscn n: double-height specification for row n n: 1 to 12 0: display a medium-size character when medium-size character display is specified. 1: display a double-height character when medium-size character display is specified. write only note: to display double-height characters, write ?10? to csn (n = 1 to 12) in the orcsm (m = 4, 8, 12) register, specify the medium character si ze, and write ?1? to dcscn (n = 1 to 12). 7 6 5 4 3 2 1 0 orcpt0 (00fc6h) cpt0md1 fixed at 0 cpt0r1 cpt0r0 cpt0g1 cpt0g0 cpt0b1 cpt0b0 (initial value: 0000 0000) 7 6 5 4 3 2 1 0 orcpt1 (00fc7h) ? ? cpt1r1 cpt1r0 cpt1g1 cpt1g0 cp t1b1 cpt1b0 (initial value: ** 00 0000) 7 6 5 4 3 2 1 0 orcpt2 (00fc8h) ? ? cpt2r1 cpt2r0 cpt2g1 cpt2g0 cp t2b1 cpt2b0 (initial value: ** 00 0000) 7 6 5 4 3 2 1 0 orcpt3 (00fc9h) ? ? cpt3r1 cpt3r0 cpt3g1 cpt3g0 cp t3b1 cpt3b0 (initial value: ** 00 0000) 7 6 5 4 3 2 1 0 orcpt4 (00fcah) ? ? cpt4r1 cpt4r0 cpt4g1 cpt4g0 cp t4b1 cpt4b0 (initial value: ** 00 0000) 7 6 5 4 3 2 1 0 orcpt5 (00fcbh) ? ? cpt5r1 cpt5r0 cpt5g1 cpt5g0 cp t5b1 cpt5b0 (initial value: ** 00 0000) 7 6 5 4 3 2 1 0 orcpt6 (00fcch) ? ? cpt6r1 cpt6r0 cpt6g1 cpt6g0 cp t6b1 cpt6b0 (initial value: ** 00 0000) 7 6 5 4 3 2 1 0 orcpt7 (00fcdh) ? ? cpt7r1 cpt7r0 cpt7g1 cpt7g0 cp t7b1 cpt7b0 (initial value: ** 00 0000) cpt0md1 27-color mode specification register 0: 8-color mode 1: 27-color mode write only cptomd1 = 0 cptomd1 = 1 cptxr0 cptxr1 r luminance specification register crtxr1 = 0, crtxr0 = 0: no output crtxr1 = 0, crtxr0 = 1: light red crtxr1 = 1, crtxr0 = 0: light red crtxr1 = 1, crtxr0 = 1: light red crtxr1 = 0, crtxr0 = 0: no output crtxr1 = 0, crtxr0 = 1: dark red crtxr1 = 1, crtxr0 = 0: dark red crtxr1 = 1, crtxr0 = 1: light red cptxg0 cptxg1 g luminance specification register crtxg1 = 0, crtxg0 = 0: no output crtxg1 = 0, crtxg0 = 1: light green crtxg1 = 1, crtxg0 = 0: light green crtxg1 = 1, crtxg0 = 1: light green crtxg1 = 0, crtxg0 = 0: no output crtxg1 = 0, crtxg0 = 1: dark green crtxg1 = 1, crtxg0 = 0: dark green crtxg1 = 1, crtxg0 = 1: light green cptxb0 cptxb1 b luminance specification register crtxb1 = 0, crtxb0 = 0: no output crtxb1 = 0, crtxb0 = 1: light blue crtxb1 = 1, crtxb0 = 0: light blue crtxb1 = 1, crtxb0 = 1: light blue crtxb1 = 0, crtxb0 = 0: no output crtxb1 = 0, crtxb0 = 1: dark blue crtxb1 = 1, crtxb0 = 0: dark blue crtxb1 = 1, crtxb0 = 1: light blue write only 7 6 5 4 3 2 1 0 orstrg1 (00fceh) ? ? ? ? ? ? ? paltrg (initial value: **** *** 0) palrg pal100 mode trigger start register 0: pal trigger stop 1: pal trigger start write only
tmp88cs34/cp34 2006-07-06 88cs34-199 osd control register list (1/3) register bit configuration register address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit contents r/w 0001d ordsn ? slnt eul blf ecbkd rdt gdt bdt when echdsn = 0 slnt = 1: slant enable, 0: slant disable eul = 1: underline display on, 0: underline display off when echdsn = 1 slnt: background color red eul: background color green blf = 1: blinking enable, 0: blinking disable ecbkd = 1:character background color display enable, character background color display disable r/w 0001e orcra cra7 cra6 cra5 cra4 cra3 cra2 cra1 cra0 0001f ? ? ? ? ? ? ? cra8 crax: character code (x: 0 to 8) r/w 00024 ordma dma7 dma6 dma5 dma4 dma3 dma2 dma1 dma0 00025 ? ? ? ? ? ? ? dma8 dmax: display memory address setting (x: 0 to 8) w 00f80 ordon ? ? epal100 romach echdsn rgwr ewdw don epal100 = 1: pal100/ntsc120 select, 0: other romach: select font number (mono font/color font) 1: 447 mono font character/64 color font character, 0: 383 mono font character/96 color font character echdsn = 1: bit 6 and 5 in ordsn is changed to character background color, 0: bit 6 and 5 in ordsn is character ornamentation rgwr: writing data transfer control bit ewdw = 1: window function enable, 0: window function disable don = 1: osd display on, 0: osd display off r/w 00f81 orhs1 hs17 hs16 hs15 hs14 hs13 hs12 hs11 hs10 hs17 to hs10: code horizontal display base position setting w 00f82 orvs1 vs17 vs16 vs15 vs14 vs13 vs12 vs11 vs10 00f83 ? ? ? ? ? ? vs19 vs18 vs19 to vs10: code vertical display potision setting w 00f84 orvs2 vs27 vs26 vs25 vs24 vs23 vs22 vs21 vs20 00f85 ? ? ? ? ? ? vs29 vs28 vs29 to vs20: code vertical display potision setting w 00f86 orvs3 vs37 vs36 vs35 vs34 vs33 vs32 vs31 vs30 00f87 ? ? ? ? ? ? vs39 vs38 vs39 to vs30: code vertical display potision setting w 00f88 orvs4 vs47 vs46 vs45 vs44 vs43 vs42 vs41 vs40 00f89 ? ? ? ? ? ? vs49 vs48 vs49 to vs40: code vertical display potision setting w 00f8a orvs5 vs57 vs56 vs55 vs54 vs53 vs52 vs51 vs50 00f8b ? ? ? ? ? ? vs59 vs58 vs59 to vs50: code vertical display potision setting w 00f8c orvs6 vs67 vs66 vs65 vs64 vs63 vs62 vs61 vs60 00f8d ? ? ? ? ? ? vs69 vs68 vs69 to vs60: code vertical display potision setting w 00f8e orvs7 vs77 vs76 vs75 vs74 vs73 vs72 vs71 vs70 00f8f ? ? ? ? ? ? vs79 vs78 vs79 to vs70: code vertical display potision setting w 00f90 orvs8 vs87 vs86 vs58 vs84 vs83 vs82 vs81 vs80 00f91 ? ? ? ? ? ? vs89 vs88 vs89 to vs80: code vertical display potision setting w 00f92 orvs9 vs97 vs96 vs95 vs94 vs93 vs92 vs91 vs90 00f93 ? ? ? ? ? ? vs99 vs98 vs99 to vs90: code vertical display potision setting w 00f94 orvs10 vs107 vs106 vs105 vs104 vs103 vs102 vs101 vs100 00f95 ? ? ? ? ? ? vs109 vs108 vs100 to vs109:code vertical display potision setting w 00f96 orvs11 vs117 vs116 vs115 vs114 vs113 vs112 vs111 vs100 00f97 ? ? ? ? ? ? vs119 vs118 vs110 to vs119:code vertical display potision setting w 00f98 orvs12 vs127 vs126 vs125 vs124 vs123 vs122 vs121 vs120 00f99 ? ? ? ? ? ? vs129 vs128 vs120 to vs129:code vertical display potision setting w 00f9a orcs4 cs4 cs3 cs2 cs1 00f9b orcs8 cs8 cs7 cs6 cs5 00f9c orcs12 cs12 cs11 cs10 cs9 csn: character size (n: 1 to 12) 00: display off 10: middle size 01: large size 11: small size w 00f9d oreula8 eula8 eula7 eula6 eula5 eula4 eula3 eula2 eula1 00f9e oreula12 ? ? ? ? eula12 eula11 eula10 eula9 eulan: underline display setting for line n (n: 0 to 12) w 00f9f orefr8 efr8 efr7 efr6 efr5 efr4 efr3 efr2 efr1 00fa0 orefr12 ? ? ? ? efr12 efr11 efr10 efr9 efrn: fringing setting for line n (n: 0 to 12) w
tmp88cs34/cp34 2006-07-06 88cs34-200 osd control register list (2/3) register bit configuration register address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit contents r/w 00fa2 orsol4 sol4 sol3 sol2 sol1 00fa3 orsol8 sol8 sol7 sol6 sol5 00fa4 orsol12 sol12 sol11 sol10 sol9 soln: solid space display setting for line n (n; 0 to 12) 00: no solid space 10: right 01: left 11: left and right w 00fa5 orbk ? rbdt gbdt bbdt ? rfdt gfdt bfdt rbdt, gbdt, bbdt: background color setting w 00fa6 oracl pisel2 aclr2 aclg2 aclb2 pisel1 aclr1 aclg1 aclb1 aclr2/aclg2/aclb2: area 2 plane color aclr1/aclg1/aclb1: area 1 plane color pisel2: set half transparency for area 2 plane pisel1: set half transparency for area 1 plane w 00fa7 orrcl ebkgd exbl aon2 aon1 ? rclr rclg rclb ebkgd: background function exbl: full-rasterblanking aon2: area 2 plane display aon1: area 1 plane display rclr/rclg/rclb:raster plane color 00fa8 ahs17 ahs16 ahs15 ahs14 ahs13 ahs12 ahs11 ahs10 00fa9 orahs1 ? ? ? ? ? ? ? ahs18 ahs1x: area 1 plane horizonatal start position (x: 0 to 8) 00faa ahe17 ahe16 ahe15 ahe14 ahe13 ahe12 ahe11 ahe10 00fab orahe1 ? ? ? ? ? ? ? ahe18 ahe1x: area 1 plane horizonatal end position (x: 0 to 8) 00fac avs17 avs16 avs15 avs14 avs13 avs12 avs11 avs10 00fad oravs1 ? ? ? ? ? ? avs19 avs18 avs1x: area 1 plane vertical start position (x: 0 to 8) 00fae ave17 ave16 ave15 ave14 ave13 ave12 ave11 ave10 00faf orave1 ? ? ? ? ? ? ave19 ave18 ave1x: area 1 plane vertical end position (x: 0 to 8) 00fb0 ahs27 ahs26 ahs25 ahs24 ahs23 ahs22 ahs21 ahs20 00fb1 orahs2 ? ? ? ? ? ? ? ahs28 ahs2x: area 2 plane horizonatal start position (x: 0 to 8) 00fb2 ahe27 ahe26 ahe25 ahe24 ahe23 ahe22 ahe21 ahe20 00fb3 orahe2 ? ? ? ? ? ? ? ahe28 ahe2x: area 2 plane horizonatal end position (x: 0 to 8) 00fb4 avs27 avs26 avs25 avs24 avs23 avs22 avs21 avs20 00fb5 oravs2 ? ? ? ? ? ? avs29 avs28 avs2x: area 2 plane vertical start position (x: 0 to 8) 00fb6 ave27 ave26 ave25 ave24 ave23 ave22 ave21 ave20 00fb7 orave2 ? ? ? ? ? ? ave29 ave28 ave2x: area 2 plane vertical end position (x: 0 to 8) 00fb8 oretc vdsmd 0 bkmf esmz 0 mfywr mbk rdwrv vdsmd: scan mode select bkmf: blinking master esmz: smoothing mfywr: display memory read mode select mbk: display memory bank switching select rdwrv: read/write mode select normal mode w 00fb9 orirc ? ? ? svd isdc svd: interrupt source select isdc: interrupt generation line select w 00fb9 orirc ? ? ? ? dctr dctr:display line counter r 00fba orp6s p67s p66s p65s p64s pids yblcs mpxs p6xs: p6 port output select (x:4 to 7) pids: i pin output select yblcs: y/bl signal select mpxs: r, g, b, y/bl signal select w 00fbb oriv vdpol hdpol yblii rgbii yiv bliv rgbiv iiv hdpol: vd input polarity select hdpol: hd input polarity select yblii: y/blin input polarity select rgbii: rin, gin, bin input polarity select y/v: y output polarity select bliv: bl output polarity select rgbiv: r, g, b output polarity select iiv: i pin output polarity select w 00fbc wvsh7 wvsh6 wvsh5 w vsh4 wvsh3 wvsh2 wvsh1 wvsh0 00fbd orwvsh ? ? ? ? ? ? wvsh9 wvsh8 wvshx: window upper limit position (x: 0 to 9) w 00fbe wvsl7 wvsl6 wvsl5 wvsl4 wvsl3 wvsl2 wvsl1 wvsl0 00fbf orwvsl ? ? ? ? ? ? wvsl9 wvsl8 wvslx: window lower limit position (x: 0 to 9) w 00fc2 ccd8 ccd7 ccd6 ccd5 ccd4 ccd3 ccd2 ccd1 00fc3 orccd ? ? ? ? ccd12 ccd11 ccd10 ccd9 ccdx: horizontal 16 dot and vertical 26 dot display at small size character (x: 0 to 12) w 00fc4 dcsc8 dcsc7 dcsc6 dcsc5 dcsc4 dcsc3 dcsc2 dcsc1 00fc5 ordcsc ? ? ? ? dcsc12 dcsc11 dcsc10 dcsc9 dcscx: double height display (x: 0 to 12) w
tmp88cs34/cp34 2006-07-06 88cs34-201 osd control register list (3/3) register bit configuration register address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit contents r/w 00fc6 orcpt0 cpt0md1 0 cpt0r1 cpt0r0 cpt0g1 cpt0g0 cpt0b1 cpt0b0 color palette composition register 0 cpt1md1: osd color select register (x: 1, 2) cpt1md1 = 0: 27-color select mode cpt1md1 = 1: 8-color select mode w 00fc7 orcpt1 ? ? cpt1r1 cpt1r0 cpt1g1 cpt1g0 cpt1b1 cpt1b0 color palette composition register 1 w 00fc8 orcpt2 ? ? cpt2r1 cpt2r0 cpt2g1 cpt2g0 cpt2b1 cpt2b0 color palette composition register 2 w 00fc9 orcpt3 ? ? cpt3r1 cpt3r0 cpt3g1 cpt3g0 cpt3b1 cpt3b0 color palette composition register 3 w 00fca orcpt4 ? ? cpt4r1 cpt4r0 cpt4g1 cpt4g0 cpt4b1 cpt4b0 color palette composition register 4 w 00fcb orcpt5 ? ? cpt5r1 cpt5r0 cpt5g1 cpt5g0 cpt5b1 cpt5b0 color palette composition register 5 w 00fcc orcpt6 ? ? cpt6r1 cpt6r0 cpt6g1 cpt6g0 cpt6b1 cpt6b0 color palette composition register 6 w 00fcd orcpt7 ? ? cpt7r1 cpt7r0 cpt7g1 cpt7g0 cpt7b1 cpt7b0 color palette composition register 7 w 00fce orstrg ? ? ? ? ? ? ? paltrg pal100/ntsc120 start trigger w note 1: except the meshed r egisters are changed by rgwr. note 2: only lower 2 bits of the register in addr ess 00f80h are changed by rgwr (the register in address 00f80h must not be used with any of the read-m odify-write instructions as set, clr, etc.).
tmp88cs34/cp34 2006-07-06 88cs34-202 2.15 jitter elimination circuit the tmp88cs34/cp34 has a built-in jitter elimination circuit which maintains the vertical stability of the osd even when input of the vertical signal fluctuates. and the field decision information for the osd ci rcuit is detected by using jitter elimination circuit. 2.15.1 configuration figure 2.15.1 jitter elimination circuit vd (to osd circuit) vdsel hd / vd edge detect circuit vd signal delay value measuring circuit hd (p70) jitter removal status register vd (p71) delay value setting circuit internal vd signal output control circuit a b y jecr jeen a fld a y b s previous field decision signal field decision circuit jrmsr phase detect signal pdf [2:0] jitter elimination control register fc/2
tmp88cs34/cp34 2006-07-06 88cs34-203 2.15.2 control jitter elimination circuit is controlled by the jitter elimination control register (jecr). jitter elimination control register 7 6 5 4 3 2 1 0 jecr (00fe4h) ? ? ? vdsel afld jeen ?0? ?0? (initial value: *** 0 0000) vdsel vd select 0: vd from p71 1: vd from jitter elimination circuit afld automatic field decision 0: automatic field decision disabled 1: automatic field decision enabled jeen jitter eliminati on enable specification 0: jitter elimination disabled 1: jitter elimination enabled write only note 1: clear the afld to ?0? to disable jitter elimination circuit. note 2: always clear ?0? to bit 1 and 0 of jecr. note 3: clear ?0? to afld and vdsel if there is no phas e shift in the vertical and horizontal sync. signals every other time, such as with non-interlaced tv. note 4: * : don?t care note 5: setting jeen to ?0?, osd display is only 2nd field. note 6: setting afld to ?0?, osd display is only 2nd field. jitter elimination status register 7 6 5 4 3 2 1 0 jesr (00fe5h) fdsf pdf1 pdf0 ? ? ? ? pdf2 (initial value: 0 *** **** ) fdsf field detect status flag 0: a position of a scanning line exists in the field which has a second display dot of character on an interlace tv screen. 1: a position of a scanning line exists in the field which has a first display dot of character on an interlace tv screen. pdf2, 1, 0 phase detect flag between hd and vd 000: phase 0 001: phase 1 010: phase 2 011: phase 3 100: phase 4 101: phase 5 110: phase 6 111: phase 7 read only note 1: fdsf is different from the 1st and the 2nd field. it is a unique fiel d decided for osd display. note 2: * : don?t care note 3: figure 2.15.2 jitter elimination control regi ster and jitter elimination status register 2.15.3 jitter elimination mode the jitter elimination circuit is to identify the phase of the falling edges of the external vd signal and hd signal. when vd signal is falling within hd signal falling + / ? 1/4hd, the jitter is automatically eliminated and internal vd signal is set to the stable location. this function is enabled by setting jeen (bit2 in jecr) in the jitter elimination control register to ?1?. phase 0 phase 1 phase 2 phase 3 phase 4 phase 5 phase 6 phase 7 phase 0 phase 7 vd hd
tmp88cs34/cp34 2006-07-06 88cs34-204 2.15.4 auto field line decision the internal vertical and horizontal sync. signals corrected by the jitter elimination circuit generate the field line decision signals used in the osd. the osd display in normal mode type a) when the osd circuit is used on th e tv system which has a phase shift in the vertical and horizontal sync. signals ev ery other filed such as the interlace tv, enable jitter elimination circuit and set ?1? to afld and vdsel. at this time, the field lines which have first and second display dot of character are displayed. type b) when the osd circuit is used on the tv system which has no phase shift in the vertical and horizontal sync. si gnals every other filed such as the non-interlace tv, enable jitter elimination circuit and clear ?0? to afld and vdsel. at this time, the field line which has a second display dot of character is only displayed. the osd display in double scan mode type c) disable jitter elimination circuit and clear ?0? to afld and vdsel. at this time, the field lines which have first and second display dot of character are displayed. scanning system register display type a vdsel = 1, afld = 1 (1) and (2) type b vdsel = 0, afld = 0 (2) type c vdsel = 0, afld = 0 (1) and (2) figure 2.15.3 relation with field line and vdsel, afld (1) the field line which has a first display dot of character (2) the field line which has a second display dot of character
tmp88cs34/cp34 2006-07-06 88cs34-205 input/output circuit (1) control pins the input/output circuitries of the tmp88cs34/cp34 control pins are shown below. control pin i/o input/output circuitry remarks xin xout i/o resonator connecting pins (high-frequency) r f = 1.2 m (typ.) r o = 0.5 k (typ.) reset i/o sink open drain output hysteresis input pull-up register r in = 220 m (typ.) r = 1 k (typ.) stop / 5 int (p20) input hysteresis input r = 1 k (typ.) test input pull-down register r in = 70 k (typ.) r = 1 k (typ.) osc1 osc2 i/o pin for connecting a resonator for on-screen display r f = 1.2 m (typ.) r o = 0.5 k (typ.) osc. enable fc vdd vdd osc1 osc2 r f r o a ddress-trap-reset watchdog-timer-reset system-clock-reset r in vdd r p20/ stop / 5 int vdd r r in vdd r osc. enable fc vdd vdd xin xout r f r o
tmp88cs34/cp34 2006-07-06 88cs34-206 (2) input/output ports port i/o input/output circuitry remarks p20 i/o sink open drain output hysteresis input r = 1 k (typ.) p30 to p33 p50, p57 p70, p71 i/o tri-state i/o hysteresis input r = 1 k (typ.) p34, p35, p51, p52 i/o tri-state i/o or open drain output programmable hysteresis input r = 1 k (typ.) p40 to p47 i/o tri-state i/o r = 1 k (typ.) p53 to p56 i/o tri-state i/o hysteresis input key-on wake-up input (v il4 = 0.65 v dd) r = 1 k (typ.) r a = 5 k (typ.) c a = 22 pf (typ.) initial ?high-z? open drain out p ut enable vdd r initial ?high-z? r vdd disable initial ?high-z? r vdd disable r a c a ke y -on wake-u p initial ?high-z? r vdd disable initial ?high-z? r vdd disable
tmp88cs34/cp34 2006-07-06 88cs34-207 port i/o input/output circuitry remarks p60 i/o sink open drain input/output high-current output i ol = 20 ma (typ.) r = 1 k (typ.) r a = 5 k (typ.) c a = 22 pf (typ.) key-on wake-up input (v il4 = 0.65 v dd) p61 i/o tri-state input/output r = 1 k (typ.) r a = 5 k (typ.) c a = 22 pf (typ.) key-on wake-up input (v il4 = 0.65 v dd) p62 to p67 i/o tri-state input/output r = 1 k (typ.) r a c a ke y -on wake-u p initial ?high-z? r vdd disable r a c a ke y -on wake-u p initial ?high-z? r vdd disable initial ?high-z? r vdd disable
tmp88cs34/cp34 2006-07-06 88cs34-208 electrical characteristics absolute maximum ratings (v ss = 0 v) parameter symbol pins ratings unit supply voltage v dd ? ? 0.3 to 6.5 input voltage v in ? ? 0.3 to v dd + 0.3 output voltage v out1 ? ? 0.3 to v dd + 0.3 v i out1 ports p2, p3, p4, p5, p61 to p67, p7 3.2 output current (per 1 pin) i out2 ports p60 30 i out1 ports p2, p3, p4, p5, p64 to p67, p7 30 output current (total) i out2 ports p60 30 ma power dissipation [topr = 70 c] pd ? 400 mw soldering temperature (time) tsld ? 260 (10 s) storage temperature tstg ? ? 55 to 125 operating temperature topr ? ? 30 to 70 c note: the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. recommended operating conditions (v ss = 0 v, topr = ? 30 to 70 c) parameter symbol pins conditions min max unit fc = 16 mhz normal mode fc = 16 mhz idle mode supply voltage v dd stop mode 4.5 5.5 v ih1 except hysteresis input v dd 0.70 v ih2 hysteresis input v dd 0.75 input high voltage v ih3 key-on wake-up input v dd = 4.5 to 5.5v v dd 0.90 v dd v il1 except hysteresis input v dd 0.30 v il2 hysteresis input v dd = 4.5 to 5.5v v dd 0.25 input low voltage v il3 key-on wake-up input v dd = 4.5 to 5.5v 0 v dd 0.65 v fc xin, xout v dd = 4.5 to 5.5v 8.0 16.0 fc = 8 mhz 8.0 12.0 clock frequency f osc internal clock v dd = 4.5 to 5.5v fc = 16 mhz 16.0 24.0 mhz note 1: the recommended operating conditions for a devic e are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), ma lfunction may occur. thus, when designing products which include this device, ensure that the re commended operating conditions for the device are always adhered to. note 2: clock frequency fc: supply voltage range is specified in normal mode and idle mode. note 3: smaller value is alternatively specified as the maximum value.
tmp88cs34/cp34 2006-07-06 88cs34-209 dc characteristics (v ss = 0 v, topr = ? 30 to 70 c) parameter symbol pins conditions min typ. max unit hysteresis voltage v hs hysteresis inputs ? 0.9 ? v i in1 test v dd = 5.5 v, v in = 5.5 v/0 v ? ? 2 i in2 open drain ports v dd = 5.5 v, v in = 5.5 v/0 v ? ? 2 i in3 tri-state ports v dd = 5.5 v, v in = 5.5 v/0 v ? ? 2 input current i in4 reset , stop v dd = 5.5 v, v in = 5.5 v/0 v ? ? 2 a input resistance r in2 reset v dd = 5.5 v, v in = 0 v 100 220 450 k i lo1 sink open drain ports v dd = 5.5 v, v out = 5.5 v ? ? 2 output leakage current i lo2 tri-state ports v dd = 5.5 v, v out = 5.5 v/0 v ? ? 2 a output high voltage v oh2 tri-state ports v dd = 4.5 v, i oh = ? 0.7 ma 4.1 ? ? output low voltage v ol except xout and ports p60 v dd = 4.5 v, i ol = 1.6 ma ? ? 0.4 v output low current i ol3 port p60 v dd = 4.5 v, i ol = 1.0 v ? 20 ? supply current in normal mode ? 25 30 supply current in idle mode v dd = 5.5 v fc = 16 mhz (note3) v in = 5.3 v/0.2 v ? 20 25 ma supply current in stop mode i dd ? v dd = 5.5 v v in = 5.3 v/0.2 v ? 0.5 10 a note 1: typical values show those at topr = 25 c, v dd = 5 v. note 2: input current i in3 ; the current through resistor is not included. note 3: supply current i dd ; the current (typ. 0.5 ma) through ladd er resistors of adc is included in normal mode and idle mode. ad conversion characteristics (v ss = 0 v, v dd = 4.5 v to 5.5 v, topr = ? 30 to 70 c) parameter symbol conditions min typ. max unit v aref supplied from v dd pin. ? v dd ? analog reference voltage v ass supplied from v ss pin. ? 0 ? analog reference voltage range v aref = v dd ? v ss ? v dd ? analog input voltage v ain v ss ? v dd v nonlinearity error ? ? 1 zero point error ? ? 2 full scale error ? ? 2 total error v dd = 5.0 v ? ? 3 lsb note: the total error means all error except quanting error.
tmp88cs34/cp34 2006-07-06 88cs34-210 ac characteristics (v ss = 0 v, v dd = 4.5 v to 5.5 v, topr = ? 30 to 70 c) parameter symbol conditions min typ. max unit in normal mode machine cycle time t cy in idle mode 0.5 ? 1.0 s high level clock pulse width t wch low level clock pulse width t wcl for external clock operation (xin input), fc = 16 mhz 31.25 ? ? ns recommended oscillating conditions (v ss = 0 v, v dd = 4.5 v to 5.5 v, topr = ? 30 to 70 c) recommended constant parameter oscillator oscillation frequency recommended oscillator c 1 c 2 8 mhz murata csa 8.00mtz 30 pf 30 pf high-frequency oscillation ceramic resonator 16 mhz murata csa 16.00mxz040 5 pf 5 pf note 1: to keep reliable operation, shield the device electrically with the metal plate on its package mold surface against the high electric field, fo r example, by crt (cathode ray tube) . note 2: the product numbers and specifications of the resonators by murata manufacturing co., ltd. are subject to change. for up-to-date information, please refer to the following url; http://www.murata.co.jp/search/index.html xin xout high-frequency oscillation c 2 c 1
tmp88cs34/cp34 2006-07-06 88cs34-211 recommended oscillating conditions (v ss = 0 v, v dd = 4.5 v to 5.5 v, topr = ? 30 to 70 c) recommended parameter value item resonator oscillation frequency l ( h) c 1 (pf) c 2 (pf) 8 mhz 33 5 to 30 10 12 mhz 15 5 to 30 10 16 mhz 10 5 to 30 10 20 mhz 6.8 5 to 25 10 oscillation for osd lc resonator 24 mhz 4.7 5 to 25 10 the frequency generated in lc oscillation can be obtained using the following equations. c c c c c , lc 2 1 f 2 1 2 1 + = = ? c 1 is not fixed at a constant value. it can be changed to tune into the desired frequency. note 1: toshiba?s osd circuit determines a horizontal display start position by counting clock pulses generated in lc oscillation. for this reason, the osd circuit may fail to detect clock pulses normally, resulting in the horizontal start position becoming unstable, at the beginning of oscillation, if the oscillation amplitude is low. changing l and c 2 from the values recommended for a specific frequency may hamper a stable osd display. if the lc oscillation frequency is th e same as a high-freq uency clock value, th e oscillation of the high-frequency oscillator may cause the lc oscilla tion frequency to fluctuate, thus making osd displays flicker. when determining these parameters, please check the oscillation frequency and the stability of oscillation on your tv sets. also check the determined parameters on your fi nal products, because the optimum parameter values may vary from one product to another. note 2: when using the lsi package in a strong electric field, such as near a crt, electrically shield the package so that its normal operation can be maintained. osc1 osc2 oscillation for osd c 2 c 1 l
tmp88cs34/cp34 2006-07-06 88cs34-212 notice of rom entry the rom area must be transferred is as follows. flow of rom data entry when you make a rom data entry for tmp88cs34/cp34, please transfer one file including program ar ea, vector table area and osd font area. program area 4000h osd font area tmp88cs34 vector table area 13effh 20000h 2a7ffh fff00h fffffh program area 4000h osd font area tmp88cp34 vector table area feffh 20000h 2a7ffh fff00h fffffh program and vector table after evaluation finished two files are merged into one file. program vector table osd font rom data entry osd font
tmp88cs34/cp34 2006-07-06 88cs34-213 package p-sdip42-600-1.78 unit: mm
tmp88cs34/cp34 2006-07-06 88cs34-214 p-qfp44-1414-0.80d unit: mm
tmp88cs34/cp34 2006-07-06 88cs34-215

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