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u2739m-b rev. a1, 22-may-01 1 (69) dab one-chip channel- and source decoder description the u2739m-b is an integrated circuit in advanced cmos technology for demodulation and decoding of a dab signal according to ets 300 401. the channel decoder part includes the main features ofdm demodulation & decoding and time & frequency synchro- nization algorithms, using the embedded oak dsp core. the source decoder consists of an audio and a data decoder part. the audio source decoder supports iso mpeg 1,2 layer 2 and the data decoder offers 2 independent packet mode decoders. several standard interfaces, like i 2 c/l3, i 2 s, spdif or rdi are implemented to offer a flexible utilization. moreover the u2739m-b includes a mechanism to replace respectively extend certain software modules by using a special boot mode (so-called use). for example, the time & frequency synchronization modules can be replaced by down-loading the corresponding user software algorithms to the oak dsp core. electrostatic sensitive device. observe precautions for handling. block diagram channel decoder audio decoder data decoder rdi interface adc rom tuner dac i2s spdif v24/rs232 mc interface mcu sfco rdi ram u2739m?a hsso sli, wagc figure 1. block diagram ordering information extended type number package remarks u2739m-bft t?pqfp?g100 tray u2739m-bfc cqfp144 tray
u2739m-b rev. a1, 22-may-01 2 (69) table of contents 1 features 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 general 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 channel decoder 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 audio source decoder 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 data decoder 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 interfaces 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 functional block diagram 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin description 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 strap pins 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin configuration 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 interface description 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 overview 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 adc interface 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 adc interface signal description 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 adc interface description 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 adc interface timing diagram 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.4 adc interface timing parameters 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 tuner interface 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 tuner interface signal description 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 tuner interface description 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 mc interface 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 mc interface signal description 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 mc interface description 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 l3 bus interface timing diagram 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.4 l3 bus timing parameter 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.5 i2c bus interface timing diagram 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.6 i2c bus timing parameter 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 c-bus / boot bus interface 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 c-bus signal description 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 c-bus / boot bus interface description 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.3 boot bus timing diagram 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.4 boot bus timing parameter 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 sram interface 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 sram interface signal description 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.2 sram interface descriptions 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.3 sram interface timing diagram 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.4 sram interface timing parameter 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 vcxo interface 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.1 vcxo interface signal description 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7.2 vcxo interface description 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
u2739m-b rev. a1, 22-may-01 3 (69) table of contents (continued) 6.8 audio interfaces 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.1 i2s interface signal description 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.2 i2s interface description 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.3 i2s interface timing diagram 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.4 i2s interface timing parameter 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.5 sp-dif interface signal description 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.6 sp-dif interface description 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.7 sp-dif interface timing parameter 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8.8 sp-dif interface timing diagram 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 rdi interface 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.1 rdi interface signal description 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.2 rdi interface description 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.3 rdi interface timing diagram 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9.4 rdi interface timing parameter 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 sfco interface 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.1 sfco interface signal description 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.2 sfco interface description 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.3 sfco interface timing diagram 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.4 detailed sfco interface timing diagram 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10.5 sfco interface timing parameter 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 rs232 interface 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.1 rs232 interface signal description 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.2 rs232 interface description 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.3 rs232 interface timing diagram 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.4 rs232 interface timing parameter 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 hsso interface 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.1 hsso interface signal description 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.2 hsso interface description 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.3 hsso interface timing diagram 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12.4 hsso interface timing parameters 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 electrical characteristics 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 absolute maximum ratings 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 operating range 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 dc characteristics 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 mc command set 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 ? set system ? commands 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 set dab system mode 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2 set asd 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3 set dd1 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.4 set dd2 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.5 set cif counter and occurrence change 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.6 set current sbchid long form 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.7 set next sbchid long form 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.8 set current sbchid short form 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
u2739m-b rev. a1, 22-may-01 4 (69) table of contents (continued) 8.2 ? set configuration ? commands 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 set global configuration 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2 set ts configuration 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3 set fs configuration 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.4 set xo configuration 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.5 set hsso / rs232 configuration 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.6 set wagc configuration 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.7 set rcc slot configuration 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.8 set rfu 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 ? read status ? commands 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 read global status 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 read synchronization status 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 read cir status 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 ? read data ? commands 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 read asd header data 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 read x ? pad 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3 read f ? pad 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4 read aic data 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.5 read tii data 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.6 read efc data 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.7 read fic data 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.8 read rcc slot 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.9 read slot pointer 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.10 read rfu 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 package information 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
u2739m-b rev. a1, 22-may-01 5 (69) 1 features 1.1 general support of mode i, ii, iii and iv acc. to ets 300 401 time & frequency synchronization with a wide-range parameter set optional implementation of user-defined synchro- nization strategy by using use boot mode flexible software configuration: set 1 ? (temic kernel), set 2 ? (user extension) concept automatic mode detection (amd) fic on-chip memory, access via mc interface generation of receiver status information generation of tuner control signals generation of pulse width modulated vcxo control signal power supply 3.3 v, master clock 24.576 mhz plastic tqfp100 package or ceramic qfp144 package for software development 1.2 channel decoder demodulation and decoding of up to 64 uep/eep sub-channels support of dynamic multiplex reconfiguration (dmr) without mute state digital null-symbol detection (fsynch generation) channel filtering (48 db) optional saw filter equalization digital afc (freq. tolerance < 0.5 hz for mode i) digital agc with a wide gain control range off-chip de-interleaver memory for full 1.8 mbit/s decoding data rate time & frequency synchronization on dsp oak core support of tii decoding and corresponding rdi insertion (set 2) 1.3 audio source decoder supports mpeg1 layer ii streams according to iso/ iec 11172/3 supports mpeg2 layer ii (half sampling rate) streams according to iso/iec 13818 ? 3 supports all bit rates defined in the ets 300 401 standard i 2 s and spdif output interfaces programmable fader programmable drc pad extraction 1.4 data decoder 2 independent packet mode decoder flexible configuration via mc commands data group length limited to ~1 kbyte each output via hsso or v24 dd1 option: fidc decoder support of aic decoding (set 2)
u2739m-b rev. a1, 22-may-01 6 (69) 1.5 interfaces source decoder output interface: i 2 s and spdif data decoder output interface: v24 or hsso channel decoder output interface: rdi and sfco microcontroller interface: i 2 c/l3 rdi: ? extended high capacity mode ? iec 958 format ? rdi control channel (rcc) sfco simple full capacity output: ? window-, serial sub-channel identifier (sbchid)-, data-, error- and clock line ? 3.072 mhz burst mode interface 10-bit adc interface: ? adc sampling clock generation ? adc binary or 2 ? s complement format selection ? support of several intermediate frequencies dsp oak core bootstrap rom interface voltage controlled reference oscillator (vcxo) interface time de-interleaver sram (4 mbit) interface high speed serial output hsso (pad, dd1, dd2, cir) interface, 3-line serial burst mode interface 2 functional block diagram mc interface rdi interface data decoder source decoder channel iq splitting filtering afc agc de- modulation de- interleaving decodeing audio source decoding pa d extraction data decoder 1 (fidc) data decoder 2 (aic (use)) rdi controller fsync generation amd time synchro ? nization frequency synchro ? tii decoding (use) status generation boot unit mc interface adc xo unit dac sram mc vcxo tank rom i2s spdif v24/rs232 rdi_tx sfco sli w_agc pwm df fs_in fsync tuner rdi_rx hsso memory mc nization decoder u2739m-b figure 2. functional block diagram
u2739m-b rev. a1, 22-may-01 7 (69) 3 pin description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 1 1 adc_clk adc sampling clock output 8.192 mhz pdo04t out 2 tin0 test input 0 (pull down) pddz in x 3 tin1 test input 1 (pull down) pddz in x 4 2 adc_data9 adc data input, bit 9 (msb) pdiz in x 5 3 adc_data8 adc data input, bit 8 pdiz in x 6 4 adc_data7 adc data input, bit 7 pdiz in x 7 5 adc_data6 adc data input, bit 6 pdiz in x 8 tin2 test input 2 (pull down) pddz in x 9 dvsse ground pvss1z, pvss2z gnd x 10 6 adc_data5 adc data input, bit 5 pdiz in x 11 7 adc_data4 adc data input, bit 4 pdiz in x 12 8 adc_data3 adc data input, bit 3 pdiz in x 13 9 adc_data2 adc data input, bit 2 pdiz in x 14 tin3 test input 3 (pull down) pddz in x 15 tin4 test input 4 (pull down) pddz in x 16 10 adc_data1 adc data input, bit 1 pdiz in x 17 11 adc_data0 adc data input, bit 0 (lsb) pdiz in x 18 12 dvss1 digital ground pvss1z, pvss2z gnd x 19 13 avss1 analog ground pvss3z gnd x 20 14 xin oscillator input pdx02 osc 21 15 xout oscillator output (pdx02) osc 22 16 avdd1 analog power supply pvdd3z pwr 23 /c_dr c-bus data read enable pro04t out 24 17 /rs low active reset pdiz in x 25 18 pwm pulse width modulated control output pro04t out 26 /c_dw c-bus data write enable pro04t out 27 19 w_agc window agc pro04t out 28 20 sli synchronization lock indicator pro04t out 29 /c_pr c-bus program read enable pro04t out 30 21 hsso_win hsso window signal pro04t out 31 /c_pw c-bus program write enable pro04t out 32 22 hsso _clk hsso clock signal pro04t out 33 /abort low active abort signal (pull up) pduz in x 34 23 hsso _dat hsso data signal pro04t out 35 24 c_add0 c-bus address bit 0 (lsb) pro04t out 36 25 c_add1 c-bus address bit 1 pro04t out 37 26 /boot_re boot read enable pro04t out 38 27 c_add2 c-bus address bit 2 pro04t out 39 28 c_add3 c-bus address bit 3 pro04t out 40 29 c_add4 c-bus address bit 4 pro04t out 41 30 c_add5 c-bus address bit 5 pro04t out 42 31 c_add6 c-bus address bit 6 pro04t out 43 tout0 test output bit 0 pro02t out 44 32 c_add7 c-bus address bit 7 pro04t out
u2739m-b rev. a1, 22-may-01 8 (69) qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 45 33 c_add8 c-bus address bit 8 pro04t out 46 34 c_add9 c-bus address bit 9 pro04t out 47 35 c_add10 c-bus address bit 10 pro04t out 48 36 c_add11 c-bus address bit 11 pro04t out 49 37 c_add12 c-bus address bit 12 pro04t out 50 38 dvdd1 digital power supply pvdd1z, pvdd2z pwr x 51 39 c_add13 c-bus address bit 13 pro04t out 52 c_add14 c-bus address bit 14 pro04t out 53 c_add15 c-bus address bit 15 pro04t out 54 40 c_data0/dbg c-bus data bit 0 (pull down) prd04tz inout x 55 41 c_data1/boot c-bus data bit 1 (pull down) prd04tz inout x 56 c_data8 c-bus data bit 8 (pull down) prd04tz inout x 57 c_data9 c-bus data bit 9 (pull down) prd04tz inout x 58 42 dvss2 digital ground pvss1z, pvss2z gnd x 59 43 c_data2/urst c-bus data bit 2 (pull down) prd04tz inout x 60 44 c_data3/xuse c-bus data bit 3 (pull down) prd04tz inout x 61 c_data10 c-bus data bit 10 (pull down) prd04tz inout x 62 c_data11 c-bus data bit 11 (pull down) prd04tz inout x 63 45 c_data4/pspc c-bus data bit 4 (pull down) prd04tz inout x 64 46 c_data5/rdi_vbit c-bus data bit 5 (pull down) prd04tz inout x 65 c_data12 c-bus data bit 12 (pull down) prd04tz inout x 66 c_data13 c-bus data bit 13 (pull down) prd04tz inout x 67 47 c_data6/xo12 c-bus data bit 6 (pull down) prd04tz inout x 68 48 c_data7/ade c-bus data bit 7 (pull down) prd04tz inout x 69 c_data14 c-bus data bit 14 (pull down) prd04tz inout x 70 c_data15 c-bus data bit 15 (pull down) prd04tz inout x 71 49 test_mode/bypp test mode selection (pull down) pddz in x 72 50 mcm_trigger mcm trigger signal pro04t out 73 51 mc_mode microcontroller mode signal pdiz in x 74 52 mc_clk microcontroller clock signal pdiz in x 75 53 mc_dat microcontroller data signal prb04tz inout x 76 dvdde digital power supply pvdd1z, pvdd2z pwr x 77 54 spdif spdif output pro04t out 78 55 rs232 rs232 output pro04t out 79 56 i2s_clk i2s clock output pro04t out 80 57 i2s_dat i2s data output pro04t out 81 tout1 test output bit 1 pro02t out 82 58 i2s_win i2s win output pro04t out 83 tout2 test output bit 2 pro02t out 84 59 tout3 test output bit 3 pro02t out 85 60 rdi_rx rdi receive data pdiz in x 86 61 rdi_tx rdi transmit data pro04t out 87 62 dvss3 digital ground pvss1z, pvss2z gnd x 88 tout4 test output bit 4 pro02t out
u2739m-b rev. a1, 22-may-01 9 (69) qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 89 tout5 test output bit 5 pro02t out 90 63 sfco_sid sfco sub-channel id pro04t out 91 64 sfco_err sfco errorflag pro04t out 92 65 sfco_dat sfco data pro04t out 93 tout6 test output bit 6 pro02t out 94 66 sfco_clk sfco clock pro04t out 95 67 sfco_win sfco window pro04t out 96 tout7 test output bit 7 pro02t out 97 68 dvdd2 digital power supply pvdd1z, pvdd2z pwr x 98 69 tout8 test output bit 8 pro02t out 99 tout9 test output bit 9 pro02t out 100 70 sram_d7 sram data bit 7 prb04tz inout x 101 71 sram_d6 sram data bit 6 prb04tz inout x 102 tout10 test output bit 10 pro02t out 103 72 sram_d5 sram data bit 5 prb04tz inout x 104 73 sram_d4 sram data bit 4 prb04tz inout x 105 tout11 test output bit 11 pro02t out 106 74 sram_d3 sram data bit 3 prb04tz inout x 107 75 sram_d2 sram data bit 2 prb04tz inout x 108 tout12 test output bit 12 pro02t out 109 76 sram_d1 sram data bit 1 prb04tz inout x 110 77 sram_d0 sram data bit 0 prb04tz inout x 111 tin5 test input 5 (pull down) pddz in x 112 78 sram_wr sram write signal pro04t out 113 79 sram_oe sram output enable pro04t out 114 80 sram_a18 sram address bit 18 pro04t out 115 tin6 test input 6 (pull down) pddz in x 116 81 sram_a17 sram address bit 17 pro04t out 117 82 sram_a16 sram address bit 16 pro04t out 118 tout13 test output bit 13 pro02t out 119 83 sram_a15 sram address bit 15 pro04t out 120 84 sram_a14 sram address bit 14 pro04t out 121 85 dvss4 digital ground pvss1z, pvss2z gnd x 122 tin7 test input 7 (pull down) pddz in x 123 86 sram_a13 sram address bit 13 pro04t out 124 87 sram_a12 sram address bit 12 pro04t out 125 tout14 test output bit 14 pro02t out 126 88 sram_a11 sram address bit 11 pro04t out 127 89 sram_a10 sram address bit 10 pro04t out 128 tout15 test output bit 15 pro02t out 129 90 sram_a9 sram address bit 9 pro04t out 130 91 sram_a8 sram address bit 8 pro04t out
u2739m-b rev. a1, 22-may-01 10 (69) qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 131 tout16 test output bit 16 pro02t out 132 92 sram_a7 sram address bit 7 pro04t out 133 93 sram_a6 sram address bit 6 pro04t out 134 94 dvdd3 digital power supply pvdd1z, pvdd2z pwr 135 tout17 test output bit 17 pro02t out 136 95 sram_a5 sram address bit 5 pro04t out 137 96 sram_a4 sram address bit 4 pro04t out 138 tmux0 test mux in bit 0 (lsb) (pull down) pddz in x 139 97 sram_a3 sram address bit 3 pro04t out 140 98 sram_a2 sram address bit 2 pro04t out 141 tmux1 test mix in bit 1 (pull down) pddz in x 142 99 sram_a1 sram address bit 1 pro04t out 143 100 sram_a0 sram address bit 0 pro04t out 144 tmux2 test mux in bit 2 (pull down) pddz in x 4 strap pins qfp144 qfp100 pin name signal description pad type dir comment 16 10 adc_data1 adc data input, bit 1 pdiz in strap pin ocsel 1 17 11 adc_data0 adc data input, bit 0 pdiz in strap pin ocsel 0 54 40 c_data0/dbg c-bus data bit 0 prd04tz inout strap pin c_data0/dbg 55 41 c_data1/boot c-bus data bit 1 prd04tz inout strap pin c_data1/boot 59 43 c_data2/urst c-bus data bit 2 prd04tz inout strap pin c_data2/urst 60 44 c_data3/xuse c-bus data bit 3 prd04tz inout strap pin c_data3/xuse 63 45 c_data4/pspc c-bus data bit 4 prd04tz inout strap pin c_data4/pspc 64 46 c_data5/ rdi_vbit c-bus data bit 5 prd04tz inout strap pin c_data5/rdi_vbit 0 rdi spec.: validity bit 1 1 iec958 spec.: validity bit 0 67 47 c_data6/xo12 c-bus data bit 6 prd04tz inout strap pin c_data6/xo12 0 external oscillator 24.576 mhz 1 external oscillator 12.288 mhz 68 48 c_data7/ade c-bus data bit 7 adc_data strap pin function enable prd04tz inout strap pin c_data7/ade 0 adc_data strap pin function disabled 1 adc_data strap pin function enabled 71 49 test_mode/bypp test mode selection pddz in strap pin test_mode/bypp 0 pll activated 1 pll bypassed 73 51 mc_mode microcontroller mode signal pdiz in strap pin i2c/l3 0 i2c 1 l3
u2739m-b rev. a1, 22-may-01 11 (69) 5 pin configuration 35 39 38 37 36 34 33 32 31 30 29 28 27 26 50 49 48 47 46 45 44 43 42 41 40 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 51 52 53 54 75 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 qfp100 adc_clk adc_d9 mc_clk mc_mode dvdd2 dvss3 c_add13 dvdd1 adc_d8 adc_d7 adc_d6 adc_d5 adc_d4 adc_d3 adc_d2 adc_d1 adc_d0 c_add0 dvss1 sli dvdd3 sram_a0 w_agc xout xin pwm avss1 avdd1 sram_a1 sram_a2 sram_a3 sram_a4 sram_a5 sram_a6 sram_a7 sram_a8 sram_a9 sram_d0 sram_d1 sram_a10 sram_a11 sram_a12 sram_a13 sram_a14 sram_a15 dvss4 sram_a16 sram_a17 sram_a18 sram_oe sram_wr sram_d2 sram_d3 sram_d4 sram_d5 sram_d6 sram_d7 tout8 sfco_win sfco_clk sfco_dat sfco_err sfco_sid rdi_tx rdi_rx i2s_win i2s_dat i2s_clk spdif rs232 mc_dat test_mode c_add4 /rs mcm_trigger c_data7 c_data6 c_data4 c_data5 c_data3 c_data2 c_add6 c_data1 c_data0 c_add5 c_add3 c_add12 c_add11 c_add10 c_add9 c_add8 c_add7 dvss2 hsso_dat hsso_clk hsso_win c_add2 /boot_re tout3 c_add1 figure 3. production version qfp100
u2739m-b rev. a1, 22-may-01 12 (69) 46 50 49 48 47 45 44 43 42 41 40 39 38 37 61 60 59 58 57 56 55 54 53 52 51 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 tmux2 72 71 70 69 68 67 66 65 64 63 62 98 99 100 101 102 103 104 105 106 107 108 36 35 34 33 32 31 30 29 28 27 26 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 cqfp 144 adc_clk tin0 adc_d9 mc_clk mc_mode dvdd2 dvss3 c_add13 dvdd1 adc_d8 adc_d7 adc_d6 dvsse adc_d5 adc_d4 adc_d3 adc_d2 adc_d1 adc_d0 c_add0 dvss1 sli dvdd3 sram_a0 w_agc xout xin pwm avss1 avdd1 sram_a1 sram_a2 sram_a3 tout17 sram_a4 sram_a5 sram_a6 sram_a7 sram_a8 sram_a9 sram_d0 sram_d1 sram_a10 sram_a11 sram_a12 sram_a13 sram_a14 sram_a15 dvss4 sram_a16 sram_a17 sram_a18 sram_oe sram_wr sram_d2 sram_d3 sram_d4 sram_d5 sram_d6 sram_d7 tout9 tout8 sfco_win sfco_clk sfco_dat sfco_err sfco_sid rdi_tx rdi_rx dvdde i2s_win i2s_dat i2s_clk spdif rs232 mc_dat c_add14 test_mode c_data8 c_add4 c_data9 /rs mcm_trigger c_data15 c_data7 c_data6 c_data13 c_data4 c_data5 c_data12 c_data11 c_data10 c_data3 c_data2 c_add6 c_data1 c_data0 c_add5 c_data14 c_add15 tout0 c_add3 c_add12 c_add11 c_add10 c_add9 c_add8 c_add7 dvss2 hsso_dat hsso_clk /c_pw hsso_win c_add2 /boot_re /abort /c_pr /c_dw /c_dr tin1 tin2 tin3 tin4 tout1 tout2 tout3 tout4 tout5 tout6 tout7 tmux1 tmux0 tout10 tout11 tout12 tout16 tout15 tout14 tin7 tout13 tin6 tin5 c_add1 figure 4. software development version qfp144
u2739m-b rev. a1, 22-may-01 13 (69) 46 50 49 48 47 45 44 43 42 41 40 39 38 37 61 60 59 58 57 56 55 54 53 52 51 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 72 71 70 69 68 67 66 65 64 63 62 98 99 100 101 102 103 104 105 106 107 108 36 35 34 33 32 31 30 29 28 27 26 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 cqfp 144 adc_clk adc_d9 mc_clk mc_mode dvdd2 dvss3 c_add13 dvdd1 adc_d8 adc_d7 adc_d6 adc_d5 adc_d4 adc_d3 adc_d2 adc_d1 adc_d0 c_add0 dvss1 sli dvdd3 sram_a0 w_agc xout xin pwm avss1 avdd1 sram_a1 sram_a2 sram_a3 sram_a4 sram_a5 sram_a6 sram_a7 sram_a8 sram_a9 sram_d0 sram_d1 sram_a10 sram_a11 sram_a12 sram_a13 sram_a14 sram_a15 dvss4 sram_a16 sram_a17 sram_a18 sram_oe sram_wr sram_d2 sram_d3 sram_d4 sram_d5 sram_d6 sram_d7 tout8 sfco_win sfco_clk sfco_dat sfco_err sfco_sid rdi_tx rdi_rx i2s_win i2s_dat i2s_clk spdif rs232 mc_dat test_mode c_add4 /rs mcm_trigger c_data7 c_data6 c_data4 c_data5 c_data3 c_data2 c_add6 c_data1 c_data0 c_add5 c_add3 c_add12 c_add11 c_add10 c_add9 c_add8 c_add7 dvss2 hsso_dat hsso_clk hsso_win c_add2 /boot_re tout3 c_add1 figure 5. version qfp144 used as production version
u2739m-b rev. a1, 22-may-01 14 (69) 6 interface description 6.1 overview the interface description explains the purpose, the utilization and the meaning of every interface and every signal. it is divided into twelve sections, which are related to the different interfaces. an overview of all interfaces is shown in the functional block diagram below. several standard output interfaces like i 2 s or spdif are used to offer a flexible usage of the u2739m-b. mc interface rdi interface data decoder source decoder channel iq splitting filtering afc agc de- modulation de- interleaving decodeing audio source decoding pa d extraction data decoder 1 (fidc) data decoder 2 (aic (use)) rdi controller fsync generation amd time synchro ? nization frequency synchro ? tii decoding (use) status generation boot unit mc interface adc xo unit dac sram mc vcxo tank rom i2s spdif v24/rs232 rdi_tx sfco sli w_agc pwm df fs_in fsync tuner rdi_rx hsso memory mc nization decoder u2739m-b figure 6. functional block diagram 6.2 adc interface 6.2.1 adc interface signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 1 1 adc_clk adc sampling clock output 8.192 mhz pdo04t out 4 2 adc_data9 adc data input, bit 9 (msb) pdiz in x 5 3 adc_data8 adc data input, bit 8 pdiz in x 6 4 adc_data7 adc data input, bit 7 pdiz in x 7 5 adc_data6 adc data input, bit 6 pdiz in x 10 6 adc_data5 adc data input, bit 5 pdiz in x 11 7 adc_data4 adc data input, bit 4 pdiz in x 12 8 adc_data3 adc data input, bit 3 pdiz in x 13 9 adc_data2 adc data input, bit 2 pdiz in x 16 10 adc_data1 adc data input, bit 1 pdiz in x 17 11 adc_data0 adc data input, bit 0 (lsb) pdiz in x
u2739m-b rev. a1, 22-may-01 15 (69) 6.2.2 adc interface description the adc interface as shown in figure 6 consists of the adc data input signal adc_data(9:0) and the adc sampling clock output signal adc_clk. the u2739m-b can be connected to every standard ad with either binary or 2 ? s complement output format. the sampling frequency is 8.192 mhz and a bandwidth of 2 mhz is necessary. the possible if ? s, which are supported in conjunction with the if input signal mode (parameter ifm) are given by the formula. f if = 2.048 mhz + n 4.096 mhz, with n = 0, 1, 2, 3 .... thus possible ifs are 2.048 mhz, 6.144 mhz, ... 38.912 mhz. the parameter ifm is defined by the mc command ? set global configuration ? [atmel wireless & microcontrollers u2739m documentation set ? ? u2739m_mc_command_set_vxxx.pdf ? ]. the analog input bandwidth of the a/d converter must be chosen accordingly. the adc_data input is 10 bit wide. the typical output delay (td3 in figure 7) of the ad converter related to the falling edge of the sampling clock clk8192 should be 20 ns. the generated 8.192 mhz output clock take over the adc_data with his rising edge of adc_clk. the format ? binary offset ? or ? 2 ? s complement ? of the a/d converter can be selected by the parameter adcf. this parameter is also defined by the ? set global configuration ? mc command [atmel wireless & microcontrollers u2739m documentation set ? ? u2739m_mc_command_set_vxxx.pdf ? ]. furthermore, the sampling clock generation is performed by the u2739m-b. the input data appearing at the adc_data port are assumed to be generated by an a/d converter. the effective resolution of this converter should be greater than 9 bit in order to use the full dynamic range implemented in the u2739m-b. the sampling clock required for the external a/d converter is derived inside u2739m-b. it has to be 8.192 mhz. 6.2.3 adc interface timing diagram xin tclk th tl adc_clk td1 adc_d[9:0] ts1 tc8 tc8 h tc8 l td1 figure 7. adc interface timing diagram 6.2.4 adc interface timing parameters parameter symbol min. typ. max. unit xin clock period tclk 40.7 ns xin clock high th 15.0 20.35 25.0 ns xin clock low tl 15.0 20.35 25.0 ns adc_clk clock period tc8 3 40.7 ns adc_clk clock high tc8h 1 40.7 ns adc_clk clock low tc8l 2 40.7 ns setup time adc_d(9:0) ts1 5.0 ns output delay of adc_clk td1 12.0 20.0 28.0 ns
u2739m-b rev. a1, 22-may-01 16 (69) 6.3 tuner interface 6.3.1 tuner interface signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 27 19 w_agc window agc 0 during cofdm symbols 1 during the null symbol pro04t out 28 20 sli synchronization lock indicator 0 receiver synchronization not locked 1 receiver synchronization locked pro04t out 6.3.2 tuner interface description in order to implement a flexible agc concept of a dab receiver the signals w_agc and sli can be used to control the tuner ic u2731b. the influence of w_agc and sli to the rf agc voltage generation block is described in the u2731b preliminary datasheet. the wagc signal must be controlled by the mc by using the set wagc configuration mc command. the wagc signal does not follow the moving fft window. the rising and falling edge can be adjusted by the mc. the mc can use the differential dt, which correspond to the fft window shift, from the read synchronization status command to adjust the wagc rising and falling edge. 6.4 mc interface 6.4.1 mc interface signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 72 50 mcm_trigger mcm trigger signal pro04t out 73 51 mc_mode microcontroller mode signal 0 i2c bus protocol 1 l3 bus protocol pdiz in x 74 52 mc_clk microcontroller clock signal pdiz in x 75 53 mc_dat microcontroller data signal prb04tz inout x 6.4.2 mc interface description the mc interface is used for data transmission between the u2739m-b (slave) and an external microcontroller (master). it can be configured for l3- or i2c protocol depending on the status of the mc_mode line during reset (/rs = low): mc_mode = high l3 bus selected mc_mode = low i2c bus selected the mcm_trigger line indicates the status of the internal interface controller. the external mcu is able to communicate with the u2739m-b during low phases of mcm_trigger only ! further the mcm trigger signal indicates the synchro- nization status. if the mcm trigger has period of 8 ms, then the u2739m-b is not locked. in the synchronized ( ? locked ? ) state the mcm trigger period correspond to the cif frame, which is provided every 24 ms. the complete fic is processed at the beginning of the transmission frame.
u2739m-b rev. a1, 22-may-01 17 (69) 6.4.3 l3 bus interface timing diagram 0 mc_dat mc_mode ts2 mc_clk 1 6 7 ts1 th1 th2 0 mc_mode ts2 mc_clk 1 6 7 tlc thc ts th1 th2 1 address mode 2 data mode 0 1 6 7 mc_dat (mcu u2739m) mc_dat (u2739m mcu) mc_mode ts2 mc_clk tl th2 td3 3 halt mode tlc thc mc_dat (u2739m mcu) td1 high z td2 figure 8. mc l3 bus interface timing diagram
u2739m-b rev. a1, 22-may-01 18 (69) 6.4.4 l3 bus timing parameter parameter symbol min. typ. max. unit mc_clk low phase tlc 61 ns mc_clk high phase thc 61 ns mc_dat input setup time ts1 61 ns mc_dat input hold time th1 61 ns mc_mode hold time th2 61 ns mc_mode setup time ts2 61 ns mc_clk(h/l) / mc_dat delay td1 20 100 ns mc_mode(l/h) / mc_dat (output driven) td2 110 130 ns mc_clk(l/h) / mc_dat(high z) td3 120 160 ns 6.4.5 i2c bus interface timing diagram s p r s t s t s p mc_data mc_clk tsd thd tlc thc 7 0 7 0 ths tss tbf ths tss figure 9. mc i2c bus timing diagram 6.4.6 i2c bus timing parameter parameter symbol min. typ. max. unit bus free time between stop and start condition tbf 400 ns hold time (repeated) start condition ths 200 ns setup time data tsd 120 ns hold time data thd 320 ns low period clock tlc 300 ns high period clock thc 200 ns setup time: repeated start condition, stop condition tss 240 ns
u2739m-b rev. a1, 22-may-01 19 (69) 6.5 c-bus / boot bus interface 6.5.1 c-bus signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 23 /c_dr c-bus data read enable pro04t out 26 /c_dw c-bus data write enable pro04t out 29 /c_pr c-bus program read enable pro04t out 31 /c_pw c-bus program write enable pro04t out 35 24 c_add0 c-bus address bit 0 (lsb) pro04t out 36 25 c_add1 c-bus address bit 1 pro04t out 37 26 /boot_re boot read enable pro04t out 38 27 c_add2 c-bus address bit 2 pro04t out 39 28 c_add3 c-bus address bit 3 pro04t out 40 29 c_add4 c-bus address bit 4 pro04t out 41 30 c_add5 c-bus address bit 5 pro04t out 42 31 c_add6 c-bus address bit 6 pro04t out 44 32 c_add7 c-bus address bit 7 pro04t out 45 33 c_add8 c-bus address bit 8 pro04t out 46 34 c_add9 c-bus address bit 9 pro04t out 47 35 c_add10 c-bus address bit 10 pro04t out 48 36 c_add11 c-bus address bit 11 pro04t out 49 37 c_add12 c-bus address bit 12 pro04t out 51 39 c_add13 c-bus address bit 13 pro04t out 52 c_add14 c-bus address bit 14 pro04t out 53 c_add15 c-bus address bit 15 pro04t out 54 40 c_data0/dbg c-bus data bit 0 (pull down) prd04tz inout x 55 41 c_data1/boot c-bus data bit 1 (pull down) prd04tz inout x 56 c_data8 c-bus data bit 8 (pull down) prd04tz inout x 57 c_data9 c-bus data bit 9 (pull down) prd04tz inout x 59 43 c_data2/urst c-bus data bit 2 (pull down) prd04tz inout x 60 44 c_data3/xuse c-bus data bit 3 (pull down) prd04tz inout x 61 c_data10 c-bus data bit 10 (pull down) prd04tz inout x 62 c_data11 c-bus data bit 11 (pull down) prd04tz inout x 63 45 c_data4/pspc c-bus data bit 4 (pull down) prd04tz inout x 64 46 c_data5/rdi_vbit c-bus data bit 5 (pull down) prd04tz inout x 65 c_data12 c-bus data bit 12 (pull down) prd04tz inout x 66 c_data13 c-bus data bit 13 (pull down) prd04tz inout x 67 47 c_data6/xo12 c-bus data bit 6 (pull down) prd04tz inout x 68 48 c_data7/bypp c-bus data bit 7 (pull down) prd04tz inout x 69 c_data14 c-bus data bit 14 (pull down) prd04tz inout x 70 c_data15 c ? -bus data bit 15 (pull down) prd04tz inout x
u2739m-b rev. a1, 22-may-01 20 (69) 6.5.2 c-bus / boot bus interface description the c-bus is a multiplexed program as well as data bus system to communicate with external components. the complete bus system is available only in the qfp144 package version and needed for debugging the internal oak dsp core. the boot bus covers a subset of the c-bus signals. the user is able to download his own so-called ? user software extensions ? using this bus system to replace or extend the atmel wireless & microcontrollers firmware. the boot bus is a standard rom interface (address/ data buses, read enable line) and the read access is always with 16 wait states (referring the oak internal 49.152 mhz clock) to support slow devices. the boot bus is available in both package versions. the timing diagram refers to the boot bus signals only. 6.5.3 boot bus timing diagram valid address c_data (7..0) c_add (13..0) /boot_re tacc valid data valid address valid data figure 10. c-bus interface timing diagram 6.5.4 boot bus timing parameter parameter symbol min. typ. max. unit boot rom access time tacc 120 ns
u2739m-b rev. a1, 22-may-01 21 (69) 6.6 sram interface 6.6.1 sram interface signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 100 70 sram_d7 sram data bit 7 prb04tz inout x 101 71 sram_d6 sram data bit 6 prb04tz inout x 103 72 sram_d5 sram data bit 5 prb04tz inout x 104 73 sram_d4 sram data bit 4 prb04tz inout x 106 74 sram_d3 sram data bit 3 prb04tz inout x 107 75 sram_d2 sram data bit 2 prb04tz inout x 109 76 sram_d1 sram data bit 1 prb04tz inout x 110 77 sram_d0 sram data bit 0 prb04tz inout x 112 78 sram_wr sram write signal pro04t out 113 79 sram_oe sram output enable pro04t out 114 80 sram_a18 sram address bit 18 pro04t out 116 81 sram_a17 sram address bit 17 pro04t out 117 82 sram_a16 sram address bit 16 pro04t out 119 83 sram_a15 sram address bit 15 pro04t out 120 84 sram_a14 sram address bit 14 pro04t out 123 86 sram_a13 sram address bit 13 pro04t out 124 87 sram_a12 sram address bit 12 pro04t out 126 88 sram_a11 sram address bit 11 pro04t out 127 89 sram_a10 sram address bit 10 pro04t out 129 90 sram_a9 sram address bit 9 pro04t out 130 91 sram_a8 sram address bit 8 pro04t out 132 92 sram_a7 sram address bit 7 pro04t out 133 93 sram_a6 sram address bit 6 pro04t out 136 95 sram_a5 sram address bit 5 pro04t out 137 96 sram_a4 sram address bit 4 pro04t out 139 97 sram_a3 sram address bit 3 pro04t out 140 98 sram_a2 sram address bit 2 pro04t out 142 99 sram_a1 sram address bit 1 pro04t out 143 100 sram_a0 sram address bit 0 pro04t out 6.6.2 sram interface descriptions for time de-interleaving and further task an external static random access memory of 4 mb is necessary. the organization of the sram is 512 k 8 bit. due to the high data rates a fast sram with a access time of 18 ns or below is necessary.
u2739m-b rev. a1, 22-may-01 22 (69) 6.6.3 sram interface timing diagram valid address sram_wr sram_a(18:0) read cycle sram_oe data valid sram_d(7:0) high ? z td1 valid address sram_wr sram_a(18:0) write cycle sram_oe data valid sram_d(7:0) tavav tdvwh twleh xin tavav td2 td3 tsdata xin td1 td2 td3 tddata figure 11. sram interface timing diagram
u2739m-b rev. a1, 22-may-01 23 (69) 6.6.4 sram interface timing parameter parameter symbol min. typ. max. unit read/ write cycle time tavav 40.7 ns output delay sram_a(18:0) td1 15.0 25.0 35.0 ns output delay sram_wr td2 12.0 20.0 28.0 ns output delay sram_oe td3 16.0 24.0 32.0 ns setup time sram_d(7:0) tsdata 2.0 ns write pulse with twleh 33.0 40.7 48.0 ns output delay sram_d(7:0) tddata 15.0 23.0 31.0 ns data valid to end of write tdvwh 33.0 40.7 48.0 ns 6.7 vcxo interface 6.7.1 vcxo interface signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 19 13 avss1 analog ground pvss3z gnd x 20 14 xin oscillator input pdx02 osc 21 15 xout oscillator output (pdx02) osc 22 16 avdd1 analog power supply pvdd3z pwr 25 18 pwm pulse width modulated control output pro04t out 6.7.2 vcxo interface description pll xin pa d xout pa d pwm pa d vcxo 24.576 mhz 49.192 mhz f pwm = f clk2457 / 2 n n = 11 ? > f pwm = 12 khz u2739m-b figure 12. vcxo application circuit the u2739m-b master clock should be derived from a voltage-controlled reference oscillator. the pulse width modu- lated output signal pwm of the u2739m-b can be used to control the vcxo frequency of 24.576 mhz.
u2739m-b rev. a1, 22-may-01 24 (69) 6.8 audio interfaces 6.8.1 i2s interface signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 79 56 i2s_clk i2s clock line pro04t out 80 57 i2s_dat i2s data line pro04t out 82 58 i2s_win i2s window line pro04t out 6.8.2 i2s interface description the i2s interface is a standard continuous audio interface consisting of bit clock (_clk), word select (_win) and data (_dat) lines. the word select line indicates the transmitted channel: low for left, high for right. please be aware of the 1 cycle delay of the data word msb corresponding to the i2s_win edge ! as in the dab system the i2s_win clock is fixed as 48 khz (mpeg1) or 24 khz (mpeg2) the bit clock depends on the data word length. the standard word length is 16 bit, hence the bit clock is fixed at 1.536 mhz resp. 768 khz. 6.8.3 i2s interface timing diagram 0 15 14 13 12 i2s_dat i2s_win i2s_clk 3 2 1 0 15 14 12 3 2 1 0 13 td1 tl th tclk td2 15 14 12 13 left sample right sample figure 13. i2s interface timing diagram 6.8.4 i2s interface timing parameter parameter symbol min. typ. max. unit i2s clock period tclk 16.28 us i2s clock high th 14.28 us i2s clock low tl 14.28 us i2s_win output delay td1 ? 5.0 0.0 5.0 ns i2s_dat output delay td2 ? 5.0 0.0 5.0 ns 6.8.5 sp-dif interface signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 77 54 spdif spdif output pro04t out
u2739m-b rev. a1, 22-may-01 25 (69) 6.8.6 sp-dif interface description the sp-dif format is frame based, which means one frame represents one audio sampling period. every frame comprises 2 subframes a 32 bit referring to the left and right sample. the data is transmitted in bi-phase coded format. the frame synchronization pattern are based on biphase violations and indicate whether a left or right subframe follows. the last 4 bi-phase coded bits of each subframe represent the v (validity flag), u (user channel data), c (channel status data) and p (parity) information as described in the sp-dif specification. complete frames (left and right sample according to 64 2 bit due to bi-phase coding) are transmitted at the audio sampling rate (48 resp. 24 khz). 6.8.7 sp-dif interface timing parameter the sp-dif interface was designed according the digital audio interface iec958 specification [cei/iso 958 digital audio interface standard]. 6.8.8 sp-dif interface timing diagram spdif s3 s2 s1 a0 a1 a2 a14 a15 audio data bits (bi ? phase coded) v u c p flag bits (bi ? phase coded) 8 zero ? s (bi ? phase coded) frame sync. pattern sp ? dif subframe (left or right audio sample) figure 14. sp-dif interface timing diagram 6.9 rdi interface 6.9.1 rdi interface signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 64 46 c_data5/rdi_vbit c ? bus data bit 5 (pull down) prd04tz inout x 85 60 rdi_rx rdi receive data pdiz in x 86 61 rdi_tx rdi transmit data pro04t out 6.9.2 rdi interface description the rdi interface is designed according to the ? digital audio broadcasting system: specification of the receiver data interface (rdi) ? [digital audio broadcasting system: specification of the receiver data interface (rdi), issue 1.4]. the rdi frames are embedded into the iec 958 interface. the rdi output data is provided in the extended format of the high capacity mode. further the rdi control channel (rcc) can be implemented according to the preliminary specifi- cation [digital audio broadcasting system: preliminary specification of the rdi control channel], [proposal of dab command set for receiver (dcsr)]. 6.9.3 rdi interface timing diagram rdi_tx/rx tl th 2 * th 2 * tl 3 * th 3 * tl figure 15. rdi interface timing diagram
u2739m-b rev. a1, 22-may-01 26 (69) 6.9.4 rdi interface timing parameter the rdi interface is realized according to the digital audio interface iec958 specification [cei/iso 958 digital audio interface standard]. parameter symbol min. typ. max. unit data high period th 160 ns data low period tl 160 ns 6.10 sfco interface 6.10.1 sfco interface signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 90 63 sfco_sid sfco sub-channel id pro04t out 91 64 sfco_err sfco error flag pro04t out 92 65 sfco_dat sfco data pro04t out 94 66 sfco_clk sfco clock pro04t out 95 67 sfco_win sfco window pro04t out 6.10.2 sfco interface description the simple full capacity output interface (sfco) is a 3.072 mhz burst mode interface. it consists of a window, data, errorflag and clock line. furthermore, a serial sub- channel identifier information is provided. the interface carries fast information channel (fic) and main service information (msc) at the output of the cofdm channel decoder. the window line can be used to distinguish between fic and msc data. via the mc interface the provided sub-channel can be selected. only these selected sub-channels are processed by the channel decoder.
u2739m-b rev. a1, 22-may-01 27 (69) 6.10.3 sfco interface timing diagram fib1 1 sfco_win 0 sfco_clk sfco_data sfco_subchid sfco_errfl fic fib1 12 fibn 12 fibn crc 20*clk 12*clk 16 *clk 48*clk 32*clk fib1 crc fib2 1 80*clk msc 1 sfco_win id sfco_clk sfco_data sfco_subchid sfco_errfl msc msc n ? 1 22*clk 32*clk msc n 1*clk 6*clk 10 *clk 32*clk 16*clk 3 * 32 * clk 2 * 32 * clk 32 * clk figure 16. sfco interface timing diagram
u2739m-b rev. a1, 22-may-01 28 (69) 6.10.4 detailed sfco interface timing diagram 0 sfco_win 1 n thc tlc ts th 0 sfco_clk sfco_data sfco_subchid sfco_errfl fic 0 sfco_win 1 6 thc tlc ts th 6 5 0 sfco_clk sfco_data sfco_subchid sfco_errfl msc th n td1 td2 thw figure 17. detailed sfco interface timing diagram
u2739m-b rev. a1, 22-may-01 29 (69) 6.10.5 sfco interface timing parameter parameter symbol min. typ. max. unit clock high period thc 160 ns clock low period tlc 160 ns data setup time ts 160 ns data hold time th 160 ns window msc high period thw 10.56 us delay data valid td1 10.24 us delay window fic low td2 10.24 us 6.11 rs232 interface 6.11.1 rs232 interface signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 78 55 rs232 rs232 output pro04t out 6.11.2 rs232 interface description the rs232 interface is an standard serial output used for transferring data directly to a pc com port. one of 3 applications can be given out: data decoder 1 data decoder 2 programme associated data (pad) each rs232 burst consists of a header word followed by n data words (as indicated in the header): rs232-id (burst identifier) length (number of transmitted data words n without header word) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dd1 0 0 0 1 number of dd1 words dd2 0 0 1 0 number of dd2 words pa d 0 0 1 1 number of pad words the rs232 output can be configured using the ? set hsso/ rs232 configuration ? mc command [atmel wireless & microcontrollers u2739m documentation set ? ? u2739m_mc_command_set_vxxx.pdf ? ]. using this command the user can select the application to be given out and the baud rate. please notice the byte order: first the high byte is trans- mitted followed by the low byte (lsb first both). 6.11.3 rs232 interface timing diagram 8 9 10 14 15 0 1 2 6 7 8 9 10 11 12 rs232 figure 18. rs232 interface timing diagram 6.11.4 rs232 interface timing parameter the rs232 timing is related to the defined baud rate of the interface.
u2739m-b rev. a1, 22-may-01 30 (69) 6.12 hsso interface 6.12.1 hsso interface signal description qfp144 qfp100 pin name signal description pad type dir. 5 v tol. 30 21 hsso_win hsso window signal pro04t out 32 22 hsso _clk hsso clock signal pro04t out 34 23 hsso _dat hsso data signal pro04t out 6.12.2 hsso interface description the high speed serial output (hsso) is a standard 3-line output interface implemented to give out data bursts in a multiplexed way. up to 4 applications can be given out simultaneously: channel impulse response (cir) data decoder 1 data decoder 2 programme associated data (pad) the hsso can be configured using the ? set hsso / rs232 configuration ? mc command (see section 8). each hsso burst consists of a header word followed by n data words (as indicated in the header). hsso-id (burst identifier) length (number of transmitted data words n without header word) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cir 0 0 0 0 number of cir words dd1 0 0 0 1 number of dd1 words dd2 0 0 1 0 number of dd2 words pa d 0 0 1 1 number of pad words 6.12.3 hsso interface timing diagram 15 14 13 1 0 hsso_dat hsso_win hsso_clk 15 14 13 1 0 0 15 14 1 0 15 td1 td2 header data 0 data n ? 1 tl th tclk figure 19. hsso interface timing diagram 6.12.4 hsso interface timing parameters parameter symbol min. typ. max. unit hsso clock period tclk 4.07 us hsso clock high th 2.035 us hsso clock low tl 2.035 us hsso_win output delay td1 ? 5.0 0.0 5.0 ns hsso_dat output delay td2 ? 5.0 0.0 5.0 ns
u2739m-b rev. a1, 22-may-01 31 (69) 7 electrical characteristics 7.1 absolute maximum ratings parameter symbol min. max. unit supply voltage vdd ? 0.5 vdd + 0.5 v input / output voltage vin/vout ? 0.5 vdd + 0.5 v storage temperature tstg ? 65 125 c 7.2 operating range parameter symbol min. typ. max. unit supply voltage vdd 3.0 3.3 3.6 v input / output voltage vin/vout 0 vdd v ambient temperature tamb ? 40 +85 c power dissipation pstat 20 mw power dissipation pdyn 860 mw 7.3 dc characteristics parameter test conditions pad type symbol min. typ. max. unit input high voltage vih 2.0 v input low voltage vil 0.8 v threshold vt 1.4 v output high voltage ioh= ? 2 ma voh pxx02x 2.4 vdd v ioh= ? 4 ma pxx04x 2.4 vdd v output low voltage iol= 2 ma vol pxx02x 0.2 0.4 v iol= 4 ma pxx04x 0.2 0.4 v
u2739m-b rev. a1, 22-may-01 32 (69) 8 mc command set 8.1 ?set system? commands 8.1.1 set dab system mode command settings overview: set system mode set fsli control loops command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 $00 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 smode nsm 0 0 0 0 0 $xx command parameters: parameter meaning description smode(1..0) new dab system mode 00: dab system mode 4 01: dab system mode 1 10: dab system mode 2 11: dab system mode 3 nsm new system mode valid 0: smode not valid 1: smode indicates new system mode
u2739m-b rev. a1, 22-may-01 33 (69) 8.1.2 set asd command settings overview: set asd on/off set asd mute state set asd sub ? channel id set asd dynamic range control on/off set asd dynamic range control fixed value set asd scf ? crc on/off set asd dual channel configuration set asd fader value command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 $10 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 asde mute idv dccv fadv drcon drcfix scfon $xx fadd sbchid $xx dcc drcfv $xx
u2739m-b rev. a1, 22-may-01 34 (69) command parameters: parameter meaning description asde asd enable 0: asd disabled 1: asd enabled mute asd mute state 0: asd output active 1: asd output muted idv asd sbchid valid 0: last set asd sbchid remains valid 1: following asd sbchid valid dccv dcc setting valid 0: last set dcc remains valid 1: following dcc valid fadv fader setting valid 0: last set fad remains valid 1: following fad valid drcon drc on/off switch 0: drc off 1: drc on drcfix drc additional fixed gain value valid 0: drc additional fixed gain + 6 db (default) 1: drc additional fixed gain according to drcfv scfon scf ? crc on/off switch 0: scf ? crc off 1: scf ? crc on fad fader value 00: fade in / fade out over 0 frames each 01: fade in / fade out over 30 frames each 10: fade in / fade out over 60 frames each 11: fade in / fade out over 90 frames each sbchid(5..0) sub ? channel identifier n: asd sub ? channel id dcc(1..0) dual channel configuration 00/10: left channel on both asd output channels 01: right channel on both asd output channels 11: both channels on asd output drcfv(5..0) drc additional fixed gain value 000000: fixed gain 0 db 000001: fixed gain + 0.25 db ... (continuous steps of +0.25 db) 111111: fixed gain + 15.75 db
u2739m-b rev. a1, 22-may-01 35 (69) 8.1.3 set dd1 dd configuration for transmission in packet mode command settings overview: set dd1 on/off set dd1 sub ? channel id set dd1 packet address command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 $11 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 dd1e fidc pa1v id1v 0 pa(9/8) $xx pa(7..0) $xx 0 sbchid $xx command parameters: parameter meaning description dd1e dd1 enable 0: dd1 disabled 1: dd1 enabled fidc fidc decoding switch 0: dd1 decodes msc 1: dd1 decodes fidc 1) pa1v pa valid 0: last set dd1 pa remains valid 1: following dd1 pa valid id1v dd1 sbchid valid 0: last set dd1 sbchid remains valid 1: following dd1 sbchid valid pa(9..0) packet address n: dd1 packet address sbchid(5..0) sub ? channel identifier n: dd1 sub ? channel id 1) in this case pa and sbchid parameters are ignored (regardless of whether pa1v/id1v have been set or not)
u2739m-b rev. a1, 22-may-01 36 (69) 8.1.4 set dd2 dd configuration for transmission in packet mode command settings overview: set dd2 on/off set dd2 aic on/off set dd2 sub ? channel id set dd2 packet address command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 0 $12 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 dd2e aic pa2v id2v 0 pa(9/8) $0x pa(7..0) $xx 0 sbchid $xx command parameters: parameter meaning description dd2e dd2 enable 0: dd2 disabled 1: dd2 enabled aic aic decoding switch 0: dd2 decodes msc 1: dd2 decodes aic 2) pa2v dd2 pa valid 0: last set dd2 pa remains valid 1: following dd2 pa valid id2v dd2 sbchid valid 0: last set dd2 sbchid remains valid 1: following dd2 sbchid valid pa(9..0) packet address n: dd2 packet address sbchid(5..0) sub ? channel identifier n: dd2 sub ? channel id 1) in this case pa and sbchid parameters are ignored (regardless of whether pa2v/id2v have been set or not) and the default values for aic decoding (pa = 1023, sbchid = 63) are used instead
u2739m-b rev. a1, 22-may-01 37 (69) 8.1.5 set cif counter and occurrence change command settings overview: set channel decoder cif counter set channel decoder occurrence change command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 1 $13 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 cf af cifch(4..0) $xx cifcl(7..0) $xx oc(7..0) $xx command parameters: parameter meaning description cf(1..0) change flags 00: no change 01: sub ? channel organization change 10: service organization change 11: sub ? channel & service organization change af alarm flag 0: alarm messages not accessible 1: alarm messages accessible cifch(4..0) cif counter (higher part) n: cif counter higher part (modulo 20) cifcl(7..0) cif counter (lower part) n: cif counter lower part (modulo 250) oc(7..0) occurrence change n: value for cifcl, from which the new configuration is valid
u2739m-b rev. a1, 22-may-01 38 (69) 8.1.6 set current sbchid long form command settings overview: set current sub ? channel parameters (long form) command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 0 1 0 1 0 0 $14 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 on scefc sbchid $xx scu(9..2) $xx scu(1..0) ep eppar cu(9..8) $xx cu(7..0) $xx
u2739m-b rev. a1, 22-may-01 39 (69) command parameters: parameter meaning description on sub ? channel on/off switch 0: switch sub ? channel off 1: switch sub ? channel on scefc single sub ? channel for efc 0: single sub ? channel for efc remains unchanged 1: set sbchid as single sub ? channel for efc sbchid(5..0) sub ? channel identifier n: sub ? channel id scu(9..0) start cu for sbchid n: start cu address (0..863) ep error protection 0: uep 1: eep eppar(2..0) error protection parameters if ep = 0 (uep): 000: protection level p 1 001: protection level p 2 010: protection level p 3 011: protection level p 4 100: protection level p 5 if ep = 1 (eep): 0xx: eep long form option 0 (protection level xx ? a) 00: protection level 1 ? a (code rate 2/8) 01: protection level 2 ? a (code rate 3/8) 10: protection level 3 ? a (code rate 4/8) 11: protection level 4 ? a (code rate 6/8) 1xx: eep long form option 1 (protection level xx ? b) 00: protection level 1 ? b (code rate 4/9) 01: protection level 2 ? b (code rate 4/7) 10: protection level 3 ? b (code rate 4/6) 11: protection level 4 ? b (code rate 4/5) cu(9..0) sub ? channel size (number of cu ? s) n: sub ? channel size in cu ? s (4..864)
u2739m-b rev. a1, 22-may-01 40 (69) 8.1.7 set next sbchid long form command settings overview: set next sub ? channel parameters command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 0 1 0 1 0 1 $15 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 on scefc sbchid $xx scu(9..2) $xx scu(1..0) ep eppar cu(9..8) $xx cu(7..0) $xx
u2739m-b rev. a1, 22-may-01 41 (69) command parameters: parameter meaning description on sub ? channel on/off switch 0: switch sub ? channel off 1: switch sub ? channel on scefc single sub ? channel for efc 0: single sub ? channel for efc remains unchanged 1: set sbchid as single sub ? channel for efc sbchid(5..0) sub ? channel identifier n: sub ? channel id scu(9..0) start cu for sbchid n: start cu address (0..863) ep error protection 0: uep 1: eep eppar(2..0) error protection parameters if ep = 0 (uep): 000: protection level p 1 001: protection level p 2 010: protection level p 3 011: protection level p 4 100: protection level p 5 if ep = 1 (eep): 0xx: eep long form option 0 (protection level xx ? a) 00: protection level 1 ? a (code rate 2/8) 01: protection level 2 ? a (code rate 3/8) 10: protection level 3 ? a (code rate 4/8) 11: protection level 4 ? a (code rate 6/8) 1xx: eep long form option 1 (protection level xx ? b) 00: protection level 1 ? b (code rate 4/9) 01: protection level 2 ? b (code rate 4/7) 10: protection level 3 ? b (code rate 4/6) 11: protection level 4 ? b (code rate 4/5) cu(9..0) sub ? channel size (number of cu ? s) n: sub ? channel size in cu ? s (4..864)
u2739m-b rev. a1, 22-may-01 42 (69) 8.1.8 set current sbchid short form command settings overview: set current sub ? channel parameters (short form) command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 0 1 0 1 1 0 $16 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 on scefc sbchid $xx command parameters: parameter meaning description on sub ? channel on/off switch 0: switch sub ? channel off 1: switch sub ? channel on scefc single sub ? channel for efc 0: single sub ? channel for efc remains unchanged 1: set sbchid as single sub ? channel for efc sbchid(5..0) sub ? channel identifier n: sub ? channel id
u2739m-b rev. a1, 22-may-01 43 (69) 8.2 ? set configuration ? commands 8.2.1 set global configuration command settings overview: set channel decoder agc values set channel decoder global parameters command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6g data mode 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 0 $00 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 agcv 0 db3 dsc psc(10..8) $xx psc(7..0) $xx cdpv ifm fsys saw adcf 0 $xx command parameters: parameter meaning description d efaults agcv agc values valid 0: following dsc/psc values ignored 1: following dsc/psc values valid dsc(1..0) input data scale n: scale value psc(10..0) programmable (i)fft scale n: scale value cdpv channel decoder parameters valid 0: following global parameters ignored 1: following global parameters valid ifm if input signal mode 0: common if representation 1: reverse if representation 1 fsys frame synchronization sensitivity level 00: very high 01: high 10: low 11: very low 01 saw saw filter equalization switch 0: equalization off 1: equalization on 1 adcf adc format 0: binary adc input format 1: 2 ? s complement adc input format 0
u2739m-b rev. a1, 22-may-01 44 (69) 8.2.2 set ts configuration command settings overview: set ts post processing parameters command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 1 0 0 0 0 1 $21 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 pa rv cov pks ispcnt $xx tmin $xx cirth $xx nsth $xx gfch $xx gfcl $xx
u2739m-b rev. a1, 22-may-01 45 (69) command parameters: parameter meaning description d e- faults pa rv cir post processing parameters valid (pks / avg / cirth / nsth / tmin) 0: parameters not valid 1: following parameters valid cov cir post processing filter coefficients valid 0: coefficients not valid 1: following coefficients valid pks number of peaks required for ? cir correct ? indication 2 n : required peaks 0 ispcnt cir post processing average n: cir output average over n+1 values 0 tmin(7..0) cir minimum dt output n: minimum dt output after cir post processing (* 488 ns) 0 cirth(7..0) cir threshold n.n: ? threshold value for cir peak detection (format: 4.4 bit) ? will be multiplied by ? (standard deviation) 3.0 nsth(7..0) noise threshold n: ? noise threshold value (8 bit unsigned) ? will be multiplied by 32 0 b0(15..0) iir filter coefficients coefficients for 1 st order iir filter used for cir post processing (q15 format required) 0.5 0.5 0
u2739m-b rev. a1, 22-may-01 46 (69) 8.2.3 set fs configuration command settings overview: set fs post processing parameters command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 0 $22 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 ga $xx tha $xx gb $xx thb $xx gc $xx f2ft $xx command parameters: parameter meaning description d efaults ga(7..0) area a gradient n: fractional part 0.03125 tha(7..0) area a threshold n: fractional part 0.03125 gb(7..0) area b gradient n: fractional part 0.125 thb(7..0) area b threshold n: fractional part 0.25 gc(7..0) area c gradient n: fractional part 0.5 f2ft(7..0) max. frame ? to ? frame tolerance n: maximum frequency shift in carriers (format: 3.5 bit) 1.0
u2739m-b rev. a1, 22-may-01 47 (69) 8.2.4 set xo configuration command settings overview: set xo control parameters command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 1 0 0 0 1 1 $23 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 xo_rough line $xx xo_fine line $xx xoavg 0 $xx command parameters: parameter meaning description d efaults xo_b0(15..0) xo_b1(15..0) xo_b2(15..0) xo_a1(15..0) xo_a2(15..0) iir filter coefficients coefficients for 2 nd order iir filter used for xo control 0.25 0.5 0.25 0 0 xoavg(4..0) xo control average n: xo control average over n+1 values 0
u2739m-b rev. a1, 22-may-01 48 (69) 8.2.5 set hsso / rs232 configuration command settings overview: set hsso parameters set rs232 parameters command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 1 0 0 1 0 0 $00 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 hclk hcirl hpad hdd2 hdd1 hcir $xx rsbaud 0 rssel $xx command parameters: parameter meaning description hclk(1..0) hsso bit clock 00: 0.768 mhz 10: 3.072 mhz 01: 1.536 mhz 11: 6.144 mhz hcirl(1..0) hsso cir output length 00: n values (dab system mode dependent) 01: n/2 1x: n/4 hpad hsso pad output switch 0: no pad output via hsso 1: pad output hdd2 hsso dd2 output switch 0: no dd2 output via hsso 1: dd2 output hdd1 hsso dd1 output switch 0: no dd1 output via hsso 1: dd1 output hcir hsso cir output switch 0: no cir output via hsso 1: cir output rsbaud(1..0) rs232 baud rate 00: 19200 baud 10: 57600 baud 01: 38400 baud 11: 115200 baud rssel(1..0) rs232 output selection 00: no output 01: dd1 10: dd2 11: pad
u2739m-b rev. a1, 22-may-01 49 (69) command parameters: parameter meaning description ufs use fs module 0: internal set2 xtfpr module used 1: external use module used ufsp use fs post processing module 0: internal set2 module used 1: external use module used utsp use ts post processing module 0: internal set2 module used 1: external use module used uxoc use xo control module 0: internal set2 module used 1: external use module used udd1 use dd1 module 0: internal set2 module used 1: external use module used udd2 use dd2 module 0: internal set2 module used 1: external use module used upad use pad extraction module 0: internal set2 module used 1: external use module used utii use tii module 0: internal set2 module used 1: external use module used uamd ... unmi reserved
u2739m-b rev. a1, 22-may-01 50 (69) 8.2.6 set wagc configuration command settings overview: set wagc rising edge / falling edge parameters command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 0 $26 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 wrise(3..0) ws 0 wv $xx wrise(11..4) $xx wfall(1..0) wrise(17..12) $xx wfall(9..2) $xx wfall(17..10) $xx command parameters: parameter meaning description wv wagc values valid 0: use default wagc values 1: use following wagc values wrise(17..0) wagc rising edge time marker n: value for wagc rising edge wfall(17..0) wagc falling edge time marker n: value for wagc falling edge
u2739m-b rev. a1, 22-may-01 51 (69) 8.2.7 set rcc slot configuration command settings overview: set rcc slot data command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 1 0 0 1 1 1 $27 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 rcc(7..0) $xx rcc(15..8) $xx rcc(23..16) $xx rcc(31..24) $xx rcc(39..32) $xx rcc(47..40) $xx rcc(55..48) $xx rcc(63..56) $xx command parameters: parameter meaning description rcc(63..0) rcc slot data
u2739m-b rev. a1, 22-may-01 52 (69) 8.2.8 set rfu command settings overview: set rfu parameters command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 0 dab u2739m-b write command $6e data mode 7 6 5 4 3 2 1 0 0 0 1 1 0 0 0 0 $30 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 0 dab u2739m-b write command $6c data mode 7 6 5 4 3 2 1 0 (reserved) $xx (reserved) $xx (reserved) $xx (reserved) $xx rfu4 $xx rfu5 $xx rfu6 $xx ... $xx ... $xx rfu42 $xx rfu43 $xx rfu44 $xx command parameters: parameter meaning description (reserved) reserved for internal use (atmel wireless & microcontrollers will deliver default values, if necessary) rfu4..44 reserved for future use
u2739m-b rev. a1, 22-may-01 53 (69) 8.3 ? read status ? commands 8.3.1 read global status command overview: get dab system mode get oak core operating mode get synchronization status get agc information command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 0 $40 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 dabmode oakmode mv fsli sli wdsp $xx 0 cirs ccir cafc $xx 0 psli idsl p(8) $xx p(7..0) $xx
u2739m-b rev. a1, 22-may-01 54 (69) command parameters: parameter meaning description dabmode(1..0) dab system mode 00: dab system mode 4 01: dab system mode 1 10: dab system mode 2 11: dab system mode 3 oakmode(1..0) oak operating mode 00: normal stand ? alone 01: use boot mode 10: xuse boot mode 11: host boot mode mv mode_valid line status fsli fsli line status sli sli line status cirs cir status 0: no cir detected 1: cir correct ccir(1..0) coded cir status 00: |average| ? n/64 01: n/64 < |average| ? n/8 10: |average| > n/4 11: rfu. cafc(1..0) coded afc status 00: |df frame | ? ta 01: ta < |df frame | ? tb 10: tb < |df frame |< 16 khz 11: |df frame | ? 16 khz psli(3..0) precise signal level infor- mation 0000: very weak signal ... 1111: v ery strong signal idsl(1..0) input data signal level 00: weak input signal 01: typical input signal 10: strong input signal 11: rfu. p(8..0) calculated in ? band power wdsp watchdog dsp toggels every 24 ms from 0 to 1
u2739m-b rev. a1, 22-may-01 55 (69) 8.3.2 read synchronization status command overview: get ts control value get fs control value command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 0 1 0 0 0 0 0 1 $41 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 dt(9..2) $xx dt(1..0) 0 df(19..16) $xx df(15..8) $xx df(7..0) $xx command parameters: parameter meaning description dt(9..0) detected time deviation n: cycle count (signed, @2.048 mhz) 1) df(19..0) detected channel frequency deviation n: deviation in carriers (signed, q11 format) 1) signed values refers to virtual zero at t guard /2
u2739m-b rev. a1, 22-may-01 56 (69) 8.3.3 read cir status command overview: get cir post processing results 1) command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 0 1 0 0 0 0 1 0 $42 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 p_first(15..8) $xx p_first(7..0) $xx p_agv(15..8) $xx p_agv(7..0) $xx p_last(15..8) $xx p_last(7..0) $xx command parameters: parameter meaning description p_first(15..0) index of 1 st cir peak above cir threshold n: cycle count (signed, @2.048 mhz) 2) p_avg(15..0) index of cir average value n: cycle count (signed, @2.048 mhz) p_last(15..0) index of last cir peak above cir threshold n: cycle count (signed, @2.048 mhz) 1) if time synchronization has lost all values are set to $8000 ! 2) signed values refers to zero at t guard /2
u2739m-b rev. a1, 22-may-01 57 (69) 8.4 ? read data ? commands 8.4.1 read asd header data command overview: get mpeg audio header command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 0 1 0 1 0 0 0 0 $50 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 mpg_hw1(15..8) $xx mpg_hw1(7..0) $xx mpg_hw2(15..8) $xx mpg_hw2(7..0) $xx command parameters: parameter meaning description mpg_hw1(15..0) 1 st mpeg header word sync. word ($fffx) expected mpg_hw2(15..0) 2 nd mpeg header word mpeg stream signature
u2739m-b rev. a1, 22-may-01 58 (69) 8.4.2 read x ? pad command overview: get mpeg ancillary data (x ? pad) command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 0 1 0 1 0 xpnum $5x address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 x ? pad0 $xx ... x ? pad31 $xx command parameters: parameter meaning description xpnum x ? pad block number n (n from 1..5) the maximum x ? pad capacity supported by the u2739m-b is 64kbit/s. the access is splitted into 6 blocks (numbered 1..5) of 32 bytes. the blocks are time aligned, that means block 1 is the first block in an mpeg frame after audio samples. x ? padm x ? pad byte m byte 0 is the first byte of block n, byte 31 the last one. it is followed by the first one of block n+1. read rfu use mc command ? rfu ? to read block 6
u2739m-b rev. a1, 22-may-01 59 (69) 8.4.3 read f ? pad command overview: get mpeg ancillary data (f ? pad) command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 0 1 0 1 1 0 0 0 $58 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 f ? pad0 $xx f ? pad1 $xx command parameters: parameter meaning description f ? pad0 f ? pad byte 0 f ? pad1 f ? pad byte 1
u2739m-b rev. a1, 22-may-01 60 (69) 8.4.4 read aic data command overview: get aic data command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 0 1 1 0 aicnum $6x address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 aic0 $xx ... aic31 $xx command parameters: parameter meaning description aicnum aic block number n the maximum aic capacity is 512 bytes. the access is splitted into 16 blocks (numbered 0..15) of 32 bytes. the blocks are time aligned, that means block 0 is the first filled block. aicm aic byte m byte 0 is the first byte of block n, byte 31 the last one. it is followed by the first one of block n+1.
u2739m-b rev. a1, 22-may-01 61 (69) 8.4.5 read tii data command overview: get tii data command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 0 1 1 1 0 0 tiinum $7x address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 tii0 $xx ... tii31 $xx command parameters: parameter meaning description tiinum tii block number n the maximum tii capacity is 128 bytes. the access is splitted into 4 blocks (numbered 0..3) of 32 bytes. the blocks are time aligned, that means block 0 is the first filled block. tiim tii byte m byte 0 is the first byte of block n, byte 31 the last one. it is followed by the first one of block n+1.
u2739m-b rev. a1, 22-may-01 62 (69) 8.4.6 read efc data command overview: get efc data command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 1 0 0 0 0 0 efcsel $8x address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 efc(7..0) $xx efc(15..8) $xx command parameters: parameter meaning description efcsel efc selection 00: efc of fic 01: efc of all msc applications efc(15..0) efc value for chosen application n: efc value summarized over... ... 12 fib ? s (dab mode 1) ... 3 fib ? s (dab mode 2) ... 4 fib ? s (dab mode 3) ... 6 fib ? s (dab mode 4)
u2739m-b rev. a1, 22-may-01 63 (69) 8.4.7 read fic data command overview: get fib bytes command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 1 0 0 1 fibnum $9x address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 fib0 $xx ... fib31 $xx command parameters: parameter meaning description fibnum fib number n possible fib numbers dab mode dependent: 0..11 (dab mode 1) 0..2 (dab mode 2) 0..3 (dab mode 3) 0..5 (dab mode 4) fibm fib byte m each fib consists of 32 bytes. the order of the fib bytes and bits corresponds to the serial fic processing. that means: (1) byte order: the first 8 output bits after fic processing represent fib byte 0 of fib num- ber 0, the next ones fib byte 1 of fib number 0 and so on. (2) bit order: the fib bytes are given out msb first. the first outgoing bit represents bit 7 of the corresponding byte, the next one bit 6 and so on. the fib bits are num- bered from bit 0 (msb of fib0) up to bit 255 (lsb of fib31). note: the last 2 bytes of an fib represent the result of the u2739m internal crc check. that means, if these bytes are $00 both, the internal crc check was successful and the fib data bytes are correct.
u2739m-b rev. a1, 22-may-01 64 (69) 8.4.8 read rcc slot command overview: get rcc slot data command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 0 $a0 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 rcc(7..0) $xx rcc(15..8) $xx rcc(23..16) $xx rcc(31..24) $xx rcc(39..32) $xx rcc(47..40) $xx rcc(55..48) $xx rcc(3..56) $xx command parameters: parameter meaning description rcc(63..0) rcc slot data
u2739m-b rev. a1, 22-may-01 65 (69) 8.4.9 read slot pointer command overview: get rcc rx/tx slot pointer command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 1 0 1 0 0 0 0 1 $a1 address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 txptr rxptr $xx command parameters: parameter meaning description rxptr(3..0) rcc rx slot pointer txptr(3..0) rcc tx slot pointer
u2739m-b rev. a1, 22-may-01 66 (69) 8.4.10 read rfu command overview: get rfu data command sequence: address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 1 1 dab u2739m-b write command $6f data mode 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 0 $9x address mode 7 6 5 4 3 2 1 0 0 1 1 0 1 1 0 1 dab u2739m-b write command $6d data mode 7 6 5 4 3 2 1 0 rfu0 $xx ... rfu43 $xx command parameters: parameter meaning description xpad0..31 xpad block 6 see: read xpad command rfu0..11 reserved for future use
u2739m-b rev. a1, 22-may-01 67 (69) 9 package information
u2739m-b rev. a1, 22-may-01 68 (69)
u2739m-b rev. a1, 22-may-01 69 (69) ozone depleting substances policy statement it is the policy of atmel germany gmbh to 1. meet all present and future national and international statutory requirements. 2. regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. it is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (odss). the montreal protocol ( 1987) and its london amendments ( 1990) intend to severely restrict the use of odss and forbid their use within the next ten years. various national and international initiatives are pressing for an earlier ban on these substances. atmel germany gmbh has been able to use its policy of continuous improvements to eliminate the use of odss listed in the following documents. 1. annex a, b and list of transitional substances of the montreal protocol and the london amendments respectively 2. class i and ii ozone depleting substances in the clean air act amendments of 1990 by the environmental protection agency (epa) in the usa 3. council decision 88/540/eec and 91/690/eec annex a, b and c (transitional substances) respectively. atmel germany gmbh can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. we reserve the right to make changes to improve technical design and may do so without further notice . parameters can vary in different applications. all operating parameters must be validated for each customer application by the customer. should the buyer use atmel wireless & microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify atmel wireless & microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. data sheets can also be retrieved from the internet: http://www.atmel ? wm.com atmel germany gmbh, p.o.b. 3535, d-74025 heilbronn, germany telephone: 49 (0)7131 67 2594, fax number: 49 (0)7131 67 2423

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