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1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view in 1 in 2 d 1 d 2 s 1 s 2 v? v+ gnd nc s 4 s 3 d 4 d 3 in 4 in 3 top view s 1 s 2 v? v+ nc nc gnd nc s 4 s 3 lcc nc in 3 d 3 d 4 in 4 nc in 2 d 2 d 1 in 1 key 910111213 4 5 6 7 8 1 2 319 20 14 15 16 17 18 dual-in-line, soic and tssop dg201hs vishay siliconix document number: 70038 s-52433?rev. f, 06-sep-99 www.vishay.com 1 high-speed quad spst cmos analog switch

fast switching?t on : 38 ns low on-resistance: 25 low leakage: 100 pa low charge injection ttl/cmos logic compatible single supply compatibility high current rating: ?30 ma faster throughput higher accuracy reduced pedestal error upgrades existing designs simple interfacing replaces hi201hs, adg201hs space savings (tssop) data acquisition hi-rel systems sample-and-hold circuits communication systems automatic test equipment integrator reset circuits choppers gain switching avionics

the dg201hs is an improved monolithic device containing four independent analog switches. it is designed to provide high speed, low error switching of analog signals. combining low on-resistance (25 ) with high speed (t on : 38 ns), the dg201hs is ideally suited for high speed data acquisition requirements. to achieve high voltage ratings and superior switching performance, the dg201hs is built on a proprietary high-voltage silicon-gate process. an epitaxial layer prevents latchup. each switch conducts equally well in both directions when on, and blocks input voltages to the supply values, when off.

logic switch 0 on 1 off logic ?0? 0.8 v logic ?1? 2.4 v
dg201hs vishay siliconix www.vishay.com 2 document number: 70038 s-52433 ? rev. f, 06-sep-99

temp range package part number 16-pin plastic dip dg201hsdj ? 40 to 85 c 16-pin narrow soic dg201hsdy 16-pin tssop dg201hsdq 16-pin cerdip dg201hsak/883 ? 55 to 125 c lcc-20 dg201hsaz/883

v+ to v ? 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd to v ? 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a v s , v d (v ? ) ? 4 v to (v+) +4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . or 30 ma, whichever occurs first continuous current (any terminal) 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current, s or d (pulsed 1 ms, 10% duty cycle) 100 ma . . . . . . . . . . . . . . . . . . storage temperature (a suffix) ? 65 to 150 c . . . . . . . . . . . . . . . . . . . . (d suffix) ? 65 to 125 c . . . . . . . . . . . . . . . . . . . . power dissipation (package)b 16-pin plastic dip c 470 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin cerdip d 900 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-pin narrow body soic and tssop e 600 mw . . . . . . . . . . . . . . . . . . . . . . . lcc-20 d 900 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x , or in x exceeding v+ or v ? will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6 mw/ c above 75 c. d. derate 12 mw/ c above 75 c. e. derate 7.6 mw/ c above 75 c.

figure 1. gnd v ? d x s x v+ 5 v reg v+ in x v ? level shift/ drive
dg201hs vishay siliconix document number: 70038 s-52433 ? rev. f, 06-sep-99 www.vishay.com 3

test conditions unless specified a suffix ? 55 to 125 c d suffix ? 40 to 85 c parameter symbol v+ = 15 v, v ? = ? 15 v v in = 3 v, 0.8 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full v ? v+ v ? v+ v drain-source on-resistance r ds(on) i s = ? 10 ma, v d = 8.5 v v+ = 13.5 v, v ? = ? 13.5 v room full 25 50 75 50 75 r ds(on) match room 3 % i s(off) v+ = 16.5 v, v ? = ? 16.5 v room full 0.1 ? 1 ? 60 1 60 ? 1 ? 20 1 20 switch off leakage current i d(off) v d = 15.5 v v s = 15.5 v room full 0.1 ? 1 ? 60 1 60 ? 1 ? 20 1 20 na channel on leakage current i d(on) v+ = 16.5 v, v ? = ? 16.5 v v s = v d = 15.5 v room full 0.1 ? 1 ? 60 1 60 ? 1 ? 20 1 20 digital control input, high voltage v inh full 2.4 2.4 input, low voltage v inl full 0.8 0.8 v input capacitance c in full 5 pf input current i inl or i inh v in under test = 0.8 v, 3 v full ? 1 1 ? 1 1 a dynamic characteristics turn-on time t on , c l = 35 pf v s = 10 v, v inh = 3 v see figure 2 room full 30 50 70 50 70 ns turn-off time t off2 room 150 output settling time to 0.1% t s room 180 charge injection q c l = 1 nf, v s = 0 v v gen = 0 v, r gen = 0 room ? 5 pc off isloation oirr r l = 1 k , c l = 10 pf f = 100 khz room 85 crosstalk (channel-to-channel) x talk any other channel switches r l = 1 k , c l = 10 pf f = 100 khz room 100 db source off capacitance c s(off) room 8 drain off capacitance c d(off) room 8 channel on capacitance c d(on) v s , v d = 0 v, f = 1 mhz room 30 pf drain-to-source capacitance c ds(off) room 0.5 power supplies positive supply current i+ room full 4.5 10 10 negative supply current i ? v+ = 15 v, v ? = ? 15 v v in = 0 or 5 v room full 3.5 ? 6 ? 6 ma power consumption c p c full 240 240 mw
dg201hs vishay siliconix www.vishay.com 4 document number: 70038 s-52433 ? rev. f, 06-sep-99

test conditions unless specified a suffix ? 55 to 125 c d suffix ? 40 to 85 c parameter symbol v+ = 10.8 v to 16.5 v v ? = gnd = 0 v v in = 3 v, 0.8 v f temp b typ c min d max d min d max d unit analog switch analog signal range e v analog full 0 v+ 0 v+ v drain-source on-resistance r ds(on) i s = ? 10 ma, v d = 8.5 v v+ = 10.8 v room full 65 90 120 90 120 i s(off) v+ = 16.5 v, v s = 0.5 v, 10 v room full 0.1 ? 1 ? 60 1 60 ? 1 ? 20 1 20 switch off leakage current i d(off) v+ = 16.5 v, v s = 0.5 v, 10 v v d = 10 v, 0.5 v room full 0.1 ? 1 ? 60 1 60 ? 1 ? 20 1 20 na channel on leakage current i d(on) + i s(on) v+ = 16.5 v, v d = 0.5 v, 10 v room full 0.1 ? 1 ? 60 1 60 ? 1 ? 20 1 20 digital control input, high voltage v inh full 2.4 2.4 input, low voltage v inl full 0.8 0.8 v input capacitance c in full 5 pf input current i inl or i inh v+ = 16.5 v v in under test = 0.8 v, 3 v full ? 1 1 ? 1 1 a dynamic characteristics turn-on time t on room full 50 70 50 70 turn-off time t off1 r l = 1 k , c l = 35 pf, v s = 2 v v= 10.8 v, see figure 2 room full 50 70 50 70 ns turn-off time t off2 room 150 output settling time to 0.1% t s room 180 charge injection q c l = 1 nf, v s = 0 v v gen = 0 v, r gen = 0 room 10 pc off isloation oirr r l = 1 k , c l = 10 pf f = 100 khz room 85 crosstalk (channel-to-channel) x talk any other channel switches r l = 1 k , c l = 10 pf f = 100 khz room 100 db source off capacitance c s(off) room 10 drain off capacitance c d(off) f = 1 mhz room 10 pf channel on capacitance c d(on) v analog = 0 v room 30 power supplies positive supply current i+ full 10 10 ma power consumption c p c v+ = 15 v, v in = 0 or 5 v full 150 150 mw notes: a. refer to process option flowchart. b. room = 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. e. guaranteed by design, not subject to production test. f. v in = input voltage to perform proper function.
dg201hs vishay siliconix document number: 70038 s-52433 ? rev. f, 06-sep-99 www.vishay.com 5

? 20 ? 16 ? 12 ? 8 ? 4 0 4 8 12 16 20 0 10 20 30 40 50 60 70 5 v r ds(on) vs. v d and power supply voltages v d ? drain voltage (v) 10 v 15 v 20 v 0 10 20 30 40 50 ? 15 ? 10 ? 50 51015 r ds(on) vs. v d and temperature v d ? drain voltage (v) 125 c 85 c ? 55 c 0 c v+ = 15 v v ? = ? 15 v r ds(on) ? drain-source on-resistance ( ) r ds(on) ? drain-source on-resistance ( ) 0246810121416 0 20 40 60 80 100 120 140 160 180 r ds(on) vs. v d and single power supply voltages v d ? drain voltage (v) v+ = 5 v 7 v 10 v 12 v 15 v ? 60 ? 40 ? 20 0 20 40 60 80 100 120 140 10 pa 100 pa 1 na 10 na i d(on) leakage leakage currents vs. temperature temperature ( c) i s(off), i d(off) 0 0.5 1 1.5 2 2.5 v th () v input switching threshold vs. supply voltage positive supplies (v) 4 6 8 101214161820 30 35 40 45 50 55 4 6 8 10 12 14 16 18 20 switching time vs. power supply voltage supply voltage (v) switching time (ns) r ds(on) ? drain-source on-resistance ( ) t on t off 25 c
dg201hs vishay siliconix www.vishay.com 6 document number: 70038 s-52433 ? rev. f, 06-sep-99

? 55 ? 25 0 25 50 75 100 125 20 25 30 35 40 45 temperature ( c) switching times vs. temperature switching time (ns) t on t off v+ = 15 v v ? = ? 15 v 4 6 8 10 12 14 16 18 20 30 35 40 45 50 55 60 65 v+ ? positive supply (v) switching times vs. single supply voltage (ns) t on ,t off t on t off ? 55 ? 25 0 25 50 75 100 125 20 25 30 35 40 45 50 temperature ( c) switching times vs. temperature switching time (ns) v+ = 10.8 v v ? = 0 v ? 15 ? 10 ? 50 51015 ? 40 ? 30 ? 20 ? 10 0 10 20 v s ? source voltage (v) v+ = 15 v, v ? = 0 v v+ = 15 v v ? = ? 15 v chargie injection (pc) charge injection vs. source voltage 10 k 100 k 1 m 10 m 40 50 60 70 80 90 100 110 120 f ? frequency (hz) off isolation vs. frequency oirr r l = 100 v+ = 15 v v ? = ? 15 v r l = 1 k t on t off
dg201hs vishay siliconix document number: 70038 s-52433 ? rev. f, 06-sep-99 www.vishay.com 7

10% 90% figure 2. switching time 10 v r l r l + r ds(on) v o = v s c l (includes fixture and stray capacitance) v ? v+ in s c l 35 pf d 3 v r l 1 k v o ? 15 v gnd +15 v 50% 0 v 3 v t off1 t on v o v s t r <20 ns t f <20 ns logic input switch input switch output t off2 figure 3. charge injection c l 1 nf 3 v v ? ? 15 v v o gnd v+ r g s d in +15 v s in r l d r g = 50 v s v o 0v, 3 v off isolation = 20 log v s v o v+ ? 15 v gnd v ? c c +15 v figure 4. off isolation 50 d 1 v o r g = 50 s 1 +15 v ? 15 v d 2 gnd v+ v ? nc c c s 2 r l in 1 x talk isolation = 20 log v s v o 0v, 3 v 0v, 3 v v s in 2 c = rf bypass figure 5. crosstalk v o v o in x sw on off q = v o x c l
dg201hs vishay siliconix www.vishay.com 8 document number: 70038 s-52433 ? rev. f, 06-sep-99

a high-speed, low-glitch analog switch such as vishay siliconix ? s dg201hs improves the accuracy and shortens the acquisition and settling times of a sample-and-hold circuit. v analog input buffer si581 sample /hold ch (polystyrene) jfet buffer output to a/d converter dg201hs

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