PJLC1V5, 1v5d single and dual low capacitance esd / transient protector for 1.5 v systems specification features applications this patented single and dual zener like esd/transient protector has been designed to protect sensitive equipment against esd and prevent latch-up events, offering a minimum insertion loss in high speed data lines in communications ports used in portable consumer, computing and networking applications operating at 1.5v and below. maximum capacitance of 10pf @ 0vdc, 1 mhz industry standard sot23 package maximum leakage current of 2a @ 1.5v breakdown voltage of 1.9v @ 1ma iec61000-4-2 compliance 15kv air, 8kv contact discharge high speed data transmission lines microcontroller and microprocessor i/o interfaces portable consumer electronics instrumentation equipment lan/wan equipment 1 2 3 1 2 3 1 2 3 (gnd) sot23 1 2 3 (gnd) sot23 maximum ratings rating symbol value units electrical characteristics tj = 25c parameter symbol min unit s conditions typical max reverse stand-off voltage reverse breakdown voltage reverse leakage current clamping voltage (8/20s) clamping voltage (8/20s) off state junction capacitance v wrm v br i r c v v c cj br i = r v = i = pp i = pp 0 vdc bias f = 1mhz between i/o pins and pin 3 1.5 v 1.75 1.8 v a 2.0 4v 7v 5a pf 610 100a 1.5v 1 a 3 a 50 >25 -55 to +125 -55 to +150 260 w kv c c c peak pulse power (8/20s waveform) esd voltage (hbm) operating temperature range storage temperature range p pp v esd t j t stg 7/21/2006 page 1 www.panjit.com maximum peak pulse current pp i i = br 1.9 2.2 v 1ma lead soldering temperature (max 10 s) t l 8/20 s waveform
www.panjit.com PJLC1V5, 1v5d 7/21/2006 page 2 typical characteristics leakage current 0.001 0.01 0.1 1 10 100 0.8 1 1.2 1.4 1.6 1.8 2 voltage, volts leakage current, a ta = 25c pulse waveform 0 10 20 30 40 50 60 70 80 90 100 110 0 5 10 15 20 25 30 time, sec percent of ipp 50% of ipp @ 20s rise time 10-90% - 8s voltage vs current characterisitc 0.01 0.1 1 10 100 1 1.5 2 2.5 3 voltage, volts current, ma tj = 25c
www.panjit.com PJLC1V5, 1v5d 7/21/2006 page 3 12 3 (gnd) data line 1 data line 2 1.2-1.5v 0 PJLC1V5d 12 3 (gnd) data line 1 data line 2 1.2-1.5v 0 PJLC1V5d typical application information esd protection for two data lines 12 3 (gnd) data line 1 data line 2 pjlc1v 5d 12 PJLC1V5d data line 3 data line 4 0 12 3 (gnd) data line 1 data line 2 pjlc1v 5d 12 PJLC1V5d data line 3 data line 4 12 3 (gnd) data line 1 data line 2 pjlc1v 5d 12 PJLC1V5d data line 3 data line 4 0 esd protection for four data lines 1.2-1.5v1.2-1.5v1.2-1.5v1.2-1.5v
PJLC1V5, 1v5d package and pad layout dimensions 7/21/2006 www.panjit.com page 4 ? copyright panjit international, inc 2011 the information presented in this document is believed to be accurate and reliable. the specifications and information herein a re subject to change without notice. pan jit makes no warranty, representation or guarantee regarding the suitability of its produ cts for any particular purpose. pan jit products are not authorized for use in life support devices or systems. pan jit does not convey any license under its patent rights or rights of others. device marking code PJLC1V5 t1l PJLC1V5d t2l
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