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products and specifications discussed herein are subject to change by micron without notice. 32, 64, 128mb x 64 sdram dimm sd5c4_8_16x72ag.fm - rev. c 6/04 en 1 ?2004 micron technology, inc. all rights reserved. 32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm synchronous dram module mt5lsdt472a ? 32mb mt5lsdt872a(i) ? 64mb mt5lsdt1672a(i) ? 128mb for the latest data sheet, please refer to the micron ? web site: www.micron.com/products/modules features ? 168-pin, dual in-line memory module (dimm) pc100- and pc133-compliant unbuffered 32mb (4 meg x 72), 64mb (8 meg x 72), 128mb (16 meg x 72) supports ecc error detection and correction single +3.3v power supply fully synchronous; all signals registered on positive edge of system clock internal pipelined operation; column address can be changed every clock cycle internal sdram banks for hiding row access/precharge programmable burst length s: 1, 2, 4, 8, or full page auto precharge, including concurrent auto precharge, and auto refresh modes self refresh mode: 64ms, 4,096-cycle refresh for 32mb and 64mb; 64ms, 8,192-cycle refresh for 128mb lvttl-compatible inputs and outputs serial presence-detect (spd) gold edge contacts figure 1: 168-pin dimm (mo-161) note: 1. consult micron for product availability. 2. industrial temperature option available in -133 speed only. table 1: timing parameters cl = cas (read) latency module marking clock frequency access time setup time hold time cl = 2 cl = 3 -13e 133 mhz 5.4ns ? 1.5 0.8 -133 133 mhz ? 5.4ns 1.5 0.8 -10e 100 mhz 9ns 7.5ns 2ns 1ns options marking package 168-pin dimm (standard) g 168-pin dimm (lead-free) y 1 operating temperature range commercial (0c to +65c) none industrial (-40c to +85c) i 2 frequency / cas latency 7.5ns (133 mhz) / cl = 2 -13e 7.5ns (133 mhz) / cl = 3 -133 8ns (100 mhz) / cl = 2 -10e standard 1.00in. (25.40mm) table 2: address table 32mb 64mb 128mb refresh count 4k 4k 8k device banks 4 (ba0, ba1) 4 (ba0, ba1) 4 (ba0, ba1) device configuration 64mb (4 meg x 16) 128mb (8 meg x 16) 256mb (16 meg x 16) row addressing 4k (a0-a11) 4k (a0-a11) 8k (a0-a12) column addressing 256 (a0-a7) 512 (a0-a8) 512 (a0-a8) module ranks 1 (s0#, s2#) 1 (s0#, s2#) 1 (s0#, s2#)
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 2 ?2004 micron technology, inc. all rights reserved. table 3: part numbers part number module density configuration system bus speed mt5lsdt472ag-13e_ 32mb 4 meg x 72 133 mhz mt5lsdt472ay-13e_ 32mb 4 meg x 72 133 mhz mt5lsdt472ag-133_ 32mb 4 meg x 72 133 mhz mt5lsdt472ay-133_ 32mb 4 meg x 72 133 mhz mt5lsdt472ag-10e_ 32mb 4 meg x 72 100 mhz mt5lsdt472ay-10e_ 32mb 4 meg x 72 100 mhz mt5lsdt872ag-13e_ 64mb 8 meg x 72 133 mhz mt5lsdt872ay-13e_ 64mb 8 meg x 72 133 mhz mt5lsdt872a(i)g-133_ 64mb 8meg x 72 133 mhz mt5lsdt872a(i)y-133_ 64mb 8meg x 72 133 mhz mt5lsdt872ag-10e_ 64mb 8 meg x 72 100 mhz mt5lsdt872ay-10e_ 64mb 8 meg x 72 100 mhz mt5lsdt1672ag-13e_ 128mb 16 meg x 72 133 mhz mt5lsdt1672ay-13e_ 128mb 16 meg x 72 133 mhz mt5lsdt1672a (i) g-133_ 128mb 16 meg x 72 133 mhz mt5lsdt1672a (i) y-133_ 128mb 16 meg x 72 133 mhz mt5lsdt1672ag-10e_ 128mb 16 meg x 72 100 mhz mt5lsdt1672ay-10e_ 128mb 16 meg x 72 100 mhz note: the designators for component and pcb revision are the last two characters of each part number. consult factory for current revision codes. example: mt5lsdt1672ag-133b1.
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 3 ?2004 micron technology, inc. all rights reserved. note: 1. pin 126 is nc for 32mb and 64mb modules, or a12 for the 128mb module. figure 2: pin locations (168-pin dimm) table 4: pin assignment (168-pin dimm front) pin symbol pin symbol pin symbol pin symbol 1v ss 22 cb1 43 v ss 64 v ss 2dq0 23 v ss 44 nc 65 dq21 3dq1 24 nc 45 s2# 66 dq22 4dq2 25 nc 46 dqm2 67 dq23 5dq3 26 v dd 47 dqm3 68 v ss 6v dd 27 we# 48 nc 69 dq24 7dq4 28 dqm0 49 v dd 70 dq25 8dq5 29 dqm1 50 nc 71 dq26 9dq6 30 s0# 51 nc 72 dq27 10 dq7 31 nc 52 cb2 73 v dd 11 dq8 32 v ss 53 cb3 74 dq28 12 v ss 33 a0 54 v ss 75 dq29 13 dq9 34 a2 55 dq16 76 dq30 14 dq10 35 a4 56 dq17 77 dq31 15 dq11 36 a6 57 dq18 78 v ss 16 dq12 37 a8 58 dq19 79 ck2 17 dq13 38 a10 59 v dd 80 nc 18 v dd 39 ba1 60 dq20 81 wp 19 dq14 40 v dd 61 nc 82 sda 20 dq15 41 v dd 62 nc 83 scl 21 cb0 42 cko 63 nc 84 v dd table 5: pin assignment (168-pin dimm back) pin symbol pin symbol pin symbol pin symbol 85 v ss 106 cb5 127 v ss 148 v ss 86 dq32 107 v ss 128 cke0 149 dq53 87 dq33 108 nc 129 dnu 150 dq54 88 dq34 109 nc 130 dqm6 151 dq55 89 dq35 110 v dd 131 dqm7 152 v ss 90 v dd 111 cas# 132 dnu 153 dq56 91 dq36 112 dqm4 133 v dd 154 dq57 92 dq37 113 dqm5 134 nc 155 dq58 93 dq38 114 dnu 135 nc 156 dq59 94 dq39 115 ras# 136 cb6 157 v dd 95 dq40 116 v ss 137 cb7 158 dq60 96 v ss 117 a1 138 v ss 159 dq61 97 dq41 118 a3 139 dq48 160 dq62 98 dq42 119 a5 140 dq49 161 dq63 99 dq43 120 a7 141 dq50 162 v ss 100 dq44 121 a9 142 dq51 163 dnu 101 dq45 122 ba0 143 v dd 164 nc 102 v dd 123 a11 144 dq52 165 sa0 103 dq46 124 v dd 145 nc 166 sa1 104 dq47 125 dnu 146 nc 167 sa2 105 cb4 126 nc/ a12 1 147 nc 168 v dd u1 u2 u4 u5 back view pin 1 pin 84 pin 85 pin 168 u3 no components on this side of module front view u6
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 4 ?2004 micron technology, inc. all rights reserved. table 6: pin descriptions pins may not correlate with symbols; refer to pin assignment tables on page 3 for more information pin numbers symbol type description 27, 111, 115 ras#, cas#, we#, input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 42, 79 ck0, ck2 input clock: ck is driven by the system clock. all sdram input signals are sampled on the posit ive edge of ck. ck also increments the internal burst counter and controls the output registers. 128 cke0 input clock enable: cke activates (high) and deactivates (low) the ck signal. deactivating the clock provides precharge power-down and self refresh operation (all device banks idle) or clock suspend operatio n (burst access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including ck, are disabled during power-down and self refresh modes, providing low standby power. 30, 45 s0#, s2# input chip select: s# enables (registered low) and disables (registered high) the command decoder. all commands are masked when s# is registered high. s# is considered part of the command code. 28, 29, 46, 47, 112, 113, 130, 131 dqmb0?dqmb7 input input/output mask: dqmb is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (two- clock latency) when dqmb is sampled high during a read cycle. 39, 122 ba0, ba1 input bank address: ba0 and ba1 define to which device bank the active, read, write, or precharge command is being applied. 33?38, 117?121, 123, 126 (128mb) a0?a11 (32mb/64mb) a0?a12 (128mb) input address inputs: provide the row address for active commands, and the column address and auto prcharge bit (a10) for read/write commands, to select one location out of the memory arrary in the respective device bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low ? device bank selected by ba0, ba1) or all device banks (a10 high). the address inputs also provide the op-code during a mode register set command. 83 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 165-167 sa0?sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 82 sda input/output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module. 2?5, 7?11, 13?17, 19?20, 55?58, 60, 65?67, 69?72, 74?77, 86?89, 91?95, 97? 101, 103?104, 139?142, 144, 149?151, 153?156, 158?161 dq0?dq63 input/output data i/os: data bus.
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 5 ?2004 micron technology, inc. all rights reserved. 21, 22, 52, 53, 105, 106, 136, 137 cb0?cb7 input/output ecc check bits. 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 v dd supply power supply: +3.3v 0.3v. 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 v ss supply ground. 114, 125, 129, 132, 163 dnu ? do not use: these pins are not used on these modules, but are assigned pins on other modules in this product family. 24, 25, 31, 44, 48, 50, 51, 61, 62,63, 80, 81, 108, 109, 126 (32mb/64mb), 134, 135, 145-147, 164 nc ? not connected: these pins are not connected on these modules. table 6: pin descriptions pins may not correlate with symbols; refer to pin assignment tables on page 3 for more information pin numbers symbol type description
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 6 ?2004 micron technology, inc. all rights reserved. figure 3: functional block diagram dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqmh u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqmb4 s2# ras# cas# cke0 we# ras#: sdrams cas#: sdrams cke: sdrams we#: sdrams a0-a11: sdrams a0-a12: sdrams ba0-1: sdrams a0-a11(32mb/64mb) a0-a12(128mb) ba0-1 dqml cs# dqmb0 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqmh u2 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dqmb5 dqmb1 dqml cs# dqmb1 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqmh u4 dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqmb6 dq dq dq dq dq dq dq dq dqml cs# dqmb2 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqmh u5 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dqm7 dq dq dq dq dq dq dq dq dqml cs# dqmbb3 s0# dqmh u3 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dqml cs# dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq dq v dd v ss sdrams sdrams 10pf ck1, ck3 ck0 6.6pf a0 sa0 spd u6 sda a1 sa1 a2 sa2 wp scl u1 u2 u3 ck2 13.6pf u4 u5 standard modules use the following sdram devices: mt48lc4m16a2tg (32mb); mt48lc8m16a2tg (64mb); mt48lc16m16a2tg ( 128mb) lead-free modules use the following sdram devices: mt48lc4m16a2p (32mb); mt48lc8m16a2p (64mb); mt48lc16m16a2p (128mb) note: 1. all resistor values are 10 ? unless otherwise specified. 2. per industry standard, micron modules use various component speed grades as referenced in the module part numbering guide at www.micron.com/numberguide .
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 7 ?2004 micron technology, inc. all rights reserved. general description the micron ? mt5lsdt472a, mt5lsdt872a(i), and mt5lsdt1672a(i) are a high-speed cmos, dynamic random-access, 32mb, 64mb, and 128mb memory modules organized in a x72, ecc configuration. ecc functions to detect and correct one-bit memory errors. these module use sdram devices which are internally configured as quad-bank drams with a synchronous interface (all signals are registered on the positive edge of the clock signals ck0, ck2). read and write accesses to the sdram module are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the device bank and row to be accessed (ba0, ba1 select th e device bank, a0?a11 for 32mb and 64mb; a0?a12 for 128mb select the device row). the address bits registered coincident with the read or write command (a0?a7 32mb; a0?a8 64mb and 128mb) are used to select the starting device col- umn location for the burst access. these modules provide for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. these modules use an internal pipelined architecture to achieve high-speed operation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high- speed, fully random access. precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, random access operation. these modules are designed to operate in 3.3v, low- power memory systems. an auto refresh mode is pro- vided, along with a power-saving, power-down mode. all inputs, outputs, and clocks are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with auto- matic column-address generation, the ability to inter- leave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding sdram opera- tion, refer to the 64mb, 128mb, or 256mb sdram component data sheets. serial presence-detect operation these modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be pro- grammed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals. write protect (wp) is tied to ground on the module, permanently disabling hardware write protect. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tion. once power is applied to v dd and v dd q (simulta- neously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a com- mand inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop com- mands should be applied. once the 100s delay has been satisfied with at least one command inhibit or nop command having been applied, a precharge command should be applied. all device banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. mode register definition the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an operating mode, and a write burst mode, as shown in the mode register definition dia- gram. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power.
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 8 ?2004 micron technology, inc. all rights reserved. mode register bits m0?m2 specify the burst length, m3 specifies the type of burst (sequential or inter- leaved), m4?m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. for the 128mb module, address a12 (m12) is undefined but should be driven low during loading of the mode register. the mode register must be loaded when all device banks are idle, and the controller must wait the speci- fied time before initiating the subsequent operation. violating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst ori- ented, with the burst length being programmable, as shown in figure 4, mode register definition diagram, on page 8. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in table 7, burst definition table, on page 9. tthe block is uniquely selected by a1?a i when the burst length is set to two; by a2?a i when the burst length is set to four; and by a3?a i when the burst length is set to eight. see note 8 of table 7, burst definition table, on page 9 for a i values. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached, as shown in table 7, burst defini- tion table, on page 9. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in table 7, burst definition table, on page 9. figure 4: mode register definition diagram m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length 128mb module 32mb module, 64mb module m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a10 a11 10 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m12, m11, m10 = ?0, 0, 0? to ensure compatibility with future devices. *should program m11 and m10 = ?0, 0, 0? to ensure compatibility with future devices. a12 12 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 op mode a10 a11 10 11 reserved* wb
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 9 ?2004 micron technology, inc. all rights reserved. note: 1. for full-page accesses: y = 256 (32mb); y = 512 (64mb/ 128mb). 2. for a burst length of two, a1?a i select the block-of- two burst; a0 selects the starting column within the block. 3. for a burst length of four, a2?a i select the block-of- four burst; a?a1 select the starting column within the block. 4. for a burst length of eight, a3?a i select the block-of- eight burst; a0?a2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a0?a i select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0?a i select the unique col- umn to be accessed, and mode register bit m3 is ignored. 8. i = 7 for 32mb module i = 8 for 64mb and 128mb modules figure 5: cas latency diagram cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dq will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all rele- vant access times are met, if a read command is regis- tered at t0 and the latency is programmed to two clocks, the dq will start driving after t1 and the data will be valid by t2, as shown in figure 5, cas latency diagram, on page 9. the cas latency table indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. table 7: burst definition table burst length starting column address order of accesses wthin a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-4-5-6-7-0-1-2- 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0-a i (location 0- y) cn, cn + 1, cn + 2, cn + 3, cn + 4. . . cn - 1, cn . . . not supported clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 10 ?2004 micron technology, inc. all rights reserved. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0- m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (non- burst) accesses. table 8: cas latency table speed allowable operating clock frequency (mhz) cas latency = 2 cas latency = 3 -13e 133 143 -133 100 133 -10e 100 n/a
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 11 ?2004 micron technology, inc. all rights reserved. commands table 9, commands and dqmb operation truth table, provides a general reference of available com- mands. for a more detailed description of commands and operations, refer to the 64mb, 128mb, or 256mb sdram component data sheet. note: 1. a0?a11 define the op-code written to the mode registe r, and for the 128mb module, a12 should be driven low. 2. a0?a11 (32mb and 64mb) or a0?a12 (128mb) provide device row address, and ba0, ba1 determine which device bank is made active. 3. a0?a7 (32mb) or a0?a8 (64mb and 128mb) provide device column address; a10 high enables the auto precharge fea- ture (nonpersistent), while a10 low disables the auto prec harge feature; ba0, ba1 determine which device bank is being read from or written to. 4. a10 low: ba0, ba1 determine the device bank being precha rged. a10 high: all device banks precharged and ba0, ba1 are ?don?t care.? 5. this command is auto refresh if cke is high, self refresh if cke is low. 6. internal refresh counter controls device row addressi ng; all inputs and i/os are ?don?t care? except for cke. 7. activates or deactivates the dq during writes (zero-clock delay) and reads (two-clock delay). table 9: commands and dqmb operation truth table cke is high for all commands shown except self refresh name (function) s# ras# cas# we# dqmb addr dqs notes command inhibit (nop) hxxx x x x no operation (nop) l hhh x x x active (select bank and activate row) l l h h x bank/row x 2 read (select bank and column, and start read burst) lhlh l/h 8 bank/col x 3 write (select bank and column, and start write burst) lhl l l/h 8 bank/col valid 3 burst terminate lhhl x x active precharge (deactivate row in bank or banks) l l h l x code x 4 auto refresh or self refresh (enter self refresh mode) lllh x x x 5, 6 load mode register l l l l x op-code x 1 write enable/output enable ???? l ? active 7 write inhibit/output high-z ???? h ? high-z 7
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 12 ?2004 micron technology, inc. all rights reserved. absolute maximum ratings stresses greater than those listed may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on v dd , v dd q supply relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss . . . . . . . . . . . . . . . . . . . . -1v to +4.6v operating temperature t opr (commercial - ambient) . . . . . . 0c to +65c t opr (industrial - ambient) . . . . . . . -40c to +85c storage temperature (plastic) . . . . . . -55c to +150c table 10: dc electrical characteristics and operating conditions notes: 1, 5, 6; notes appear following the parameter tables; v dd , v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd , v dd q3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 input leakage current: any input 0v v in v dd (all other pins not under test = 0v) command/ address, cke i i -25 25 a 33 ck, s0# -15 15 ck2, s2# -10 10 dqmb -5 5 output leakage current: dqs are disabled; 0v v out v dd q dq i oz -5 5 a 33 output levels: output high voltage (i out = - 4ma) v oh 2.4 ? v output low voltage (i out = 4ma) v ol ?0.4v ta bl e 1 1 : i dd specifications and conditions ? 32mb notes: 1, 5, 6, 11, 13; notes appear following the parameter tables; v dd , v dd q = +3.3v 0.3v; dram components only max parameter/condition symbol -13e -133 -10e units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 625 575 475 ma 3, 18, 19, 29 standby current: power-down mode; all device banks idle; cke = low i dd 2 10 10 10 ma 29 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 225 225 175 ma 3, 12, 19, 29 operating current: burst mode; continuous burst; read or write; all device banks active i dd 4 750 700 600 ma 3, 18, 19, 29 auto refresh current cs# = high; cke = high t rfc = t rfc (min) i dd 5 1,150 1,050 950 ma 3, 12, 18, 19, 29, 30 t rfc = 15.62s i dd 6 15 15 15 ma self refresh current: cke 0.2v i dd 7 555 ma 4
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 13 ?2004 micron technology, inc. all rights reserved. ta bl e 1 2 : i dd specifications and conditions ? 64mb notes: 1, 5, 6, 11, 13; notes appear following the parameter tables; v dd , v dd q = +3.3v 0.3v; dram components only max parameter/condition symbol -13e -133 -10e units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 800 750 700 ma 3, 18, 19, 29 standby current: power-down mode; all device banks idle; cke = low i dd 2 10 10 10 ma 29 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 250 250 200 ma 3, 12, 19, 29 operating current: burst mode; continuous burst; read or write; all device banks active i dd 4 825 750 700 ma 3, 18, 19, 29 auto refresh current cs# = high; cke = high t rfc = t rfc (min) i dd 5 1,650 1,550 1,350 ma 3, 12, 18, 19, 29, 30 t rfc = 15.62s i dd 6 15 15 15 ma self refresh current: cke 0.2v i dd 7 10 10 10 ma 4 ta bl e 1 3 : i dd specifications an d conditions ? 128mb notes: 1, 5, 6, 11, 13; notes appear following the parameter tables; v dd , v dd q = +3.3v 0.3v; dram components only max parameter/condition symbol -13e -133 -10e units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 625 625 625 ma 3, 18, 19, 29 standby current: power-down mode; all device banks idle; cke = low i dd 2 10 10 10 ma 29 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 200 200 200 ma 3, 12, 19, 29 operating current: burst mode; continuous burst; read or write; all device banks active i dd 4 675 675 675 ma 3, 18, 19, 29 auto refresh current cs# = high; cke = high t rfc = t rfc (min) i dd 5 1,425 1,350 1,350 ma 3, 12, 18, 19, 29, 30 t rfc = 7.81s i dd 6 17.5 17.5 17.5 ma self refresh current: cke 0.2v i dd 7 12.5 12.5 12.5 ma 4 table 14: capacitance notes 1, 2; notes appear following parameter table parameter symbol min max units input capacitance: address and command, cke c i 1 12.5 19 pf input capacitance: s0# c i 2 a 7.5 11.4 pf input capacitance: s2# c i 2 b 57.6pf input capacitance: ck0 c i 3 a 14.1 17.1 pf input capacitance: ck2 c i 3 b 18.6 20.6 pf input capacitance: dqmb c i 4 2.5 3.8 pf inuput/output capacitance: dq c io 46pf
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 14 ?2004 micron technology, inc. all rights reserved. table 15: electrical characteristics and recommended ac operating conditions notes: 5, 6, 8, 9, 11, 31; notes appear following the parameter tables; v dd , v dd q = +3.3v 0.3v ac characteristics -13e -133 -10e parameter symbol min max min max min max units notes access time from clk (pos. edge) cl = 3 t ac(3) 5.4 5.4 6 ns 27 cl = 2 t ac(2) 5.4 6 6 ns address hold time t ah 0.8 0.8 1 ns address setup time t as 1.5 1.5 2 ns clk high-level width t ch 2.5 2.5 3 ns clk low-level width t cl 2.5 2.5 3 ns clock cycle time cl = 3 t ck(3) 77.58ns23 cl = 2 t ck(2) 7.5 10 10 ns 23 cke hold time t ckh 0.8 0.8 1 ns cke setup time t cks 1.5 1.5 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 0.8 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 2 ns data-in hold time t dh 0.8 0.8 1 ns data-in setup time t ds 1.5 1.5 2 ns data-out high-impedance time cl = 3 t hz(3) 5.4 5.4 6 ns 10 cl = 2 t hz(2) 5.4 6 6 ns 10 data-out low-impedance time t lz 111ns data-out hold time (load) t oh 333ns data-out hold time (no load) t oh n 1.8 1.8 1.8 ns 28 active to prechargecommand t ras 37 120,000 44 120,000 50 120,000 ns 32 active to active command period t rc 60 66 70 ns active to read or write delay t rcd 15 20 20 ns refresh period (8,192 rows) t ref 64 64 64 ms auto refresh period t rfc 66 66 70 ns precharge command period t rp 15 20 20 ns active bank a to active bank b command t rrd 14 15 20 ns transition time t t 0.3 1.2 0.3 1.2 0.3 1.2 ns 7 write recovery time t wr 1 clk + 7ns 1 clk + 7.5ns 1 clk + 7ns ns 24 14 15 15 ns 25 exit self refresh to active command t xsr 67 75 80 ns 20
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 15 ?2004 micron technology, inc. all rights reserved. table 16: ac functional characteristics notes: 5, 6, 8, 9, 11, 31; notes appear following the parameter tables parameter symbol -13e -133 -10e units notes read/write command to read/write command t ccd 111 t ck 17 cke to clock disable or power-down entry mode t cked 111 t ck 14 cke to clock enable or power-down exit setup mode t ped 111 t ck 14 dqm to input data delay t dqd 000 t ck 17 dqm to data mask during writes t dqm 000 t ck 17 dqm to data high-impedance during reads t dqz 222 t ck 17 write command to input data delay t dwd 000 t ck 17 data-in to active command t dal 454 t ck 15, 21 data-into precharge command t dpl 222 t ck 16, 21 last data-in to burst stop command t bdl 111 t ck 17 last data-in to new read/write command t cdl 111 t ck 17 last data-in to precharge command t rdl 222 t ck 16, 21 load mode register command to active or refresh command t mrd 222 t ck 26 data-out to high-impedance from precharge command cl =3 t roh(3) 333 t ck 17 cl = 2 t roh(2) 222 t ck 17
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 16 ?2004 micron technology, inc. all rights reserved. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +3.3v; f = 1 mhz; t a = 25c; pin under test biased at 1.4v. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (0c t a +70c for commercial, -40c t a +85c for industrial). 6. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifi- cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 9. outputs measured at 1.5v with equivalent load: 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v ih (min) and no longer at the isv crossover point. 12. other input signals are allowed to transition no more than once every two clocks and are other- wise at valid v ih or v il levels. 13. i dd specifications are tested after the device is properly initialized. 14. timing actually specified by t cks; clock(s) speci- fied as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 18. the i dd current will increase or decrease propor- tionally according to the amount of frequency alteration for the test condition. 19. address transitions average one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 10ns for -10e; t ck = 7.5ns for -133 and -13e. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one-third of the cycle rate. v il under- shoot: v il (min) = -2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, includ- ing t wr and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins 7ns for -13e; 7.5ns for -133; and 7ns for -10e after the first clock delay, after the last write is executed. may not exceed limit set for precharge mode. 25. precharge mode only. 26. jedec and pc100 specify three clocks. 27. t ac for -133/-13e at cl = 3 with no load is 4.6ns and is guaranteed by design. 28. parameter guaranteed by design. 29. for -13e, cl = 2 and t ck = 7.5ns; for -133, cl = 3 and t ck = 7.5ns; for -10e, cl=2 and t ck = 10ns. 30. cke is high during refresh command period t rfc (min), else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 31. refer to device data sheet for timing waveforms. 32. the value of t ras used in -13e speed grade mod- ules is calculated from t rc - t rp. 33. leakage number reflects the worst-case leakage possible through the module pin, not what each memory device contributes. q 50pf
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 17 ?2004 micron technology, inc. all rights reserved. spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions, as indicated in figure 6, data validity, and figure 7, defi- nition of start and stop. spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condi- tion, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indi- cate successful data transfers. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data as indicated in figure 8, acknowledge response from receiver, on page 17. the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both the device and a write oper- ation have been selected, the spd device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. in the read mode, the spd device will transmit eight bits of data, release the sda line, and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is gen- erated by the master, the slave will continue to trans- mit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. figure 6: data validity figure 7: definition of start and stop figure 8: acknowledge response from receiver scl sda data stable data stable data change scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 18 ?2004 micron technology, inc. all rights reserved. figure 9: spd eeprom timing diagram table 17: eeprom device select code the most significant bit (b7) is sent first device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1010sa2sa1sa0rw protection register select code 0110sa2sa1sa0rw table 18: eeprom operating modes mode rw bit w c bytes initial sequence current address read 1v ih or v il 1 start, device select, rw = ?1? random address read 0v ih or v il 1 start, device select, rw = ?0?, address 1v ih or v il 1 restart, device select, rw = ?1? sequential read 1v ih or v il 1 similar to current or random address read byte write 0v il 1 start, device select, rw = ?0? page write 0v il 16 start, device select, rw = ?0? scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 19 ?2004 micron technology, inc. all rights reserved. note: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop conditi on of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address. table 19: serial presence-detect eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units supply voltage v dd 33.6v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i outl = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li ?10a output leakage current: v out = gnd to v dd i lo ?10a standby current: scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v 10% i sb ?30a power supply current: scl clock frequency = 100 khz i dd ?2ma table 20: serial presence-detect eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 s data-out hold time t dh 200 ns sda and scl fall time t f 300 ns 2 data-in hold time t hd:dat 0 s start condition hold time t hd:sta 0.6 s clock high period t high 0.6 s noise suppression time constant at scl, sda inputs t i50ns clock low period t low 1.3 s sda and scl rise time t r0.3s2 scl clock frequency f scl 400 khz data-in setup time t su:dat 100 ns start condition setup time t su:sta 0.6 s 3 stop condition setup time t su:sto 0.6 s write cycle time t wrc 10 ms 4
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 20 ?2004 micron technology, inc. all rights reserved. table 21: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low.? byte description entry (version) mt5lsdt472a mt5lsdt872a(i) mt5lsdt1672a(i) 0 number of bytes used by micron 128 80 80 80 1 total number of spd memory bytes 256 08 08 08 2 memory type sdram 04 04 04 3 number of row addresses 12 or 13 0c 0c 0d 4 number of column addresses 8 or 9 08 09 09 5 number of banks 10101 01 6 module data width 72 48 48 48 7 module data width (continued) 00000 00 8 module voltage interface levels lvttl 01 01 01 9 sdram cycle time, t ck (cas latency = 3) 7ns (-13e) 7.5ns (-133) 8ns (-10e) 70 75 80 70 75 80 70 75 80 10 sdram access from clock, t ac (cas latency = 3) 5.4ns (-13e/-133) 6ns (-10e) 54 60 54 60 54 60 11 module configuration type ecc 02 02 02 12 refresh rate/type (80) 15.6s/self (82) 7.81s/self 80 80 82 13 sdram width (primary sdram) 16 10 10 10 14 error-checking sdram data width 16 10 10 10 15 minimum clock delay, t ccd 10101 01 16 burst lengths supported 1, 2, 4, 8, page 8f 8f 8f 17 number of internal banks on sdram device 40404 04 18 cas latencies supported 2, 3 06 06 06 19 cs latency 00101 01 20 we latency 00101 01 21 sdram module attributes unbuffered 00 00 00 22 sdram device attributes: general 0e 0e 0e 0e 23 sdram cycle time, t ck (cas latency = 2) 7.5ns (-13e) 10ns (-133/-10e) 75 a0 75 a0 75 a0 24 sdram access from clock, t ac (cas latency = 2) 5.4ns (-13e) 6ns (-133/-10e) 54 60 54 60 54 60 25 sdram cycle time, t ck (cas latency = 1) ?0000 00 26 sdram access from clock, t ac (cas latency = 1) ?0000 00 27 minimum row precharge time, t rp 15ns (-13e) 20ns (-133/-10e) 0f 14 0f 14 0f 14 28 minimum row active to row active, t rrd 14ns (-13e) 15ns (-133) 20ns (-10e) 0e 0f 14 0e 0f 14 0e 0f 14 29 minimum ras# to cas# delay, t rcd 15ns (-13e) 20ns (-133/-10e) 0f 14 0f 14 0f 14
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 21 ?2004 micron technology, inc. all rights reserved. note: 1. the value of t ras used for the -13e part is calculated from t rc - t rp. actual device specification value is 37ns. 30 minimum ras# pulse width, t ras (note 1) 45ns (-13e) 44ns (-133) 50ns (-10e) 2d 2c 32 2d 2c 32 2d 2c 32 31 module rank density 32mb, 64mb, or 128mb 08 10 20 32 command and address setup time 1.5ns (-13e/-133) 2ns (-10e) 15 20 15 20 15 20 33 command and address hold time 0.8ns (-13e/-133) 1ns (-10e) 08 10 08 10 08 10 34 data signal input setup time 1.5ns (-13e/-133) 2ns (-10e) 15 20 15 20 15 20 35 data signal input hold time 0.8ns (-13e/-133) 1ns (-10e) 08 10 08 10 08 10 36-40 reserved 00 00 00 41 device minimum active/auto-refresh time, t rc 60ns (-13e) 66ns (-133) 70ns (10e) 3c 42 46 3c 42 46 3c 42 46 42-61 reserved 00 00 00 62 spd revision 2.0 02 20 20 63 checksum for bytes 0-62 -13e -133 -10e 9c e8 34 a5 f1 3d b8 04 50 64 manufacturer?s jedec id code micron 2c 2c 2c 65-71 manufacturer?s jedec id code (continued) ff ff ff 72 manufacturing location 1?12 01?0c 01?0c 01?0c 73-90 module part number (ascii) variable data variable data variable data 91 pcb identification code 1-9 01-09 01-09 01-09 92 identification code (continued) 00000 00 93 year of manufacture in bcd variable data variable data variable data 94 week of manufacture in bcd variable data variable data variable data 95-98 module serial number variable data variable data variable data 99-125 manufacturer-specific data (rsvd) variable data variable data variable data 126 system frequency 100/133 mhz 64 64 64 127 sdram component and clock detail af af af table 21: serial presence-detect matrix ?1?/?0?: serial data, ?driven to high?/?driven to low.? byte description entry (version) mt5lsdt472a mt5lsdt872a(i) mt5lsdt1672a(i)
32mb, 64mb, 128mb (x72, sr) 168-pin sdram udimm 32, 64, 128mb x 64 sdram dimm micron technology, inc., reserves the right to change products or specifications without notice. sd5c4_8_16x72ag.fm - rev. c 6/04 en 22 ?2004 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.m icron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. all other trademarks are the property of their respective owners. figure 10: 168-pin dimm note: all dimensions in inches (millimet ers) or typical where noted. data sheet designation released (no mark): this data sheet contains mini- mum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. pin 1 (pin 85 on backside) 0.700 (17.78) typ 0.118 (3.00) (2x) 0.118 (3.00) typ 4.550 (115.57) 0.050 (1.27) typ 0.118 (3.00) typ 0.039 (1.00) typ 0.079 (2.00) r (2x) 0.039 (1.00)r (2x) front view 0.128 (3.25) 0.118 (3.00) pin 84 (pin 168 on backside) (2x) 0.250 (6.35) typ 1.661 (42.18) 2.625 (66.68) 1.005 (25.53) 0.995 (25.27) 5.256 (133.50) 5.244 (133.20) 0.125 (3.18) max 0.054 (1.37) 0.046 (1.17) u1 u2 u4 u5 u3 u6 max min

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