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preliminary user?s manual v850es/sg2 tm 32-bit single-chip microcontroller hardware document no. u16541ej1v0um00 (1st edition) date published february 2003 n cp(k) printed in japan ? pd703260 pd703270 pd703280 pd703260y pd703270y pd703280y pd703261 pd703271 pd703281 pd703261y pd703271y pd703281y pd703262 pd703272 pd703282 pd703262y pd703272y pd703282y pd703263 pd703273 pd703283 pd703263y pd703273 pd703283y pd70f3261 pd70f3271 pd70f3281 pd70f3261y pd70f3271y pd70f3281y pd70f3263 pd70f3273 pd70f3283 pd70f3263y pd70f3273y pd70f3283y 2003
preliminary user?s manual u16541ej1v0um 2 [memo]
preliminary user?s manual u16541ej1v0um 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. purchase of nec electronics i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. iebus and inter equipment bus are registered trademarks of nec electronics corporation. v850 series and v850/sg2 are trademarks of nec electronics corporation.
preliminary user ? s manual u16541ej1v0um 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. license no needed: pd70f3261, 70f3261y, 70f3263, 70f3263y, 70f3271, 70f3271y, 70f3273, 70f3273y, 70f3281, 70f3281y, 70f3283, 70f3283y the customer must judge the need for a license: pd703260, 703260y, 703261, 703261y, 703262, 703262y, 703263, 703263y, 703270, 703270y, 703271, 703271y, 703272, 703272y, 703273, 703273y, 703280, 703280y, 703281, 703281y, 703282, 703282y, 703283, 703283y the information contained in this document is being issued in advance of the production cycle for the product. the parameters for the product may change before final production or nec electronics corporation, at its own discretion, may withdraw the product prior to its production. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannnot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire- containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special", and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics products before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m5 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":
preliminary user ? s manual u16541ej1v0um 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 fax: 6250-3583 j02.11 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 sucursal en espa ? a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 succursale fran ? aise filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 tyskland filial taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
preliminary user?s manual u16541ej1v0um 6 preface readers this manual is intended for users who wish to understand the functions of the v850es/sg2 and design application systems using these products. purpose this manual is intended to give users an understanding of the hardware functions of the v850es/sg2 shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? data types ? cpu function ? register set ? on-chip peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? pipeline operation how to read this manual it is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to understand the details of an instruction function refer to the v850es architecture user?s manual available separately. register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defined as a reserved word in the device file. to understand the overall functions of the v850es/sg2 read this manual according to the contents . conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (overscore over pin or signal name) memory map address: higher addresses on the top and lower addresses on the bottom note: footnote for item marked with note in the text caution: information requiring particular attention remark: supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3
preliminary user?s manual u16541ej1v0um 7 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v850es/sg2 document name document no. v850es architecture user?s manual u15943e v850es/sg2 hardware user?s manual this manual documents related to development tools document name document no. ie-v850es-g1 (in-circuit emulator) to be prepared ie-703288-g1-em1 (in-circuit emulator option board) to be prepared operation u16053e c language u16054e pm plus u16055e ca850 ver. 2.50 c compiler package assembly language u16042e id850 ver. 2.50 integrated debugger operation u16217e sm850 ver. 2.50 systerm simulator operation u15182e sm850 ver. 2.00 or later system simulator external part user open interface specification u14873e basics u13430e installation u13410e rx850 ver. 3.13 or later real-time os technical u13431e basics u13773e installation u13774e rx850 pro ver. 3.15 real-time os technical u13772e rd850 ver. 3.01 task debugger u13737e rd850 pro ver. 3.01 task debugger u13916e az850 ver. 3.0 system performance analyzer u14410e pg-fp4 flash memory programmer u15260e
preliminary user?s manual u16541ej1v0um 8 contents chapter 1 introduction...................................................................................................... ............32 1.1 general..................................................................................................................... .................32 1.2 features .................................................................................................................... ................35 1.3 application fields.......................................................................................................... ..........36 1.4 ordering information........................................................................................................ .......37 1.5 pin configuration (top view) ................................................................................................ .39 1.6 function block configuration ................................................................................................ 44 1.6.1 internal block diagram .................................................................................................... ...........44 1.6.2 internal units ............................................................................................................ ..................45 chapter 2 pin functions .................................................................................................... ............48 2.1 list of pin functions ....................................................................................................... ........48 2.2 pin states.................................................................................................................. ................55 2.3 description of pin functions................................................................................................ ..56 2.4 pin i/o circuit types, i/o buffer power supplies and handling of unused pins ..............65 chapter 3 cpu function ..................................................................................................... ............70 3.1 features .................................................................................................................... ................70 3.2 cpu register set ............................................................................................................ .........71 3.2.1 program register set ...................................................................................................... ............72 3.2.2 system register set....................................................................................................... .............73 3.3 operation modes ............................................................................................................. ........79 3.3.1 operation modes ........................................................................................................... ............79 3.4 address space ............................................................................................................... ..........80 3.4.1 cpu address space......................................................................................................... ..........80 3.4.2 image..................................................................................................................... ....................81 3.4.3 wraparound of cpu address space..........................................................................................8 2 3.4.4 memory map................................................................................................................ ..............83 3.4.5 areas ..................................................................................................................... ....................85 3.4.6 recommended use of address space .......................................................................................93 3.4.7 peripheral i/o registers.................................................................................................. ............96 3.4.8 programmable peripheral i/o registers....................................................................................1 07 3.4.9 special registers ......................................................................................................... .............108 3.4.10 notes .................................................................................................................... ...................112 chapter 4 port functions ................................................................................................... .......114 4.1 features .................................................................................................................... ..............114 4.2 basic port configuration .................................................................................................... ..114 4.3 port configuration .......................................................................................................... .......115 4.3.1 notes on setting port pins................................................................................................ ........115 4.3.2 port 0 .................................................................................................................... ...................116 4.3.3 port 1 .................................................................................................................... ...................121
preliminary user?s manual u16541ej1v0um 9 4.3.4 port 3.................................................................................................................... ................... 123 4.3.5 port 4.................................................................................................................... ................... 131 4.3.6 port 5.................................................................................................................... ................... 135 4.3.7 port 7.................................................................................................................... ................... 140 4.3.8 port 9.................................................................................................................... ................... 143 4.3.9 port cm ................................................................................................................... ................ 153 4.3.10 port ct .................................................................................................................. .................. 156 4.3.11 port dh.................................................................................................................. .................. 159 4.3.12 port dl .................................................................................................................. .................. 162 4.4 port function operation ..................................................................................................... ..176 4.4.1 write to i/o ports ........................................................................................................ ............. 176 4.4.2 read from i/o port........................................................................................................ ........... 176 4.4.3 i/o port calculation ...................................................................................................... ............ 176 chapter 5 bus control function ...........................................................................................1 77 5.1 features.................................................................................................................... ..............177 5.2 bus control pins ............................................................................................................ .......178 5.2.1 pin status when internal rom, internal ram, or on-chip peripheral i/o is accessed.............. 178 5.2.2 pin status in each operation mode ......................................................................................... . 178 5.3 memory block function....................................................................................................... .179 5.4 external bus interface mode control function ..................................................................180 5.5 bus access .................................................................................................................. ..........181 5.5.1 number of clocks for access ............................................................................................... .... 181 5.5.2 bus size setting function ................................................................................................. ........ 181 5.5.3 access by bus size........................................................................................................ .......... 182 5.6 wait function............................................................................................................... ..........188 5.6.1 programmable wait function................................................................................................ .... 188 5.6.2 external wait function .................................................................................................... .......... 189 5.6.3 relationship between programmable wait and external wait .................................................. 190 5.6.4 programmable address wait function ...................................................................................... 19 1 5.7 idle state insertion function ............................................................................................... .192 5.8 bus hold function........................................................................................................... ......193 5.8.1 functional outline ........................................................................................................ ............ 193 5.8.2 bus hold procedure ........................................................................................................ ......... 194 5.8.3 operation in power save mode .............................................................................................. . 194 5.9 bus priority ................................................................................................................ ............195 5.10 boundary operation conditions..........................................................................................195 5.10.1 program space ............................................................................................................ ............ 195 5.10.2 data space ............................................................................................................... ............... 195 5.11 bus timing ................................................................................................................. ............196 5.11.1 multiplexed bus .......................................................................................................... ............. 196 5.11.2 separate bus ............................................................................................................. .............. 205 chapter 6 clock generation function................................................................................214 6.1 overview.................................................................................................................... .............214 6.2 configuration ............................................................................................................... ..........215
preliminary user?s manual u16541ej1v0um 10 6.3 control registers........................................................................................................... ........217 6.4 operation ................................................................................................................... .............222 6.4.1 operation of each clock................................................................................................... ........222 6.4.2 clock output function ..................................................................................................... ..........222 6.5 pll function................................................................................................................ ..........223 6.5.1 overview.................................................................................................................. ................223 6.5.2 control registers ......................................................................................................... .............223 6.5.3 usage ..................................................................................................................... .................227 chapter 7 16-bit timer/event counter p ..............................................................................228 7.1 features .................................................................................................................... ..............228 7.2 function outline ............................................................................................................ ........228 7.3 configuration ............................................................................................................... ..........229 7.4 control registers........................................................................................................... ........233 7.5 operation ................................................................................................................... .............239 7.5.1 anytime write and reload .................................................................................................. .......239 7.5.2 interval timer mode (tpnmd2 to tpnmd0 = 000) ...................................................................244 7.5.3 external event count mode (tpnmd2 to tpnmd0 = 001) .......................................................247 7.5.4 external trigger pulse mode (tpnmd2 to tpnmd0 = 010) ......................................................251 7.5.5 one-shot pulse mode (tpnmd2 to tpnmd0 = 011)................................................................254 7.5.6 pwm mode (tpnmd2 to tpnmd0 = 110) ...............................................................................257 7.5.7 free-running mode (tpnmd2 to tpnmd0 = 101) ...................................................................262 7.5.8 pulse width measurement mode (tpnmd2 to tpnmd0 = 110)...............................................268 chapter 8 16-bit timer/event counter q..............................................................................270 8.1 features .................................................................................................................... ..............270 8.2 function outline ............................................................................................................ ........270 8.3 configuration ............................................................................................................... ..........271 8.4 control registers........................................................................................................... ........276 8.5 operation ................................................................................................................... .............282 8.5.1 anytime write and reload .................................................................................................. .......282 8.5.2 interval timer mode (tq0md2 to tq0md0 = 000) ..................................................................287 8.5.3 external event count mode (tq0md2 to tq0md0 = 001) ......................................................290 8.5.4 external trigger pulse mode (tq0md2 to tq0md0 = 010) .....................................................294 8.5.5 one-shot pulse mode (tq0md2 to tq0md0 = 011)...............................................................297 8.5.6 pwm mode (tq0md2 to tq0md0 = 110) ..............................................................................300 8.5.7 free-running mode (tq0md2 to tq0md0 = 101)...................................................................305 8.5.8 pulse width measurement mode (tq0md2 to tq0md0 = 110) ..............................................312 chapter 9 16-bit interval timer m ........................................................................................ ..314 9.1 outline ..................................................................................................................... ...............314 9.2 configuration ............................................................................................................... ..........315 9.3 control register............................................................................................................ .........316 9.4 operation ................................................................................................................... .............317 9.4.1 interval timer mode....................................................................................................... ...........317
preliminary user?s manual u16541ej1v0um 11 9.4.2 clock generator and clock enable timing ................................................................................ 317 chapter 10 real-time output function (rto) ....................................................................318 10.1 function ................................................................................................................... ..............318 10.2 configuration .............................................................................................................. ...........319 10.3 control registers .......................................................................................................... ........320 10.4 operation.................................................................................................................. ..............322 10.5 usage...................................................................................................................... ................323 10.6 cautions ................................................................................................................... ..............323 chapter 11 watch timer functions........................................................................................32 4 11.1 functions .................................................................................................................. .............324 11.2 configuration .............................................................................................................. ...........326 11.3 control registers .......................................................................................................... ........327 11.4 operation.................................................................................................................. ..............329 11.4.1 operation as watch timer ................................................................................................. ....... 329 11.4.2 operation as interval timer .............................................................................................. ........ 329 11.4.3 cautions ................................................................................................................. ................. 330 11.5 prescaler 3................................................................................................................ ..............331 11.5.1 control register......................................................................................................... ............... 331 11.5.2 generation of watch timer count clock .................................................................................... 332 chapter 12 functions of watchdog timer 2 ....................................................................333 12.1 functions .................................................................................................................. .............333 12.2 configuration .............................................................................................................. ...........334 12.3 control registers .......................................................................................................... ........334 12.4 operation.................................................................................................................. ..............338 chapter 13 a/d converter ................................................................................................... .......340 13.1 functions .................................................................................................................. .............340 13.2 configuration .............................................................................................................. ...........342 13.3 control registers .......................................................................................................... ........344 13.4 operation.................................................................................................................. ..............352 13.4.1 basic operation.......................................................................................................... .............. 352 13.4.2 trigger mode ............................................................................................................. .............. 354 13.4.3 operation mode........................................................................................................... ............ 356 13.4.4 power-fail compare mode .................................................................................................. ..... 362 13.5 cautions ................................................................................................................... ..............368 13.6 how to read a/d converter characteristics table ............................................................371 chapter 14 d/a converter ................................................................................................... .......375 14.1 functions .................................................................................................................. .............375 14.2 configuration .............................................................................................................. ...........375 14.3 control registers .......................................................................................................... ........376
preliminary user?s manual u16541ej1v0um 12 14.4 operation .................................................................................................................. ..............378 14.4.1 operation in normal mode ................................................................................................. ......378 14.4.2 operation in real-time output mode ....................................................................................... ..378 14.4.3 cautions ................................................................................................................. .................379 chapter 15 asynchronous serial interface a (uarta) ...............................................380 15.1 mode switching of uarta and other serial interfaces ....................................................380 15.1.1 csib4 and uarta0 mode switching ......................................................................................380 15.1.2 uarta2 and i 2 c00 mode switching ........................................................................................381 15.1.3 uarta1 and i 2 c02 mode switching ........................................................................................382 15.2 features ................................................................................................................... ...............383 15.3 configuration .............................................................................................................. ...........384 15.4 control registers.......................................................................................................... .........386 15.5 interrupt request signals .................................................................................................. ...393 15.6 operation .................................................................................................................. ..............394 15.6.1 data format.............................................................................................................. ................394 15.6.2 sbf transmission/reception format ........................................................................................ .396 15.6.3 sbf transmission ......................................................................................................... ...........398 15.6.4 sbf reception............................................................................................................ ..............399 15.6.5 uart transmission........................................................................................................ ..........400 15.6.6 continuous transmission procedure ........................................................................................ 401 15.6.7 uart reception ........................................................................................................... ............403 15.6.8 reception error.......................................................................................................... ..............404 15.6.9 parity types and operations .............................................................................................. .......405 15.6.10 receive data noise filter ............................................................................................... ...........406 15.7 dedicated baud rate generator...........................................................................................407 chapter 16 3-wire variable-length serial i/o (csib) .....................................................415 16.1 mode switching of csib and other serial interfaces ........................................................415 16.1.1 csib4 and uarta0 mode switching ......................................................................................415 16.1.2 csib0 and i 2 c01 mode switching ............................................................................................417 16.2 features ................................................................................................................... ...............418 16.3 configuration .............................................................................................................. ...........418 16.4 control registers.......................................................................................................... .........421 16.5 operation .................................................................................................................. ..............427 16.5.1 single transfer (master mode, transmission/reception mode) .................................................427 16.5.2 single transfer mode (master mode, reception mode) ............................................................428 16.5.3 continuous mode (master mode, transmission/reception mode) ............................................429 16.5.4 continuous mode (master mode, reception mode) .................................................................430 16.5.5 continuous reception mode (error)........................................................................................ ..431 16.5.6 continuous mode (slave mode, transmission/reception mode)...............................................432 16.5.7 continuous mode (slave mode, reception mode) ....................................................................433 16.5.8 clock timing ............................................................................................................. ................434 16.6 output pins ................................................................................................................ ............436 16.7 operation flow............................................................................................................. ..........437 16.8 baud rate generator........................................................................................................ .....443
preliminary user?s manual u16541ej1v0um 13 16.8.1 baud rate generation..................................................................................................... .......... 444 chapter 17 i 2 c bus ......................................................................................................................... ..445 17.1 mode switching of i 2 c bus and other serial interfaces ....................................................445 17.1.1 uarta2 and i 2 c00 mode switching ........................................................................................ 445 17.1.2 csib0 and i 2 c01 mode switching............................................................................................ 446 17.1.3 uarta1 and i 2 c02 mode switching ........................................................................................ 447 17.2 features................................................................................................................... ...............448 17.3 configuration .............................................................................................................. ...........451 17.4 control registers .......................................................................................................... ........453 17.5 i 2 c bus mode functions........................................................................................................468 17.5.1 pin configuration........................................................................................................ .............. 468 17.6 i 2 c bus definitions and control methods ...........................................................................469 17.6.1 start condition .......................................................................................................... ............... 469 17.6.2 addresses ................................................................................................................ ............... 470 17.6.3 transfer direction specification ......................................................................................... ...... 471 17.6.4 acknowledge signal (ack)................................................................................................. ..... 472 17.6.5 stop condition........................................................................................................... ............... 473 17.6.6 wait signal (wait) ....................................................................................................... ........... 474 17.7 i 2 c interrupt request signals (intiicn) ...............................................................................476 17.7.1 master device operation .................................................................................................. ........ 476 17.7.2 slave device operation (when receiving slave address data (matches with address)) ........... 479 17.7.3 slave device operation (when receiving extension code) ....................................................... 483 17.7.4 operation without communication .......................................................................................... . 487 17.7.5 arbitration loss operation (operation as slave after arbitration loss) ....................................... 487 17.7.6 operation when arbitration loss occurs (no communication after arbitration loss).................. 489 17.8 interrupt request signal (intiicn) generation timing and wait control........................494 17.9 address match detection method .......................................................................................495 17.10 error detection ........................................................................................................... ...........495 17.11 extension code ............................................................................................................ .........495 17.12 arbitration ............................................................................................................... ...............496 17.13 wakeup function........................................................................................................... ........497 17.14 communication reservation................................................................................................4 98 17.14.1 when communication reservation function is enabled (iicrsvn bit of iicfn register = 0) ..... 498 17.14.2 when communication reservation function is disabled (iicrsvn bit of iicfn register = 1) .... 502 17.15 cautions .................................................................................................................. ...............503 17.16 communication operations .................................................................................................5 04 17.16.1 master operation 1 ...................................................................................................... ............ 504 17.16.2 master operation 2 ...................................................................................................... ............ 506 17.16.3 slave operation ......................................................................................................... .............. 507 17.17 timing of data communication ...........................................................................................508 chapter 18 iebus controller ................................................................................................ ....515 18.1 functions .................................................................................................................. .............515 18.1.1 communication protocol of iebus .......................................................................................... . 515 18.1.2 determination of bus mastership (arbitration) ......................................................................... 516
preliminary user?s manual u16541ej1v0um 14 18.1.3 communication mode....................................................................................................... .......516 18.1.4 communication address.................................................................................................... ......516 18.1.5 broadcast communication .................................................................................................. .....517 18.1.6 transfer format of iebus ................................................................................................. ........517 18.1.7 transfer data ............................................................................................................ ...............527 18.1.8 bit format ............................................................................................................... ..................529 18.2 configuration .............................................................................................................. ...........530 18.3 control registers.......................................................................................................... .........532 18.4 interrupt operations of iebus controller ............................................................................562 18.4.1 interrupt control block .................................................................................................. ............562 18.4.2 example of identifying interrupt ......................................................................................... ......564 18.4.3 interrupt source list .................................................................................................... ..............567 18.4.4 communication error source processing list ...........................................................................568 18.5 interrupt request signal generation timing and main cpu processing ........................570 18.5.1 master transmission ...................................................................................................... ..........570 18.5.2 master reception......................................................................................................... .............572 18.5.3 slave transmission ....................................................................................................... ...........574 18.5.4 slave reception.......................................................................................................... ..............576 18.5.5 interval of occurrence of interrupt request signal for iebus control.........................................578 chapter 19 can controller.................................................................................................. .....582 19.1 outline .................................................................................................................... ................582 19.1.1 features ................................................................................................................. .................582 19.1.2 overview of functions .................................................................................................... ..........583 19.1.3 configuration ............................................................................................................ ...............584 19.2 can protocol ............................................................................................................... ..........585 19.2.1 frame format ............................................................................................................. ..............585 19.2.2 frame types.............................................................................................................. ...............586 19.2.3 data frame and remote frame.............................................................................................. ....586 19.2.4 error frame .............................................................................................................. ................594 19.2.5 overload frame........................................................................................................... .............595 19.3 functions.................................................................................................................. ..............596 19.3.1 arbitration .............................................................................................................. ..................596 19.3.2 bit stuffing............................................................................................................. ...................597 19.3.3 multi masters ............................................................................................................ ...............597 19.3.4 multi cast ............................................................................................................... ..................597 19.3.5 sleep mode/stop function ................................................................................................. .......597 19.3.6 error control function ................................................................................................... ............598 19.3.7 baud rate control function............................................................................................... .........601 19.3.8 state transition chart................................................................................................... .............604 19.4 connection with target system ...........................................................................................607 19.5 internal registers of can controller ...................................................................................608 19.5.1 can controller configuration............................................................................................. .......608 19.5.2 register access type ..................................................................................................... ..........609 19.5.3 control bits of message buffers.......................................................................................... .....626 19.6 control registers.......................................................................................................... .........629 19.7 bit set/clear function ..................................................................................................... ......663
preliminary user?s manual u16541ej1v0um 15 19.8 can controller initialization.............................................................................................. ...665 19.8.1 initialization of can module ............................................................................................. ....... 665 19.8.2 initialization of message buffer......................................................................................... ....... 665 19.8.3 transition from init mode in operational mode ...................................................................... 666 19.8.4 resetting of can module error counter c0erc in init mode................................................ 667 19.9 message reception .......................................................................................................... .....668 19.9.1 message reception ........................................................................................................ .......... 668 19.9.2 receive history list function............................................................................................ ......... 668 19.9.3 mask function ............................................................................................................ .............. 672 19.9.4 multi buffer receive block function ...................................................................................... ..... 673 19.9.5 remote frame reception................................................................................................... ....... 673 19.10 message transmission ...................................................................................................... ...675 19.10.1 message transmission.................................................................................................... ......... 675 19.10.2 transmit history list function.......................................................................................... .......... 677 19.10.3 automatic block transmission (abt) ...................................................................................... . 680 19.10.4 transmission request abort process ...................................................................................... . 680 19.11 power saving modes........................................................................................................ .....682 19.11.1 can sleep mode .......................................................................................................... ........... 682 19.11.2 can stop mode ........................................................................................................... ............ 682 19.12 interrupt function........................................................................................................ ..........684 19.12.1 interrupts generated by can module...................................................................................... 684 19.13 diagnosis functions and special operational modes.......................................................685 19.13.1 receive-only mode....................................................................................................... ........... 685 19.13.2 single-shot mode ........................................................................................................ ............ 686 19.13.3 self-test mode .......................................................................................................... ............... 687 19.14 time stamp function ....................................................................................................... .....688 19.14.1 basic time stamp function ............................................................................................... ........ 688 19.15 rules for setting baud rate ............................................................................................... ..689 19.16 operation of can controller ............................................................................................... .693 chapter 20 dma functions (dma controller) ..................................................................715 20.1 features................................................................................................................... ...............715 20.2 configuration .............................................................................................................. ...........716 20.3 control registers .......................................................................................................... ........717 20.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) ........................................................... 717 20.3.2 dma destination address registers 0 to 3 (dda0 to dda3) .................................................... 718 20.3.3 dma byte count registers 0 to 3 (dbc0 to dbc3)................................................................... 719 20.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3)................................................. 720 20.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) ..................................................... 721 20.3.6 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) ........................................................... 722 20.4 dma bus states............................................................................................................. ........725 20.4.1 types of bus states ...................................................................................................... ........... 725 20.4.2 dmac bus cycle state transition .......................................................................................... ... 726 20.5 transfer mode.............................................................................................................. ..........727 20.5.1 single transfer mode ..................................................................................................... .......... 727 20.6 transfer types............................................................................................................. ..........727 20.6.1 two-cycle transfer ....................................................................................................... ............ 727
preliminary user?s manual u16541ej1v0um 16 20.7 transfer object ............................................................................................................ ..........728 20.7.1 transfer object.......................................................................................................... ...............728 20.7.2 external bus cycles during dma transfer (two-cycle transfer).................................................728 20.8 dma channel priorities..................................................................................................... ....729 20.9 dma transfer start factors ................................................................................................. .729 20.10 dma transfer end .......................................................................................................... .......729 20.10.1 dma transfer end interrupt .............................................................................................. ........729 20.10.2 terminal count output upon dma transfer end........................................................................729 20.11 precautions ............................................................................................................... .............730 20.11.1 interrupt factors ....................................................................................................... ................731 chapter 21 crc function .................................................................................................... .........732 21.1 functions.................................................................................................................. ..............732 21.2 configuration .............................................................................................................. ...........732 21.3 control registers.......................................................................................................... .........733 21.4 operation .................................................................................................................. ..............734 21.4.1 crc operation circuit operation example................................................................................73 4 21.4.2 operation circuit configuration.......................................................................................... .......735 21.4.3 usage method ............................................................................................................. ............736 chapter 22 interrupt/exception processing function ................................................738 22.1 features ................................................................................................................... ...............738 22.2 non-maskable interrupts.................................................................................................... ...742 22.2.1 operation................................................................................................................ .................744 22.2.2 restore .................................................................................................................. ..................745 22.2.3 np flag.................................................................................................................. ...................746 22.2.4 eliminating noise on nmi pin ............................................................................................. ......746 22.2.5 function to detect edge of nmi pin....................................................................................... ...746 22.3 maskable interrupts........................................................................................................ .......748 22.3.1 operation................................................................................................................ .................748 22.3.2 restore .................................................................................................................. ..................750 22.3.3 priorities of maskable interrupts ........................................................................................ ......751 22.3.4 interrupt control register (xxicn)....................................................................................... .......755 22.3.5 interrupt mask registers 0 to 3 (imr0 to imr3) .......................................................................758 22.3.6 in-service priority register (ispr) ...................................................................................... ......759 22.3.7 id flag .................................................................................................................. ....................760 22.3.8 watchdog timer mode register 2 (wdtm2) .............................................................................761 22.3.9 eliminating noise on intp0 to intp7 pins ..............................................................................761 22.3.10 function to detect edge of intp0 to intp7 pins .....................................................................761 22.4 software exception ......................................................................................................... ......766 22.4.1 operation................................................................................................................ .................766 22.4.2 restore .................................................................................................................. ..................767 22.4.3 ep flag .................................................................................................................. ...................768 22.5 exception trap ............................................................................................................. ..........769 22.5.1 illegal opcode definition ................................................................................................ ...........769 22.5.2 debug trap............................................................................................................... ................771
preliminary user?s manual u16541ej1v0um 17 22.6 interrupt acknowledge time of cpu ...................................................................................773 22.7 periods in which interrupts are not acknowledged by cpu ...........................................774 chapter 23 key interrupt function.......................................................................................77 5 23.1 function ................................................................................................................... ..............775 23.2 control register ........................................................................................................... .........776 chapter 24 standby function ................................................................................................ ...777 24.1 overview................................................................................................................... ..............777 24.2 halt mode.................................................................................................................. ...........780 24.2.1 setting and operation status............................................................................................. ....... 780 24.2.2 releasing halt mode ...................................................................................................... ...... 780 24.3 idle1 mode ................................................................................................................. ...........782 24.3.1 setting and operation status............................................................................................. ....... 782 24.3.2 releasing idle1 mode ..................................................................................................... ...... 782 24.4 idle2 mode ................................................................................................................. ...........784 24.4.1 setting and operation status............................................................................................. ....... 784 24.4.2 releasing idle2 mode ..................................................................................................... ...... 784 24.4.3 securing setup time when releasing idle2 mode .................................................................. 786 24.5 software stop mode ......................................................................................................... ...787 24.5.1 setting and operation status............................................................................................. ....... 787 24.5.2 releasing software stop mode ............................................................................................. 787 24.5.3 securing oscillation stabilization time when releasing software stop mode ......................... 789 24.7 subclock operation mode .................................................................................................... 790 24.7.1 setting and operation status............................................................................................. ....... 790 24.7.2 releasing subclock operation mode ....................................................................................... 7 90 24.8 sub-idle mode .............................................................................................................. ........792 24.8.1 setting and operation status............................................................................................. ....... 792 24.8.2 releasing sub-idle mode .................................................................................................. .... 792 24.9 control registers .......................................................................................................... ........794 chapter 25 reset functions ................................................................................................. .....795 25.1 overview................................................................................................................... ..............795 25.2 registers to check reset source ........................................................................................795 25.3 operation.................................................................................................................. ..............796 25.3.1 reset operation via reset pin............................................................................................ ... 796 25.3.2 reset operation by wdt2res signal ..................................................................................... 79 8 25.3.3 reset operation by low-voltage detector ................................................................................. 8 00 25.3.4 clock monitor ............................................................................................................ .............. 804 chapter 26 regulator ........................................................................................................ ..........807 26.1 outline .................................................................................................................... ................807 26.2 operation.................................................................................................................. ..............808
preliminary user?s manual u16541ej1v0um 18 chapter 27 rom correction function ..................................................................................809 27.1 overview ................................................................................................................... ..............809 27.2 control registers.......................................................................................................... .........810 27.3 rom correction operation and program flow...................................................................812 chapter 28 flash memory .................................................................................................... .......814 28.1 features ................................................................................................................... ...............815 28.1.1 erasure unit ............................................................................................................. ................815 28.2 writing with flash programmer ...........................................................................................816 28.3 programming environment ..................................................................................................81 6 28.4 communication mode ......................................................................................................... ..817 28.5 pin connection ............................................................................................................. .........819 28.5.1 flmd0 pin ................................................................................................................ ...............819 28.5.2 flmd1 pin ................................................................................................................ ...............820 28.5.3 serial interface pin..................................................................................................... ..............821 28.5.4 reset pin................................................................................................................ ...............823 28.5.5 port pins (including nmi) ................................................................................................ .........823 28.5.6 other signal pins........................................................................................................ ..............823 28.5.7 power supply ............................................................................................................. ..............823 28.6 programming method......................................................................................................... ...824 28.6.1 flash memory control ..................................................................................................... .........824 28.6.2 flash memory programming mode..........................................................................................82 5 28.6.3 selection of communication mode.......................................................................................... .826 28.6.4 communication command .................................................................................................... ...827
preliminary user?s manual u16541ej1v0um 19 list of figures (1/9) figure no. title page 2-1 pin i/o circuits ............................................................................................................ .................................... 68 3-1 cpu address space ........................................................................................................... ............................ 80 3-2 image on address space ...................................................................................................... .......................... 81 3-3 data memory map (physical addresses) ........................................................................................ ................ 83 3-4 program memory map.......................................................................................................... ........................... 84 3-5 internal rom area (256 kb) .................................................................................................. ......................... 85 3-6 internal rom/internal flash memory area (384 kb)............................................................................ ........... 86 3-7 internal rom area (512 kb) .................................................................................................. ......................... 86 3-8 internal rom/internal flash memory area (640 kb)............................................................................ ........... 87 3-9 internal ram area (24 kb)................................................................................................... ........................... 89 3-10 internal ram area (32 kb).................................................................................................. ............................ 90 3-11 internal ram area (40 kb).................................................................................................. ............................ 90 3-12 internal ram area (48 kb).................................................................................................. ............................ 91 3-13 on-chip peripheral i/o area ................................................................................................ ........................... 92 3-14 recommended memory map ..................................................................................................... ..................... 95 3-15 timing when on-chip debug function is not used............................................................................. ........ 113 4-1 port configuration diagram.................................................................................................. ......................... 114 5-1 data memory map............................................................................................................. ............................ 179 5-2 little-endian address in word............................................................................................... ........................ 182 5-3 inserting wait example ...................................................................................................... ........................... 190 5-4 basic bus cycle ............................................................................................................. ............................... 196 5-5 when wait state (1 wait) is inserted ........................................................................................ .................... 197 5-6 when idle state is inserted ................................................................................................. .......................... 198 5-7 when wait state (1 wait) and idle state are inserted ........................................................................ .......... 199 5-8 when address wait state is inserted ......................................................................................... .................. 200 5-9 basic bus cycle ............................................................................................................. ............................... 201 5-10 when wait state (1 wait) is inserted ....................................................................................... ..................... 202 5-11 when address wait state is inserted ........................................................................................ ................... 203 5-12 bus hold cycle............................................................................................................. ................................. 204 5-13 basic bus cycle ............................................................................................................ ................................ 205 5-14 when wait state (1 wait) is inserted ....................................................................................... ..................... 206 5-15 when idle state is inserted ................................................................................................ ........................... 207 5-16 when wait state (1 wait) and idle state are inserted ....................................................................... ........... 208 5-17 when address wait state is inserted ........................................................................................ ................... 209 5-18 basic bus cycle ............................................................................................................ ................................ 210 5-19 when wait state (1 wait) is inserted ....................................................................................... ..................... 211 5-20 when address wait state is inserted ........................................................................................ ................... 212
preliminary user?s manual u16541ej1v0um 20 list of figures (2/9) figure no. title page 5-21 bus hold cycle ............................................................................................................. .................................213 6-1 clock generator ............................................................................................................. ...............................215 7-1 block diagram of timer p.................................................................................................... ..........................229 7-2 flowchart of basic operation for anytime write.............................................................................. ..............240 7-3 timing diagram for anytime write............................................................................................ .....................241 7-4 flowchart of basic operation for reload..................................................................................... ..................242 7-5 timing chart for reload ..................................................................................................... ...........................243 7-6 flowchart of basic operation in interval timer mode......................................................................... ...........244 7-7 basic operation timing in interval timer mode ............................................................................... .............245 7-8 flowchart of basic operation in external event count mode................................................................... .....248 7-9 basic operation timing in external event count mode ......................................................................... .......249 7-10 flowchart of basic operation in external trigger pulse output mode ......................................................... .252 7-11 basic operation timing in external trigger pulse output mode ............................................................... ....253 7-12 flowchart of basic operation in one-shot pulse mode ........................................................................ ........255 7-13 timing of basic operation in one-shot pulse mode ........................................................................... ..........256 7-14 flowchart of basic operation in pwm mode ................................................................................... ..............258 7-15 basic operation timing in pwm mode......................................................................................... .................260 7-16 flowchart of basic operation in free-running mode.......................................................................... ..........263 7-17 basic operation timing in free-running mode (tpnccs1 = 0, tpnccs0 = 0)...........................................264 7-18 basic operation timing in free-running mode (tpnccs1 = 1, tpnccs0 = 1)...........................................265 7-19 basic operation timing in free-running mode (tpnccs1 = 1, tpnccs0 = 0)...........................................266 7-20 basic operation timing in free-running mode (tpnccs1 = 0, tpnccs0 = 1)...........................................267 7-21 flowchart of basic operation in pulse width measurement mode............................................................... .268 7-22 basic operation timing in pulse width measurement mode ..................................................................... ...269 8-1 timer q block diagram ....................................................................................................... ..........................271 8-2 flowchart of basic operation for anytime write.............................................................................. ..............283 8-3 timing diagram for anytime write............................................................................................ .....................284 8-4 flowchart of basic operation for reload..................................................................................... ..................285 8-5 timing chart for reload ..................................................................................................... ...........................286 8-6 flowchart of basic operation in interval timer mode......................................................................... ...........287 8-7 basic operation timing in interval timer mode ............................................................................... .............288 8-8 flowchart of basic operation in external event count mode................................................................... .....291 8-9 basic operation timing in external event count mode ......................................................................... .......292 8-10 flowchart of basic operation in external trigger pulse output mode ......................................................... .295 8-11 basic operation timing in external trigger pulse output mode ............................................................... ....296 8-12 flowchart of basic operation in one-shot pulse mode ........................................................................ ........298 8-13 timing of basic operation in one-shot pulse mode ........................................................................... ..........299
preliminary user?s manual u16541ej1v0um 21 list of figures (3/9) figure no. title page 8-14 flowchart of basic operation in pwm mode................................................................................... .............. 301 8-15 basic operation timing in pwm mode ......................................................................................... ................ 303 8-16 flowchart of basic operation in free-running mode .......................................................................... ......... 306 8-17 basic operation timing in free-running mode (tq0ccs3 = 0, tq0ccs2 = 0, tq0ccs1 = 0, tq0ccs0 = 0).................................................................... 308 8-18 basic operation timing in free-running mode (tq0ccs3 = 1, tq0ccs2 = 1, tq0ccs1 = 1, tq0ccs0 = 1).................................................................... 309 8-19 basic operation timing in free-running mode (tq0ccs3 = 1, tq0ccs2 = 1, tq0ccs1 = 1, tq0ccs0 = 0).................................................................... 310 8-20 basic operation timing in free-running mode (tq0ccs3 = 1, tq0ccs2 = 0, tq0ccs1 = 0, tq0ccs0 = 1).................................................................... 311 8-21 flowchart of basic operation in pulse width measurement mode ............................................................... 312 8-22 basic operation timing in pulse width measurement mode ..................................................................... ... 313 9-1 block diagram of tmm........................................................................................................ .......................... 315 10-1 block diagram of rto ....................................................................................................... ........................... 318 10-2 example of operation timing of rto0 (when extr0 bit = 0, byte0 bit = 0) ............................................ 322 11-1 block diagram of watch timer............................................................................................... ....................... 324 11-2 block diagram of prescaler 3............................................................................................... ......................... 325 11-3 operation timing of watch timer/interval timer ............................................................................. ............. 330 11-4 example of generation of watch timer interrupt request signal (intwt) (when interrupt period = 0.5 s)................................................................................................ ..................... 330 12-1 block diagram of watchdog timer 2.......................................................................................... ................... 333 13-1 block diagram of a/d converter ............................................................................................. ...................... 341 13-2 relationship between analog input voltage and a/d conversion results ................................................... 350 13-3 a/d converter basic operation .............................................................................................. ....................... 353 13-4 timing example of continuous select mode operation (ada0s = 01h) ...................................................... 356 13-5 timing example of continuous scan mode operation (ada0s register = 03h) ......................................... 358 13-6 timing example of one-shot select mode operation (ada0s register = 01h) .......................................... 359 13-7 timing example of one-shot scan mode operation (ada0s register = 03h) ............................................ 361 13-8 timing example of continuous select mode operation (when power-fail compare is made: ada0s register = 01h) .................................................................... 362 13-9 timing example of continuous scan mode operation (when power-fail compare is made: ada0s register = 03h) .................................................................... 364 13-10 timing example of one-shot select mode operation (when power-fail compare is made: ada0s register = 01h) .................................................................... 365
preliminary user?s manual u16541ej1v0um 22 list of figures (4/9) figure no. title page 13-11 timing example of one-shot scan mode operation (when power-fail compare is made: ada0s register = 03h) ....................................................................367 13-12 processing of analog input pin ............................................................................................ .........................368 13-13 generation timing of a/d conversion end interrupt request................................................................. ......369 13-14 av ref0 pin processing example........................................................................................................ ............370 13-15 overall error ............................................................................................................. .....................................371 13-16 quantization error ........................................................................................................ .................................372 13-17 zero-scale error .......................................................................................................... ..................................372 13-18 full-scale error.......................................................................................................... ....................................373 13-19 differential linearity error.............................................................................................. ................................373 13-20 integral linearity error .................................................................................................. .................................374 13-21 sampling time............................................................................................................. ..................................374 14-1 block diagram of d/a converter ............................................................................................. ......................375 14-2 external pin connection example ............................................................................................ .....................379 15-1 csib4 and uarta0 mode switch settings...................................................................................... .............380 15-2 uarta2 and i 2 c00 mode switch settings ....................................................................................................381 15-3 uarta1 and i 2 c02 mode switch settings ....................................................................................................382 15-4 block diagram of asynchronous serial interface n ........................................................................... ............385 15-5 uarta transmit/receive data format......................................................................................... ................395 15-6 lin transmission manipulation outline...................................................................................... ...................396 15-7 lin reception manipulation outline ......................................................................................... .....................397 15-8 sbf transmission ........................................................................................................... ..............................398 15-9 sbf reception .............................................................................................................. ................................399 15-10 uart transmission ......................................................................................................... .............................400 15-11 continuous transmission processing flow................................................................................... ................401 15-12 continuous transfer operation timing ...................................................................................... ...................402 15-13 uart reception............................................................................................................ ................................403 15-14 noise filter circuit ...................................................................................................... ...................................406 15-15 configuration of baud rate generator ...................................................................................... ....................407 15-16 allowable baud rate range during reception................................................................................ .............412 15-17 transfer rate during continuous transfer .................................................................................. .................414 16-1 csib4 and uarta0 mode switch settings...................................................................................... .............416 16-2 csib0 and i 2 c01 mode switch settings ....................................................................................................... .417 16-3 block diagram of csib...................................................................................................... ............................419 17-1 uarta2 and i 2 c00 mode switch settings ....................................................................................................445 17-2 csib0 and i 2 c01 mode switch settings ....................................................................................................... .446
preliminary user?s manual u16541ej1v0um 23 list of figures (5/9) figure no. title page 17-3 uarta1 and i 2 c02 mode switch settings .................................................................................................... 447 17-4 block diagram of i 2 c0n ............................................................................................................................ ..... 449 17-5 serial bus configuration example using i 2 c bus.......................................................................................... 450 17-6 pin configuration diagram .................................................................................................. .......................... 468 17-7 i 2 c bus serial data transfer timing.............................................................................................. ................ 469 17-8 start conditions........................................................................................................... .................................. 469 17-9 address .................................................................................................................... ..................................... 470 17-10 transfer direction specification .......................................................................................... .......................... 471 17-11 ack signal ................................................................................................................ .................................... 472 17-12 stop condition............................................................................................................ ................................... 473 17-13 wait signal ............................................................................................................... ..................................... 474 17-14 arbitration timing example ................................................................................................ ........................... 496 17-15 communication reservation timing .......................................................................................... ................... 500 17-16 timing for accepting communication reservations........................................................................... ........... 500 17-17 communication reservation flowchart....................................................................................... .................. 501 17-18 master operation flowchart (1)............................................................................................ ......................... 505 17-19 master operation flowchart (2)............................................................................................ ......................... 506 17-20 slave operation flowchart ................................................................................................. ........................... 507 17-21 example of master to slave communication (when 9-clock wait is selected for both master and slave)...................................................................... .. 509 17-22 example of slave to master communication (when 9-clock wait is selected for both master and slave)...................................................................... .. 512 18-1 iebus transfer signal format ............................................................................................... ........................ 517 18-2 master address field ....................................................................................................... ............................. 518 18-3 slave address field ........................................................................................................ .............................. 519 18-4 control field .............................................................................................................. .................................... 521 18-5 telegraph length field ..................................................................................................... ............................ 523 18-6 data field ................................................................................................................. ..................................... 524 18-7 bit configuration of slave status.......................................................................................... ......................... 527 18-8 configuration of lock address .............................................................................................. ........................ 528 18-9 bit format of iebus ........................................................................................................ ............................... 529 18-10 iebus controller block diagram............................................................................................ ........................ 530 18-11 timing at which mstrq bit cannot be set ................................................................................... .............. 535 18-12 example of broadcast communication flag operation ......................................................................... ....... 541 18-13 timing of underrun error occurrence ....................................................................................... .................... 547 18-14 timing of overrun error occurrence ........................................................................................ ..................... 548 18-15 timing of write error occurrence.......................................................................................... ........................ 549 18-16 interrupt request signal generation timing (for (1), (3), and (4)) ........................................................ ........ 553 18-17 interrupt request signal generation timing (for (2) and (5)).............................................................. .......... 554
preliminary user?s manual u16541ej1v0um 24 list of figures (6/9) figure no. title page 18-18 timing of intie2 and intsta interrupt request signal generation in locked state (for (4) and (5)) .........554 18-19 timing of intie2 and intsta interrupt request signal generation in locked state (for (3))......................555 18-20 configuration of interrupt control block .................................................................................. ......................563 18-21 example of identifying intie1 signal interrupt (when intie1, interr, and intsta signals are used)............................................................................. 564 18-22 example of identifying interr signal interrupt (when intie1, interr, and intsta signals are used)............................................................................. 564 18-23 example of identifying intsta signal interrupt (when intie1, interr, and intsta signals are used)............................................................................. 565 18-24 example of identifying intie1 signal interrupt (when intie1 and intie2 signals are used).....................565 18-25 example of identifying intie2 signal interrupt (when intie1 and intie2 signals are used).....................566 18-26 master transmission ....................................................................................................... ..............................570 18-27 master reception .......................................................................................................... ................................572 18-28 slave transmission ........................................................................................................ ...............................574 18-29 slave reception ........................................................................................................... .................................576 18-30 master transmission (interval of interrupt request signal occurrence)..................................................... ..578 18-31 master reception (interval of interrupt request signal occurrence)........................................................ ....579 18-32 slave transmission (interval of interrupt request signal occurrence)...................................................... ...580 18-33 slave reception (interval of interrupt request signal occurrence)......................................................... .....581 19-1 block diagram of can module ................................................................................................ ......................584 19-2 composition of layers...................................................................................................... .............................585 19-3 data frame................................................................................................................. ...................................586 19-4 remote frame............................................................................................................... ................................587 19-5 start of frame (sof) ....................................................................................................... ..............................587 19-6 arbitration field (in standard format mode) ................................................................................ .................588 19-7 arbitration field (in extended format mode)................................................................................ .................588 19-8 control field .............................................................................................................. ....................................589 19-9 data field ................................................................................................................. .....................................590 19-10 crc field ................................................................................................................. .....................................590 19-11 ack field ................................................................................................................. .....................................591 19-12 end of frame (eof) ........................................................................................................ ..............................591 19-13 interframe space (error active node) ...................................................................................... .....................592 19-14 interframe space (error passive node) ..................................................................................... ...................592 19-15 error frame ............................................................................................................... ....................................594 19-16 overload frame............................................................................................................ .................................595 19-17 nominal bit time (8 to 25 time quanta) .................................................................................... ...................601 19-18 adjusting synchronization of data bit ..................................................................................... ......................602 19-19 bit synchronization....................................................................................................... .................................603 19-20 transmission state transition chart ....................................................................................... ......................604
preliminary user?s manual u16541ej1v0um 25 list of figures (7/9) figure no. title page 19-21 reception state transition chart .......................................................................................... ........................ 605 19-22 error state transition chart .............................................................................................. ............................ 606 19-23 connection to can bus ..................................................................................................... ........................... 607 19-24 can0 module mask 1 registers (c0mask1l, c0mask1h) ........................................................................ 6 35 19-25 can0 module mask 2 registers (c0mask2l, c0mask2h) ........................................................................ 6 35 19-26 can0 module mask 3 registers (c0mask3l, c0mask3h) ........................................................................ 6 35 19-27 can0 module mask 4 registers (c0mask4l, c0mask4h) ........................................................................ 6 36 19-28 can controller clocks ..................................................................................................... ............................. 647 19-29 data bit time............................................................................................................. .................................... 648 19-30 example of bit setting/clearing operations ................................................................................ .................. 663 19-31 16-bit data during write operation........................................................................................ ....................... 664 19-32 transition to can module operational modes................................................................................ .............. 666 19-33 receive history list ...................................................................................................... ................................ 669 19-34 message reception procedure using receive history list .................................................................... ...... 670 19-35 c0rgpt pointer handling with respect to rhpm bit .......................................................................... ........ 671 19-36 message processing example (when pbb bit = 0)............................................................................. ......... 675 19-37 transmit history list..................................................................................................... ................................. 677 19-38 message transmission procedure using transmit history list................................................................ .... 678 19-39 c0tgpt pointer handling with respect to thpm bit.......................................................................... ......... 679 19-40 can module terminal connection in receive-only mode....................................................................... ..... 685 19-41 can module terminal connection in self-test mode.......................................................................... ......... 687 19-42 timing diagram of capture output signal tsout ............................................................................. .......... 688 19-43 c0btr register settings ................................................................................................... ........................... 692 19-44 initialization ............................................................................................................ ....................................... 693 19-45 reinitialization .......................................................................................................... ..................................... 694 19-46 message buffer initialization ............................................................................................. ............................ 695 19-47 message buffer redefinition ............................................................................................... .......................... 696 19-48 transmit preparation (normal mode) ........................................................................................ .................... 697 19-49 transmit preparation (abt mode) ........................................................................................... ..................... 698 19-50 transmission via interrupt (c0lopt)....................................................................................... ..................... 699 19-51 transmission via interrupt (case of c0tgpt) ............................................................................... ............... 700 19-52 transmit software polling ................................................................................................. ............................ 701 19-53 transmission request abort process (normal mode) .......................................................................... ........ 702 19-54 transmission request abort process (abt mode)............................................................................. .......... 703 19-55 reception via interrupt (c0lipt).......................................................................................... ......................... 704 19-56 reception via interrupt (c0rgpt) .......................................................................................... ...................... 705 19-57 receive software polling .................................................................................................. ............................ 706 19-58 setting can sleep/stop mode ............................................................................................... ....................... 707 19-59 clear can sleep/stop mode................................................................................................. ........................ 708 19-60 bus off recovery .......................................................................................................... ................................ 709
preliminary user?s manual u16541ej1v0um 26 list of figures (8/9) figure no. title page 19-61 shutdown process (normal shutdown)........................................................................................ .................710 19-62 shutdown process (forcible shutdown) ...................................................................................... .................711 19-63 error handling ............................................................................................................ ...................................712 19-64 setting cpu standby (from can sleep mode) ................................................................................. ............713 19-65 setting cpu standby (from can stop mode) .................................................................................. .............714 20-1 dmac bus cycle state transition............................................................................................ .....................726 21-1 block diagram of crc register .............................................................................................. ......................732 21-2 crc operation circuit operation example (lsb first) ........................................................................ .........734 21-3 operation circuit configuration (crc data register) ........................................................................ ...........735 21-4 crc operation flow ......................................................................................................... ............................736 21-5 crc transmission example ................................................................................................... ......................737 22-1 non-maskable interrupt request signal acknowledgment operation...........................................................74 2 22-2 servicing configuration of non-maskable interrupt.......................................................................... .............744 22-3 reti instruction processing ................................................................................................ ..........................745 22-4 maskable interrupt servicing ............................................................................................... ..........................749 22-5 reti instruction processing ................................................................................................ ..........................750 22-6 example of processing in which another interrupt request signal is issued while an interrupt is being serviced ........................................................................................... ..................752 22-7 example of servicing interrupt request signals simultaneously generated................................................754 22-8 software exception processing.............................................................................................. .......................766 22-9 reti instruction processing ................................................................................................ ..........................767 22-10 exception trap processing................................................................................................. ...........................770 22-11 restore processing from exception trap.................................................................................... ..................770 22-12 debug trap processing format .............................................................................................. ......................771 22-13 processing format of restoration from debug trap .......................................................................... ...........772 22-14 pipeline operation at interrupt request signal acknowledgment (outline) ..................................................7 73 23-1 key return block diagram ................................................................................................... .........................775 24-1 status transition.......................................................................................................... ..................................778 24-2 status transition (during subclock operation) .............................................................................. ...............779 25-1 timing of reset operation by reset pin input............................................................................... .............797 25-2 timing of power-on reset operation ......................................................................................... ...................797 25-3 timing of reset operation by wdt2res signal generation..................................................................... ...799 25-4 timing of reset operation by low-voltage detector .......................................................................... ..........801 25-5 when oscillation of main clock is stopped.................................................................................. .................805
preliminary user?s manual u16541ej1v0um 27 list of figures (9/9) figure no. title page 25-6 operation in software stop mode and after software stop mode is released........................................ 806 25-7 operation when main clock is stopped ....................................................................................... ................ 806 26-1 regulator.................................................................................................................. ..................................... 807 26-2 regc pin connection (regc = capacity)...................................................................................... ............. 808 27-1 block diagram of rom correction ............................................................................................ .................... 809 27-2 rom correction operation and program flow .................................................................................. ........... 813 28-1 environment required for writing programs to flash memory .................................................................. ... 816 28-2 communication with dedicated flash programmer (uarta0)..................................................................... 817 28-3 communication with dedicated flash programmer (csib0) ...................................................................... .. 817 28-4 communication with dedicated flash programmer (csib0 + hs)................................................................ 818 28-5 flmd0 pin connection example ............................................................................................... ................... 819 28-6 flmd1 pin connection example ............................................................................................... ................... 820 28-7 conflict of signals (serial interface input pin)........................................................................... .................... 821 28-8 malfunction of other device ................................................................................................ .......................... 822 28-9 conflict of signals (reset pin) ............................................................................................ ........................ 823 28-10 procedure for manipulating flash memory ................................................................................... ................ 824 28-11 flash memory programming mode ............................................................................................. .................. 825 28-12 communication command ..................................................................................................... ....................... 827
preliminary user?s manual u16541ej1v0um 28 list of tables (1/4) table no. title page 1-1 v850es/sg2 product list ..................................................................................................... ..........................33 2-1 pin i/o buffer power supplies ............................................................................................... ..........................48 2-2 pin operation states in various modes....................................................................................... ....................55 3-1 program registers........................................................................................................... ................................72 3-2 system register numbers..................................................................................................... ..........................73 3-3 interrupt/exception table ................................................................................................... .............................88 4-1 i/o buffer power supplies for pins .......................................................................................... ......................114 4-2 port configuration.......................................................................................................... ................................115 4-3 port 0 alternate-function pins.............................................................................................. .........................116 4-4 valid edge specification.................................................................................................... ............................120 4-5 port 1 alternate-function pins.............................................................................................. .........................121 4-6 port 3 alternate-function pins.............................................................................................. .........................123 4-7 valid edge specification.................................................................................................... ............................130 4-8 port 4 alternate-function pins.............................................................................................. .........................131 4-9 port 0 alternate-function pins.............................................................................................. .........................135 4-10 port 7 alternate-function pins............................................................................................. ..........................140 4-11 port 9 alternate-function pins............................................................................................. ..........................143 4-12 valid edge specification................................................................................................... .............................152 4-13 port cm alternate-function pins ............................................................................................ .......................153 4-14 port ct alternate-function pins............................................................................................ ........................156 4-15 port dh alternate-function pins ............................................................................................ .......................159 4-16 port dl alternate-function pins ............................................................................................ ........................162 4-17 using port pin as alternate-function pin ................................................................................... ...................166 5-1 bus control pins (multiplexed bus) .......................................................................................... .....................178 5-2 external control pins (separate bus)........................................................................................ ....................178 5-3 pin status when internal rom, internal ram, or on-chip peripheral i/o is accessed ...............................178 5-4 bus priority ................................................................................................................ ....................................195 6-1 operation status of each clock .............................................................................................. ......................222 7-1 configuration of tmp0 to tmp5 ............................................................................................... .....................229 8-1 tmq configuration ........................................................................................................... .............................271 9-1 configuration of tmm ........................................................................................................ ............................315
preliminary user?s manual u16541ej1v0um 29 list of tables (2/4) table no. title page 10-1 configuration of rto ....................................................................................................... ............................. 319 10-2 operation during manipulation of real-time output buffer register 0 ........................................................ 319 10-3 operation modes and output triggers of real-time output port ............................................................... .. 321 11-1 interval time of interval timer............................................................................................ ........................... 325 11-2 configuration of watch timer............................................................................................... ......................... 326 11-3 interval time of interval timer............................................................................................ ........................... 329 12-1 configuration of watchdog timer 2.......................................................................................... ..................... 334 12-2 watchdog timer 2 clock selection ........................................................................................... .................... 336 13-1 configuration of a/d converter ............................................................................................. ........................ 342 13-2 normal conversion mode setting examples.................................................................................... ............. 346 13-3 high-speed conversion mode setting examples ................................................................................ ......... 346 14-1 configuration of d/a converter ............................................................................................. ........................ 376 15-1 interrupts and their default priorities.................................................................................... ........................ 393 15-2 baud rate generator setting data ........................................................................................... .................... 411 15-3 maximum/minimum allowable baud rate error .................................................................................. .......... 413 16-1 configuration of csib...................................................................................................... .............................. 418 17-1 configuration of i 2 c0n ............................................................................................................................ ....... 451 17-2 clock settings ............................................................................................................. .................................. 465 17-3 intiicn generation timing and wait control................................................................................. ............... 494 17-4 extension code bit definitions ............................................................................................. ......................... 495 17-5 status during arbitration and interrupt request signal generation timing.................................................. 4 97 17-6 wait periods ............................................................................................................... ................................... 499 17-7 wait periods ............................................................................................................... ................................... 502 18-1 transfer rate and maximum number of transfer bytes in each communication mode .............................. 516 18-2 contents of control bits ................................................................................................... ............................. 520 18-3 control field for locked slave unit........................................................................................ ....................... 521 18-4 control field for unlocked slave unit ...................................................................................... ..................... 521 18-5 acknowledge signal output condition of control field....................................................................... .......... 522 18-6 contents of telegraph length bit........................................................................................... ....................... 523 18-7 lock setting conditions .................................................................................................... ............................ 529 18-8 unlock release conditions (while locked) ................................................................................... ............... 529 18-9 control registers of iebus controller ...................................................................................... ..................... 532
preliminary user?s manual u16541ej1v0um 30 list of tables (3/4) table no. title page 18-10 timing of setting eniebus bit and participation in communication .......................................................... ..534 18-11 registers that are not reset by eniebus bit ............................................................................... ..............534 18-12 registers that must be set before each communication ...................................................................... ......534 18-13 slave request condition (slvrq bit setting condition) ..................................................................... .........540 18-14 operation if parity does not match ........................................................................................ .......................546 18-15 field status.............................................................................................................. ......................................558 18-16 interrupt request signal generation source list ........................................................................... ...............563 18-17 interrupt source list ..................................................................................................... .................................567 18-18 communication error source processing list................................................................................ ...............568 19-1 overview of functions ...................................................................................................... .............................583 19-2 frame types ................................................................................................................ .................................586 19-3 rtr frame settings......................................................................................................... .............................588 19-4 frame format setting (ide bit) and number of identifier (id) bits.......................................................... ......588 19-5 data length code settings .................................................................................................. .........................589 19-6 operation in error status.................................................................................................. .............................593 19-7 operation when third bit of intermission is dominant level................................................................. .......593 19-8 definition of each field................................................................................................... ...............................594 19-9 field definition of overload frame......................................................................................... .......................595 19-10 arbitration ............................................................................................................... .......................................596 19-11 bit stuffing .............................................................................................................. .......................................597 19-12 error types............................................................................................................... .....................................598 19-13 output timing of error frame.............................................................................................. ..........................598 19-14 types of error............................................................................................................ ....................................599 19-15 error counter............................................................................................................. ....................................600 19-16 segment name and segment length ........................................................................................... ................601 19-17 list of can controller registers.......................................................................................... ..........................608 19-18 control register access types ............................................................................................. ........................609 19-19 message buffer register access types...................................................................................... ..................610 19-20 control bits of control registers ......................................................................................... ..........................626 19-21 control bits of message buffers ........................................................................................... .........................628 19-22 minimum configuration of message buffer even when unused in application ............................................665 19-23 list of can module interrupt sources ...................................................................................... .....................684 20-1 dma start factor........................................................................................................... ................................723 20-2 relationship with transfer object.......................................................................................... ........................728 20-3 external bus cycles during dma transfer (two-cycle transfer)............................................................... ..728 21-1 crc configuration .......................................................................................................... ..............................732
preliminary user?s manual u16541ej1v0um 31 list of tables (4/4) table no. title page 22-1 interrupt source list ...................................................................................................... ................................ 739 22-2 nmi valid edge specification ............................................................................................... ......................... 747 22-3 interrupt control register (xxicn) ......................................................................................... ........................ 756 22-4 valid edge specification ................................................................................................... ............................ 762 22-5 valid edge specification ................................................................................................... ............................ 763 22-6 valid edge specification ................................................................................................... ............................ 764 23-1 assignment of key return detection pins .................................................................................... ................ 775 24-1 standby modes .............................................................................................................. ............................... 777 24-2 operation after releasing halt mode by interrupt request signal ............................................................ 780 24-3 operation status in halt mode .............................................................................................. ..................... 781 24-4 operation after releasing idle1 mode by interrupt request signal ........................................................... 783 24-5 operation status in idle1 mode............................................................................................. ...................... 783 24-6 operation after releasing idle2 mode by interrupt request signal ........................................................... 785 24-7 operation status in idle2 mode............................................................................................. ...................... 785 24-8 operation after releasing software stop mode by interrupt request signal............................................. 788 24-9 operation status in software stop mode..................................................................................... ............... 788 24-10 operation status in subclock operation mode ............................................................................... .............. 791 24-11 operation after releasing sub-idle mode by interrupt request signal ...................................................... 7 93 24-12 operation status in sub-idle mode ......................................................................................... .................... 793 25-1 hardware status on reset pin input ......................................................................................... ................. 796 25-2 hardware statuses during wst2res signal generation ......................................................................... ... 798 25-3 hardware statuses during reset operation by low-voltage detector......................................................... 80 0 25-4 operation status of clock monitor (clm.clme bit = 1, with ring-osc operating)..................................... 804 27-1 correspondence between corcn register bits and coradn registers .................................................. 811 28-1 signal generation of dedicated flash programmer (pg-fp4) ................................................................... .. 818 28-2 relationship of operation mode of flmd0 and flmd1 pins ..................................................................... .. 820 28-3 pins used by serial interfaces ............................................................................................. ......................... 821 28-4 list of communication modes ................................................................................................ ....................... 826 28-5 flash memory control command............................................................................................... ................... 827 28-6 response commands.......................................................................................................... ......................... 827
preliminary user?s manual u16541ej1v0um 32 chapter 1 introduction the v850es/sg2 is one of the products in the nec electronics v850 series tm of single-chip microcontrollers designed for low-power operation for real-time control applications. 1.1 general the v850es/sg2 is a 32-bit single-chip microcontroller that includes the v850es cpu core and peripheral functions such as rom/ram, a timer/counter, serial interfaces, an a/d converter, and a d/a converter. some models of the v850es/sg2 are provided with iebus ? (inter equipment bus ? ) or can (control area network) as an automotive lan. in addition to high real-time response characteristics and 1-clock-pitch basic instructions, the v850es/sg2 features multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware multiplier, as optimum instructions for digital servo control applications. moreover, as a real-time control system, the v850es/sg2 enables an extremely high cost-performance for applications that require a low power consumption, such as audio and car audio. table 1-1 lists the products of the v850es/sg2.
chapter 1 introduction preliminary user?s manual u16541ej1v0um 33 table 1-1. v850es/sg2 product list rom maskable interrupts function part number ty p e s i z e ram size i 2 ciebuscan external internal non-maskable interrupts pd703260 none pd703260y 256 kb 24 kb on-chip pd703261 none pd703261y mask rom on-chip pd70f3261 none pd70f3261y flash memory 384 kb 32 kb on-chip pd703262 none pd703262y 512 kb 40 kb on-chip pd703263 none pd703263y mask rom on-chip pd70f3263 none pd70f3263y flash memory 640 kb 48 kb on-chip none 47 pd703270 none pd703270y 256 kb 24 kb on-chip pd703271 none pd703271y mask rom on-chip pd70f3271 none pd70f3271y flash memory 384 kb 32 kb on-chip pd703272 none pd703272y 512 kb 40 kb on-chip pd703273 none pd703273y mask rom on-chip pd70f3273 none pd70f3273y flash memory 640 kb 48 kb on-chip on-chip none 51 pd703280 none pd703280y 256 kb 24 kb on-chip pd703281 none pd703281y mask rom on-chip pd70f3281 none pd70f3281y flash memory 384 kb 32 kb on-chip pd703282 none pd703282y 512 kb 40 kb on-chip pd703283 none pd703283y mask rom on-chip pd70f3283 none pd70f3283y flash memory 640 kb 48 kb on-chip none on-chip 8 51 2 remark the part numbers of the v850es/sg2 are shown as follows in this manual.
chapter 1 introduction preliminary user?s manual u16541ej1v0um 34 ? mask rom version pd703260, 703260y, 703261, 703261y, 703262, 703262y, 703263, 703263y, 703270, 703270y, 703271, 703271y, 703272, 703272y, 703273, 703273y, 703280, 703280y, 703281, 703281y, 703282, 703282y, 703283, 703283y ? flash memory version pd70f3261, 70f3261y, 70f3263, 70f3263y, 70f3271, 70f3271y, 70f3273, 70f3273y, 70f3281, 70f3281y, 70f3283, 70f3283y ? i 2 c bus version (y version) pd703260y, 703261y, 703262y, 703263y, 703270y, 703271y, 703272y, 703273y, 703280y, 703281y, 703282y, 703283y, 70f3261y, 70f3263y, 70f3271y, 70f3273y, 70f3281y, 70f3283y ? general-purpose version pd703260, 703260y, 703261, 703261y, 703262, 703262y, 703263, 703263y, 70f3261, 70f3261y, 70f3263, 70f3263y ? iebus controller version pd703270, 703270y, 703271, 703271y, 703272, 703272y, 703273, 703273y, 70f3271, 70f3271y, 70f3273, 70f3273y ? can controller version pd703280, 703280y, 703281, 703281y, 703282, 703282y, 703283, 703283y, 70f3281, 70f3281y, 70f3283, 70f3283y
chapter 1 introduction preliminary user?s manual u16541ej1v0um 35 1.2 features { number of instructions: 83 { minimum instruction execution time: 50 ns (operating with main clock (f xx ) of 20 mhz) { general-purpose registers: 32 bits 32 registers { instruction set: signed multiplication (16 16 32): 1 to 2 clocks signed multiplication (32 32 64): 1 to 5 clocks saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space: 64 mb of linear address space (for programs and data) external expansion: up to 16 mb (including 1 mb used as internal rom/ram) programmable wait function idle state insertion function { external bus interface: separate bus/multiplexed bus output selectable 8/16 bit data bus sizing function wait function ? programmable wait function ? external wait function idle state function bus hold function { internal memory: ram: 24/32/40/48 kb (see table 1-1 ) mask rom: 256/384/512/640 kb (see table 1-1 ) flash memory: 384/640 kb (see table 1-1 ) { interrupts and exceptions: non-maskable interrupts: 2 sources maskable interrupts: 55/59 sources (see table 1-1 ) software exceptions: 32 sources exception trap: 2 sources { i/o lines: i/o ports: 84 { timer/counter: 16-bit interval timer m (tmm): 1 channel 16-bit timer/event counter p (tmp): 6 channels 16-bit timer/event counter q (tmq): 1 channel { real-time output port: 6 bits 1 channel { watch timer: 1 channel { watchdog timer: 1 channel { serial interface (sio): asynchronous serial interface a (uarta) 3-wire variable-length serial interface b (csib) i 2 c bus interface (i 2 c) uarta/csib: 1 channel uarta/i 2 c: 2 channels csib/i 2 c: 1 channel csib: 3 channels { iebus controller: 1 channel (iebus controller version only) { can controller: 1 channel (can controller version only) { a/d converter: 10-bit resolution: 12 channels { d/a converter: 8-bit resolution: 2 channels { dma controller: 4 channels
chapter 1 introduction preliminary user?s manual u16541ej1v0um 36 { rom correction: 4 correction addresses specifiable { clock generator: during main clock or subclock operation 7-level cpu clock (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable { ring-osc: 200 khz (typ.) { power-save functions: halt/idle1/idle2/software stop/subclock/sub-idle mode { package: 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 1.3 application fields audio, car audio
chapter 1 introduction preliminary user?s manual u16541ej1v0um 37 1.4 ordering information part number package internal rom pd703260gf-xxx-3ba pd703260gc-xxx-8eu pd703260ygf-xxx-3ba pd703260ygc-xxx-8eu pd703261gf-xxx-3ba pd703261gc-xxx-8eu pd703261ygf-xxx-3ba pd703261ygc-xxx-8eu pd703262gf-xxx-3ba pd703262gc-xxx-8eu pd703262ygf-xxx-3ba pd703262ygc-xxx-8eu pd703263gf-xxx-3ba pd703263gc-xxx-8eu pd703263ygf-xxx-3ba pd703263ygc-xxx-8eu pd703270gf-xxx-3ba pd703270gc-xxx-8eu pd703270ygf-xxx-3ba pd703270ygc-xxx-8eu pd703271gf-xxx-3ba pd703271gc-xxx-8eu pd703271ygf-xxx-3ba pd703271ygc-xxx-8eu pd703272gf-xxx-3ba pd703272gc-xxx-8eu pd703272ygf-xxx-3ba pd703272ygc-xxx-8eu pd703273gf-xxx-3ba pd703273gc-xxx-8eu pd703273ygf-xxx-3ba pd703273ygc-xxx-8eu pd703280gf-xxx-3ba pd703280gc-xxx-8eu pd703280ygf-xxx-3ba pd703280ygc-xxx-8eu pd703281gf-xxx-3ba pd703281gc-xxx-8eu 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 256 kb (mask rom) 256 kb (mask rom) 256 kb (mask rom) 256 kb (mask rom) 384 kb (mask rom) 384 kb (mask rom) 384 kb (mask rom) 384 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 256 kb (mask rom) 256 kb (mask rom) 256 kb (mask rom) 256 kb (mask rom) 384 kb (mask rom) 384 kb (mask rom) 384 kb (mask rom) 384 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 256 kb (mask rom) 256 kb (mask rom) 256 kb (mask rom) 256 kb (mask rom) 384 kb (mask rom) 384 kb (mask rom) remark xxx indicates rom code suffix.
chapter 1 introduction preliminary user?s manual u16541ej1v0um 38 part number package internal rom pd703281ygf-xxx-3ba pd703281ygc-xxx-8eu pd703282gf-xxx-3ba pd703282gc-xxx-8eu pd703282ygf-xxx-3ba pd703282ygc-xxx-8eu pd703283gf-xxx-3ba pd703283gc-xxx-8eu pd703283ygf-xxx-3ba pd703283ygc-xxx-8eu pd70f3261gf-3ba pd70f3261gc-8eu pd70f3261ygf-3ba pd70f3261ygc-8eu pd70f3263gf-3ba pd70f3263gc-8eu pd70f3263ygf-3ba pd70f3263ygc-8eu pd70f3271gf-3ba pd70f3271gc-8eu pd70f3271ygf-3ba pd70f3271ygc-8eu pd70f3273gf-3ba pd70f3273gc-8eu pd70f3273ygf-3ba pd70f3273ygc-8eu pd70f3281gf-3ba pd70f3281gc-8eu pd70f3281ygf-3ba pd70f3281ygc-8eu pd70f3283gf-3ba pd70f3283gc-8eu pd70f3283ygf-3ba pd70f3283ygc-8eu 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 100-pin plastic qfp (14 20) 100-pin plastic lqfp (fine pitch) (14 14) 384 kb (mask rom) 384 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 384 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) remark xxx indicates rom code suffix.
chapter 1 introduction preliminary user?s manual u16541ej1v0um 39 1.5 pin configuration (top view) 100-pin plastic qfp (14 20) pd703260gf-xxx-3ba pd703270gf-xxx-3ba pd703280gf-xxx-3ba pd703260ygf-xxx-3ba pd703270ygf-xxx-3ba pd703280ygf-xxx-3ba pd703261gf-xxx-3ba pd703271gf-xxx-3ba pd703281gf-xxx-3ba pd703261ygf-xxx-3ba pd703271ygf-xxx-3ba pd703281ygf-xxx-3ba pd703262gf-xxx-3ba pd703272gf-xxx-3ba pd703282gf-xxx-3ba pd703262ygf-xxx-3ba pd703272ygf-xxx-3ba pd703282ygf-xxx-3ba pd703263gf-xxx-3ba pd703273gf-xxx-3ba pd703283gf-xxx-3ba pd703263ygf-xxx-3ba pd703273ygf-xxx-3ba pd703283ygf-xxx-3ba pd70f3261gf-3ba pd70f3271gf-3ba pd70f3281gf-3ba pd70f3261ygf-3ba pd70f3271ygf-3ba pd70f3281ygf-3ba pd70f3263gf-3ba pd70f3273gf-3ba pd70f3283gf-3ba pd70f3263ygf-3ba pd70f3273ygf-3ba pd70f3283ygf-3ba
chapter 1 introduction preliminary user?s manual u16541ej1v0um 40 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p34/tip10/top10 p35/tip11/top11 p36/ctxd0 note 3 /ietx0 note 4 p37/crxd0 note 3 /ierx0 note 4 ev ss ev dd p38/txda2/sda00 note 2 p39/rxda2/scl00 note 2 p50/tiq01/kr0/toq01/rtp00 p51/tiq02/kr1/toq02/rtp01 p52/tiq03/kr2/toq03/rtp02/ddi note 5 p53/sib2/kr3/tiq00/toq00/rtp03/ddo note 5 p54/sob2/kr4/rtp04/dck note 5 p55/sckb2/kr5/rtp05/dms note 5 p90/a0/kr6/txda1/sda02 note 2 p91/a1/kr7/rxda1/scl02 note 2 p92/a2/tip41/top41 p93/a3/tip40/top40 p94/a4/tip31/top31 p95/a5/tip30/top30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 note 1 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct6/astb pct4/rd pct1/wr1 pct0/wr0 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pdh3/a19 pdh2/a18 p915/a15/intp6/tip50/top50 p914/a14/intp5/tip51/top51 p913/a13/intp4 p912/a12/sckb3 p911/a11/sob3 p910/a10/sib3 p99/a9/sckb1 p98/a8/sob1 p97/a7/sib1/tip20/top20 p96/a6/tip21/top21 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p71/ani1 p70/ani0 av ref0 av ss p10/ano0 p11/ano1 av ref1 pdh4/a20 pdh5/a21 ic note 1 /flmd0 note 1 v dd regc v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst note 5 p06/intp3 p40/sib0/sda01 note 2 p41/sob0/scl01 note 2 p42/sckb0 p30/txda0/sob4 p31/rxda0/intp7/sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01 notes 1. ic: directly connect this pin to v ss (mask rom version only). flmd0, flmd1: connect these pins to v ss in the normal mode (flash memory version only). 2. scl00 to scl02 and sda00 to sda02 are valid only in the i 2 c bus version (y version). 3. ctxd0 and crxd0 are valid only in the can controller version. 4. ietx0 and ierx0 are valid only in the iebus controller version. 5. drst, ddi, ddo, dck, and dms are valid only in the flash memory version.
chapter 1 introduction preliminary user ? s manual u16541ej1v0um 41 100-pin plastic lqfp (fine pitch) (14 14) pd703260gc-xxx-8eu pd703270gc-xxx-8eu pd703280gc-xxx-8eu pd703260ygc-xxx-8eu pd703270ygc-xxx-8eu pd703280ygc-xxx-8eu pd703261gc-xxx-8eu pd703271gc-xxx-8eu pd703281gc-xxx-8eu pd703261ygc-xxx-8eu pd703271ygc-xxx-8eu pd703281ygc-xxx-8eu pd703262gc-xxx-8eu pd703272gc-xxx-8eu pd703282gc-xxx-8eu pd703262ygc-xxx-8eu pd703272ygc-xxx-8eu pd703282ygc-xxx-8eu pd703263gc-xxx-8eu pd703273gc-xxx-8eu pd703283gc-xxx-8eu pd703263ygc-xxx-8eu pd703273ygc-xxx-8eu pd703283ygc-xxx-8eu pd70f3261gc-8eu pd70f3271gc-8eu pd70f3281gc-8eu pd70f3261ygc-8eu pd70f3271ygc-8eu pd70f3281ygc-8eu pd70f3263gc-8eu pd70f3273gc-8eu pd70f3283gc-8eu pd70f3263ygc-8eu pd70f3273ygc-8eu pd70f3283ygc-8eu
chapter 1 introduction preliminary user ? s manual u16541ej1v0um 42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 p78/ani8 p79/ani9 p710/ani10 p711/ani11 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 note 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p31/rxda0/intp7/sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01 p34/tip10/top10 p35/tip11/top11 p36/ctxd0 note 3 /ietx0 note 4 p37/crxd0 note 3 /ierx0 note 4 ev ss ev dd p38/txda2/sda00 note 2 p39/rxda2/scl00 note 2 p50/tiq01/kr0/toq01/rtp00 p51/tiq02/kr1/toq02/rtp01 p52/tiq03/kr2/toq03/rtp02/ddi note 5 p53/sib2/kr3/tiq00/toq00/rtp03/ddo note 5 p54/sob2/kr4/rtp04/dck note 5 p55/sckb2/kr5/rtp05/dms note 5 p90/a0/kr6/txda1/sda02 note 2 p91/a1/kr7/rxda1/scl02 note 2 p92/a2/tip41/top41 p93/a3/tip40/top40 p94/a4/tip31/top31 p95/a5/tip30/top30 p96/a6/tip21/top21 p97/a7/sib1/tip20/top20 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 pdl4/ad4 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct6/astb pct4/rd pct1/wr1 pct0/wr0 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pdh3/a19 pdh2/a18 p915/a15/intp6/tip50/top50 p914/a14/intp5/tip51/top51 p913/a13/intp4 p912/a12/sckb3 p911/a11/sob3 p910/a10/sib3 p99/a9/sckb1 p98/a8/sob1 av ref0 av ss p10/ano0 p11/ano1 av ref1 pdh4/a20 pdh5/a21 ic note 1 /flmd0 note 1 v dd regc v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst note 5 p06/intp3 p40/sib0/sda01 note 2 p41/sob0/scl01 note 2 p42/sckb0 p30/txda0/sob4 notes 1. ic: directly connect this pin to v ss (mask rom version only). flmd0, flmd1: connect these pins to v ss in the normal mode (flash memory version only). 2. scl00 to scl02 and sda00 to sda02 are valid only in the i 2 c bus version (y version). 3. ctxd0 and crxd0 are valid only in the can controller version. 4. ietx0 and ierx0 are valid only in the iebus controller version. 5. drst, ddi, ddo, dck, and dms are valid only in the flash memory version.
chapter 1 introduction preliminary user ? s manual u16541ej1v0um 43 pin names a0 to a21: ad0 to ad15: adtrg: ani0 to ani11: ano0, ano1: ascka0: astb: av ref0 , av ref1 : av ss : bv dd : bv ss : clkout: crxd0: ctxd0: dck: ddi: ddo: dms: drst: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: ic: ierx0: ietx0: intp0 to intp7: kr0 to kr7: nmi: p02 to p06: p10, p11: p30 to p39: p40 to p42: p50 to p55: p70 to p711: p90 to p915: address bus address/data bus a/d trigger input analog input analog output asynchronous serial clock address strobe analog reference voltage analog v ss power supply for bus interface ground for bus interface clock output can receive data can transmit data debug clock debug data input debug data output debug mode select debug reset power supply for port ground for port flash programming mode hold acknowledge hold request internally connected iebus receive data iebus transmit data interrupt request from peripherals key return non-maskable interrupt request port 0 port 1 port 3 port 4 port 5 port 7 port 9 pcm0 to pcm3: pct0, pct1, pct4, pct6: pdh0 to pdh5: pdl0 to pdl15: rd: regc: reset: rtp00 to rtp05: rxda0 to rxda2: sckb0 to sckb4: scl00 to scl02: sda00 to sda02: sib0 to sib4: sob0 to sob4: tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51, tiq00 to tiq03: top00, top01, top10, top11, top20, top21, top30, top31, top40, top41, top50, top51, toq00 to toq03: txda0 to txda2: v dd : v ss : wait: wr0: wr1: x1, x2: xt1, xt2: port cm port ct port dh port dl read strobe regulator control reset real-time output port receive data serial clock serial clock serial data serial input serial output timer input timer output transmit data power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock
chapter 1 introduction preliminary user ? s manual u16541ej1v0um 44 1.6 function block configuration 1.6.1 internal block diagram nmi toq00 to toq03 sio tiq00 to tiq03 rtp00 to rtp05 sob0/sda01 note 3 sib0/scl01 note 3 sckb0 intp0 to intp7 intc 16-bit timer/ counter q: 1 ch top00 to top50, top01 to top51 tip00 to tip50, tip01 to tip51 16-bit timer/ counter p: 6 ch kr0 to kr7 rto iebus note 5 csib1 dmac watchdog timer 2 watch timer key return function note 1 note 2 ram rom pc general-purpose registers 32 bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 a0 to a21 ad0 to ad15 ic note 4 flmd0 note 4 flmd1 note 4 ports cg rg regulator pll ring-osc pcm0 to pcm3 pct0, pct1, pct4, pct6 pdh0 to pdh5 pdl0 to pdl15 p90 to p915 p70 to p711 p50 to p55 p40 to p42 p30 to p39 p10, p11 p02 to p06 av ref1 ano0, ano1 ani0 to ani11 av ss av ref0 adtrg clkout xt1 xt2 x1 x2 v dd v ss regc bv dd bv ss ev dd ev ss instruction queue bcu sob1 sib1 sckb1 csib2 sob2 sib2 sckb2 csib3 sob3 sib3 sckb3 txda0/sob4 rxda0/sib4 ascka0/sckb4 txda2/sda00 note 3 rxda2/scl00 note 3 ietx0 ierx0 csib0 iic01 rom correction 16-bit interval timer m: 1 ch uarta0 csib4 uarta2 iic00 txda1/sda02 note 3 rxda1/scl02 note 3 uarta1 iic02 on-chip debug function drst note 7 dms note 7 ddi note 7 dck note 7 ddo note 7 a/d converter d/a converter can0 note 6 ctxd0 crxd0 reset notes 1. 256/384/512/640 kb (mask rom) (see table 1-1 ) 384/640 kb (flash memory) (see table 1-1 ) 2. 24/32/40/48 kb (see table 1-1 ) 3. i 2 c bus version (y version) only 4. ic: mask rom version only flmd0, flmd1: flash memory version 5. iebus controller version only 6. can controller version only 7. flash memory version only
chapter 1 introduction preliminary user ? s manual u16541ej1v0um 45 1.6.2 internal units (1) cpu the cpu uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) contribute to faster processing of complex instructions. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtained by the cpu. when an instruction is fetched from external memory space and the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the prefetched instruction code is stored in an instruction queue. (3) rom this is a 640/512/384/256 kb mask rom or flash memory mapped to addresses 0000000h to 009ffffh/0000000h to 007ffffh/0000000h to 005ffffh/0000000h to 003ffffh. it can be accessed from the cpu in one clock during instruction fetch. (4) ram this is a 48/40/32/24 kb ram mapped to addresses 3ff3000h to 3ffefffh/3ff5000h to 3ffefffh/3ff7000h to 3ffefffh/3ff9000h to 3ffefffh. it can be accessed from the cpu in one clock during data access. (5) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp7) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed for interrupt sources. (6) clock generator (cg) the clock generator includes two types of oscillators: one for the main clock (f xx ) and one for the subclock (f x ). it generates seven types of clocks (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ), and supplies one of them as the operating clock for the cpu (f cpu ). (7) ring-osc a ring oscillator (ring-osc) is provided on chip. the oscillation frequency is 200 khz (typ.). ring-osc supplies the clock for watchdog timer 2 and timer m. (8) timer/counter six-channel 16-bit timer/event counter p (tmp), one-channel 16-bit timer/event counter q (tmq), and one- channel 16-bit interval timer m (tmm), are provided on chip. (9) watch timer this timer counts the reference time period (0.5 s) for counting the clock (the 32.768 khz from the subclock or the 32.768 khz f brg from prescaler 3). the watch timer can also be used as an interval timer for the main clock.
chapter 1 introduction preliminary user ? s manual u16541ej1v0um 46 (10) watchdog timer 2 a watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. either the ring-osc, the main clock, or the subclock can be selected as the source clock. watchdog timer 2 generates a non-maskable interrupt request signal (intwdt2) or a system reset signal (wdt2res) after an overflow occurs. (11) serial interface (sio) the v850es/sg2 includes three kinds of serial interfaces: asynchronous serial interface a (uarta), 3-wire variable-length serial interface b (csib), and an i 2 c bus interface (i 2 c). these interfaces which can use up to seven channels at the same time. one of these channels is switchable between uarta and csib, another two channels are switchable between uarta and i 2 c, and another one is switchable between csib and i 2 c. in the case of uarta, data is transferred via the txda0 to txda2 pins and rxda0 to rxda2 pins. in the case of csib, data is transferred via the sob0 to sob4 pins, sib0 to sib4 pins, and sckb0 to sckb4 pins. in the case of i 2 c, data is transferred via the sda00 to sda02 and scl00 to scl02 pins. a dedicated baud rate generator is provided on chip for uarta. (12) iebus controller the iebus controller is a small-scale digital data transmission system for transferring data between units. the iebus controller is provided only in the iebus controller version (see table 1-1 ). (13) can controller the can controller is a small-scale digital data transmission system for transferring data between units. the can controller is provided only in the can controller version (see table 1-1 ). (14) a/d converter this high-speed, high-resolution 10-bit a/d converter includes 12 analog input pins. conversion is performed using the successive approximation method. (15) d/a converter a two-channel, 8-bit-resolution d/a converter that uses the r-2r ladder method is provided on chip. (16) dma controller a 4-channel dma controller is provided on chip. this controller transfers data between the internal ram and on-chip peripheral i/o devices in response to interrupt requests sent by on-chip peripheral i/o. (17) rom correction a rom correction function that replaces part of a program in the mask rom with a program in the internal ram is provided. up to four correction addresses can be specified. (18) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to key input pins (8 channels).
chapter 1 introduction preliminary user ? s manual u16541ej1v0um 47 (19) real-time output function the real-time output function transfers preset 6-bit data to output latches upon the occurrence of an external trigger signal or a timer compare register match signal. (20) crc function a crc operation circuit that generates 16-bit crc (cyclic redundancy check) code upon setting of 8-bit data is provided on chip. (21) on-chip debug function an on-chip debug function via an n-wire-type in-circuit emulator that uses the jtag (joint test action group) communication specifications is provided. switching between the normal port function and on-chip debugging function is done with the control pin input level and the on-chip d ebug m ode setting register (ocdm). on-chip debug function is provided only in the flash memory version. (22) port there are general-purpose port functions and control pin functions, as listed below. port i/o port function control function p0 5-bit i/o nmi, external interrupt, a/d converter trigger, debug reset p1 2-bit i/o d/a converter analog output p3 10-bit i/o external interrupt, serial interface, timer i/o, can data i/o, iebus data i/o p4 3-bit i/o serial interface p5 6-bit i/o timer i/o, real-time output, key interrupt input, serial interface p7 12-bit i/o a/d converter analog input p9 16-bit i/o external address bus, serial interface, key interrupt input, timer i/o, external interrupt pcm 4-bit i/o external bus interface pct 4-bit i/o external bus interface pdh 6-bit i/o external address bus pdl 16-bit i/o general- purpose port external address/data bus
preliminary user?s manual u16541ej1v0um 48 chapter 2 pin functions 2.1 list of pin functions the names and functions of the pins of the v850es/sg2 pin are described below. there are three types of pin i/o buffer power supplies: av ref0 , av ref1 , bv dd , and ev dd . the relationship between these power supplies and the pins is described below. table 2-1. pin i/o buffer power supplies power supply corresponding pin av ref0 port 7 av ref1 port 1 bv dd port cm, port ct, port dh (bits 0 to 3), port dl ev dd port 0, port 3, port 4, port 5, port 9, port dh (bits 4, 5), reset (1) port pins (1/3) pin name i/o function alternate function p02 nmi p03 intp0/adtrg p04 intp1 p05 intp2/drst note 1 p06 i/o port 0 5-bit i/o port input/output can be specified in 1-bit units. intp3 p10 ano0 p11 i/o port 1 2-bit i/o port input/output can be specified in 1-bit units. ano1 p30 txda0/sob4 p31 rxda0/intp7/sib4 p32 ascka0/sckb4/tip00/top00 p33 tip01/top01 p34 tip10/top10 p35 tip11/top11 p36 ctxd0 note 2 /ietx0 note 3 p37 crxd0 note 2 /ierx0 note 3 p38 txda2/sda00 note 4 p39 i/o port 3 10-bit i/o port input/output can be specified in 1-bit units. rxda2/scl00 note 4 notes 1. flash memory version only 2. can controller version only 3. iebus controller version only 4. i 2 c bus version (y version) only
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 49 (2/3) pin name i/o function alternate function p40 sib0/sda01 note 1 p41 sob0/scl01 note 1 p42 i/o port 4 3-bit i/o port input/output can be specified in 1-bit units. sckb0 p50 tiq01/kr0/toq01/rtp00 p51 tiq02/kr1/toq02/rtp01 p52 tiq03/kr2/toq03/rtp02/ ddi note 2 p53 sib2/kr3/tiq00/toq00/rtp03/ ddo note 2 p54 sob2/kr4/rtp04/dck note 2 p55 i/o port 5 6-bit i/o port input/output can be specified in 1-bit units. sckb2/kr5/rtp05/dms note 2 p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 ani7 p78 ani8 p79 ani9 p710 ani10 p711 i/o port 7 12-bit i/o port input/output can be specified in 1-bit units. ani11 p90 a0/kr6/txda1/sda02 note 1 p91 a1/kr7/rxda1/scl02 note 1 p92 a2/tip41/top41 p93 a3/tip40/top40 p94 a4/tip31/top31 p95 a5/tip30/top30 p96 a6/tip21/top21 p97 a7/sib1/tip20/top20 p98 a8/sob1 p99 a9/sckb1 p910 a10/sib3 p911 a11/sob3 p912 a12/sckb3 p913 a13/intp4 p914 a14/intp5/tip51/top51 p915 i/o port 9 16-bit i/o port input/output can be specified in 1-bit units. a15/intp6/tip50/top50 notes 1 .i 2 c bus version (y version) only 2. flash memory version only
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 50 (3/3) pin name i/o function alternate function pcm0 wait pcm1 clkout pcm2 hldak pcm3 i/o port cm 4-bit i/o port input/output can be specified in 1-bit units. hldrq pct0 wr0 pct1 wr1 pct4 rd pct6 i/o port ct 4-bit i/o port input/output can be specified in 1-bit units. astb pdh0 a16 pdh1 a17 pdh2 a18 pdh3 a19 pdh4 a20 pdh5 i/o port dh 6-bit i/o port input/output can be specified in 1-bit units. a21 pdl0 ad0 pdl1 ad1 pdl2 ad2 pdl3 ad3 pdl4 ad4 pdl5 ad5/flmd1 note pdl6 ad6 pdl7 ad7 pdl8 ad8 pdl9 ad9 pdl10 ad10 pdl11 ad11 pdl12 ad12 pdl13 ad13 pdl14 ad14 pdl15 i/o port dl 16-bit i/o port input/output can be specified in 1-bit units. ad15 note flash memory version only
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 51 (2) non-port pins (1/4) pin name i/o function alternate function a0 p90/kr6/tdxa1/sda02 note 1 a1 p91/kr7/rxda1/scl02 note 1 a2 p92/tip41/top41 a3 p93/tip40/top40 a4 p94/tip31/top31 a5 p95/tip30/top30 a6 p96/tip21/top21 a7 p97/sib1/tip20/top20 a8 p98/sob1 a9 p99/sckb1 a10 p910/sib3 a11 p911/sob3 a12 p912/sckb3 a13 p913/intp4 a14 p914/intp5/tip51/top51 a15 output address bus for external memory (when using separate bus) p915/intp6/tip50/top50 a16 to a21 output address bus for external memory pdh0 to pdh5 ad0 to ad4 pdl0 to pdl4 ad5 pdl5/flmd1 note 2 ad6 to ad15 i/o address bus/data bus for external memory pdl6 to pdl15 adtrg input a/d converter external trigger input p03/intp0 ani0 p70 ani1 p71 ani2 p72 ani3 p73 ani4 p74 ani5 p75 ani6 p76 ani7 p77 ani8 p78 ani9 p79 ani10 p710 ani11 input analog voltage input for a/d converter p711 ano0 p10 ano1 output analog voltage output for d/a converter p11 ascka0 input uarta0 baud rate clock input p32/sckb4/tip00/top00 astb output address strobe signal output for external memory pct6 av ref0 reference voltage input for a/d converter (same potential as v dd ) ? av ref1 ? reference voltage input for d/a converter (same potential as v dd ) ? av ss ? ground potential for a/d and d/a converters (same potential as v ss ) ? notes 1. i 2 c bus version (y version) only 2. flash memory version only
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 52 (2/4) pin name i/o function alternate function bv dd ? positive power supply for bus interface and alternate-function ports ? bv ss ? ground potential for bus interface and alternate-function ports ? clkout output internal system clock output pcm1 crxd0 note 1 input can receive data input p37/ierx0 note 2 ctxd0 note 1 output can transmit data output p36/ietx0 note 2 dck note 3 input debug clock input p54/sob2/kr4/rtp04 ddi note 3 input debug data input p52/tiq03/kr2/toq03/rtp02 ddo note 3 output debug data output p53/sib2/kr3/tiq00/toq00/ rtp03 dms note 3 input debug mode select p55/sckb2/kr5/rtp05 drst note 3 input debug reset input p05/intp2 ev dd ? positive power supply for external (same potential as v dd ) ? ev ss ? ground potential for external (same potential as v ss ) ? flmd0 note 3 ? flmd1 note 3 input flash programming mode setting pin pdl5/ad5 hldak output bus hold acknowledge output pcm2 hldrq input bus hold request input pcm3 ic note 4 ? internally connected ? ierx0 note 2 input iebus receive data input p37/crxd0 note 1 ietx0 note 2 output iebus transmit data output p36/ctxd0 note 1 intp0 p03/adtrg intp1 p04 intp2 p05/drst note 3 intp3 p06 intp4 p913/a13 intp5 p914/a14/tip51/top51 intp6 p915/a15/tip50/top50 intp7 input external interrupt request input (maskable, analog noise elimination note 5 ) p31/rxda0/sib4 kr0 p50/tiq01/toq01/rtp00 kr1 p51/tiq02/toq02/rtp01 kr2 p52/tiq03/toq03/rtp02/ddi note 3 kr3 p53/sib2/tiq00/toq00/rtp03/ ddo note 3 kr4 p54/sob2/rtp04/dck note 3 kr5 p55/sckb2/rtp05/dms note 3 kr6 p90/a0/txda1/sda02 note 6 kr7 input key interrupt input p91/a1/rxda1/scl02 note 6 notes 1. can controller version only 2. iebus controller version only 3. flash memory version only 4. mask rom version only 5. an analog noise elimination function or digital noise elimination function is selectable for the intp3 pin. 6. i 2 c bus version (y version) only
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 53 (3/4) pin name i/o function alternate function nmi input external interrupt input (non-maskable, analog noise elimination) p02 rd output read strobe signal output for external memory pct4 regc ? connection of regulator output stabilization capacitance ? reset input system reset input ? rtp00 p50/tiq01/kr0/toq01 rtp01 p51/tiq02/kr1/toq02 rtp02 p52/tiq03/kr2/toq03/ddi note 1 rtp03 p53/sib2/kr3/tiq00/toq00/ ddo note 1 rtp04 p54/sob2/kr4/dck note 1 rtp05 output real-time output port p55/sckb2/kr5/dms note 1 rxda0 serial receive data input (uarta0) p31/intp7/sib4 rxda1 serial receive data input (uarta1) p91/a1/kr7/scl02 note 2 rxda2 input serial receive data input (uarta2) p39/scl00 note 2 sckb0 serial clock i/o (csib0) p42 sckb1 serial clock i/o (csib1) p99/a9 sckb2 serial clock i/o (csib2) p55/kr5/rtp05/dms note 1 sckb3 serial clock i/o (csib3) p912/a12 sckb4 i/o serial clock i/o (csib4) p32/ascka0/tip00/top00 scl00 note 2 serial clock i/o (i 2 c00) p39/rxda2 scl01 note 2 serial clock i/o (i 2 c01) p41/sob0 scl02 note 2 i/o serial clock i/o (i 2 c02) p91/a1/kr7/rxda1 sda00 note 2 serial transmit/receive data i/o (i 2 c00) p38/txda2 sda01 note 2 serial transmit/receive data i/o (i 2 c01) p40/sib0 sda02 note 2 i/o serial transmit/receive data i/o (i 2 c02) p90/a0/kr6/txda1 sib0 serial receive data input (csib0) p40/sda01 note 2 sib1 serial receive data input (csib1) p97/a7/tip20/top20 sib2 serial receive data input (csib2) p53/kr3/tiq00/toq00/rtp03/ ddo note 1 sib3 serial receive data input (csib3) p910/a10 sib4 input serial receive data input (csib4) p31/rxda0/intp7 sob0 serial transmit data output (csib0) p41/scl01 note 2 sob1 serial transmit data output (csib1) p98/a8 sob2 serial transmit data output (csib2) p54/kr4/rtp04/dck note 1 sob3 serial transmit data output (csib3) p911/a11 sob4 output serial transmit data output (csib4) p30/txda0 tip00 external event/clock input (tmp0) p32/ascka0/sckb4/top00 tip01 external event/clock input (tmp0) p33/top01 tip10 external event/clock input (tmp1) p34/top10 tip11 external event/clock input (tmp1) p35/top11 tip20 external event/clock input (tmp2) p97/a7/sib1/top20 tip21 input external event/clock input (tmp2) p96/a6/top21 notes 1. flash memory version only 2. i 2 c bus version (y version) only
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 54 (4/4) pin name i/o function alternate function tip30 external event/clock input (tmp3) p95/a5/top30 tip31 external event/clock input (tmp3) p94/a4/top31 tip40 external event/clock input (tmp4) p93/a3/top40 tip41 external event/clock input (tmp4) p92/a2/top41 tip50 external event/clock input (tmp5) p915/a15/intp6/top50 tip51 input external event/clock input (tmp5) p914/a14/intp5/top51 tiq00 external event/clock input (tmq0) p53/sib2/kr3/toq00/rtp03 /ddo note 1 tiq01 external event/clock input (tmq0) p50/kr0/toq01/rtp00 tiq02 external event/clock input (tmq0) p51/kr1/toq02/rtp01 tiq03 input external event/clock input (tmq0) p52/kr2/toq03/rtp02/ddi note 1 top00 timer output (tmp0) p32/ascka0/sckb4/tip00 top01 timer output (tmp0) p33/tip01 top10 timer output (tmp1) p34/tip10 top11 timer output (tmp1) p35/tip11 top20 timer output (tmp2) p97/a7/sib1/tip20 top21 timer output (tmp2) p96/a6/tip21 top30 timer output (tmp3) p95/a5/tip30 top31 timer output (tmp3) p94/a4/tip31 top40 timer output (tmp4) p93/a3/tip40 top41 timer output (tmp4) p92/a2/tip41 top50 timer output (tmp5) p915/a15/intp6/tip50 top51 output timer output (tmp5) p914/a14/intp5/tip51 toq00 timer output (tmq0) p53/sib2/kr3/tiq00/rtp03/ ddo note 1 toq01 timer output (tmq0) p50/tiq01/kr0/rtp00 toq02 timer output (tmq0) p51/rtp01/kr1/tiq02 toq03 output timer output (tmq0) p52/tiq03/kr2/rtp02/ddi note 1 txda0 serial transmit data output (uarta0) p30/sob4 txda1 serial transmit data output (uarta1) p90/a0/kr6/sda02 note 2 txda2 output serial transmit data output (uarta2) p38/sda00 note 2 v dd ? positive power supply for internal ? v ss ? ground potential for internal ? wait input external wait input pcm0 wr0 write strobe for external memory (lower 8-bits) pct0 wr1 output write strove for external memory (higher 8 bits) pct1 x1 input ? x2 ? connection of resonator for main clock ? xt1 input ? xt2 ? connection of resonator for subclock ? notes 1. flash memory version only 2. i 2 c bus version (y version) only
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 55 2.2 pin states the operation states of pins in the various modes are described below. table 2-2. pin operation states in various modes bus control pin reset halt mode during dma transfer idle1, idle2 mode, software stop mode idle state note 2 bus hold ad0 to ad15 a0 to a21 hi-z held hi-z wait ??? clkout l operating operating wr0, wr1 rd astb hi-z hldak hh l hldrq hi-z note 1 operating ?? operating notes 1. the bus control pin is shared with a port pin, so it is initialized to the input mode (port mode). 2. the state of the pins in the idle state inserted following the t3 state is shown. remark hi-z: high impedance held: the state during the immediately preceding external bus cycle is held. l: low-level output h: high-level output ? : input without sampling (not acknowledged)
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 56 2.3 description of pin functions (1) p02 to p05 (port 0) ? 3-state i/o p02 to p05 function as a 5-bit i/o port for which input and output can be specified in 1-bit units. in addition to i/o port pins, these pins can also be used as an nmi input, external interrupt request signal inputs, the external trigger for the a/d converter, and debug reset input. the port or control mode can be selected for each bit, and a pin?s valid edge is specified by the intr0 and intf0 registers. normal output and n-ch open-drain output can be selected for p02 to p05. (a) port mode p02 to p05 can be set to input or output in 1-bit units using port mode register 0 (pm0). (b) control mode (i) nmi (non-maskable interrupt request) ? input this is a non-maskable interrupt request signal input pin. (ii) intp0 to intp3 (interrupt request from peripherals) ? input these are external interrupt request signal input pins. (iii) adtrg (a/d trigger input) ? input this is the a/d converter?s external trigger input pin. this pin is controlled by a/d converter mode register 0 (ada0m0). (iv) drst (debug reset) ? input this is the debug reset input pin. this is a negative logic signal that initializes the on-chip debug circuit asynchronously. when set to low level, it resets/disables the on-chip debug circuit. when not using the debug function, set this pin to low level (drst is valid only in the flash memory version). (2) p10, p11 (port 1) ? 3-state i/o p10 and p11 function as a 2-bit i/o port for which input and output can be specified in 1-bit units. in addition to i/o pins, these pins can also be used as the analog output pins for the a/d converter in the control mode. when using these pins as analog output pins, set them in the input mode. at this time, do not read the port. (a) port mode p10 and p11 can be set to input or output in 1-bit units using port mode register 1 (pm1). (b) control mode (i) ano0, ano1 (analog output) ? output these are analog output pins for the d/a converter.
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 57 (3) p30 to p39 (port 3) ? 3-state i/o p30 to p39 function as a 10-bit i/o port for which input and output can be set in 1-bit units. in addition to i/o port pins, these pins can also be used as external interrupt request signal inputs, serial interface i/o, timer/counter i/o, can data i/o, and iebus data i/o. the port or control mode can be selected for each bit, and the valid edge for p31 is specified by the intr3 and intf3 registers. normal output and n-ch open-drain output can be selected for p30 to p39. (a) port mode p30 to p39 can be set to input or output in 1-bit units using port mode register 3 (pm3). (b) control mode (i) sib4 (serial input 1) ? input this is the serial receive data input pin for csib4. (ii) sob4 (serial output) ? output this is the serial transmit data output pin for csib4. (iii) sckb4 (serial clock) ? 3-state i/o this is the serial clock i/o pin for csib4. (iv) rxda0, rxda2 (receive data) ? input these are the serial receive data input pins for uarta0 and uarta2. (v) txda0, txda2 (transmit data) ? output these are the serial transmit data output pins for uarta0 and uarta2. (vi) ascka0 (asynchronous serial clock) ? input this is the serial baud rate input pin for uarta0. (vii) intp7 (interrupt request from peripherals) ? input this is the external interrupt request signal input pin. (viii) tip00, tip01, tip10, tip11 (timer input) ? input these are the external count clock input pins for timers p0 and p1. (ix) top00, top01, top10, top11 (timer output) ? output these are the pulse signal output pins for timers p0 and p1. (x) sda00 (serial data) ? input this is the serial transmit/receive data i/o pin for i 2 c00 (sda00 is valid only in the i 2 c bus version (y version)). (xi) scl00 (serial clock) ? i/o this is the serial clock i/o pin for i 2 c00 (scl00 is valid only in the i 2 c bus version (y version)).
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 58 (xii) crxd0 (can receive data) ? input this is the receive data input pin for can0 (crxd0 is valid only in the can controller version). (xiii) ctxd0 (can transmit data) ? output this is the transmit data output pin for can0 (ctxd0 is valid only in the can controller version). (xiv) ierx0 (iebus receive data) ? input this is the receive data input pin for iebus (ierx0 is valid only in the iebus controller version). (xv) ietx0 (iebus transmit data) ? output this is the transmit data output pin for iebus (ietx0 is valid only in the iebus controller version). (4) p40 to p42 (port 4) ? 3-state i/o p40 to p42 function as a 3-bit i/o port for which input and output can be set in 1-bit units. in addition to i/o port pins, these pins can also be used as serial interface i/o. the port or control mode can be selected for each bit. normal output and n-ch open-drain output can be selected for p40 to p42. (a) port mode p40 to p42 can be set to input or output in 1-bit units using port mode register 4 (pm4). (b) control mode (i) sib0 (serial input) ? input this is the serial receive data input pin for csib0. (ii) sob0 (serial output) ? output this is the serial transmit data output pin for csib0. (iii) sckb0 (serial clock) ? 3-state i/o this is the serial clock i/o pin for csib0. (iv) sda01 (serial data) ? i/o this is the serial transmit/receive data i/o pin for i 2 c00 (sda01 is valid only in the i 2 c bus version (y version)). (v) scl01 (serial clock) ? i/o this is the serial clock i/o pin for i 2 c00 (scl01 is valid only in the i 2 c bus version (y version)).
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 59 (5) p50 to p55 (port 5) ? 3-state i/o p50 to p55 function as a 6-bit i/o port for which input and output can be set in 1-bit units. in addition to i/o port pins, these pins can also be used as serial interface i/o, timer/counter i/o, real-time output, debug function i/o, and key interrupt i nput function. the port or control mode can be selected for each bit. normal output and n-ch open-drain output can be selected for p50 to p55. (a) port mode p50 to p55 can be set to input or output in 1-bit units using port mode register 5 (pm5). (b) control mode (i) sib2 (serial input) ? input this is the serial receive data input pin for csib2. (ii) sob2 (serial output) ? output this is the serial transmit data output pin for csib2. (iii) sckb2 (serial clock) ? 3-state i/o this is the serial clock i/o pin for csib2. (iv) rtp00 to rtp05 (real-time output port) ? output these are real-time output port. (v) kr0 to kr5 (key return) ? input these are the key interrupt input pins. in the input port mode, the operation is specified by the key return mode register (krm). (vi) tiq00, tiq01, tiq02, tiq03 (timer input) ? input these are the external count clock input pins for timer q0. (vii) toq00, toq01, toq02, toq03 (timer output) ? output these are the pulse signal output pins for timer q0. (viii) ddi (debug data input) ? input this is the debug data input pin for the on-chip debug circuit. (ix) ddo (debug data output) ? output this is the debug data output pin for the on-chip debug circuit. (x) dck (debug clock input) ? input this is the debug clock input pin for the on-chip debug circuit. (xi) dms (debug mode select) ? input this is the debug mode select pin for the on-chip debug circuit.
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 60 (6) p70 to p711 (port 7) ? 3-state i/o p70 to p711 function as a 12-bit i/o port for which input and output can be set in 1-bit units. in addition to i/o port pins, these pins can also be used as analog input pins for the a/d converter in the control mode. when using these pins as analog output pins, set them in the input mode. at this time, do not read the port. (a) port mode p70 to p711 can be set to input or output in 1-bit units using port mode register 7 (pm7). (b) control mode p70 to p711 function alternatively with ani0 to ani11. (i) ani0 to ani11 (analog input) ? input these are the analog input pins for the a/d converter. (7) p90 to p915 (port 9) ? 3-state i/o p90 to p915 function as a 16-bit i/o port for which input and output can be set in 1-bit units. in addition to i/o port pins, these pins can also be used as serial interface i/o, timer/counter i/o, an address bus when externally expanding memory, external interrupt request signal inputs, and the key interrupt input function. the port or control mode can be selected for each bit. normal output and n-ch open-drain output can be selected for p90 to p915. (a) port mode p90 to p915 can be set to input or output in 1-bit units using port mode register 9 (pm9) (to use these pins as the a0 to a15 pins, the mode must be changed in 16-bit units). (b) control mode (i) sib1, sib3 (serial input) ? input these are the serial receive data input pins for csib1 and csib3. (ii) sob1, sob3 (serial output) ? output these are the serial transmit data output pins for csib1 and csib3. (iii) sckb1, sckb3 (serial clock) ? 3-state i/o these are the serial clock i/o pins for csib1 and csib3. (iv) rxda1 (receive data) ? input this is the serial receive data input pin for uarta1. (v) txda1 (transmit data) ? output this is the serial transmit data output pin for uarta1. (vi) tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51 (timer input) ? input these are the external count clock input pins for timers p2, p3, p4, and p5. (vii) top20, top21, top30, top31, top40, top41, top50, top51 (timer output) ? output these are the pulse signal output pins for timers p2, p3, p4, and p5.
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 61 (viii) a0 to a15 (address bus) ? output these are 16-bit address output pins used during external access. the output changes in synchronization with the rising edge of the clock in the t1 state of the bus cycle. when the bus cycle becomes inactive, these pins hold the address of the immediately preceding bus cycle. (ix) intp4 to intp6 (interrupt request from peripherals) ? input these are external interrupt request signal input pins. (iix) kr6, kr7 (key return) ? input these are key interrupt input pins. the operation is specified by the key return mode register (krm) in the input port mode. (xi) sda02 (serial data) ? i/o this is the serial transmit/receive data i/o pin for i 2 c02 (sda02 is valid only in the i 2 c bus version (y version)). (xii) scl02 (serial clock) ? i/o this is the serial clock data i/o pin for i 2 c02 (scl02 is valid only in the i 2 c bus version (y version)). (8) pcm0 to pcm3 (port cm) ? 3-state i/o pcm0 to pcm3 function as a 4-bit i/o port for which input and output can be set in 1-bit units. in addition to i/o pins, these pins can also be used as the bus hold signal i/o in the control mode, bus clock output, and the control signal (wait) that inserts waits into the bus cycle. (a) port mode pcm0 to pcm3 can be set to input or output in 1-bit units using port mode register cm (pmcm). (b) control mode (i) hldak (hold acknowledge) ? output this is an output pin for the acknowledge signal that indicates the high-impedance status for the address bus, data bus, and control bus when the v850es/sg2 receives a bus hold request. the address bus, data bus, and control bus are high impedance while this signal is active. (ii) hldrq (hold request) ? input this is an input pin by which an external device requests the v850es/sg2 to release the address bus, data bus, and control bus release requests. this pin accepts asynchronous input for clkout. when this pin is made active, the v850es/sg2 sets the address bus, data bus, and control bus to high impedance upon the end of the bus cycle currently being executed, or immediately if no bus cycle is being executed, and the hldak signal is then made active and the bus is released. (iii) clkout (clock output) ? output this pin outputs internally generated bus clocks.
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 62 (iv) wait (wait) ? input this is a control signal input pin that inserts data wait states in the bus cycle. data can be input to this pin asynchronous to the clkout signal. in the multiplexed mode, this pin is sampled at the falling edge of the clkout signal in the t2 and tw states of the bus cycle. in the separate mode, it is sampled at the rising edge of the clkout signal immediately after the t1 and tw states of the bus cycle. a wait state may not be inserted if the setup/hold time of the sampling timing is not satisfied. on/off switching of the wait function is performed using port mode control register cm (pmccm). (9) pct0, pct1, pct4, pct6 (port ct) ? 3-state i/o pct0, pct1, pct4, and pct6 function as a 4-bit i/o port for which input and output can be set in 1-bit units. in addition to i/o pins, these pins can also be used as control signal output pins for external memory expansion in the control mode. (a) port mode pct0, pct1, pct4, and pct6 can be set to input or output in 1-bit units using port mode register ct (pmct). (b) control mode (i) wr0 (lower byte write strobe) ? output this is the write strobe signal output pin for the lower data of the external 16-bit data bus. (ii) wr1 (upper byte write strobe) ? output this is the write strobe signal output pin for the higher data of the external 16-bit data bus. (iii) rd (read strobe) ? output this is the read strobe signal output pin for the external 16-bit data bus. (iv) astb (address strobe) ? output this is the output pin for the latch strobe signal for the external address bus. output becomes low level in synchronization with the falling edge of the clock during the t1 state of the bus cycle, and becomes high level in synchronization with the falling edge of the clock during the t3 state of the bus cycle. output becomes high level when the bus cycle is inactive. (10) pdh0 to pdh5 (port dh) ? 3-state i/o pdh0 to pdh5 function as a 6-bit i/o port for which input and output can be set in 1-bit units. in addition to i/o port pins, these pins can also be used as an address bus during external memory expansion in the control mode. (a) port mode pdh0 to pdh5 can be set to input or output in 1-bit units using port mode register dh (pmdh).
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 63 (b) control mode (i) a16 to a21 (address bus) ? output these are 6-bit address output pins used by the address bus during external access. the output changes in synchronization with the rising edge of the clock during the t1 state of the bus cycle. when the bus cycle becomes inactive, these pins hold the address of the immediately preceding bus cycle. (11) pdl0 to pdl15 (port dl) ? 3-state i/o pdl0 to pdl15 function as a 16-bit i/o port for which input and output can be set in 1-bit units. in addition to i/o pins, these pins can also be used as a time division address/data bus (ad0 to ad15) during external memory expansion. moreover, during flash memory programming (input of high level to flmd0), pdl5/ad5 function as the flmd1 pin. at this time, be sure to input a low level to the flmd1 pin. (a) port mode pdl0 to pdl15 can be set to input or output in 1-bit units using port mode register dl (pmdl). (b) control mode (i) ad0 to ad15 (address/data bus) ? 3-state i/o these form an address/data multiplexed bus during external access. in the multiplexed bus mode, they function as address output or data i/o, and in the separate bus mode, they function as data i/o. (12) reset (reset) ? input reset is a signal that is input asynchronously and has a low level width regardless of the status of the operating clock. when this signal is input, a system reset is executed with a higher priority than all other operations. in addition to being used for ordinary initializations/start operations, this signal can also be used to release a standby mode (halt, idle1, idle2, software stop). (13) x1, x2 (crystal for main clock) these pins are used to connect the resonator that generates the system clock. (14) xt1, xt2 (crystal for subclock) these pins are used to connect the resonator that generates the subclock. (15) av ss (ground for analog) this is the ground pin for the a/d converter, d/a converter, and alternate-function ports. (16) av ref0 (analog reference voltage) ? input this pin the analog positive power supply pin for the a/d converter and alternate-function ports. it is also used to supply a reference voltage to the a/d converter. (17) av ref1 (analog reference voltage) ? input this pin the analog positive power supply pin for the d/a converter and alternate-function ports. it is also used to supply a reference voltage to the d/a converter.
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 64 (18) ev dd (power supply for port) this is the positive power supply pin for i/o ports and alternate-function pins. (19) ev ss (ground for port) this is the ground pin for i/o ports and alternate-function pins. (20) v dd (power supply) this is the positive power supply pin. connect all the v dd pins to a positive power supply. (21) v ss (ground) this is the ground pin. connect all the v ss pins to ground. (22) flmd0, flmd1 (flash programming mode) these are the positive power supply pins for the flash memory programming mode. in the normal operation mode, connect these pins to v ss . (23) bv dd (power supply for bus interface) this is the positive power supply pin for the bus interface. (24) bv ss (ground for bus interface) this is the ground pin for the bus interface. (25) ic (internally connect) this is an internally connected pin. in the normal operation mode, directly connect this pin to v ss . (26) regc (regulator control) ? input this is the capacitor pin for the regulator.
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 65 2.4 pin i/o circuit types, i/o buffer power supplies and handling of unused pins (1/3) pin alternate function i/o circuit type recommended connection p02 nmi p03 intp0/adtrg p04 intp1 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p05 intp2/drst note 1 10-n input: independently connect to ev ss via a resistor. fixing to v dd level is prohibited. output: leave open. internally pull-down after reset. p06 intp3 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p10 ano0 p11 ano1 12-d input: independently connect to av ref1 or av ss via a resistor. output: leave open. p30 txda0/sob4 p31 rxda0/intp7/sib4 p32 ascka0/sckb4/tip00 p33 tip01/top01 p34 tip10/top10 p35 tip11/top11 p36 ctxd0 note 2 /ietx0 note 3 p37 crxd0 note 2 /ierx0 note 3 p38 txda2/sda00 note 4 p39 rxda2/scl00 note 4 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p40 sib0/sda01 note 4 p41 sob0/scl01 note 4 p42 sckb0 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p50 tiq01/kr0/toq01/rtp00 p51 tiq02/kr1/toq02/rtp01 p52 tiq03/kr2/toq03/rtp02/ddi note 1 p53 sib2/kr3/tiq00/toq00/rtp03/ ddo note 1 p54 sob2/kr4/rtp04/dck note 1 p55 sckb2/kr5/rtp05/dms note 1 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. notes 1. flash memory version only 2. can controller version only 3. iebus controller version only 4. i 2 c version (y version) only
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 66 (2/3) pin alternate function i/o circuit type recommended connection p70 to p711 ani0 to ani11 11-f input: independently connect to av ref0 or av ss via a resistor. output: leave open. p90 a0/kr6/tdxa1/sda02 note 1 p91 a1/kr7/rxda1/scl02 note 1 p92 a2/tip41/top41 p93 a3/tip40/top40 p94 a4/tip31/top31 p95 a5/tip30/top30 p96 a6/tip21/top21 p97 a7/sib1/tip20/top20 p98 a8/sob1 p99 a9/sckb1 p910 a10/sib3 p911 a11/sob3 p912 a12/sckb3 p913 a13/intp4 p914 a14/intp5/tip51/top51 p915 a15/intp6/tip50/top50 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. pcm0 wait pcm1 clkout pcm2 hldak pcm3 hldrq 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. pct0, pct1 wr0, wr1 pct4 rd pct6 astb 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. pdh0 to pdh3 a16 to a19 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. pdh4, pdh5 a20, a21 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. pdl0 to pdl4 ad0 to ad4 input: independently connect to bv dd or bv ss via a resistor. output: leave open. pdl5 ad5/flmd1 note 2 input: independently connect to bv dd or bv ss via a resistor. output: leave open. pdl6 to pdl15 ad6 to ad15 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. notes 1. i 2 c version (y version) only 2. flash memory version only
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 67 (3/3) pin alternate function i/o circuit type recommended connection av ref0 ?? directly connect to v dd . av ref1 ?? directly connect to v dd . av ss ?? directly connect to v ss . bv dd ? bv ss ? ev dd ?? ? ev ss ?? ? flmd0 note 1 ?? directly connect to v ss in a mode other than the flash programming mode. ic note 2 ?? directly connect to v ss . regc ?? connect regulator output stabilization capacitance. reset ? 2 ? v dd ?? ? v ss ?? ? x1 ?? ? x2 ?? ? xt1 ? 16 connect to v ss via a resistor. xt2 ? 16 leave open. notes 1. flash memory version only 2. mask rom version only
chapter 2 pin functions preliminary user?s manual u16541ej1v0um 68 figure 2-1. pin i/o circuits (1/2) type 2 schmitt-triggered input with hysteresis characteristics type 5 type 10-g in data output disable p-ch in/out ev dd n-ch input enable type 10-n type 11-f type 12-d data output disable v dd p-ch in/out n-ch open drain input enable ocdm0 bit data output disable v dd p-ch in/out n-ch open drain input enable data output disable open drain av dd p-ch in/out n-ch p-ch n-ch av ref0 (threshold voltage) comparator input enable + ? av ss av ss data output disable input enable av dd p-ch in/out n-ch p-ch n-ch analog output voltage av ss n-ch
chapter 2 pin functions preliminary user ? s manual u16541ej1v0um 69 figure 2-1. pin i/o circuits (2/2) type 16 p-ch feedback cut-off xt1 xt2
preliminary user?s manual u16541ej1v0um 70 chapter 3 cpu function the cpu of the v850es/sg2 is based on risc architecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 features minimum instruction execution time: 50 ns (at 20 mhz operation: 3.0 to 3.6 v) 30.5 ns (with subclock (f xt = 32.768 khz operation)) memory space program space: 64 mb linear data space: 4 gb linear general-purpose registers: 32 bits 32 registers internal 32-bit architecture 5-stage pipeline control multiplication/division instruction saturation operation instruction 32-bit shift instruction: 1 clock load/store instruction with long/short format four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1
chapter 3 cpu function preliminary user?s manual u16541ej1v0um 71 3.2 cpu register set the registers of the v850es/sg2 can be classified into two types: general-purpose program registers and dedicated system registers. all the registers are 32 bits wide. for details, refer to the v850es architecture user?s manual . (1) program register set (2) system register set r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register)
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 72 3.2.1 program register set the program registers include general-purpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are available. any of these registers can be used to store a data variable or an address variable. however, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the sld and sst instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. when using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time os. if the real-time os does not use r2, it can be used as a register for variables. table 3-1. program registers name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as working register to create 32-bit immediate data r2 register for address/data variable (if real-time os does not use r2) r3 stack pointer used to create a stack frame when a function is called r4 global pointer used to access a global variable in the data area r5 text pointer used as register that indicates the beginning of a text area (area where program codes are located) r6 to r29 register for address/data variable r30 element pointer used as base pointer to access memory r31 link pointer used when the compiler calls a function pc program counter holds the instruction address during program execution (2) program counter (pc) the program counter holds the instruction address during program execution. the lower 32 bits of this register are valid. bits 31 to 26 are fixed to 0. a carry from bit 25 to 26 is ignored even if it occurs. bit 0 is fixed to 0. this means that execution cannot branch to an odd address. 31 26 25 1 0 pc fixed to 0 instruction address during program execution 0 default value 00000000h
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 73 3.2.2 system register set the system registers control the status of the cpu and hold interrupt information. these registers can be read or written by using system register load/store instructions (ldsr and stsr), using the system register numbers listed below. table 3-2. system register numbers operand specification register number system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 ? 1 interrupt status saving register (eipsw) note 1 ? 2 nmi status saving register (fepc) ? 3 nmi status saving register (fepsw) ? 4 interrupt source register (ecr) 5 program status word (psw) ? 6 to 15 reserved for future function expansion (operation is not guaranteed if these registers are accessed) 16 callt execution status saving register (ctpc) ? 17 callt execution status saving register (ctpsw) ? 18 exception/debug trap status saving register (dbpc) note 2 19 exception/debug trap status saving register (dbpsw) note 2 20 callt base pointer (ctbp) ? 21 to 31 reserved for future function expansion (operation is not guaranteed if these registers are accessed) notes 1. because only one set of these registers is available, the contents of this register must be saved by program if multiple interrupts are enabled. 2. these registers can be accessed only when the dbtrap instruction is executed. caution even if eipc or fepc, or bit 0 of ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution is returned to the main routine by the reti instruction after interrupt servicing (this is because bit 0 of the pc is fixed to 0). set an even value to eipc, fepc, and ctpc (bit 0 = 0). remark : can be accessed : access prohibited
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 74 (1) interrupt status saving registers (eipc and eipsw) eipc and eipsw are used to save the status when an interrupt occurs. if a software exception or a maskable interrupt occurs, the contents of the program counter (pc) are saved to eipc, and the contents of the program status word (psw) are saved to eipsw (these contents are saved to the nmi status saving registers (fepc and fepsw) if a non-maskable interrupt occurs). the address of the instruction next to the instruction under execution, except some instructions, is saved to eipc when a software exception or a maskable interrupt occurs. the current contents of the psw are saved to eipsw. because only one set of interrupt status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are reserved for future function expansion (these bits are always fixed to 0). 31 0 eipc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (contents of psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 75 (2) nmi status saving registers (fepc and fepsw) fepc and fepsw are used to save the status when a non-maskable interrupt (nmi) occurs. if an nmi occurs, the contents of the program counter (pc) are saved to fepc, and those of the program status word (psw) are saved to fepsw. the address of the instruction next to the one of the instruction under execution, except some instructions, is saved to fepc when an nmi occurs. the current contents of the psw are saved to fepsw. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are reserved for future function expansion (these bits are always fixed to 0). 31 0 fepc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (contents of psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (3) interrupt source register (ecr) the interrupt source register (ecr) holds the source of an exception or interrupt if an exception or interrupt occurs. this register holds the exception code of each interrupt source. because this register is a read-only register, data cannot be written to this register using the ldsr instruction. 31 0 ecr fecc eicc default value 00000000h 16 15 bit position bit name meaning 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 76 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the cpu. if the contents of a bit of this register are changed by using the ldsr instruction, the new contents are validated immediately after completion of ldsr instruction execution. if the id flag is set to 1, however, interrupt request acknowledgement is disabled even while the ldsr instruction is being executed. bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 0 psw rfu default value 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name meaning 31 to 8 rfu reserved field. fixed to 0. 7np indicates that a non-maskable interrupt (nmi) is being serviced. this bit is set to 1 when an nmi request is acknowledged, disabling multiple interrupts. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that an exception is being processed. this bit is set to 1 when an exception occurs. even if this bit is set, interrupt requests are acknowledged. 0: exception is not being processed. 1: exception is being processed. 5id indicates whether a maskable interrupt can be acknowledged. 0: interrupt enabled 1: interrupt disabled 4sat note indicates that the result of a saturation operation has overflowed and is saturated. because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. use the ldsr instruction to clear this bit. this flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: not saturated 1: saturated 3cy indicates whether a carry or a borrow occurs as a result of an operation. 0: carry or borrow does not occur. 1: carry or borrow occurs. 2ov note indicates whether an overflow occurs during operation. 0: overflow does not occur. 1: overflow occurs. 1s note indicates whether the result of an operation is negative. 0: the result is positive or 0. 1: the result is negative. 0 z indicates whether the result of an operation is 0. 0: the result is not 0. 1: the result is 0. remark also read note on the next page.
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 77 (2/2) note the result of the operation that has performed saturation processing is determined by the contents of the ov and s flags. the sat flag is set to 1 only when the ov flag is set to 1 when a saturation operation is performed. flag status status of operation result sat ov s result of operation of saturation processing maximum positive value is exceeded 1 1 0 7fffffffh maximum negative value is exceeded 1 1 1 80000000h positive (maximum value is not exceeded) 0 negative (maximum value is not exceeded) holds value before operation 0 1 operation result itself (5) callt execution status saving registers (ctpc and ctpsw) ctpc and ctpsw are callt execution status saving registers. when the callt instruction is executed, the contents of the program counter (pc) are saved to ctpc, and those of the program status word (psw) are saved to ctpsw. the contents saved to ctpc are the address of the instruction next to callt. the current contents of the psw are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are reserved for future function expansion (fixed to 0). 31 0 ctpc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (contents of psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 78 (6) exception/debug trap status saving registers (dbpc and dbpsw) dbpc and dbpsw are exception/debug trap status registers. if an exception trap or debug trap occurs, the contents of the program counter (pc) are saved to dbpc, and those of the program status word (psw) are saved to dbpsw. the contents to be saved to dbpc are the address of the instruction next to the one that is being executed when an exception trap or debug trap occurs. the current contents of the psw are saved to dbpsw. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved for future function expansion (fixed to 0). 31 0 dbpc (contents of pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (contents of psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a table address or generate a target address (bit 0 is fixed to 0). bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 0 ctbp (base address) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 79 3.3 operation modes 3.3.1 operation modes the v850es/sg2 has the following operation modes. (1) normal operation mode in this mode, each pin related to the bus interface is set to the port mode after system reset has been released. execution branches to the reset entry address of the internal rom, and then instruction processing is started. by setting the pmcdh, pmcdl, pmccm, and pmcct registers to the control mode using software, an external device can be connected to the external memory area. (2) flash memory programming mode in this mode, the internal flash memory can be programmed by using a flash programmer.
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 80 3.4 address space 3.4.1 cpu address space the cpu of the v850es/sg2 has 32-bit architecture and supports up to 4 gb of linear address space (data space) for operand addressing (data access). it also supports up to 64 mb of linear address space (program space) for instruction addressing. note, however, that both the program and data spaces have areas that are prohibited from being used. for details, see figure 3-2 . figure 3-1 shows the cpu address space. figure 3-1. cpu address space data area (4 gb linear) program area (64 mb linear) cpu address space ffffffffh 04000000h 00000000h 03ffffffh
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 81 3.4.2 image for addressing instruction addresses, up to 16 mb of external memory area, internal rom area, and internal ram area in an area of up to 16 mb of linear address space (program space) is supported. up to 4 gb of linear address space (data space) is supported for operand addressing (data access). in the 4 gb address space, it seems that there are sixty-four 64 mb physical address spaces. this means that the same 64 mb physical address space is accessed, regardless of the values of bits 31 to 26. figure 3-2. image on address space program space internal ram area programmable peripheral i/o area or use prohibited area use-prohibited area external memory area internal rom area (external memory area) data space image 63 image 1 image 0 peripheral i/o area internal ram area programmable peripheral i/o area or use-prohibited area external memory area internal rom area (external memory area) 16 mb 4 gb 64 mb 64 mb
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 82 3.4.3 wraparound of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. the higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. therefore, the lowest address of the program space, 00000000h, and the highest address, 03ffffffh, are contiguous addresses. that the lowest address and the highest address of the program space are contiguous in this way is called wraparound. caution because the 4 kb area of addresses 03fff000h to 03ffffffh is an on-chip peripheral i/o area, instructions cannot be fetched from this area. therefore, do not execute an operation in which the result of a branch address calculation affects this area. program space program space (+) direction ( ? ) direction 03fffffeh 03ffffffh 00000000h 00000001h (2) data space the result of an operand address calculation operation that exceeds 32 bits is ignored. therefore, the lowest address of the data space, 00000000h, and the highest address, ffffffffh, are contiguous, and wraparound occurs at the boundary of these addresses. data space data space (+) direction ( ? ) direction fffffffeh ffffffffh 00000000h 00000001h
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 83 3.4.4 memory map the areas shown in figure 3-3 are reserved in the v850es/sg2. figure 3-3. data memory map (physical addresses) (80 kb) use prohibited external memory area (14 mb) internal rom area note 3 (1 mb) external memory area (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) use prohibited note 1 (2 mb) 3ffffffh 3fec000h 1000000h 0ffffffh 0200000h 01fffffh 0000000h 3febfffh 3ffffffh 3fff000h 3ffefffh 3ff0000h 3feffffh programmable peripheral i/o area or use prohibited note 2 3fef000h 3feefffh 3fec000h 01fffffh 0100000h 00fffffh 0000000h notes 1. use of addresses 3fef000h to 3feffffh is prohibited because these addresses are in the same area as the on-chip peripheral i/o area. 2. addresses 3fec000h to 3fecbffh are allocated to addresses 3fec000h to 3feefffh of the can controller version as a programmable peripheral i/o area. use of these addresses in a version without a can controller is prohibited. 3. fetch access and read access to addresses 0000000h to 00fffffh is made to the internal rom area. however, data write access to these addresses is made to the external memory area.
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 84 figure 3-4. program memory map internal ram area (60 kb) programmable peripheral i/o area or use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area (14 mb) external memory area (1 mb) internal rom area (1 mb) 03ffffffh 03fff000h 03ffefffh 01000000h 00ffffffh 03ff0000h 03feffffh 00200000h 001fffffh 00100000h 000fffffh 00000000h remark instructions can be executed to the external memory area without execution branching from the internal rom area to the external memory area.
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 85 3.4.5 areas (1) internal rom/internal flash memory area up to 1 mb is reserved as an internal rom/internal flash memory area. (a) internal rom (256 kb) 256 kb are allocated to addresses 0000000h to 003ffffh of the following versions. accessing addresses 0040000h to 00fffffh is prohibited. ? pd703260, 703260y, 703270, 703270y, 703280, 703280y figure 3-5. internal rom area (256 kb) access-prohibited area internal rom 0040000h 003ffffh 0000000h 00fffffh
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 86 (b) internal rom/internal flash memory area (384 kb) 384 kb are allocated to addresses 0000000h to 005ffffh of the following versions. accessing addresses 0060000h to 00fffffh is prohibited. ? pd703261, 703261y, 703271, 703271y, 703281, 703281y, 70f3261, 70f3261y, 70f3271, 70f3271y, 70f3281, 70f3281y figure 3-6. internal rom/internal flash memory area (384 kb) access-prohibited area internal rom/ internal flash memory 0060000h 005ffffh 0000000h 00fffffh (c) internal rom (512 kb) 512 kb are allocated to addresses 0000000h to 007ffffh of the following versions. accessing addresses 0080000h to 00fffffh is prohibited. ? pd703262, 703262y, 703272, 703272y, 703282, 703282y, figure 3-7. internal rom area (512 kb) access-prohibited area internal rom 0080000h 007ffffh 0000000h 00fffffh
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 87 (d) internal rom/internal flash memory area (640 kb) 640 kb are allocated to addresses 0000000h to 009ffffh of the following versions. accessing addresses 00a0000h to 00fffffh is prohibited. ? pd703263, 703263y, 703273, 703273y, 703283, 703283y, 70f3263, 70f3263y, 70f3273, 70f3273y, 70f3283, 70f3283y figure 3-8. internal rom/internal flash memory area (640 kb) access-prohibited area internal rom/ internal flash memory 00a0000h 009ffffh 0000000h 00fffffh
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 88 table 3-3. interrupt/exception table first address of interrupt/ exception table interrupt/ exception source first address of interrupt/ exception table interrupt/ exception source 00000000h reset 00000230h inttp4cc0 00000010h nmi 00000240h inttp4cc1 00000020h intwdt2 00000250h inttp5ov 0000004nh trap0n (n = 0 to f) 00000260h inttp5cc0 0000005nh trap1n (n = 0 to f) 00000270h inttp5cc1 00000060h ilgop/dbg0 00000280h inttm0eq0 00000080h intlvi 00000290h intcb0r/intiic1 note 1 00000090h intp0 000002a0h intcb0t 000000a0h intp1 000002b0h intcb1r 000000b0h intp2 000002c0h intcb1t 000000c0h intp3 000002d0h intcb2r 000000d0h intp4 000002e0h intcb2t 000000e0h intp5 000002f0h intcb3r 000000f0h intp6 00000300h intcb3t 00000100h intp7 00000310h intua0r/intcb4r 00000110h inttq0ov 00000320h intua0t/intcb4t 00000120h inttq0cc0 00000330h intua1r/intiic2 note 1 00000130h inttq0cc1 00000340h intua1t 00000140h inttq0cc2 00000350h intua2r/intiic0 note 1 00000150h inttq0cc3 00000360h intua2t 00000160h inttp0ov 00000370h intad 00000170h inttp0cc0 00000380h intdma0 00000180h inttp0cc1 00000390h intdma1 00000190h inttp1ov 000003a0h intdma2 000001a0h inttp1cc0 000003b0h intdma3 000001b0h inttp1cc1 000003c0h intkr 000001c0h inttp2ov 000003d0h intwti 000001d0h inttp2cc0 000003e0h intwt 000001e0h inttp2cc1 000003f0h intc0err note 2 /interr note 3 000001f0h inttp3ov 00000400h intc0wup note 2 /intsta note 3 00000200h inttp3cc0 00000410h intc0rec note 2 /intie1 note 3 00000210h inttp3cc1 00000420h intc0trx note 2 /intie2 note 3 00000220h inttp4ov ?? notes 1. i 2 c bus version only 2. can controller version only 3. iebus controller version only
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 89 (2) internal ram area up to 60 kb are reserved as the internal ram area. (a) internal ram (24 kb) 24 kb are allocated to addresses 3ff9000h to 3ffefffh of the following versions. accessing addresses 3ff0000h to 3ff8fffh is prohibited. ? pd703260, 703260y, 703270, 703270y, 703280, 703280y figure 3-9. internal ram area (24 kb) access-prohibited area internal ram 3ff9000h 3ff8fffh 3ff0000h 3ffefffh
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 90 (b) internal ram (32 kb) 32 kb are allocated to addresses 3ff7000h to 3ffefffh of the following versions. accessing addresses 3ff0000h to 3ff6fffh is prohibited. ? pd703261, 703261y, 703271, 703271y, 703281, 703281y, 70f3261, 70f3261y, 70f3271, 70f3271y, 70f3281, 70f3281y figure 3-10. internal ram area (32 kb) access-prohibited area internal ram 3ff7000h 3ff6fffh 3ff0000h 3ffefffh (c) internal ram (40 kb) 40 kb are allocated to addresses 3ff5000h to 3ffefffh of the following versions. accessing addresses 3ff0000h to 3ff4fffh is prohibited. ? pd703262, 703262y, 703272, 703272y, 703282, 703282y, figure 3-11. internal ram area (40 kb) access-prohibited area internal ram 3ff5000h 3ff4fffh 3ff0000h 3ffefffh
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 91 (d) internal ram area (48 kb) 48 kb are allocated to addresses 3ff3000h to 3ffefffh of the following versions. accessing addresses 3ff0000h to 3ff2fffh is prohibited. ? pd703263, 703263y, 703273, 703273y, 703283, 703283y, 70f3263, 70f3263y, 70f3273, 70f3273y, 70f3283, 70f3283y figure 3-12. internal ram area (48 kb) access prohibited area internal ram 3ff3000h 3ff2fffh 3ff0000h 3ffefffh
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 92 (3) on-chip peripheral i/o area 4 kb of addresses 3fff000h to 3ffffffh are reserved as the on-chip peripheral i/o area. figure 3-13. on-chip peripheral i/o area on-chip peripheral i/o area (4 kb) 3ffffffh 3fff000h peripheral i/o registers that have functions to specify the operation mode for and monitor the status of the on- chip peripheral i/o are mapped to the on-chip peripheral i/o area. program cannot be fetched from this area. cautions 1. when a register is accessed in word units, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read, and data is written to the lower 8 bits. 3. addresses not defined as registers are reserved for future expansion. the operation is undefined and not guaranteed when these addresses are accessed. (4) external memory area 15 mb (0100000h to 0ffffffh) are allocated as the external memory area. for details, see chapter 5 bus control function . caution the v850es/sg2 has 22 address pins (a0 to a21), so the external memory area appears as a repeated 4 mb image. in this case, it is necessary that ev dd = bv dd = v dd .
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 93 3.4.6 recommended use of address space the architecture of the v850es/sg2 requires that a register that serves as a pointer be secured for address generation when operand data in the data space is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. because the number of general-purpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, therefore, a 64 mb space of contiguous addresses starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the program space, access following addresses. ram size access address 48 kb 3ff3000h to 3ffefffh 40 kb 3ff5000h to 3ffefffh 32 kb 3ff7000h to 3ffefffh 24 kb 3ff9000h to 3ffefffh
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 94 (2) data space with the v850es/sg2, it seems that there are sixty-four 64 mb address spaces on the 4 gb cpu address space. therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. example : pd703261, 703261y internal rom area on-chip peripheral i/o area internal ram area 3 2 kb 4 kb 28 kb (r = ) 0005ffffh 00007fffh 00000000h fffff000h ffffefffh ffff8000h (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st disp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the resources, including the internal hardware, can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers dedicated to pointers.
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 95 figure 3-14. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory use prohibited external memory use prohibited internal ram on-chip peripheral i/o note program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh fffec000h fffebfffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ff7000h 03ff6fffh 03fec000h 03febfffh 01000000h 00ffffffh 00060000h 0005ffffh 00100000h 000fffffh 00000000h xfffffffh xffff000h xfffefffh xfff7000h xfff6fffh xffec000h xffebfffh x0100000h x00fffffh x0000000h note access to this area is prohibited. to access the on-chip peripheral i/o in this area, specify addresses ffff000h to fffffffh. remarks 1. indicates the recommended area. 2. this figure is the recommended memory map of the pd703261 and 703261y.
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 96 3.4.7 peripheral i/o registers (1/11) manipulatable bits address function register name symbol r/w 1816 default value fffff004h port dl pdl undefined fffff004h port dll pdll ? undefined fffff005h port dlh pdlh ? undefined fffff006h port dh pdh ? undefined fffff00ah port ct pct ? undefined fffff00ch port cm pcm ? undefined fffff024h port mode register dl pmdl ffffh fffff024h port mode register dll pmdll ? ffh fffff025h port mode register dlh pmdlh ? ffh fffff026h port mode register dh pmdh ? ffh fffff02ah port mode register ct pmct ? ffh fffff02ch port mode register cm pmcm ? ffh fffff044h port mode control register dl pmcdl 0000h fffff044h port mode control register dll pmcdll ? 00h fffff045h port mode control register dlh pmcdlh ? 00h fffff046h port mode control register dh pmcdh ? 00h fffff04ah port mode control register ct pmcct ? 00h fffff04ch port mode control register cm pmccm ? 00h fffff064h peripheral i/o area select control register bpc note 0000h fffff066h bus size configuration register bsc 5555h fffff06eh system wait control register vswc 77h fffff080h dma source address register 0l dsa0l undefined fffff082h dma source address register 0h dsa0h undefined fffff084h dma destination address register 0l dda0l undefined fffff086h dma destination address register 0h dda0h undefined fffff088h dma source address register 1l dsa1l undefined fffff08ah dma source address register 1h dsa1h undefined fffff08ch dma destination address register 1l dda1l undefined fffff08eh dma destination address register 1h dda1h undefined fffff090h dma source address register 2l dsa2l undefined fffff092h dma source address register 2h dsa2h undefined fffff094h dma destination address register 2l dda2l undefined fffff096h dma destination address register 2h dda2h undefined fffff098h dma source address register 3l dsa3l undefined fffff09ah dma source address register 3h dsa3h undefined fffff09ch dma destination address register 3l dda3l undefined fffff09eh dma destination address register 3h dda3h undefined fffff0c0h dma transfer count register 0 dbc0 undefined fffff0c2h dma transfer count register 1 dbc1 undefined fffff0c4h dma transfer count register 2 dbc2 undefined fffff0c6h dma transfer count register 3 dbc3 r/w undefined note can controller version only
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 97 (2/11) manipulatable bits address function register name symbol r/w 1816 default value fffff0d0h dma addressing control register 0 dadc0 0000h fffff0d2h dma addressing control register 1 dadc1 0000h fffff0d4h dma addressing control register 2 dadc2 0000h fffff0d6h dma addressing control register 3 dadc3 0000h fffff0e0h dma channel control register 0 dchc0 ? 00h fffff0e2h dma channel control register 1 dchc1 ? 00h fffff0e4h dma channel control register 2 dchc2 ? 00h fffff0e6h dma channel control register 3 dchc3 ? 00h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ? ffh fffff101h interrupt mask register 0h imr0h ? ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ? ffh fffff103h interrupt mask register 1h imr1h ? ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ? ffh fffff105h interrupt mask register 2h imr2h ? ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ? ffh fffff107h interrupt mask register 3h imr3h ? ffh fffff110h interrupt control register lviic ? 47h fffff112h interrupt control register pic0 ? 47h fffff114h interrupt control register pic1 ? 47h fffff116h interrupt control register pic2 ? 47h fffff118h interrupt control register pic3 ? 47h fffff11ah interrupt control register pic4 ? 47h fffff11ch interrupt control register pic5 ? 47h fffff11eh interrupt control register pic6 ? 47h fffff120h interrupt control register pic7 ? 47h fffff122h interrupt control register tq0ovic ? 47h fffff124h interrupt control register tq0ccic0 ? 47h fffff126h interrupt control register tq0ccic1 ? 47h fffff128h interrupt control register tq0ccic2 ? 47h fffff12ah interrupt control register tq0ccic3 ? 47h fffff12ch interrupt control register tp0ovic ? 47h fffff12eh interrupt control register tp0ccic0 ? 47h fffff130h interrupt control register tp0ccic1 ? 47h fffff132h interrupt control register tp1ovic ? 47h fffff134h interrupt control register tp1ccic0 ? 47h fffff136h interrupt control register tp1ccic1 ? 47h fffff138h interrupt control register tp2ovic ? 47h fffff13ah interrupt control register tp2ccic0 ? 47h fffff13ch interrupt control register tp2ccic1 r/w ? 47h
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 98 (3/11) manipulatable bits address function register name symbol r/w 1816 default value fffff13eh interrupt control register tp3ovic ? 47h fffff140h interrupt control register tp3ccic0 ? 47h fffff142h interrupt control register tp3ccic1 ? 47h fffff144h interrupt control register tp4ovic ? 47h fffff146h interrupt control register tp4ccic0 ? 47h fffff148h interrupt control register tp4ccic1 ? 47h fffff14ah interrupt control register tp5ovic ? 47h fffff14ch interrupt control register tp5ccic0 ? 47h fffff14eh interrupt control register tp5ccic1 ? 47h fffff150h interrupt control register tm0eqic0 ? 47h fffff152h interrupt control register cb0ric/iicic1 note 1 ? 47h fffff154h interrupt control register cb0tic ? 47h fffff156h interrupt control register cb1ric ? 47h fffff158h interrupt control register cb1tic ? 47h fffff15ah interrupt control register cb2ric ? 47h fffff15ch interrupt control register cb2tic ? 47h fffff15eh interrupt control register cb3ric ? 47h fffff160h interrupt control register cb3tic ? 47h fffff162h interrupt control register ua0ric/cb4ric ? 47h fffff164h interrupt control register ua0tic/cb4tic ? 47h fffff166h interrupt control register ua1ric/iicic2 note 1 ? 47h fffff168h interrupt control register ua1tic ? 47h fffff16ah interrupt control register ua2ric/iicic0 note 1 ? 47h fffff16ch interrupt control register ua2tic ? 47h fffff16eh interrupt control register adic ? 47h fffff170h interrupt control register dmaic0 ? 47h fffff172h interrupt control register dmaic1 ? 47h fffff174h interrupt control register dmaic2 ? 47h fffff176h interrupt control register dmaic3 ? 47h fffff178h interrupt control register kric ? 47h fffff17ah interrupt control register wtiic ? 47h fffff17ch interrupt control register wtic ? 47h fffff17eh interrupt control register erric0 note 2 / erric note 3 ? 47h fffff180h interrupt control register wupic0 note 2 / staic note 3 ? 47h fffff182h interrupt control register recic0 note 2 / ieic1 note 3 ? 47h fffff184h interrupt control register trxic0 note 2 / ieic2 note 3 r/w ? 47h notes 1. i 2 c bus version (y version) only 2. can controller version only 3. iebus controller version only
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 99 (4/11) manipulatable bits address function register name symbol r/w 1816 default value fffff1fah in-service priority register ispr r ? 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc ? 00h fffff200h a/d converter mode register 0 ada0m0 ? 00h fffff201h a/d converter mode register 1 ada0m1 ? 00h fffff202h a/d converter channel specification register ada0s ? 00h fffff203h a/d converter mode register 2 ada0m2 ? 00h fffff204h power-fail compare mode register ada0pfm ? 00h fffff205h power-fail compare threshold value register ada0pft r/w ? 00h fffff210h a/d conversion result register 0 ada0cr0 undefined fffff211h a/d conversion result register 0h ada0crh0 undefined fffff212h a/d conversion result register 1 ada0cr1 undefined fffff213h a/d conversion result register 1h ada0crh1 undefined fffff214h a/d conversion result register 2 ada0cr2 undefined fffff215h a/d conversion result register 2h ada0crh2 undefined fffff216h a/d conversion result register 3 ada0cr3 undefined fffff217h a/d conversion result register 3h ada0crh3 undefined fffff218h a/d conversion result register 4 ada0cr4 undefined fffff219h a/d conversion result register 4h ada0crh4 undefined fffff21ah a/d conversion result register 5 ada0cr5 undefined fffff21bh a/d conversion result register 5h ada0crh5 undefined fffff21ch a/d conversion result register 6 ada0cr6 undefined fffff21dh a/d conversion result register 6h ada0crh6 undefined fffff21eh a/d conversion result register 7 ada0cr7 undefined fffff21fh a/d conversion result register 7h ada0crh7 undefined fffff220h a/d conversion result register 8 ada0cr8 undefined fffff221h a/d conversion result register 8h ada0crh8 undefined fffff222h a/d conversion result register 9 ada0cr9 undefined fffff223h a/d conversion result register 9h ada0crh9 undefined fffff224h a/d conversion result register 10 ada0cr10 undefined fffff225h a/d conversion result register 10h ada0crh10 undefined fffff226h a/d conversion result register 11 ada0cr11 undefined fffff227h a/d conversion result register 11h ada0crh11 r undefined fffff280h d/a converter conversion value setting register 0 da0cs0 00h fffff281h d/a converter conversion value setting register 1 da0cs1 00h fffff282h d/a converter mode register da0m ? 00h fffff300h key return mode register krm ? 00h fffff308h selector operation control register selcnt ? 00h fffff310h crc input register crcin 00h fffff312h crc data register crcd 0000h fffff318h noise elimination control register nfc 00h fffff320h brg1 prescaler mode register prsm1 r/w 00h
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 100 (5/11) manipulatable bits address function register name symbol r/w 1816 default value fffff321h brg1 prescaler compare register prscm1 00h fffff324h brg2 prescaler mode register prsm2 00h fffff325h brg2 prescaler compare register prscm2 00h fffff328h brg3 prescaler mode register prsm3 00h fffff329h brg3 prescaler compare register prscm3 00h fffff340h iic division clock select register ocks0 note 1 00h fffff344h iic division clock select register ocks1 note 1 00h fffff348h iebus clock select register ocks2 note 2 00h fffff360h iebus control register bcr note 2 ? 00h fffff361h iebus power save register psr note 2 r/w ? 00h fffff362h iebus slave status register ssr note 2 81h fffff363h iebus unit status register usr note 2 r 00h fffff364h iebus interrupt status register isr note 2 ? 00h fffff365h iebus error status register esr note 2 ? 00h fffff366h iebus unit address register uar note 2 0000h fffff368h iebus slave address register sar note 2 r/w 0000h fffff36ah iebus partner address register par note 2 0000h fffff36ch iebus receive slave address register rsa note 2 r 0000h fffff36eh iebus control data register cdr note 2 00h fffff36fh iebus telegraph length register dlr note 2 01h fffff370h iebus data register dr note 2 r/w 00h fffff371h iebus field status register fsr note 2 00h fffff372h iebus success count register scr note 2 01h fffff373h iebus communication count register ccr note 2 r 20h fffff400h port 0 p0 ? undefined fffff402h port 1 p1 ? undefined fffff406h port 3 p3 undefined fffff406h port 3l p3l ? undefined fffff407h port 3h p3h ? undefined fffff408h port 4 p4 ? undefined fffff40ah port 5 p5 ? undefined fffff40eh port 7l p7l ? undefined fffff40fh port 7h p7h ? undefined fffff412h port 9 p9 undefined fffff412h port 9l p9l ? undefined fffff413h port 9h p9h ? undefined fffff420h port mode register 0 pm0 ? ffh fffff422h port mode register 1 pm1 ? ffh fffff426h port mode register 3 pm3 ffffh fffff426h port mode register 3l pm3l ? ffh fffff427h port mode register 3h pm3h r/w ? notes 1. i 2 c bus version (y version) only 2. iebus controller version only
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 101 (6/11) manipulatable bits address function register name symbol r/w 1816 default value fffff428h port mode register 4 pm4 ? ffh fffff42ah port mode register 5 pm5 ? ffh fffff42eh port mode register 7l pm7l ? ffh fffff42fh port mode register 7h pm7h ? ffh fffff432h port mode register 9 pm9 ffffh fffff432h port mode register 9l pm9l ? ffh fffff433h port mode register 9h pm9h ? ffh fffff440h port mode control register 0 pmc0 ? 00h fffff446h port mode control register 3 pmc3 0000h fffff446h port mode control register 3l pmc3l ? 00h fffff447h port mode control register 3h pmc3h ? 00h fffff448h port mode control register 4 pmc4 ? 00h fffff44ah port mode control register 5 pmc5 ? 00h fffff452h port mode control register 9 pmc9 0000h fffff452h port mode control register 9l pmc9l ? 00h fffff453h port mode control register 9h pmc9h ? 00h fffff460h port function control register 0 pfc0 ? 00h fffff466h port function control register 3 pfc3 0000h fffff466h port function control register 3l pfc3l ? 00h fffff467h port function control register 3h pfc3h ? 00h fffff468h port function control register 4 pfc4 ? 00h fffff46ah port function control register 5 pfc5 ? 00h fffff472h port function control register 9 pfc9 0000h fffff472h port function control register 9l pfc9l ? 00h fffff473h port function control register 9h pfc9h ? 00h fffff484h data wait control register 0 dwc0 7777h fffff488h address wait control register awc ffffh fffff48ah bus cycle control register bcc aaaah fffff540h tmq0 control register 0 tq0ctl0 ? 00h fffff541h tmq0 control register 1 tq0ctl1 ? 00h fffff542h tmq0 i/o control register 0 tq0ioc0 ? 00h fffff543h tmq0 i/o control register 1 tq0ioc1 ? 00h fffff544h tmq0 i/o control register 2 tq0ioc2 ? 00h fffff545h tmq0 option register tq0opt0 ? 00h fffff546h tmq0 capture/compare register 0 tq0ccr0 0000h fffff548h tmq0 capture/compare register 1 tq0ccr1 0000h fffff54ah tmq0 capture/compare register 2 tq0ccr2 0000h fffff54ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff54eh tmq0 read buffer register tq0cnt r 0000h
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 102 (7/11) manipulatable bits address function register name symbol r/w 1816 default value fffff590h tmp0 control register 0 tp0ctl0 ? 00h fffff591h tmp0 control register 1 tp0ctl1 ? 00h fffff592h tmp0 i/o control register 0 tp0ioc0 ? 00h fffff593h tmp0 i/o control register 1 tp0ioc1 ? 00h fffff594h tmp0 i/o control register 2 tp0ioc2 ? 00h fffff595h tmq0 option register tp0opt0 ? 00h fffff596h tmq0 capture/compare register 0 tp0ccr0 0000h fffff598h tmq0 capture/compare register 1 tp0ccr1 r/w 0000h fffff59ah tmp0 counter register tp0cnt r 0000h fffff5a0h tmp1 control register 0 tp1ctl0 ? 00h fffff5a1h tmp1 control register 1 tp1ctl1 ? 00h fffff5a2h tmp1 i/o control register 0 tp1ioc0 ? 00h fffff5a3h tmp1 i/o control register 1 tp1ioc1 ? 00h fffff5a4h tmp1 i/o control register 2 tp1ioc2 ? 00h fffff5a5h tmp1 option register tp1opt0 ? 00h fffff5a6h tmp1 capture/compare register 0 tp1ccr0 0000h fffff5a8h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff5aah tmp1 counter register tp1cnt r 0000h fffff5b0h tmp2 control register 0 tp2ctl0 ? 00h fffff5b1h tmp2 control register 1 tp2ctl1 ? 00h fffff5b2h tmp2 i/o control register 0 tp2ioc0 ? 00h fffff5b3h tmp2 i/o control register 1 tp2ioc1 ? 00h fffff5b4h tmp2 i/o control register 2 tp2ioc2 ? 00h fffff5b5h tmp2 option register tp2opt0 ? 00h fffff5b6h tmp2 capture/compare register 0 tp2ccr0 0000h fffff5b8h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff5bah tmp2 counter register tp2cnt r 0000h fffff5c0h tmp3 control register 0 tp3ctl0 ? 00h fffff5c1h tmp3 control register 1 tp3ctl1 ? 00h fffff5c2h tmp3 i/o control register 0 tp3ioc0 ? 00h fffff5c3h tmp3 i/o control register 1 tp3ioc1 ? 00h fffff5c4h tmp3 i/o control register 2 tp3ioc2 ? 00h fffff5c5h tmp3 option register tp3opt0 ? 00h fffff5c6h tmp3 capture/compare register 0 tp3ccr0 0000h fffff5c8h tmp3 capture/compare register 1 tp3ccr1 r/w 0000h fffff5cah tmp3 counter register tp3cnt r 0000h fffff5d0h tmp4 control register 0 tp4ctl0 ? 00h fffff5d1h tmp4 control register 1 tp4ctl1 ? 00h fffff5d2h tmp4 i/o control register 0 tp4ioc0 ? 00h fffff5d3h tmp4 i/o control register 1 tp4ioc1 ? 00h fffff5d4h tmp4 i/o control register 2 tp4ioc2 ? 00h fffff5d5h tmp4 option register tp4opt0 ? 00h fffff5d6h tmp4 capture/compare register 0 tp4ccr0 0000h fffff5d8h tmp4 capture/compare register 1 tp4ccr1 r/w 0000h
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 103 (8/11) manipulatable bits address function register name symbol r/w 18632 default value fffff5dah tmp4 counter register tp4cnt r 0000h fffff5e0h tmp5 control register 0 tp5ctl0 ? 00h fffff5e1h tmp5 control register 1 tp5ctl1 ? 00h fffff5e2h tmp5 i/o control register 0 tp5ioc0 ? 00h fffff5e3h tmp5 i/o control register 1 tp5ioc1 ? 00h fffff5e4h tmp5 i/o control register 2 tp5ioc2 ? 00h fffff5e5h tmp5 option register tp5opt0 ? 00h fffff5e6h tmp5 capture/compare register 0 tp5ccr0 0000h fffff5e8h tmp5 capture/compare register 1 tp5ccr1 r/w 0000h fffff5eah tmp5 counter register tp5cnt r 0000h fffff680h watch timer operation mode register wtm ? 00h fffff690h tmm0 control register 0 tm0ctl0 ? 00h fffff694h tmm0 compare register 0 tm0cmp0 0000h fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 ? 67h fffff6d1h watchdog timer enable register wdte 9ah fffff6e0h real-time output buffer register 0l rtbl0 ? 00h fffff6e2h real-time output buffer register 0h rtbh0 ? 00h fffff6e4h real-time output port mode register 0 rtpm0 ? 00h fffff6e5h real-time output port control register 0 rtpc0 ? 00h fffff706h port function control expansion register 3l pfce3l ? 00h fffff70ah port function control expansion register 5 pfce5 ? 00h fffff712h port function control expansion register 9 pfce9 0000h fffff712h port function control expansion register 9l pfce9l ? 00h fffff713h port function control expansion register 9h pfce9h ? 00h fffff802h system status register sys ? 00h fffff80ch ring-osc mode register rcm ? 00h fffff810h dma trigger factor register 0 dtfr0 ? 00h fffff812h dma trigger factor register 1 dtfr1 ? 00h fffff814h dma trigger factor register 2 dtfr2 ? 00h fffff816h dma trigger factor register 3 dtfr3 ? 00h fffff820h power save mode register psmr ? 00h fffff822h clock control register ckc r/w ? 0ah fffff824h lock register lockr r 00h fffff828h processor clock control register pcc ? 03h fffff82ch pll control register pllctl r/w ? 01h fffff82eh cpu operation clock status registe ccls r ? 00h fffff840h correction address register 0 corad0 00000000h fffff840h correction address register 0l corad0l 0000h fffff842h correction address register 0h corad0h r/w 0000h
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 104 (9/11) manipulatable bits address function register name symbol r/w 1 8 16 32 default value fffff844h correction address register 1 corad1 00000000h fffff844h correction address register 1l corad1l 0000h fffff846h correction address register 1h corad1h 0000h fffff848h correction address register 2 corad2 00000000h fffff848h correction address register 2l corad2l 0000h fffff84ah correction address register 2h corad2h 0000h fffff84ch correction address register 3 corad3 00000000h fffff84ch correction address register 3l corad3l 0000h fffff84eh correction address register 3h corad3h 0000h fffff870h clock monitor mode register clm ? 00h fffff880h correction control register corcn ? 0000h fffff888h reset source flag register resf ? 00h fffff890h low-voltage detection register lvim ? 00h fffff891h low-voltage detection level select register lvis 00h fffff892h internal ram data status register rams ? 01h fffff8b0h prescaler mode register prsm0 0000h fffff8b1h prescaler compare register prscm0 00h fffff9fch on-chip debug alternate-function pin setting register ocdm note ? 01h fffffa00h uarta0 control register 0 ua0ctl0 ? 00h fffffa01h uarta0 control register 1 ua0ctl1 01h fffffa02h uarta0 control register 2 ua0ctl2 10h fffffa03h uarta0 option control register 0 ua0opt0 ? 00h fffffa04h uarta0 status register ua0str r/w ? ffh fffffa06h uarta0 receive data register ua0rx r 14h fffffa07h uarta0 transmit data register ua0tx 00h fffffa10h uarta1 control register 0 ua1ctl0 ? ffh fffffa11h uarta1 control register 1 ua1ctl1 ffh fffffa12h uarta1 control register 2 ua1ctl2 10h fffffa13h uarta1 option control register 0 ua1opt0 ? 00h fffffa14h uarta1 status register ua1str r/w ? ffh fffffa16h uarta1 receive data register ua1rx r 14h fffffa17h uarta1 transmit data register ua1tx 00h fffffa20h uarta2 control register 0 ua2ctl0 ? ffh fffffa21h uarta2 control register 1 ua2ctl1 ffh fffffa22h uarta2 control register 2 ua2ctl2 10h fffffa23h uarta2 option control register 0 ua2opt0 ? 00h fffffa24h uarta2 status register ua2str r/w ? ffh fffffa26h uarta2 receive data register ua2rx r ffh fffffa27h uarta2 transmit data register ua2tx 14h fffffc00h external interrupt falling edge specification register 0 intf0 ? 00h fffffc06h external interrupt falling edge specification register 3l intf3l ? 00h fffffc13h external interrupt falling edge specification register 9h intf9h r/w ? 00h note flash memory version only
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 105 (10/11) manipulatable bits address function register name symbol r/w 1816 default value fffffc20h external interrupt rising edge specification register 0 intr0 ? 00h fffffc26h external interrupt rising edge specification register 3l intr3l ? 00h fffffc33h external interrupt rising edge specification register 9h intr9h ? 00h fffffc60h port function control register 0 pf0 ? 00h fffffc66h port function control register 3 pf3 0000h fffffc66h port function control register 3l pf3l ? 00h fffffc67h port function control register 3h pf3h ? 00h fffffc68h port function control register 4 pf4 ? 00h fffffc6ah port function control register 5 pf5 ? 00h fffffc72h port function control register 9 pf9 0000h fffffc72h port function control register 9l pf9l ? 00h fffffc73h port function control register 9h pf9h ? 00h fffffd00h csib0 control register 0 cb0ctl0 ? 01h fffffd01h csib0 control register 1 cb0ctl1 ? 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str r/w ? 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 01h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 ? 00h fffffd11h csib1 control register 1 cb1ctl1 ? 00h fffffd12h csib1 control register 2 cb1ctl2 0000h fffffd13h csib1 status register cb1str r/w ? 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl 00h fffffd20h csib2 control register 0 cb2ctl0 ? 01h fffffd21h csib2 control register 1 cb2ctl1 ? 00h fffffd22h csib2 control register 2 cb2ctl2 00h fffffd23h csib2 status register cb2str r/w ? 00h fffffd24h csib2 receive data register cb2rx 0000h fffffd24h csib2 receive data register l cb2rxl r 00h fffffd26h csib2 transmit data register cb2tx 0000h fffffd26h csib2 transmit data register l cb2txl 00h fffffd30h csib3 control register 0 cb3ctl0 ? 01h fffffd31h csib3 control register 1 cb3ctl1 ? 00h fffffd32h csib3 control register 2 cb3ctl2 00h fffffd33h csib3 status register cb3str r/w ? 00h fffffd34h csib3 receive data register cb3rx 0000h fffffd34h csib3 receive data register l cb3rxl r 00h
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 106 (11/11) manipulatable bits address function register name symbol r/w 1816 default value fffffd36h csib3 transmit data register cb3tx 0000h fffffd36h csib3 transmit data register l cb3txl 00h fffffd40h csib4 control register 0 cb4ctl0 ? 01h fffffd41h csib4 control register 1 cb4ctl1 ? 00h fffffd42h csib4 control register 2 cb4ctl2 00h fffffd43h csib4 status register cb4str r/w ? 00h fffffd44h csib4 receive data register cb4rx 0000h fffffd44h csib4 receive data register l cb4rxl r 00h fffffd46h csib4 transmit data register cb4tx 0000h fffffd46h csib4 transmit data register l cb4txl 00h fffffd80h iic shift register 0 iic0 note 00h fffffd82h iic control register 0 iicc0 note ? 00h fffffd83h slave address register 0 sva0 note 00h fffffd84h iic clock select register 0 iiccl0 note ? 00h fffffd85h iic function expansion register 0 iicx0 note r/w ? 00h fffffd86h iic status register 0 iics0 note r ? 00h fffffd8ah iic flag register 0 iicf0 note ? 00h fffffd90h iic shift register 1 iic1 note 00h fffffd92h iic control register 1 iicc1 note ? 00h fffffd93h slave address register 1 sva1 note 00h fffffd94h iic clock select register 1 iiccl1 note ? 00h fffffd95h iic function expansion register 1 iicx1 note r/w ? 00h fffffd96h iic status register 1 iics1 note r ? 00h fffffd9ah iic flag register 1 iicf1 note ? 00h fffffda0h iic shift register 2 iic2 note 00h fffffda2h iic control register 2 iicc2 note ? 00h fffffda3h iic slave address register 2 sva2 note 00h fffffda4h iic clock select register 2 iiccl2 note ? 00h fffffda5h iic function expansion register 2 iicx2 note r/w ? 00h fffffda6h iic status register 2 iics2 note r ? 00h fffffdaah iic flag register 2 iicf2 note ? 00h fffffdbeh external bus interface mode control register eximc r/w ? 00h note i 2 c bus version (y version) only
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 107 3.4.8 programmable peripheral i/o registers the peripheral i/o area select control register (bpc) is used for programmable peripheral i/o register area selection. (1) peripheral i/o area select control register (bpc) the bpc register can be read or written in 16-bit units. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address default value bpc pa15 0 pa13 pa12 pa11 pa10 pa09 pa08 pa07 pa06 pa05 pa04 pa03 pa02 pa01 pa00 fffff064h 0000h bit position bit name function enables/disables usage of programmable peripheral i/o area pa15 usage of programmable peripheral i/o area 0 usage of programmable peripheral i/o area disabled 1 usage of programmable peripheral i/o area disabled 15 pa15 13 to 0 pa13 to pa00 specify an address in programmable peripheral i/o area (correspond to a27 to a14, respectively). caution when setting the pa15 bit to 1, be sure to set the bpc register to 8ffbh. when clearing the pa15 bit to 0, be sure to set the bpc register to 0000h. for a list of the programmable peripheral i/o register areas, see table 19-17 control register access type and table 19-18 message buffer access type .
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 108 3.4.9 special registers special registers are registers that are protected from being written with illegal data due to a program hang-up. v850es/sg2 has the following eight (seven in mask rom version) special registers. ? power save control register (psc) ? clock control register (ckc) ? processor clock control register (pcc) ? clock monitor mode register (clm) ? reset source flag register (resf) ? low-voltage detection register (lvim) ? internal ram data status register (rams) ? on-chip debug mode setting register (ocdm) (flash memory version) in addition, a command register (prcdm) is provided to protect against a write access to the special registers so that the application system does not inadvertently stop due to a program hang-up. a write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the system status register (sys).
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 109 (1) setting data to special registers set data to the special registers in the following sequence. <1> disable dma operation. <2> prepare data to be set to the special register in a general-purpose register. <3> write the data prepared in <2> to the command register (prcmd). <3> write the setting data to the special register (by using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) <5> to <9> insert nop instructions (5 instructions). <10> enable dma operation if necessary. [example] with psc register (setting standby mode) st.b r11, psmr[r0] ; set psmr register (setting idle1, idle2, and software stop modes). <1>clr1 0, dchcn[r0] ; disable dma operation. n = 0 to 3 <2>mov0x02, r10 <3>st.b r10, prcmd[r0] ; write prcmd register. <4>st.b r10, psc[r0] ; set psc register. <5>nop ; dummy instruction <6>nop ; dummy instruction <7>nop ; dummy instruction <8>nop ; dummy instruction <9>nop ; dummy instruction <10>set1 0, dchcn[r0] ; enable dma operation. n = 0 to 3 (next instruction) there is no special sequence to read a special register. cautions 1. when a store instruction is executed to store data in the command register, interrupts are not acknowledged. this is because it is assumed that steps <3> and <4> above are performed by successive store instructions. if another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction. 2. although dummy data is written to the prcmd register, use the same general-purpose register used to set the special register (<4> in example) to write data to the prcmd register (<3> in example). the same applies when a general-purpose register is used for addressing. 3. five nop instructions or more must be inserted immediately after setting the idle1 mode, idle2 mode, or software stop mode (by setting the stp bit of the psc register to 1).
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 110 (2) command register (prcmd) the command register (prcmd) is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang- up. the first write access to a special register is valid after data has been written in advance to the prcmd register. in this way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write access. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 111 (3) system status register (sys) status flags that indicate the operation status of the overall system are allocated to this register. this register can be read or written in 8-bit or 1-bit units. 0 protection error did not occur protection error occurred prerr 0 1 detects protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the prerr flag operates under the following conditions. (a) set condition (prerr flag = 1) (i) when data is written to a special register without writing anything to the prcmd register (when <4> is executed without executing <3> in 3.4.9 (1) setting data to special registers ) (ii) when data is written to an on-chip peripheral i/o register other than a special register (including execution of a bit manipulation instruction) after writing data to the prcmd register (if <4> in 3.4.9 (1) setting data to special registers is not the setting of a special register) remark even if an on-chip peripheral i/o register is read (except by a bit manipulation instruction) between an operation to write the prcmd register and an operation to write a special register, the prerr flag is not set, and the set data can be written to the special register. (b) clear condition (prerr flag = 0) (i) when 0 is written to the prerr flag of the sys register (ii) when the system is reset cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write access to the prcmd register, the prerr bit is cleared to 0 (the write access takes precedence). 2. if data is written to the prcmd register, which is not a special register, immediately after a write access to the prcmd register, the prerr bit is set to 1.
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 112 3.4.10 notes be sure to set the following register first when using the v850es/sg2. ? system wait control register (vswc) ? on-chip debug mode register (ocdm) (flash memory version only) after setting the ocdm register, set the vswc register, and then set the other registers as necessary. when using the external bus, set each pin to the control mode by using the port-related registers after setting the above register. (1) system wait control register (vswc) the vswc register controls wait of bus access to the on-chip peripheral i/o registers. three clocks are required to access an on-chip peripheral i/o register (without a wait cycle). the v850es/sg2 requires wait cycles according to the operating frequency. set the following value to the vswc register in accordance with the frequency used. the vswc register can be read or written in 8-bit units (address: fffff06eh, default value: 77h). operating frequency (f clk ) set value of vswc number of waits 32 khz f clk < 16.6 mhz 00h 0 (no wait) 16.6 mhz f clk 20 mhz 01h 1 remark when any of the following registers is accessed, the register access is kept waiting if the hardware changes the contents of the register at the same time as the cpu accesses the register. consequently, it may take a longer time than usual to access an on-chip peripheral i/o register. peripheral function target register name timer p (n = 0 to 5) tpnccr0, tpnccr1, tpncnt timer q tq0ccr0, tq0ccr1, tq0ccr2, tq0ccr3, tq0cnt watchdog timer 2 wdtm2 real-time output function rtbl0, rtbh0 i 2 c bus (n = 0 to 2) iicsn a/d converter (n = 0 to 11) adam0, ada0crn, ada0crnh crc function crcd can controller each control register, each message buffer register
chapter 3 cpu function preliminary user ? s manual u16541ej1v0um 113 (2) on-chip debug mode register (ocdm) (flash memory version only) the ocdm register is used to switch between the normal operation mode and the on-chip debug mode. this register is a special register (see 3.4.9 special registers ). writing is possible only using a specific sequence so as to not overwrite setting contents by mistake due to inadvertent program loops, etc. when the ocdm0 bit is set to 1 and the drst pin input is high level, the on-chip d ebug m ode is selected. since after reset the initial value of the ocdm0 bit is 1, when not using the on-chip debug function, it is necessary to clear (0) the ocdm0 bit and maintain the drst pin at low level until the ocdm0 bit is cleared (the drst pin has a pull-down resistor (30 k ? typ.) in the buffer and therefore does not have to be fixed to low level from the external source. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0)). this register can be read or written in 8-bit or 1-bit units. 0 normal operation mode drst pin = low level: normal operation mode drst pin = high level: on-chip debug mode ocdm0 0 1 operation mode ocdm 0 0 0 0 0 0 ocdm0 after reset: 01h note r/w address: fffff9fch < > note this register holds the value 01h when reset is executed by the reset pin, or the value of the ocdm register when reset is executed by the wdt2res signal, clock monitor (clm), or low-voltage detector (lvi). figure 3-15. timing when on-chip debug function is not used maintain low level high-level i/o is possible after clearing of ocdm0 bit clearing of ocdm0 bit reset release reset ocdm0 p05/intp2/drst
preliminary user?s manual u16541ej1v0um 114 chapter 4 port functions 4.1 features { i/o ports: 84 { other peripheral function i/o pins can be alternatively used { input/output specifiable in 1-bit units 4.2 basic port configuration the v850es/sg2 features a total of 84 i/o ports consisting of ports 0, 1, 3, 4, 5, 7, 9, cm, ct, dh, and dl. the port configuration is shown below. figure 4-1. port configuration diagram p02 p06 port 0 pcm0 pcm3 port cm p90 p915 port 9 pct0 pct1 pct4 pct6 port ct pdh0 pdh5 port dh pdl0 pdl15 port dl p30 p39 port 3 port 1 p40 p42 port 4 p50 p55 port 5 p70 p711 port 7 p10 p11 caution ports 0, 3, 4, 5, and 9 are 5 v tolerant. table 4-1. i/o buffer power supplies for pins power supply corresponding pins av ref0 port 7 av ref1 port 0 bv dd port cm, port ct, port dh (bits 0 to 3), port dl ev dd port 0, port 3, port 4, port 5, port 9, port dh (bits 4, 5), reset
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 115 4.3 port configuration table 4-2. port configuration item configuration control register port mode register n (pmn: n = 0, 1, 3, 4, 5, 7, 9, cm, ct, dh, dl) port mode control register n (pmcn: n = 0, 3, 4, 5, 9, cm, ct, dh, dl) port function control register n (pfcn: n = 0, 3, 4, 5, 9) port function control expansion register n (pfcen: n = 3, 5, 9) port function register n (pfn: n = 0, 3, 4, 5, 9) external interrupt falling edge specification register n (intfn: n = 0, 3, 9) external interrupt rising edge specification register n (intrn: n = 0, 3, 9) ports i/o: 84 4.3.1 notes on setting port pins (1) set the registers of a port in the following sequence. <1> set port function control register n (pfcn) and port function control expansion register n (pfcen). <2> set port mode control register n (pmcn). <3> set external interrupt falling edge specification register n (intfn) and external interrupt rising edge specification register n (intrn). if the pfcn and pfcen registers are set after the pmcn register is set, an unexpected peripheral function may be selected while the pfcn and pfcen registers are being set. (2) the pfnm bit of the pfn register is valid only in the output mode (pmnm bit of pmn register = 0). in the input mode (pmn bit = 1), the value of the pfnm bit is not reflected in the buffer.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 116 4.3.2 port 0 port 0 is a 5-bit port for which i/o settings can be controlled in 1-bit units. (1) port 0 functions { port input/output data specifiable in 1-bit units specification made by port register 0 (p0) { port input/output specifiable in 1-bit units specification made by port mode register 0 (pm0) { port mode/control mode (alternate functions) specifiable in 1-bit units specification made by port mode control register 0 (pmc0) { control mode 1/control mode 2 specifiable in 1-bit units specification made by port function control register 0 (pfc0) { n-ch open-drain specifiable in 1-bit units specification made by port function register 0 (pf0) { valid edge of external interrupts (alternate function) specifiable in 1-bit units specification made by external interrupt falling edge specification register 0 (intf0) and external interrupt rising edge specification register 0 (intr0) port 0 includes the following alternate-function pins. table 4-3. port 0 alternate-function pins pin name alternate-function pin name i/o remark p02 nmi p03 intp0/adtrg p04 intp1 p05 intp2/drst note port 0 p06 intp3 i/o selectable as n-ch open-drain output note the p05 pin ? s alternate function is a pin for on-chip debugging (flash memory version only). after external reset, the p05/intp2/drst pin is initialized to the on-chip debugging pin (drst). when using the p05 pin as a port pin and not as an on-chip debugging pin, the following handling is required. <1> clear (0) the ocdm0 bit of the ocdm register (special register). if a high level is input to the drst pin when the on-chip debug function is not used and before the above processing is performed, malfunction (cpu deadlock) may occur. exercise care in handling the p05 pin. (the p05 pin has a pull-down resistor (30 k ? typ.) in the buffer and does not have to be fixed to low level by an external source. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0).)
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 117 (2) registers (a) port register 0 (p0) the p0 register is an 8-bit register that controls pin level read and output level write. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0 outputs 1 p0n 0 1 output data control (in output mode) (n = 2 to 6) p0 p06 p05 p04 p03 p02 0 0 after reset: undefined r/w address: fffff400h remarks 1. input mode: when port 0 (p0) is read, the pin levels at this time are read. writing to p0 writes the values to that port. this does not affect the input pins. output mode: when port 0 (p0) is read, the p0 values are read. writing to p0 writes the values to that port, and those values are immediately output. 2. the value of p0 is undefined (pin input level) when it is read in the input mode after reset. when p0 is read in the output mode, 00h (output latch value) is read. (b) port mode register 0 (pm0) the pm0 register is an 8-bit register that specifies input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. 1 output mode input mode pm0n 0 1 i/o mode control (n = 2 to 6) pm0 pm06 pm05 pm04 pm03 pm02 1 1 after reset: ffh r/w address: fffff420h
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 118 (c) port mode control register 0 (pmc0) the pmc0 register is an 8-bit register that specifies port or control mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 pmc0 pmc06 pmc05 pmc04 pmc03 pmc02 0 0 i/o port intp3 input pmc06 0 1 specification of p06 pin operation mode i/o port intp2 input pmc05 0 1 specification of p05 pin operation mode i/o port intp1 input pmc04 0 1 specification of p04 pin operation mode i/o port intp0/adtrg input pmc03 0 1 specification of p03 pin operation mode i/o port nmi input pmc02 0 1 specification of p02 pin operation mode after reset: 00h r/w address: fffff440h caution the p05/intp2/drst pin becomes the drst pin regardless of the value of the pmc05 bit when the ocdm0 bit of the ocdm register = 1. (d) port function control register 0 (pfc0) the pfc0 register is an 8-bit register that specifies control mode 1 or control mode 2. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. pfc0 after reset: 00h r/w address: fffff460h 0 0 0 0 pfc03 0 0 0 intp0 input adtrg input pfc03 0 1 specification of p03 pin operation mode in control mode
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 119 (e) port function register 0 (pf0) the pf0 register is an 8-bit register that specifies normal output or n-ch open-drain output. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 normal output n-ch open drain output pf0n 0 1 control of normal output or n-ch open-drain output (n = 2 to 6) pf0 pf06 pf05 pf04 pf03 pf02 0 0 after reset: 00h r/w address: fffffc60h (f) external interrupt falling edge specification register 0 (intf0) the intf0 register is an 8-bit register that specifies detection of the falling edge for the external interrupt pin. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions 1. when switching from the external interrupt function (alternate function) to the port function, edge detection may occur. therefore, set the port mode after setting intf0n bit = intr0n bit = 0. 2. an on-chip circuit for eliminating noise through analog delay is provided for external interrupt input. however, noise elimination by digital delay is selectable for intp3. 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 after reset: 00h r/w address: fffffc00h remark for details on valid edge specification, see table 4-4 .
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 120 (g) external interrupt rising edge specification register 0 (intr0) the intr0 register is an 8-bit register that specifies detection of the rising edge for the external interrupt pin. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions 1. when switching from the external interrupt function (alternate function) to the port function, edge detection may occur. therefore, set the port mode after setting intf0n bit = intr0n bit = 0. 2. an on-chip circuit for eliminating noise through analog delay is provided for external interrupt input. however, noise elimination by digital delay is selectable for intp3. 0 intr0 intr06 intr05 intr04 intr03 intr02 0 0 after reset: 00h r/w address: fffffc20h remark for details on valid edge specification, see table 4-4 . table 4-4. valid edge specification intf0n intr0n valid edge specification (n = 2 to 6) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges remark n = 2: control of nmi pin n = 3 to 6: control of intp0 to intp3 pins
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 121 4.3.3 port 1 port 1 is a 2-bit port for which i/o settings can be controlled in 1-bit units. (1) port 1 functions { port input/output data specifiable in 1-bit units specification made by port register 1 (p1) { port input/output specification in 1-bit units specification made by port mode register 1 (pm1) port 1 includes the following alternate-function pins. table 4-5. port 1 alternate-function pins pin name alternate-function pin name i/o remark p10 ano0 ? port 1 p11 ano1 output ?
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 122 (2) registers (a) port register 1 (p1) the p1 register is an 8-bit register that controls pin level read and output level write. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0 outputs 1 p1n 0 1 output data control (in output mode) (n = 0, 1) p1 0 0 0 0 0 p11 p10 after reset: undefined r/w address: fffff402h remarks 1. input mode: when port 1 (p1) is read, the pin levels at this time are read. writing to p1 writes the values to that port. this does not affect the input pins. output mode: when port 1 (p1) is read, the p1 values are read. writing to p1 writes the values to that port, and those values are immediately output. 2. the value of p1 is undefined (pin input level) when it is read in the input mode after reset. when p1 is read in the output mode, 00h (output latch value) is read. (b) port mode register 1 (pm1) the pm1 register is an 8-bit register that specifies input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. 1 output mode input mode pm1n 0 1 i/o mode control (n = 0, 1) pm1 1 1 1 1 1 pm11 pm10 after reset: ffh r/w address: fffff422h caution when using p10 and p11 as alternate functions (ano0, ano1), set the pm1 register = ffh.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 123 4.3.4 port 3 port 3 is a 10-bit port for which i/o settings can be controlled in 1-bit units. (1) port 3 functions { port input/output data specifiable in 1-bit units specification made by port register 3 (p3) { port input/output specifiable in 1-bit units specification made by port mode register 3 (pm3) { port mode/control mode (alternate functions) specifiable in 1-bit units specification made by port mode control register 3 (pmc3) { control mode specifiable in 1-bit units specification made by port function control register 3 (pfc3) and port function control expansion register 3l (pfce3l) { n-ch open-drain specifiable in 1-bit units specification made by port function register 3 (pf3) { valid edge of external interrupts (alternate function) specifiable in 1-bit units specification made by external interrupt falling edge specification register 3l (intf3l) and external interrupt rising edge specification register 3l (intr3l) port 3 includes the following alternate-function pins. table 4-6. port 3 alternate-function pins pin name alternate-function pin name i/o remark p30 txda0/sob4 p31 rxda0/intp7/sib4 p32 ascka0/sckb4/tip00/top00 p33 tip01/top01 p34 tip10/top10 p35 tip11/top11 p36 ctxd0 note 1 /ietx0 note 2 p37 crxd0 note 1 /ierx0 note 2 p38 txda2/sda00 note 3 port 3 p39 rxda2/scl00 note 3 i/o selectable as n-ch open-drain output notes 1. can controller version only 2. iebus controller version only 3. i 2 c bus version (y version) only
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 124 (2) registers (a) port register 3 (p3) the p3 register is a 16-bit register that controls pin level read and output level write. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the p3 register as the p3h register and the lower 8 bits as the p3l register, p3 can be read or written in 8-bit or 1-bit units. outputs 0 outputs 1 p3n 0 1 output data control (in output mode) (n = 0 to 9) p3 (p3h note ) after reset: undefined r/w address: p3 fffff406h, p3l fffff406h, p3h ffff407h 0 0 0 0 0 0 p39 p38 p37 p36 p35 p34 p33 p32 p31 p30 8 9 10 11 12 13 14 15 (p3l) note to read/write bits 8 to 15 of the p3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the p3h register. remarks 1. input mode: when port 3 (p3) is read, the pin levels at this time are read. writing to p3 writes the values to that port. this does not affect the input pins. output mode: when port 3 (p3) is read, the p3 values are read. writing to p3 writes the values to that port, and those values are immediately output. 2. the value of p3 is undefined (pin input level) when it is read in the input mode after reset. when p3 is read in the output mode, 0000h (output latch value) is read.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 125 (b) port mode register 3 (pm3) the pm3 register is a 16-bit register that specifies input or output mode. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pm3 register as the pm3h register and the lower 8 bits as the pm3l register, pm3 can be read or written in 8-bit or 1-bit units. reset input sets this register to ffffh. 1 output mode input mode pm3n 0 1 i/o mode control (n = 0 to 9) 1 1 1 1 1 pm39 pm38 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: pm3 fffff426h, pm3l fffff426h, pm3h fffff427h 8 9 10 11 12 13 14 15 pm3 (pm3h note ) (pm3l) note to read/write bits 8 to 15 of the pm3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pm3h register. (c) port mode control register 3 (pmc3) the pmc3 register is a 16-bit register that specifies port or control mode. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmc3 register as the pmc3h register and the lower 8 bits as the pmc3l register, pmc3 can be read or written in 8-bit or 1-bit units. reset input clears this register to 0000h.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 126 i/o port rxda2/scl00 i/o pmc39 0 1 specification of p39 pin operation mode in control mode i/o port txda2/sda00 i/o pmc38 0 1 specification of p38 pin operation mode in control mode after reset: 0000h r/w address: pmc3 fffff446h, pmc3l fffff446h, pmc3h fffff447h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 i/o port tip11/top11 i/o pmc35 0 1 specification of p35 pin operation mode in control mode i/o port tip10/top10 i/o pmc34 0 1 specification of p34 pin operation mode in control mode i/o port crxd0/ierx0 input pmc37 0 1 specification of p37 pin operation mode in control mode i/o port ctxd0/ietx0 output pmc36 0 1 specification of p36 pin operation mode in control mode i/o port tip01/top01 i/o pmc33 0 1 specification of p33 pin operation mode in control mode i/o port ascka0/sckb4/tip00/top00 i/o pmc32 0 1 specification of p32 pin operation mode in control mode i/o port rxda0/sib4/intp7 input pmc31 0 1 specification of p31 pin operation mode in control mode i/o port txda0/sob4 output pmc30 0 1 specification of p30 pin operation mode in control mode pmc3 (pmc3h note ) (pmc3l) note to read/write bits 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc3h register.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 127 (d) port function control register 3 (pfc3) the pfc3 register is a 16-bit register that specifies control mode 1, control mode 2, control mode 3, or control mode 4. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfc3 register as the pfc3h register and the lower 8 bits as the pfc3l register, pfc3 can be read or written in 8-bit and 1-bit units. reset input clears this register to 0000h. after reset: 0000h r/w address: pfc3 fffff466h, pfc3l fffff466h, pfc3l fffff467h 0 0 0 0 0 0 pfc39 pfc38 pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfc3 (pfc3h note ) (pfc3l) note to read/write bits 8 to 15 of the pfc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc3h register. remark for details on control mode specification, see 4.3.4 (2) (f) p3 pin control mode settings . (e) port function control expansion register 3l (pfce3l) the pfce3l register is an 8-bit register that specifies control mode 1, control mode 2, control mode 3, or control mode 4. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. pfce3l after reset: 00h r/w address: fffff706h 0 0 0 0 0 pfce32 0 0 remark for details on control mode specification, see 4.3.4 (2) (f) p3 pin control mode settings .
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 128 (f) p3 pin control mode settings pfc39 specification of p39 pin control mode 0 rxda2 input 1 scl00 input pfc38 specification of p38 pin control mode 0 txda2 output 1 sda00 i/o pfc37 specification of p37 pin control mode 0 crxd0 input 1 ierx0 input pfc36 specification of p36 pin control mode 0 ctxd0 output 1 ietx0 output pfc35 specification of p35 pin control mode 0 tip11 input 1 top11 output pfc34 specification of p34 pin control mode 0 tip10 input 1 top10 output pfc33 specification of p33 pin control mode 0 tip01 input 1 top01 output pfce32 pfc32 specification of p32 pin control mode 0 0 ascka0 input 0 1 sckb4 i/o 1 0 tip00 input 1 1 top00 output
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 129 pfc31 specification of p31 pin control mode 0 rxda0/intp7 note input 1 sib4 input pfc30 specification of p30 pin control mode 0 txda0 output 1 sob4 output note the intp7 pin and rxda0 pin are alternate-function pins. when using the pin as the rxda0 pin, disable edge detection for the intp7 alternate-function pin. (clear the intf31 bit of the intf3l register and the intr31 bit of the intr3l register to 0.) when using the pin as the intp7 pin, stop uarta0 reception. (clear the ua0rxe bit of the ua0ctl0 register to 0.) (g) port function register 3 (pf3) the pf3 register is a 16-bit register that specifies normal output or n-ch open-drain output. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pf3 register as the pf3h register and the lower 8 bits as the pf3l register, pf3 can be read or written in 8-bit or 1-bit units. reset input clears this register to 0000h. after reset: 0000h r/w address: pf3 fffffc66h, pf3l fffffc66h, pf3h fffffc67h pf37 pf36 pf35 pf34 pf33 pf32 pf31 pf30 0 0 0 0 0 0 pf39 pf38 8 9 10 11 12 13 14 15 normal output n-ch open-drain output pf3n 0 1 control of normal output or n-ch open-drain output (n = 0 to 9) pf3 (pf3h note ) (pf3l) note to read/write bits 8 to 15 of the pf3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pf3h register.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 130 (h) external interrupt falling edge specification register 3l (intf3l) the intf3l register is an 8-bit register that specifies detection of the falling edge for the external interrupt pin. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions 1. when switching from the external interrupt function (alternate function) to the port function, edge detection may occur. therefore, set the port mode after setting intf31 bit = intr31 bit = 0. 2. an on-chip circuit for eliminating noise through analog delay is provided for external interrupt input. intf3l after reset: 00h r/w address: fffffc06h 0 0 0 0 0 0 intf31 0 remark for details on valid edge specification, see table 4-7 . (i) external interrupt rising edge specification register 3l (intr3l) the intr3l register is an 8-bit register that specifies detection of the rising edge for the external interrupt pin. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions 1. when switching from the external interrupt function (alternate function) to the port function, edge detection may occur. therefore, set the port mode after setting intf31 bit = intr31 bit = 0. 2. an on-chip circuit for eliminating noise through analog delay is provided for external interrupt input. intr3l after reset: 00h r/w address: intr3: fffffc26h 0 0 0 0 0 0 intr31 0 remark for details on valid edge specification, see table 4-7 . table 4-7. valid edge specification intf31 intr31 valid edge specification 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution when not using the pin as intp7 pin, be sure to set intf31 bit = intr31 bit = 0.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 131 4.3.5 port 4 port 4 is a 3-bit port that controls i/o in 1-bit units. (1) port 4 functions { port input/output specifiable in 1-bit units specification made by port register 4 (p4) { port input/output specifiable in 1-bit units specification made by port mode register 4 (pm4) { port mode/control mode (alternate functions) specifiable in 1-bit units specification made by port mode control register 4 (pmc4) { control mode 1/control mode 2 specifiable in 1-bit units specification made by port function control register 4 (pfc4) { n-ch open-drain specifiable in 1-bit units specification made by port function register 4 (pf4) port 4 includes the following alternate-function pins. table 4-8. port 4 alternate-function pins pin name alternate-function pin name i/o remark p40 sib0/sda01 note p41 sob0/scl01 note port 4 p42 sckb0 i/o selectable as n-ch open-drain output note i 2 c bus version (y version) only
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 132 (2) registers (a) port register (p4) the p4 register is an 8-bit register that controls pin level read and output level write. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0 outputs 1 p4n 0 1 output data control (in output mode) (n = 0 to 2) p4 0 0 0 0 p42 p41 p40 after reset: undefined r/w address: fffff408h remarks 1. input mode: when port 4 (p4) is read, the pin levels at this time are read. writing to p4 writes the values to that port. this does not affect the input pins. output mode: when port 4 (p4) is read, the p4 values are read. writing to p4 writes the values to that port, and those values are immediately output. 2. the value of p4 is undefined (pin input level) when it is read in the input mode after reset. when p4 is read in the output mode, 00h (output latch value) is read. (b) port mode register 4 (pm4) the pm4 register is an 8-bit register that specifies input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. 1 output mode input mode pm4n 0 1 i/o mode control (n = 0 to 2) pm4 1 1 1 1 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 133 (c) port mode control register 4 (pmc4) the pmc4 register is an 8-bit register that specifies port or control mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 i/o port sckb0 i/o pmc42 0 1 specification of p42 pin operation mode i/o port scb0/scl01 i/o pmc41 0 1 specification of p41 pin operation mode i/o port sb0/sda01 i/o pmc40 0 1 specification of p40 pin operation mode after reset: 00h r/w address: fffff448h (d) port function control register 4 (pfc4) the pfc4 register is an 8-bit register that specifies control mode 1 or control mode 2. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 0 pfc41 pfc40 scb0 output scl01 i/o pfc41 0 1 specification of p41 pin operation mode in control mode sib0 input sda01 i/o pfc40 0 1 specification of p40 pin operation mode in control mode
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 134 (e) port function register 4 (pf4) the pf4 register is an 8-bit register that specifies normal output or n-ch open-drain output. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 normal output n-ch open-drain output pf4n 0 1 control of normal output or n-ch open-drain output (n = 0 to 2) pf4 0 0 0 0 pf42 pf41 pf40 after reset: 00h r/w address: fffffc68h
chapter 4 port functions preliminary user?s manual u16541ej1v0um 135 4.3.6 port 5 port 5 is a 6-bit port that controls i/o in 1-bit units. (1) port 5 functions { port input/output data specifiable in 1-bit units specification made by port register 5 (p5) { port input/output specifiable in 1-bit units specification made by port mode register 5 (pm5) { port mode/control mode (alternate functions) specifiable in 1-bit units specification made by port mode control register 5 (pmc5) { control mode specifiable in 1-bit units specification made by port function control register 5 (pfc5) and port function control expansion register 5 (pfce5) { n-ch open-drain specifiable in 1-bit units specification made by port function register 5 (pf5) port 5 includes the following alternate-function pins. table 4-9. port 0 alternate-function pins pin name alternate-function pin name i/o remark p50 tiq01/kr0/toq01/rtp00 p51 tiq02/kr1/toq02/rtp01 p52 tiq03/kr2/toq03/rtp02/ddi note p53 sib2/kr3/tiq00/toq00/rtp03/ddo note p54 sob2/kr4/rtp04/dck note port 5 p55 sckb2/kr5/rtp05/dms note i/o selectable as n-ch open-drain output note the ddi, ddo, dck, and dms pins are pins for on-chip debugging (flash memory version only). after external reset, when not using these pins as on-chip debugging pins and using them instead as a port, the following handling is required. ? input a low level to the p05/intp2/drst pin. ? set the odcm0 bit of the odcm register (special register). the handling in this case is as follows. <1> clear (0) the ocdm0 bit of the ocdm register. <2> fix the p05/intp2/drst pin input to low level until the handling in <1> above is completed. if a high level is input to the drst pin when the on-chip debug function is not used and before the above processing is performed, malfunction (cpu deadlock) may occur. exercise care in handling the p05 pin. (the p05 pin has a pull-down resistor (30 k ? typ.) in the buffer and does not have to be fixed to low level by an external source. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0).)
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 136 (2) registers (a) port register 5 (p5) the p5 register is an 8-bit register that controls pin level read and output level write. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0 outputs 1 p5n 0 1 output data control (in output mode) (n = 0 to 5) p5 0 p55 p54 p53 p52 p51 p50 after reset: undefined r/w address: fffff40ah remarks 1. input mode: when port 5 (p5) is read, the pin levels at this time are read. writing to p5 writes the values to that port. this does not affect the input pins. output mode: when port 5 (p5) is read, the p5 values are read. writing to p5 writes the values to that port, and those values are immediately output. 2. the value of p5 is undefined (pin input level) when it is read in the input mode after reset. when p5 is read in the output mode, 00h (output latch value) is read. (b) port mode register 5 (pm5) the pm5 register is an 8-bit register that specifies input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. 1 output mode input mode pm5n 0 1 i/o mode control (n = 0 to 5) pm5 1 pm55 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 137 (c) port mode control register 5 (pmc5) the pmc5 register is an 8-bit register that specifies port or control mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 pmc5 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 i/o port sckb2/kr5/rtp05 i/o pmc55 0 1 specification of p55 pin operation mode i/o port sob2/kr4/rtp04 i/o pmc54 0 1 specification of p54 pin operation mode i/o port sb2/kr3/tiq00/toq00/rtp03 i/o pmc53 0 1 specification of p53 pin operation mode i/o port tiq03/kr2/toq03/rtp02 i/o pmc52 0 1 specification of p52 pin operation mode i/o port tiq02/kr1/toq02/rtp01 i/o pmc51 0 1 specification of p51 pin operation mode i/o port tiq01/kr0/toq01/rtp00 i/o pmc50 0 1 specification of p50 pin operation mode after reset: 00h r/w address: fffff44ah (d) port function control register 5 (pfc5) the pfc5 register is an 8-bit register that specifies control mode 1, control mode 2, control mode 3, or control mode 4. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 pfc5 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 after reset: 00h r/w address: fffff46ah remark for details on control mode specification, see 4.3.6 (2) (f) p5 pin control mode settings .
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 138 (e) port function control expansion register 5 (pfce5) the pfce5 register is an 8-bit register that specifies control mode 1, control mode 2, control mode 3, or control mode 4. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 pfce5 0 pfce55 pfce54 pfce53 pfce52 pfce51 pfce50 after reset: 00h r/w address: fffff70ah < > < > < > < > < > < > remark for details on control mode specification, see 4.3.6 (2) (f) p5 pin control mode settings . (f) p5 pin control mode settings pfce55 pfc55 specification of p55 pin control mode 0 0 sckb2 i/o 0 1 kr5 input 1 0 setting prohibited 1 1 rtp05 output pfce54 pfc54 specification of p54 pin control mode 0 0 sob2 output 0 1 kr4 input 1 0 setting prohibited 1 1 rtp04 output pfce53 pfc53 specification of p53 pin control mode 0 0 sib2 input 0 1 tiq00/kr3 note input 1 0 toq00 output 1 1 rtp03 output pfce52 pfc52 specification of p52 pin control mode 0 0 setting prohibited 0 1 tiq03/kr2 note input 1 0 toq03 input 1 1 rtp02 output
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 139 pfce51 pfc51 specification of p51 pin control mode 0 0 setting prohibited 0 1 tiq02/kr1 note input 1 0 toq02 output 1 1 rtp01 output pfce50 pfc50 specification of p50 pin control mode 0 0 setting prohibited 0 1 tiq01/kr0 note input 1 0 toq01 output 1 1 rtp00 output note the krn pin and tiq0m pin are alternate-function pins. when using the pin as the tiq0m pin, disable krn pin key return detection, which is the alternate function. (clear the krmn bit of the krm register to 0.) also, when using the pin as the krn pin, disable tiq0m pin edge detection, which is the alternate function (n = 0 to 3, m = 0 to 3). pin name use as tiq0m pin use as krn pin kr0/tiq01 krm0 bit of krm register = 0 tq0tig2, tq0tig3 bits of tq0ioc1 register = 0 kr1/tiq02 krm1 bit of krm register = 0 tq0tig4, tq0tig5 bits of tq0ioc1 register = 0 kr2/tiq03 krm2 bit of krm register = 0 tq0tig6, tq0tig7 bits of tq0ioc1 register = 0 kr3/tiq00 krm3 bit of krm register = 0 tq0tig0, tq0tig1 bits of tq0ioc1 register = 0 tq0ees0, tq0ees1 bits of tq01oc2 register = 0 tq0ets0, tq0ets1 bits of tq01oc2 register = 0 (g) port function register 5 (pf5) the pf5 register is an 8-bit register that specifies normal output or n-ch open-drain output. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 normal output n-ch open-drain output pf5n 0 1 control of normal output or n-ch open-drain output (n = 0 to 5) pf5 0 pf55 pf54 pf53 pf52 pf51 pf50 after reset: 00h r/w address: fffffc6ah
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 140 4.3.7 port 7 port 7 is a 12-bit port for which i/o settings can be controlled in 1-bit units. (1) port 7 functions { port input/output data specifiable in 1-bit units specification made by port 7 register (p7) { port input/output specifiable in 1-bit units specification made by port mode register 7 (pm7) port 7 includes the following alternate-function pins. table 4-10. port 7 alternate-function pins pin name alternate-function pin name i/o remark p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p77 ani5 p76 ani6 p77 ani7 p78 ani8 p79 ani9 p710 ani10 port 7 p711 ani11 i/o ?
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 141 (2) registers (a) port register 7h, port register 7l (p7h, p7l) the p7h and p7l registers are 8-bit registers that control pin level read and output level write. these registers can be read or written in 8-bit or 1-bit units. 16-bit access is not possible. outputs 0 outputs 1 p7n 0 1 output data control (in output mode) (n = 0 to 11) p7h p7l after reset: undefined r address: p7h fffff40eh, p7l fffff40fh p77 p76 p75 p74 p73 p72 p71 p70 0 0 0 0 p711 p710 p79 p78 caution do not read the p7h and p7l registers during a/d conversion. remarks 1. input mode: when ports 7h and 7l (p7h, p7l) are read, the pin levels at this time are read. writing to p7h and p7l writes the values to that port. this does not affect the input pins. output mode: when ports 7h and 7l (p7h, p7l) are read, the p7h and p7l values are read. writing to p7h and p7l writes the values to that port, and those values are immediately output. 2. the values of p7h and p7h are undefined (pin input level) when they are read in the input mode after reset. when p7h and p7l are read in the output mode, 00h (output latch value) is read.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 142 (b) port mode register 7h, port mode register 7l (pm7h, pm7l) the pm7h and pm7l registers are 8-bit registers that specify input or output mode. these registers can be read or written in 8-bit or 1-bit units. 16-bit access is not possible. reset input sets these registers to ffh. 1 output mode input mode pm7n 0 1 i/o mode control (n = 0 to 11) pm7h pm7l 1 1 1 pm711 pm710 pm79 pm78 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 after reset: ffh r/w address: pm7h fffff42eh, pm7l fffff42fh caution when using p7n as its alternate function (anin), set pm7n to 1.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 143 4.3.8 port 9 port 9 is a 16-bit port for which i/o settings can be controlled in 1-bit units. (1) port 9 functions { port input/output data specifiable in 1-bit units specification made by port register 9 (p9) { port input/output specifiable in 1-bit units specification made by port mode register 9 (pm9) { port mode/control mode (alternate functions) specifiable in 1-bit units specification made by port mode control register 9 (pmc9) { control mode specifiable in 1-bit units specification made by port function control register 9 (pfc9) and port function control expansion register 9 (pfce9) { n-ch open-drain specifiable in 1-bit units specification made by port function register 9 (pf9) { external interrupt (alternate function) valid edge specifiable in 1-bit units specification made by external interrupt falling edge specification register 9h (intf9h) and external interrupt rising edge specification register 9h (intr9h) port 9 includes the following alternate-function pins. table 4-11. port 9 alternate-function pins pin name alternate-function pin name i/o remark p90 a0/kr6/tdxa1/sda02 note p91 a1/kr7/rxda1/scl02 note p92 a2/tip41/top41 p93 a3/tip40/top40 p94 a4/tip31/top31 p95 a5/tip30/top30 p96 a6/tip21/top21 p97 a7/sib1/tip20/top20 p98 a8/sob1 p99 a9/sckb1 p910 a10/sib3 p911 a11/sob3 p912 a12/sckb3 p913 a13/intp4 p914 a14/intp5/tip51/top51 port 9 p915 a15/intp6/tip50/top50 i/o selectable as n-ch open-drain output note i 2 c bus version (y version) only
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 144 (2) registers (a) port register 9 (p9) the p9 register is a 16-bit register that controls pin level read and output level write. this register can be read or written in 8-bit or 1-bit units. however, when using the higher 8 bits of the p9 register as the p9h register and the lower 8 bits as the p9l register, p9 can be read or written in 8-bit or 1-bit units. p915 outputs 0 outputs 1 p9n 0 1 output data control (in output mode) (n = 0 to 15) p914 p913 p912 p911 p910 p99 p98 after reset: undefined r/w address: p9 fffff412h, p9l fffff412h, p9h fffff413h p97 p96 p95 p94 p93 p92 p91 p90 8 9 10 11 12 13 14 15 p9 (p9h note ) (p9l) note to read/write bits 8 to 15 of the p9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the p9h register. remarks 1. input mode: when port 9 (p9) is read, the pin levels at this time are read. writing to p9 writes the values to that port. this does not affect the input pins. output mode: when port 9 (p9) is read, the p9 values are read. writing to p9 writes the values to that port, and those values are immediately output. 2. the value of p9 is undefined (pin input level) when it is read in the input mode after reset. when p9 is read in the output mode, 0000h (output latch value) is read.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 145 (b) port mode register 9 (pm9) the pm9 register is a 16-bit register that specifies input or output mode. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pm9 register as the pm9h register and the lower 8 bits as the pm9l register, pm9 can be read or written in 8-bit and 1-bit units. reset input sets this register to ffffh. pm97 output mode input mode pm9n 0 1 i/o mode control (n = 0 to 15) pm96 pm95 pm94 pm93 pm92 pm91 pm90 after reset: ffffh r/w address: pm9 fffff432h, pm9l fffff432h, pm9h fffff433h pm915 pm914 pm913 pm912 pm911 pm910 pm99 pm98 8 9 10 11 12 13 14 15 pm9 (pm9h note ) (pm9l) note to read/write bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pm9h register.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 146 (c) port mode control register 9 (pmc9) the pmc9 register is a 16-bit register that specifies port or control mode. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmc9 register as the pmc9h register and the lower 8 bits as the pmc9l register, pmc9 can be read or written in 8-bit or 1-bit units. reset input clears this register to 0000h. (1/2) i/o port a15/intp6/tip50/top50 i/o pmc915 0 1 specification of p915 pin operation mode pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 i/o port a14/intp5/tip51/top51 i/o pmc914 0 1 specification of p914 pin operation mode i/o port a11/sob3 i/o pmc911 0 1 specification of p911 pin operation mode i/o port a10/sib3 i/o pmc910 0 1 specification of p910 pin operation mode i/o port a9/sckb1 i/o pmc99 0 1 specification of p99 pin operation mode i/o port a13/intp4 i/o pmc913 0 1 specification of p913 pin operation mode i/o port a12/sckb3 i/o pmc912 0 1 specification of p912 pin operation mode 8 9 10 11 12 13 14 15 pmc9 (pmc9h note ) (pmc9l) note to read/write bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc9h register.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 147 (2/2) i/o port a8/sob1 output pmc98 0 1 specification of p98 pin operation mode i/o port a7/sib1/tip20/top20 i/o pmc97 0 1 specification of p97 pin operation mode i/o port a6/tip21/top21 output pmc96 0 1 specification of p96 pin operation mode i/o port a5/tip30/top30 i/o pmc95 0 1 specification of p95 pin operation mode i/o port a4/tip31/top31 i/o pmc94 0 1 specification of p94 pin operation mode i/o port a3/tip40/top40 i/o pmc93 0 1 specification of p93 pin operation mode i/o port a2/tip41/top41 i/o pmc92 0 1 specification of p92 pin operation mode i/o port a1/kr7/rxda1/scl02 i/o pmc91 0 1 specification of p91 pin operation mode i/o port a0/kr6/txda1/sda02 i/o pmc90 0 1 specification of p90 pin operation mode caution only when using the a0 to a15 pins as the alternate functions of the p90 to p915 pins, set all 16 bits of the pmc9 register to ffffh at once.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 148 (d) port function control register 9 (pfc9) the pfc9 register is a 16-bit register that specifies control mode 1, control mode 2, control mode 3, or control mode 4. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfc9 register as the pfc9h register and the lower 8 bits as the pfc9l register, pfc9 can be read or written in 8-bit or 1-bit units. reset input clears this register to 0000h. caution when performing separate address bus output (a0 to a15), set the pmc9 register to ffffh for all 16 bits at once after clearing the pfc9 register to 0000h. after reset: 0000h r/w address: pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 8 9 10 11 12 13 14 15 pfc9 (pfc9h note ) (pfc9l) note to read/write bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc9h register. remark for details on control mode specification, see 4.3.8 (2) (f) p9 pin control mode settings . (e) port function control expansion register 9 (pfce9) the pfce9 register is a 16-bit register that specifies control mode 1, control mode 2, control mode 3, or control mode 4. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfce9 register as the pfce9h register and the lower 8 bits as the pfce9l register, pfce9 can be read or written in 8-bit or 1-bit units. reset input clears this register to 0000h. after reset: 0000h r/w address: pfce9 fffff712h, pfce9l fffff712h, pfce9h fffff713h pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 pfce915 pfce914 0 0 0 0 0 0 8 9 10 11 12 13 14 15 pfce9 (pfce9h note ) (pfce9l) note to read/write bits 8 to 15 of the pfce9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfce9h register. remark for details on control mode specification, see 4.3.8 (2) (f) p9 pin control mode settings .
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 149 (f) p9 pin control mode settings pfce915 pfc915 specification of p915 pin control mode 0 0 a15 output 0 1 intp6 input 1 0 tip50 input 1 1 setting prohibited pfce914 pfc914 specification of p914 pin control mode 0 0 a14 output 0 1 intp5 input 1 0 tip51 input 1 1 top51 output pfc913 specification of p913 pin control mode 0 a13 output 1 intp4 input pfc912 specification of p912 pin control mode 0 a12 output 1 sckb3 i/o pfc911 specification of p911 pin control mode 0 a11 output 1 sob3 output pfc910 specification of p910 pin control mode 0 a10 output 1 sib3 input pfc99 specification of p99 pin control mode 0 a9 output 1 sckb1 i/o pfc98 specification of p98 pin control mode 0 a8 output 1 sob1 output pfce97 pfc97 specification of p97 pin control mode 0 0 a7 output 0 1 sib1 input 1 0 tip20 input 1 1 top20 output
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 150 pfce96 pfc96 specification of p96 pin control mode 0 0 a6 output 0 1 setting prohibited 1 0 tip21 input 1 1 top21 output pfce95 pfc95 specification of p95 pin control mode 0 0 a5 output 0 1 tip30 input 1 0 top30 output 1 1 setting prohibited pfce94 pfc94 specification of p94 pin control mode 0 0 a4 output 0 1 tip31 input 1 0 top31 output 1 1 setting prohibited pfce93 pfc93 specification of p93 pin control mode 0 0 a3 output 0 1 tip40 input 1 0 top40 output 1 1 setting prohibited pfce92 pfce92 specification of p92 pin control mode 0 0 a2 output 0 1 tip41 input 1 0 top41 output 1 1 setting prohibited pfce91 pfce91 specification of p91 pin control mode 0 0 a1 output 0 1 kr7 input 1 0 rxda1/kr7 input 1 1 scl02 i/o pfce90 pfc90 specification of p90 pin control mode 0 0 a0 output 0 1 kr6 input 1 0 txda1 output 1 1 sda02 i/o
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 151 (g) port function register 9 (pf9) the pf9 register is a 16-bit register that specifies normal output or n-ch open-drain output. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pf9 register as the pf9h register and the lower 8 bits as the pf9l register, pf9 can be read or written in 8-bit or 1-bit units. reset input clears this register to 0000h. after reset: 0000h r/w address: pf3 fffffc72h, pf9l fffffc72h, pf9h fffffc73h pf97 pf96 pf95 pf94 pf93 pf92 pf91 pf90 pf915 pf914 pf913 pf912 pf911 pf910 pf99 pf98 normal output n-ch open-drain output pf9n 0 1 control of normal output or n-ch open-drain output (n = 0 to 15) 8 9 10 11 12 13 14 15 pf9 (pf9h note ) (pf9l) note to read/write bits 8 to 15 of the pf9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pf9h register. (h) external interrupt falling edge specification register 9h (intf9h) the intf9h register is an 8-bit register that specifies external interrupt pin falling edge detection. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions 1. when switching from the external interrupt function (alternate function) to the port function, edge detection may occur. therefore, set the port mode after setting intf9n bit = intr9n bit = 0. 2. an on-chip circuit for eliminating noise through analog delay is provided for external interrupt input. intf9h after reset: 00h r/w address: fffffc13h intf915 intf914 intf913 0 0 0 0 0 8 9 10 11 12 13 14 15 remark for details on valid edge specification, see table 4-12 .
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 152 (i) external interrupt rising edge specification register 9h (intr9h) the intr9h register is an 8-bit register that specifies external interrupt pin rising edge detection. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. cautions 1. when switching from the external interrupt function (alternate function) to the port function, edge detection may occur. therefore, set the port mode after setting intf9n bit = intr9n bit = 0. 2. an on-chip circuit for eliminating noise through analog delay is provided for external interrupt input. intr9h after reset: 00h r/w address: fffffc33h intr915 intr914 intr913 0 0 0 0 0 8 9 10 11 12 13 14 15 remark for details on valid edge specification, see table 4-12 . table 4-12. valid edge specification intf9n intr9n valid edge specification (n = 13 to 15) 0 0 no edge detection 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution when not using the pins as intp4 to intp6 pins, be sure to set intf9n bit = intr9n bit = 0. remark n = 13 to 15: control of intp4 to intp6 pins
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 153 4.3.9 port cm port cm is a 4-bit port for which i/o settings can be controlled in 1-bit units. (1) port cm functions { port input/output data specifiable in 1-bit units specification made by port register cm (pcm) { port input/output specifiable in 1-bit units specification made by port mode register cm (pmcm) { port mode/control mode (alternate functions) specifiable in 1-bit units specification made by port mode control register (pmccm) port cm includes the following alternate-function pins. table 4-13. port cm alternate-function pins pin name alternate-function pin name i/o remark pcm0 wait pcm1 clkout pcm2 hldak port cm pcm3 hldrq i/o ?
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 154 (2) registers (a) port register cm (pcm) the pcm register is an 8-bit register that controls pin level read and output level write. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0 outputs 1 pcmn 0 1 output data control (in output mode) (n = 0 to 3) pcm 0 0 0 pcm3 pcm2 pcm1 pcm0 after reset: undefined r/w address: fffff00ch remarks 1. input mode: when port cm (pcm) is read, the pin levels at this time are read. writing to pcm writes the values to that port. this does not affect the input pins. output mode: when port cm (pcm) is read, the pcm values are read. writing to pcm writes the values to that port, and those values area immediately output. 2. the value of pcm is undefined (pin input level) when it is read in the input mode after reset. when pcm is read in the output mode, 00h (output latch value) is read. (b) port mode register cm (pmcm) the pmcm register is an 8-bit register that specifies the input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. 1 output mode input mode pmcmn 0 1 i/o mode control (n = 0 to 3) pmcm 1 1 1 pmcm3 pmcm2 pmcm1 pmcm0 after reset: ffh r/w address: fffff02ch
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 155 (c) port mode control register cm (pmccm) the pmccm register is an 8-bit register that specifies port or control mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 pmccm 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 i/o port hldrq input pmccm3 0 1 specification of pcm3 pin operation mode i/o port hldak output pmccm2 0 1 specification of pcm2 pin operation mode i/o port clkout output pmccm1 0 1 specification of pcm1 pin operation mode i/o port wait input pmccm0 0 1 specification of pcm0 pin operation mode after reset: 00h r/w address: fffff04ch
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 156 4.3.10 port ct port ct is a 4-bit port for which i/o settings can be controlled in 1-bit units. (1) port ct functions { port input/output data specifiable in 1-bit units specification made by port register ct (pct) { port input/output specifiable in 1-bit units specification made by port mode register ct (pmct) { port mode/control mode (alternate functions) specifiable in 1-bit units specification made by port mode control register ct (pmcct) table 4-14. port ct alternate-function pins pin name alternate-function pin name i/o remark pct0 wr0 pct1 wr1 pct4 rd port ct pct6 astb i/o ?
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 157 (2) registers (a) port register ct (pct) the pct register is an 8-bit register that controls pin level read and output level write. this register can be read or written in 8-bit or 1-bit units. 0 outputs 0 outputs 1 pctn 0 1 output data control (in output mode) (n = 0, 1, 4, 6) pct pct6 0 pct4 0 0 pct1 pct0 after reset: undefined r/w address: fffff00ah remarks 1. input mode: when port ct (pct) is read, the pin levels at this time are read. writing to pct writes the values that port. this does not affect the input pins. output mode: when port ct (pct) is read, the pct values are read. writing to pct writes the values to that port, and those values are immediately output. 2. the value of pct is undefined (pin input level) when it is read in the input mode after reset. when pct is read in the output mode, 00h (output latch value) is read. (b) port mode register ct (pmct) the pmct register is an 8-bit port that specifies input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. 1 output mode input mode pmctn 0 1 i/o mode control (n = 0, 1, 4, 6) pmct pmct6 1 pmct4 1 1 pmct1 pmct0 after reset: ffh r/w address: fffff02ah
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 158 (c) port mode control register ct (pmcct) the pmcct register is an 8-bit register that specifies port or control mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 pmcct pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 i/o port astb output pmcct6 0 1 specification of pct6 pin operation mode i/o port rd output pmcct4 0 1 specification of pct4 pin operation mode i/o port wr1 output pmcct1 0 1 specification of pct1 pin operation mode i/o port wr0 output pmcct0 0 1 specification of pct0 pin operation mode after reset: 00h r/w address: fffff04ah
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 159 4.3.11 port dh port dh is a 6-bit port for which i/o settings can be controlled in 1-bit units. (1) port dh functions { port input/output data specifiable in 1-bit units specification made by port register dh (pdh) { port input/output specifiable in 1-bit units specification made by port mode register dh (pmdh) { port mode/control mode (alternate functions) specifiable in 1-bit units specification made by port mode control register dh (pmcdh) port dh includes the following alternate-function pins. table 4-15. port dh alternate-function pins pin name alternate-function pin name i/o remark pdh0 a16 pdh1 a17 pdh2 a18 pdh3 a19 pdh4 a20 port dh pdh5 a21 i/o ?
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 160 (2) registers (a) port register dh (pdh) the pdh register is an 8-bit register that controls pin level read and output level write. this register can be read or written in 8-bit or 1-bit units. outputs 0 outputs 1 pdhn 0 1 output data control (in output mode) (n = 0 to 5) pdh after reset: undefined r/w address: fffff006h 0 0 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 remarks 1. input mode: when port dh (pdh) is read, the pin levels at this time are read. writing to pdh writes the values to that port. this does not affect the input pins. output mode: when port dh (pdh) is read, the pdh values are read. writing to pdh writes the values to that port, and those the values are immediately output. 2. the value of pdh is undefined (pin input level) when it is read in the input mode after reset. when pdh is read in the output mode, 00h (output latch value) is read. (b) port mode register dh (pmdh) the pmdh is an 8-bit register that specifies input or output mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to ffh. 1 output mode input mode pmdhn 0 1 i/o mode control (n = 0 to 5) 1 pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff026h pmdh
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 161 (c) port mode control register dh (pmcdh) the pmcdh register is an 8-bit register that specifies port or control mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. i/o port am output (address bus output) (m = 16 to 21) pmcdhn 0 1 specification of pdhn pin operation mode (n = 0 to 5) 00 pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset: 00h r/w address: fffff046h pmcdh
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 162 4.3.12 port dl port dl is a 16-bit port for which i/o settings can be controlled in 1-bit units. (1) port dl functions { port input/output data specifiable in 1-bit units specification made by port register dl (pdl) { port input/output specifiable in 1-bit units specification made by port mode register dl (pmdl) { port mode/control mode (alternate functions) specifiable specification made by port mode control register dl (pmcdl) port dl includes the following alternate-function pins. table 4-16. port dl alternate-function pins pin name alternate-function pin name i/o remark pdl0 ad0 pdl1 ad1 pdl2 ad2 pdl3 ad3 pdl4 ad4 pdl5 ad5/flmd1 note pdl6 ad6 pdl7 ad7 pdl8 ad8 pdldl ad9 pdl10 ad10 pdl11 ad11 pdl12 ad12 pdl13 ad13 pdl14 ad14 port dl pdl15 ad15 i/o ? note since this pin is set in the flash programming mode, it does not need to be manipulated with the port control register. for details, see chapter 28 flash memory .
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 163 (2) registers (a) port register dl (pdl) the pdl register is a 16-bit register that controls pin level read and output level write. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pdl register as the pdlh register and the lower 8 bits as the pdll register, pdl can be read or written in 8-bit or 1-bit units. pdl15 outputs 0 outputs 1 pdln 0 1 output data control (in output mode) (n = 0 to 15) pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 after reset: undefined r/w address: pdl fffff004h, pdll fffff004h, pdlh fffff005h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 8 9 10 11 12 13 14 15 pdl (pdlh note ) (pdll) note to read/write bits 8 to 15 of the pdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pdlh register. remarks 1. input mode: when port dl (pdl) is read, the pin levels at this time are read. writing to pdl writes the values to that port. this does not affect the input pins. output mode: when port dl (pdl) is read, the pdl values are read. writing to pdl writes the values to that port, and those values are immediately output. 2. the value of pdl is undefined (pin input level) when it is read in the input mode after reset. when pdl is read in the output mode, 0000h (output latch value) is read.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 164 (b) port mode register dl (pmdl) the pmdl register is a 16-bit register that specifies input or output mode. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmdl register as the pmdlh register and the lower 8 bits as the pmdll register, pmdl can be read or written in 8-bit or 1-bit units. reset input sets this register to ffffh. pmdl7 output mode input mode pmdln 0 1 i/o mode control (n = 0 to 15) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffffh r/w address: pmdl fffff024h, pmdll fffff024h, pmdlh fffff025h pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 pmdl (pmdlh note ) (pmdll) note to read/write bits 8 to 15 of the pmdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmdlh register.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 165 (c) port mode control register dl (pmcdl) the pmcdl register is a 16-bit register that specifies port or control mode. this register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmcdl register as the pmcdlh register and the lower 8 bits as the pmcdll register, pmcdl can be read or written in 8-bit or 1-bit units. reset input clears this register to 0000h. i/o port adn i/o (address/data bus i/o) pmcdln 0 1 specification of pdln pin operation mode (n = 0 to 15) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 after reset: 0000h r/w address: pmcdl fffff044h, pmcdll fffff044h, pmcdlh fffff045h pmcdl15 pmcdl14pmcdl13 pmcdl12 pmcdl11pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 pmcdl (pmcdlh note ) (pmcdll) note to read/write bits 8 to 15 of the pmcdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmcdlh register. caution when the smsel bit of the eximc register = 1 (separate mode) and the bs30 to bs00 bits of the bsc register = 0 (8-bit bus width), do not specify the ad8 to ad15 pins.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 166 table 4-17. using port pin as alternate-function pin (1/10) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) p02 = setting not required p03 = setting not required p03 = setting not required p04 = setting not required p05 = setting not required p05 = setting not required p06 = setting not required p10 = setting not required p11 = setting not required p02 p03 p04 p05 p06 p10 p11 nmi intp0 adtrg intp1 intp2 drst note intp3 ano0 ano1 input input input input input input input output output intr02 (intr0), intf02 (intf0) intr03 (intr0), intf03 (intf0) intr04 (intr0), intf04 (intf0) intr05 (intr0), intf05 (intf0) ocdm0 (ocdm) = 1 intr06 (intr0), intf06 (intf0) pm02 = setting not required pm03 = setting not required pm03 = setting not required pm04 = setting not required pm05 = setting not required pm05 = setting not required pm06 = setting not required pm10 = 1 pm11 = 1 ? ? ? ? ? ? ? ? ? pmc02 = 1 pmc03 = 1 pmc03 = 1 pmc04 = 1 pmc05 = 1 pmc05 = setting not required pmc06 = 1 pfc03 = 0 pfc03 = 1 ? ? ? ? ? ? ? ? ? note the p05 pin ? s alternate function is a pin for on-chip debugging (flash memory version only). after external reset, the p05/intp2/drst pin is initialized to the on-chip debugging pin (drst). when using the p05 pin as a port pin and not as an on-chip debugging pin, the following handling is required. <1> clear (0) the ocdm0 bit of the ocdm register (special register). if a high level is input to the drst pin when the on-chip debug function is not used and before the above processing is perform ed, malfunction (cpu deadlock) may occur. exercise care in handling the p05 pin. (the p05 pin has a pull-down resistor (30 k ? typ.) in the buffer and does not have to be fixed to low level by an external source. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0).) caution when using the p10 and p11 pins as alternate functions (ano0, ano1 pin), set the pm1 register to ffh.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 167 table 4-17. using port pin as alternate-function pin (2/10) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? p30 p31 p32 p33 p34 p35 p36 p37 p38 txda0 sob4 rxda0 intp7 sib4 ascka0 sckb4 tip00 top00 tip01 top01 tip10 top10 tip11 top11 ctxd0 note 2 ietx0 note 3 crxd0 note 2 ierx0 note 3 txda2 sda00 note 4 p30 = setting not required p30 = setting not required p31 = setting not required p31 = setting not required p31 = setting not required p32 = setting not required p32 = setting not required p32 = setting not required p32 = setting not required p33 = setting not required p33 = setting not required p34 = setting not required p34 = setting not required p35 = setting not required p35 = setting not required p36 = setting not required p36 = setting not required p37 = setting not required p37 = setting not required p38 = setting not required p38 = setting not required pm30 = setting not required pm30 = setting not required pm31 = setting not required pm31 = setting not required pm31 = setting not required pm32 = setting not required pm32 = setting not required pm32 = setting not required pm32 = setting not required pm33 = setting not required pm33 = setting not required pm34 = setting not required pm34 = setting not required pm35 = setting not required pm35 = setting not required pm36 = setting not required pm36 = setting not required pm37 = setting not required pm37 = setting not required pm38 = setting not required pm38 = setting not required pmc30 = 1 pmc30 = 1 pmc31 = 1 pmc31 = 1 pmc31 = 1 pmc32 = 1 pmc32 = 1 pmc32 = 1 pmc32 = 1 pmc33 = 1 pmc33 = 1 pmc34 = 1 pmc34 = 1 pmc35 = 1 pmc35 = 1 pmc36 = 1 pmc36 = 1 pmc37 = 1 pmc37 = 1 pmc38 = 1 pmc38 = 1 pfce32 = 0 pfce32 = 0 pfce32 = 1 pfce32 = 1 pfce33 = 0 pfce33 = 0 pfce34 = 0 pfce34 = 0 pfce35 = 0 pfce35 = 0 pfc30 = 0 pfc30 = 1 note 1 , pfc31 = 0 note 1 , pfc31 = 0 pfc31 = 1 pfc32 = 0 pfc32 = 1 pfc32 = 0 pfc32 = 1 pfc33 = 0 pfc33 = 1 pfc34 = 0 pfc34 = 1 pfc35 = 0 pfc35 = 1 pfc36 = 0 pfc36 = 1 pfc37 = 0 pfc37 = 1 pfc38 = 0 pfc38 = 1 intr31 (intr3), intf31 (intf3) output output input input input input i/o input output input output input input input output output output input input output i/o notes 1. the intp7 pin and rxda0 pin are alternate-function pins. when using the pin as the rxda0 pin, disable edge detection for the i ntp7 alternate-function pin. (clear the intf31 bit of the intf3 register and the intr31 bit of the inrt3 register to 0.) when using the pin as the in tp7 pin, stop uarta0 reception. (clear the ua0rxe bit of the ua0ctl0 register to 0.) 2. can controller version only 3. iebus controller version only 4. i 2 c bus version (y version) only
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 168 table 4-17. using port pin as alternate-function pin (3/10) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? input i/o input i/o output i/o i/o input input output output input input output output p39 p40 p41 p42 p50 p51 rxda2 scl00 note sib0 sda01 note sob0 scl01 note sckb0 tiq01 kr0 toq01 rtp00 tiq02 kr1 toq02 rtp01 p39 = setting not required p39 = setting not required p40 = setting not required p40 = setting not required p41 = setting not required p41 = setting not required p42 = setting not required p50 = setting not required p50 = setting not required p50 = setting not required p50 = setting not required p51 = setting not required p51 = setting not required p51 = setting not required p51 = setting not required pm39 = setting not required pm39 = setting not required pm40 = setting not required pm40 = setting not required pm41 = setting not required pm41 = setting not required pm42 = setting not required pm50 = setting not required pm50 = setting not required pm50 = setting not required pm50 = setting not required pm51 = setting not required pm51 = setting not required pm51 = setting not required pm51 = setting not required pmc39 = 1 pmc39 = 1 pmc40 = 1 pmc40 = 1 pmc41 = 1 pmc41 = 1 pmc42 = 1 pmc50 = 1 pmc50 = 1 pmc50 = 1 pmc50 = 1 pmc51 = 1 pmc51 = 1 pmc51 = 1 pmc51 = 1 pfce50 = 0 pfce50 = 0 pfce50 = 1 pfce50 = 1 pfce51 = 0 pfce51 = 0 pfce51 = 1 pfce51 = 1 pfc39 = 0 pfc39 = 1 pfc40 = 0 pfc40 = 1 pfc41 = 0 pfc41 = 1 pfc50 = 1 pfc50 = 1 pfc50 = 0 pfc50 = 1 pfc51 = 1 pfc51 = 1 pfc51 = 0 pfc51 = 1 krm0 (krm) = 0 tq0tig2, tq0tig3 (tq0ioc1) = 0 krm1 (krm) = 0 tq0tig4, tq0tig5 (tq0ioc1) = 0 ? note i 2 c bus version (y version) only
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 169 table 4-17. using port pin as alternate-function pin (4/10) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? input input output output input input input input input output output p52 p53 tiq03 kr2 toq03 rtp02 ddi note sib2 tiq00 kr3 toq00 rtp03 ddo note p52 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p52 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required p53 = setting not required pm52 = setting not required pm52 = setting not required pm52 = setting not required pm52 = setting not required pm52 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pm53 = setting not required pmc52 = 1 pmc52 = 1 pmc52 = 1 pmc52 = 1 pmc52 = setting not required pmc53 = 1 pmc53 = 1 pmc53 = 1 pmc53 = 1 pmc53 = 1 pmc53 = setting not required pfce52 = 0 pfce52 = 0 pfce52 = 1 pfce52 = 1 pfce53 = 0 pfce53 = 0 pfce53 = 0 pfce53 = 1 pfce53 = 1 pfc52 = 1 pfc52 = 1 pfc52 = 0 pfc52 = 1 pfc53 = 0 pfc53 = 1 pfc53 = 1 pfc53 = 0 pfc53 = 1 krm2 (krm) = 0 tq0tig6, tq0tig7 (tq0i0c1) = 0 ocdm0 (ocdm) = 1 krm3 (krm) = 0 tq0tig0, tq0tig1 (tq0ioc1) = 0, tq0ees0, tq0ees1 (tq0ioc2) = 0, tq0ets0, tq0ets1 (tq0ioc2) = 0 ocdm0 (ocdm) = 1 ? ? note the ddi and ddo pins are pins for on-chip debugging (flash memory version only). after external reset, when not using these pi ns as on-chip debugging pins and using them instead as port pins, the following handling is required. ? input a low level to the p05/intp2/drst pin. ? set the odcm0 bit of the odcm register (special register). the handling in this case is as follows. <1> clear (0) the ocdm0 bit of the ocdm register. <2> fix the p05/intp2/drst pin input to low level until the handling in <1> above is completed. if a high level is input to the drst pin when the on-chip debug function is not used and before the above processing is perform ed, malfunction (cpu deadlock) may occur. exercise care in handling the p05 pin. (the p05 pin has a pull-down resistor (30 k ? typ.) in the buffer and does not have to be fixed to low level by an external source. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0).)
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 170 table 4-17. using port pin as alternate function-pin (5/10) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? output input output input i/o input output input p54 p55 sob2 kr4 rtp04 dck note sckb2 kr5 rtp05 dms note p54 = setting not required p54 = setting not required p54 = setting not required p54 = setting not required p55 = setting not required p55 = setting not required p55 = setting not required p55 = setting not required pm54 = setting not required pm54 = setting not required pm54 = setting not required pm54 = setting not required pm55 = setting not required pm55 = setting not required pm55 = setting not required pm55 = setting not required ? ? pmc54 = 1 pmc54 = 1 pmc54 = 1 pmc54 = setting not required pmc55 = 1 pmc55 = 1 pmc55 = 1 pmc55 = setting not required pfce54 = 0 pfce54 = 0 pfce54 = 1 pfce55 = 0 pfce55 = 0 pfce55 = 1 pfc54 = 0 pfc54 = 1 pfc54 = 1 pfc55 = 0 pfc55 = 1 pfc55 = 1 ocdm0 (ocdm) = 1 ocdm0 (ocdm) = 1 note the dck and dms pins are pins for on-chip debugging (flash memory version only). after external reset, when not using these pi ns as on-chip debugging pins and using them instead as port pins, the following handling is required. ? input a low level to the p05/intp2/drst pin. ? set the odcm0 bit of the odcm register (special register). the handling in this case is as follows. <1> clear (0) the ocdm0 bit of the ocdm register. <2> fix the p05/intp2/drst pin input to low level until the handling in <1> above is completed. if a high level is input to the drst pin when the on-chip debug function is not used and before the above processing is perform ed, malfunction (cpu deadlock) may occur. exercise care in handling the p05 pin. (the p05 pin has a pull-down resistor (30 k ? typ.) in the buffer and does not have to be fixed to the low level by an external source. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0).)
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 171 table 4-17. using port pin as alternate-function pin (6/10) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? note 1 note 1 note 1 input input input input input input input input input input input input output input output i/o output input input i/o output input output p70 p71 p72 p73 p74 p75 p76 p77 p78 p79 p710 p711 p90 p91 p92 ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 a0 kr6 txda1 sda02 note 2 a1 kr7 rxda1/kr7 scl02 note 2 a2 tip41 top41 p70 = setting not required p71 = setting not required p72 = setting not required p73 = setting not required p74 = setting not required p75 = setting not required p76 = setting not required p77 = setting not required p78 = setting not required p79 = setting not required p710 = setting not required p711 = setting not required p90 = setting not required p90 = setting not required p90 = setting not required p90 = setting not required p91 = setting not required p91 = setting not required p91 = setting not required p91 = setting not required p92 = setting not required p92 = setting not required p92 = setting not required pm70 = 1 pm71 = 1 pm72 = 1 pm73 = 1 pm74 = 1 pm75 = 1 pm76 = 1 pm77 = 1 pm78 = 1 pm79 = 1 pm710 = 1 pm711 = 1 pm90 = setting not required pm90 = setting not required pm90 = setting not required pm90 = setting not required pm91 = setting not required pm91 = setting not required pm91 = setting not required pm91 = setting not required pm92 = setting not required pm92 = setting not required pm92 = setting not required pmc90 = 1 pmc90 = 1 pmc90 = 1 pmc90 = 1 pmc91 = 1 pmc91 = 1 pmc91 = 1 pmc91 = 1 pmc92 = 1 pmc92 = 1 pmc92 = 1 pfce90 = 0 pfce90 = 0 pfce90 = 1 pfce90 = 1 pfce91 = 0 pfce91 = 0 pfce91 = 1 pfce91 = 1 pfce92 = 0 pfce92 = 0 pfce92 = 1 pfc90 = 0 pfc90 = 1 pfc90 = 0 pfc90 = 1 pfc91 = 0 pfc91 = 1 pfc91 = 0 pfc91 = 1 pfc92 = 0 pfc92 = 1 pfc92 = 0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? notes 1. when setting pins a0 to a15 as the alternate function, set the pmc9 register to ffffh for all 16 bits at once. 2. i 2 c bus version (y version) only
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 172 table 4-17. using port pin as alternate-function pin (7/10 ) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) note note note note note note note note note ? ? ? ? ? ? ? ? output input output output input output output input output output input output output input input output output output output i/o output input output output p93 p94 p95 p96 p97 p98 p99 p910 p911 a3 tip40 top40 a4 tip31 top31 a5 tip30 top30 a6 tip21 top21 a7 sib1 tip20 top20 a8 sob1 a9 sckb1 a10 sib3 a11 sob3 p93 = setting not required p93 = setting not required p93 = setting not required p94 = setting not required p94 = setting not required p94 = setting not required p95 = setting not required p95 = setting not required p95 = setting not required p96 = setting not required p96 = setting not required p96 = setting not required p97 = setting not required p97 = setting not required p97 = setting not required p97 = setting not required p98 = setting not required p98 = setting not required p99 = setting not required p99 = setting not required p910 = setting not required p910 = setting not required p911 = setting not required p911 = setting not required pm93 = setting not required pm93 = setting not required pm93 = setting not required pm94 = setting not required pm94 = setting not required pm94 = setting not required pm95 = setting not required pm95 = setting not required pm95 = setting not required pm96 = setting not required pm96 = setting not required pm96 = setting not required pm97 = setting not required pm97 = setting not required pm97 = setting not required pm97 = setting not required pm98 = setting not required pm98 = setting not required pm99 = setting not required pm99 = setting not required pm910 = setting not required pm910 = setting not required pm911 = setting not required pm911 = setting not required pmc93 = 1 pmc93 = 1 pmc93 = 1 pmc94 = 1 pmc94 = 1 pmc94 = 1 pmc95 = 1 pmc95 = 1 pmc95 = 1 pmc96 = 1 pmc96 = 1 pmc96 = 1 pmc97 = 1 pmc97 = 1 pmc97 = 1 pmc97 = 1 pmc98 = 1 pmc98 = 1 pmc99 = 1 pmc99 = 1 pmc910 = 1 pmc910 = 1 pmc911 = 1 pmc911 = 1 pfce93 = 0 pfce93 = 0 pfce93 = 1 pfce94 = 0 pfce94 = 0 pfce94 = 1 pfce95 = 0 pfce95 = 0 pfce95 = 1 pfce96 = 0 pfce96 = 1 pfce96 = 1 pfce97 = 0 pfce97 = 0 pfce97 = 1 pfce97 = 1 pfc93 = 0 pfc93 = 1 pfc93 = 0 pfc94 = 0 pfc94 = 1 pfc94 = 0 pfc95 = 0 pfc95 = 1 pfc95 = 0 pfc96 = 0 pfc96 = 0 pfc96 = 1 pfc97 = 0 pfc97 = 1 pfc97 = 0 pfc97 = 1 pfc98 = 0 pfc98 = 1 pfc99 = 0 pfc99 = 1 pfc910 = 0 pfc910 = 1 pfc911 = 0 pfc911 = 1 note when setting pins a0 to a15 as the alternate function, set the pmc9 register to ffffh for all 16 bits at once.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 173 table 4-17. using port pin as alternate-function pin (8/10) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) output i/o output input output input input output output input input output p912 p913 p914 p915 a12 sckb3 a13 intp4 note 2 a14 intp5 note 2 tip51 top51 a15 intp6 note 2 tip50 top50 p912 = setting not required p912 = setting not required p913 = setting not required p913 = setting not required p914 = setting not required p914 = setting not required p914 = setting not required p914 = setting not required p915 = setting not required p915 = setting not required p915 = setting not required p915 = setting not required pm912 = setting not required pm912 = setting not required pm913 = setting not required pm913 = setting not required pm914 = setting not required pm914 = setting not required pm914 = setting not required pm914 = setting not required pm915 = setting not required pm915 = setting not required pm915 = setting not required pm915 = setting not required pmc912 = 1 pmc912 = 1 pmc913 = 1 pmc913 = 1 pmc914 = 1 pmc914 = 1 pmc914 = 1 pmc914 = 1 pmc915 = 1 pmc915 = 1 pmc915 = 1 pmc915 = 1 pfce914 = 0 pfce914 = 0 pfce914 = 1 pfce914 = 1 pfce915 = 0 pfce915 = 0 pfce915 = 1 pfce915 = 1 pfc912 = 0 pfc912 = 1 pfc913 = 0 note 2 , pfc913 = 1 pfc914 = 0 note 2 , pfc914 = 1 pfc914 = 0 pfc914 = 1 pfc915 = 0 note 2 , pfc915 = 1 pfc915 = 0 pfc915 = 1 note 1 note 1 intr913 (intr9h), intf913 (intf9h) note 1 intr914 (intr9h), intf914 (intf9h) note 1 intr915 (intr9h), intf915 (intf9h) notes 1. when setting pins a0 to a15 as the alternate function, set the pmc9 register to ffffh for all 16 bits at once. 2. when not using the pins as the intp4 to intp6 pins, disable edge detection (clear the intf9n bit of the intf9h register and int r9n bit of the intr9h register to 0 (n = 13 to 15)).
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 174 table 4-17. using port pin as alternate-function pin (9/10) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? input output output input output output output output output output output output output output pcm0 pcm1 pcm2 pcm3 pct0 pct1 pct4 pct6 pdh0 pdh1 pdh2 pdh3 pdh4 pdh5 wait clkout hldak hldrq wr0 wr1 rd astb a16 a17 a18 a19 a20 a21 pcm0 = setting not required pcm1 = setting not required pcm2 = setting not required pcm3 = setting not required pct0 = setting not required pct1 = setting not required pct4 = setting not required pct6 = setting not required pdh0 = setting not required pdh1 = setting not required pdh2 = setting not required pdh3 = setting not required pdh4 = setting not required pdh5 = setting not required pmcm0 = setting not required pmcm1 = setting not required pmcm2 = setting not required pmcm3 = setting not required pmct0 = setting not required pmct1 = setting not required pmct4 = setting not required pmct6 = setting not required pmdh0 = setting not required pmdh1 = setting not required pmdh2 = setting not required pmdh3 = setting not required pmdh4 = setting not required pmdh5 = setting not required pmccm0 = 1 pmccm1 = 1 pmccm2 = 1 pmccm3 = 1 pmcct0 = 1 pmcct1 = 1 pmcct4 = 1 pmcct6 = 1 pmcdh0 = 1 pmcdh1 = 1 pmcdh2 = 1 pmcdh3 = 1 pmcdh4 = 1 pmcdh5 = 1 note when setting pins a0 to a15 as the alternate function, set the pmc9 register to ffffh for all 16 bits at once.
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 175 table 4-17. using port pin as alternate-function pin (10/10) pin name alternate function name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i/o i/o i/o i/o i/o i/o input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o pdl0 pdl1 pdl2 pdl3 pdl4 pdl5 pdl6 pdl7 pdl8 pdl9 pdl10 pdl11 pdl12 pdl13 pdl14 pdl15 ad0 ad1 ad2 ad3 ad4 ad5 flmd1 note ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 pdl0 = setting not required pdl1 = setting not required pdl2 = setting not required pdl3 = setting not required pdl4 = setting not required pdl5 = setting not required pdl5 = setting not required pdl6 = setting not required pdl7 = setting not required pdl8 = setting not required pdl9 = setting not required pdl10 = setting not required pdl11 = setting not required pdl12 = setting not required pdl13 = setting not required pdl14 = setting not required pdl15 = setting not required pmdl0 = setting not required pmdl1 = setting not required pmdl2 = setting not required pmdl3 = setting not required pmdl4 = setting not required pmdl5 = setting not required pmdl5 = setting not required pmdl6 = setting not required pmdl7 = setting not required pmdl8 = setting not required pmdl9 = setting not required pmdl10 = setting not required pmdl11 = setting not required pmdl12 = setting not required pmdl13 = setting not required pmdl14 = setting not required pmdl15 = setting not required pmcdl0 = 1 pmcdl1 = 1 pmcdl2 = 1 pmcdl3 = 1 pmcdl4 = 1 pmcdl5 = 1 setting not required pmcdl6 = 1 pmcdl7 = 1 pmcdl8 = 1 pmcdl9 = 1 pmcdl10 = 1 pmcdl11 = 1 pmcdl12 = 1 pmcdl13 = 1 pmcdl14 = 1 pmcdl15 = 1 note since this pin is set in the flash programming mode, it does not need to be manipulated with the port control register. for de tails, see chapter 28 flash memory .
chapter 4 port functions preliminary user ? s manual u16541ej1v0um 176 4.4 port function operation the port operation differs according to the i/o mode settings, as follows. 4.4.1 write to i/o ports (1) output mode values are written to output latches using transfer instructions. moreover, the output latch contents are output from the pin. once data has been written to an output latch, it is held until data is newly written to that output latch. (2) i/o mode values are written to output latches using transfer instructions. however, since the output buffer is off, the status of the pin does not change. once data has been written to an output latch, it is held until data is newly written to that output latch. caution in the case of a 1-bit memory manipulation instruction, the manipulation target is 1 bit, but the port is accessed in 8-bit units. therefore, for ports where input and output are mixed, the contents of output latches of pins specified for input other than the manipulation target bit become undefined. 4.4.2 read from i/o port (1) output mode the contents of the output latch are read using a transfer instruction. the contents of the output latch do not change. (2) input mode the pin status is read using a transfer instruction. the contents of the output latch do not change. 4.4.3 i/o port calculation (1) output port calculation for the output latch contents is performed and the result is written to the output latch. the output latch contents are output from the pin. once data has been written to an output latch, it is held until data is newly written to that output latch. (2) input mode the output latch contents become undefined. however, since the output buffer is off, the pin status does not change. caution in the case of a 1-bit memory manipulation instruction, the manipulation target is 1 bit, but the port is accessed in 8-bit units. therefore, for ports where input and output are mixed, the contents of output latches of pins specified for input other than the manipulation target bit become undefined.
preliminary user?s manual u16541ej1v0um 177 chapter 5 bus control function the v850es/sg2 is provided with an external bus interface function by which external memories such as rom and ram, and i/o can be connected. 5.1 features output is selectable from a multiplexed bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles. 8-bit/16-bit data bus selectable wait function ? programmable wait function of up to 7 states ? external wait function using wait pin idle state function bus hold function up to 4 mb of physical memory connectable
chapter 5 bus control function preliminary user?s manual u16541ej1v0um 178 5.2 bus control pins the pins used to connect an external device are listed in the table below. table 5-1. bus control pins (multiplexed bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus a16 to a21 pdh0 to pdh5 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control table 5-2. external control pins (separate bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o data bus a0 to a15 p90 to p915 output address bus a16 to a21 pdh0 to pdh5 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal hldrq pcm3 input hldak pcm2 output bus hold control 5.2.1 pin status when internal rom, internal ram, or on-chip peripheral i/o is accessed table 5-3. pin status when internal rom, internal ram, or on-chip peripheral i/o is accessed access destination address bus data bus control signal internal rom undefined hi-z inactive internal ram undefined hi-z inactive on-chip peripheral i/o note hi-z inactive note when an on-chip peripheral i/o is accessed, the address bus outputs the address of the on-chip peripheral i/o that is accessed. 5.2.2 pin status in each operation mode for the pin status of the v850es/sg2 in each operation mode, see 2.2 pin status .
chapter 5 bus control function preliminary user?s manual u16541ej1v0um 179 5.3 memory block function the 64 mb memory space is divided into memory blocks of (lower) 2 mb, 2 mb, 4 mb, and 8 mb. the programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units. figure 5-1. data memory map (80 kb) use prohibited memory block 3 (8 mb) internal rom area note (1 mb) external memory area (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) use prohibited memory block 2 (4 mb) memory block 1 (2 mb) memory block 0 (2 mb) 3ffffffh 3fec000h 3febfffh 1000000h 0ffffffh 0800000h 07fffffh 0400000h 03fffffh 0200000h 01fffffh 0000000h 3ffffffh 3fff000h 3ffefffh 3ff0000h 3ffefffh 3fec000h 01fffffh 0100000h 00fffffh 0000000h note this area is an external memory area in the case of a data write access.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 180 5.4 external bus interface mode control function the v850es/sg2 includes the following two external bus interface modes. ? multiplexed bus mode ? separate bus mode these two modes can be selected by using the external bus interface mode control register (eximc). (1) external bus interface mode control register (eximc) the eximc register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 multiplexed bus mode separate bus mode smsel 0 1 mode selection eximc 0 0 0 0 0 0 smsel after reset: 00h r/w address: ffffffbeh caution set the eximc register from the internal rom or internal ram area before making an external access. after setting the eximc register, be sure to insert a nop instruction.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 181 5.5 bus access 5.5.1 number of clocks for access the following table shows the number of basic clocks required for accessing each resource. area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) instruction fetch (normal access) 1 1 note 1 3 + n note 2 instruction fetch (branch) 2 1 3 + n note 2 operand data access 3 1 3 + n note 2 notes 1. 2 if a conflict with a data access occurs. 2. 2 + n clocks (n: number of wait states) when the separate bus mode is selected. remark unit: clocks/access 5.5.2 bus size setting function the bus size of each external memory area selected by memory block n can be set (to 8 bits or 16 bits) by using the bus size configuration register (bsc). the external memory area (01000000h to 0ffffffh) of the v850es/sg2 is selected by memory blocks 0 to 3. (1) bus size configuration register (bsc) the bsc register can be read or written in 16-bit units. reset input sets this register to 5555h. caution write to the bsc register after reset, and then do not change the set values. also, do not access an external memory area other than the one for this initialization routine until the initial settings of the bsc register are complete. however, external memory areas whose initial settings are complete may be accessed. after reset: 5555h r/w address: fffff066h 0 0 bsn0 0 1 8 bits 16 bits bsc 1 bs30 0 0 1 bs20 0 0 1 bs10 0 0 1 bs00 8 9 10 11 12 13 data bus width of memory block n space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block 2 memory block 1 caution be sure to set bits 14, 12, 10, and 8 to 1, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 182 5.5.3 access by bus size the v850es/sg2 accesses the on-chip peripheral i/o and external memory in 8-bit, 16-bit, or 32-bit units. the bus size is as follows. ? the bus size of the on-chip peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is described below. all data is accessed starting from the lower side. the v850es/sg2 supports only the little-endian format. figure 5-2. little-endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 183 (2) halfword access (16 bits) (a) with 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus first access second access 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 halfword data external data bus 2n address halfword data external data bus address 2n + 1 (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus first access second access 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 184 (3) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 185 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 186 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 187 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access word data external data bus address word data external data bus address word data external data bus address word data external data bus address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 188 5.6 wait function 5.6.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-speed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each memory block space. the number of wait states can be programmed by using data wait control register 0 (dwc0). immediately after system reset, 7 data wait states are inserted for all the blocks. the dwc0 register can be read or written in 16-bit units. reset input sets this register to 7777h. cautions 1. the internal rom and internal ram areas are not subject to programmable wait, and are always accessed without a wait state. the on-chip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. write to the dwc0 register after reset, and then do not change the set values. also, do not access an external memory area other than the one for this initialization routine until the initial settings of the dwc0 register are complete. however, external memory areas whose initial settings are complete may be accessed. after reset: 7777h r/w address: fffff484h 0 0 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 dwc0 dw32 dw12 dw31 dw11 dw30 dw10 0 0 dw22 dw02 dw21 dw01 dw20 dw00 8 9 10 11 12 13 number of wait states inserted in memory block n space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block 2 memory block 1 caution be sure to clear bits 15, 11, 7, and 3 to 0.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 189 5.6.2 external wait function to synchronize an extremely slow external device, i/o, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (wait). access to each area of the internal rom, internal ram, and on-chip peripheral i/o is not subject to control by the external wait function, in the same manner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle in the multiplexed bus mode. in the separate bus mode, it is sampled at the rising edge of the clock immediately after the t1 and tw states of the bus cycle. if the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 190 5.6.3 relationship between programmable wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the wait pin. in other words, the number of wait cycles is determined by the side with the greatest number of cycles. wait control programmable wait wait via wait pin for example, if the timing of the programmable wait and the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-3. inserting wait example (a) multiplexed bus clkout t1 t2 tw tw tw t3 wait pin wait via wait pin programmable wait wait control (b) separate bus t1 tw tw tw t2 clkout wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 191 5.6.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be set by using the address wait control register (awc). address wait insertion is set for each memory block area (memory blocks 0 to 3). if an address setup wait is inserted, it seems that the high-clock period of the t1 state is extended by 1 clock. if an address hold wait is inserted, it seems that the low-clock period of the t1 state is extended by 1 clock. (1) address wait control register (awc) the awc register can be read or written in 16-bit units. reset input sets this register to ffffh. after reset: ffffh r/w address: fffff488h 1 ahw3 ahwn 0 1 not inserted inserted awc 1 asw3 1 ahw2 1 asw2 1 ahw1 1 asw1 1 ahw0 1 asw0 8 9 10 11 12 13 specifies insertion of address hold wait (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 aswn 0 1 not inserted inserted specifies insertion of address setup wait (n = 0 to 3) memory block 0 memory block 3 memory block 2 memory block 1 caution be sure to set bits 15 to 8 to 1.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 192 5.7 idle state insertion function to facilitate interfacing with low-speed memories, one idle state (ti) can be inserted after the t3 state in the bus cycle that is executed for each space selected by the chip select function in the multiplexed address/data bus mode. in the separate bus mode, one idle state (ti) can be inserted after the t2 state. by inserting an idle state, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access). whether the idle state is to be inserted can be programmed by using the bus cycle control register (bcc). an idle state is inserted for all the areas immediately after system reset. (1) bus cycle control register (bcc) the bcc register can be read or written in 16-bit units. reset input sets this register to aaaah. cautions 1. the internal rom, internal ram, and on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area other than the one for this initialization routine until the initial settings of the bcc register are complete. however, external memory areas whose initial settings are complete may be accessed. after reset: aaaah r/w address: fffff48ah 1 bc31 bcn1 0 1 not inserted i nserted bcc 0 0 1 bc21 0 0 1 bc11 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 memory block 0 memory block 3 memory block 2 memory block 1 caution be sure to set bits 15, 13, 11, and 9 to 1, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to 0.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 193 5.8 bus hold function 5.8.1 functional outline the hldak and hldrq functions are valid if the pcm2 and pcm3 pins are set in the control mode. when the hldrq pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status). if the request for the bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the program in the internal rom and internal ram is continued until a peripheral i/o register or the external memory is accessed. the bus hold status is indicated by assertion of the hldak pin (low level). the bus hold function enables the configuration of multi-processor type systems in which two or more bus masters exist. note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing function or a bit manipulation instruction. status data bus width access type timing in which bus hold request is not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ?? between read access and write access
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 194 5.8.2 bus hold procedure the bus hold status transition procedure is shown below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.8.3 operation in power save mode because the internal system clock is stopped in the software stop, idle1, and idle2 modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has been asserted, and the bus hold status is entered. when the hldrq pin is later deasserted, the hldak pin is also deasserted, and the bus hold status is cleared.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 195 5.9 bus priority bus hold, instruction fetch (branch), instruction fetch (successive), and operand data accesses are executed in the external bus cycle. bus hold has the highest priority, followed by operand data access, instruction fetch (branch), and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. table 5-4. bus priority priority external bus cycle bus master bus hold external device dma transfer dmac operand data access cpu instruction fetch (branch) cpu high low instruction fetch (successive) cpu 5.10 boundary operation conditions 5.10.1 program space (1) if a branch instruction exists at the upper limit of the internal ram area, a prefetch operation straddling over the on-chip peripheral i/o area (invalid fetch) does not occur. (2) instruction execution to the external memory area cannot be continued without a branch from the internal rom area to the external memory area. 5.10.2 data space the v850es/sg2 has an address misalign function. with this function, data can be placed at all addresses, regardless of the format of the data (word data or halfword data). however, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (1) halfword-length data access a byte-length bus cycle is generated twice if the least significant bit of the address is 1. (2) word-length data access (a) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (b) a halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 196 5.11 bus timing 5.11.1 multiplexed bus (1) read cycle figure 5-4. basic bus cycle t1 t2 t3 clkout a16 to a21 ad0 to ad15 note address data address astb rd wait wr0, wr1 h note ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 197 figure 5-5. when wait state (1 wait) is inserted t1 t2 tw clkout a16 to a21 astb address address rd wr0, wr1 wait t3 data h ad0 to ad15 note note ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 198 figure 5-6. when idle state is inserted t1 t2 t3 clkout ad0 to ad15 note astb address rd wr0, wr1 wait h ti data a16 to a21 address note ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 199 figure 5-7. when wait state (1 wait) and idle state are inserted t1 t2 tw clkout a16 to a21 astb address address rd wr0, wr1 wait t3 ti data h ad0 to ad15 note note ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 200 figure 5-8. when address wait state is inserted tasw t1 tahw clkout a16 to a21 astb address address rd wr0, wr1 wait t2 t3 data h ad0 to ad15 note note ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 201 (2) write cycle figure 5-9. basic bus cycle t1 t2 t3 clkout a16 to a21 ad0 to ad15 note 1 address data address astb rd wait wr0, wr1 note 2 h notes 1. ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. 2. wr0 and wr1 output a low level as shown in the above timing chart when target data access is performed. at all other times, these pins output a high level. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 202 figure 5-10. when wait state (1 wait) is inserted t1 t2 tw t3 clkout a16 to a21 ad0 to ad15 note 1 address data address astb rd wait wr0, wr1 note 2 h notes 1. ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. 2. wr0 and wr1 output a low level as shown in the above timing chart when target data access is performed. at all other times, these pins output a high level. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 203 figure 5-11. when address wait state is inserted tasw t1 tahw t2 t3 clkout a16 to a21 ad0 to ad15 note 1 address data address astb rd wait wr0, wr1 note 2 h notes 1. ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. 2. wr0 and wr1 output a low level as shown in the above timing chart when target data access is performed. at all other times, these pins output a high level. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 204 (3) bus hold cycle figure 5-12. bus hold cycle clkout wait bus hold cycle hldrq t2 t3 th th th ti t1 hldak a16 to a21 ad0 to ad15 note 1 address data address astb rd wr0, wr1 note 2 undefined address undefined notes 1. ad0 to ad7 hold the address output when odd address byte data is accessed. ad8 to ad15 hold the address output when even address byte data is accessed. 2. wr0 and wr1 output a low level as shown in the above timing chart when target data access is performed. at all other times, these pins output a high level. remarks 1. upon detection of a low level in the t2 and t3 states of hldrq (sampling timing), the operation moves on to the bus hold cycle after the t3 state ends. thereafter, upon detection of a low level or high level in the th state (sampling timing), the bus hold status is maintained after the th state ends, or the bus cycle is restarted. 2. the mark indicates the sampling timing when 0 is set for the programmable wait. 3. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 205 5.11.2 separate bus (1) read cycle figure 5-13. basic bus cycle t1 t2 clkout a0 to a21 ad0 to ad15 note address data astb rd wait wr0, wr1 note ad0 to ad7 go into a high-impedance state when odd address byte data is accessed. ad8 to ad15 go into a high-impedance state when even address byte data is accessed. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 206 figure 5-14. when wait state (1 wait) is inserted t1 tw t2 clkout a0 to a21 ad0 to ad15 note address data astb rd wait wr0, wr1 note ad0 to ad7 go into a high-impedance state when odd address byte data is accessed. ad8 to ad15 go into a high-impedance state when even address byte data is accessed. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 207 figure 5-15. when idle state is inserted t1 t2 ti clkout a0 to a21 ad0 to ad15 note address data astb rd wait wr0, wr1 note ad0 to ad7 go into a high-impedance state when odd address byte data is accessed. ad8 to ad15 go into a high-impedance state when even address byte data is accessed. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 208 figure 5-16. when wait state (1 wait) and idle state are inserted t1 tw t2 ti clkout a0 to a21 ad0 to ad15 note address data astb rd wait wr0, wr1 note ad0 to ad7 go into a high-impedance state when odd address byte data is accessed. ad8 to ad15 go into a high-impedance state when even address byte data is accessed. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 209 figure 5-17. when address wait state is inserted tasw t1 tahw t2 clkout a0 to a21 ad0 to ad15 note address data astb rd wait wr0, wr1 note ad0 to ad7 go into a high-impedance state when odd address byte data is accessed. ad8 to ad15 go into a high-impedance state when even address byte data is accessed. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 210 (2) write cycle figure 5-18. basic bus cycle t1 t2 clkout a0 to a21 ad0 to ad15 note 1 address data astb rd wait wr0, wr1 note 2 notes 1. ad0 to ad7 become undefined when odd address byte data is accessed. ad8 to ad15 become undefined when even address byte data is accessed. 2. wr0 and wr1 output a low level as shown in the above timing chart when target data access is performed. at all other times, these pins output a high level. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 211 figure 5-19. when wait state (1 wait) is inserted t1 tw t2 clkout a0 to a21 ad0 to ad15 note 1 address data astb rd wait wr0, wr1 note 2 notes 1. ad0 to ad7 become undefined when odd address byte data is accessed. ad8 to ad15 become undefined when even address byte data is accessed. 2. wr0 and wr1 output a low level as shown in the above timing chart when target data access is performed. at all other times, these pins output a high level. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 212 figure 5-20. when address wait state is inserted tasw t1 tahw t2 clkout a0 to a21 ad0 to ad15 note 1 address data astb rd wait wr0, wr1 note 2 notes 1. ad0 to ad7 become undefined when odd address byte data is accessed. ad8 to ad15 become undefined when even address byte data is accessed. 2. wr0 and wr1 output a low level as shown in the above timing chart when target data access is performed. at all other times, these pins output a high level. remarks 1. the mark indicates the sampling timing when 0 is set for the programmable wait. 2. the broken line indicates high impedance.
chapter 5 bus control function preliminary user ? s manual u16541ej1v0um 213 (3) bus hold cycle figure 5-21. bus hold cycle clkout wait bus hold cycle hldrq t1 t2 th th th ti t1 hldak a0 to a21 ad0 to ad15 note 1 address data address astb rd wr0, wr1 note 2 undefined notes 1. ad0 to ad7 become undefined when odd address byte data is accessed. ad8 to ad15 become undefined when even address byte data is accessed. 2. wr0 and wr1 output a low level as shown in the above timing chart when target data access is performed. at all other times, these pins output a high level. remarks 1. upon detection of a low level in the t2 and t3 states of hldrq (sampling timing), the operation moves on to the bus hold cycle after the t3 state ends. thereafter, upon detection of a low level or high level in the th state (sampling timing), the bus hold status is maintained after the th state ends, or the bus cycle is restarted. 2. the mark indicates the sampling timing when 0 is set for the programmable wait. 3. the broken line indicates high impedance.
preliminary user?s manual u16541ej1v0um 214 chapter 6 clock generation function 6.1 overview the following clock generation functions are available. { main clock oscillator ? in clock-through mode f x = 2.5 to 10 mhz (f xx = 2.5 to 10 mhz) ? in pll mode f x = 2.5 to 5 mhz (f xx = 10 to 20 mhz) { subclock oscillator (sub-resonator) ? 32.768 khz { multiply ( 4/ 8) function by pll (phase locked loop) ? clock-through mode/pll mode selectable { ring osc ? f r = 200 khz (typ.) { internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) { peripheral clock generation { clock output function
chapter 6 clock generation function preliminary user?s manual u16541ej1v0um 215 6.2 configuration figure 6-1. clock generator frc bit mfrc bit ck2 to ck0 bits selpll bit pllon bit cclsf bit, cls bit, ck3 bit software stop mode subclock oscillator port cm prescaler 1 prescaler 2 idle control halt control halt mode cpu clock watch timer clock timer m clock watch timer clock, watchdog timer 2 clock peripheral clock, watchdog timer 2 clock internal system clock prescaler 3 main clock oscillator main clock oscillator stop control xt1 xt2 clkout x1 x2 idle mode selector pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /1,024 f brg = f x to f x /2 12 f xt f xt f xx f x idle control idle mode selector selector ring-osc 1/8 divider rstp bit watchdog timer 2 clock timer m clock (1) main clock oscillator the main resonator oscillates the following frequencies (f x ). ? in clock-through mode f x = 2.5 to 10 mhz (internal f xx = 2.5 to 10 mhz) ? in pll mode f x = 2.5 to 5 mhz (internal f xx = 10 to 20 mhz) (2) subclock oscillator the sub-resonator oscillates a frequency of 32.768 khz (f xt ). (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscillator is stopped in the software stop mode or when the mck bit of the pcc register = 1 (valid only when the cls bit of the pcc register = 1).
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 216 (4) ring-osc outputs a frequency (f r ) of 200 khz (typ.). (5) prescaler 1 this prescaler generates the clock (f xx to f xx /1,024) to be supplied to the following on-chip peripheral functions: tmp0 to tmp5, tmq, tmm, csib0 to csib4, uarta0 to uarta2, i 2 c00 to i 2 c02, adc, dac, and wdt2 (6) prescaler 2 this circuit divides the cpu clock (f cpu ) and main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the internal system clock (f clk ). f clk is the clock supplied to the intc, rom correction, rom, and ram blocks, and can be output from the clkout pin. (7) prescaler 3 this circuit divides the clock generated by the main clock oscillator (f x ) to a specific frequency (32.768 khz) and supplies that clock to the watch timer block. for details, see chapter 9 watch timer . (8) pll this circuit multiplies the clock generated by the main clock oscillator (f x ) by 4 or 8. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be selected by using the selpll bit of the pll control register (pllctl). whether the clock is multiplied by 4 or 8 is selected by the ckdiv0 bit of the ckc register, and pll is started or stopped by the pllon bit of the pllctl register.
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 217 6.3 control registers (1) processor clock control register (pcc) the pcc register is a special register. data can be written to this register only in combination of specific sequences (see 3.4.9 special registers ). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 03h. (1/2) frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 operating stopped mck 0 1 operation of main clock used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w address: fffff828h main clock operation subclock operation cls 0 1 status of cpu clock (f cpu ) even if the mck bit is set to 1 while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. when the main clock is stopped and the device is operating on the subclock, clear the mck bit to 0 and wait until the oscillation stabilization time has been secured by the program before switching back to the main clock. < > < > < > note the cls bit is a read-only bit.
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 218 (2/2) f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 cautions 1. do not change the cpu clock (by using the ck3 to ck0 bits) while clkout is being output. 2. use a bit manipulation instruction to manipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. remark : don ? t care (a) example of setting main clock operation subclock operation <1> ck3 bit 1: use of a bit manipulation instruction is recommended. do not change the ck2 to ck0 bits. <2> subclock operation: it takes up to the following number of instructions after the ck3 bit is set until the subclock operation is started. f cpu /f xt of main clock therefore, read the cls bit to check if the subclock operation has started. <3> mck bit 0: clear the mck bit to 0 only when stopping the main clock. (b) example of setting subclock operation main clock operation <1> mck bit 1: main clock oscillation starts. <2> insert wait cycles by program and wait until the oscillation of the main clock has stabilized. <3> ck3 bit 0: use of a bit manipulation instruction is recommended. do not change the ck2 to ck0 bits. <4> main clock operation: it takes up to the following number of instructions after the ck3 bit is set until the main clock operation specified by the ck2 to ck0 bits is started. max.: (1/subclock frequency) therefore, read the cls bit to check if the subclock operation has started.
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 219 (2) power save control register (psc) the psc register is a special register. data can be written to this register only in a combination of specific sequences (see 3.4.9 special registers ). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 psc nmi1m nmi0m intm 0 0 stp 0 standby mode release by intwdt2 enabled standby mode release by intwdt2 disabled nmi1m 0 1 standby mode release control upon occurrence of intwdt2 standby mode release by nmi pin input enabled standby mode release by nmi pin input disabled nmi0m 0 1 standby mode release control by nmi pin input standby mode release by maskable interrupt request enabled standby mode release by maskable interrupt request disabled intm 0 1 standby mode release control by maskable interrupt request normal mode standby mode stp 0 1 standby mode setting after reset: 00h r/w address: fffff1feh < > < > < > < > cautions 1. when setting the idle1, idle2 mode (including sub-idle mode)/software stop mode, set the stp bit to 1 after setting the psm0 and psm1, bits of the psmr register. 2. the standby modes controlled by the stp bit include the idle1, idle2, software stop, and sub-idle modes.
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 220 (3) power save mode register (psmr) the psmr register is an 8-bit register that controls the operation status in the power save mode and the clock operation. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 idle1 mode software stop mode idle2 mode software stop mode psm1 0 0 1 1 specification of operation in software standby mode psmr 0 0 0 0 0 psm1 psm0 after reset: 00h r/w address: fffff820h psm0 0 1 0 1 < > < > cautions 1. be sure to clear bits 2 to 7 to 0. 2. the psm0 and psm1 bits are valid only when the stp bit of the psc register is 1. remark idle1: in this mode, all operations except the oscillator operation and some other circuits (flash memory and pll) are stopped. after the idle1 mode is released, the normal operation mode is restored without needing to secure the oscillation stabilization time, like the halt mode. idle2: in this mode, all operations except the oscillator operation are stopped. after the idle2 mode is released, the normal operation mode is restored following the lapse of the setup time specified by the osts register (flash memory and pll). stop: in this mode, all operations except the subclock oscillator operation are stopped. after the software stop mode is released, the normal operation mode is restored following the lapse of the oscillation stabilization time specified by the osts register.
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 221 (4) ring osc mode register (rcm) the rcm register is an 8-bit register that sets the operation mode of ring osc. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 rcm 0 0 0 00 0 rstop ring-osc operating ring-osc stopped rstop 0 1 operation/stop of ring-osc after reset: 01h r/w after reset: fffff806h < > (5) cpu operation clock status register (ccls) the ccls register indicates the status of the cpu operation clock. this register is read-only, in 8-bit or 1-bit units. reset input clears this register to 00h. 0 ccls 0 0 0 0 0 0 cclsf after reset: 00h r address: fffff82eh operating on main clock (f x ) or subclock (f xt ). operating on ring-osc (f xr ). cclsf 0 1 cpu operation clock status (6) oscillation stabilization time select register (osts) the osts register selects the oscillation stabilization time following reset or release of the stop mode. see 12.3 (1) oscillation stabilization time select register (osts) .
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 222 6.4 operation 6.4.1 operation of each clock the following table shows the operation status of each clock. table 6-1. operation status of each clock pll register clk bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 <1> <2> <3> <4> <5> <6> <7> <6> <7> main clock oscillator (f x ) {{{ {{ subclock oscillator (f xt ) {{{{{{{{{ cpu clock (f cpu ) { { internal system clock (f clk ) { { { peripheral clock (f xx to f xx /1,024) { { wt clock (main) {{{ {{ wt clock (sub) {{{{{{{{{ wdt2 clock (ring) {{{{{{{{ wdt2 clock (main) { { wdt2 clock (sub) {{{{{{{{{ remark cls bit: bit 4 of the processor clock control register (pcc) mck bit: bit 6 of the pcc register o: operable : stopped <1>: reset pin input <2>: during oscillation stabilization time count <3>: halt mode <4>: idle1, idle2 mode <5>: software stop mode <6>: subclock operation mode <7>: sub-idle mode 6.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the ck3 to ck0 bits of the processor clock control register (pcc). the clkout pin functions alternately as the pcm1 pin and functions as a clock output pin if so specified by the control register of port cm. the status of the clkout pin is the same as the internal system clock in table 6-1 and the pin can output the clock when it is in the operable status. it outputs a low level in the stopped status. however, the alternate-function pin (pcm1: input mode) is selected in <1> and <2> after the reset signal has been input. consequently, the clkout pin goes into a high-impedance state.
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 223 6.5 pll function 6.5.1 overview the pll function is used to output the operating clock of the cpu and peripheral macro at a frequency 4 or 8 times higher than the oscillation frequency, and select the clock-through mode. when pll function is used: input clock = 2.5 to 5 mhz (output: 10 to 20 mhz) clock-through mode: input clock = 2.5 to 10 mhz (output: 2.5 to 10 mhz) 6.5.2 control registers (1) pll control register (pllctl) the pllctl register is an 8-bit register that controls the pll function. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 01h. 0 pllctl 0 0 0 00 selpll pllon pll stopped pll operating (after pll operation starts, a lockup time is required for frequency stabilization) pllon 0 1 pll operation stop register clock-through mode pll mode selpll 0 1 cpu operation clock selection register after reset: 01h r/w address: fffff82ch < > < > cautions 1. when the pllon bit is cleared to 0, the selpll bit is automatically cleared to 0 (clock- through mode). 2. the selpll bit can be set to 1 only when the pll clock frequency is stabilized. if not (unlocked), ?0? is written to the seloll bit if data is written to it.
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 224 (2) clock control register (ckc) the ckc register controls the internal system clock in the pll mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 0ah. 0 ckc 0 0 0 1 0 1 ckdiv0 after reset: 0ah r/w address: fffff822h f xx = 4 f x (f x = 2.5 to 5.0 mhz) f xx = 8 f x (f x = 2.5 mhz) ckdiv0 0 1 internal system clock (f xx ) in pll mode caution the pll mode cannot be used at f x = 5.0 to 10.0 mhz. remark both the cpu clock and peripheral clock are divided by the ckc register, but only the cpu clock is divided by the pcc register.
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 225 (3) lock register (lockr) phase lock occurs at a given frequency following power application or immediately after the software stop mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). this time until stabilization is called the lockup status, and the stabilized state is called the locked status. the lock register (lockr) includes a lock bit that reflects the pll frequency stabilization status. this register is read-only, in 8-bit or 1-bit units. reset input clears this register to 00h. 0 lockr 0 0 0 00 0 lock locked status unlocked status lock 0 1 pll lock status check after reset: 00h r address: fffff824h < > caution the lock register does not reflect the lock status of the pll in real time. the set/reset conditions are as follows. [set conditions] ? upon system reset note ? in idle2 or software stop mode ? upon setting of pll stop (clearing of pllon bit of pllctl register to 0) ? upon stopping main clock and using cpu with subclock (setting of ck3 bit of pcc register to 1 and setting of mck bit of same register to 1) note this register is set to 01h by reset and cleared to 00h after the reset has been released and the oscillation stabilization time has elapsed. [reset conditions] ? upon overflow of oscillation stabilization time following reset release (osts register default time (see 12.3 (1) oscillation stabilization time select register (osts) )) ? upon oscillation stabilization timer overflow (time set by osts register) following software stop mode release, when the software stop mode was set in the pll operating status ? upon pll lockup time timer overflow (time set by plls register) when the pllon bit of the pllctl register is changed from 0 to 1
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 226 (4) pll lockup time specification register (plls) the plls register is an 8-bit register used to select the pll lockup time when the pllon bit of the pllctl register is changed from 0 to 1. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 03h. 0 2 10 /f x 2 11 f x 2 12 /f x 2 13 /f x (default value) plls1 0 0 1 1 plls0 0 1 0 1 selection of pll lockup time plls 0 0 0 0 0 plls1 plls0 after reset: 03h r/w address: fffff6c1h caution set so that the interval time is 800 s or longer.
chapter 6 clock generation function preliminary user ? s manual u16541ej1v0um 227 6.5.3 usage (1) to use pll ? after the reset signal has been released, the pll operates (pllon bit = 1), but because the default mode is the clock-through mode (selpll bit = 0), select the pll mode (selpll bit = 1). ? to set the idle1 or idle2 mode, first select the clock-through mode and then stop the pll. to return from the idle1 or idle2 mode, first enable pll operation (pllon bit = 1), and then select the pll mode (selpll bit = 1). ? to enable pll operation, first set the pllon bit to 1, and then set the selpll bit to 1 after the lock bit = 0. to stop the pll, first select the clock-through mode (selpll bit = 0), wait for 8 clocks or more, and then stop the pll (pllon bit = 0). (2) when pll is not used ? the clock-through mode (selpll bit = 0) is selected after the reset signal has been released, but the pll is operating (pllon bit = 1) and must therefore be stopped (pllon bit = 0).
preliminary user?s manual u16541ej1v0um 228 chapter 7 16-bit timer/event counter p 7.1 features timer p (tmp) is a 16-bit timer/event counter that can be used in various ways. tmp can perform the following operations. ? pwm output ? interval timer ? external event counter (operation not possible when clock is stopped) ? one-shot pulse output ? pulse width measurement 7.2 function outline ? capture trigger input signal 2 ? external trigger input signal 1 ? clock select 8 ? external event count input 1 ? readable counter 1 ? capture/compare reload register 2 ? capture/compare match interrupt 2 ? timer output (topn0, topn1) 2
chapter 7 16-bit timer/event counter p preliminary user?s manual u16541ej1v0um 229 7.3 configuration tmp includes the following hardware. table 7-1. configuration of tmp0 to tmp5 item configuration timer register 16-bit counter registers tmpn capture/compare registers 0, 1 (tpnccr0, tpnccr1) tmpn counter register (tpncnt) ccr0 buffer register, ccr1 buffer register timer input 2 4 (tipn0 note , tipn1) timer output 2 4 (topn0, topn1) control registers tmpn control registers 0, 1 (tpnctl0, tpnctl1) tmpn i/o control registers 0 to 2 (tpnioc0 to tpnioc2) tmpn option registers 0, 1 (tpnopt0, tpnopt1) note tipn0 is multiplexed with a capture trigger input signal, external trigger input signal, and external event input signal. remark n = 0 to 5 figure 7-1. block diagram of timer p f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 note 1 , f xx /256 note 2 f xx /128 note 1 , f xx /512 note 2 selector internal bus internal bus topn0 topn1 tipn0 tipn1 selector edge detector ccr0 buffer register ccr1 buffer register tp0ccr0 tp0ccr1 16-bit timer counter tp0cnt inttpnov inttpncc0 inttpncc1 output controller clear notes 1. tmp0, tmp2, tmp4 2. tmp1, tmp3, tmp5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 230 (1) tmpn capture/compare register 0 (tpnccr0) the tpnccr0 register is a 16-bit register that functions both as a capture register and as a compare register. whether this register functions as a capture register or as a compare register can be controlled with the tpnccss0 bit of the tpnopt0 register, but only in the free-running mode. in the pulse width measurement mode, this register can be used as a dedicated capture register (the compare function cannot be used.) in modes other than the free-running mode and pulse width measurement mode, this register is used as a dedicated compare register. in the initial setting, the tpnccr0 register is a compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tpnccr0 (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr0 fffff596h, tp1ccr0 fffff5a6h, tp2ccr0 fffff5b6h, tp3ccr0 fffff5c6h, tp4ccr0 fffff5d6h, tp5ccr0 fffff5e6h 14 0 13 11 9 7 5 3 15 1 ? use as a compare register tpnccr0 can be rewritten when tpnce = 1 the rewrite method is as follows. tmp operation mode method of writing tpnccr0 register pwm output mode, external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse output mode, interval timer mode anytime write pulse width measurement mode cannot be used because dedicated capture register ? use as capture register the counter value is saved to tpnccr0 upon capture trigger (tipn0) input edge detection.
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 231 (2) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is a 16-bit register that functions both as a capture register and as a compare register. whether this register functions as a capture register or as a compare register can be controlled with the tpnccs1 bit of the tpnopt0 register, but only in the free-running mode. in the pulse width measurement mode, this register can be used as a dedicated capture register (the compare function cannot be used.) in modes other than the free-running mode and pulse width measurement mode, this register is used as a dedicated compare register. in the initial setting, the tpnccr1 register is a reload register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tpnccr1 (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr1 fffff598h, tp1ccr1 fffff5a8h, tp2ccr1 fffff5b8h, tp3ccr1 fffff5c8h, tp4ccr1 fffff5d8h, tp5ccr1 fffff5e8h 14 0 13 11 9 7 5 3 15 1 ? use as a compare register tpnccr1 can be rewritten when tpnce = 1 the timing at which the tpnccr1 rewrite values become valid when tpnce = 1 is as follows. tmp operation mode method of writing tpnccr1 register pwm output mode, external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse output mode, interval timer mode anytime write pulse width measurement mode cannot be used because dedicated capture register ? use as a capture register the counter value is saved to tpnccr1 upon capture trigger (tipn1) input edge detection.
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 232 (3) tmpn counter register (tpncnt) the tpncnt register is a read buffer register that can read 16-bit counter values. this register is read-only, in 16-bit units. reset input clears this register to 0000h. tpncnt (n = 0 to 5) 12 10 8 6 4 2 after reset: 0000h r address: tp0cnt fffff59ah, tp1cnt fffff5aah, tp2cnt fffff5bah, tp3cnt fffff5cah, tp4cnt fffff5dah, tp5cnt fffff5eah 14 0 13 11 9 7 5 3 15 1
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 233 7.4 control registers (1) tmpn control register 0 (tpnctl0) the tpnctl0 register is an 8-bit register that controls the operation of timer p. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. the same value can always be written to the tpnctl0 register by software. tpnce internal operating clock operation disabled (tmpn reset asynchronously) internal operating clock operation enabled tpnce 0 1 timer pn operation control tpnctl0 (n = 0 to 5) 0 0 0 0 tpncks2 tpncks1 tpncks0 654321 after reset: 00h r/w address: tp0ctl0 fffff590h, tp1ctl0 fffff5a0h, tp2ctl0 fffff5b0h, tp3ctl0 fffff5c0h, tp4ctl0 fffff5d0h, tp5ctl0 fffff5e0h internal operating clock control and tmpn asynchronous reset are performed with the tpnce bit. when the tpnce bit is cleared to 0, the internal operating clock of tmpn stops (fixed to low level) and tmpn is reset asynchronously. when the tpnce bit is set to 1, the internal operating clock is enabled and count-up operation starts within 2 input clocks after the tpnce bit was set to 1. <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 tpncks2 0 0 0 0 1 1 1 1 internal count clock selection n = 0, 2, 4 n = 1, 3, 5 tpncks1 0 0 1 1 0 0 1 1 tpncks0 0 1 0 1 0 1 0 1 caution set the tpncks2 to tpncks0 bits when tpnce = 0. when the value of the tpnce bit is changed from 0 to 1, the tpncks2 to tpncks0 bits can be set simultaneously.
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 234 (2) tmpn control register 1 (tpnctl1) the tpnctl1 register is an 8-bit register that controls the operation of timer p. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 no operation in one-shot pulse mode: one-shot pulse software trigger in external trigger pulse output mode: pulse output software trigger tpnest 0 1 software trigger control tpnctl1 (n = 0 to 5) tpnest tpneee 0 0 tpnmd2 tpnmd1 tpnmd0 <6> <5> 4 3 2 1 after reset: 00h r/w address: tp0ctl1 fffff591h, tp1ctl1 fffff5a1h, tp2ctl1 fffff5b1h, tp3ctl1 fffff5c1h, tp4ctl1 fffff5d1h, tp5ctl1 fffff5e1h the tpnest bit functions as a software trigger in the one-shot pulse mode and the external trigger pulse output mode. (this bit is invalid even if it is controlled in any other mode.) tpnest functions as a software trigger if it is set to 1 when tpnce = 1. therefore, be sure to set tpnest to 1 when tpnce = 1. the tipn0 pin is used for an external trigger. the read value of the tpnest bit is always 0. use the internal clock (clock selected with bits tpncks2 to tpncks0) use external clock (tipn0 input edge) tpneee 0 1 count clock selection the valid edge when tpneet = 1 (external clock: tipn0) is specified with bits tpnees1 and tpnees0. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse mode pwm mode free-running mode pulse width measurement mode setting prohibited tpnmd2 0 0 0 0 1 1 1 1 timer mode selection tpnmd1 0 0 1 1 0 0 1 1 tpnmd0 0 1 0 1 0 1 0 1 caution set the tpneee and tpnmd2 to tpnmd0 bits when tpnce = 0. (the same value can be written when tpnce = 1.) the operation is not guaranteed when rewriting is performed when tpnce = 1. if rewriting was mistakenly performed, set tpnce = 0 and then set the bits again.
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 235 (3) tmpn i/o control register 0 (tpnioc0) the tpnioc0 register is an 8-bit register that controls the timer output (topn0, topn1). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tpnol1 0 1 topn1 output level setting normal output inverted output tpnioc0 (n = 0 to 5) 0 0 0 tpnol1 tpnoe1 tpnol0 tpnoe0 6 5 4 <3> <2> <1> after reset: 00h r/w address: tp0ioc0 fffff592h, tp1ioc0 fffff5a2h, tp2ioc0 fffff5b2h, tp3ioc0 fffff5c2h, tp4ioc0 fffff5d2h, tp5ioc0 fffff5e2h tpnoe1 0 1 topn1 output setting timer output prohibited (low level and high level are output from the topn1 pin when tpnol1 = 0 and tpnol1 = 1, respectively). timer output enabled (a pulse is output from the topn1 pin.) tpnol0 0 1 topn0 output level setting normal output inverted output tpnoe0 0 1 topn0 output setting timer output prohibited (low level and high level are output from the topn0 pin when tpnol0 = 0 and tpnol0 = 1, respectively). timer output enabled (a pulse is output from the topn0 pin.) 7 <0> caution rewrite the tpnol1, tpnoe1, tpnol0, and tpnoe0 bits when tpnce = 0. (the same value can be written when tpnce = 1.) if rewriting was mistakenly performed, set tpnce = 0 and then set the bits again.
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 236 (4) tmpn i/o control register 1 (tpnioc1) the tpnioc1 register is an 8-bit register that controls the valid edge for the external input signals (tipn0, tipn1). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tpnis3 0 0 1 1 tpnis2 0 1 0 1 capture input (tipn1) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tpnioc1 (n = 0 to 5) 0 0 0 tpnis3 tpnis2 tpnis1 tpnis0 654321 after reset: 00h r/w address: tp0ioc1 fffff593h, tp1ioc1 fffff5a3h, tp2ioc1 fffff5b3h, tp3ioc1 fffff5c3h, tp4ioc1 fffff5d3h, tp5ioc1 fffff5e3h tpnis1 0 0 1 1 tpnis0 0 1 0 1 capture input (tipn0) valid edge detection no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnis3 to tpnis0 bits when tpnce = 0. (the same value can be written when tpnce = 1.) if rewriting was mistakenly performed, set tpnce = 0 and then set the bits again. 2. the tpnis3 to tpnis0 bits are valid only in the free- running mode and the pulse width measurement mode. in all other modes, a capture operation is not possible.
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 237 (5) tmpn i/o control register 2 (tpnioc2) the tpnioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tipn0) and external trigger input signal (tipn0). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tpnees1 0 0 1 1 tpnees0 0 1 0 1 external event count input valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tpnioc2 (n = 0 to 5) 0 0 0 tpnees1 tpnees0 tpnets1 tpnets0 654321 after reset: 00h r/w address: tp0ioc2 fffff594h, tp1ioc2 fffff5a4h, tp2ioc2 fffff5b4h, tp3ioc2 fffff5c4h, tp4ioc2 fffff5d4h, tp5ioc2 fffff5e4h tpnets1 0 0 1 1 tpnets0 0 1 0 1 external trigger input valid edge detection no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnees1, tpnees0, tpnest1, and tpnest0 bits when tpnce = 0. (the same value can be written when tpnce = 1.) if rewriting was mistakenly performed, set tpnce = 0 and then set the bits again. 2. the tpnees1 and tpnees0 bits are valid only when tpneee = 1 or when the external event count mode (tpnmd2 to tpnmd0 = 001 of the tipnctl1 register) has been set.
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 238 (6) tmpn option register 0 (tpnopt0) the tpnopt0 register is an 8-bit register used to set the capture/compare operation and detect overflow. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tpnccs1 0 1 tpnccr1 register capture/compare selection the tpnccs1 bit setting is valid only in the free-running mode. compare register selection capture register selection tpnopt0 (n = 0 to 5) 0 tpnccs1 tpnccs0 0 0 0 tpnovf 6 <5> <4> 3 2 1 after reset: 00h r/w address: tp0opt0 fffff595h, tp1opt0 fffff5a5h, tp2opt0 fffff5b5h, tp3opt0 fffff5c5h, tp4opt0 fffff5d5h, tp5opt0 fffff5e5h tpnccs0 0 1 tpnccr0 register capture/compare selection the tpnccs0 bit setting is valid only in the free-running mode. compare register selection capture register selection tpnovf set (1) reset (0) timer p overflow detection the tpnovf bit is reset when the 16-bit counter value overflows from ffffh to 0000h in the free-running mode or the pulse width measurement mode. an interrupt request signal (inttpnov) is generated at the same time that the tpnovf bit is set (1). the inttpnov signal is not generated in modes other than the free-running mode and the pulse width measurement mode. the tpnovf bit is not cleared even when the tpnovf bit and the tpnopt0 register are read when tpnovf = 1. the tpnovf bit can be both read and written, but 1 cannot be written to the tpnovf bit from the cpu. writing 1 has no influence on the operation of timer p. overflow occurrence tpnovf bit 0 write or tpnce = 0 7 <0> caution rewrite the tpnccs1 and tpnccs0 bits when tpnce = 0. (the same value can be written when tpnce = 1.) if rewriting was mistakenly performed, set tpnce = 0 and then set the bits again.
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 239 7.5 operation timer p can perform the following operations. operation tpnest (software trigger bit) tipn0 (external trigger input) capture/compare write compare write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only reload one-shot pulse output mode note 2 valid valid compare only anytime write pwm mode invalid invalid compare only reload free-running mode invalid invalid capture/compare switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count function, specify that the edge of the tip00 capture input is not detected (by clearing the tp0is1 and tp0is0 bits of the tp0ioc1 register to ? 00 ? ). 2. when using the external trigger pulse output mode, one-shot pulse mode, and pulse width measurement mode, select a count clock (by clearing the tpneee bit of the tpnctl1 register to 0). remark n = 0 to 5 7.5.1 anytime write and reload tpnccr0 and tpnccr1 register rewrite is possible for timer p during timer operation (tpnce = 1), but the write method (anytime write, reload) differs depending on the mode. (1) anytime write when the tpnccrm register is written during timer operation, the write data is transferred at that time to the ccrm buffer register and used as the 16-bit counter comparison value. remark n = 0 to 5 m = 0, 1
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 240 figure 7-2. flowchart of basic operation for anytime write start initial settings inttpncc0 output tpnccr1 rewrite transfer to ccr1 buffer register tpnccr0 rewrite transfer to ccr0 buffer register ? match between ccr0 buffer register and 16-bit counter ? 16-bit counter clear & start timer operation enable (tpnce = 1) transfer of tpnccr0, tpnccr1 values to ccr0 buffer register and ccr1 buffer register remarks 1. the above flowchart illustrates an example of the operation in the interval timer mode. 2. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 241 figure 7-3. timing diagram for anytime write 16-bit counter tpnccr0 ccr0 buffer register tpnccr1 ccr1 buffer register d 01 d 01 d 02 d 11 d 11 d 12 d 12 inttpncc0 inttpncc1 d 01 0000h d 11 d 12 d 02 tpnce = 1 d 01 d 02 0000h d 11 d 12 remarks 1. d 01 , d 02 : setting values of tpnccr0 register (0000h to ffffh) d 11 , d 12 : setting values of tpnccr1 register (0000h to ffffh) 2. the above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 242 (2) reload when the tpnccr0 and tpnccr1 registers is written during timer operation via the ccrm buffer register, the write data is used as the 16-bit counter comparison value. the tpnccr0 register and the tpnccr1 register can be rewritten when tpnce = 1. in order for the setting value when the tpnccr0 register and the tpnccr1 register are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to the ccrm buffer register), it is necessary to rewrite tpnccr0 and then write to the tpnccr1 register before the 16-bit counter value and the tpnccr0 register value match. thereafter, the values of the tpnccr0 and the tpnccr1 register are reloaded upon tpnccr0 register match. whether to enable or disable the next reload timing is controlled by writing to the tpnccr1 register. thus even when wishing only to rewrite the value of the tpnccr0 register, also write the same value to the tpnccr1 register. figure 7-4. flowchart of basic operation for reload start initial settings reload enable inttpncc0 output tpnccr1 rewrite tpnccr0 rewrite ? match between tpnccr0 and 16-bit counter ? 16-bit counter clear & start ? reload of tpnccrm values to ccrm buffer register timer operation enable (tpnce = 1) transfer of tpnccrm values to ccrm buffer register caution writing to the tpnccr1 register includes enabling of reload. thus, rewrite the tpnccr1 register after rewriting the tpnccr0 register. remarks 1. the above flowchart illustrates an example of the operation in the pwm mode. 2. n = 0 to 5, m = 0, 1
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 243 figure 7-5. timing chart for reload d 01 d 01 d 02 d 03 0000h d 01 d 11 d 12 d 12 d 02 d 03 0000h d 11 d 12 d 12 tpnce = 1 note d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter tpnccr0 tpnccr1 inttpncc0 inttpncc1 ccr0 buffer register ccr1 buffer register note same value write note reload is not performed because the tpnccr1 register was not rewritten. remarks 1. d 01 , d 02 , d 03 : setting value of tpnccr0 register (0000h to ffffh) d 11 , d 12 : setting value of tpnccr1 register (0000h to ffffh) 2. the above flowchart illustrates the operation in the pwm mode as an example. 3. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 244 7.5.2 interval timer mode (tpnmd2 to tpnmd0 = 000) in the interval timer mode, an interrupt request signal (inttpncc0) is output upon a match between the setting value of the tpnccr0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. the tpnccr0 register can be rewritten when tpnce = 1, and when a value is set to the tpnccr0 register with a write instruction from the cpu, it is transferred to the ccr0 buffer register through anytime write, and is used as the value for comparison with the 16-bit counter value. in the interval timer mode, the 16-bit counter is cleared only upon a match between the value of the 16-bit counter and the value of the ccr0 buffer register. 16-bit counter clearing using the tpnccr1 register is not performed. however, the setting value of the tpnccr1 register is transferred to the ccr1 buffer register and compared with the value of the 16-bit counter, and an interrupt request (inttpncc1) is output if these values match. moreover, topnm pin output is also possible by setting the tpnoem bit to 1. when the tpnccr1 register is not used, it is recommended to set ffffh as the setting value for the tpnccr1 register. remark n = 0 to 5, m = 0, 1 figure 7-6. flowchart of basic operation in interval timer mode start initial settings ? clock selection (tpnctl0: tpncks2 to tpncks0) ? interval timer mode setting (tpnctl0: tpnmd2 to tpnmd0 = 000) ? compare register setting (tpnccr0, tpnccr1) timer operation enable (tpnce = 1) transfer of tpnccr0, tpnccr1 values to ccr0 buffer register and ccr1 buffer register match between 16-bit counter and ccr1 buffer register note match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start inttpncc1 output inttpncc0 output note the 16-bit counter is not cleared upon a match between the 16-bit counter and tpnccr1. remark n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 245 figure 7-7. basic operation timing in interval timer mode (1/2) (a) d 1 > d 2 > d 3 ; rewrite of tpnccr0 register only; no topn0, topn1 output 16-bit counter inttpncc0 d 1 d 2 d 1 ffffh d 3 d 3 d 3 inttpncc1 tpnccr0 d 1 tpnce = 1 tpnccr1 d 2 0000h d 2 d 1 d 3 d 3 0000h ccr0 buffer register ccr1 buffer register remarks 1. d 1 , d 2 : setting values of tpnccr0 register (0000h to ffffh) d 3 : setting value of tpnccr1 register (0000h to ffffh) 2. interval time = (dn + 1) (count clock cycle) 3. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 246 figure 7-7. basic operation timing in interval timer mode (2/2) (b) d 1 = d 2 ; no tpnccr0, tpnccr1 rewrite; topn1 output 16-bit counter d 1 inttpncc0 d 1 = d 2 ffffh tpnccr1 inttpncc1 tpnccr0 d 2 tpnce = 1 topn0/topn1 d 1 = d 2 d 1 = d 2 d 1 0000h ccr0 buffer register ccr1 buffer register d 2 0000h remarks 1. d 1 : setting value of tpnccr0 register (0000h to ffffh) d 2 : setting value of tpnccr1 register (0000h to ffffh) 2. interval time = (dn + 1) (count clock cycle) 3. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 247 7.5.3 external event count mode (tpnmd2 to tpnmd0 = 001) in the external event count mode, external event count input (tipn0 pin input) is used as a count-up signal. when the external event count mode is set, count-up is performed using external event count input (tipn0 pin input), regardless of the setting of the tpneee bit of the tpnctl0 register. in the external event count mode, a match interrupt request (inttpncc0) is output upon a match between the setting value of the tpnccr0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. when a value is set to the tpnccr0 register with a write instruction from the cpu, it is transferred to the ccr0 buffer register through anytime write, and is used as the value for comparison with the 16-bit counter value. in the external event count mode, the 16-bit counter is cleared only upon a match between the value of the 16-bit counter and the value of the ccr0 buffer register. 16-bit counter clearing using the tpnccr1 register is not performed. however, the setting value of the tpnccr1 register is transferred to the ccr1 buffer register and compared with the value of the 16-bit counter, and an interrupt request (inttpncc1) is output if these values match. moreover, topnm pin output is also possible by setting the tpnoem bit to 1. the tpnccr0 register can be rewritten when tpnce = 1. when the tpnccr1 register is not used, it is recommended to set ffffh as the setting value for the tpnccr1 register. remark n = 0 to 5 m = 0, 1
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 248 figure 7-8. flowchart of basic operation in external event count mode start initial settings ? external event count mode setting (tpnctl0: tpnmd2 to tpnmd0 = 001) note 1 ? valid edge setting (tpnioc2: tpnees1, tpnees0) ? compare register setting (tpnccr0, tpnccr1) inttpncc1 output inttpncc0 output timer operation enable (tpnce = 1) transfer of tpnccr0, tpnccr1 values to ccr0 buffer register and ccr1 buffer register match between 16-bit counter and ccr1 buffer register note 2 match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start notes 1. selection of the tpneee bit has no influence. 2. the 16-bit counter is not cleared upon a match between the 16-bit counter and the ccr1 buffer register. remark n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 249 figure 7-9. basic operation timing in external event count mode (1/2) (a) d 1 > d 2 > d 3 ; rewrite of tpnccr0 only; no topn0, topn1 output 16-bit counter inttpncc0 d 1 d 2 d 1 ffffh d 3 d 3 d 3 inttpncc1 tpnccr0 d 1 tpnce = 1 tpnccr1 d 2 0000h d 2 d 1 d 3 d 3 0000h ccr0 buffer register ccr1 buffer register remarks 1. d 1 , d 2 : setting values of tpnccr0 register (0000h to ffffh) d 3 : setting value of tpnccr1 register (0000h to ffffh) 2. event count = (dn + 1) 3. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 250 figure 7-9. basic operation timing in external event count mode (2/2) (b) d 1 = d 2 ; no tpnccr0, tpnccr1 rewrite; topn0, topn1 output 16-bit counter d 1 inttpncc0 d 1 = d 2 ffffh tpnccr1 inttpncc1 tpnccr0 d 2 tpnce = 1 topn0/topn1 d 1 = d 2 d 1 = d 2 d 1 0000h ccr0 buffer register ccr1 buffer register d 2 0000h remarks 1. d 1 : setting value of tpnccr0 register (0000h to ffffh) d 2 : setting value of tpnccr1 register (0000h to ffffh) 2. event count = (dn + 1) 3. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 251 7.5.4 external trigger pulse mode (tpnmd2 to tpnmd0 = 010) in the external trigger pulse mode, setting tpnce = 1 causes external trigger input (tipn0 pin input) wait with the 16-bit counter stopped at ffffh. the count-up operation starts upon detection of the external trigger input (tipn0 pin input) edge. regarding topn1 output control, the reload register (tpnccr1) is used as the duty setting register and the compare register (tpnccr0) is used as the cycle setting register. the tpnccr0 register and the tpnccr1 register can be rewritten when tpnce = 1. in order for the setting value when the tpnccr0 register and the tpnccr1 register are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to the ccrm buffer register), it is necessary to rewrite tpnccr0 and then write to the tpnccr1 register before the 16-bit counter value and the tpnccr0 register value match. thereafter, the values of the tpnccr0 and the tpnccr1 register are reloaded upon a tpnccr0 register match. whether to enable or disable the next reload timing is controlled by writing to the tpnccr1 register. thus even when wishing only to rewrite the value of the tpnccr0 register, also write the same value to the tpnccr1 register. reload is disabled even when only the tpnccr0 register is rewritten. to stop timer p, set tpnce = 0. if the external trigger (tipn0 pin input) edge is detected several times in the external trigger pulse mode, the 16-bit counter is cleared at the edge detection timing and count-up starts. to realize the same function (software trigger pulse mode) as external trigger pulse mode using a software trigger instead of external trigger input (tipn0 pin input), set the tpnest bit of the tpnctl1 register to 1 so that the software trigger is output. the external trigger pulse waveform is output from topn1. the topn0 pin performs toggle output upon a match between the tpnccr0 register and the 16-bit counter. since the tpnccr0 register and the tpnccr1 register have their function fixed to that of a compare register in the external trigger pulse mode, they cannot be used for capture operation in this mode. caution in the external trigger pulse mode, select the internal clock (tpneee bit of tpnctl1 register = 0) for the count clock. remarks 1. for the reload operation when tpnccr0 and tpnccr1 are rewritten during timer operation, refer to 7.5.6 pwm mode . 2. n = 0 to 5, m = 0, 1
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 252 figure 7-10. flowchart of basic operation in external trigger pulse output mode start initial settings ? clock selection (tpnctl1: tpneee = 0) (tpnctl0: tpncks2 to tpncks0) ? external trigger pulse output mode setting (tpnctl1: tpnmd2 to tpnmd0 = 010) ? compare register setting (tpnccr0, tpnccr1) match between 16-bit counter and tpnccr1 note inttpncc1 output inttpncc0 output external trigger (tipn0 pin) input 16-bit counter start match between 16-bit counter and tpnccr0, 16-bit counter clear & start 16-bit counter clear & start external trigger (tipn0 pin) input timer operation enable (tpnce = 1) transfer of tpnccr0, tpnccr1 values to ccr0 buffer register and ccr1 buffer register note the 16-bit counter is not cleared upon a match between the 16-bit counter and the ccr1 buffer register. remark n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 253 figure 7-11. basic operation timing in external trigger pulse output mode tpnce = 1 d 11 d 11 d 12 d 11 d 12 d 11 d 12 d 02 d 12 d 02 d 01 d 01 d 01 d 02 d 02 ffffh 16-bit counter external trigger (tipn0 pin) tpnccr0 tpnccr1 topn0 topn1 ccr0 buffer register ccr1 buffer register 0000h 0000h remarks 1. d 01 , d 02 : setting value of tpnccr0 register (0000h to ffffh) d 11 , d 12 : setting value of tpnccr1 register (0000h to ffffh) 2. topn1 output duty = (setting value of tpnccr1 register)/(setting value of tp0ccr0 register) topn1 output cycle = (setting value of tpnccr0 register) (count clock cycle) 3. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 254 7.5.5 one-shot pulse mode (tpnmd2 to tpnmd0 = 011) in the one-shot pulse mode, setting tpnce = 1 causes tpnest bit setting (1) or tipn0 pin edge detection trigger wait with the 16-bit counter held at ffffh. the 16-bit counter starts counting up upon trigger input, and upon a match between the value of the 16-bit counter and the value of the ccr1 buffer register transferred from the tpncr1 register, topn1 becomes high level; upon a match between the value of the 16-bit counter and the value of the ccr0 register transferred from the tpnccr0 register, topn1 becomes low level and the 16-bit counter is cleared to 0000h and stops. any trigger input past the first one during 16-bit counter operation is ignored. be sure to input the second and subsequent triggers when the 16-bit counter has stopped at 0000h. in the one-shot pulse mode, the tpnccr0 and tpnccr1 registers can be rewritten when tpnce = 1. the setting values rewritten to the tpnccr0 and tpnccr1 registers become valid following execution of a write instruction from the cpu, at which time they are transferred to the ccr0 buffer register and the ccr0 buffer register through anytime write, and become the values for comparison with the 16-bit counter value. the one-shot pulse waveform is output from the topn1 pin. the topn0 pin performs toggle output upon a match between the 16-bit counter and the tpnccr0 register. since the tpnccr0 and tpnccr1 registers have their function fixed to that of a compare register in the one-shot pulse mode, they cannot be used for capture operation in this mode. caution in the one-shot pulse mode, select the internal clock (tpneee bit of tpnctl1 register = 0) for the count clock. remark n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 255 figure 7-12. flowchart of basic operation in one-shot pulse mode start initial settings ? clock selection (tpnctl1: tpneee = 0) (tpnctl0: tpncks2 to tpncks0) ? one-shot pulse mode setting (tpnctl1: tpnmd2 to tpnmd0 = 011) ? compare register setting (tpnccr0, tpnccr1) match between 16-bit counter and ccr1 buffer register note inttpncc1 output inttpncc0 output external trigger (tipn0 pin) input, or tpnest = 1 16-bit counter start match between 16-bit counter and ccr0 buffer register, 16-bit counter clear trigger wait status, 16-bit counter in standby at ffffh trigger wait status, 16-bit counter in standby at 0000h timer operation enable (tpnce = 1) transfer of tpnccr0, tpnccr1 values to ccr0 buffer register and ccr1 buffer register note the 16-bit counter is not cleared upon a match between the 16-bit counter and the ccr1 buffer register. caution the 16-bit counter is not cleared and trigger input is ignored even if trigger input is performed during the count-up operation of the 16-bit counter. remark n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 256 figure 7-13. timing of basic operation in one-shot pulse mode tpnce = 1 tpnest = 1 d 1 d 0 d 1 d 0 d 1 d 0 d 0 d 0 d 1 d 1 ffffh 16-bit counter external trigger (tipn0 pin) tpnccr0 inttpncc0 tpnccr1 inttpncc1 topn1 topn0 ccr0 buffer register ccr1 buffer register 0000h 0000h note note the 16-bit counter starts counting up when either tpnest = 1 is set or tipn0 is input. remarks 1. d 0 : setting value of tpnccr0 register (0000h to ffffh) d 1 : setting value of tpnccr1 register (0000h to ffffh) 2. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 257 7.5.6 pwm mode (tpnmd2 to tpnmd0 = 110) in the pwm mode, tmpn capture/compare register 1 (tpnccr1) is used as the duty setting register and tmpn capture/compare register 0 (tpnccr0) is used as the cycle setting register. variable duty pwm is output by setting these two registers and operating the timer. the tpnccr0 register and the tpnccr1 register can be rewritten when tpnce = 1. in order for the setting value when the tpnccr0 register and the tpnccr1 register are rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to ccr0 buffer register or ccr1 buffer register), it is necessary to rewrite tpnccr0 and then write to the tpnccr1 register before the 16-bit counter value and the tpnccr0 register value match. thereafter, the values of the tpnccr0 register and the tpnccr1 register are reloaded upon a tpnccr0 register match. whether to enable or disable the next reload timing is controlled by writing to the tpnccr1 register. thus even when wishing only to rewrite the value of the tpnccr0 register, also write the same value to the tpnccr1 register. reload is disabled even when only the tpnccr0 register is rewritten. to stop timer p, set tpnce = 0. pwm waveform output is performed from the topn1 pin. the topn0 pin performs toggle output upon a match between the 16-bit counter and the tpnccr0 register. since the tpnccr0 and tpnccr1 registers have their function fixed that of a compare register in the pwm mode, they cannot be used for capture operation in this mode. remark n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 258 figure 7-14. flowchart of basic operation in pwm mode (1/2) (a) values of tpnccr0, tpnccr1 registers not rewritten during timer operation start initial settings ? clock selection (tpnctl0: tpncks2 to tpncks0) ? pwm mode settings (tpnctl1: tpnmd2 to tpnmd0 = 100) ? compare register setting (tpnccr0, tpnccr1) match between 16-bit counter and ccr1 buffer register, topn1 low-level output match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start topn1 high-level output inttpncc1 output inttpncc0 output timer operation enable (tpnce = 1) transfer of tpnccrm register values to ccrm buffer register remark n = 0 to 5, m = 0, 1
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 259 figure 7-14. flowchart of basic operation in pwm mode (2/2) (b) values of tpnccr0, tpnccr1 registers rewritten during timer operation start initial settings ? clock selection (tpnctl0: tpncks2 to tpncks0) ? pwm mode setting (tpnctl1: tpnmd2 to tpnmd0 = 100) ? compare register setting (tpnccr0, tpnccr1) match between 16-bit counter and tpnccr1, topn1 low-level output match between 16-bit counter and tpnccr0, 16-bit counter clear & start, topn1 high-level output inttpncc1 output inttpncc0 output reload enable inttpncc0 output tpnccr1 rewrite tpnccr0 rewrite ? match between ccr0 buffer register and 16-bit counter ? 16-bit counter clear & start ? values of tpnccrm reloaded to ccrm buffer register note <1> <2> <3> inttpncc1 output timer operation enable (tpnce = 1) transfer of tpnccrm register values to ccrm buffer register match between 16-bit counter and ccr1 buffer register, topn1 low-level output note the timing of <2> in the above flowchart may differ depending on the rewrite timing of steps <1> and <3> and the value of tpnccr1, but make sure that step <3> comes after step <1>. remark n = 0 to 5 m = 0, 1
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 260 figure 7-15. basic operation timing in pwm mode (1/2) (a) tpnccr1 value rewritten tpnce = 1 16-bit counter tpnccr0 tpnccr1 topn1 topn0 ccr0 buffer register ccr1 buffer register 0000h 0000h d 10 d 11 d 12 d 13 d 00 d 00 d 00 d 00 d 00 d 00 d 10 d 10 d 10 d 11 d 11 d 12 d 12 d 13 ffffh remarks 1. d 00 : setting value of tpnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 , d 13 : setting values of tpnccr1 register (0000h to ffffh) 2. topn1 output duty = (setting value of tpnccr1 register)/(setting value of tp0ccr0 register) topn1 output cycle = (setting value of tpnccr0 register) (count clock cycle) topn0 output toggle width = (setting value of tpnccr0 register + 1) (count clock cycle) 3. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 261 figure 7-15. basic operation timing in pwm mode (2/2) (b) tpnccr0, tpnccr1 values rewritten tpnce = 1 16-bit counter tpnccr0 tpnccr1 topn1 topn0 0000h 0000h d 10 d 11 d 12 d 12 d 00 d 00 d 10 d 10 d 11 d 11 d 11 d 12 d 12 d 12 d 00 d 01 d 02 d 03 d 01 d 01 d 01 d 02 d 02 d 03 ffffh same value write note note ccr0 buffer register ccr1 buffer register note reload is not performed because the tpnccr1 register was not rewritten. remarks 1. d 00 , d 01 , d 02 , d 03 : setting values of tpnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 , d 13 : setting values of tpnccr1 register (0000h to ffffh) 2. topn1 output duty = (setting value of tpnccr1 register)/(setting value of tp0ccr0 register) topn1 output cycle = (setting value of tpnccr0 register)/(count clock cycle) topn0 output toggle width = (setting value of tpnccr0 register + 1) (count clock cycle) 3. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 262 7.5.7 free-running mode (tpnmd2 to tpnmd0 = 101) in the free-running mode, both the interval function and the compare function can be realized by operating the 16- bit counter as a free-running counter and selecting capture/compare operation with the tpnccs1 and tpnccs0 bits. the settings of the tpnccs1 and tpnccs0 bits of the tpnopt0 register are valid only in the free-running mode. tpnccs1 operation 0 use tpnccr1 register as compare register 1 use tpnccr1 register as capture register tpnccs0 operation 0 use tpnccr0 register as compare register 1 use tpnccr0 register as capture register ? using tpnccr1 register as compare register an interrupt is output upon a match between the 16-bit counter and the ccr1 buffer register in the free-running mode (interval function). rewrite during compare timer operation is enabled and performed with anytime write. (once the compare value has been written, synchronization with the internal clock is done and this value is used as the 16-bit counter comparison value.) when timer output (topn1) has been enabled, topn1 performs toggle output upon a match between the 16-bit counter and the ccr1 buffer register. ? using tpnccr1 register as capture register the value of the 16-bit counter is saved to the tpnccr1 register upon tipn1 pin edge detection. ? using tpnccr0 register as compare register an interrupt is output upon a match between the 16-bit counter and the ccr0 buffer register in the free-running mode (interval function). rewrite during compare timer operation is enabled and performed with anytime rewrite. when timer output (topn0) has been enabled, topn0 performs toggle output upon a match between the 16-bit counter and the ccr0 buffer register. ? using tpnccr0 register as capture register the value of the 16-bit counter is saved to the tpnccr0 register upon tipn0 pin edge detection.
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 263 figure 7-16. flowchart of basic operation in free-running mode start initial settings ? clock selection (tpnctl0: tpncks2 to tpncks0) ? free-running mode setting (tpnctl1: tpnmd2 to tpnmd0 = 101) tpnccs1, tpnccs0 setting timer operation enable (tpnce = 1) transfer of tpnccr0 and tpnccr1 values to ccr0 buffer register ccr0 and ccr1 buffer registers respectively match between ccr1 buffer register and 16-bit counter match between ccr0 buffer register and 16-bit counter 16-bit counter overflow timer operation enable (tpnce = 1) transfer of tpnccr1 value to ccr1 buffer register tipn1 edge detection, capture of 16-bit counter value to tpnccr1 tipn0 edge detection, capture of 16-bit counter value to tpnccr0 16-bit counter overflow timer operation enable (tpnce = 1) tipn0 edge detection, capture of 16-bit counter value to tpnccr0 16-bit counter overflow match between ccr1 buffer register and 16-bit counter timer operation enable (tpnce = 1) transfer of tpnccr0 value to ccr0 buffer register 16-bit counter overflow tipn1 edge detection, capture of 16-bit counter value to tpnccr1 match between ccr0 buffer register and 16-bit counter tpnccs1 = 0 tpnccs0 = 0 tpnccs1 = 1 tpnccs0 = 0 tpnccs1 = 0 tpnccs0 = 1 tpnccs1 = 1 tpnccs0 = 1 tipn0 edge detection setting (tpnis1, tpnis0) tipn1 edge detection setting (tpnis3, tpnis2) tipn1, tipn0 edge detection setting (tpnis3 to tpnis0) remark n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 264 (1) tpnccs1 = 0, tpnccs0 = 0 settings (interval function description) when tpnce = 1 is set, the 16-bit counter counts from 0000h to ffffh and the free-running count-up operation continues until tpnce = 0 is set. in this mode, when a value is written to the tpnccr0 and tpnccr1 registers, they are transferred to the ccr0 buffer register and the ccr1 buffer register (anytime write). in this mode, no one-shot pulse is output even when a one-shot pulse trigger is input. moreover, when tpnoem = 1 is set, topnm performs toggle output upon a match between the 16-bit counter and the ccrm buffer register. remark n = 0 to 5, m = 0, 1 figure 7-17. basic operation timing in free-running mode (tpnccs1 = 0, tpnccs0 = 0) tpnce = 1 0000h 0000h d 10 d 11 d 10 d 11 d 10 d 00 d 00 d 11 d 11 d 01 d 00 d 00 d 01 d 01 ffffh 16-bit counter tpnccr0 topn0 topn1 inttpncc0 match interupt inttpncc1 match interupt tpnccr1 ccr0 buffer register ccr1 buffer register remarks 1. d 00 , d 01 : setting values of tpnccr0 register (0000h to ffffh) d 10 , d 11 : setting values of tpnccr1 register (0000h to ffffh) 2. topn0 output toggle width = (setting value of tpnccr0 register) (count clock cycle) topn1 output toggle width = (setting value of tpnccr1 register) 3. topnm output rises to the high level when counting is started. 4. n = 0 to 5, m = 0, 1
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 265 (2) tpnccs1 = 1, tpnccs0 = 1 settings (capture function description) when tpnce = 1, the 16-bit counter counts from 0000h to ffffh and free-running count-up operation continues until tpnce = 0 is set. during this time, values are captured by capture trigger operation and are written to the tpnccr0 and tpnccr1 registers. regarding capture in the vicinity of overflow (ffffh), judgment is made using the overflow flag (tpnovf). however, if overflow occurs twice (2 or more free-running cycles), the capture trigger interval cannot be judged with the tpnovf flag. in this case, the system should be revised. figure 7-18. basic operation timing in free-running mode (tpnccs1 = 1, tpnccs0 = 1) d 11 d 10 0000h d 12 16-bit counter ffffh tipn1 tipn0 tpnce = 1 tpnccr1 d 00 d 01 d 12 d 02 d 11 d 10 d 00 d 01 tpnccr0 d 02 d 03 0000h d 03 remarks 1. d 00 , d 01 : values captured to tpnccr0 register (0000h to ffffh) d 10 , d 11 : values captured to tpnccr1 register (0000h to ffffh) 2. tipn0: set to rising edge detection (tpnis1, tpnis0 = 01) tipn1: set to falling edge detection (tpnis3, tpnis2 = 10) 3. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 266 (3) tpnccs1 = 1, tpnccs0 = 0 settings when tpnce = 1 is set, the counter counts from 0000h to ffffh and free-running count-up operation continues until tpnce = 0 is set. the tpnccr0 register is used as a compare register. an interrupt signal is output upon a match between the value of the 16-bit counter and the setting value transferred to the ccr0 buffer register from the tpnccr0 register as an interval function. even if tpnoe1 = 1 is set to realize the capture function, the tpnccr1 register cannot control topn1. figure 7-19. basic operation timing in free-running mode (tpnccs1 = 1, tpnccs0 = 0) d 11 d 10 0000h d 13 d 15 d 14 d 12 16-bit counter ffffh tipn1 tpnccr0 tpnce = 1 tpnccr1 d 00 d 00 d 01 d 10 inttpncc0 match interrupt d 00 d 01 d 11 d 13 d 12 d 14 d 15 d 00 d 01 0000h ccr0 buffer register remarks 1. d 00 , d 01 : setting values of tpnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 , d 13 , d 14 , d 15 : values captured to tpnccr1 register (0000h to ffffh) 2. tipn1: set to detection of both rising and falling edges (tpnis3, tpnis2 = 11) 3. n = 0 to 5
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 267 (4) tpnccs1 = 0, tpnccs0 = 1 settings when tpnce is set to 1, the 16-bit counter counts from 0000h to ffffh and free-running count-up operation continues until tpnce = 0 is set. the tpnccr1 register is used as a compare register. an interrupt signal is output upon a match between the value of the 16-bit counter and the setting value of the tpnccr1 register as an interval function. when tpnoe1 = 1 is set, topn1 performs toggle output upon mach between the value of the 16-bit counter and the setting value of the tpnccr1 register. figure 7-20. basic operation timing in free-running mode (tpnccs1 = 0, tpnccs0 = 1) tpnce = 1 0000h d 10 d 11 d 12 0000h d 00 d 01 d 02 d 03 d 10 d 10 d 11 d 12 d 11 d 01 d 03 d 00 d 11 d 12 ffffh 16-bit counter tipn0 inttpncc1 tpnccr1 tpnccr0 inttpncc0 capture interrupt ccr1 buffer register d 02 remarks 1. d 00 , d 01 , d 02 , d 03 : values captured to tpnccr0 register (0000h to ffffh) d 10 , d 11 , d 12 : setting value of tpnccr1 register (0000h to ffffh) 2. tipn0: set to falling edge detection (tpnis1, tpnis0 = 10) 3. n = 0 to 5 (5) overflow flag when the counter overflows from ffffh to 0000h in the free-running mode, the overflow flag (tpnovf) is set to 1 and an overflow interrupt (inttpnov) is output. be sure to confirm that the overflow flag (tpnovf) is set to ? 1 ? when the overflow interrupt (inttpnov) has occurred. the overflow flag is cleared by writing 0 from the cpu.
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 268 7.5.8 pulse width measurement mode (tpnmd2 to tpnmd0 = 110) in the pulse width measurement mode, free-running count is performed, and upon detection of both the rising and falling edges of tipn0 pin, the 16-bit counter value is saved to capture register 0 (tpnccr0) and the 16-bit counter is cleared to 0000h. the external input pulse width can be measured as a result. however, when measuring a large pulse width that exceeds 16-bit counter overflow, perform judgment with the overflow flag. since measurement of pulses for which overflow occurs twice or more is not possible, adjust the operating frequency of the 16-bit counter. the value of the 16-bit counter is also saved to capture register 1 (tpnccr1) and the 16-bit counter cleared upon edge detection of the tipn1 pin. caution in the pulse width measurement mode, select the internal clock (tpneee of tpnctl1 register = 0). figure 7-21. flowchart of basic operation in pulse width measurement mode start initial settings ? clock selection (tpnctl0: tpncks2 to tpncks0) ? pulse width measurement mode setting (tpnctl1: tpnmd2 to tpnmd0 = 110) ? compare register setting (tpnccr0, tpnccr1) timer operation enable (tpnce = 1) rising edge input to tipnm, capture of value to tpnccrm, 16-bit counter clear & start tipn1/tipn0 edge detection setting note (tpnis3 to tpnis0) falling edge input to tipnm, capture of value to tpnccrm, 16-bit counter clear & start note external pulse input is possible both for tipn0 and tipn1, but only one can be selected. specify ? both the rising and the falling edges ? for edge detection. specify the edge of the external input pulse that is not used as ? no edge to be detected ? . remark n = 0 to 5, m = 0, 1
chapter 7 16-bit timer/event counter p preliminary user ? s manual u16541ej1v0um 269 figure 7-22. basic operation timing in pulse width measurement mode 16-bit counter ffffh inttpncc0 tipn0 tpnce = 1 tpnovf d 00 tpnccr0 0000h d 00 d 01 d 02 d 03 d 01 d 02 d 03 ffffh inttpnov cleared by writing 0 from cpu remarks 1. d 00 , d 01 , d 02 , d 03 : values captured to tpnccr0 register (0000h to ffffh) 2. tipn0: set to detection of both rising and falling edges (tpnis1, tpnis0 = 11) 3. n = 0 to 5
preliminary user?s manual u16541ej1v0um 270 chapter 8 16-bit timer/event counter q 8.1 features timer q (tmq) is a 16-bit timer/event counter that can be used in various ways. tmq can perform the following operations. ? pwm output ? interval timer ? external event count (operation not possible when clock is stopped) ? one-shot pulse output ? pulse width measurement function 8.2 function outline ? capture trigger input signal 4 ? external trigger input signal 1 ? clock select 8 ? external event count input 1 ? readable counter 1 ? capture/compare reload register 4 ? capture/compare match interrupt 4 ? timer output (toq00 to toq04) 4
chapter 8 16-bit timer/event counter q preliminary user?s manual u16541ej1v0um 271 8.3 configuration tmq includes the following hardware. table 8-1. tmq configuration item configuration timer register 16-bit counter 1 registers tmq0 timer capture/compare registers 0 to 3 (tq0ccr0 to tq0ccr3) tmq0 read buffer register (tq0cnt) ccr0 buffer register to ccr3 buffer register timer input 4 (tiq00 note to tiq03) timer output 4 (toq00 totoq03) control registers tmq0 control registers 0, 1 (tq0ctl0, tq0ctl1) tmq0 i/o control registers 0 to 2 (tq0ioc0 to tq0ioc2) tmq0 option register 0 (tq0opt0) note tiq00 is multiplexed with a capture trigger input signal, external trigger input signal, and external event input signal. figure 8-1. timer q block diagram f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 selector internal bus internal bus toq00 toq01 toq02 toq03 tiq00 tiq01 tiq02 tiq03 selector edge detector tq0ccr0 tq0ccr1 ccr3 buffer register tq0ccr2 tq0ccr3 tq0cnt inttq0ov inttq0cc0 inttq0cc1 inttq0cc2 inttq0cc3 clear output controller ccr1 buffer register ccr2 buffer register ccr0 buffer register 16-bit timer counter
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 272 (1) tmq0 capture/compare register 0 (tq0ccr0) the tq0ccr0 register is a 16-bit register that functions both as a capture register and as a compare register. whether this register functions as a capture register or as a compare register can be controlled with the tq0ccs0 bit of the tq0opt0 register, but only in the free-running mode. in the pulse width measurement mode, this register can be used as a dedicated capture register (the compare function cannot be used.) in modes other than the free-running mode and pulse width measurement mode, this register is used as a dedicated compare register. in the initial setting, the tq0ccr0 register is a compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tq0ccr0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff546h 14 0 13 11 9 7 5 3 15 1 ? use as a compare register tq0ccr0 can be rewritten when tq0ce = 1 the rewrite method is as follows. tmq operation mode method of writing tq0ccr0 register pwm mode, external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode anytime write pulse width measurement mode cannot be used because dedicated capture register ? use as capture register the counter value is saved to tq0ccr0 upon capture trigger (tiq00) input edge detection.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 273 (2) tmq0 capture/compare register 1 (tq0ccr1) the tq0ccr1 register is a 16-bit register that functions both as a capture register and as a compare register. whether this register functions as a capture register or as a compare register can be controlled with the tq0ccs1 bit of the tq0opt0 register, but only in the free-running mode. in the pulse width measurement mode, this register can be used as a dedicated capture register (the compare function cannot be used.) in modes other than the free-running mode and pulse width measurement mode, this register is used as a dedicated compare register. in the initial setting, the tq0ccr1 register is a reload register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tq0ccr1 12 10 8 6 4 2 after reset: 0000h r/w address: fffff548h 14 0 13 11 9 7 5 3 15 1 ? use as a compare register tq0ccr1 can be rewritten when tq0ce = 1 the rewrite method is as follows. tmq operation mode method of writing tq0ccr1 register pwm mode, external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode anytime write pulse width measurement mode cannot be used because dedicated capture register ? use as a capture register the counter value is saved to tq0ccr1 upon capture trigger (tiq01) input edge detection.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 274 (3) tmq0 capture/compare register 2 (tq0ccr2) the tq0ccr2 register is a 16-bit register that functions both as a capture register and as a compare register. whether this register functions as a capture register or as a compare register can be controlled with the tq0ccs2 bit of the tq0opt0 register, but only in the free-running mode. in the pulse width measurement mode, this register can be used as a dedicated capture register (the compare function cannot be used.) in modes other than the free-running mode and pulse width measurement mode, this register is used as a dedicated compare register. in the initial setting, the tq0ccr2 register is a compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tq0ccr2 12 10 8 6 4 2 after reset: 0000h r/w address: fffff54ah 14 0 13 11 9 7 5 3 15 1 ? use as a compare register tq0ccr2 can be rewritten when tq0ce = 1 the rewrite method is as follows. tmq operation mode method of writing tq0ccr2 register pwm mode, external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode anytime write pulse width measurement mode cannot be used because dedicated capture register ? use as capture register the counter value is saved to tq0ccr2 upon capture trigger (tiq02) input edge detection.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 275 (4) tmq0 capture/compare register 3 (tq0ccr3) the tq0ccr3 register is a 16-bit register that functions both as a capture register and as a compare register. whether this register functions as a capture register or as a compare register can be controlled with the tq0ccs3 bit of the tq0opt0 register, but only in the free-running mode. in the pulse width measurement mode, this register can be used as a dedicated capture register (the compare function cannot be used.) in modes other than the free-running mode and pulse width measurement mode, this register is used as a dedicated compare register. in the initial setting, the tq0ccr3 register is a compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. tq0ccr3 12 10 8 6 4 2 after reset: 0000h r/w address: fffff54ch 14 0 13 11 9 7 5 3 15 1 ? use as a compare register tq0ccr3 can be rewritten when tq0ce = 1 the rewrite method is as follows. tmq operation mode method of writing tq0ccr3 register pwm mode, external trigger pulse output mode reload free-running mode, external event count mode, one-shot pulse mode, interval timer mode anytime write pulse width measurement mode cannot be used because dedicated capture register ? use as capture register the counter value is saved to tq0ccr3 upon capture trigger (tiq03) input edge detection. (5) tmq0 read buffer register 0 (tq0cnt) the tq0cnt register is a read buffer register that can read 16-bit counter values. this register is read-only, in 16-bit units. reset input clears this register to 0000h. tq0cnt 12 10 8 6 4 2 after reset: 0000h r address: fffff54eh 14 0 13 11 9 7 5 3 15 1
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 276 8.4 control registers (1) tmq0 control register 0 (tq0ctl0) the tq0ctl0 register is an 8-bit register that controls the operation of timer q. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. the same value can always be written to the tq0ctl0 register by software. tq0ce internal operating clock operation disabled (tmq0 reset asynchronously) internal operating clock operation enabled tq0ce 0 1 timer qn operation control tq0ctl0 0 0 0 0 tq0cks2 tq0cks1 tq0cks0 654321 after reset: 00h r/w address: fffff540h internal operating clock control and tmq0 asynchronous reset are performed with the tq0ce bit. when the tq0ce bit is cleared to 0, the internal operating clock of tmq0 stops (fixed to low level) and tmq0 is reset asynchronously. when the tq0ce bit is set to 1, the internal operating clock is enabled and count-up operation starts within 2 input clocks after the tq0ce bit was set to 1. <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 tq0cks2 0 0 0 0 1 1 1 1 internal count clock selection tq0cks1 0 0 1 1 0 0 1 1 tq0cks0 0 1 0 1 0 1 0 1 caution set the tq0cks2 to tq0cks0 bits when tq0ce = 0. when the value of the tq0ce bit is changed from 0 to 1, the tq0cks2 to tq0cks0 bits can be set simultaneously.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 277 (2) tmq0 control register 1 (tq0ctl1) 0 no operation in one-shot pulse mode: one-shot pulse software trigger in external trigger pulse output mode: pulse output software trigger tq0est 0 1 software trigger control tq0ctl1 tq0est tq0eee 0 0 tq0md2 tq0md1 tq0md0 <6> <5> 4 3 2 1 after reset: 00h r/w address: fffff541h the tq0est bit functions as a software trigger in the one-shot pulse mode and the external trigger pulse output mode. (this bit is invalid even if it is controlled in any other mode.) tq0est functions as a software trigger if it is set to 1 when tq0ce = 1. therefore, be sure to set tq0est to 1 when tq0ce = 1. the tiq00 pin is used for an external trigger. the read value of the tq0est bit is always 0. use the internal clock (clock selected with bits tq0cks2 to tq0cks0) use the clock input from the tiq00 pin tq0eee 0 1 count clock selection the valid edge when tq0eet = 1 (the clock input from the tiq00 pin) is specified with bits tq0ees1 and tq0ees0. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse mode pwm mode free-running mode pulse width measurement mode setting prohibited tq0md2 0 0 0 0 1 1 1 1 timer mode selection tq0md1 0 0 1 1 0 0 1 1 tq0md0 0 1 0 1 0 1 0 1 caution set the tq0eee and tq0md2 to tq0md0 bits when tq0ce = 0. (the same value can be written when tq0ce = 1.) the operation is not guaranteed when rewriting is performed when tq0ce = 1. if rewriting was mistakenly performed, set tq0ce = 0 and then set the bits again.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 278 (3) tmq0 i/o control register 0 (tq0ioc0) the tq0ioc0 register is an 8-bit register that controls the timer output. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. tq0ol3 tq0oln 0 1 timer output level setting (n = 0 to 3) normal output inverted output tq0ioc0 tq0oe3 tq0ol2 tq0oe2 tq0ol1 tq0oe1 tq0ol0 tq0oe0 <6> <5> <4> <3> <2> <1> after reset: 00h r/w address: fffff542h tq0oen 0 1 timer output setting (n = 0 to 3) timer output prohibited (low level and high level are output from toq0n pin when tq0oln = 0 and tq0oln = 1, respectively.) timer output enabled (a pulse is output from the toq0n pin.) <7> <0> caution rewrite the tq0oln and tq0oen bits when tq0ce = 0. (the same value can be written when tq0ce = 1.) if rewriting was mistakenly performed, set tq0ce = 0 and then set the bits again.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 279 (4) tmq0 i/o control register 1 (tq0ioc1) the tq0ioc1 register is an 8-bit register that controls the valid edge for the external input signals (tiq00 to tiq03). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. tq0is7 tq0is7 0 0 1 1 tq0is6 0 1 0 1 capture input (tiq03) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tq0ioc1 tq0is6 tq0is5 tq0is4 tq0is3 tq0is2 tq0is1 tq0is0 654321 after reset: 00h r/w address: fffff593h tq0is5 0 0 1 1 tq0is4 0 1 0 1 capture input (tiq02) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tq0is3 0 0 1 1 tq0is2 0 1 0 1 capture input (tiq01) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tq0is1 0 0 1 1 tq0is0 0 1 0 1 capture input (tiq00) valid edge detection no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tq0is3 to tq0is0 bits when tq0ce = 0. (the same value can be written when tq0ce = 1.) if rewriting was mistakenly performed, set tq0ce = 0 and then set the bits again. 2. the tq0is7 to tq0is0 bits are valid only in the free- running mode and pulse width measurement mode. in the other modes, the capture operation is not performed.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 280 (5) tmq0 i/o control register 2 (tq0ioc2) the tq0ioc2 register is an 8-bit register that controls the valid edge for external event counter input signal (tiq00) and external trigger input signal (tiq00). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 tq0ees1 0 0 1 1 tq0ees0 0 1 0 1 external event count input (tiq00) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tq0ioc2 0 0 0 tq0ees1 tq0ees0 tq0ets1 tq0ets0 654321 after reset: 00h r/w address: fffff544h tq0ets1 0 0 1 1 tq0ets0 0 1 0 1 external trigger input (tiq00) valid edge detection no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tq0eesn and tq0estn bits when tq0ce = 0. (the same value can be written when tq0ce = 1.) if rewriting was mistakenly performed, set tq0ce = 0 and then set the bits again. 2. the tqnees1 and tqnees0 bits are valid only when the tqneee bit = 1 or when the external event count mode is set (tq0md2 to tq0md0 of tq0ctl1 register = 001).
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 281 (6) tmq0 option register 0 (tq0opt0) the tq0opt0 register is an 8-bit register used to set the capture/compare operation and detect overflow. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. tq0ccs3 tq0ccsn 0 1 tq0ccrn register capture/compare selection (n = 0 to 3) the tq0ccsn bit setting is valid only in the free-running mode. compare register selection capture register selection tq0opt0 tq0ccs2 tq0ccs1 tq0ccs0 0 0 0 tq0ovf 654321 after reset: 00h r/w address: fffff545h tq0ovf set (1) reset (0) timer q overflow detection the tq0ovf bit is reset when the 16-bit counter value overflows from ffffh to 0000h in the free-running mode or the pulse width measurement mode. an interrupt request signal (inttq0ov) is generated at the same time that the tq0ovf bit is set (1). the inttq0ov signal is not generated in modes other than the free-running mode and the pulse width measurement mode. the tq0ovf bit is not cleared even when the tq0ovf bit and the tq0opt0 register are read when tq0ovf = 1. the tq0ovf bit can be both read and written, but 1 cannot be written to the tq0ovf bit from the cpu. writing 1 has no influence on the operation of timer q. overflow occurrence tq0ovf bit 0 write or tq0ce = 0 7 <0> caution rewrite the tq0ccs3 to tq0ccs0 bits when tq0ce = 0. (the same value can be written when tq0ce = 1.) if rewriting was mistakenly performed, set tq0ce = 0 and then set the bits again.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 282 8.5 operation timer q can perform the following operations. operation tq0est (software trigger bit) tiq00 (external trigger input) capture/compare write compare write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only reload one-shot pulse output mode note 2 valid valid compare only anytime write pwm mode invalid invalid compare only reload free-running mode invalid invalid capture/compare switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count function, specify that the edge of the tiq00 capture input is not detected (by clearing the tq0is1 and tq0is0 bits of the tq0ioc1 register to ? 00 ? ). 2. when using the external trigger pulse output mode, one-shot pulse mode, or pulse width measurement mode, select the internal clock as the count clock (by setting the tq0eee bit of the tq0ctl1 register to 1). 8.5.1 anytime write and reload tq0ccr0 to tq0ccr3 register rewrite is possible for timer q during timer operation (tq0ce = 1), but the write method (anytime write, reload) differs depending on the mode. (1) anytime write when the tq0ccr0 to tq0ccr3 registers are written during timer operation, the write data is transferred at that time to the ccr0 buffer register and used as the 16-bit counter comparison value.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 283 figure 8-2. flowchart of basic operation for anytime write start inttq0cc0 output timer operation enable (tq0ce = 1) transfer of tq0ccrn value to ccrn buffer register (n = 0 to 3) tq0ccr0 rewrite transfer to ccr0 buffer register tq0ccr1 rewrite transfer to ccr1 buffer register tq0ccr2 rewrite transfer to ccr2 buffer register tq0ccr3 rewrite transfer to ccr3 buffer register ? match between ccr0 buffer register and 16-bit counter ? 16-bit counter clear & start initial settings remark the above flowchart illustrates an example of the operation in the interval timer mode.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 284 figure 8-3. timing diagram for anytime write tq0ce = 1 16-bit counter tq0ccr0 tq0ccr1 tq0ccr2 tq0ccr3 inttq0cc0 inttq0cc1 inttq0cc2 inttq0cc3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 11 d 11 d 12 d 11 d 11 d 12 d 12 d 21 d 21 d 21 d 01 d 01 d 02 d 02 d 01 d 12 d 21 0000h d 01 d 02 0000h d 21 d 31 0000h d 31 d 31 d 31 d 31 d 31 remarks 1. d 01 , d 02 : setting values of tq0ccr0 register (0000h to ffffh) d 11 , d 12 : setting values of tq0ccr1 register (0000h to ffffh) d 21 : setting value of tq0ccr2 register (0000h to ffffh) d 31 : setting value of tq0ccr3 register (0000h to ffffh) 2. the above timing chart illustrates an example of the operation in the interval timer mode.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 285 (2) reload when the tq0ccrn register is written during timer operation via the ccrn buffer register, the write data is used as the 16-bit counter comparison value. the tq0ccrn register can be rewritten when tq0ce = 1. in order for the setting value when the tq0ccrn register is rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to the ccrn buffer register), it is necessary to rewrite tq0ccr0 and finally write to the tq0ccr1 register before the 16-bit counter value and the ccrn buffer register value match. when the ccrn buffer register value later matches the 16-bit counter value, the tq0ccrn register value is reloaded to the ccrn buffer register. whether to enable or disable the next reload timing is controlled by writing to the tq0ccr1 register. figure 8-4. flowchart of basic operation for reload start reload enable timer operation enable (tq0ce = 1) transfer of tq0ccrn value to ccrn buffer register tq0ccr0 rewrite tq0ccr2 rewrite tq0ccr3 rewrite tq0ccr1 rewrite ? match between tq0ccr0 and 16-bit counter ? 16-bit counter clear & start ? reload of tq0ccrn value to ccrn buffer register inttq0cc0 output initial settings caution writing to the tq0ccr1 register includes enabling of reload. therefore, rewrite the tq0ccr1 register after rewriting the other tq0ccr registers. remark the above flowchart illustrates an example of the operation in the pwm mode.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 286 figure 8-5. timing chart for reload tq0ce = 1 16-bit counter tq0ccr0 tq0ccr1 tq0ccr2 tq0ccr3 inttq0cc0 inttq0cc1 inttq0cc2 inttq0cc3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 d 02 d 03 0000h d 11 0000h d 21 d 12 d 21 d 12 0000h d 31 d 32 d 33 d 31 d 32 d 33 d 01 d 02 d 03 d 11 d 12 d 12 d 21 d 31 d 11 d 01 d 21 d 21 d 12 d 12 d 12 d 12 d 32 d 32 d 32 d 02 d 02 d 03 d 21 d 21 note note note same value write note reload is not performed because the tq0ccr1 register was not rewritten. remarks 1. d 01 , d 02 , d 03 : setting values of tq0ccr0 register (0000h to ffffh) d 11 , d 12 : setting values of tq0ccr1 register (0000h to ffffh) d 21 : setting value of tq0ccr2 register (0000h to ffffh) d 31 , d 32 , d 33 : setting values of tq0ccr3 register (0000h to ffffh) 2. the above flowchart illustrates the operation in the pwm mode as an example.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 287 8.5.2 interval timer mode (tq0md2 to tq0md0 = 000) in the interval timer mode, an interrupt request signal (inttq0cc0) is output upon a match between the setting value of the tq0ccr0 register and the value of the 16-bit counter, and the 16-bit counter is cleared. the tq0ccrn register can be rewritten when tq0ce = 1, and when a value is set to tq0ccrn with a write instruction from the cpu, it is transferred to the ccrn buffer register through anytime write, and is used as the value for comparison with the 16-bit counter value. in the interval timer mode, the 16-bit counter is cleared only upon a match between the value of the 16-bit counter and the value of the ccr0 buffer register. 16-bit counter clearing using the tq0ccrm register is not performed. however, the setting value of the tq0ccrm register is transferred to the ccrm buffer register and compared with the value of the 16-bit counter, and an interrupt request (inttq0ccm) is output if these values match. moreover, toq0n pin output is also possible by setting the tq0oen bit to 1. when the tq0ccrm register is not used, it is recommended to set ffffh as the setting value for the tq0ccrm register. remark n = 0 to 3 m = 1 to 3 figure 8-6. flowchart of basic operation in interval timer mode start inttq0cc0 output timer operation enable (tq0ce = 1) transfer of tq0ccrn value to ccrn buffer register match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start match between 16-bit counter and ccrm buffer register note inttq0ccm output initial settings ? clock selection (tq0ctl0: tq0cks2 to tq0cks0) ? interval timer mode setting (tq0ctl0: tq0md2 to tq0md0 = 000) ? compare register setting (tq0ccr0 to tq0ccr3) note the 16-bit counter is not cleared upon a match between the 16-bit counter and tq0ccrm. remark n = 0 to 3 m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 288 figure 8-7. basic operation timing in interval timer mode (1/2) rewrite of tq0ccr0 register only; no toq0n output tq0ce = 1 16-bit counter tq0ccr0 ffffh tq0ccr1 tq0ccr2 tq0ccr3 inttq0cc0 inttq0cc1 inttq0cc2 inttq0cc3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 0000h d 11 0000h d 21 0000h d 31 d 11 d 21 d 31 d 02 d 01 d 31 d 31 d 31 d 11 d 11 d 21 d 11 d 01 d 01 d 02 d 02 remarks 1. d 01 , d 02 : setting values of tq0ccr0 register (0000h to ffffh) d 11 : setting value of tq0ccr1 register (0000h to ffffh) d 21 : setting value of tq0ccr2 register (0000h to ffffh) d 31 : setting value of tq0ccr3 register (0000h to ffffh) 2. interval time = (dn + 1) (count clock cycle) 3. n = 0 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 289 figure 8-7. basic operation timing in interval timer mode (2/2) d 01 = d 31 ; rewrite of tq0ccr1 only; toq0n output tq0ce = 1 16-bit counter tq0ccr0 ffffh tq0ccr1 tq0ccr2 tq0ccr3 inttq0cc0 inttq0cc1 inttq0cc2 inttq0cc3 toq01 toq02 toq03 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register toq00 0000h d 01 d 01 d 31 0000h d 11 d 12 d 11 d 12 0000h d 21 d 21 d 21 d 21 d 11 d 11 d 12 d 01 = d 31 d 01 = d 31 d 31 d 21 0000h remarks 1. d 01 : setting value of tq0ccr0 register (0000h to ffffh) d 11 , d 12 : setting values of tq0ccr1 register (0000h to ffffh) d 21 : setting value of tq0ccr2 register (0000h to ffffh) d 31 : setting value of tq0ccr3 register (0000h to ffffh) 2. interval time = (dn + 1) (count clock cycle) 3. n = 0 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 290 8.5.3 external event count mode (tq0md2 to tq0md0 = 001) in the external event count mode, external event count input (tiq00 pin input) is used as a count-up signal. when the external event count mode is set, count-up is performed using external event count input (tiq00 pin input), regardless of the setting of the tq0eee bit of the tq0ctl0 register. in the external event count mode, a match interrupt request (inttq0cc0) is output upon a match between the setting value of the tq0ccr0 register (value of ccr0 buffer register) and the value of the 16-bit counter, and the 16- bit counter is cleared. when a value is set to the tq0ccrn register with a write instruction from the cpu, it is transferred to the ccrn buffer register through anytime write, and is used as the value for comparison with the 16-bit counter value. in the external event count mode, the 16-bit counter is cleared only upon a match between the value of the 16-bit counter and the value of the ccr0 buffer register. 16-bit counter clearing using the tq0ccrm register is not performed. however, the setting value of the tq0ccrm register is transferred to the ccrm buffer register and compared with the value of the 16-bit counter, and an interrupt request (inttq0ccm) is output if these values match. moreover, toq0n pin output is also possible by setting the tq0oen bit to 1. the tq0ccr0 register can be rewritten when tq0ce = 1. when the tq0ccrm register is not used, it is recommended to set ffffh as the setting value for the tq0ccrm register. remark n = 0 to 3 m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 291 figure 8-8. flowchart of basic operation in external event count mode start inttq0cc0 output timer operation enable (tq0ce = 1) transfer of tq0ccrn value to ccrn buffer register match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start match between 16-bit counter and ccrm buffer register note 2 inttq0ccm output initial settings ? external event count mode setting (tq0ctl0: tq0md2 to tq0md0 = 001) note 1 ? valid edge setting (tq0ioc2: tq0ees1, tq0ees0) ? compare register setting (tq0ccrn) notes 1. selection of the tq0eee bit has no influence. 2. the 16-bit counter is not cleared upon a match between the 16-bit counter and the ccrm buffer register. remark n = 0 to 3 m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 292 figure 8-9. basic operation timing in external event count mode (1/2) (a) rewrite of tq0ccr0 only; no toq0n output tq0ce = 1 16-bit counter tq0ccr0 ffffh tq0ccr1 tq0ccr2 tq0ccr3 inttq0cc0 inttq0cc1 inttq0cc2 inttq0cc3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 0000h d 11 0000h d 21 0000h d 31 d 11 d 21 d 31 d 02 d 01 d 31 d 31 d 31 d 11 d 11 d 21 d 11 d 01 d 01 d 02 d 02 remarks 1. d 01 , d 02 : setting values of tq0ccr0 register (0000h to ffffh) d 11 : setting value of tq0ccr1 register (0000h to ffffh) d 21 : setting value of tq0ccr2 register (0000h to ffffh) d 31 : setting value of tq0ccr3 register (0000h to ffffh) 2. interval time = (dn + 1) (count clock cycle) 3. n = 0 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 293 figure 8-9. basic operation timing in external event count mode (2/2) (b) d 01 = d 31 ; rewrite of tq0ccr1 only; toq0n output tq0ce = 1 16-bit counter tq0ccr0 ffffh tq0ccr1 tq0ccr2 tq0ccr3 inttq0cc0 inttq0cc1 inttq0cc2 inttq0cc3 toq01 toq02 toq03 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register 0000h d 01 d 01 d 31 0000h d 11 d 12 d 11 d 12 0000h d 21 d 21 d 21 d 21 d 11 d 11 d 12 d 01 = d 31 d 01 = d 31 d 31 d 21 0000h remarks 1. d 01 : setting value of tq0ccr0 register (0000h to ffffh) d 11 , d 12 : setting values of tq0ccr1 register (0000h to ffffh) d 21 : setting value of tq0ccr2 register (0000h to ffffh) d 31 : setting value of tq0ccr3 register (0000h to ffffh) 2. interval time = (dn + 1) (count clock cycle) 3. n = 0 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 294 8.5.4 external trigger pulse mode (tq0md2 to tq0md0 = 010) in the external trigger pulse mode, setting tq0ce = 1 causes external trigger input (tiq00 pin input) wait with the 16-bit counter stopped at ffffh. the count-up operation starts upon detection of the external trigger input (tiq00 pin input) edge. regarding toq0m output control, the reload register (tq0ccrm) is used as the duty setting register and the compare register (tq0ccr0) is used as the cycle setting register. the tq0ccrn register can be rewritten when tq0ce = 1. in order for the setting value when the tq0ccrn register is rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to the ccrn buffer register), it is necessary to rewrite tq0ccr0 and finally write to the tq0ccr1 register before the 16-bit counter value and the tq0ccr0 register value match. thereafter, the value of the tq0ccr0 is reloaded upon a tq0ccr0 register match. whether to enable or disable the next reload timing is controlled by writing to the tq0ccr1 register. thus even when wishing only to rewrite the value of the tq0ccr0 register, also write the same value to the tq0ccr1 register. reload is disabled even when only the tq0ccr0 register is rewritten. to stop timer q, set tq0ce = 0. if the external trigger (tiq00 pin input) edge is detected several times in the external trigger pulse mode, the 16-bit counter is cleared at the edge detection timing and count-up starts. to realize the same function (software trigger pulse mode) as external trigger pulse mode using a software trigger instead of external trigger input (tiq00 pin input), set the tq0est bit of the tq0ctl1 register to 1 so that the software trigger is output. the external trigger pulse waveform is output from toq0m. since the tq0ccrn register has its function fixed to that of a compare register in the external trigger pulse mode, they cannot be used for capture operation in this mode. caution in the external trigger pulse mode, select the internal clock (tq0eee bit of tq0ctl1 register = 0) for the count clock. remarks 1. for the reload operation when tq0ccrn is rewritten during timer operation, refer to 8.5.6 pwm mode . 2. n = 0 to 3 m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 295 figure 8-10. flowchart of basic operation in external trigger pulse output mode start inttq0cc0 output timer operation enable (tq0ce = 1) transfer of tq0ccrn value to ccrn buffer register match between 16-bit counter and tq0ccr0, 16-bit counter clear & start match between 16-bit counter and tq0ccrm note external trigger (tiq00 pin) input 16-bit counter start inttq0ccm output initial settings ? clock selection (tq0ctl1: tq0eee = 0) (tq0ctl0: tq0cks2 to tq0cks0) ? external trigger pulse output mode setting (tq0ctl1: tq0md2 to tq0md0 = 010) ? compare register setting (tq0ccrn) external trigger (tiq00 pin) input 16-bit counter clear & start note the 16-bit counter is not cleared upon a match between the 16-bit counter and the ccrm buffer register. remark n = 0 to 3 m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 296 figure 8-11. basic operation timing in external trigger pulse output mode tq0ce = 1 16-bit counter tq0ccr0 ffffh tq0ccr1 tq0ccr2 tq0ccr3 toq01 toq02 toq03 ccr0 buffer register output trigger (tiq00 pin) ccr1 buffer register ccr2 buffer register ccr3 buffer register toq00 d 01 d 02 d 01 d 02 d 11 d 12 d 11 d 12 d 31 d 32 d 31 d 32 d 21 d 21 d 31 d 31 d 11 d 21 d 21 d 01 d 12 d 02 d 12 d 32 0000h 0000h 0000h 0000h remarks 1. d 01 , d 02 : setting values of tq0ccr0 register (0000h to ffffh) d 11 , d 12 : setting values of tq0ccr1 register (0000h to ffffh) d 21 : setting value of tq0ccr2 register (0000h to ffffh) d 31 , d 32 : setting values of tq0ccr3 register (0000h to ffffh) 2. toqm output duty = (setting value of tq0ccrm register)/(setting value of tq0ccr0 register) toqm output cycle = (setting value of tq0ccr0 register) (count clock cycle) 3. m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 297 8.5.5 one-shot pulse mode (tq0md2 to tq0md0 = 011) in the one-shot pulse mode, setting tq0ce = 1 causes tq0est bit setting (1) or tiq00 pin edge detection trigger wait with the 16-bit counter held at ffffh. the 16-bit counter starts counting up upon trigger input, and upon a match between the value of the 16-bit counter and the value of the ccrm buffer register transferred from the tq0ccrm register, toq0m becomes high level; upon a match between the value of the 16-bit counter and the value of the ccr0 register transferred from the tq0ccr0 register, toq0m becomes low level and the 16-bit counter is cleared to 0000h and stops. any trigger input past the first one during 16-bit counter operation is ignored. be sure to input the second and subsequent triggers when the 16-bit counter has stopped at 0000h. in the one-shot pulse mode, the tq0ccrn register can be rewritten when tq0ce = 1. the setting values rewritten to the tq0ccrn register becomes valid following execution of a write instruction from the cpu, at which time they are transferred to the ccrn buffer register through anytime write, and become the values for comparison with the 16-bit counter value. the one-shot pulse waveform is output from the toq0m pin. the toqn0 pin performs toggle output upon a match between the 16-bit counter and the tq0ccr0 register. since the tq0ccrn register has their function fixed to that of a compare register in the one-shot pulse mode, they cannot be used for capture operation in this mode. caution in the one-shot pulse mode, select the internal clock (tq0eee bit of tq0ctl1 register = 0) for the count clock. remark n = 0 to 3 m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 298 figure 8-12. flowchart of basic operation in one-shot pulse mode start match between 16-bit counter and ccr0 buffer register, 16-bit counter clear external trigger (tiq00 pin) input, or tq0est = 1 16-bit counter start inttq0cc0 output timer operation enable (tq0ce = 1) transfer of tq0ccrn value to ccrn buffer register match between 16-bit counter and ccrm buffer register note trigger wait status, 16-bit counter in standby at ffffh trigger wait status, 16-bit counter in standby at 0000h inttq0ccm output initial settings ? clock selection (tq0ctl1: tq0eee = 0) (tq0ctl0: tq0cks2 to tq0cks0) ? one-shot pulse mode setting (tq0ctl1: tq0md2 to tq0md0 = 011) ? compare register setting (tq0ccrn) note the 16-bit counter is not cleared upon a match between the 16-bit counter and the ccrm buffer register. caution the 16-bit counter is not cleared and trigger input is ignored even if trigger input is performed during the count-up operation of the 16-bit counter. remark n = 0 to 3 m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 299 figure 8-13. timing of basic operation in one-shot pulse mode d 01 d 31 d 31 d 31 d 11 d 11 d 11 d 21 d 21 d 21 d 01 d 01 d 01 d 01 0000h d 11 d 11 0000h d 21 d 21 0000h d 31 d 32 d 31 d 32 0000h note tq0ce = 1 tq0est = 1 ffffh 16-bit counter external trigger (tq000 pin) tq0ccr0 inttq0cc0 tq0ccr1 tq0ccr2 inttq0cc1 inttq0cc2 inttq0cc3 toq01 toq00 toq02 toq03 ccr0 buffer register ccr1 buffer register ccr2 buffer register tq0ccr3 ccr3 buffer register note the 16-bit counter starts counting up when either tq0est = 1 is set or external trigger (tiq00 pin) is input. remark d 01 : setting value of tq0ccr0 register (0000h to ffffh) d 11 : setting value of tq0ccr1 register (0000h to ffffh) d 21 : setting value of tq0ccr2 register (0000h to ffffh) d 31 , d 32 : setting value of tq0ccr3 register (0000h to ffffh)
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 300 8.5.6 pwm mode (tq0md2 to tq0md0 = 110) in the pwm mode, tmq0 capture/compare register m (tq0ccrm) is used as the duty setting register and tmq0 capture/compare register 0 (tq0ccr0) is used as the cycle setting register. variable duty pwm is output by setting these two registers and operating the timer. the tq0ccrn register can be rewritten when tq0ce = 1. in order for the setting value when the tq0ccrn register is rewritten to become the 16-bit counter comparison value (in other words, in order for this value to be reloaded to ccrn buffer register), it is necessary to rewrite tq0ccr0 and finally write to the tq0ccr1 register before the 16-bit counter value and the tq0ccr0 register value match. thereafter, the values of the tq0ccrn register is reloaded upon a tq0ccr0 register match. whether to enable or disable the next reload timing is controlled by writing to the tq0ccr1 register. thus even when wishing only to rewrite the value of the tq0ccr0 register, also write the same value to the tq0ccr1 register. reload is disabled even when only the tq0ccr0 register is rewritten. to stop timer q, set tq0ce = 0. pwm waveform output is performed from the toq0m pin. the toq0m pin performs toggle output upon a match between the 16-bit counter and the tq0ccr0 register. since the tq0ccrn register has its function fixed that of a compare register in the pwm mode, they cannot be used for capture operation in this mode. remark n = 0 to 3 m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 301 figure 8-14. flowchart of basic operation in pwm mode (1/2) (i) value of tq0ccrn register not rewritten during timer operation start inttq0cc0 output timer operation enable (tq0ce = 1) transfer of tq0ccrn value to ccrn buffer register match between 16-bit counter and ccrm buffer register, toq0m low-level output match between 16-bit counter and ccr0 buffer register, 16-bit counter clear & start toq0m high-level output inttq0ccm output initial settings ? clock selection (tq0ctl0: tq0cks2 to tq0cks0) ? pwm mode settings (tq0ctl1: tq0md2 to tq0md0 = 100) ? compare register setting (tq0ccrn) remark n = 0 to 3 m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 302 figure 8-14. flowchart of basic operation in pwm mode (2/2) (ii) value of tq0ccrn register rewritten during timer operation start inttq0cc0 output match between 16-bit counter and ccrm buffer register, toq0m low-level output timer operation enable (tq0ce = 1) transfer of tq0ccrn value to ccrn buffer register match between 16-bit counter and tq0ccrm , toq0m low-level output rewite of registers other than tq0ccr1 (tq0ccr0, tq0ccr2, tq0ccr3) tq0ccr1 rewrite match between 16-bit counter and tq0ccr0, 16-bit counter clear & start, toq0m high-level output inttq0ccm output reload enable note <1> <2> <3> inttq0cc0 output inttq0ccm output initial settings ? clock selection (tq0ctl0: tq0cks2 to tq0cks0) ? pwm mode setting (tq0ctl1: tq0md2 to tq0md0 = 100) ? compare register setting (tq0ccrn) ? match between ccr0 buffer register and 16-bit counter ? 16-bit counter clear & start ? value of tq0ccrn reloaded to ccrn buffer register note the timing of <2> in the above flowchart may differ depending on the rewrite timing of steps <1> and <3> and the value of tq0ccrm, but make sure that step <3> comes after step <1>. remark n = 0 to 3 m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 303 figure 8-15. basic operation timing in pwm mode (1/2) (i) tq0ccr1 to tq0ccr3 values rewritten tq0ce = 1 ffffh 16-bit counter tq0ccr0 tq0ccr1 tq0ccr2 tq0ccr3 toq01 toq02 toq03 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register d 11 d 31 d 32 d 32 d 21 d 21 d 01 d 01 d 01 d 12 d 22 d 12 same value write toq00 0000h d 01 d 01 0000h d 11 d 12 d 12 d 31 d 32 d 33 0000h d 21 d 22 d 13 0000h d 31 d 32 d 33 d 11 d 12 d 12 d 21 d 22 d 13 remarks 1. d 10 : setting value of tq0ccr0 register (0000h to ffffh) d 11 , d 12 , d 13 : setting values of tq0ccr1 register (0000h to ffffh) d 21 , d 22 : setting values of tq0ccr2 register (0000h to ffffh) d 31 , d 32 , d 33 : setting values of tq0ccr3 register (0000h to ffffh) 2. toq0m output duty = (setting value of tq0ccrm register)/(setting value of tq0ccr0 register) toq0m output cycle = (setting value of tq0ccr0 register + 1) (count clock cycle) toq00 output toggle width = (setting value of tq0ccr0 register + 1) (count clock cycle) 3. m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 304 figure 8-15. basic operation timing in pwm mode (2/2) (ii) tq0ccr0 to tq0ccr3 values rewritten tq0ce = 1 ffffh 16-bit counter tq0ccr0 tq0ccr1 tq0ccr2 tq0ccr3 toq01 toq02 toq03 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register d 11 d 11 d 31 d 32 d 33 d 21 d 21 d 01 d 01 d 01 d 31 d 12 d 22 d 22 same value write toq00 0000h d 01 d 02 d 01 d 02 0000h d 11 d 12 d 31 d 32 d 33 0000h d 21 d 22 d 12 0000h d 31 d 32 d 33 d 11 d 12 d 21 d 22 d 12 note note note reload is not performed because the tq0ccr1 register was not rewritten. remarks 1. d 01 , d 02 : setting values of tq0ccr0 register (0000h to ffffh) d 11 , d 12 : setting values of tq0ccr1 register (0000h to ffffh) d 21 , d 22 : setting values of tq0ccr2 register (0000h to ffffh) d 31 , d 32 , d 33 : setting values of tq0ccr3 register (0000h to ffffh) 2. toq0m output duty = (setting value of tq0ccrm register)/(setting value of tq0ccr0 register) toq0m output cycle = (setting value of tq0ccr0 register + 1) (count clock cycle) toq00 output toggle width = (setting value of tq0ccr0 register + 1) (count clock cycle) 3. m = 1 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 305 8.5.7 free-running mode (tq0md2 to tq0md0 = 101) in the free-running mode, both the interval function and the compare function can be realized by operating the 16- bit counter as a free-running counter and selecting capture/compare operation with the tq0ccs3 to tq0ccs0 bits of the tq0opt0 register. the settings of the tq0ccs7 to tq0ccs0 bits of the tq0opt0 register are valid only in the free-running mode. tq0ccsn operation 0 use tq0ccrn register as compare register 1 use tq0ccrn register as capture register ? using tq0ccrn register as compare register an interrupt is output upon a match between the 16-bit counter and the ccrn buffer register in the free-running mode (interval function). rewrite during compare timer operation is enabled and performed with anytime write. (once the compare value has been written, synchronization with the internal clock is done and this value is used as the 16-bit counter comparison value.) when timer output (toq0n) has been enabled, toq0n performs toggle output upon a match between the 16-bit counter and the ccrn buffer register. ? using tq0ccrn register as capture register the value of the 16-bit counter is saved to the tq0ccrn register upon tiq0n pin edge detection. remark n = 0 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 306 figure 8-16. flowchart of basic operation in free-running mode start tq0ccsn setting initial settings ? clock selection (tq0ctl0: tq0cks2 to tq0cks0) ? free-running mode setting (tq0ctl1: tq0md2 to tq0md0 = 101) timer operation enable (tq0ce = 1) transfer of tq0ccrn value to ccrn buffer register match between ccrn buffer register and 16-bit counter 1 6-bit counter overflow tiq0n edge detection, capture of 16-bit counter value to tq0ccrn 16-bit counter overflow timer operation enable (tq0ce = 1) tiq0n edge detection setting (tq0ioc1 register note ) tq0ccsn = 0 (compare) tq0ccsn = 1 (capture) note tqccr0 edge detection: tq0is1 and tq0is0 bits tqccr1 edge detection: tq0is3 and tq0is2 bits tqccr2 edge detection: tq0is5 and tq0is4 bits tqccr3 edge detection: tq0is7 and tq0is6 bits remark n = 0 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 307 (1) tq0ccsn = 0 setting (interval function description) when tq0ce = 1 is set, the 16-bit counter counts from 0000h to ffffh and the free-running count-up operation continues until tq0ce = 0 is set. in this mode, when a value is written to the tq0ccrn register, it is transferred to the ccrn buffer register (anytime write). in this mode, no one-shot pulse is output even when a one-shot pulse trigger is input. moreover, when tq0oen = 1 is set, toq0n performs toggle output upon a match between the 16-bit counter and the ccrn buffer register. (2) tq0ccsn = 1 setting (capture function description) when tq0ce = 1, the 16-bit counter counts from 0000h to ffffh and free-running count-up operation continues until tq0ce = 0 is set. during this time, values are captured by capture trigger operation and are written to the tq0ccrn register. regarding capture in the vicinity of overflow (ffffh), judgment is made using the overflow flag (tq0ovf). however, if overflow occurs twice (2 or more free-running cycles), the capture trigger interval cannot be judged with the tq0ovf flag. remark n = 0 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 308 figure 8-17. basic operation timing in free-running mode (tq0ccs3 = 0, tq0ccs2 = 0, tq0ccs1 = 0, tq0ccs0 = 0) tq0ce = 1 ffffh 0000h d 00 d 00 d 00 d 00 d 20 d 20 d 20 d 30 d 30 d 10 d 11 d 11 d 31 d 01 d 01 d 01 0000h d 30 d 30 d 31 d 31 0000h d 20 d 20 0000h d 10 d 10 d 11 d 11 16-bit counter tq0ccr0 inttq0cc0 match interrupt toq00 inttq0cc1 match interrupt toq01 toq02 inttq0cc2 match interrupt toq03 inttq0cc3 match interrupt tq0ccr1 tq0ccr2 tq0ccr3 ccr0 buffer register ccr1 buffer register ccr2 buffer register ccr3 buffer register remarks 1. d 00 , d 01 : setting values of tq0ccr0 register (0000h to ffffh) d 10 , d 11 : setting values of tq0ccr1 register (0000h to ffffh) d 20 : setting value of tq0ccr2 register (0000h to ffffh) d 30 , d 31 : setting values of tq0ccr3 register (0000h to ffffh) 2. toq0n output toggle width = (setting value of tq0ccrn register) (count clock cycle) 3. toq0n output rises to high level when counting is started. 4. n = 0 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 309 figure 8-18. basic operation timing in free-running mode (tq0ccs3 = 1, tq0ccs2 = 1, tq0ccs1 = 1, tq0ccs0 = 1) 0000h d 20 d 21 d 22 0000h d 30 d 31 d 32 0000h d 10 d 11 d 12 d 20 d 30 d 00 d 10 d 01 d 21 d 31 d 22 d 11 d 02 d 12 d 32 tq0ce = 1 ffffh 16-bit counter tiq00 inttq0cc0 capture interrupt inttq0cc1 capture interrupt inttq0cc2 capture interrupt inttq0cc3 capture interrupt tiq01 tiq02 tiq03 tq0ccr0 tq0ccr1 tq0ccr2 tq0ccr3 0000h d 01 d 00 d 02 remarks 1. d 00 , d 01 , d 02 : values captured to tq0ccr0 register (0000h to ffffh) d 10 , d 11 , d 12 : values captured to tq0ccr1 register (0000h to ffffh) d 20 , d 21 , d 22 : values captured to tq0ccr2 register (0000h to ffffh) d 30 , d 31 , d 32 : values captured to tq0ccr3 register (0000h to ffffh) 2. tiq00: set to rising edge detection (tq0is1, tq0is0 = 01) tiq01: set to falling edge detection (tq0is3, tq0is2 = 10) tiq02: set to falling edge detection (tq0is5, tq0is4 = 10) tiq03: set to detection of both rising and falling edges (tq0is7, tq0is6 = 11)
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 310 figure 8-19. basic operation timing in free-running mode (tq0ccs3 = 1, tq0ccs2 = 1, tq0ccs1 = 1, tq0ccs0 = 0) 0000h d 20 d 21 d 20 d 21 0000h d 30 d 30 0000h d 10 d 11 d 12 d 13 d 30 d 30 d 30 d 00 d 01 d 21 d 11 d 20 d 20 d 02 d 03 d 13 d 10 tq0ce = 1 ffffh 16-bit counter tiq00 inttq0cc0 capture interrupt inttq0cc1 capture interrupt inttq0cc2 match interrupt inttq0cc3 match interrupt tiq01 tq0ccr2 tq0ccr3 inttq0cc0 tq0ccr1 0000h d 00 d 01 d 02 d 03 d 12 ccr2 buffer register ccr3 buffer register remarks 1. d 00 , d 01 , d 02 , d 03 : values captured to tq0ccr0 register (0000h to ffffh) d 10 , d 11 , d 12 , d 13 : values captured to tq0ccr1 register (0000h to ffffh) d 20 , d 21 : setting values of tq0ccr2 register (0000h to ffffh) d 30 : setting value of tq0ccr3 register (0000h to ffffh) 2. tiq00: set to rising edge detection (tq0is1, tq0is0 = 01) tiq01: set to falling edge detection (tq0is3, tq0is2 = 10)
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 311 figure 8-20. basic operation timing in free-running mode (tq0ccs3 = 1, tq0ccs2 = 0, tq0ccs1 = 0, tq0ccs0 = 1) 0000h d 20 d 21 0000h 0000h d 30 d 31 d 30 d 31 d 10 d 11 d 12 d 11 d 10 d 12 d 30 d 20 d 10 d 11 d 01 d 11 d 12 d 03 d 31 d 21 d 31 d 00 tq0ce = 1 ffffh 16-bit counter tiq00 inttq0cc0 capture interrupt inttq0cc1 match interrupt inttq0cc2 capture interrupt inttq0cc3 match interrupt tq0ccr1 tq0ccr2 tiq02 tq0ccr3 tq0ccr0 0000h d 00 d 01 d 02 d 03 ccr1 buffer register ccr3 buffer register d 02 remarks 1. d 00 , d 01 , d 02 , d 03 : values captured to tq0ccr0 register (0000h to ffffh) d 10 , d 11 , d 12 : setting values of tq0ccr1 register (0000h to ffffh) d 20 , d 21 : values captured to tq0ccr2 register (0000h to ffffh) d 30 , d 31 : setting values of tq0ccr3 register (0000h to ffffh) 2. tiq00: set to falling edge detection (tq0is1, tq0is0 = 10) tiq02: set to falling edge detection (tq0is5, tq0is4 = 10) (c) overflow flag when the counter overflows from ffffh to 0000h in the free-running mode, the overflow flag (tq0ovf) is set to 1 and an overflow interrupt (inttq0ov) is output. the overflow flag is cleared by writing 0 from the cpu.
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 312 8.5.8 pulse width measurement mode (tq0md2 to tq0md0 = 110) in the pulse width measurement mode, free-running count is performed, and upon detection of both the rising and falling edges of tiq00, the 16-bit counter value is saved to capture register n (tq0ccrn) and the 16-bit counter is cleared to 0000h. the external input pulse width can be measured as a result. however, when measuring a large pulse width that exceeds 16-bit counter overflow, perform judgment with the overflow flag. since measurement of pulses for which overflow occurs twice or more is not possible, adjust the operating frequency of the 16-bit counter. caution in the pulse width measurement mode, select the internal clock (tq0eee of tq0ctl1 register = 0). figure 8-21. flowchart of basic operation in pulse width measurement mode start tiq0n edge detection setting note (tq0is3 to tq0is0) rising edge input to tiq0n, capture of value to tq0ccrn, 16-bit counter clear & start falling edge input to tiq0n, capture of value to tq0ccrn, 16-bit counter clear & start timer operation enable (tq0ce = 1) initial settings ? clock selection (tq0ctl0: tq0cks2 to tq0cks0) ? pulse width measurement mode setting (tq0ctl1: tq0md2 to tq0md0 = 110) ? capture register setting (tq0opt0: tq0ccs3 to tq0ccs0) note external pulse input is possible any for tiq00 to tiq03, but only one can be selected. specify ? both the rising and the falling edges ? for edge detection. specify the edge of the external input pulse that is not used as ? no edge to be detected ? . remark n = 0 to 3
chapter 8 16-bit timer/event counter q preliminary user ? s manual u16541ej1v0um 313 figure 8-22. basic operation timing in pulse width measurement mode tq0ce = 1 0000h d 01 d 00 d 00 d 01 d 02 d 03 d 02 d 03 ffffh 16-bit counter tiq00 inttq0cc0 tq0ovf inttqov tq0ccr0 ffffh cleared by writing 0 from cpu remarks 1. d 00 , d 01 , d 02 , d 03 : values captured to tq0ccr0 register (0000h to ffffh) 2. tiq00: set to detection of both rising and falling edges
preliminary user?s manual u16541ej1v0um 314 chapter 9 16-bit interval timer m 9.1 outline ? interval function ? 8 clocks selectable ? simple counter 1 (the simple counter is a counter that does not use a counter read buffer and cannot be read during timer count operation.) ? simple compare 1 (simple compare is a type of compare that does not use a compare write buffer and the compare register cannot be written during timer counter operation.) ? compare match interrupt 1 timer m supports only the clear & start mode. the free-running mode is not supported. for operation equivalent to that in the free-running mode, set the compare register to ffffh to start the 16-bit counter in order to realize a function that uses the match interrupt as the overflow timing.
chapter 9 16-bit interval timer m preliminary user?s manual u16541ej1v0um 315 9.2 configuration tmm includes the following hardware. table 9-1. configuration of tmm item configuration timer register 16-bit counter register tmm compare register 0 (tm0cmp0) control register tmm0 control register (tm0ctl0) figure 9-1. block diagram of tmm tm0ctl0 internal bus f xx f xx /2 f xx /4 f xx /64 f xx /512 intwt f r /8 f xt controller 16-bit counter match clear inttm0eq0 tm0cmp0 tm0ce tm0cks2 tm0cks1tm0cks0 selector remark f xx : internal system clock frequency f r : ring-osc clock frequency f xt : subclock frequency (1) tmm0 compare register 0 (tm0cmp0) the tm0cmp0 register is a 16-bit compare register. this register can be read or written in 16-bit units. reset input clears this register to 0000h. the same value can always be written to the tm0cmp0 register by software. tm0cmp0 register rewrite is prohibited when the tm0ce bit = 1. tm0cmp0 12 10 8 6 4 2 after reset: 0000h r/w address: fffff694h 14 0 13 11 9 7 5 3 15 1
chapter 9 16-bit interval timer m preliminary user ? s manual u16541ej1v0um 316 9.3 control register (1) tmm0 control register (tm0ctl0) the tm0ctl0 register is an 8-bit register that controls the timer operation. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. the same value can always be written to the tm0ctl0 register by software. tm0ce internal clock operation disabled (tmm reset asynchronously) internal clock operation enabled tm0ce 0 1 internal clock operation enable/disable specification tm0ctl0 0 0 0 0 tm0cks2 tm0cks1 tm0cks0 654321 after reset: 00h r/w address: fffff690h the internal clock control and internal circuit reset for timer m are performed asynchronously with the tm0ce bit. when the tm0ce bit is cleared to 0, the internal clock of timer m is disabled (fixed to low level) and is reset asynchronously to the tmm latch. when the tm0ce bit is set to 1, the internal clock is enabled after 2 input clocks have been input after 1 is written to the tm0ce bit, and the count-up operation starts. <7> 0 f xx f xx /2 f xx /4 f xx /64 f xx /512 intwt f r /8 f xt tm0cks2 0 0 0 0 1 1 1 1 internal count clock selection tm0cks1 0 0 1 1 0 0 1 1 tm0cks0 0 1 0 1 0 1 0 1 caution the tm0cks2 to tm0cks0 bits can be rewritten when tm0ce = 0. however, the tm0cks2 to tm0cks0 and tm0ce bits are mapped to the same register. therefore, when changing the value of tm0ce from 0 to 1, it is also possible to change the value of bits tm0cks2 to tm0cks0. remark f xx : internal system clock frequency f r : ring-osc frequency f xt : subclock frequency
chapter 9 16-bit interval timer m preliminary user ? s manual u16541ej1v0um 317 9.4 operation 9.4.1 interval timer mode in the interval timer mode, a match interrupt signal (inttm0eq0) is output when the value of tmm0 compare register 0 (tm0cmp0) and the 16-bit counter value match, and at the same timing the counter is cleared to 0000h and the count-up operation is started again. the free-running mode can also be used when the tm0cmp0 register is set to ffffh. count clock 16-bit counter m ? 2m ? 1m m 0000h 0001h tm0cmp0 inttm0eq0 caution to set the interval time to m clocks, set m ? ? ? ? 1 to the tm0cmp0 register. 9.4.2 clock generator and clock enable timing since the value of the tm0ce bit is changed from 0 to 1 and the second clock becomes the initial pulse of the timer count-up signal, a miscount of 1 clock occurs.
preliminary user?s manual u16541ej1v0um 318 chapter 10 real-time output function (rto) 10.1 function the real-time output function transfers preset data to real-time output buffer registers 0l and 0h (rtbl0 and rtbh0), and then transfers this data by hardware to an external device via the output latches, upon occurrence of an external interrupt or external trigger. the pins through which the data is output to an external device constitute a port called a real-time output function (rto). because rto can output signals without jitter, it is suitable for controlling a stepper motor. in the v850es/sg2, one 6-bit real-time output port channel is provided. the real-time output port can be set to the port mode or real-time output port mode in 1-bit units. the block diagram of rto is shown below. figure 10-1. block diagram of rto real-time output buffer register 0h (rtbh0) real-time output latch 0h selector inttp5cc0 inttp0cc0 inttp4cc0 real-time output latch 0l rtpoe0 rtpeg0 byte0 extr0 real-time output port control register 0 (rtpc0) transfer trigger (h) transfer trigger (l) rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 real-time output port mode register 0 (rtpm0) 4 2 2 4 internal bus real-time output buffer register 0l (rtbl0) rtpout04, rtpout05 rtpout00 to rtpout03
chapter 10 real-time output function (rto) preliminary user ? s manual u16541ej1v0um 319 10.2 configuration rto consists of the following hardware. table 10-1. configuration of rto item configuration registers real-time output buffer registers 0l, 0h (rtbl0, rtbh0) control registers real-time output port mode register 0 (rtpm0) real-time output port control register 0 (rtpc0) (1) real-time output buffer registers 0l, 0h (rtbl0, rtbh0) the rtbl0 and rtbh0 registers are 4-bit registers that hold output data in advance. these registers are mapped to independent addresses in the peripheral i/o register area. these registers can be read or written in 8-bit or 1-bit units. reset input clears these registers to 00h. if an operation mode of 4 bits 1 channel or 2 bits 1 channel is specified (byte0 bit of rtpc0 register = 0), data can be individually set to the rtbl0 and rtbh0 registers. the data of both these registers can be read at once by specifying the address of either of these registers. if an operation mode of 6 bits 1 channel is specified (byte0 bit = 1), 8-bit data can be set to both the rtbl0 and rtbh0 registers by writing the data to either of these registers. moreover, the data of both these registers can be read at once by specifying the address of either of these registers. table 10-2 shows the operation when the rtbl0 and rtbh0 registers are manipulated. 0 rtbl0 rtbh0 0 rtbh05 rtbh04 rtbl03 rtbl02 rtbl01 rtbl00 after reset: 00h r/w address: rtbl0 fffff6e0h, rtbh0 fffff6e2h caution when writing to bits 6 and 7 of the rtbh0 register, always write 0. table 10-2. operation during manipulation of real-time output buffer register 0 read write note operation mode register to be manipulated higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbl0 rtbh0 rtbl0 invalid rtbl0 4 bits 1 channel, 2 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 invalid rtbl0 rtbh0 rtbl0 rtbh0 rtbl0 6 bits 1 channel rtbh0 rtbh0 rtbl0 rtbh0 rtbl0 note after setting the real-time output port, set output data to the rtbl0 and rtbh0 registers by the time a real- time output trigger is generated.
chapter 10 real-time output function (rto) preliminary user ? s manual u16541ej1v0um 320 10.3 control registers rto is controlled using the following two registers. ? real-time output port mode register 0 (rtpm0) ? real-time output port control register 0 (rtpc0) (1) real-time output port mode register 0 (rtpm0) the rtpm0 register selects the real-time output port mode or port mode in 1-bit units. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 rtpm0 0 1 port mode real-time output port mode selection of real-time output port rtpm0 0 rtpm05 rtpm04 rtpm03 rtpm02 rtpm01 rtpm00 after reset: 00h r/w address: fffff6e4h cautions 1. by enabling the real-time output operation (rtpoe0 bit of rtpc0 register = 1), the bits specified for the real-time output port mode in the rtpout00 to rtpout05 signals perform real-time output, and the bits specified for the port mode output 0. 2. if real-time output is disabled (rtpoe0 bit = 0), the real-time output signal bits (rtpout00 to rtpout05) all output 0, regardless of the rtpm0 register setting.
chapter 10 real-time output function (rto) preliminary user ? s manual u16541ej1v0um 321 (2) real-time output port control register 0 (rtpc0) the rtpc0 register is a register that sets the operation mode and output trigger of the real-time output port. the relationship between the operation mode and output trigger of the real-time output port is as shown in table 10-3. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. rtpoe0 disables operation note 1 enables operation rtpoe0 0 1 control of real-time output operation rtpc0 rtpeg0 byte0 extr0 0 0 0 0 falling edge note 2 rising edge rtpeg0 0 1 valid edge of inttp0cc0 signal 4 bits 2 channels 8 bits 1 channel byte0 0 1 specification of channel configuration for real-time output after reset: 00h r/w address: fffff6e5h < > notes 1. when the real-time output operation is disabled (rtpoe0 bit = 0), all the bits of the real-time output signals (rtpout00 to rtpout05) output ? 0 ? . 2. the inttp0cc0 signal is output for 1 clock of the count clock selected by tmp0. caution set the rtpeg0, byte0, and extr0 bits only when rtpoe0 = 0. table 10-3. operation modes and output triggers of real-time output port byte0 extr0 operation mode rtbh0 (rtp04, rtp05) rtbl0 (rtp00 to rtp03) 0 inttp5cc0 inttp4cc0 0 1 4 bits 1 channel, 2 bits 1 channel inttp4cc0 inttp0cc0 0 inttp4cc0 1 1 6 bits 1 channel inttp0cc0
chapter 10 real-time output function (rto) preliminary user ? s manual u16541ej1v0um 322 10.4 operation if the real-time output operation is enabled by setting the rtpoe0 bit of the rtpc0 register to 1, the data of real- time output buffer registers 0l and 0h (rtbh0 and rtbl0) is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the extr0 and byte0 bits of the rtpc0 register). of the transferred data, only the data of the bits specified in the real-time output port mode by the rtpm0 register is output from the rtpout00 to rtpout05 bits. the bits specified in the port mode by the rtpm0 register output 0. if the real-time output operation is disabled by clearing the rtpoe0 bit to 0, the rtpout00 to rtpout05 si gnals output 0 regardless of the setting of the rtpm0 register. figure 10-2. example of operation timing of rto0 (when extr0 bit = 0, byte0 bit = 0) abababab d01 d02 d03 d04 d11 d12 d13 d14 d11 d12 d13 d14 d01 d02 d03 d04 inttp5cc0 (internal) inttp4cc0 (internal) cpu operation rtbh0 rtbl0 rt output latch 0 (h) rt output latch 0 (l) a: software processing by interrupt request input to inttp5cc0 (rtbh0 write) b: software processing by interrupt request input to inttp4cc0 (rtbl0 write) remark for the operation during standby, see chapter 24 standby function .
chapter 10 real-time output function (rto) preliminary user ? s manual u16541ej1v0um 323 10.5 usage (1) disable real-time output. clear the rtpoe0 bit of the rtpc0 register to 0. (2) perform initialization as follows. ? set the alternate-function pins of port 5 set the pfc5.pfc5n bit and pfce5.pfce5n bit to 1, and then set the pmc5.pmc5n bit to 1 (n = 0 to 5). ? specify the real-time output port mode or port mode in 1-bit units. set the rtpm0 register. ? channel configuration: select the trigger and valid edge. set the extr0, byte0, and rtpeg0 bits of the rtpc0 register. ? set the initial values to the rtbh0 and rtbl0 registers note 1 . (3) enable real-time output. set the rtpoe0 bit = 1. (4) set the next output value to the rtbh0 and rtbl0 registers by the time the selected transfer trigger is generated note 2 . (5) set the next real-time output value to the rtbh0 and rtbl0 registers through interrupt servicing corresponding to the selected trigger. notes 1. if write to the rtbh0 and rtbl0 registers is performed when the rtpoe0 bit = 0, that value is transferred to real-time output latches 0h and 0l, respectively. 2. even if write is performed to the rtbh0 and rtbl0 registers when the rtpoe0 bit = 1, data transfer to real-time output latches 0h and 0l is not performed. 10.6 cautions (1) prevent the following conflicts by software. ? conflict between real-time output disable/enable switching (rtpoe0 bit) and selected real-time output trigger. ? conflict between write to the rtbh0 and rtbl0 registers in the real-time output enabled status and the selected real-time output trigger. (2) before performing initialization, disable real-time output (rtpoe0 bit = 0). (3) once real-time output has been disabled (rtpoe0 bit = 0), be sure to initialize the rtbh0 and rtbl0 registers before enabling real-time output again (rtpoe0 bit = 0 1).
preliminary user?s manual u16541ej1v0um 324 chapter 11 watch timer functions 11.1 functions the watch timer has the following functions. ? watch timer ? interval timer the watch timer and interval timer functions can be used at the same time. figure 11-1. block diagram of watch timer internal bus watch timer operation mode register (wtm) f brg f x f w /2 4 f w /2 5 f w /2 6 f w /2 7 f w /2 8 f w /2 10 f w /2 11 f w /2 9 f xt 11-bit prescaler prescaler 3 note clear clear intwt intwti wtm0 wtm1 wtm2 wtm3 wtm4 wtm5 wtm6 wtm7 5-bit counter f w 3 selector selector selector selector note for details about prescaler 3, see figure 11-2 block diagram of prescaler 3 . remark f brg : prescaler 3 output frequency f x : oscillation frequency f xt : subclock frequency f w : watch timer clock frequency intwt: watch timer interrupt inwti: interval timer interrupt
chapter 11 watch timer functions preliminary user ? s manual u16541ej1v0um 325 figure 11-2. block diagram of prescaler 3 f x f x /8 f x /4 f x /2 f x bgcs00 bgcs01 bgce0 3-bit prescaler 8-bit counter output control match f bgcs f brg prescaler mode register (prsm0) prescaler compare register (prscm0) 2 selector remark f bgcs : prescaler 3 count clock frequency f brg : prescaler 3 output frequency f x : oscillation frequency (1) watch timer the watch timer generates an interrupt request (intwt) at time intervals of 0.5 or 0.25 seconds by using the main clock or subclock. caution when using a clock obtained by dividing the main clock as the watch timer count clock, set the prsm0 and prscm0 registers according to the main clock frequency that is used so as to obtain a divided clock frequency of 32.768 khz. (2) interval timer the watch timer generates an interrupt request (intwti) at time intervals specified in advance. table 11-1. interval time of interval timer interval time operating at f w = 32.768 khz 2 4 1/f w 488 s 2 5 1/f w 977 s 2 6 1/f w 1.95 ms 2 7 1/f w 3.91 ms 2 8 1/f w 7.81 ms 2 9 1/f w 15.6 ms 2 10 1/f w 31.2 ms 2 11 1/f w 62.5 ms remark f w : watch timer clock frequency
chapter 11 watch timer functions preliminary user ? s manual u16541ej1v0um 326 11.2 configuration the watch timer consists of the following hardware. table 11-2. configuration of watch timer item configuration counter 5 bits 1 prescaler 11 bits 1 control register watch timer operation mode register (wtm)
chapter 11 watch timer functions preliminary user ? s manual u16541ej1v0um 327 11.3 control registers the watch timer operation mode register (wtm) controls the watch timer. before operating the watch timer, set the count clock and the interval time. (1) watch timer operation mode register (wtm) the wtm register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. this register is set by an 8-bit or 1-bit memory manipulation instruction. reset input clears this register to 00h. (1/2) wtm7 2 4 /f w (488 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 6 /f w (1.95 ms: f w = f xt ) 2 7 /f w (3.91 ms: f w = f xt ) 2 8 /f w (7.81 ms: f w = f xt ) 2 9 /f w (15.6 ms: f w = f xt ) 2 10 /f w (31.3 ms: f w = f xt ) 2 11 /f w (62.5 ms: f w = f xt ) 2 4 /f w (488 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 6 /f w (1.95 ms: f w = f brg ) 2 7 /f w (3.90 ms: f w = f brg ) 2 8 /f w (7.81 ms: f w = f brg ) 2 9 /f w (15.6 ms: f w = f brg ) 2 10 /f w (31.2 ms: f w = f brg ) 2 11 /f w (62.5 ms: f w = f brg ) wtm7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 wtm6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 selection of interval time of prescaler wtm wtm6 wtm5 wtm4 wtm3 wtm2 wtm1 wtm0 wtm5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 wtm4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 after reset: 00h r/w address: fffff680h < > < >
chapter 11 watch timer functions preliminary user ? s manual u16541ej1v0um 328 (2/2) 2 14 /f w (0.5 s: f w = f xt ) 2 13 /f w (0.25 s: f w = f xt ) 2 5 /f w (977 s: f w = f xt ) 2 4 /f w (488 s: f w = f xt ) 2 14 /f w (0.5 s: f w = f brg ) 2 13 /f w (0.25 s: f w = f brg ) 2 5 /f w (977 s: f w = f brg ) 2 4 /f w (488 s: f w = f brg ) wtm7 0 0 0 0 1 1 1 1 selection of set time of watch flag clears after operation stops starts wtm1 0 1 control of 5-bit counter operation wtm3 0 0 1 1 0 0 1 1 wtm2 0 1 0 1 0 1 0 1 stops operation (clears both prescaler and 5-bit counter) enables operation wtm0 0 1 watch timer operation enable caution rewrite the wtm2 to wtm7 bits while both the wtm0 and wtm1 bits are 0. remarks 1. f w : watch timer clock frequency 2. values in parentheses apply when f w = 32.768 khz
chapter 11 watch timer functions preliminary user ? s manual u16541ej1v0um 329 11.4 operation 11.4.1 operation as watch timer the watch timer generates an interrupt request at fixed time intervals. the watch timer operates using time intervals of 0.5 seconds with the subclock (32.768 khz) or prescaler 3 (at 32.768 khz). the count operation starts when the wtm1 and wtm0 bits of the wtm register are set to 11. when the wtm0 bit is cleared to 0, the 11-bit prescaler and 5-bit counter are cleared and the count operation stops. the time of the watch timer can be adjusted by clearing the wtm1 bit to 0 and then the 5-bit counter. at this time, an error of up to 15.6 ms may occur. the interval timer may be cleared by clearing the wtm0 bit to 0. however, because the 5-bit counter is cleared at the same time, an error of up to 0.5 seconds may occur when the watch timer overflows (intwt). 11.4.2 operation as interval timer the watch timer can also be used as an interval timer that repeatedly generates an interrupt at intervals specified by a count value set in advance. the interval time can be selected by the wtm4 to wtm7 bits of the wtm register. table 11-3. interval time of interval timer wtm7 wtm6 wtm5 wtm4 interval time 00002 4 1/fw 488 s (operating at f w = f xt = 32.768 khz) 00012 5 1/fw 977 s (operating at f w = f xt = 32.768 khz) 00102 6 1/fw 1.95 ms (operating at f w = f xt = 32.768 khz) 00112 7 1/fw 3.91 ms (operating at f w = f xt = 32.768 khz) 01002 8 1/fw 7.81 ms (operating at f w = f xt = 32.768 khz) 01012 9 1/fw 15.6 ms (operating at f w = f xt = 32.768 khz) 01102 10 1/fw 31.3 ms (operating at f w = f xt = 32.768 khz) 01112 11 1/fw 62.5 ms (operating at f w = f xt = 32.768 khz) 10002 4 1/fw 488 s (operating at f w = f brg = 32.768 khz) 10012 5 1/fw 977 s (operating at f w = f brg = 32.768 khz) 10102 6 1/fw 1.95 ms (operating at f w = f brg = 32.768 khz) 10112 7 1/fw 3.91 ms (operating at f w = f brg = 32.768 khz) 11002 8 1/fw 7.81 ms (operating at f w = f brg = 32.768 khz) 11012 9 1/fw 15.6 ms (operating at f w = f brg = 32.768 khz) 11102 10 1/fw 31.3 ms (operating at f w = f brg = 32.768 khz) 11112 11 1/fw 62.5 ms (operating at f w = f brg = 32.768 khz) remark f w : watch timer clock frequency
chapter 11 watch timer functions preliminary user ? s manual u16541ej1v0um 330 figure 11-3. operation timing of watch timer/interval timer start overflow overflow 0h interrupt time of watch timer (0.5 s) interrupt time of watch timer (0.5 s) interval time (t) interval time (t) nt nt 5-bit counter count clock f w or f w /2 9 watch timer interrupt intwt interval timer interrupt intwti remark f w : watch timer clock frequency values in parentheses apply when count clock f w = 32.768 khz. n: number of interval timer operations 11.4.3 cautions some time is required before the first watch timer interrupt request signal (intwt) is generated after operation is enabled (wtm1 and wtm0 bits of wtm register = 1). figure 11-4. example of generation of watch timer interrupt request signal (intwt) (when interrupt period = 0.5 s) it takes 0.515625 seconds for the first intwt signal to be generated (2 9 1/32768 = 0.015625 s longer). the intwt signal is then generated every 0.5 seconds. 0.5 s 0.5 s 0.515625 s wtm0, wtm1 intwt
chapter 11 watch timer functions preliminary user ? s manual u16541ej1v0um 331 11.5 prescaler 3 the prescaler 3 has the following function. ? generation of watch timer count clock (source clock: main oscillation clock) 11.5.1 control register (1) prescaler mode register 0 (prsm0) the prsm0 register controls the generation of the watch timer count clock. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 prsm0 0 0 bgce0 0 0 bgcs01 bgcs00 disabled (fixed to 0) enabled bgce0 0 1 prescaler output f x f x /2 f x /4 f x /8 5 mhz 50 ns 100 ns 200 ns 400 ns 4 mhz 250 ns 500 ns 1 s 2 s bgcs01 0 0 1 1 bgcs00 0 1 0 1 selection of prescaler 3 clock (f bgcs ) after reset: 00h r/w address: fffff8b0h < > cautions 1. do not change the values of the bgcs00 and bgcs01 bits during watch timer operation. 2. set the prsm0 register before setting the bgce0 bit to 1. 3. set the prsm0 and prscm0 registers according to the main clock frequency that is used so as to obtain an f brg frequency of 32.768 khz.
chapter 11 watch timer functions preliminary user ? s manual u16541ej1v0um 332 (2) prescaler compare register 0 (prscm0) the prscm0 register is an 8-bit compare register. this register can be read or written in 8-bit units. reset input clears this register to 00h. prscm07 prscm0 prscm06 prscm05 prscm04 prscm03 prscm02 prscm01 prscm00 after reset: 00h r/w address: fffff8b1h cautions 1. do not rewrite the prscm0 register during watch timer operation. 2. set the prscm0 register before setting the bgce0 bit of the prsm0 register to 1. 3. set the prsm0 and prscm0 registers according to the main clock frequency that is used so as to obtain an f brg frequency of 32.768 khz. 11.5.2 generation of watch timer count clock the clock (f brg ) input to the watch timer can be corrected to approximate 32.768 khz. the relationship between the main clock (f x ), prescaler 3 clock selection bit bgcsn setting value (m), prscm0 register setting value (n) and output clock (f brg ) is as follows. f brg = example: when f x = 4.00 mhz, m = 0 (bgcs01 bit = bgcs00 bit = 0), and n = 3dh f brg = 32.787 khz remark f brg : watch timer count clock n: prscm0 register setting value (1 to ffh) in the case of prscm0 register setting value 00h, n = 256 m: bgcs01, bgcs00 bit setting value (0 to 3) n = 00, 01 f x 2 m n 2
preliminary user?s manual u16541ej1v0um 333 chapter 12 functions of watchdog timer 2 12.1 functions watchdog timer 2 has the following functions. ? default start watchdog timer note 1 reset mode: reset operation upon overflow of watchdog timer 2 (generation of wdt2res signal) non-maskable interrupt request mode: nmi operation upon overflow of watchdog timer 2 (generation of intwdt2 signal) note 2 ? input selectable from main clock, ring-osc, and subclock as the source clock notes 1. watchdog timer 2 automatically starts in the reset mode following reset release. when watchdog timer 2 is not used, either stop its operation before reset is executed through this function, or clear watchdog timer 2 once and stop it within the next interval time. also, perform write to the wdtm2 register for verification purposes only once, even if the default settings (reset mode, interval time: f r /2 19 ) need not be changed. 2. restoring using the reti instruction following non-maskable interrupt servicing due to a non- maskable interrupt request signal (intwdt2) is not possible. therefore, following completion of interrupt servicing, perform a system reset. figure 12-1. block diagram of watchdog timer 2 f xx /2 9 clock input controller output controller wdt2res (internal reset signal) wdcs22 internal bus intwdt2 wdcs21 wdcs20 f xt wdcs23 wdcs24 0 wdm21 wdm20 selector 16-bit counter f xx /2 18 to f xx /2 25 , f xt /2 9 to f xt /2 16 , f r /2 12 to f r /2 19 watchdog timer enable register (wdte) watchdog timer mode register 2 (wdtm2) 3 3 2 clear f r remark f xx : internal system clock frequency f xt : subclock frequency f r : ring-osc clock frequency intwdt2: non-maskable interrupt request signal from watchdog timer 2 wdtres2: watchdog timer 2 reset signal
chapter 12 functions of watchdog timer 2 preliminary user ? s manual u16541ej1v0um 334 12.2 configuration watchdog timer 2 consists of the following hardware. table 12-1. configuration of watchdog timer 2 item configuration control registers oscillation stabilization time select register (osts) watchdog timer mode register 2 (wdtm2) watchdog timer enable register (wdte) 12.3 control registers (1) oscillation stabilization time select register (osts) the osts register selects the oscillation stabilization time following reset or release of the stop mode. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 06h. 0 osts 0 0 0 0 osts2 osts1 osts0 osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time/setup time note osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 setting prohibited after reset: 06h r/w address: fffff6c0h 2 10 /f x 2 11 /f x 2 12 /f x 2 13 /f x 2 14 /f x 2 15 /f x 2 16 /f x 4 mhz 0.256 ms 0.512 ms 1.024 ms 2.048 ms 4.096 ms 8.192 ms 16.38 ms 5 mhz 0.205 ms 0.410 ms 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.107 ms f x note the oscillation stabilization time and setup time are required when the software stop mode and idle mode are released, respectively.
chapter 12 functions of watchdog timer 2 preliminary user ? s manual u16541ej1v0um 335 (2) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time and operation clock of watchdog timer 2. this register can be read or written in 8-bit units. this register can be read any number of times, but it is write- only once following reset release. reset input sets this register to 67h. 0 wdtm2 wdm21 wdm20 wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 after reset: 67h r/w address: fffff6d0h stops operation non-maskable interrupt request mode (generation of intwdt2 signal) reset mode (generation of wdt2res signal) wdm21 0 0 1 wdm20 0 1 ? selection of operation mode of watchdog timer 2 cautions 1. for details of bits wdcs20 to wdcs24, see table 12-2 watchdog timer 2 clock selection. 2. although watchdog timer 2 can be stopped just by stopping the ring-osc operation, set the wdtm2 register to 00h to secure the operation (to avoid selection of the main clock or subclock due to an erroneous write operation). 3. if the wdtm2 register is rewritten twice after reset, an overflow signal is forcibly generated. 4. to stop the operation of watchdog timer 2, set the rstp bit of the rcm register to 1 (to stop ring-osc) and write 00h to the wdtm2 register.
chapter 12 functions of watchdog timer 2 preliminary user ? s manual u16541ej1v0um 336 table 12-2. watchdog timer 2 clock selection wdcs24 wdcs23 wdcs22 wdcs21 wdcs20 selected clock 100 khz (min.) 200 khz (typ.) 400 khz (max.) 000002 12 /f r 41.0 ms 20.5 ms 10.2 ms 000012 13 /f r 81.9 ms 41.0 ms 20.5 ms 000102 14 /f r 163.8 ms 81.9 ms 41.0 ms 000112 15 /f r 327.7 ms 163.8 ms 81.9 ms 001002 16 /f r 655.4 ms 327.7 ms 163.8 ms 001012 17 /f r 1310.7 ms 655.4 ms 327.7 ms 001102 18 /f r 2621.4 ms 1310.7 ms 655.4 ms 001112 19 /f r 5242.9 ms 2621.47 ms 1310.7 ms f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz 010002 18 /f xx 13.1 ms 16.4 ms 26.2 ms 010012 19 /f xx 26.2 ms 32.8 ms 52.4 ms 010102 20 /f xx 52.4 ms 65.5 ms 104.9 ms 010112 21 /f xx 104.9 ms 131.1 ms 209.7 ms 011002 22 /f xx 209.7 ms 262.1 ms 419.4 ms 011012 23 /f xx 419.4 ms 524.3 ms 838.9 ms 011102 24 /f xx 838.9 ms 1048.6 ms 1677.7 ms 011112 25 /f xx 1677.7 ms 2097.2 ms 3355.4 ms f xt = 32.768 khz 1 0002 9 /f xt 15.625 ms 1 0012 10 /f xt 31.25 ms 1 0102 11 /f xt 62.5 ms 1 0112 12 /f xt 125 ms 1 1002 13 /f xt 250 ms 1 1012 14 /f xt 500 ms 1 1102 15 /f xt 1000 ms 1 1112 16 /f xt 2000 ms
chapter 12 functions of watchdog timer 2 preliminary user ? s manual u16541ej1v0um 337 (3) watchdog timer enable register (wdte) the counter of the watchdog timer 2 is cleared and counting restarted by writing ? ach ? to the wdte register. the wdte register can be read or written in 8-bit units. reset input sets this register to 9ah. wdte after reset: 9ah r/w address: fffff6d1h cautions 1. when a value other than ?ach? is written to the wdte register, an overflow signal is forcibly output. 2. when a 1-bit memory manipulation instruction is executed for the wdte register, an overflow signal is forcibly output (an error results in the assembler). 3. the read value of the wdte register is ?9ah? (value that differs from written value ?ach?).
chapter 12 functions of watchdog timer 2 preliminary user ? s manual u16541ej1v0um 338 12.4 operation (1) oscillation stabilization time selection function the wait time until the oscillation stabilizes after the software stop mode is released is controlled by the osts register. the osts register can be read or written 8-bit units. reset input sets this register to 06h. 0 osts 0 0 0 0 osts2 osts1 osts0 osts2 0 0 0 0 1 1 1 1 selection of oscillation stabilization time/setup time note osts1 0 0 1 1 0 0 1 1 osts0 0 1 0 1 0 1 0 1 after reset: 06h r/w address: fffff6c0h 2 10 /f x 2 11 /f x 2 12 /f x 2 13 /f x 2 14 /f x 2 15 /f x 2 16 /f x 4 mhz 0.256 ms 0.512 ms 1.024 ms 2.048 ms 4.096 ms 8.192 ms 16.38 ms 5 mhz 0.205 ms 0.410 ms 0.819 ms 1.638 ms 3.277 ms 6.554 ms 13.107 ms f x setting prohibited note the oscillation stabilization time and setup time are required when the software stop mode and idle mode are released, respectively. cautions 1. the wait time following release of the software stop mode does not include the time until the clock oscillation starts ( ? a ? in the figure below) following release of the software stop mode, regardless of whether the software stop mode is released through reset input or the occurrence of an interrupt request signal. a stop mode release voltage waveform of x1 pin v ss 2. be sure to clear bits 3 to 7 to 0. 3. the oscillation stabilization time following reset release is 2 16 /f x (because the initial value of the osts register = 06h). remark f x = oscillation frequency
chapter 12 functions of watchdog timer 2 preliminary user ? s manual u16541ej1v0um 339 (2) operation as watchdog timer 2 watchdog timer 2 automatically starts in the reset mode following reset release. the wdtm2 register can be written to only once following reset using byte access. to use watchdog timer 2, write the operation mode and the interval time to the wdtm2 register using an 8-bit memory manipulation instruction. after this, the operation of watchdog timer 2 cannot be stopped. the wdcs24 to wdcs20 bits of the wdtm2 register are used to select the watchdog timer 2 loop detection time interval. writing ach to the wdte register clears the counter of watchdog timer 2 and starts the counting operation again. after the counting operation has started, write ach to wdte within the time interval of detecting a loop. if the time interval expires without ach being written to the wdte register, a reset signal (wdt2res) or a non-maskable interrupt request signal (intwdt2) is generated, depending on the set values of the wdm21 and wdm20 bits of the wdtm2 register. to not use watchdog timer 2, write 1fh to the wdtm2 register. if the non-maskable interrupt request mode has been set, restoring using the reti instruction following non- maskable interrupt servicing is not possible. therefore, following completion of interrupt servicing, perform a system reset.
preliminary user?s manual u16541ej1v0um 340 chapter 13 a/d converter 13.1 functions the a/d converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 12 channels of analog input signals (ani0 to ani11). the a/d converter has the following features. { 10-bit resolution { 12 channels { successive approximation method { operating voltage: av ref0 = 3.0 to 3.6 v { analog input voltage: 0 v to av ref0 { the following functions are provided as operation modes. ? continuous select mode ? continuous scan mode ? one-shot select mode ? one-shot scan mode { the following functions are provided as trigger modes. ? software trigger mode ? external trigger mode (external, 1) ? timer trigger mode { power-fail monitor function (conversion result compare function)
chapter 13 a/d converter preliminary user?s manual u16541ej1v0um 341 the block diagram of the a/d converter is shown below. figure 13-1. block diagram of a/d converter ani0 : : ani1 ani2 ani9 ani10 ani11 ada0m2 ada0m1 ada0m0 ada0s ada0pft controller voltage comparator ada0pfm voltage comparator ada0cr0 ada0cr1 : : ada0cr2 ada0cr10 ada0cr11 internal bus av ref0 ada0ce bit av ss intad edge detection adtrg controller sample & hold circuit tap selector ada0ets0 bit inttp2cc0 inttp2cc1 ada0ets1 bit ada0ce bit ada0tmd1 bit ada0tmd0 bit selector selector ada0pfe bit ada0pfc bit sar
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 342 13.2 configuration the a/d converter includes the following hardware. table 13-1. configuration of a/d converter item configuration analog inputs 12 channels (ani0 to ani11 pins) registers successive approximation register (sar) a/d conversion result registers 0 to 11 (ada0cr0 to ada0cr11) a/d conversion result registers 0h to 11h (adcr0h to adcr11h): only higher 8 bits can be read control registers a/d converter mode registers 0, 1 (ada0m0, ada0m1) a/d converter channel specification register 0 (ada0s) (1) successive approximation register (sar) the sar register compares the voltage value of the analog input signal with the voltage tap (compare voltage) value from the series resistor string, and holds the comparison result starting from the most significant bit (msb). when the comparison result has been held down to the least significant bit (lsb) (i.e. when a/d conversion has been completed), the contents of the sar register are transferred to the ada0crn register. remark n = 0 to 11 (2) a/d conversion result register n (ada0crn), a/d conversion result register nh (ada0crnh) the ada0crn register is a 16-bit register that stores the a/d conversion result. ada0arn consist of 12 registers and the a/d conversion result is stored in the 10 higher bits of the ad0crn register corresponding to analog input. (the lower 6 bits are fixed to 0.) the ada0crn register is read-only, in 16-bit units. moreover, when using only the higher 8 bits of the a/d conversion result, the ada0crnh register is read-only, in 8-bit units. caution a write operation to the ada0m0 and ada0s registers may cause the contents of the ada0crn register to become undefined. after the conversion, read the conversion result before performing write to the ada0m0 and ada0s registers. correct conversion results may not be read if a sequence other than the above is used. remark n = 0 to 11 (3) power-fail compare threshold value register (ada0pft) the ada0pft register sets a threshold value that is compared with the value of a/d conversion result register nh (ada0crnh). the 8-bit data set to the ada0pft register is compared with the higher 8 bits (ada0crnh) of the a/d conversion result register. this register can be read or written in 8-bit units. reset input clears this register to 00h.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 343 (4) sample & hold circuit the sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the sampled data to the voltage comparator. this circuit also holds the sampled analog input signal voltage during a/d conversion. (5) voltage comparator the voltage comparator compares a voltage value that has been sampled and held with the voltage value of the series resistor string. (6) series resistor string this series resistor string is connected between av ref0 and av ss and generates a voltage for comparison with the analog input signal. (7) ani0 to ani11 pins these are analog input pins for the 12 channels of the a/d converter and are used to input analog signals to be converted into digital signals. pins other than ones selected as analog input with the ada0s register can be used as input ports. caution make sure that the voltages input to ani0 to ani11 pins do not exceed the rated values. in particular if a voltage higher than av ref0 is input to a channel, the conversion value of that channel becomes undefined, and the conversion values of the other channels may also be affected. (8) av ref0 pin this is the pin used to input the reference voltage of the a/d converter. the signals input to the ani0 to ani11 pins are converted to digital signals based on the voltage applied between the av ref0 and av ss pins. (9) av ss pin this is the ground pin of the a/d converter. always make the potential at this pin the same as that at the v ss pin even when the a/d converter is not used.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 344 13.3 control registers the a/d converter is controlled by the following registers. ? a/d converter mode registers 0, 1, 2 (ada0m0, ada0m1, ada0m2) ? a/d converter channel specification register 0 (ada0s) ? power-fail compare mode register (ada0pfm) the following registers are also used. ? a/d conversion result register n (ada0crn) ? a/d conversion result register nh (ada0crnh) ? power-fail compare threshold value register (ada0pft)
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 345 (1) a/d converter mode register 0 (ada0m0) the ada0m0 register is an 8-bit register that specifies the operation mode and controls conversion operation. this register can be read or written in 8-bit or 1-bit units. however, bit 0 is read-only. reset input clears this register to 00h. ada0ce ada0ce 0 1 stops conversion enables conversion a/d conversion control ada0m0 0 ada0md1 ada0md0 ada0ets1 ada0ets0 ada0tmd ada0ef ada0tmd 0 1 software trigger mode external trigger mode/timer trigger mode trigger mode specification ada0ef 0 1 a/d conversion stopped a/d conversion in progress a/d converter status display ada0md1 0 0 1 1 ada0md0 0 1 0 1 continuous select mode continuous scan mode one-shot select mode one-shot scan mode specification of a/d converter operation mode ada0ets1 0 0 1 1 ada0ets0 0 1 0 1 no edge detection falling edge detection rising edge detection detection of both rising and falling edges specification of external trigger (adtrg pin) input valid edge after reset: 00h r/w address: fffff200h < > < > cautions 1. if bit 0 is written to, this is ignored. 2. changing the ada0fr2 to ada0fr0 bits of the ada0m1 register during conversion (ada0ce0 bit = 1) is prohibited. 3. when not using the a/d converter, stop the operation by setting ada0ce bit = 0 to reduce the consumption current.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 346 (2) a/d converter mode register 1 (ada0m1) the ada0m1 register is an 8-bit register that specifies the conversion time. this register can be read or written in 8-bit or 1-bit units. reset input clears this bit to 00h. ada0hs1 ada0m1 0 00 0 ada0fr2 ada0fr1 ada0fr0 after reset: 00h r/w address: fffff201h ada0hs1 0 1 normal conversion mode high-speed conversion mode specification of normal conversion mode/high-speed mode (a/d conversion time) caution be sure to clear bits 6 to 3 to 0. remark for a/d conversion time setting examples, see tables 13-2 and 13-3 . table 13-2. normal conversion mode setting examples ada0fr2 ada0fr1 ada0fr0 a/d conversion time note f xx = 20 mhz f xx = 16 mhz f xx = 4 mhz 0 0 0 65/f xx setting prohibited setting prohibited 16.25 s 0 0 1 130/f xx 6.50 s 8.13 s setting prohibited 0 1 0 195/f xx 9.75 s 12.19 s setting prohibited 0 1 1 258/f xx 12.90 s 16.13 s setting prohibited 1 0 0 310/f xx 15.50 s 19.38 s setting prohibited 1 0 1 362/f xx 18.10 s 22.63 s setting prohibited 1 1 0 414/f xx 20.70 s setting prohibited setting prohibited 1 1 1 466/f xx 23.30 s setting prohibited setting prohibited note set the a/d conversion time so that 5.16 s conversion time 26.0 s. table 13-3. high-speed conversion mode setting examples ada0fr2 ada0fr1 ada0fr0 a/d conversion time note 1 f xx = 20 mhz f xx = 16 mhz f xx = 4 mhz a/d stabilization time note 2 0 0 0 26/f xx setting prohibited setting prohibited 6.5 s 13/f xx 0 0 1 52/f xx 2.60 s 3.25 s setting prohibited 26/f xx 0 1 0 78/f xx 3.90 s 4.88 s setting prohibited 39/f xx 0 1 1 104/f xx 5.20 s 6.50 s setting prohibited 50/f xx 1 0 0 130/f xx 6.50 s 8.13 s setting prohibited 50/f xx 1 0 1 156/f xx 7.80 s 9.75 s setting prohibited 50/f xx 1 1 0 182/f xx 9.10 s setting prohibited setting prohibited 50/f xx 1 1 1 208/f xx 10.40 s setting prohibited setting prohibited 50/f xx notes 1. set the conversion time so that 2.08 s conversion time 10.40 s. 2. when the ada0ce bit of the ada0m0 register is changed from 0 to 1 to secure the a/d converter stabilization time (1 s), prior to the first conversion only, a/d conversion starts after one of the above clock values is input.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 347 (3) a/d converter mode register (ada0m2) the ada0m2 register specifies the hardware trigger mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 ada0m2 0 0 0 00 ada0tmd1 ada0tmd0 ada0tmd1 0 0 1 1 ada0tmd0 0 1 0 1 specification of hardware trigger mode external trigger mode (when adtrg pin valid edge detected) timer trigger mode 0 (when inttp2cc0 interrupt request generated) timer trigger mode 1 (when inttp2cc1 interrupt request generated) setting prohibited after reset: 00h r/w address: fffff203h 6543210 7 caution be sure to clear bits 7 to 2 to 0.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 348 (4) analog input channel specification register 0 (ada0s) the ada0s register is a register that specifies the port for inputting the analog voltage to be converted into a digital signal. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 ada0s 0 0 0 ada0s3 ada0s2 ada0s1 ada0s0 after reset: 00h r/w address: fffff202h ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 ani8 ani9 ani10 ani11 setting prohibited setting prohibited setting prohibited setting prohibited ani0 ani0, ani1 ani0 to ani2 ani0 to ani3 ani0 to ani4 ani0 to ani5 ani0 to ani6 ani0 to ani7 ani0 to ani8 ani0 to ani9 ani0 to ani10 ani0 to ani11 setting prohibited setting prohibited setting prohibited setting prohibited ada0s3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ada0s2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ada0s1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ada0s0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 select mode scan mode caution be sure to clear bits 7 to 4 to 0.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 349 (5) a/d conversion result registers n, nh (ada0crn, ada0crnh) the ada0crn and ada0crnh registers store a/d conversion results. these registers are read-only, in 16-bit or 8-bit units. however, specify the ada0crn register for 16-bit access and the ada0crnh register for 8-bit access. the 10 bits of the conversion result can be read from the higher 10 bits of the ada0crn register, and 0 can be read from the lower 6 bits. the higher 8 bits of the conversion result can be read from the ada0crn register. after reset: undefined r address: ada0cr0 fffff210h, ada0cr1 fffff212h, ada0cr2 fffff214h, ada0cr3 fffff216h, ada0cr4 fffff218h, ada0cr5 fffff21ah, ada0cr6 fffff21ch, ada0cr7 fffff21eh, ada0cr8 fffff220h, ada0cr9 fffff222h, ada0cr10 fffff224h, ada0cr11 fffff226h ada0crn (n = 0 to 11) ad9 ad8 ad7 ad6 ad0000000 ad1 ad2 ad3 ad4 ad5 ad9 ada0crnh (n = 0 to 11) ad8 ad7 ad6 ad5 ad4 ad3 ad2 76 54 32 1 0 after reset: undefined r address: ada0cr0h fffff211h, ada0cr1h fffff213h, ada0cr2h fffff215h, ada0cr3h fffff217h, ada0cr4h fffff219h, ada0cr5h fffff21bh, ada0cr6h fffff21dh, ada0cr7h fffff21fh, ada0cr8h fffff221h, ada0cr9h fffff223h, ada0cr10h fffff225h, ada0cr11h fffff227h
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 350 the relationship between the analog voltage input to the analog input pins (ani0 to ani11) and the a/d conversion result (of a/d conversion result register n (ada0crn)) is as follows: 0.5) 1,024 av v ( int ada0cr ref0 in + = or, 1,024 av 0.5) (ada0cr v 1,024 av 0.5) (ada0cr ref0 in ref0 + < ? int( ): function that returns the integer of the value in ( ) v in : analog input voltage av ref0 : av ref0 pin voltage ada0cr: value of a/d conversion result register n (ada0crn) figure 13-2 shows the relationship between the analog input voltage and the a/d conversion results. figure 13-2. relationship between analog input voltage and a/d conversion results 1,023 1,022 1,021 3 2 1 0 input voltage/av ref0 1 2,048 1 1,024 3 2,048 2 1,024 5 2,048 3 1,024 2,043 2,048 1,022 1,024 2,045 2,048 1,023 1,024 2,047 2,048 1 a/d conversion results (ada0crn) remark n = 0 to 11
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 351 (6) power-fail compare mode register (ada0pfm) the ada0pfm register is an 8-bit register that sets the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. ada0pfe power-fail compare enabled power-fail compare disabled ada0pfe 0 1 selection of power-fail compare enable/disable ada0pfm ada0pfc 00 00 0 0 generates an interrupt request signal (intad) when ada0crnh ada0pft generates an interrupt request signal (intad) when ada0crnh < ada0pft ada0pfc 0 1 selection of power-fail compare mode after reset: 00h r/w address: fffff204h <7> <6> 5 4 3 2 1 0 cautions 1. in the select mode, the 8-bit data set to the ada0pft register is compared with the value of the ada0crnh register specified by the ada0s register. if the result matches the condition specified by the ada0pfc bit, the conversion result is stored in the ada0crn register and the intad signal is generated. if it does not match, however, the interrupt signal is not generated. 2. in the scan mode, the 8-bit data set to the ada0pft register is compared with the contents of the ada0cr0h register. if the result matches the condition specified by the ada0pfc bit, the conversion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, however, the intad signal is not generated. regardless of the comparison result, the scan operation is continued and the conversion result is stored in the ada0crn register until the scan operation is completed. however, the intad signal is not generated after the scan operation has been completed. (7) power-fail compare threshold value register (ada0pft) the ada0pft register sets the compare value in the power-fail compare mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. ada0pft after reset: 00h r/w address: fffff205h <7> <6> <5> <4> <3> <2> <1> <0>
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 352 13.4 operation 13.4.1 basic operation <1> set the operation mode, trigger mode, and conversion time for executing a/d conversion by using the ada0m0, ada0m1, ada0m2, and ada0s registers. when the ada0ce bit of the ada0m0 register is set, conversion is started in the software trigger mode and the a/d converter waits for a trigger in the external timer trigger mode. <2> when a/d conversion is started, the voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3> when the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and holds the input analog voltage until the a/d conversion is completed. <4> set bit 9 of the successive approximation register (sar). the tap selector selects (1/2) av ref0 as the voltage tap of the series resistor string. <5> the voltage difference between the voltage of the series resistor string and the analog input voltage is compared by the voltage comparator. if the analog input voltage is higher than (1/2) av ref0 , the msb of the sar register remains set. if it is lower than (1/2) av ref0 , the msb is reset. <6> next, bit 8 of the sar register is automatically set and the next comparison is started. depending on the value of bit 9 to which a result has been already set, the voltage tap of the series resistor string is selected as follows. ? bit 9 = 1: (3/4) av ref0 ? bit 9 = 0: (1/4) av ref0 this voltage tap and the analog input voltage are compared and, depending on the result, bit 8 is manipulated as follows. analog input voltage voltage tap: bit 8 = 1 analog input voltage voltage tap: bit 8 = 0 <7> this comparison is continued to bit 0 of the sar register. <8> when comparison of the 10 bits has been completed, the valid digital result is stored in the sar register, which is then transferred to and stored in the ada0crn register. at the same time, an a/d conversion end interrupt request signal (intad) is generated.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 353 figure 13-3. a/d converter basic operation sar ada0crn intad conversion time sampling time sampling a/d converter operation a/d conversion undefined conversion result conversion result
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 354 13.4.2 trigger mode the timing of starting the conversion operation is specified by setting a trigger mode. the trigger mode includes a software trigger mode and hardware trigger modes. the hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode. the ada0tmd bit of the ada0m0 register is used to set the trigger mode. the hardware trigger modes are set by the ada0tmd1 and ada0tmd0 bits of the ada0m2 register. (1) software trigger mode when the ada0ce bit of the ada0m0 register is set to 1, the signal of the analog input pin (ani0 to ani11 pin) specified by the ada0s register is converted. when conversion is complete, the result is stored in the ada0crn register. at the same time, the a/d conversion end interrupt request signal (intad) is generated. if the operation mode specified by the ada0md1 and ada0md0 bits of the ada0m0 register is the continuous select/scan mode, the next conversion is started, unless the ada0ce bit is cleared to 0 after completion of the first conversion. conversion is performed once and completed if the operation mode is the one-shot select/scan mode. when conversion is started, the ada0ef bit is set to 1 (indicating that the operation is in progress). if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft register is written during conversion, the conversion is aborted and started again from the beginning. (2) external trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani11 pin) specified by the ada0s register is started when an external trigger is input (to the adtrg pin). how the edge of the external trigger is to be detected (i.e., whether the rising edge, falling edge, or both rising and falling edges are to be detected) can be specified by using the ada0ets1 and ata0ets0 bits of the ada0m0 register. when the ada0ce bit of the ada0m0 register set to 1, the a/d converter waits for the trigger, and starts conversion after the external trigger has been input. when conversion is completed, the result of conversion is stored in the ada0crn register. at the same time, the a/d conversion end interrupt request signal (intad) is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that the operation is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that the operation is stopped). if the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft register is written during the conversion operation, the conversion is not aborted, and the a/d converter waits for the trigger again.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 355 (3) timer trigger mode in this mode, converting the signal of the analog input pin (ani0 to ani11 pin) specified by the ada0s register is started by the compare match interrupt request signal (inttp2cc0 or inttp2cc1) of the capture/compare register connected to the timer. either of the compare match interrupt request signals (inttp2cc0 and inttp2cc1) of the timer is selected by the ada0tmd1 and ada0tmd0 bits of the ada0m2 register, and conversion is started at the rising edge of the specified compare match interrupt request signal. when the ada0ce bit of the ada0m0 register is set to 1, the a/d converter waits for a trigger, and starts conversion when the compare match interrupt signal of the timer is input. when conversion is completed, the result of the conversion is stored in the ada0crn register. at the same time, the a/d conversion end interrupt request signal (intad) is generated, and the a/d converter waits for the trigger again. when conversion is started, the ada0ef bit is set to 1 (indicating that the operation is in progress). while the a/d converter is waiting for the trigger, however, the ada0ef bit is cleared to 0 (indicating that the operation is stopped). if the valid trigger is input during the conversion operation, the conversion is aborted and started again from the beginning. if the ada0m0, ada0m2, ada0s, ada0pfm, or ada0pft register is written during conversion, the conversion is stopped and the a/d converter waits for the trigger again.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 356 13.4.3 operation mode four operation modes are available as modes to set the ani0 to ani11 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. the operation mode is selected by the ada0md1 and ada0md0 bits of the ada0m0 register. (1) continuous select mode in this mode, the voltage of one analog input pin selected by the ada0s register is continuously converted into a digital value. the conversion result is stored in the ada0crn register corresponding to the analog input pin. in this mode, an analog input pin corresponds to an ada0crn register on a one-to-one basis. each time a/d conversion has been completed, the a/d conversion end interrupt request signal (intad) is generated. after completion of conversion, the next conversion is started, unless the ada0ce bit of the ada0m0 register is cleared to ? 0 ? (n = 0 to 11). figure 13-4. timing example of continuous select mode operation (ada0s = 01h) ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani6) data 5 ( ani1) data 6 (ani1) data 7 (ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 (ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 6 (ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 357 (2) continuous scan mode in this mode, the voltages on the analog input pins specified by the ada0s register are sequentially selected, starting from the ani0 pin, and converted into digital values. the result of conversion is stored in the ada0crn register corresponding to the analog input pin. when conversion of the signals on the analog input pins selected by the ada0s register is complete, the a/d conversion end interrupt request signal (intad) is generated, and a/d conversion is started again from the ani0 pin, unless the ada0ce bit of the ada0m0 register is cleared to 0 (n = 0 to 11).
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 358 figure 13-5. timing example of continuous scan mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) data 7 (ani2) data 1 (ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) data 5 (ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 359 (3) one-shot select mode in this mode, the voltage on one analog input pin specified by the ada0s register is converted into a digital value only once. the conversion result is stored in the ada0crn register corresponding to the analog input pin. in this mode, an analog input pin and an ada0crn register correspond on a one-to-one basis. when a/d conversion has been completed once, the a/d conversion end interrupt request signal (intad) is generated. the a/d conversion operation is stopped after it has been completed (n = 0 to 11). figure 13-6. timing example of one-shot select mode operation (ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 6 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 conversion end conversion end
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 360 (4) one-shot scan mode in this mode, the voltages on the analog input pins specified by the ada0s register are sequentially selected and converted into digital values, starting from the ani0 pin. the a/d conversion result is stored in the ada0crn register corresponding to the analog input pin. when the voltages on the analog input pins specified by the ada0s register have been converted, the a/d conversion end interrupt request signal (intad) is generated. the a/d conversion is stopped after it has been completed (n = 0 to 11).
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 361 figure 13-7. timing example of one-shot scan mode operation (ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 (ani2) data 4 ( ani3) data 1 ( ani0) data 2 (ani1) data 3 (ani2) data 4 (ani3) ada0cr1 intad conversion start set ada0ce bit = 1 conversion end ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 362 13.4.4 power-fail compare mode the a/d conversion end interrupt request signal (intad) can be controlled as follows by the ada0pfm and ada0pft registers. ? when the ada0pfe bit = 0, the intad signal is generated each time conversion has been completed (normal use of the a/d converter). ? when the ada0pfe bit = 1 and when the ada0pfc bit = 0, the value of the ada0crnh register is compared with the value of the ada0pft register when conversion is completed, and the intad signal is generated only if ada0cr0h ada0pft. ? when the ada0pfe bit = 1 and when the ada0pfc bit = 1, the value of the ada0crnh register is compared with the value of the ada0pft register when conversion is completed, and the intad signal is generated only if ada0cr0h < ada0pft. remark n = 0 to 11 in the power-fail compare mode, four modes are available as modes to set the ani0 to ani11 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. (1) continuous select mode in this mode, the voltage of one analog input pin selected by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail compare matches the condition set by the ada0pfc bit, the conversion result is stored in the ada0crn register, and the intad signal is generated. if it does not match, the conversion result is stored in the ada0crn register, and the intad signal is not generated. after completion of the first conversion, the next conversion is started, unless the ada0ce bit of the ada0m0 register is cleared to 0 (n = 0 to 11). figure 13-8. timing example of continuous select mode operation (when power-fail compare is made: ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 2 (ani1) data 3 (ani1) data 4 (ani1) data 5 ( ani1) data 6 ( ani1) data 7 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 2 ( ani1) data 3 ( ani1) data 4 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start set ada0ce bit = 1 ada0pft unmatch ada0pft unmatch ada0pft match ada0pft match ada0pft match conversion start set ada0ce bit = 1
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 363 (2) continuous scan mode in this mode, the voltages on the analog input pins specified by the ada0s register are sequentially selected, starting from the ani0 pin, and converted into digital values, and the set value of the ada0cr0h register of channel 0 is compared with the value of the ada0pft register. if the result of power-fail compare matches the condition set by the ada0pfc bit of the ada0pfm register, the conversion result is stored in the ada0cr0 register, and the intad signal is generated. if it does not match, the conversion result is stored in the ada0cr0 register, and the intad signal is not generated. after the result of the first conversion has been stored in the ada0cr0 register, the results of sequentially converting the voltages on the analog input pins specified by the ada0s register are continuously stored. after completion of conversion, the next conversion is started from the ani0 pin again, unless the ada0ce bit of the ada0m0 register is cleared to 0.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 364 figure 13-9. timing example of continuous scan mode operation (when power-fail compare is made: ada0s register = 03h) (b) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) data 7 ( ani2) data 1 ( ani0) data 2 (ani1) data 3 ( ani2) data 4 ( ani3) data 5 ( ani0) data 6 ( ani1) ada0crn intad conversion start set ada0ce bit = 1 ada0pft match ada0pft unmatch ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 365 (3) one-shot select mode in this mode, the result of converting the voltage of one analog input pin specified by the ada0s register is compared with the set value of the ada0pft register. if the result of power-fail compare matches the condition set by the ada0pfc bit of the ada0pfm register, the conversion result is stored in the ada0crn register, and the intad signal is generated. if it does not match, the conversion result is stored in the ada0crn register, and the intad signal is not generated. conversion is stopped after it has been completed. figure 13-10. timing example of one-shot select mode operation (when power-fail compare is made: ada0s register = 01h) ani1 a/d conversion data 1 ( ani1) data 6 ( ani1) data 1 data 2 data 3 data 4 data 5 data 6 data 7 data 1 ( ani1) data 6 ( ani1) ada0cr1 intad conversion start set ada0ce bit = 1 conversion start set ada0ce bit = 1 ada0pft match conversion end ada0pft unmatch conversion end
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 366 (4) one-shot scan mode the voltages on the analog input pins selected by the ada0s register are sequentially converted and the results of conversion are sequentially stored, starting from the ani0 pin, and the set value of the ada0cr0h register of channel 0 is compared with the set value of the ada0pft register. if the result of power-fail compare matches the condition set by the ada0pfc bit of the ada0pfm register, the conversion result is stored in the ada0cr0 register and the intad signal is generated. if it does not match, the conversion result is stored in the ada0cr0 register, and the intad0 signal is not generated. after the result of the first conversion has been stored in the ada0cr0 register, the results of converting the signals on the analog input pins specified by the ada0s register are sequentially stored. the conversion is stopped after it has been completed (n = 0 to 11).
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 367 figure 13-11. timing example of one-shot scan mode operation (when power-fail compare is made: ada0s register = 03h) (a) timing example a/d conversion data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) data 1 ( ani0) data 2 ( ani1) data 3 ( ani2) data 4 ( ani3) ada0crn intad conversion start set ada0ce bit = 1 conversion end ada0pft match ani3 ani0 ani1 ani2 data 1 data 2 data 3 data 4 data 6 data 5 data 7 (b) block diagram a/d converter ada0crn register analog input pin ani0 ani1 ani2 ani3 ani4 ani5 ani9 ani10 ani11 . . . . ada0cr0 ada0cr1 ada0cr2 ada0cr3 ada0cr4 ada0cr5 ada0cr9 ada0cr10 ada0cr11 . . .
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 368 13.5 cautions (1) when a/d converter is not used when the a/d converter is not used, the power consumption can be reduced by clearing the ada0ce bit of the ada0m0 register to 0. (2) input range of ani0 to ani11 pins input the voltage within the specified range to the ani0 to ani11 pins. if a voltage equal to or higher than av ref0 or equal to or lower than av ss (even within the range of the absolute maximum ratings) is input to any of these pins, the conversion value of that channel is undefined, and the conversion value of the other channels may also be affected. (3) countermeasures against noise to maintain the 10-bit resolution, the ani0 to ani11 pins must be effectively protected from noise. the influence of noise increases as the output impedance of the analog input source becomes higher. to lower the noise, connecting an external capacitor as shown in figure 13-12 is recommended. figure 13-12. processing of analog input pin av ref0 v dd gnd0 av ss clamp with a diode with a low v f (0.3 v or less) if noise equal to or higher than av ref0 or equal to or lower than av ss may be generated. c = 100 to 1,000 pf (4) alternate i/o the analog input pins (ani0 to ani11) function alternately as port pins. when selecting one of the ani0 to ani11 pins to execute a/d conversion, do not execute an instruction to read an input port or write to an output port during conversion as the conversion resolution may drop. if a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the a/d conversion value may not be as expected due to the influence of coupling noise. therefore, do not apply a pulse to the pin adjacent to the pin under a/d conversion.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 369 (5) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the contents of the ada0s register are changed. if the analog input pin is changed during a/d conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ada0s register is rewritten. if the adif flag is read immediately after the ada0s register is rewritten, the adif flag may be set even though the a/d conversion of the newly selected analog input pin has not been completed. when a/d conversion has been stopped, clear the adif flag before resuming conversion. figure 13-13. generation timing of a/d conversion end interrupt request ada0s rewriting (anin conversion start) ada0s rewriting (anim conversion start) adif is set, but anim conversion does not end a/d conversion ada0crn intad anin anin anim anim anim anin anin anim remark n = 0 to 11 m = 0 to 11
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 370 (6) av ref0 pin (a) the av ref0 pin is also used as the power supply pin of the a/d converter and supplies power to the port with which it is multiplexed. in an application where a backup power supply is used, be sure to supply the same voltage as v dd to the av ref0 pin as shown in figure 13-14. (b) the av ref0 pin is also used as the reference voltage pin of the a/d converter. if the source supplying power to the av ref0 pin has a high impedance or if the power supply has a low current supply capability, the reference voltage may fluctuate due to the current that flows during conversion (especially, immediately after the conversion operation enable bit ada0ce has been set to 1). as a result, the conversion accuracy may drop. to avoid this, it is recommended to connect a capacitor across the av ref0 and av ss pins to suppress the reference voltage fluctuation. (c) if the source supplying power to the av ref0 pin has a high dc resistance (for example, because of insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when conversion is stopped, because of a voltage drop caused by the a/d conversion current. figure 13-14. av ref0 pin processing example av ref0 22 f or more av ss main power supply (7) reading ada0crn register when the ada0m0 to ada0m2 or ada0s register is written, the contents of the ada0crn register may be undefined. read the conversion result after completion of conversion and before writing the ada0m0 to ada0m2 and ada0s registers. the correct conversion result may not be read at a timing different from the above.
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 371 13.6 how to read a/d converter characteristics table this section describes the terms related to the a/d converter. (1) resolution the minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 lsb (least significant bit). the ratio of 1 lsb to the full scale is expressed as %fsr (full-scale range). %fsr is the ratio of a range of convertible analog input voltages expressed as a percentage, and can be expressed as follows, independently of the resolution. 1%fsr = (maximum value of convertible analog input voltage ? minimum value of convertible analog input voltage)/100 = (av ref0 ? 0)/100 = av ref0 /100 where the resolution is 10 bits, 1 lsb is as follows: 1 lsb = 1/2 10 = 1/1,024 = 0.098%fsr the accuracy is determined by the overall error, independently of the resolution. (2) overall error this is the maximum value of the difference between an actually measured value and a theoretical value. it is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. the overall error in the characteristics table does not include the quantization error. figure 13-15. overall error ideal line overall error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 372 (3) quantization error this is an error of 1/2 lsb that inevitably occurs when an analog value is converted into a digital value. because the a/d converter converts analog input voltages in a range of 1/2 lsb into the same digital codes, a quantization error is unavoidable. this error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or differential linearity error in the characteristics table. figure 13-16. quantization error quantization error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output 1/2 lsb 1/2 lsb (4) zero-scale error this is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 0 ? 000 to 0 ? 001 (1/2 lsb). figure 13-17. zero-scale error av ref0 analog input (lsb) digital output (lower 3 bits) ideal line 111 ? 10123 100 011 010 001 000 zero-scale error
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 373 (5) full-scale error this is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1 ? 110 to 0 ? 111 (full scale ? 3/2 lsb). figure 13-18. full-scale error av ref0 analog input (lsb) digital output (lower 3 bits) 111 av ref0 ? 3 0 av ref0 ? 2av ref0 ? 1 100 011 010 000 full-scale error (6) differential linearity error ideally, the width to output a specific code is 1 lsb. this error indicates the difference between the actually measured value and its theoretical value when a specific code is output. figure 13-19. differential linearity error ideal width of 1 lsb differential linearity error 1 ...... 1 0 ...... 0 av ref0 analog input digital output
chapter 13 a/d converter preliminary user ? s manual u16541ej1v0um 374 (7) integral linearity error this error indicates the extent to which the conversion characteristics differ from the ideal linear relations. it indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0. figure 13-20. integral linearity error 1 ...... 1 0 ...... 0 0av ref0 analog input digital output ideal line integral linearity error (8) conversion time this is the time required to obtain a digital output after an analog input voltage has been assigned. the conversion time in the characteristics table includes the sampling time. (9) sampling time this is the time for which the analog switch is on to load an analog voltage to the sample & hold circuit. figure 13-21. sampling time sampling time conversion time
preliminary user?s manual u16541ej1v0um 375 chapter 14 d/a converter 14.1 functions the d/a converter has the following functions. { 8-bit resolution 2 channels (da0cs0, da0cs1) { r-2r radder method { conversion time: 20 s max. (av ref1 = 3.0 to 3.6 v) { analog output voltage: av ref1 m/256 (m = 0 to 255; value set to da0csn register) { operation modes: normal mode, real-time output mode remark n = 0, 1 14.2 configuration the d/a converter configuration is shown below. figure 14-1. block diagram of d/a converter da0cs0 r-2r radder resistor r-2r radder resistor da0cs1 ano0 ano1 da0ce0 da0ce1 da0cs0 write da0md0 inttp2cc0 da0cs1 write da0md1 inttp3cc0 av ref1 av ss
chapter 14 d/a converter preliminary user ? s manual u16541ej1v0um 376 the d/a converter consists of the following hardware. table 14-1. configuration of d/a converter item configuration control registers d/a converter mode register (da0m) d/a conversion value setting registers 0, 1 (da0cs0, da0cs1) 14.3 control registers the registers that control the d/a converter are as follows. ? d/a converter mode register (da0m) ? d/a conversion value setting registers 0, 1 (da0cs0, da0cs1) (1) d/a converter mode register (da0m) the da0m register controls the operation of the d/a converter. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 normal mode real-time output mode note da0mdn 0 1 selection of d/a converter operation mode (n = 0, 1) da0m 0 da0ce1 da0ce0 0 0 da0md1 da0md0 after reset: 00h r/w address: fffff282h disables operation enables operation da0cen 0 1 control of d/a converter operation enable/disable (n = 0, 1) < > < > note the output trigger in the real-time output mode (da0mdn bit = 1) is as follows. ? when n = 0: inttp2cc0 signal (see chapter 7 16-bit timer/event counter p ) ? when n = 1: inttp3cc0 signal (see chapter 7 16-bit timer/event counter p )
chapter 14 d/a converter preliminary user ? s manual u16541ej1v0um 377 (2) d/a conversion value setting registers 0, 1 (da0cs0, da0cs1) the da0cs0 and da0cs1 registers set the analog voltage value output to the ano0 and ano1 pins. these registers can be read or written in 8-bit units. reset input clears these registers to 00h. da0csn7 da0csn da0csn6 da0csn5 da0csn4 da0csn3 da0csn2 da0csn1 da0csn0 after reset: 00h r/w address: da0cs0 fffff280h, da0cs1 fffff281h caution in the real-time output mode (da0mdn bit = 1), set the da0csn register before the inttp2cc0/inttp3cc0 signals are generated. d/a conversion starts when the inttp2cc0/inttp3cc0 signals are generated. remark n = 0, 1
chapter 14 d/a converter preliminary user ? s manual u16541ej1v0um 378 14.4 operation 14.4.1 operation in normal mode d/a conversion is performed using a write operation to the da0csn register as the trigger. the setting method is described below. <1> set the da0mdn bit of the da0m register to 0 (normal mode). <2> set the analog voltage value to be output to the anon pin to the da0csn register. steps <1> and <2> above constitute the initial settings. <3> set the da0cen bit of the da0m register to 1 (d/a conversion enable). d/a conversion starts when this setting is performed. <4> to perform subsequent d/a conversions, write to the da0csn register. the previous d/a conversion result is held until the next d/a conversion is performed. remark n = 0, 1 14.4.2 operation in real-time output mode d/a conversion is performed using the interrupt request signals (inttp2cc0 and inttp3cc0) of 16-bit timer/event counters p2 and p3 (tmp2 and tmp3) as triggers. the setting method is described below. <1> set the da0mdn bit of the da0m register to 1 (real-time output mode). <2> set the analog voltage value to be output to the anon pin to the da0csn register. <3> set the da0cen bit of the da0m register to 1 (d/a conversion enable). steps <1> to <3> above constitute the initial settings. <4> operate tmp2 and tmp3. <5> d/a conversion starts when the inttp2cc0 and inttp3cc0 signals are generated. <6> the inttp2cc0 and inttp3cc0 signals are generated when subsequent d/a conversions are performed. before performing the next d/a conversion (generation of inttp2cc0 and inttp3cc0 signals), set the analog voltage value to be output to the anon pin to the da0csn register.
chapter 14 d/a converter preliminary user ? s manual u16541ej1v0um 379 14.4.3 cautions observe the following cautions when using the d/a converter of the v850es/sg2. (1) do not change the set value of the da0csn register while the trigger signal is being issued in the real-time output mode. (2) before changing the operation mode, be sure to clear the da0cen bit of the da0m register to 0. (3) when using the p10/ano0 and p11/ano1 pins as port pins, make sure that their input level does not change much. (4) make sure that av ref0 = ev dd = av ref1 = 3.0 to 3.6 v. if this range is exceeded, the operation is not guaranteed. (5) apply power to av ref1 at the same timing as av ref0 . (6) no current can be output from the anon pin (n = 0, 1) because the output impedance of the d/a converter is high. when connecting a resistor of 5 m ? or less, insert a jfet input operational amplifier between the resistor and the anon pin. (7) do not perform d/a conversion of two channels at the same time. otherwise, the conversion accuracy may drop. figure 14-2. external pin connection example av ref1 ev dd output 10 f 0.1 f 10 f 0.1 f av ref0 anon av ss ? + jfet input operational amplifier
preliminary user?s manual u16541ej1v0um 380 chapter 15 asynchronous serial interface a (uarta) 15.1 mode switching of uarta and other serial interfaces 15.1.1 csib4 and uarta0 mode switching in the v850es/sg2, csib4 and uarta0 are alternate functions of the same pin and therefore cannot be used simultaneously. csib4 and uarta0 switching must be set in advance using the pmc3 and pfc3 registers. caution the transmit/receive operation of csib4 and uarta0 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 15-1. csib4 and uarta0 mode switch settings pmc3 after reset: 0000h r/w address: fffff446h, fffff447h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, ffff467h 0 0 0 0 0 0 pfc39 pfc38 pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfce3l after reset: 00h r/w address: fffff706h 0 pfce36 pfce35 pfce34 pfce33 pfce32 0 0 port i/o mode ascka0 mode sckb4 mode port i/o mode uarta0 mode csib4 mode pmc32 0 1 1 pmc3n 0 1 1 operation mode operation mode pfce32 0 0 pfc32 0 1 pfc3n 0 1 remarks 1. n = 0, 1 2. = don ? t care
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 381 15.1.2 uarta2 and i 2 c00 mode switching in the v850es/sg2, uarta2 and i 2 c00 are alternate functions of the same pin and therefore cannot be used simultaneously. uarta2 and i 2 c00 switching must be set in advance using the pmc3 and pfc3 registers. caution the transmit/receive operation of uarta2 and i 2 c00 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 15-2. uarta2 and i 2 c00 mode switch settings pmc3 after reset: 0000h r/w address: fffff446h, fffff447h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, ffff467h 0 0 0 0 0 0 pfc39 pfc38 pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 port i/o mode uarta2 mode i 2 c00 mode pmc3n 0 1 1 operation mode pfc3n 0 1 remarks 1. n = 8, 9 2. = don ? t care
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 382 15.1.3 uarta1 and i 2 c02 mode switching in the v850es/sg2, uarta1 and i 2 c02 are alternate functions of the same pin and therefore cannot be used simultaneously. uarta1 and i 2 c02 switching must be set in advance using the pmc9, pfc9, and pmce9 registers. caution the transmit/receive operation of uarta1 and i 2 c02 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 15-3. uarta1 and i 2 c02 mode switch settings pmc9 after reset: 0000h r/w address: fffff452h, fffff453h pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc9 after reset: 0000h r/w address: fffff472h, ffff473h pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 8 9 10 11 12 13 14 15 pfce915 pfce914 0 0 0 0 0 0 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 8 9 10 11 12 13 14 15 pfce9 after reset: 0000h r/w address: fffff712h, fffff713 uarta1 mode i 2 c02 mode pmc9n 1 1 operation mode pfce9n 1 1 pfc9n 0 1 remark n = 0, 1
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 383 15.2 features { transfer speed: 300 bps to 312.5 kbps (using internal system clock of 20 mhz and dedicated baud rate generator) { full-duplex communication: internal uarta receive data register n (uanrx) internal uarta transmit data register n (uantx) { 2-pin configuration: txdan: transmit data output pin rxdan: receive data input pin { receive error output function ? parity error ? framing error ? overrun error { interrupt sources: 2 ? reception complete end interrupt (intuanr): this interrupt is generated upon transfer of receive data from the shift register to receive buffer register n when an interrupt is generated by oring three types of reception errors or after serial transfer completion, in the reception enabled status. ? transmission enable interrupt (intuant): this interrupt is generated upon transfer of transmit data from the transmit buffer register to the shift register in the transmission enabled status. { character length of transmit/receive data specified by the uanctl0 register { character length: 7, 8 bits { parity function: odd, even, 0, none { transmission stop bit: 1, 2 bits { on-chip dedicated baud rate generator { msb/lsb-first transfer selectable { transmit/receive data inversion possible { 13 to 20 bits selectable for the sbf (sync break field) in the lin (local interconnect network) communication format { recognition of 11 bits or more possible for sbf reception in lin communication format { sbf reception flag provided remark n = 0 to 2
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 384 15.3 configuration (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register used to specify the asynchronous serial interface operation. (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register used to select the input clock for the asynchronous serial interface. (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register used to control the baud rate for the asynchronous serial interface. (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit register used to control serial transfer for the asynchronous serial interface. (5) uartan status register (uanstr) the uanstrn register consists of flags indicating the error contents when a reception error occurs. each one of the reception error flags is set (to 1) upon occurrence of a reception error and is reset (to 0) by reading the uanstr register. (6) uartan receive shift register this is a shift register used to convert the serial data input to the rxdan pin into parallel data. upon reception of 1 byte of data and detection of the stop bit, the receive data is transferred to the uanrx register. this register cannot be manipulated directly. (7) uartan receive data register (uanrx) the uanrx register is an 8-bit register that holds receive data. when 7 characters are received, 0 is stored in the highest bit (when lsb first received). in the reception enabled status, receive data is transferred from the uartan receive shift register to the uanrx register in synchronization with the completion of shift-in processing of 1 frame. transfer to the uanrx register also causes reception complete interrupt request signal (intuanr) to be output. (8) uartan transmit shift register the transmit shift register is a shift register used to convert the parallel data transferred from the uantx register into serial data. when 1 byte of data is transferred from the uantx register, the shift register data is output from the txdan pin. this register cannot be manipulated directly. (9) uartan transmit data register (uantx) the uantx register is an 8-bit transmit data buffer. transmission starts when transmit data is written to the uantx register. when data can be written to the uantx register (when data of one frame is transferred from the uantx register to the uartn transmit shift register), the transmission enable interrupt request signal (inuant) is generated.
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 385 figure 15-4. block diagram of asynchronous serial interface n internal bus internal bus uanotp0 uanctl0 uanstr uanctl1 uanctl2 receive shift register uanrx filter selector uantx transmit shift register transmission controller reception controller selector baud rate generator baud rate generator intuanr intuant txdan rxdan f xx to f xx /2 10 ascka0 reception unit transmission unit clock selector remark n = 0 to 2
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 386 15.4 control registers (1) uartan control register 0 (uanctl0) the uanctl0 register is an 8-bit register that controls the uartan serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 10h. caution be sure to set the uanpwr bit = 1 and the uanrxe bit = 1 while the rxdan pin is high level (when uanrdl bit of uanop0 register = 0). if the uanpwr bit = 1 and the uanrxe bit = 1 are set while the rxdan pin is low level, reception will inadvertently start. (1/2) uanpwr disable operating clock operation (uartan reset asynchronously) enable operating clock operation uanpwr 0 1 uartan operation control uanctl0 (n = 0 to 2) uantxe uanrxe uandir uanps1 uanps0 uancl uansl <6> <5> <4> 3 2 1 after reset: 10h r/w address: ua0ctl0 fffffa00h, ua1ctl0 fffffa10h, ua2ctl0 fffffa20h operating clock control and uartan asynchronous reset are performed with the uanpwr bit. the txdan pin output is fixed to high level by setting the uanpwr bit to 0. stop transmission operation enable transmission operation uantxe 0 1 transmission operation enable the txdan pin output is fixed to high level by setting the uantxe bit to 0. since the uantxe bit is initialized by the operating clock, to initialize the transmission unit, set the uantxe bit from 0 to 1, and 2 clocks later, the transmission enabled status is entered. when the uanpwr bit = 0, the value written to the uantxe bit is ignored. stop reception operation enable reception operation uanrxe 0 1 reception operation enable the receive operation is stopped by setting the uanrxe bit to 0. therefore, even if the prescribed data is transferred, no reception completion interrupt is output and the uanrx register is not updated. since the uanrxe bit is synchronized using the operating clock, to initialize the reception unit, set the uanrxe bit from 0 to 1, and 2 clocks later, the reception enabled status is entered. when the uanpwr bit = 0, the value written to the uanrxe bit is ignored. <7> 0
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 387 (2/2) 7 bits 8 bits uancl 0 1 specification of data character length of 1 frame of transmit/receive data this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. 1 bit 2 bits uansl 0 1 specification of length of stop bit for transmit data this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. this register is rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. if ? reception with 0 parity ? is selected during reception, a parity check is not performed. therefore, since the uanpe bit of the uanstr register is not set, no error interrupt is output. when transmission and reception are performed in the lin format, set the uanps1 and uanps0 bits to 00. no parity output 0 parity output odd parity output even parity output reception with no parity reception with 0 parity odd parity check even parity check uanps1 0 0 1 1 parity selection during transmission parity selection during reception uanps0 0 1 0 1 msb-first transfer lsb-first transfer uandir 0 1 transfer direction selection this register can be rewritten only when the uanpwr bit = 0 or the uantxe bit = the uanrxe bit = 0. remark for details of parity, see 15.6.9 parity types and operations .
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 388 (2) uartan control register 1 (uanctl1) for details, see 15.7 (2) uartan control register 1 (uanctl1) . (3) uartan control register 2 (uanctl2) for details, see 15.7 (3) uartan control register 2 (uanctl2) . (4) uartan option control register 0 (uanopt0) the uanopt0 register is an 8-bit register that controls the serial transfer operation of the uartan register. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 14h. (1/2) uansrf when the uanpwr bit = the uanrxe bit of the uanctl0 register = 0 are set. also upon normal end of sbf reception. during sbf reception uansrf 0 1 sbf reception flag uanopt0 (n = 0 to 2) uansrt uanstt uansls2 uansls1 uansls0 uantdl uanrdl 654321 after reset: 14h r/w address: ua0opt0 fffffa03h, ua1opt0 fffffa13h, ua2opt0 fffffa23h sbf reception trigger uansrt 0 1 sbf reception trigger sbf (sync brake field) reception is judged during lin communication. the uansrf bit is held high when an sbf reception error occurs, and then sbf reception is started again. this is the sbf reception trigger bit during lin communication, and when read, ? 0 ? is always read. for sbf reception, set the uansrt bit (to 1) to enable sbf reception. set the uansrt bit after setting the uanpwr bit = the uanrxe bit of the uanctl0 register = 1. this is the sbf transmission trigger bit during lin communication, and when read, ? 0 ? is always read. set the uanstt bit after setting the uanpwr bit = the uanrxe bit of the uanctl0 register = 1. sbf transmission trigger uanstt 0 1 sbf transmission trigger <7> 0 ? ?
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 389 (2/2) uansls2 1 1 1 0 0 0 0 1 uansls1 0 0 1 1 0 0 1 1 uansls0 1 0 1 0 1 0 1 0 13-bit output (reset value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output sbf length selection the value of the txdan pin can be inverted using the uantdl bit. this register can be set when the uanpwr bit of the uanctl0 register = 0 or when the uantxe bit of the uanctl0 register = 0. this register can be set when the uanpwr bit of the uanctl0 register = 0 or when the uanrxe bit of the uanctl0 register = 0. normal output of transfer data inverted output of transfer data uantdl 0 1 transmit data level bit the value of the rxdan pin can be inverted using the uanrdl bit. this register can be set when the uanpwr bit of the uanctl0 register = 0 or the uanrxe bit of the uanctl0 register = 0. normal input of transfer data inverted input of transfer data uanrdl 0 1 receive data level bit
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 390 (5) uartan status register (uanstr) the uanstr register is an 8-bit register that displays the uartan transfer status and reception error contents. this register can be read or written in 8-bit or 1-bit units, but the uantsf bit is a read-only bit, while the uanpe, uanfe, and uanove bits can both be read and written. however, these bits can only be cleared by writing 0 and they cannot be set by writing 1. (if 1 is written to them, the hold status is entered.) the initialization conditions are shown below. register/bit initialization conditions uanstr register ? reset input ? uanpwr bit of uanctl0 register = 0 uantsf bit ? uantxe bit of uanctl0 register = 0 uanpe, uanfe, uanove bits ? 0 write ? uanrxe bit of uanctl0 register = 0
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 391 uantsf when the uanpwr bit of the uanctl0 register = 0 or the uantxe bit of the uanctl0 register = 0 has been set. when, following transfer completion, there was no next data transfer from uantx write to uantxb bit uantsf 0 1 transfer status flag uanstr (n = 0 to 2) 0 0 0 0 uanpe uanfe uanove 6 5 4 3 <2> <1> after reset: 00h r/w address: ua0str fffffa04h, ua1str fffffa14h, ua2str fffffa24h the uantsf bit is always 1 when performing continuous transmission. when initializing the transmission unit, check that the uantsf bit = 0 before performing initialization. the transmit data is not guaranteed when initialization is performed while the uantsf bit = 1. when the uanpwr bit of the uanctl0 register = 0 or the uanrxe bit of the uanctl0 register = 0 has been set. when 0 has been written when parity of data and parity bit do not match during reception. uanpe 0 1 parity error flag the operation of the uanpe bit is controlled by the settings of the uanps1 and uanps0 bits of the uanctl0 register. the uanpe bit can be read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the hold status is entered. when the uanpwr bit of the uanctl0 register = 0 or the uanrxe bit of the uanctl0 register = 0 has been set when 0 has been written when no stop bit is detected during reception uanfe 0 1 framing error flag only the first bit of the receive data stop bits is checked, regardless of the value of the uansl bit of the uanctl0 register. the uanfe bit can be both read and written, but it can only be cleared by writing 0 to it, and it cannot be set by writing 1 to it. when 1 is written to this bit, the hold status is entered. when the uanpwr bit of the uanctl0 register = 0 or the uanrxe bit of the uanctl0 register = 0 has been set. when 0 has been written when receive data has been set to the uanrxb register and the next receive operation is completed before that receive data has been read uanove 0 1 overrun error flag when an overrun error occurs, the data is discarded without the next receive data being written to the receive buffer. the uanove bit can be both read and written, but it can only be cleared by writing 0 to it. when 1 is written to this bit, the hold status is entered. <7> <0>
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 392 (6) uartan receive data register (uanrx) the uanrx register is an 8-bit buffer register that stores parallel data converted by receive shift register. the data stored in the receive shift register is transferred to the uanrx register upon completion of reception of 1 byte of data. during lsb-first reception when the data length has been specified as 7 bits, the receive data is transferred to bits 6 to 0 of the uanrx register and the msb always becomes 0. during msb-first reception, the receive data is transferred to bits 7 to 1 of the uanrx register and the lsb always becomes 0. when an overrun error (uanove) occurs, the receive data at this time is not transferred to the uanrx register. this register is read-only, in 8-bit units. in addition to reset input, the uanrx register can be set to ffh by clearing the uanpwr bit of the uanctl0 register to 0. uanrx (n = 0 to 2) 654321 after reset: ffh r address: ua0rx fffffa06h, ua1rx fffffa16h, ua2rx fffffa26h 7 0 (7) uartan transmit data register (uantx) the uantx register is an 8-bit register used to set transmit data. this register can be read or written in 8-bit units. reset input sets this register to ffh. uantx (n = 0 to 2) 654321 after reset: ffh r/w address: ua0tx fffffa07h, ua1tx fffffa17h, ua2tx fffffa27h 7 0
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 393 15.5 interrupt request signals the following two interrupt request signals are generated from uartan. ? reception complete interrupt request signal (intuanr) ? transmission enable interrupt request signal (intuant) the default priority for these two interrupt request signals is highest for the reception complete interrupt request signal. table 15-1. interrupts and their default priorities interrupt priority reception complete high transmission enable low (1) reception complete interrupt request signal (intuanr) a reception complete interrupt request signal is output when data is shifted into the receive shift register and transferred to the uanrx register in the reception enabled status. a reception complete interrupt request signal can be generated instead of a reception error interrupt even when a reception error has occurred. when a reception complete interrupt request signal is received and the data is read, read the uanstr register and check that the reception result is not an error. no reception complete interrupt request signal is generated in the reception disabled status. (2) transmission enable interrupt request signal (intuant) if transmit data is transferred from the uantx register to the uartan transmit shift register with transmission enabled, the transmission enable interrupt request signal is generated.
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 394 15.6 operation 15.6.1 data format full-duplex serial data reception and transmission is performed. as shown in figure 15-5, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s). specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and specification of msb/lsb-first transfer are performed using the uanctl0 register. moreover, control of uart output/inverted output for the txdan bit is performed using the uantdl bit of the uanopt0 register. ? start bit..................1 bit ? character bits ........7 bits/8 bits ? parity bit ................even parity/odd parity/0 parity/no parity ? stop bit ..................1 bit/2 bits
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 395 figure 15-5. uarta transmit/receive data format (a) 8-bit data length, lsb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit (b) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (c) 8-bit data length, msb first, even parity, 1 stop bit, transfer data: 55h, txdan inversion 1 data frame start bit d7 d6 d5 d4 d3 d2 d1 d0 parity bit stop bit (d) 7-bit data length, lsb first, odd parity, 2 stop bits, transfer data: 36h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 parity bit stop bit stop bit (e) 8-bit data length, lsb first, no parity, 1 stop bit, transfer data: 87h 1 data frame start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 396 15.6.2 sbf transmission/reception format the v850es/sg2 has an sbf (sync break field) transmission/reception control function to enable use of the lin (local interconnect network) function. figure 15-6. lin transmission manipulation outline sleep bus wake-up signal frame synch break field synch field ident field data field data field check sum field intuanr interrupt txdan (output) note 3 8 bits note 1 note 2 13 bits sbf transmission note 4 55h transmission data transmission data transmission data transmission data transmission notes 1. the interval between each field is controlled by software. 2. sbf output is performed by hardware. the output width is the bit length set by bits uansbl2 to uansbl0 of the uanopt0 register. if even finer output width adjustments are required, such adjustments can be performed using bits uanbrs7 to uanbrs0 of the uanctln register. 3. 80h transfer in the 8-bit mode is substituted for the wake-up signal frame. 4. a transmission enable interrupt request signal (intuant) is output at the start of each transmission. the intuant signal is also output at the start of each sbf transmission.
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 397 figure 15-7. lin reception manipulation outline reception interrupt (intuanr) edge detection capture timer disable disable enable txdan (output) enable note 2 13 bits sbf reception note 3 note 4 note 1 sf reception id reception data transmission data transmission note 5 data transmission sleep bus wake-up signal frame synch break field synch field ident field data field data field check sum field notes 1. the wakeup signal is sent by the pin edge detector, uarta is enabled, and the sbf reception mode is set. 2. the receive operation is performed until detection of the stop bit. upon detection of sbf reception of 11 or more bits, normal sbf reception end is judged, and an interrupt signal is output. upon detection of sbf reception of less than 11 bits, an sbf reception error is judged, no interrupt signal is output, and the mode returns to the sbf reception mode. 3. if sbf reception ends normally, an interrupt signal is output. the timer is enabled by an sbf reception complete interrupt. moreover, error detection for the uanove, uanpe, and uanfe bits of the uanstr register is suppressed and uart communication error detection processing and uartan receive shift register and data transfer of the uanrx register are not performed. the uartan receive shift register holds the initial value, ffh. 4. the rxdan pin is connected to ti (capture input) of the timer, the transfer rate is calculated, and the baud rate error is calculated. the value of the uanctl2 register obtained by compensating the baud rate error after dropping uarta enable is set again, causing the status to become the reception status. 5. check-sum field distinctions are made by software. the uarta is initialized following csf reception, and the processing for setting the sbf reception mode again is performed by software.
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 398 15.6.3 sbf transmission when the uanpwr bit = the uantxe bit of the uanctl0 register = 1, the transmission enabled status is entered, and sbf transmission is started by setting (to 1) the sbf transmission trigger (uanstt bit of uanopt0 register). thereafter, a low-level width of bits 13 to 20 specified by the uansls2 to uansls0 bits of the uanopt0 register is output. a transmission enable interrupt request signal (intuant) is generated upon sbf transmission start. following the end of sbf transmission, the uanstt bit is automatically cleared. thereafter, the uart transmission mode is restored. transmission is suspended until the data to be transmitted next is written to the uantx register, or until the sbf transmission trigger (uanstt bit) is set. figure 15-8. sbf transmission intuant interrupt 12345678910111213 stop bit setting of uanstt bit
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 399 15.6.4 sbf reception the reception enabled status is achieved by setting the uanpwr bit of the uanctl0 register to 1 and then setting the uanrx bit of the uanctl0 register to 1. the sbf reception wait status is set by setting the sbf reception trigger (uanstr bit of the uanopt0 register) to 1. in the sbf reception wait status, similarly to the uart reception wait status, the rxdan pin is monitored and start bit detection is performed. following detection of the start bit, reception is started and the internal counter counts up according to the set baud rate. when a stop bit is received, if the sbf width is 11 or more bits, normal processing is judged and a reception complete interrupt request signal (intuanr) is output. error detection for the uanove, uanpe, and uanfe bits of the uanstr register is suppressed and uart communication error detection processing is not performed. moreover, uartan reception shift register and data transfer of the uanrx register are not performed and ffh, the initial value, is held. if the sbf width is 10 or fewer bits, reception is terminated as error processing without outputting an interrupt, and the sbf reception mode is returned to. the uansrf bit is not cleared at this time. figure 15-9. sbf reception (a) normal sbf reception (detection of stop bit in more than 10.5 bits) uansrf 123456 11.5 7 8 9 10 11 intuanr interrupt (b) sbf reception error (detection of stop bit in 10.5 or fewer bits) ua0srf 123456 10.5 78910 intuanr interrupt
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 400 15.6.5 uart transmission a high level is output to the txdan pin by setting the uanpwr bit of the uanctl0 register to 1. next, the transmission enabled status is set by setting the uantxe bit of the uanctl0 register to 1, and transmission is started by writing transmit data to the uantx register. the start bit, parity bit, and stop bit are automatically added. the data in the uantx register is transferred to the uartan transmit shift register upon the start of the transmit operation. a transmission enable interrupt request signal (intuant) is generated upon completion of transmission of the data of the uantx register to the uartan transmit shift register, and thereafter the contents of the uartan transmit shift register are output to the txdan pin lsb first. write of the next transmit data to the uantx register is enabled by generating the intuant signal. continuous transmission is enabled by writing the data to be transmitted next to the uantx register during transfer. figure 15-10. uart transmission start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intuant
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 401 15.6.6 continuous transmission procedure uarta can write the next transmit data to the uantx register when the uartan transmit shift register starts the shift operation. the transfer timing of the uartan transmit shift register can be judged from the transmission enable interrupt request signal (intuant). transmission can be performed without interruption even during interrupt processing following the transmission of 1 data frame via the intuant signal, and an efficient communication rate can thus be achieved. during continuous transmission, overrun (the completion of the next transmission before the first transmission completion processing has been executed) may occur. an overrun can be detected by incorporating a program that can count the number of transmit data and by referencing transfer status flag (uantsf bit of uansrt register). caution during continuous transmission execution, perform initialization after checking that the uantsf bit is 0. the transmit data cannot be guaranteed when initialization is performed when the uantsf bit is 1. figure 15-11. continuous transmission processing flow start register settings uantx write yes yes no no occurrence of transmission interrupt? required number of writes performed? end
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 402 figure 15-12. continuous transfer operation timing (a) transmission start start data (1) data (1) txdan uantx transmission shift register intuant uantsf data (2) data (2) data (1) data (3) parity stop start data (2) parity stop start (b) transmission end start data (n ? 1) data (n ? 1) data (n ? 1) data (n) ff data (n) uattxd uantx transmission shift register intuant uantsf uanpwr or uantxe parity stop stop start data (n) parity parity stop
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 403 15.6.7 uart reception the reception wait status is set by setting the uanpwr bit of the uanctl0 register to 1 and then setting the uanrx bit of the uanctl0 register to 1. in the reception wait status, the rxdan pin is monitored and start bit detection is performed. start bit detection is performed using a two-step detection routine. first, an 8-bit counter starts upon detection of the falling edge of the rxdan pin. when the 8-bit counter has counted the uanctl2 register setting value, the level of the rxdan pin is monitored again (corresponds to the mark in figure 15-3). if the rxdan pin is low level at this time too, a start bit is recognized. after a start bit has been recognized, the receive operation starts, and serial data is saved to the uartan receive shift register according to the set baud rate. when the reception complete interrupt request signal (intuanr) is output upon reception of the stop bit, the data of the uartan receive shift register is written to the uanrx register. however, if an overrun error (uanove bit of uanstr register) occurs, the receive data at this time is not written to the uanrx register. even if a parity error (uanpe bit of uanstr register) or a framing error (uanfe bit of uansrt register) occurs during reception, reception continues until the stop bit reception position, and intuanr is output following reception completion. figure 15-13. uart reception start bit d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit intuanr uanrx cautions 1. be sure to read the uanrx register even when a reception error occurs. if the uanrx register is not read, an overrun error occurs during reception of the next data, and reception errors continue occurring indefinitely. 2. the operation during reception is performed assuming that there is only one stop bit. a second stop bit is ignored.
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 404 15.6.8 reception error errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. a data reception result error flag is set to the uanstr register and a reception complete interrupt request signal (intuanr) is output. during reception error interrupt processing, it is possible to ascertain which error occurred during reception by reading the contents of the uanstr register. the reception error flag is cleared by writing 0 to it. ? reception error causes error flag reception error cause uanpe parity error received parity bit does not match the setting uanfe framing error stop bit not detected uanove overrun error reception of next data completed before data was read from receive buffer
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 405 15.6.9 parity types and operations caution when using the lin function, fix the uanps1 and uanps0 bits of the uanctl0 register to 00. the parity bit is used to detect bit errors in the communication data. normally the same parity is used on the transmission side and the reception side. in the case of even parity and odd parity, it is possible to detect ? 1 ? bit errors (odd count). in the case of 0 parity and no parity, errors cannot be detected. (a) even parity (i) during transmission the number of bits whose value is ? 1 ? among the transmit data, including the parity bit, is controlled so as to be an even number. the parity bit values are as follows. ? odd number of bits whose value is ? 1 ? among transmit data: 1 ? even number of bits whose value is ? 1 ? among transmit data: 0 (ii) during reception the number of bits whose value is ? 1 ? among the reception data, including the parity bit, is counted, and if it is an odd number, a parity error is output. (b) odd parity (i) during transmission opposite to even parity, the number of bits whose value is ? 1 ? among the transmit data, including the parity bit, is controlled so that it is an odd number. the parity bit values are as follows. ? odd number of bits whose value is ? 1 ? among transmit data: 0 ? even number of bits whose value is ? 1 ? among transmit data: 1 (ii) during reception the number of bits whose value is ? 1 ? among the receive data, including the parity bit, is counted, and if it is an even number, a parity error is output. (c) 0 parity during transmission, the parity bit is always made 0, regardless of the transmit data. during reception, parity bit check is not performed. therefore, no parity error is generated, regardless of whether the parity bit is 0 or 1. (d) no parity no parity bit is added to the transmit data. reception is performed assuming that there is no parity bit. no parity error occurs since there is no parity bit.
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 406 15.6.10 receive data noise filter this filter performs the rxdan pin sampling using the internal system clock (f xx ). when the same sampling value is read twice, the match detector output changes and sampling as the input data is performed. moreover, since the circuit is as shown in figure 15-14, the processing that goes on within the receive operation is delayed by 2 clocks in relation to the external signal status. figure 15-14. noise filter circuit match detector in f xx rxdan qin ld_en q receive data signal
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 407 15.7 dedicated baud rate generator the dedicated baud rate generator is configured of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with uartan. regarding the serial clock, a dedicated baud rate generator output can be selected for each channel. there is an 8-bit counter for transmission and another one for reception. (1) baud rate generator configuration figure 15-15. configuration of baud rate generator clock (f xclk ) selector uanpwr 8-bit counter match detector baud rate uanctl2: uanbrs7 to uanbrs0 1/2 uanpwr, uantxen (or uanrxe) uanctl1: uancks3 to uancks0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1024 ascka0 note note only uarta0 is valid, setting uarta1 and uarta2 is prohibited. remarks 1. n = 0 to 2 2. f xx : internal system clock (a) base clock (clock) when the uanpwr bit of the uanctl0 register is 1, the clock selected by bits uancks3 to uancks0 of the uanctl1 register is supplied to the 8-bit counter. this clock is called the base clock (clock) and its frequency is called f xclk . when the uanpwr bit = 0, the clock is fixed to the low level. (b) serial clock generation a serial clock can be generated by setting the uanctl1 register and the uanctl2 register (n = 0 to 2). the base clock is selected by uancks3 to uancks0 bits of the uanctl1 register. the frequency division value for the 8-bit counter can be set using bits uanbrs7 to uanbrs0 of the uanctl2 register.
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 408 (2) uartan control register 1 (uanctl1) the uanctl1 register is an 8-bit register that selects the uartan clock. this register can be read or written in 8-bit units. reset input clears this register to 00h. 0 uanctl1 (n = 0 to 2) 0 0 0 uancks3 uancks2 uancks1 uancks0 654321 after reset: 00h r/w address: ua0ctl1 fffffa01h, ua1ctl1 fffffa11h, ua2ctl1 fffffa21h 7 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 external clock note (ascka0 pin) setting prohibited uancks2 0 0 0 0 1 1 1 1 0 0 0 0 uancks3 0 0 0 0 0 0 0 0 1 1 1 1 base clock (f xclk ) selection uancks1 0 0 1 1 0 0 1 1 0 0 1 1 uancks0 0 1 0 1 0 1 0 1 0 1 0 1 other than above note only uarta0 is valid; setting uarta1 and uarta2 is prohibited.
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 409 (3) uartan control register 2 (uanctl2) the uanctl2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of uartan. this register can be read or written in 8-bit units. reset input sets this register to ffh. uanbrs7 uanctl2 (n = 0 to 2) uanbrs6 uanbrs5 uanbrs4 uanbrs3 uanbrs2 uanbrs1 uanbrs0 654321 after reset ffh r/w address: ua0ctl2 fffffa02h, ua1ctl2 fffffa12h, ua2ctl2 fffffa22h 7 0 uan brs7 0 0 0 0 : 1 1 1 1 uan brs6 0 0 0 0 : 1 1 1 1 uan brs5 0 0 0 0 : 1 1 1 1 uan brs4 0 0 0 0 : 1 1 1 1 uan brs3 0 0 0 0 : 1 1 1 1 uan brs2 0 1 1 1 : 1 1 1 1 uan brs1 0 0 1 : 0 0 1 1 uan brs0 0 1 0 : 0 1 0 1 default (k) 4 5 6 : 252 253 254 255 serial clock f xclk /4 f xclk /5 f xclk /6 : f xclk /252 f xclk /253 f xclk /254 f xclk /255 setting prohibited remark f xclk : clock frequency selected by the uancks3 to uancks0 bits of the uanctl1 register
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 410 (4) baud rate the baud rate is obtained by the following equation. baud rate = [bps] f xclk = frequency of base clock (clock) selected by bits uancks3 to uancks0 of uanctl1 register k = value set using bits uanbrs7 to uanbrs0 of uanctl2 register (k = 4, 5, 6, ..., 255) (5) baud rate error the baud rate error is obtained by the following equation. error (%) = ? 1 100 [%] cautions 1. the baud rate error during transmission must be within the error tolerance on the receiving side. 2. the baud rate error during reception must satisfy the range indicated in section (7) allowable baud rate range during reception. example base clock (clock) frequency = 20 mhz = 20,000,000 hz setting value of bits uanbrs7 to uanbrs0 of uanctl2 register = 01000001b (k = 65) target baud rate = 153,600 baud rate = 20,000,000/ (2 65) = 153,846 [bps] error = (153,846/153,600 ? 1) 100 = 0.160 [%] f xclk 2 k actual baud rate (baud rate with error) desired baud rate (correct baud rate)
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 411 (6) baud rate setting example table 15-2. baud rate generator setting data baud rate f xx = 20 mhz f xx = 16 mhz f xx = 10 mhz (bps) uanctl1 uanctl2 err (%) uanctl1 uanctl2 err (%) uanctl1 uanctl2 err (%) 300 09h 41h 0.16 0ah 1ah 0.16 08h 41h 0.16 600 08h 41h 0.16 0ah 0dh 0.16 07h 41h 0.16 1200 07h 41h 0.16 09h 0dh 0.16 06h 41h 0.16 2400 06h 41h 0.16 08h 0dh 0.16 05h 41h 0.16 4800 05h 41h 0.16 07h 0dh 0.16 04h 41h 0.16 9600 04h 41h 0.16 06h 0dh 0.16 03h 41h 0.16 19200 03h 41h 0.16 05h 0dh 0.16 02h 41h 0.16 31250 06h 05h 0.00 06h 04h 0.00 05h 05h 0.00 38400 02h 41h 0.16 04h 0dh 0.16 01h 41h 0.16 76800 01h 41h 0.16 03h 0dh 0.16 00h 41h 0.16 153600 00h 41h 0.16 02h 0dh 0.16 00h 21h ? 1.36 312500 03h 04h 0.00 01h 0dh ? 1.54 02h 04h 0.00 remark f xx : internal system clock err: baud rate error (%)
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 412 (7) allowable baud rate range during reception the baud rate error range at the destination that is allowable during reception is shown below. caution the baud rate error during reception must be set within the allowable error range using the following equation. figure 15-16. allowable baud rate range during reception fl 1 data frame (11 fl) flmin flmax uartn transfer rate start bit bit 0 bit 1 bit 7 parity bit minimum allowable transfer rate maximum allowable transfer rate stop bit start bit bit 0 bit 1 bit 7 parity bit latch timing stop bit start bit bit 0 bit 1 bit 7 parity bit stop bit remark n = 0 to 2 as shown in figure 15-16, the receive data latch timing is determined by the counter set using the uanctl2 register following start bit detection. the transmit data can be normally received if up to the last data (stop bit) can be received in time for this latch timing. when this is applied to 11-bit reception, the following results in terms of logic. fl = (brate) ? 1 brate: uartan baud rate (n = 0 to 2) k: uanctl2 setting value (n = 0 to 2) fl: 1-bit data length latch timing margin: 2 clocks minimum allowable transfer rate: flmin = 11 fl ? fl = fl k ? 2 2k 21k + 2 2k
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 413 therefore, the maximum baud rate that can be received by the destination is as follows. brmax = (flmin/11) ? 1 = brate similarly, obtaining the following maximum allowable transfer rate yields the following. flmax = 11 fl ? fl = fl flmax = fl 11 therefore, the minimum baud rate that can be received by the destination is as follows. brmin = (flmax/11) ? 1 = brate obtaining the allowable baud rate error for uartn and the destination from the above-described equations for obtaining the minimum and maximum baud rate values yields the following. table 15-3. maximum/minimum allowable baud rate error divide ratio (k) maximum allowable baud rate error minimum allowable baud rate error 8 +3.53% ? 3.61% 20 +4.26% ? 4.31% 50 +4.56% ? 4.58% 100 +4.66% ? 4.67% 255 +4.72% ? 4.73% remarks 1. the reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division ratio (k). the higher the input clock frequency and the larger the division ratio (k), the higher the accuracy is. 2. k: uanctl2 setting value (n = 0 to 2) 10 11 k + 2 2 k 21k ? 2 2 k 21k ? 2 20 k 22k 21k + 2 20k 21k ? 2
chapter 15 asynchronous serial interface a (uarta) preliminary user ? s manual u16541ej1v0um 414 (8) baud rate during continuous transmission during continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 clocks longer. however, timing initialization is performed through start bit detection by the receiving side, so this has no influence on the transfer result. figure 15-17. transfer rate during continuous transfer start bit bit 0 bit 1 bit 7 parity bit stop bit fl 1 data frame fl fl fl fl fl fl flstp start bit of 2nd byte start bit bit 0 assuming 1 bit data length: fl; stop bit length: flstp; and base clock frequency: f xclk , we obtain the following equation. flstop = fl + 2/f xclk therefore, the transfer rate during continuous transmission is as follows. transfer rate = 11 fl + 2/f xclk
preliminary user?s manual u16541ej1v0um 415 chapter 16 3-wire variable-length serial i/o (csib) 16.1 mode switching of csib and other serial interfaces 16.1.1 csib4 and uarta0 mode switching in the v850es/sg2, csib4 and uarta0 are alternate functions of the same pin and therefore cannot be used simultaneously. csib4 and uarta0 switching must be set in advance using the pmc3 and pfc3 registers. caution the transmit/receive operation of csib4 and uarta0 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user?s manual u16541ej1v0um 416 figure 16-1. csib4 and uarta0 mode switch settings pmc3 after reset: 0000h r/w address: fffff446h, fffff447h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, ffff467h 0 0 0 0 0 0 pfc39 pfc38 pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfce3l after reset: 00h r/w address: fffff706h 0 pfce36 pfce35 pfce34 pfce33 pfce32 0 0 port i/o mode ascka0 mode sckb4 mode port i/o mode uarta0 mode csib4 mode pmc32 0 1 1 pmc3n 0 1 1 operation mode operation mode pfce32 0 0 pfc32 0 1 pfc3n 0 1 remarks 1. n = 0, 1 2. = don ? t care
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 417 16.1.2 csib0 and i 2 c01 mode switching in the v850es/sg2, csib0 and i 2 c01 are alternate functions of the same pin and therefore cannot be used simultaneously. csib0 and i 2 c01 switching must be set in advance using the pmc4 and pfc4 registers. caution the transmit/receive operation of csib0 and i 2 c01 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 16-2. csib0 and i 2 c01 mode switch settings port i/o mode csib0 mode i 2 c01 mode pmc4n 0 1 1 operation mode pfc4n 0 1 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 after reset: 00h r/w address: fffff448h pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 0 pfc41 pfc40 remarks 1. n = 0, 1 2. = don ? t care
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 418 16.2 features { master mode and slave mode selectable { 8-bit to 16-bit transfer, 3-wire serial interface { interrupt request signals (intcbnt, intcbnr) 2 { serial clock and data phase switchable { transfer data length selectable in 1-bit units between 8 and 16 bits { transfer data msb-first/lsb-first switchable { 3-wire transfer sobn: serial data output sibn: serial data input sckbn: serial clock output { transmission mode, reception mode, and transmission/reception mode specifiable remark n = 0 to 4 16.3 configuration csib includes the following hardware. table 16-1. configuration of csib item configuration csibn receive data register (cbnrx) registers csibn transmit data register (cbntx) csibn control register 0 (cbnctl0) csibn control register 1 (cbnctl1) csibn control register 2 (cbnctl2) control registers csibn status register (cbnstr)
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 419 figure 16-3. block diagram of csib internal bus cbnctl2 cbnctl0 cbnstr controller intcbnr sobn intcbnt cbntx so latch phase control shift register cbnrx cbnctl1 phase control sibn f brgm f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 sckbn selector remarks n = 0 to 4 m = 1 (n = 0, 1) m = 2 (n = 2, 3) m = 3 (n = 4)
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 420 (1) csibn receive data register (cbnrx) the cbnrx register is a 16-bit buffer register that holds receive data. this register is read-only, in 16-bit units. the receive operation is started by reading the cbnrx register in the reception enabled status. if the transfer data length is 8 bits, this register is read-only as the cbnrxl register for lower 8 bits of the cbnrx register in 8-bit units. reset input clears this register to 0000h. in addition to reset input, the cbnrx register can be initialized by clearing (to 0) the cbnpwr bit of the cbnctl0 register. after reset: 0000h r address: cb0rx fffffd04h, cb1rx fffffd14h, cb2rx fffffd24h, cb3rx fffffd34h, cb4rx fffffd44h cbnrx (n = 0 to 4) (2) csib transmit data register (cbntx) the cbntx register is a 16-bit buffer register used to write the csib transfer data. this register can be read or written in 16-bit units. the transmit operation is started by writing data to the cbntx register in the transmission enabled status. if the transfer data length is 8 bits, this register is read-only as the cbntxl register for lower 8 bits of the cbntx register in 8-bit units. reset input clears this register to 0000h. in addition to reset input, the cbntx register can be initialized by clearing (to 0) the cbnpwr bit of the cbnctl0 register. after reset 0000h r/w address: cb0tx fffffd06h, cb1tx fffffd16h, cb2tx fffffd26h, cb3tx fffffd36h, cb4tx fffffd46h cbntx (n = 0 to 4)
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 421 16.4 control registers the following registers are used to control csib. ? csibn control register 0 (cbnctl0) ? csibn control register 1 (cbnctl1) ? csibn control register 2 (cbnctl2) ? csibn status register (cbnstr) (1) csibn control register 0 (cbnctl0) the cbnctl0 register is a register that controls the csib serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 01h. (1/2) cbnpwr stops clock operation and reset the internal circuit enables clock operation cbnpwr 0 1 specification of csib operation stop/enable cbnctl0 (n = 0 to 4) cbntxe note cbnrxe note cbndir note 00 cbntms note cbnsce after reset: 01h r/w address: cb0ctl0 fffffd00h, cb1ctl0 fffffd10h, cb2ctl0 fffffd20h, cb3ctl0 fffffd30h, cb4ctl0 fffffd40h the cbnpwr bit controls the csib operating clock and resets the internal circuit. stops transmit operation enables trasmit operation cbntxe note 0 1 note specification of transmit operation stop/enable the sobn serial output pin is fixed to low level and communication is stopped by clearing the cbntxe bit to 0. when the cbnrxe bit is cleared to 0, no reception complete interrupt is output even when the prescribed data is transferred in order to stop the receive operation, and the receive data register cbnrx0 is not updated. stops receive operation enables receive operation cbnrxe note 0 1 specification of receive operation stop/enable < > < > < > < > < > note rewrite is possible only when the cbnpwr bit = 0. however, the cbnpwr bit = 1 can also be set at the same time.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 422 (2/2) single transfer mode continuous transfer mode cbntms note 0 1 transfer mode specification when the cbntms bit = 0, single transfer results, so continuous transmission/ continuous reception are not supported. even in the case of transmission only, an interrupt is output upon completion of reception transfer. clock output stopped clock output enabled cbnsce 0 1 specification of start transfer disable/enable the cbnsce bit controls start of the transfer operation in the master mode. if only reception is enabled (cbnrxe bit = 1, cbntxe bit = 0) in the single transfer mode, the reception operation is started when the cbnrx0 register is read. to read the last receive data, clear the cbnsce bit to 0 to disable the start of the next reception operation. similarly, if only reception is enabled in the continuous transfer mode (cbntms bit = 1), the reception operation after reception of the last data has been completed can be disabled by clearing the cbnsce bit one clock before completion of reception of the last data. after the last data has been read, reception is enabled again by setting the cbnsce bit to 1 again and reading dummy data from the cbnrx0 register. in the slave reception mode, the cbnsce bit is also used to enable the internal operation clock. therefore, use the cbnsce bit when it is set to 1. msb first lsb first cbndir note 0 1 specification of transfer direction mode (msb/lsb) note rewrite is possible only when the cbnpwr bit = 0. however, the cbnpwr bit = 1 can also be set at the same time.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 423 (2) csibn control register 1 (cb0ctl1) the cb0ctl1 is an 8-bit register that controls the csib serial transfer operation. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution the cbnctl1 register can be rewritten when the cbnpwr bit of the cbnctl0 register = 0 or when both the cbntxe and cbnrxe bits = 0. 0 cbnckp 0 0 1 1 specification of data transmission/reception timing in relation to sckbn cbnctl1 (n = 0 to 4) 0 cbndap 0 1 0 1 0 cbnckp cbndap cbncks2 cbncks1 cbncks0 after reset 00h r/w address: cb0ctl1 fffffd01h, cb1ctl1 fffffd11h, cb2ctl1 fffffd21h, cb3ctl1 fffffd31h, cb4ctl1 fffffd41h cbncks2 0 0 0 0 1 1 1 1 cbncks1 0 0 1 1 0 0 1 1 cbncks0 0 1 0 1 0 1 0 1 input clock f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f brg m external clock (sckbn) master mode master mode master mode master mode master mode master mode master mode slave mode mode d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture sobn (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture (output) d7 d6 d5 d4 d3 d2 d1 d0 sckbn (i/o) sibn capture (output) note when n = 0, 1, m = 1 when n = 2, 3, m = 2 when n = 4, m = 3 for details on the baud rate generator, see 16.8 baud rate generator .
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 424 (3) csibn control register 2 (cbnctl2) the cbnctl2 register is an 8-bit register that controls the number of csib serial transfer bits. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution the cbnctl2 register can be rewritten only when the cbnpwr bit of the cbnctl0 register = 0 or when both the cb0txe and cb0rxe bits = 0. after reset: 00h r/w address: cb0ctl2 fffffd02h, cb1ctl2 fffffd12h, cb2ctl2 fffffd22h, cb3ctl2 fffffd32h, cb4ctl2 fffffd42h 0 cbnctl2 0 0 0 cbncl3 cbncl2 cbncl1 cbncl0 8 bits 9 bits 10 bits 11 bits 12 bits 13 bits 14 bits 15 bits 16 bits cbncl3 0 0 0 0 0 0 0 0 1 cbncl2 0 0 0 0 1 1 1 1 cbncl1 0 0 1 1 0 0 1 1 cbncl0 0 1 0 1 0 1 0 1 serial register bit length caution if the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the lsb of the cbntx and cbnrx registers.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 425 (a) transfer data length change function the csib transfer data length can be set in 1-bit units between 8 and 16 bits using bits cbncl3 to cbncl0 of the cbnctl2 register. when the transfer bit length is set to a value other than 16 bits, set the data to the cbntx or cbnrx register starting from the lsb, regardless of whether the transfer start bit is the msb or lsb. any data can be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer. (i) transfer bit length = 10 bits, msb first 15 10 9 0 sobn sibn insertion of 0 (ii) transfer bit length = 12 bits, lsb first 0 sobn 11 12 15 sibn insertion of 0
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 426 (4) csibn status register (cbnstr) the cbnstr register is an 8-bit register that displays the csib status. this register can be read or written in 8-bit or 1-bit units, but the cbnstf flag is a read-only. reset input clears this register to 00h. in addition to reset input, the cbnstr register can be initialized by clearing (0) the cbnpwr bit of the cbnctl0 register. cbntsf idle status operating status cbntsf 0 1 transfer operation status flag cbnstr (n = 0 to 4) 00 0 00 0 cbnove after reset 00h r/w address: cb0str fffffd03h, cb1str fffffd13h, cb2str fffffd23h, cb3str fffffd33h, cb4str fffffd43h during transmission, this register is set when data is prepared in the cbntx register, and during reception, it is set when a dummy read of the cbnrx register is performed. the clear timing is after the end of the edge of the last clock. no overrun overrun cbnove 0 1 overrun error flag an overrun error occurs when the next reception starts without performing a cpu read of the value of the receive buffer, upon completion of the receive operation. the cbnove flag displays the overrun error occurrence status in this case. the cbnove flag is cleared by writing 0 to it. it cannot be set even by writing 1 to it. < > < >
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 427 16.5 operation 16.5.1 single transfer (master mode, transmission/reception mode) msb first (cbndir bit of cbnctl0 register = 0), the cbnckp bit of the cbnctl1 register = 0, msb first (cbndir bit of cbnctl0 register = 0), the cbndap bit of the cbnctl1 register = 0, transfer data length = 8 bits (cbncl3 to cbncl0 bits of cbnctl2 register = 0, 0, 0, 0) cbntx write (55h) cbnrx read (aah) (aah) (55h) 1 0 1 1 0 1 abh 56h adh 5ah b5h 6ah d5h aah 55h (transmit data) sckbn cbntx aah 00h 00h cbnrx shift register intcbnr sibn sobn 0 0 0 1 0 0 1 0 1 1 (1) (4) (5) (7) (6) (2) (3) (1) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (2) set the cbntxe and cbnrxe bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the transmission/reception enabled status. (3) set the cbnpwr bit of the cbnctl0 register = 1 to enable csib operating clock supply. (4) write transfer data to the cbntx register (transmission start). (5) the reception complete interrupt request signal (intcbnr) is output, notifying the cpu that reading the cbnrx (cbnrxl) register is possible. (6) read the cbnrx register before clearing the cbnpwr bit to 0. (7) check that the cbntsf bit of the cbnstr register = 0 and set the cbnpwr bit to 0 to stop clock supply to csib (end of transmission/reception). to continue transfer, repeat steps (4) to (6) before (7). remark the processing of steps (2) and (3) can be set simultaneously.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 428 16.5.2 single transfer mode (master mode, reception mode) msb first (cbndir bit of cbnctl0 register = 0), the cbnckp bit of the cbnctl1 register = 0, msb first (cbndir bit of cbnctl0 register = 0), the cbndap bit of the cbnctl1 register = 0, transfer data length = 8 bits (cbncl3 to cbncl0 bits of cbnctl2 register = 0, 0, 0, 0) (aah) 1 0 1 1 0 1 abh 56h adh 5ah b5h 6ah d5h aah 55h (receive data) sckbn cbnrx cbnrx read (55h) shift register cbnsce intcbnr sibn sobn 0 0 l (1) (2) (3) (4) (5) (6) (8) (7) cbnrx read (aah) aah 00h 00h (1) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (2) set the cbnrxe bit of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the reception enabled status. (3) set the cbnpwr bit of the cbnctl0 register = 1 to enable csib operating clock supply. (4) perform a dummy read of the cbnrx register (reception start trigger). (5) the reception complete interrupt request signal (intcbnr) is output, notifying the cpu that reading the cbnrx (cbnrxl) register is possible. (6) set the cbnsce bit of the cbnctl0 register to 0 to set the reception end data status. (7) read the cbnrx register before clearing the cbnpwr bit to 0. (8) check that the cbntsf bit of the cbnstr register = 0 and set the cbnpwr bit to 0 to stop clock supply to csib (end of reception). to continue transfer, repeat steps (4) and (5) before (6). (at this time, (4) is not a dummy read, but a receive data read combined with the reception trigger.) remark the processing of steps (2) and (3) can be set simultaneously.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 429 16.5.3 continuous mode (master mode, transmission/reception mode) msb first (cbndir bit of cbnctl0 register = 0), the cbnckp bit of the cbnctl1 register = 1, the cbndap bit of the cbnctl1 register = 0, transfer data length = 8 bits (cbncl3 to cbncl0 bits of cbnctl2 register = 0, 0, 0, 0) (7) (6) (6) (5) (4) (2) (1) (3) 96h 00h cch 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 55h cbntx sckbn sobn sibn intcbnt intcbnr shift register so latch cbnrx 0 0 0 0 0 0 aah 96h cch 1 1 1 0 0 0 00h (1) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (2) set the cbntxe and cbnrxe bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the transmission/reception enabled status. (3) set the cbnpwr bit of the cbnctl0 register = 1 to enable csib operating clock supply. (4) write transfer data to the cbntx register (transmission start). (5) the transmission complete interrupt request signal (intcbnr) is received and transfer data is written to the cbntx register. (6) the reception complete interrupt request signal (intcbnr) is output, notifying the cpu that reading the cbnrx (cbnrxl) register is possible. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. (7) check that the cbntsf bit of the cbnstr register = 0 and set the cbnpwr bit to 0 to stop clock supply to csib (end of transmission/reception). to continue transfer, repeat steps (4) to (6) before (7).
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 430 16.5.4 continuous mode (master mode, reception mode) msb first (cbndir bit of cbnctl0 register = 0), the cbnckp bit of the cbnctl1 register = 0, the cbndap bit of the cbnctl1 register = 1, transfer data length = 8 bits (cbncl3 to cbncl0 bits of cbnctl2 register = 0, 0, 0, 0) (7) (5) (5) (6) (4) (2) (1) (3) 1 0 0 0 0 0 0 01 1 1 1 1 55h sckbn cbnsce sibn intcnr shift register cbnrx 1 1 0 55h aah aah 00h 00h (1) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (2) set the cbnrxe bit of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the reception enabled status. (3) set the cbnpwr bit of the cbnctl0 register = 1 to enable csib operating clock supply. (4) perform a dummy read of the cbnrx register (reception start trigger). (5) the reception complete interrupt request signal (intcbnr) is output, notifying the cpu that reading the cbnrx (cbnrxl) register is possible. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. (6) set the cbnsce bit of the cbnctl0 register = 0 to set the reception end data status. (7) check that the cbntsf bit of the cbnstr register = 0 and set the cbnpwr bit to 0 to stop clock supply to csib (end of reception). to continue transfer, repeat steps (4) and (5) before (6).
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 431 16.5.5 continuous reception mode (error) msb first (cbndir bit of cbnctl0 register = 0), the cbnckp bit of the cbnctl1 register = 0, the cbndap bit of the cbnctl1 register = 1, transfer data length = 8 bits (cbncl3 to cbncl0 bits of cbnctl2 register = 0, 0, 0, 0) (7) (8) (9) (6) (5) (4) (2) (1) (3) aah 00h 00h 1 0 0 0 0 0 01 1 1 1 1 1 sckbn sibn intcbnr shift register cbnrx cbnove 55h 55h 0 1 0 aah (1) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (2) set the cbnrxe bit of the cbnctl0 register = 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the reception enabled status. (3) set the cbnpwr bit of the cbnctl0 register = 1 to enable csib operating clock supply. (4) perform a dummy read of the cbnrx register (reception start trigger). (5) the reception complete interrupt request signal (intcbnr) is output, notifying the cpu that reading the cbnrx (cbnrxl) register is possible. (6) if the data could not be read before the end of the next transfer, the cbnove flag of the cbnstr register is set upon the end of reception and a reception complete interrupt request signal (intcbnr) is output. read the cbnrx register before the next receive data arrives. (7) overrun error processing is performed after checking that the cbnove bit = 1 in the intcbnr interrupt servicing. (8) clear (0) cbnove. (9) check that the cbntsf bit of the cbnstr register = 0 and set the cbnpwr bit to 0 to stop clock supply to csib (end of reception).
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 432 16.5.6 continuous mode (slave mode, transmission/reception mode) msb first (cbndir bit of cbnctl0 register = 0), the cbnckp bit of the cbnctl1 register = 0, the cbndap bit of the cbnctl1 register = 1, transfer data length = 8 bits (csncl3 to cbncl0 bits of cbnctl2 register = 0, 0, 0, 0) (7) (6) (6) (5) (4) (2) (1) (3) 96h 00h cch 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 55h cbntx sckbn sobn sibn intcbnt intcbnr shift register so latch cbnrx 0 0 0 0 0 0 aah 96h cch 1 0 0 0 1 1 00h (1) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (2) set the cbntxe and cbnrxe bits of the cbnctl0 register to 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the transmission/reception enabled status. (3) set the cbnpwr bit of the cbnctl0 register = 1 to enable csib operating clock supply. (4) write the transfer data to the cbntx register. (5) the transmission enable interrupt request signal (intcbnt) is received and the transfer data is written to the cbntx register. (6) the reception complete interrupt request signal (intcbnr) is output, notifying the cpu that reading the cbnrx register is possible. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. (7) check that the cbntsf bit of the cbnstr register = 0 and set the cbnpwr bit to 0 to stop clock supply to csib (end of transmission/reception). to continue transfer, repeat steps (4) to (6) before (7).
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 433 16.5.7 continuous mode (slave mode, reception mode) msb first (cbndir bit of cbnctl0 register = 0), the cbnckp bit of the cbnctl1 register = 0, the cbndap bit of the cbnctl1 register = 0, transfer data length = 8 bits (csncl3 to cbncl0 bits of cbnctl2 register = 0, 0, 0, 0) (6) (5) (5) (4) (2) (1) (3) 1 0 0 0 0 0 0 01 1 1 1 1 55h sckbn sibn intcbnr shift register cbnrx 1 1 55h aah 00h 00h aah 0 (1) set the cbnctl1 and cbnctl2 registers to specify the transfer mode. (2) set the cbndir bit of the cbnctl0 register = 1 at the same time as specifying the transfer mode using the cbndir bit of the cbnctl0 register, to set the reception enabled status. (3) set the cbnpwr bit of the cbnctl0 register = 1 to enable csib operating clock supply. (4) perform a dummy read of the cbnrx register (reception start trigger). (5) the reception complete interrupt request signal (intcbnr) is output, notifying the cpu that reading the cbnrx register is possible. read the cbnrx register before the next receive data arrives or before the cbnpwr bit is cleared to 0. (6) check that the cbntsf bit of the cbnstr register = 0 and set the cbnpwr bit to 0 to stop clock supply to csib (end of reception). to continue transfer, repeat steps (4) and (5) before (6).
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 434 16.5.8 clock timing (1/2) (i) cbnckp = 0, cbndap = 0 d6 d5 d4 d3 d2 d1 sckbn sibn capture reg-r/w sobn intcbnt interrupt intcbnr interrupt cbntsf d0 d7 (ii) cbnckp = 1, cbndap = 0 d6 d5 d4 d3 d2 d1 d0 d7 sckbn sibn capture reg-r/w sobn intcbnt interrupt intcbnr interrupt cbntsf
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 435 (2/2) (iii) cbnckp = 0, cbndap = 1 d6 d5 d4 d3 d2 d1 d0 d7 sckbn sibn capture reg-r/w sobn intcbnt interrupt intcbnr interrupt cbntsf (iv) cbnckp = 1, cbndap = 1 d6 d5 d4 d3 d2 d1 d0 d7 sckbn sibn capture reg-r/w sobn intcbnt interrupt intcbnr interrupt cbntsf
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 436 16.6 output pins (1) sckbn pin when csibn operation is disabled (cbnpwr bit of cbnctl0 register = 0), the sckbn pin output status is as follows. cbnckp sckbn pin output 0 fixed to high level 1 fixed to low level remarks 1. the sckbn pin output changes when the cbnckp bit of the cbnctl1 register is rewritten. 2. n = 0 to 4 (2) sobn pin when csibn operation is disabled (cbnpwr bit = 0), the sobn pin output status is as follows. cbntxe cbndap cbndir sobn pin output 0 fixed to low level 0 sobn latch value (low level) 0 cbntxn value (msb) 1 1 1 cbntxn value (lsb) remarks 1. the sobn pin output changes when any one of the cbntxe, cbndap, and cbndir bits of the cbnctl1 register is rewritten. 2. n = 0 to 4 3. : don ? t care
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 437 16.7 operation flow (1) single transmission start no yes intcbnr = 1 transfer data exists? end yes no initial settings cbnctl0 note /cbnctl1, etc. cbntx write (transfer start) note set the cbnsce bit to 1 as part of the initial settings.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 438 (2) single reception (master) start no no intcbnr = 1 last data? end yes yes initial settings cbnctl0 note /cbnctl1, etc. cbnrx dummy read cbnctl0: cbnsce = 0 cbnctl0: cbnsce = 1 cbnrx read cbnrx read note set the cbnsce bit to 1 as part of the initial settings.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 439 (3) single reception (slave) start no no intcbnr = 1 last data? end yes yes initial settings cbnctl0/cbnctl1, etc. cbnrx dummy read cbnrx read
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 440 (4) continuous transmission start no yes intcbnt = 1 data to be transferred next exists? end yes no initial settings cbnctl0 note /cbnctl1, etc. cbntx write (transfer start) note set the cbnsce bit to 1 as part of the initial settings. remark the steps below the broken line constitute the transmission flow. execute only the steps below the broken line when starting the second and subsequent transmissions.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 441 (5) continuous reception (master) start no no no intcbnr = 1 intcbnr = 1 data currently transmitted = last data? end yes yes yes initial settings cbnctl0 note /cbnctl1, etc. cbnrx dummy read cbnctl0: cbnsce = 0 cbnctl0: cbnsce = 1 cbnrx read cbnrx read cbnrx read note set the cbnsce bit to 1 as part of the initial settings.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 442 (6) continuous reception (slave) start no no intcbnr = 1 last data? end yes yes initial settings cbnctl0 note /cbnctl1, etc. cbnrx dummy read cbnrx read note set the cbnsce bit to 1 as part of the initial settings.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 443 16.8 baud rate generator the brg1 to brg3 and csib0 to csib4 baud rate generators are connected as shown in the following block diagram. csib0 csib1 csib2 csib3 csib4 brg1 brg2 brg3 f x f x f x (1) prescaler mode registers 1 to 3 (prsm1 to prsm3) the prsm1 to prsm3 registers control generation of the baud rate signal for csib. these registers can be read or written in 8-bit or 1-bit units. reset input clears these registers to 00h. 0 prsmm (m = 1 to 3) 0 0 bgcem 0 0 bgcs1m bgcs0m disabled enabled bgcem 0 1 baud rate output f xx f xx /2 f xx /4 f xx /8 setting value (k) 0 1 2 3 bgcs1m 0 0 1 1 bgcs0m 0 1 0 1 input clock selection (f bgcsm ) after reset: 00h r/w address: prsm1 fffff320h, prsm2 fffff324h, prsm3 fffff328h < > cautions 1. do not rewrite the prsmm register during operation. 2. set the prsmm register before setting the bgcem bit to 1.
chapter 16 3-wire variable-length serial i/o (csib) preliminary user ? s manual u16541ej1v0um 444 (2) prescaler compare registers 1 to 3 (prscm1 to prscm3) the prscm1 to prscm3 registers are 8-bit compare registers. these registers can be read or written in 8-bit units. reset input clears these registers to 00h. prscmm7 prscmm prscmm6 prscmm5 prscmm4 prscmm3 prscmm2 prscmm1 prscmm0 after reset: 00h r/w address: prscm1 fffff321h, prscm2 fffff325h, prscm3 fffff329h cautions 1. do not rewrite the prscmm register during operation. 2. set the prscmm register before setting the bgcem bit of the prsmm register to 1. 16.8.1 baud rate generation the transmission/reception clock is generated by dividing the main clock. the baud rate generated from the main clock is obtained by the following equation. f brgm = remark f brgm : brgm count clock f xx : main clock oscillation frequency k: prsm register setting value (0 k 3) n: prscm register setting value (1 to ffh) in the case of prscm register setting values 01h to ffh and 00h, n = 256 m: 1 to 3 f xx 2 k n 2
preliminary user?s manual u16541ej1v0um 445 chapter 17 i 2 c bus to use the i 2 c bus function, set the p38/sda00, p39/scl00, p40/sda01, p41/scl01, p90/sda02, and p91/scl02 pins to n-ch open-drain output. 17.1 mode switching of i 2 c bus and other serial interfaces 17.1.1 uarta2 and i 2 c00 mode switching in the v850es/sg2, uarta2 and i 2 c00 are alternate functions of the same pin and therefore cannot be used simultaneously. uarta2 and i 2 c00 switching must be set in advance using the pmc3 and pfc3 registers. caution the transmit/receive operation of uarta2 and i 2 c00 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-1. uarta2 and i 2 c00 mode switch settings pmc3 after reset: 0000h r/w address: fffff446h, fffff447h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc3 after reset: 0000h r/w address: fffff466h, ffff467h 0 0 0 0 0 0 pfc39 pfc38 pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 port i/o mode uarta2 mode i 2 c00 mode pmc3n 0 1 1 operation mode pfc3n 0 1 remarks 1. n = 8, 9 2. = don ? t care
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 446 17.1.2 csib0 and i 2 c01 mode switching in the v850es/sg2, csib0 and i 2 c01 are alternate functions of the same pin and therefore cannot be used simultaneously. csib0 and i 2 c01 switching must be set in advance using the pmc4 and pfc4 registers. caution the transmit/receive operation of csib0 and i 2 c01 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-2. csib0 and i 2 c01 mode switch settings port i/o mode csib0 mode i 2 c01 mode pmc4n 0 1 1 operation mode pfc4n 0 1 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 after reset: 00h r/w address: fffff448h pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 0 pfc41 pfc40 remarks 1. n = 0, 1 2. = don ? t care
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 447 17.1.3 uarta1 and i 2 c02 mode switching in the v850es/sg2, uarta1 and i 2 c02 are alternate functions of the same pin and therefore cannot be used simultaneously. uarta1 and i 2 c02 switching must be set in advance using the pmc9, pfc9, and pmce9 registers. caution the transmit/receive operation of uarta1 and i 2 c02 is not guaranteed if these functions are switched during transmission or reception. be sure to disable the one that is not used. figure 17-3. uarta1 and i 2 c02 mode switch settings pmc9 after reset: 0000h r/w address: fffff452h, fffff453h pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc39 pmc38 8 9 10 11 12 13 14 15 pfc9 after reset: 0000h r/w address: fffff472h, ffff473h pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 8 9 10 11 12 13 14 15 pfce915 pfce914 0 0 0 0 0 0 pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 8 9 10 11 12 13 14 15 pfce9 after reset: 0000h r/w address: fffff712h, fffff713 uarta1 mode i 2 c02 mode pmc9n 1 1 operation mode pfce9n 1 1 pfc9n 0 1 remark n = 0, 1
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 448 17.2 features i 2 c00 to i 2 c02 have the following two modes. ? operation stopped mode ? i 2 c (inter ic) bus mode (multimasters supported) (1) operation stopped mode in this mode, serial transfers are not performed, thus enabling a reduction in power consumption. (2) i 2 c bus mode (multimaster support) this mode is used for 8-bit data transfers with several devices via two lines: a serial clock pin (scl0n) and a serial data bus pin (sda0n). this mode complies with the i 2 c bus format and the master device can output ? start condition ? , ? data ? , and ? stop condition ? data to the slave device via the serial data bus. the slave device automatically detects these received data by hardware. this function can simplify the part of an application program that controls the i 2 c bus. since scl0n and sda0n pins are n-ch open-drain outputs, i 2 c0n requires pull-up resistors for the serial clock line and the serial data bus line. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 449 figure 17-4. block diagram of i 2 c0n iicen dq cln1, cln0 sda0n scl0n intiicn lreln wreln spien wtimn acken sttn sptn mstsn aldn excn coin trcn ackdn stdn spdn f xx stcfn iicbsyn stcenn iicrsvn cldn dadn smcn dfcn cln1 cln0 clxn ocksm1 prescaler ocksm0 f xx to f xx /5 internal bus internal bus iic control register n (iiccn) iic status register n (iicsn) set clear slave address register n (svan) noise eliminator match signal iic shift register n (iicn) so latch start condition generator data hold time correction circuit acknowledge output circuit wakeup controller n-ch open-drain output acknowledge detector start condition detector stop condition detector serial clock counter interrupt request signal generator noise eliminator serial clock controller serial clock wait controller bus status detector iic clock select register n (iiccln) iic function expansion register n (iicxn) iic flag register n (iicfn) n-ch open-drain output ocksenm prescaler iic division clock select register m (ocksm) remark n = 0 to 2 m = 0, 1
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 450 a serial bus configuration example is shown below. figure 17-5. serial bus configuration example using i 2 c bus sda scl sda +v dd +v dd scl sda scl slave cpu3 address 3 sda scl slave ic address 4 sda scl slave ic address n master cpu1 slave cpu1 address 1 serial data bus serial clock master cpu2 slave cpu2 address 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 451 17.3 configuration i 2 c0n includes the following hardware (n = 0 to 2). table 17-1. configuration of i 2 c0n item configuration registers iic shift register n (iicn) slave address register n (svan) control registers iic control register n (iiccn) iic status register n (iicsn) iic flag register n (iicf0n) iic clock select register n (iiccln) iic function expansion register n (iicxn) iic division clock select registers 0, 1 (ocks0, ocks1) (1) iic shift register n (iicn) the iicn register converts 8-bit serial data to 8-bit parallel data and converts 8-bit parallel data to 8-bit serial data, and can be used for both transmission and reception (n = 0 to 2). write and read operations to the iicn register are used to control the actual transmit and receive operations. this register can be read or written in 8-bit units. reset input clears this register to 00h. (2) slave address register n (svan) the svan register sets local addresses when in slave mode (n = 0 to 2). this register can be read or written in 8-bit units. reset input clears this register to 00h. (3) so latch the so latch is used to retain the output level of the sda0n pin (n = 0 to 2). (4) wake-up controller this circuit generates an interrupt request when the address received by this register matches the address value set to the svan register or when an extension code is received (n = 0 to 2). (5) clock selector this selects the sampling clock to be used. (6) serial clock counter this counter counts the serial clocks that are output and the serial clocks that are input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received.
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 452 (7) interrupt request signal generator this circuit controls the generation of interrupt request signals (intiicn). an i 2 c interrupt is generated following either of two triggers. ? eighth or ninth clock of the serial clock (set by wtimn bit of iiccn register) ? interrupt request generated when a stop condition is detected (set by spien bit of iiccn register) remark n = 0 to 2 (8) serial clock controller in master mode, this circuit generates the clock output via the scl0n pin from a sampling clock (n = 0 to 2). (9) serial clock wait controller this circuit controls the wait timing. (10) ack output circuit, stop condition detector, start condition detector, and ack detector these circuits are used to output and detect various control signals. (11) data hold time correction circuit this circuit generates the hold time for data corresponding to the falling edge of the scl0n pin. (12) start condition generator a start condition is issued when the sttn bit of the iiccn register is set. however, in the communication reservation disabled status (iicrsvn bit of iicfn register = 1), this request is ignored and the stcfn bit of the iicfn register is set if the bus is not released (iicbsyn bit of iicfn register = 1). (13) bus status detector whether the bus is released or not is ascertained by detecting a start condition and stop condition. however, the bus status cannot be detected immediately after operation, so set the initial status by using the stcenn bit of the iiccfn register.
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 453 17.4 control registers i 2 c0 to i 2 c2 are controlled by the following registers. ? iic control registers 0 to 2 (iicc0 to iicc2) ? iic status registers 0 to 2 (iics0 to iics2) ? iic flag registers 0 to 2 (iicf0 to iicf2) ? iic clock select registers 0 to 2 (iiccl0 to iiccl2) ? iic function expansion registers 0 to 2 (iicx0 to iicx2) ? iic division clock select registers 0, 1 (ocks0, ocks2) the following registers are also used. ? iic shift registers 0 to 2 (iic0 to iic2) ? slave address registers 0 to 2 (sva0 to sva2) (1) iic control registers 0 to 2 (iicc0 to iicc2) the iicc0 to iicc2 registers enable/disable i 2 c0n operations, set the wait timing, and set other i 2 c operations (n = 0 to 2). these registers can be read or written in 8-bit or 1-bit units. reset input clears these registers to 00h. caution in i 2 c00 to i 2 c02 bus mode, set the pmc3, pmc4, pmc9, pfc3, pfc4, pfc9, and pfce9 registers as follows. pin pmcn register pfcn register pfcen register p38/txda2/sda00 pmc3.pmc38 bit = 0 pfc3.pfc38 bit = 1 ? p39/rxda2/scl00 pmc3.pmc39 bit = 0 pfc3.pfc39 bit = 1 ? p40/sib0/sda01 pmc4.pmc40 bit = 0 pfc4.pfc40 bit = 1 ? p41/sob0/scl01 pmc4.pmc41 bit = 0 pfc4.pfc41 bit = 1 ? p90/a0/kr6/txda1/sda02 pmc9.pmc90 bit = 0 pfc9.pfc90 bit = 1 pfce9.pfce90 bit = 1 p91/a1/kr7/rxda1/scl02 pmc9.pmc91 bit = 0 pfc9.pfc91 bit = 1 pfce9.pfce91 bit = 1
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 454 (1/4) after reset: 00h r/w address: iicc0 fffffd82h, iicc1 fffffd92h, iicc2 fffffda2h <7> <6> <5> <4> <3> <2> <1> <0> iiccn iicen lreln wreln spien wtimn acken sttn sptn (n = 0 to 2) iicen specification of i 2 cn operation enable/disable 0 operation stopped. the iicsn register preset. internal operation stopped. 1 operation enabled. condition for clearing (iicen bit = 0) condition for setting (iicen bit = 1) ? cleared by instruction ? after reset ? set by instruction lreln exit from communications 0 normal operation 1 this exits from the current communication operation and sets standby mode. this setting is automatically cleared after being executed. its uses include cases in which a locally irrelevant extension code has been received. the scl0n and sda0n lines are set for high impedance. the sttn and sptn bits and the mstsn, excn, coin, trcn, ackdn, and stdn bits of iicsn register are cleared. the standby mode following exit from communications remains in effect until the following communication entry conditions are met. ? after a stop condition is detected, restart is in master mode. ? an address match or extension code reception occurs after the start condition. condition for clearing (lreln bit = 0) note condition for setting (lreln bit = 1) ? automatically cleared after execution ? after reset ? set by instruction wreln wait cancellation control 0 wait not canceled 1 wait canceled. this setting is automatically cleared after wait is canceled. condition for clearing (wreln bit = 0) note condition for setting (wreln bit = 1) ? automatically cleared after execution ? after reset ? set by instruction spien enable/disable generation of interrupt request when stop condition is detected 0 disabled 1 enabled condition for clearing (spien bit = 0) note condition for setting (spien bit = 1) ? cleared by instruction ? after reset ? set by instruction note this flag ? s signal is invalid when the iicen bit = 0.
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 455 (2/4) wtimn control of wait and interrupt request generation 0 interrupt request is generated at the eighth clock ? s falling edge. master mode: after output of eight clo cks, clock output is set to low level and wait is set. slave mode: after input of eight clo cks, the clock is set to low level and wait is set for master device. 1 interrupt request is generated at the ninth clock ? s falling edge. master mode: after output of nine clo cks, clock output is set to low level and wait is set. slave mode: after input of nine clo cks, the clock is set to low level and wait is set for master device. this bit ? s setting is invalid during an address transfer and is valid as the transfer is completed. in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. for a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an ack signal is issued. when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. condition for clearing (wtimn bit = 0) note condition for setting (wtimn bit = 1) ? cleared by instruction ? after reset ? set by instruction acken acknowledge control 0 acknowledgment disabled. 1 acknowledgment enabled. during the ninth clock period, the sda0n line is set to low level. however, the ack is invalid during address transfers and is valid when the excn bit = 1. condition for clearing (acken bit = 0) note condition for setting (acken bit = 1) note ? cleared by instruction ? after reset ? set by instruction note this flag ? s signal is invalid when the iicen bit = 0. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 456 (3/4) sttn start condition trigger 0 start condition is not generated. 1 when bus is released (in stop mode): generates a start condition (for starting as master). the sda0n line is changed from high level to low level and then the start condition is generated. next, after the rated amount of time has elapsed, the scl0n line is changed to low level. when bus is not used: if the communication reservation function is enabled (iicrsvn bit of iicfn register = 0) ? this trigger functions as a start condition reserve flag. when set, it releases the bus and then automatically generates a start condition. if the communication reservation function is disabled (iicrsvn = 1) ? the stcfn bit of the iicfn register is set. this trigger does not generate a start condition. in the wait state (when master device) generates a restart condition after releasing the wait. cautions concerning set timing for master reception: cannot be set during transfer. can be set only when the acken bit has been set to 0 and slave has been notified of final reception. for master transmission: a start condition cannot be generated normally during the ack period. set during the wait period. for slave: even when the communication reservation function is disabled (iicrsvn bit = 1), the communication reservation status is entered. ? cannot be set at the same time as the sptn bit condition for clearing (sttn bit = 0) condition for setting (sttn bit = 1) ? cleared by loss in arbitration ? cleared after start condition is generated by master device ? when the lreln bit = 1 ? when the iicen bit = 0 ? after reset ? set by instruction remarks 1. the sttn bit is 0 if it is read immediately after data setting. 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 457 (4/4) sptn stop condition trigger 0 stop condition is not generated. 1 stop condition is generated (termination of master device ? s transfer). after the sda0n line goes to low level, either set the scl0n line to high level or wait until it goes to high level. next, after the rated amount of time has elapsed, the sda0n line is changed from low level to high level and a stop condition is generated. cautions concerning set timing ? for master reception: cannot be set during transfer. can be set only when the acken bit has been set to 0 and during the wait period after slave has been notified of final reception. ? for master transmission: a stop condition cannot be generated normally during the ack period. set during the wait period. ? cannot be set at the same time as the sttn bit. ? the sptn bit can be set only when in master mode. note ? when the wtimn bit has been set to 0, if the sptn bit is set during the wait period that follows output of eight clocks, note that a stop c ondition will be generated during the high-level period of the ninth clock. when a ninth clock must be output, the wtimn bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the sptn bit should be set during the wait period that follows output of the ninth clock. condition for clearing (sptn bit = 0) condition for setting (sptn bit = 1) ? cleared by loss in arbitration ? automatically cleared after stop condition is detected ? when the lreln bit = 1 ? when the iicen bit = 0 ? after reset ? set by instruction note set the sptn bit only in master mode. however, when the iicrsvn bit is 0, the sptn bit must be set and a stop condition generated before the first stop condition is detected following the switch to the operation enabled status. for details, see 17.5 cautions . caution when the trcn bit = 1, the wreln bit is set during the ninth clock and wait is canceled, after which the trcn bit is cleared and the sda0n line is set to high impedance. remarks 1. the sptn bit is 0 if it is read immediately after data setting. 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 458 (2) iic status registers 0 to 2 (iics0 to iics2) the iics0 to iics2 registers indicate the status of the i 2 c0n bus (n = 0 to 2). these registers are read-only, 8-bit or 1-bit units. reset input clears these registers to 00h. (1/3) after reset: 00h r address: iiccs0 fffffd86h, iiccs1 fffffd96h, iiccs2 fffffda6h <7> <6> <5> <4> <3> <2> <1> <0> iicsn mstsn aldn excn coin trcn ackdn stdn spdn (n = 0 to 2) mstsn master device status 0 slave device status or communication standby status 1 master device communication status condition for clearing (mstsn bit = 0) condition for setting (mstsn bit = 1) ? when a stop condition is detected ? when the aldn bit = 1 ? cleared by the lreln bit = 1 ? when the iicen bit changes from 1 to 0 ? after reset ? when a start condition is generated aldn arbitration loss detection 0 this status means either that there was no arbitration or that the arbitration result was a ? win ? . 1 this status indicates the arbitration result was a ? loss ? . the mstsn bit is cleared. condition for clearing (aldn bit = 0) condition for setting (aldn bit = 1) ? automatically cleared after the iicsn register is read note ? when the iicen bit changes from 1 to 0 ? after reset ? when the arbitration result is a ? loss ? . excn detection of extension code reception 0 extension code was not received. 1 extension code was received. condition for clearing (excn bit = 0) condition for setting (excn bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lreln bit = 1 ? when the iicen bit changes from 1 to 0 ? after reset ? when the high-order four bits of the received address data is either ? 0000 ? or ? 1111 ? (set at the rising edge of the eighth clock). note this register is also cleared when a bit manipulation instruction is executed for bits other than the iicsn register.
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 459 (2/3) coin matching addresses detection 0 addresses do not match. 1 addresses match. condition for clearing (coin bit = 0) condition for setting (coin bit = 1) ? when a start condition is detected ? when a stop condition is detected ? cleared by the lreln bit = 1 ? when the iicen bit changes from 1 to 0 ? after reset ? when the received address matches the local address (svan register) (set at the rising edge of the eighth clock). trcn transmit/receive status detection 0 receive status (other than transmit status). the sda0n line is set for high impedance. 1 transmit status. the value in the so latch is enabled for output to the sda0n line (valid starting at the falling edge of the first byte ? s ninth clock). condition for clearing (trcn bit = 0) condition for setting (trcn bit = 1) ? when a stop condition is detected ? cleared by the lreln bit = 1 ? when the iicen bit changes from 1 to 0 ? cleared by the wreln bit = 1 note ? when the aldn bit changes from 0 to 1 ? after reset master ? when ? 1 ? is output to the first byte ? s lsb (transfer direction specification bit) slave ? when a start condition is detected when not used for communication master ? when a start condition is generated slave ? when ? 1 ? is input by the first byte ? s lsb (transfer direction specification bit) ackdn ack detection 0 ack was not detected. 1 ack was detected. condition for clearing (ackdn bit = 0) condition for setting (ackd bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte ? s first clock ? cleared by the lreln bit = 1 ? when the iicen bit changes from 1 to 0 ? after reset ? after the sda0n bit is set to low level at the rising edge of the scl0n pin ? s ninth clock note the trcn bit is cleared and sda0n line becomes high impedance when the wreln bit is set and the wait state is canceled at the ninth clock by the trcn bit = 1. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 460 (3/3) stdn start condition detection 0 start condition was not detected. 1 start condition was detected. this indicates that the address transfer period is in effect condition for clearing (stdn bit = 0) condition for setting (stdn bit = 1) ? when a stop condition is detected ? at the rising edge of the next byte ? s first clock following address transfer ? cleared by the lreln bit = 1 ? when the iicen bit changes from 1 to 0 ? after reset when a start condition is detected spdn stop condition detection 0 stop condition was not detected. 1 stop condition was detected. the master device ? s communication is terminated and the bus is released. condition for clearing (spdn bit = 0) condition for setting (spdn bit = 1) ? at the rising edge of the address transfer byte ? s first clock following setting of this bit and detection of a start condition ? when the iicen bit changes from 1 to 0 ? after reset when a stop condition is detected remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 461 (3) iic flag registers 0 to 2 (iicf0 to iicf2) the iicf0 to iicf2 registers set the i 2 c0n operation mode and indicate the i 2 c bus status. these registers can be read or written in 8-bit or 1-bit units. however, the stcfn and iicbsyn bits are read- only. iicrsvn enables/disables the communication reservation function (see 17.4 communication reservation ). the initial value of the iicbsyn bit is set by using the stcenn bit (see 17.5 cautions ). the iicrsvn and stcenn bits can be written only when operation of i 2 c0n is disabled (iicen bit of iiccn register = 0). after operation is enabled, iicfn can be read (n = 0 to 2). reset input clears these registers to 00h.
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 462 after reset: 00h r/w note address: iicf0 fffffd8ah, iicf1 fffffd9ah, iicf2 fffffdaah <7> <6> 5 4 3 2 <1> <0> iicfn stcfn iicbsyn 0000stcenniicrsvn (n = 0 to 2) stcfn sttn bit clear 0 start condition issued 1 the sttn bit cleared condition for clearing (stcfn bit = 0) condition for setting (stcfn bit = 1) ? cleared by the sttn bit of the iiccn register = 1 ? after reset ? clearance of the sttn bit when communication reservation disabled (iicrsvn bit = 1) iicbsyn i 2 c0n bus status 0 bus released status 1 bus communication status condition for clearing (iicbsyn bit = 0) condition for setting (iicbsyn bit = 1) ? when stop condition is detected ? after reset ? when start condition is detected ? by setting the iicen bit of the iiccn register when the stcenn bit = 0 stcenn initial start enable trigger 0 start conditions cannot be generated until a stop condition is detected following operation enable (iicen bit = 1). 1 start conditions can be generated even if a stop condition is not detected following operation enable (iicen bit = 1). condition for clearing (stcenn bit = 0) condition for setting (stcenn bit = 1) ? when start condition is detected ? after reset ? setting by instruction iicrsvn communication reservation function disable bit 0 communication reservation enabled 1 communication reservation disabled condition for clearing (iicrsvn bit = 0) condition for setting (iicrsvn bit = 1) ? clearing by instruction ? after reset ? setting by instruction note bits 6 and 7 are read-only bits. cautions 1. write the stcenn bit only when operation is stopped (iicen bit = 0). 2. when the stcenn bit = 1, the bus released status (iicbsyn bit = 0) is recognized regardless of the actual bus status immediately after the i 2 cn bus operation is enabled. therefore, to issue the first start condition (sttn bit = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications.
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 463 (4) iic clock select registers 0 to 2 (iiccl0 to iiccl2) the iiccl0 to iiccl2 registers set the transfer clock for the i 2 c0n bus. these registers can be read or written in 8-bit or 1-bit units. however, the cldn and dadn bits are read-only. the smcn, cln1, and cln0 bits are set by the combination of the clxn bit of the iicxn register and the ocksm1 and ocksm0 bits of the ocksm register (see 17.4 (6) i 2 c0n transfer clock setting method ) (n = 0 to 2, m = 0, 1). reset input clears these registers to 00h. after reset: 00h r/w note address: iiccl0 fffffd84h, iiccl1 fffffd94h, iiccl2 fffffda4h 76<5><4>321 0 iiccln 0 0 cldn dadn smcn dfcn cln1 cln0 (n = 0 to 2) cldn detection of scl0n pin level (valid only when iicen bit of iiccn register = 1) 0 the scl0n pin was detected at low level. 1 the scl0n pin was detected at high level. condition for clearing (cldn bit = 0) condition for setting (cldn bit = 1) ? when the scl0n pin is at low level ? when the iicen bit = 0 ? after reset ? when the scl0n pin is at high level dadn detection of sda0n pin level (valid only when iicen bit = 1) 0 the sda0n pin was detected at low level. 1 the sda0n pin was detected at high level. condition for clearing (dadn bit = 0) condition for setting (dad0n bit = 1) ? when the sda0n pin is at low level ? when the iicen bit = 0 ? after reset ? when the sda0n pin is at high level smcn operation mode switching 0 operates in standard mode. 1 operates in high-speed mode. dfcn digital filter operation control 0 digital filter off. 1 digital filter on. digital filter can be used only in high-speed mode. in high-speed mode, the transfer clock does not vary regardless of the dfcn bit setting (on/off). note bits 4 and 5 of iiccln are read-only bits. caution be sure to clear bits 7 and 6 of iiccln to 0.
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 464 (5) iic function expansion registers 0 to 2 (iicx0 to iicx2) the iicx0 to iics2 registers set i 2 c0n function expansion (valid only in the high-speed mode). these registers can be read or written in 8-bit or 1-bit units. however, the cldn and dadn bits are read-only. setting of the clxn bit is performed in combination with the smcn, cln1, and cln0 bits of the iiccln register and the ocksm1 and ocksm0 bits of the ocksm register (see 17.4 (6) i 2 c0n transfer clock setting method ) (m = 0, 1). reset input clears these registers to 00h. iicxn (n = 0 to 2) after reset: 00h r/w address: iicx0 fffffd85h, iicx1 fffffd95h, iicx2 fffffda5h 0 0 0 0 0 0 0 clxn < > (6) i 2 c0n transfer clock setting method the i 2 c0n transfer clock frequency (f scl ) is calculated using the following expression (n = 0 to 2). f scl = 1/(m t + t r + t f ) m = 12, 18, 24, 36, 44, 48, 54, 60, 66, 72, 86, 88, 96, 132, 172, 176, 198, 220, 258, 344 (see table 17-2 clock settings ). t: 1/f xx t r : scl0n pin rise time t f : scl0n pin fall time for example, the i 2 c0n transfer clock frequency (f scl ) when f xx = 19.2 mhz, m = 198, t r = 200 ns, and t f = 50 ns is calculated using following expression. f scl = 1/(198 52 ns + 200 ns + 50 ns) ? 94.7 khz m t + t r + t f m/2 t t f t r m/2 t scl0n scl0n inversion scl0n inversion scl0n inversion the clock to be selected can be set by the combination of the smcn, cln1, and cln0 bits of the iiccln register, the clxn bit of the iicxn register, and the ocksm1 and ocksm0 bits of the ocksm register (n = 0 to 2, m = 0, 1).
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 465 table 17-2. clock settings (1/2) iicx0 iiccl0 bit 0 bit 3 bit 1 bit 0 clx0 smc0 cl01 cl00 selection clock transfer clock settable main clock frequency (f xx ) range operating mode f xx (when ocks0 = 14h set) f xx /44 2.00 mhz f xx 4.19 mhz f xx /2 (when ocks0 = 10h set) f xx /88 4.00 mhz f xx 8.38 mhz f xx /3 (when ocks0 = 11h set) f xx /132 6.00 mhz f xx 12.57 mhz f xx /4 (when ocks0 = 12h set) f xx /176 8.00 mhz f xx 16.76 mhz 0000 f xx /5 (when ocks0 = 13h set) f xx /220 10.00 mhz f xx 20.00 mhz f xx (when ocks0 = 14h set) f xx /86 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks0 = 10h set) f xx /172 8.38 mhz f xx 16.76 mhz f xx /3 (when ocks0 = 11h set) f xx /258 12.57 mhz f xx 20.00 mhz 0001 f xx /4 (when ocks0 = 12h set) f xx /344 16.76 mhz f xx 20.00 mhz 0010 f xx note f xx /86 4.19 mhz f xx 8.38 mhz f xx (when ocks0 = 14h set) f xx /66 6.4 mhz f xx /2 (when ocks0 = 10h set) f xx /132 12.8 mhz 0011 f xx /3 (when ocks0 = 11h set) f xx /198 19.2 mhz standard mode (smc0 = 0) f xx (when ocks0 = 14h set) f xx /24 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks0 = 10h set) f xx /48 8.00 mhz f xx 16.76 mhz f xx /3 (when ocks0 = 11h set) f xx /72 12.00 mhz f xx 20.00 mhz 010 f xx /4 (when ocks0 = 12h set) f xx /96 16.00 mhz f xx 20.00 mhz 0110 f xx note f xx /24 4.00 mhz f xx 8.38 mhz f xx (when ocks0 = 14h set) f xx /18 6.4 mhz f xx /2 (when ocks0 = 10h set) f xx /36 12.8 mhz 0111 f xx /3 (when ocks0 = 11h set) f xx /54 19.2 mhz f xx (when ocks0 = 14h set) f xx /24 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks0 = 10h set) f xx /24 8.00 mhz f xx 8.38 mhz f xx /3 (when ocks0 = 11h set) f xx /36 12.00 mhz f xx 12.57 mhz f xx /4 (when ocks0 = 12h set) f xx /48 16.00 mhz f xx 16.67 mhz 110 f xx /5 (when ocks0 = 13h set) f xx /60 20.00 mhz 1110 f xx note f xx /12 4.00 mhz f xx 4.19 mhz high-speed mode (smc0 = 1) other than above setting prohibited ?? ? note since the selection clock is f xx regardless of the value set to the ocks0 register, set the ocks0 register = 00h (i 2 c division clock stopped status). remark : don ? t care
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 466 table 17-2. clock settings (2/2) iicx m iicclm bit 0 bit 3 bit 1 bit 0 clxm smcm clm1 clm0 selection clock transfer clock settable main clock frequency (f xx ) range operating mode f xx (when ocks1 = 14h set) f xx /44 2.00 mhz f xx 4.19 mhz f xx /2 (when ocks1 = 10h set) f xx /88 4.00 mhz f xx 8.38 mhz f xx /3 (when ocks1 = 11h set) f xx /132 6.00 mhz f xx 12.57 mhz f xx /4 (when ocks1 = 12h set) f xx /176 8.00 mhz f xx 16.76 mhz 0000 f xx /5 (when ocks1 = 13h set) f xx /220 10.00 mhz f xx 20.00 mhz f xx (when ocks1 = 14h set) f xx /86 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks1 = 10h set) f xx /172 8.38 mhz f xx 16.76 mhz f xx /3 (when ocks1 = 11h set) f xx /258 12.57 mhz f xx 20.00 mhz 0001 f xx /4 (when ocks1 = 12h set) f xx /344 16.76 mhz f xx 20.00 mhz 0010 f xx note f xx /86 4.19 mhz f xx 8.38 mhz f xx (when ocks1 = 14h set) f xx /66 6.4 mhz f xx /2 (when ocks1 = 10h set) f xx /132 12.8 mhz 0011 f xx /3 (when ocks1 = 11h set) f xx /198 19.2 mhz standard mode (smcm = 0) f xx (when ocks1 = 14h set) f xx /24 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks1 = 10h set) f xx /48 8.00 mhz f xx 16.76 mhz f xx /3 (when ocks1 = 11h set) f xx /72 12.00 mhz f xx 20.00 mhz 010 f xx /4 (when ocks1 = 12h set) f xx /96 16.00 mhz f xx 20.00 mhz 0110 f xx note f xx /24 4.00 mhz f xx 8.38 mhz f xx (when ocks1 = 14h set) f xx /18 6.4 mhz f xx /2 (when ocks1 = 10h set) f xx /36 12.8 mhz 0111 f xx /3 (when ocks1 = 11h set) f xx /54 19.2 mhz f xx (when ocks1 = 14h set) f xx /24 4.19 mhz f xx 8.38 mhz f xx /2 (when ocks1 = 10h set) f xx /24 8.00 mhz f xx 8.38 mhz f xx /3 (when ocks1 = 11h set) f xx /36 12.00 mhz f xx 12.57 mhz f xx /4 (when ocks1 = 12h set) f xx /48 16.00 mhz f xx 16.67 mhz 110 f xx /5 (when ocks1 = 13h set) f xx /60 20.00 mhz 1110 f xx note f xx /12 4.00 mhz f xx 4.19 mhz high-speed mode (smcm = 1) other than above setting prohibited ?? ? note since the selection clock is f xx regardless of the value set to the ocks1 register, set the ocks1 register = 00h (i 2 c division clock stopped status). remarks 1. m = 1, 2 2. : don ? t care
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 467 (7) iic division clock select registers 0, 1 (ocks0, ocks1) the ocks0 and ocks1 registers control the i 2 c0n division clock. these registers can be read or written in 8-bit or 1-bit units. reset input clears these registers to 00h. 0 ocksm (m = 0, 1) 00 ocksenm 0 ocksm2 ocksm1 ocksm0 after reset: 01h r/w address: ocks0 fffff340h, ocks1 fffff344h disable i 2 c division clock operation enable i 2 c division clock operation ocksenn 0 1 operation settings of i 2 c division clock ocksm1 0 0 1 1 0 ocksm0 0 1 0 1 0 selection of i 2 c division clock f xx /2 f xx /3 f xx /4 f xx /5 f xx ocksm2 0 0 0 0 1 (8) iic shift registers 0 to 2 (iic0 to iic2) the iic0 to iic2 registers are used for serial transmission/reception (shift operations) synchronized with the serial clock. these registers can be read or written in 8-bit units, but data should not be written to the iicn register during a data transfer (n = 0 to 2). reset input clears these registers to 00h. after reset: 00h r/w address: iic0 fffffd80h, iic1 fffffd90h, iic2 fffffda0h 76543210 iicn (n = 0 to 2) (9) slave address registers 0 to 2 (sva0 to sva2) the sva0 to sva2 registers hold the i 2 c bus ? s slave addresses. these registers can be read or written in 8-bit units, but bit 0 should be fixed to 0. reset input clears these registers to 00h. after reset: 00h r/w address: sva0 fffffd83h, sva1 fffffd93h, sva2 fffffda3h 76543210 svan 0 (n = 0 to 2)
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 468 17.5 i 2 c bus mode functions 17.5.1 pin configuration the serial clock pin (scl0n) and serial data bus pin (sda0n) are configured as follows (n = 0 to 2). scl0n ................this pin is used for serial clock input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. sda0n ................this pin is used for serial data input and output. this pin is an n-ch open-drain output for both master and slave devices. input is schmitt input. since outputs from the serial clock line and the serial data bus line are n-ch open-drain outputs, an external pull- up resistor is required. figure 17-6. pin configuration diagram portv dd scl0n sda0n scl0n sda0n portv dd clock output master device (clock input) data output data input (clock output) clock input data output data input slave device
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 469 17.6 i 2 c bus definitions and control methods the following section describes the i 2 c bus ? s serial data communication format and the signals used by the i 2 c bus. the transfer timing for the ? start condition ? , ? data ? , and ? stop condition ? output via the i 2 c bus ? s serial data bus is shown below. figure 17-7. i 2 c bus serial data transfer timing 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 scl0n sda0n start condition address r/w ack data data stop condition ack ack the master device outputs the start condition, slave address, and stop condition. the acknowledge signal (ack) can be output by either the master or slave device (normally, it is output by the device that receives 8-bit data). the serial clock (scl0n) is continuously output by the master device. however, in the slave device, the scl0n pin ? s low-level period can be extended and a wait can be inserted (n = 0 to 2). 17.6.1 start condition a start condition is met when the scl0n pin is high level and the sda0n pin changes from high level to low level. the start conditions for the scl0n and sda0n pins are signals that the master device outputs to the slave device when starting a serial transfer. the slave device includes hardware for detecting start conditions (n = 0 to 2). figure 17-8. start conditions h scl0n sda0n a start condition is output when the sttn bit of the iiccn register is set (1) after a stop condition has been detected (spdn bit of iicsn register = 1). when a start condition is detected, the stdn bit of the iicsn register is set (1) (n = 0 to 2).
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 470 17.6.2 addresses the 7 bits of data that follow the start condition are defined as an address. an address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via bus lines. therefore, each slave device connected via the bus lines must have a unique address. the slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in the svan register. if the address data matches the values of the svan register, the slave device is selected and communicates with the master device until the master device transmits a start condition or stop condition (n = 0 to 2). figure 17-9. address address scl0n 1 sda0n intiicn note 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w note the interrupt request signal (intiicn) is generated if a local address or extension code is received during slave device operation. remark n = 0 to 2 the slave address and the eighth bit, which specifies the transfer direction as described in 17.6.3 transfer direction specification below, are written together to iic shift register n (iicn) and then output. received addresses are written to the iicn register (n = 0 to 2). the slave address is assigned to the higher 7 bits of the iicn register.
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 471 17.6.3 transfer direction specification in addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. when this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device. when the transfer direction specification bit has a value of 1, it indicates that the master device is receiving data from a slave device. figure 17-10. transfer direction specification scl0n 1 sda0n intiicn 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w transfer direction specification note note the intiicn signal is generated if a local address or extension code is received during slave device operation. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 472 17.6.4 acknowledge signal (ack) the acknowledge signal (ack) is used by the transmitting and receiving devices to confirm serial data reception. the receiving device returns one ack signal for each 8 bits of data it receives. the transmitting device normally receives an ack signal after transmitting 8 bits of data. however, when the master device is the receiving device, it does not output an ack signal after receiving the final data to be transmitted. the transmitting device detects whether or not an ack signal is returned after it transmits 8 bits of data. when an ack signal is returned, the reception is judged as normal and processing continues. if the slave device does not return an ack signal, the master device outputs either a stop condition or a restart condition and then stops the current transmission. failure to return an ack signal may be caused by the following two factors. (a)reception was not performed normally. (b)the final data was received. when the receiving device sets the sda0n line to low level during the ninth clock, the ack signal becomes active (normal receive response). when the acken bit of the iiccn register is set to 1, automatic ack signal generation is enabled (n = 0 to 2). transmission of the eighth bit following the 7 address data bits causes the trcn bit of the iicsn register to be set. when this trcn bit ? s value is 0, it indicates receive mode. therefore, the acken bit should be set to 1. when the slave device is receiving (when trcn bit = 0), if the slave device does not need to receive any more data after receiving several bytes, clearing the acken bit to 0 will prevent the master device from starting transmission of the subsequent data. similarly, when the master device is receiving (when trcn bit = 0) and the subsequent data is not needed and when either a restart condition or a stop condition should therefore be output, clearing the acken bit to 0 will prevent the ack signal from being returned. this prevents the msb from being output via the sda0n line (i.e., stops transmission) during transmission from the slave device. figure 17-11. ack signal scl0n 1 sda0n 23456789 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack remark n = 0 to 2 when the local address is received, an ack signal is automatically output in synchronization with the falling edge of the scl0n pin ? s eighth clock regardless of the value of the acken bit. no ack signal is output if the received address is not a local address. the ack signal output method during data reception is based on the wait timing setting, as described below. when 8-clock wait is selected: the ack signal is output at the falling edge of the scl0n pin ? s eighth clock if the acken bit is set to 1 before wait cancellation. when 9-clock wait is selected: the ack signal is automatically output at the falling edge of the scl0n pin ? s eighth clock if the acken bit has already been set to 1.
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 473 17.6.5 stop condition when the scl0n pin is high level, changing the sda0n pin from low level to high level generates a stop condition (n = 0 to 2). a stop condition is a signal that the master device outputs to the slave device when serial transfer has been completed. the slave device includes hardware that detects stop conditions. figure 17-12. stop condition h scl0n sda0n remark n = 0 to 2 a stop condition is generated when the sptn bit of the iiccn register is set to 1. when the stop condition is detected, the spdn bit of the iicsn register is set to 1 and the intiicn register is generated when the spien of the iiccn signal is set to 1 (n = 0 to 2).
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 474 17.6.6 wait signal (wait) the wait signal (wait) is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). setting the scl0n pin to low level notifies the communication partner of the wait status. when the wait status has been canceled for both the master and slave devices, the next data transfer can begin (n = 0 to 2). figure 17-13. wait signal (1/2) (1) when master device has a nine-clock wait and slave device has an eight-clock wait (master: transmission, slave: reception, and acken bit of iiccn register = 1) scl0n 6 sda0n 78 9 123 scl0n iicn 6 h 78 123 d2 d1 d0 ack d7 d6 d5 9 iicn scl0n acken master master returns to high impedance but slave is in wait state (low level). wait after output of ninth clock. iicn data write (cancel wait) slave wait after output of eighth clock. ffh is written to iicn register or wreln bit of iiccn register is set to 1. transfer lines remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 475 figure 17-13. wait signal (2/2) (2) when master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and acken bit = 1) scl0n 6 sda0n 789 123 scl0n iicn 6 h 78 1 23 d2 d1 d0 ack d7 d6 d5 9 iicn scl0n acken master master and slave both wait after output of ninth clock. iicn data write (cancel wait) slave ffh is written to iicn register or wreln bit is set to 1. output according to previously set acken bit value transfer lines remark n = 0 to 2 a wait may be automatically generated depending on the setting of the wtimn bit of the iiccn register (n = 0 to 2). normally, when the wreln bit of the iiccn register is set to 1 or when ffh is written to the iicn register on the receiving side, the wait status is canceled and the transmitting side writes data to the iicn register to cancel the wait status. the master device can also cancel the wait status via either of the following methods. ? by setting the sttn bit of the iiccn register to 1 ? by setting the sptn bit of the iiccn register to 1
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 476 17.7 i 2 c interrupt request signals (intiicn) the following shows the value of the iicsn register at the intiicn interrupt request signal generation timing and at the intiicn signal timing (n = 0 to 2). 17.7.1 master device operation (1) start ~ address ~ data ~ data ~ stop (normal transmission/reception) <1> when wtimn bit = 0 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn register = 10xxx110b 2: iicsn register = 10xxx000b 3: iicsn register = 10xxx000b (wtimn bit = 1) 4: iicsn register = 10xxxx00b ? 5: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 10xxx110b 2: iicsn register = 10xxx100b 3: iicsn register = 10xxxx00b ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 477 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop (restart) <1> when wtimn bit = 0 sttn bit = 1 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iicsn register = 10xxx110b 2: iicsn register = 10xxx000b (wtimn bit = 1) 3: iicsn register = 10xxxx00b (wtimn bit = 0) 4: iicsn register = 10xxx110b (wtimn bit = 0) 5: iicsn register = 10xxx000b (wtimn bit = 1) 6: iicsn register = 10xxxx00b ? 7: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 sttn bit = 1 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn register = 10xxx110b 2: iicsn register = 10xxxx00b 3: iicsn register = 10xxx110b 4: iicsn register = 10xxxx00b ? 5: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 478 (3) start ~ code ~ data ~ data ~ stop (extension code transmission) <1> when wtimn bit = 0 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn register = 1010x110b 2: iicsn register = 1010x000b 3: iicsn register = 1010x000b (wtimn bit = 1) 4: iicsn register = 1010xx00b ? 5: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 1010x110b 2: iicsn register = 1010x100b 3: iicsn register = 1010xx00b ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 479 17.7.2 slave device operation (when receiving slave address data (matches with address)) (1) start ~ address ~ data ~ data ~ stop <1> when wtimn bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 0001x110b 2: iicsn register = 0001x000b 3: iicsn register = 0001x000b ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 0001x110b 2: iicsn register = 0001x100b 3: iicsn register = 0001xx00b ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 480 (2) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, match with address) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn register = 0001x110b 2: iicsn register = 0001x000b 3: iicsn register = 0001x110b 4: iicsn register = 0001x000b ? 5: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, match with address) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn register = 0001x110b 2: iicsn register = 0001xx00b 3: iicsn register = 0001x110b 4: iicsn register = 0001xx00b ? 5: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 481 (3) start ~ address ~ data ~ start ~ code ~ data ~ stop <1> when wtimn bit = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn register = 0001x110b 2: iicsn register = 0001x000b 3: iicsn register = 0010x010b 4: iicsn register = 0010x000b ? 5: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iicsn register = 0001x110b 2: iicsn register = 0001xx00b 3: iicsn register = 0010x010b 4: iicsn register = 0010x110b 5: iicsn register = 0010xx00b ? 6: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 482 (4) start ~ address ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 0001x110b 2: iicsn register = 0001x000b 3: iicsn register = 00000x10b ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 0001x110b 2: iicsn register = 0001xx00b 3: iicsn register = 00000x10b ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 483 17.7.3 slave device operation (when receiving extension code) (1) start ~ code ~ data ~ data ~ stop <1> when wtimn bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 0010x010b 2: iicsn register = 0010x000b 3: iicsn register = 0010x000b ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn register = 0010x010b 2: iicsn register = 0010x110b 3: iicsn register = 0010x100b 4: iicsn register = 0010xx00b ? 5: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 484 (2) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, match with address) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn register = 0010x010b 2: iicsn register = 0010x000b 3: iicsn register = 0001x110b 4: iicsn register = 0001x000b ? 5: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, match with address) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 ? 6 1: iicsn register = 0010x010b 2: iicsn register = 0010x110b 3: iicsn register = 0010xx00b 4: iicsn register = 0001x110b 5: iicsn register = 0001xx00b ? 6: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 485 (3) start ~ code ~ data ~ start ~ code ~ data ~ stop <1> when wtimn bit = 0 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn register = 0010x010b 2: iicsn register = 0010x000b 3: iicsn register = 0010x010b 4: iicsn register = 0010x000b ? 5: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, extension code reception) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 5 6 ? 7 1: iicsn register = 0010x010b 2: iicsn register = 0010x110b 3: iicsn register = 0010xx00b 4: iicsn register = 0010x010b 5: iicsn register = 0010x110b 6: iicsn register = 0010xx00b ? 7: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 486 (4) start ~ code ~ data ~ start ~ address ~ data ~ stop <1> when wtimn bit = 0 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 0010x010b 2: iicsn register = 0010x000b 3: iicsn register = 00000x10b ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 (after restart, mismatch with address (= not extension code)) st ad6 to ad0 rw ak d7 to d0 ak st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn register = 0010x010b 2: iicsn register = 0010x110b 3: iicsn register = 0010xx00b 4: iicsn register = 00000x10b ? 5: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 487 17.7.4 operation without communication (1) start ~ code ~ data ~ data ~ stop st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp ? 1 ? 1: iicsn register = 00000001b remarks 1. ? : generated only when spien bit = 1 2. n = 0 to 2 17.7.5 arbitration loss operation (operation as slave after arbitration loss) (1) when arbitration loss occurs during transmission of slave address data <1> when wtimn bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 0101x110b (example: when aldn bit is read during interrupt servicing) 2: iicsn register = 0001x000b 3: iicsn register = 0001x000b ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 0101x110b (example: when aldn bit is read during interrupt servicing) 2: iicsn register = 0001x100b 3: iicsn register = 0001xx00b ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 488 (2) when arbitration loss occurs during transmission of extension code <1> when wtimn bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) 2: iicsn register = 0010x000b 3: iicsn register = 0010x000b ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 3 4 ? 5 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) 2: iicsn register = 0010x110b 3: iicsn register = 0010x100b 4: iicsn register = 0010xx00b ? 5: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 489 17.7.6 operation when arbitration loss occurs (no communication after arbitration loss) (1) when arbitration loss occurs during transmission of slave address data st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iicsn register = 01000110b (example: when aldn bit is read during interrupt servicing) ? 2: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 2. n = 0 to 2 (2) when arbitration loss occurs during transmission of extension code st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 ? 2 1: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) iiccn ? s lreln bit is set to 1 by software ? 2: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 490 (3) when arbitration loss occurs during data transfer <1> when wtimn bit = 0 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iicsn register = 10001110b 2: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) ? 3: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 2. n = 0 to 2 <2> when wtimn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak sp 1 2 ? 3 1: iicsn register = 10001110b 2: iicsn register = 01000100b (example: when aldn bit is read during interrupt servicing) ? 3: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 491 (4) when arbitration loss occurs due to restart condition during data transfer <1> not extension code (example: mismatches with address) st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn register = 1000x110b 2: iicsn register = 01000110b (example: when aldn bit is read during interrupt servicing) ? 3: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. dn = d6 to d0 n = 0 to 2 <2> extension code st ad6 to ad0 rw ak d7 to dn st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn register = 1000x110b 2: iicsn register = 0110x010b (example: when aldn bit is read during interrupt servicing) iiccn ? s lreln bit is set to 1 by software ? 3: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. dn = d6 to d0 n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 492 (5) when arbitration loss occurs due to stop condition during data transfer st ad6 to ad0 rw ak d7 to dn sp 1 ? 2 1: iicsn register = 1000x110b ? 2: iicsn register = 01000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. dn = d6 to d0 n = 0 to 2 (6) when arbitration loss occurs due to low-level of sda0n pin when attempting to generate a restart condition when wtimn bit = 1 sttn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 1000x110b 2: iicsn register = 1000xx00b 3: iicsn register = 01000100b (example: when aldn bit is read during interrupt servicing) ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 493 (7) when arbitration loss occurs due to a stop condition when attempting to generate a restart condition when wtimn bit = 1 sttn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak sp 1 2 ? 3 1: iicsn register = 1000x110b 2: iicsn register = 1000xx00b ? 3: iicsn register = 01000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2 (8) when arbitration loss occurs due to low-level of sda0n pin when attempting to generate a stop condition when wtimn bit = 1 sptn bit = 1 st ad6 to ad0 rw ak d7 to d0 ak d7 to d0 ak d7 to d0 ak sp 1 2 3 ? 4 1: iicsn register = 1000x110b 2: iicsn register = 1000xx00b 3: iicsn register = 01000000b (example: when aldn bit is read during interrupt servicing) ? 4: iicsn register = 00000001b remarks 1. : always generated ? : generated only when spien bit = 1 x: don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 494 17.8 interrupt request signal (intiicn) generation timing and wait control the setting of the wtimn bit of the iiccn register determines the timing by which the intiicn register is generated and the corresponding wait control, as shown below (n = 0 to 2). table 17-3. intiicn generation timing and wait control during slave device operation during master device operation wtimn bit address data reception data transmission address data reception data transmission 09 notes 1, 2 8 note 2 8 note 2 988 19 notes 1, 2 9 note 2 9 note 2 999 notes 1. the slave device ? s intiicn signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to the svan register. at this point, the ack signal is output regardless of the value set to the acken bit of the iiccn register. for a slave device that has received an extension code, the intiicn signal occurs at the falling edge of the eighth clock. 2. if the received address does not match the contents of the svan register, neither the intiicn signal nor a wait occurs. remarks 1. the numbers in the table indicate the number of the serial clock ? s clock signals. interrupt requests and wait control are both synchronized with the falling edge of these clock signals. 2. n = 0 to 2 (1) during address transmission/reception ? slave device operation: interrupt and wait timing are determined regardless of the wtimn bit. ? master device operation: interrupt and wait timing occur at the falling edge of the ninth clock regardless of the wtimn bit. (2) during data reception ? master/slave device operation: interrupt and wait timing are determined according to the wtimn bit. (3) during data transmission ? master/slave device operation: interrupt and wait timing are determined according to the wtimn bit. (4) wait cancellation method the four wait cancellation methods are as follows. ? by setting the wreln bit of the iiccn register to 1 ? by writing to the iicn register ? by start condition setting (sttn bit of iiccn register = 1) ? by step condition setting (sptn bit of iiccn register = 1) when an 8-clock wait has been selected (wtimn bit = 0), the output level of the ack signal must be determined prior to wait cancellation. remark n = 0 to 2 (5) stop condition detection the intiicn signal is generated when a stop condition is detected. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 495 17.9 address match detection method in i 2 c bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. address match detection is performed automatically by hardware. the intiicn signal occurs when a local address has been set to the svan register and when the address set to the svan register matches the slave address sent by the master device, or when an extension code has been received (n = 0 to 2). 17.10 error detection in i 2 c bus mode, the status of the serial data bus pin (sda0n) during data transmission is captured by the iicn register of the transmitting device, so the data of the iicn register prior to transmission can be compared with the transmitted iicn data to enable detection of transmission errors. a transmission error is judged as having occurred when the compared data values do not match (n = 0 to 2). 17.11 extension code (1) when the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (excn bit of iicsn register) is set for extension code reception and an interrupt request signal (intiicn) is issued at the falling edge of the eighth clock (n = 0 to 2). the local address stored in the svan register is not affected. (2) if 11110xx0 is set to the svan register by a 10-bit address transfer and 11110xx0 is transferred from the master device, the results are as follows. note that the intiicn signal occurs at the falling edge of the eighth clock (n = 0 to 2) ? higher four bits of data match: excn bit = 1 ? seven bits of data match: coin bit of iicsn register = 1 (3) since the processing after the interrupt request signal occurs differs according to the data that follows the extension code, such processing is performed by software. for example, when operation as a slave is not desired after the extension code is received, set the lreln bit of the iiccn register to 1 and the cpu will enter the next communication wait state. table 17-4. extension code bit definitions slave address r/w bit description 0000 000 0 general call address 0000 000 1 start byte 0000 001 x cbus address 0000 010 x address that is reserved for different bus format 1111 0xx x 10-bit slave address specification
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 496 17.12 arbitration when several master devices simultaneously output a start condition (when iiccn.sttn bit is set to 1 before iicsn.stdn bit is set to 1), communication among the master devices is performed while the number of clocks are being adjusted until the data differs. this kind of operation is called arbitration (n = 0 to 2). when one of the master devices loses in arbitration, an arbitration loss flag (aldn bit of iicsn register) is set via the timing by which the arbitration loss occurred, and the scl0n and sda0n lines are both set to high impedance, which releases the bus (n = 0 to 2). the arbitration loss is detected based on the timing of the next interrupt request signal (the eighth or ninth clock, when a stop condition is detected, etc.) and the aldn bit = 1 setting that has been made by software (n = 0 to 2). for details of interrupt request timing, see 17.7 i 2 c interrupt request signals (intiicn) . figure 17-14. arbitration timing example master 1 master 2 transfer lines scl0n sda0n scl0n sda0n scl0n sda0n master 1 loses arbitration hi-z hi-z remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 497 table 17-5. status during arbitration and interrupt request signal generation timing status during arbitration interrupt request generation timing during address transmission read/write data after address transmission during extension code transmission read/write data after extension code transmission during data transmission during ack signal transfer period after data reception when restart condition is detected during data transfer at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected during data transfer when stop condition is output (when iiccn.spien bit = 1) note 2 when the sda0n pin is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 when stop condition is detected while attempting to output a restart condition when stop condition is output (when iiccn.spien bit = 1) note 2 when the dsa0n pin is at low level while attempting to output a stop condition when the scl0n pin is at low level while attempting to output a restart condition at falling edge of eighth or ninth clock following byte transfer note 1 notes 1. when the wtimn bit of the iiccn register = 1, an interrupt request signal occurs at the falling edge of the ninth clock. when the wtimn bit = 0 and the extension code ? s slave address is received, an interrupt request signal occurs at the falling edge of the eighth clock (n = 0 to 2). 2. when there is a possibility that arbitration will occur, set the spien bit = 1 for master device operation (n = 0 to 2). 17.13 wakeup function the i 2 c bus slave function is a function that generates an interrupt request signal (intiicn) when a local address and extension code have been received. this function makes processing more efficient by preventing unnecessary interrupt request signals from occurring when addresses do not match. when a start condition is detected, wake-up standby mode is set. this wake-up standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has output a start condition) to a slave device. however, when a stop condition is detected, the spien bit of the iiccn register is set regardless of the wake up function, and this determines whether interrupt request signals are enabled or disabled (n = 0 to 2).
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 498 17.14 communication reservation 17.14.1 when communication reservation function is enabled (iicrsvn bit of iicfn register = 0) to start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. there are two modes under which the bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack signal is not returned and the bus was released when the lreln bit of the iiccn register was set to ? 1 ? ) (n = 0 to 2). if the sttn bit of the iiccn register is set while the bus is not used, a start condition is automatically generated and wait status is set after the bus is released (after a stop condition is detected). when the bus release is detected (when a stop condition is detected), writing to the iicn register causes the master ? s address transfer to start. at this point, the spien bit of the iiccn register should be set (n = 0 to 2). when sttn has been set, the operation mode (as start condition or as communication reservation) is determined according to the bus status (n = 0 to 2). if the bus has been released.............................................a start condition is generated if the bus has not been released (standby mode) .............communication reservation to detect which operation mode has been determined for the sttn bit, set the sttn bit, wait for the wait period, then check the mstsn bit of the iicsn register) (n = 0 to 2). the wait periods, which should be set via software, are listed in table 17-6. these wait periods can be set by the smcn, cln1, and cln0 bits of the iiccln register and the clxn bit of the iicxn register (n = 0 to 2).
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 499 table 17-6. wait periods selection clock clxn smcn cln1 cln0 wait period f xx (when ocksm = 14h set) 000026 clocks f xx /2 (when ocksm = 10h set) 000052 clocks f xx /3 (when ocksm = 11h set) 000078 clocks f xx /4 (when ocksm = 12h set) 0000 104 clocks f xx /5 (when ocksm = 13h set) 0000 130 clocks f xx (when ocksm = 14h set) 000147 clocks f xx /2 (when ocksm = 10h set) 000194 clocks f xx /3 (when ocksm = 11h set) 0001 141 clocks f xx /4 (when ocksm = 12h set) 0001 188 clocks f xx 001047 clocks f xx (when ocksm = 14h set) 0 1 0 16 clocks f xx /2 (when ocksm = 10h set) 0 1 0 32 clocks f xx /3 (when ocksm = 11h set) 0 1 0 48 clocks f xx /4 (when ocksm = 12h set) 0 1 0 64 clocks f xx 011016 clocks f xx (when ocksm = 14h set) 1 1 0 10 clocks f xx /2 (when ocksm = 10h set) 1 1 0 20 clocks f xx /3 (when ocksm = 11h set) 1 1 0 30 clocks f xx /4 (when ocksm = 12h set) 1 1 0 40 clocks f xx 111010 clocks remarks 1. n = 0 to 2 m = 0, 1 2. = don ? t care the communication reservation timing is shown below.
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 500 figure 17-15. communication reservation timing 2 1 3456 2 1 3456 789 scl0n sda0n program processing hardware processing write to iicn set spdn and intiicn sttn =1 communication reservation set stdn output by master with bus access iicn: iic shift register n sttn: bit 1 of iic control register n (iiccn) stdn: bit 1 of iic status register n (iicsn) spdn: bit 0 of iic status register n (iicsn) remark n = 0 to 2 communication reservations are accepted via the following timing. after the stdn bit of the iicsn register is set to 1, a communication reservation can be made by setting the sttn bit of the iiccn register to 1 before a stop condition is detected (n = 0 to 2). figure 17-16. timing for accepting communication reservations scl0n sda0n stdn spdn standby mode remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 501 the communication reservation flowchart is illustrated below. figure 17-17. communication reservation flowchart di set1 sttn define communication reservation wait cancel communication reservation no yes iicn xxh ei mstsn = 0? (communication reservation) note (generate start condition) sets sttn bit (communication reservation). secures wait period set by software (see table 17-16 ). confirmation of communication reservation clears user flag. iicn write operation defines that communication reservation is in effect (defines and sets user flag to any part of ram). note the communication reservation operation executes a write to the iicn register when a stop condition interrupt request occurs. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 502 17.14.2 when communication reservation function is disabled (iicrsvn bit of iicfn register = 1) when the sttn bit of the iiccn register is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. the following two statuses are included in the status where bus is not used. ? when arbitration results in neither master nor slave operation ? when an extension code is received and slave operation is disabled (ack signal is not returned and the bus was released when the lreln bit of the iiccn register was set to 1) (n = 0 to 2). to confirm whether the start condition was generated or request was rejected, check the stcfn flag of the iicfn register. the time shown in table 17-7 is required until the stcfn flag is set after setting the sttn bit = 1. therefore, secure the time by software. table 17-7. wait periods ocksenn ocksn1 ocksn0 cln1 cln0 wait period 1000 6 clocks 1010 9 clocks 1100 12 clocks 1110 15 clocks 00010 3 clocks remarks 1. : don ? t care 2. n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 503 17.15 cautions (1) when stcenn bit of iicfn register = 0 immediately after the i 2 c0n operation is enabled, the bus communication status (iicbsyn bit of iicfn register = 1) is recognized regardless of the actual bus status. to execute master communication in the status where a stop condition has not been detected, generate a stop condition and then release the bus before starting the master communication. use the following sequence for generating a stop condition. <1> set the iiccln register. <2> set the iicen bit of the iiccn register. <3> set the sptn bit of the iiccn register. (2) when stcenn bit of iicfn register = 1 immediately after i 2 c0n operation is enabled, the bus released status (iicbsyn bit = 0) is recognized regardless of the actual bus status. to issue the first start condition (sttn bit of iiccn register = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 504 17.16 communication operations 17.16.1 master operation 1 the following shows the flowchart for master communication when the communication reservation function is enabled (iicrsvn bit of iicfn register = 0) and the master operation is started after a stop condition is detected (stcenn bit of iicfn register = 0).
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 505 figure 17-18. master operation flowchart (1) iiccn h iicen = spien = wtimn = 1 iiccln h select transfer clock sttn = 1 start acken = 0 no no no no no no no no no yes yes yes yes yes yes yes intiicn = 1? wtimn = 0 acken = 1 intiicn = 1? intiicn = 1? trcn = 1? ackdn = 1? mstsn = 1? yes no intiicn = 1? intiicn = 1? ackdn = 1? wreln = 1 start reception yes (stop condition detection) wait wait time is secured by software (see table 17-6 ) yes (start condition generation) communication reservation start iicn write transfer stop condition detection, start condition generation by communication reservation generate stop condition (no slave with matching address) no (receive) address transfer completion yes (transmit) end start iicn write transfer data processing transfer completed? generate stop condition sptn = 1 (restart) end transfer completed? data processing remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 506 17.16.2 master operation 2 the following shows the flowchart for master communication when the communication reservation function is disabled (iicrsvn bit = 1) and the master operation is started without detecting a stop condition (stcenn bit = 1). figure 17-19. master operation flowchart (2) no (receive) iiccln h iicfn h iiccn h iicen = spien = wtimn = 1 sttn = 1 start no yes iicbsyn = 0? no yes wtimn = 0 acken = 1 wreln = 1 start reception acken = 0 sptn = 1 generate stop condition no yes yes (transmit) intiicn = 1? no yes yes intiicn = 1? no yes intiicn = 1? no yes ackdn = 1? no yes no ackdn = 1? trcn = 1? stcfn = 0? end transfer clock selection iicfn register setting iiccn register initial setting wait time is secured by software (see table 17-7 ) insert wait start iicn write transfer stop master communication master communication is stopped because bus is occupied yes (address transfer completion) start iicn write transfer generate stop condition (no slave with matching address) end data processing data processing reception completed? transfer completed? (restart) remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 507 17.16.3 slave operation the following shows the flowchart for slave communication. figure 17-20. slave operation flowchart iiccn h iicen = 1 wreln = 1 start reception start acken = 0 lreln = 1 no yes no no no no no no yes no yes yes yes start (restart detection) yes yes wtimn = 0 acken = 1 intiicn = 1? yes intiicn = 1? wtimn = 1 start iicn write transfer intiicn = 1? excn = 1? coin = 1? trcn = 1? ackdn = 1? start or stop transfer completed? communicate? no (receive) yes (transmit) data processing data processing end stop (stop condition detection) remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 508 17.17 timing of data communication when using i 2 c bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. after outputting the slave address, the master device transmits the trcn bit of the iicsn register, which specifies the data transfer direction, and then starts serial communication with the slave device. the shift operation of the iicn register is synchronized with the falling edge of the serial clock pin (scl0n). the transmit data is transferred to the so latch and is output (msb first) via the sda0n pin. data input via the sda0n pin is captured by the iicn register at the rising edge of the scl0n pin. the data communication timing is shown below. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 509 figure 17-21. example of master to slave communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l l l h h h l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 123456789 4 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 w ack d4 d5 d6 d7 iicn address iicn data iicn ffh transmit start condition receive (when excn = 1) note note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 510 figure 17-21. example of master to slave communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h l l l l l l h h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 1 9 8 23456789 3 2 1 d7 d0 d6 d5 d4 d3 d2 d1 d0 d5 d6 d7 iicn data iicn ffh note iicn ffh note iicn data transmit receive note note note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 511 figure 17-21. example of master to slave communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l l h h h l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn data iicn address iicn ffh note iicn ffh note stop condition start condition transmit note note (when spien = 1) receive (when spien = 1) note to cancel slave wait, write ffh to iicn or set wreln. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 512 figure 17-22. example of slave to master communication (when 9-clock wait is selected for both master and slave) (1/3) (a) start condition ~ address iicn ackdn stdn spdn wtimn h h l l h h l acken mstsn sttn l l sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 123456789 4 56 3 2 1 ad6 ad5 ad4 ad3 ad2 ad1 ad0 r d4 d3 d2 d5 d6 d7 iicn address iicn ffh note note iicn data start condition note to cancel master wait, write ffh to iicn or set wreln. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 513 figure 17-22. example of slave to master communication (when 9-clock wait is selected for both master and slave) (2/3) (b) data iicn ackdn stdn spdn wtimn h h h l l l l l l h h h l l l l l acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 1 89 23456789 3 2 1 d7 d0 ack d6 d5 d4 d3 d2 d1 d0 ack d5 d6 d7 note note receive transmit iicn data iicn data iicn ffh note iicn ffh note note to cancel master wait, write ffh to iicn or set wreln. remark n = 0 to 2
chapter 17 i 2 c bus preliminary user ? s manual u16541ej1v0um 514 figure 17-22. example of slave to master communication (when 9-clock wait is selected for both master and slave) (3/3) (c) stop condition iicn ackdn stdn spdn wtimn h h l l l h h acken mstsn sttn sptn wreln intiicn trcn iicn ackdn stdn spdn wtimn acken mstsn sttn sptn wreln intiicn trcn scl0n sda0n processing by master device transfer lines processing by slave device 123456789 2 1 d7 d6 d5 d4 d3 d2 d1 d0 ad5 ad6 iicn address iicn ffh note note iicn data stop condition start condition (when spien = 1) n- ack (when spien = 1) note to cancel master wait, write ffh to iicn or set wreln. remark n = 0 to 2
preliminary user?s manual u16541ej1v0um 515 chapter 18 iebus controller iebus (inter equipment bus) is a small-scale digital data transfer system that transfers data between units. to implement iebus with the v850es/sg2, an external iebus driver and receiver are necessary because they are not provided. the internal iebus controller of the v850es/sg2 is of negative logic. the following models of the v850es/sg2 have an on-chip iebus controller. ? pd703270, 703270y, 703271, 703271y, 703272, 703272y, 703273, 703273y, 70f3271, 70f3271y, 70f3273, 70f3273y 18.1 functions 18.1.1 communication protocol of iebus the communication protocol of the iebus is as follows. (1) multi-task mode all the units connected to the iebus can transfer data to the other units. (2) broadcasting communication function communication between one unit and multiple units can be performed as follows. ? group-unit broadcast communication: broadcast communication to group units ? all-unit broadcast communication: broadcast communication to all units. (3) effective transfer rate the effective transfer rate is in mode 1 or mode 2 (the v850es/sg2 does not support mode 0 for the effective transfer rate). ? mode 1: approx. 17 kbps ? mode 2: approx. 26 kbps caution different modes must not be mixed on one iebus. (4) communication mode data transfer is executed in half-duplex asynchronous communication mode. (5) access control: csma/cd (carrier sense multiple access with collision detection) the priority of the iebus is as follows: <1> broadcast communication takes precedence over individual communication (communication from one unit to another). <2> the lower master address takes precedence. (6) communication scale the communication scale of iebus is as follows. ? number of units: 50 max. ? cable length: 150 m max. (when twisted pair cable is used) caution the communication scale in an actual system differs depending on the characteristics of the cables, etc., constituting the iebus driver/receiver and iebus.
chapter 18 iebus controller preliminary user?s manual u16541ej1v0um 516 18.1.2 determination of bus mastership (arbitration) an operation to occupy the bus is performed when a unit connected to the iebus controls the other units. this operation is called arbitration. when two or more units simultaneously start transmission, arbitration is used to grant one of the units the permission to occupy the bus. because only one unit is granted the bus mastership as a result of arbitration, the priority conditions of the bus are predetermined as follows. caution the bus mastership is released if communication is aborted. (1) priority by communication type broadcast communication (communication from one unit to multiple units) takes precedence over normal communication (communication from one unit to another). (2) priority by master address if the communication type is the same, communication with the lower master address takes precedence. a master address consists of 12 bits, with unit 000h having the highest priority and unit fffh having the lowest priority. 18.1.3 communication mode the iebus has three communication modes each having a different transfer rate. the v850es/sg2 supports communication modes 1 and 2. the transfer rate and the maximum number of transfer bytes in one communication frame in communication modes 1 and 2 are as shown in table 18-1. table 18-1. transfer rate and maximum number of transfer bytes in each communication mode communication mode maximum number of transfer bytes (bytes/frame) effective transfer rate (kbps) note 1 32 approx. 17 2 128 approx. 26 note the effective transfer rate when the maximum number of transfer bytes is transmitted. select the communication mode for each unit connected to the iebus before starting communication. if the communication mode of the master unit and that of the partner unit (slave unit) are not the same, communication is not correctly executed. 18.1.4 communication address with the iebus, each unit is assigned a specific 12-bit address. this communication address consists of the following identification numbers. ? higher 4 bits: group number (number to identify the group to which each unit belongs) ? lower 8 bits: unit number (number to identify each unit in a group)
chapter 18 iebus controller preliminary user?s manual u16541ej1v0um 517 18.1.5 broadcast communication normally, transmission or reception is performed between the master unit and its partner slave unit on a one-to- one basis. during broadcast communication, however, two or more slave units exist and the master unit executes transmission to these slave units. because two or more slave units exist, the nack signal is returned by the communicating slave unit as an acknowledge bit. whether broadcast communication or normal communication is to be executed is selected by the broadcast bit (for this bit, refer to 18.1.6 (2) broadcast bit ). broadcast communication is classified into two types: group-unit broadcast communication and all-unit broadcast communication. group-unit broadcast and all-unit broadcast are identified by the value of the slave address (for the slave address, refer to 18.1.6 (4) slave address field ). (1) group-unit broadcast communication broadcast communication is performed to the units in a group identified by the group number indicated by the higher 4 bits of the communication address. (2) all-unit broadcast communication broadcast communication is performed to all the units, regardless of the value of the group number. 18.1.6 transfer format of iebus figure 18-1 shows the transfer signal format of the iebus. figure 18-1. iebus transfer signal format header master address field slave address field control field telegraph length field data field start bit broad- cast bit master address bit p frame format slave address bit pa control bit pa tele- graph length bit pa data bit pa data bit pa remarks 1. p: parity bit a: acknowledge (ack/nack) bit 2. the master unit ignores the acknowledge bit during broadcast communication. (1) start bit the start bit is a signal that informs the other units of the start of data transfer. the unit that is to start data transfer outputs a high-level signal (start bit) from the ietx pin for a specific time, and then starts outputting the broadcast bit. if another unit has already output its start bit when one unit is to output the start bit, this unit does not output the start bit but waits for completion of output of the start bit by the other unit. when the output of the start bit by the other unit is complete, the unit starts outputting the broadcast bit in synchronization with the completion of the start bit output by the other unit. the units other than the one that has started communication detect this start bit, and enter the reception status.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 518 (2) broadcast bit this bit indicates whether the master selects one slave (individual communication) or multiple slaves (broadcast communication) as the other party of communication. when the broadcast bit is 0, it indicates broadcast communication; when it is 1, individual communication is indicated. broadcast communication is classified into two types: group-unit communication and all-unit communication. these communication types are identified by the value of the slave address (for the slave address, refer to 18.1.6 (4) slave address field ). because two or more slave units exist as a partner slave unit of communication in the case of broadcast communication, the nack signal is returned as an acknowledge bit in each field subsequent to the master address field. if two or more units start transmitting a communication frame at the same time, broadcast communication takes precedence over individual communication, and wins in arbitration. if one unit occupies the bus as the master, the value set to the broadcast request flag (bcr.allrq bit) is output. (3) master address field the master address field is output by the master to inform a slave of the master ? s address. the configuration of the master address field is as shown in figure 18-2. if two or more units start transmitting the broadcast bit at the same time, the master address field makes a judgment of arbitration. the master address field compares the data it outputs with the data on the bus each time it has output one bit. if the master address output by the master address field is found to be different from the data on the bus as a result of comparison, it is assumed that the master has lost in arbitration. as a result, the master stops transmission and enters the reception status. because the iebus is configured of wired and, the unit having the minimum master address of the units participating in arbitration (arbitration masters) wins in arbitration. after a 12-bit master address has been output, only one unit remains in the transmission status as one master unit. next, this master unit outputs a parity bit, determines the master address of other unit, and starts outputting a slave address field. if one unit occupies the bus as the master, the address set by the uar register is output. figure 18-2. master address field master address field master address (12 bits) msb lsb parity
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 519 (4) slave address field the master outputs the address of the unit with which it is to communicate. figure 18-3 shows the configuration of the slave address field. a parity bit is output after a 12-bit slave address has been transmitted in order to prevent a wrong slave address from being received by mistake. next, the master unit detects an ack signal from the slave unit to confirm that the slave unit exists on the bus. when the master has detected the ack signal, it starts outputting the control field. during broadcast communication, however, the master does not confirm the acknowledge bit but starts outputting the control field. the slave unit outputs the ack signal if its slave address matches and if the slave detects that the parities of both the master address and slave address are even. the slave unit judges that the master address or slave address has not been correctly received and outputs the nack signal if the parities are odd. at this time, the master unit is in the standby (monitor) status, and communication ends. during broadcast communication, the slave address is used to identify group-unit broadcast or all-unit broadcast, as follows:. if slave address is fffh: all-unit broadcast communication if slave address is other than fffh: group-unit broadcast communication remark the group no. during group-unit broadcasting communication is the value of the higher 4 bits of the slave address. if one unit occupies the bus as the master, the address set by the sar register is output. figure 18-3. slave address field slave address field unit no. msb lsb ack parity slave address (12 bits) group no. (5) control field the master outputs the operation it requires the slave to perform, by using this field. the configuration of the control field is as shown in figure 18-4. if the parity following the control bit is even and if the slave unit can execute the function required by the master unit, the slave unit outputs an ack signal and starts outputting the telegraph length field. if the slave unit cannot execute the function required by the master unit even if the parity is even, or if the parity is odd, the slave unit outputs the nack signal, and returns to the standby (monitor) status. the master unit starts outputting the telegraph field after detecting the ack signal. if the master can detect the nack signal, the master unit enters the standby status, and communication ends. during broadcast communication, however, the master unit does not confirm the acknowledge bit, and starts outputting the telegraph length field. the contents of the control bits are shown below.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 520 table 18-2. contents of control bits bit 3 note 1 bit 2 bit 1 bit 0 function 0 0 0 0 read slave status 0 0 0 1 undefined 0 0 1 0 undefined 0 0 1 1 read data and lock note 2 0 1 0 0 read lock address (lower 8 bits) note 3 0 1 0 1 read lock address (higher 4 bits) note 3 0 1 1 0 read slave status and unlock note 2 0 1 1 1 read data 1 0 0 0 undefined 1 0 0 1 undefined 1 0 1 0 write command and lock note 2 1 0 1 1 write data and lock note 2 1 1 0 0 undefined 1 1 0 1 undefined 1110write command 1111write data notes 1. the telegraph length bit of the telegraph length field and data transfer direction of the data field change as follows depending on the value of bit 3 (msb). if bit 3 is ? 1 ? : transfer from master unit to slave unit if bit 3 is ? 0 ? : transfer from slave unit to master unit 2. this is a control bit that specifies locking or unlocking (refer to 18.1.7 (4) locking and unlocking ). 3. the lock address is transferred in 1-byte (8-bit) units and is configured as follows: msb lower 8 bits undefined higher 4 bits control bit: 4h control bit: 5h lsb
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 521 if the control bit received from the master unit is not as shown in table 18-3, the unit locked by the master unit rejects acknowledging the control bit, and outputs the nack signal. table 18-3. control field for locked slave unit bit 3 note 1 bit 2 bit 1 bit 0 function 0 0 0 0 read slave status 0 1 0 0 read lock address (lower 8 bits) 0 0 0 1 read lock address (higher 4 bits) moreover, units for which lock is not set by the master unit reject acknowledgment and output a nack signal when the control data shown in table 18-4 is acknowledged. table 18-4. control field for unlocked slave unit bit 3 bit 2 bit 1 bit 0 function 0 1 0 0 lock address read (lower 8 bits) 0 1 0 1 lock address read (higher 4 bits) if one unit occupies the bus as the master, the value set to the cdr register is output. figure 18-4. control field msb lsb ack parity control bit (4 bits) control field
table 18-5. acknowledge signal output condition of control field (a) if received control data is ah, bh, eh, or fh received control data communication type (usr.alltrans bit) individual communication = 0 broadcast communication = 1 communication target (usr.slvrq bit) slave specification = 1 no specification = 0 lock status (usr.lock bit) lock = 1 unlock = 0 master unit identification (match with par register) lock request unit = 1 other = 0 slave transmission enable (bcr.enslvtx bit) slave reception enable (bcr.enslvrx bit) ah bh eh fh 0 don ? t care 01 11 don ? t care 1 { other than above (b) if received control data is 0h, 3h, 4h, 5h, 6h, or 7h received control data communication type (usr.alltrans bit) individual communication = 0 broadcast communication = 1 communication target (usr.slvrq bit) slave specification = 1 no specification = 0 lock status (usr.lock bit) lock = 1 unlock = 0 master unit identification (match with par register) lock request unit = 1 other = 0 slave transmission enable (bcr.enslvtx bit) slave reception enable (bcr.enslvrx bit) 0h 3h 4h 5h 6h 7h 0 { { 0 don ? t care 1 {{ {{ 0 don ? t care { {{ 0 { {{{ 01 1 1 1 don ? t care {{{{{{ other than above caution if the received control data is other than the data shown in table 18-5, (nack signal is returned) is unconditionally assumed. remarks 1. { : ack signal is returned. : nack signal is returned. 522 preliminary user ? s manual u16451ej1v0um chapter 18 iebus controller
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 523 (6) telegraph length field this field is output by the transmission side to inform the reception side of the number of bytes of the transmit data. the configuration of the telegraph length field is as shown in figure 18-5. table 18-6 shows the relationship between the telegraph length bit and the number of transmit data. figure 18-5. telegraph length field msb lsb telegraph length field telegraph length bit (8 bits) parity ack table 18-6. contents of telegraph length bit telegraph length bit (hex) number of transmit data bytes 01h 02h | ffh 00h 1 byte 2 bytes | 255 bytes 256 bytes the operation of the telegraph length field differs depending on whether the master transmits data (when control bit 3 is 1) or receives data (when control bit 3 is 0). (a) when master transmits data the telegraph length bit and parity bit are output by the master unit and the synchronization signals of bits are output by the master unit. when the slave unit detects that the parity is even, it outputs the ack signal, and starts outputting the data field. during broadcast communication, however, the slave unit outputs the nack signal. if the parity is odd, the slave unit judges that the telegraph length bit has not been correctly received, outputs the nack signal, and returns to the standby (monitor) status. at this time, the master unit also returns to the standby status, and communication ends. (b) when master receives data the telegraph length bit and parity bit are output by the slave unit and the synchronization signals of bits are output by the master unit. if the master unit detects that the parity bit is even, it outputs the ack signal. if the parity bit is odd, the master unit judges that the telegraph length bit has not been correctly received, outputs the nack signal, and returns to the standby status. at this time, the slave unit also returns to the standby status, and communication ends.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 524 (7) data field this is data output by the transmission side. the master unit transmits or receives data to or from a slave unit by using the data field. the configuration of the data field is as shown below. figure 18-6. data field data field (number specified by telegraph length field) msb lsb one data ack parity data bit (8 bits) ack parity following the data bit, the parity bit and acknowledge bit are respectively output by the master unit and slave unit. use broadcast communication only for when the master unit transmits data. at this time, the acknowledge bit is ignored. the operation differs as follows depending on whether the master transmits or receives data. (a) when master transmits data when the master units writes data to a slave unit, the master unit transmits the data bit and parity bit to the slave unit. if the parity is even and the receive data is not stored in the dr register when the slave unit has received the data bit and parity bit, the slave unit outputs an ack signal. if the parity is odd or if the receive data is stored in the dr register, the slave unit rejects receiving the data, and outputs the nack signal. if the slave unit outputs the nack signal, the master unit transmits the same data again. this operation continues until the master detects the ack signal from the slave unit, or the data exceeds the maximum number of transmit bytes. if there is more data and the maximum number of transmit bytes is not exceeded when the parity is even and when the slave unit outputs the ack signal, the master unit transmits the next data. during broadcast communication, the slave unit outputs the nack signal, and the master unit transfers 1 byte of data at a time. if the parity is odd or the dr register is storing receive data after the slave unit has received the data bit and parity bit during broadcast communication, the slave unit judges that reception has not been performed correctly, and stops reception.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 525 (b) when master receives data when the master unit reads data from a slave unit, the master unit outputs a sync signal corresponding to all the read bits. the slave unit outputs the contents of the data and parity bits to the bus in response to the sync signal from the master unit. the master unit reads the data and parity bits output by the slave unit, and checks the parity. if the parity is odd, or if the dr register is storing a receive data, the master unit rejects accepting the data, and outputs the nack signal. if the maximum number of transmit bytes is within the value that can be transmitted in one communication frame, the master unit repeats reading the same data. if the parity is even and the dr register is not storing a receive data, the master unit accepts the data and outputs the ack signal. if the maximum number of transmit bytes is within the value that can be transmitted in one frame, the master unit reads the next data. caution do not operate master reception in broadcast communication, because the slave unit cannot be defined and data transfer cannot be performed correctly. (8) parity bit the parity bit is used to check to see if the transmit data has no error. the parity bit is appended to each data of the master address, slave address, control, telegraph length, and data bits. the parity is an even parity. if the number of bits in data that are ? 1 ? is odd, the parity bit is ? 1 ? . if the number of bits in the data that are ? 1 ? is even, the parity bit is ? 0 ? . (9) acknowledge bit during normal communication (communication from one unit to another), an acknowledge bit is appended to the following locations to check if the data has been correctly received. ? end of slave address field ? end of control field ? end of telegraph length field ? end of data field the definition of the acknowledge bit is as follows. ? 0: indicates that the transmit data is recognized (ack signal). ? 1: indicates that the transmit data is not recognized (nack signal). during broadcast communication, however, the contents of the acknowledge bit are ignored. (a) last acknowledge bit of slave field the last acknowledge bit of the slave field serves as a nack signal in any of the following cases, and transmission is stopped. ? if the parity of the master address bit or slave address bit is incorrect ? if a timing error (error in bit format) occurs ? if a slave unit does not exist
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 526 (b) last acknowledge bit of control field the last acknowledge bit of the control field serves as a nack signal in any of the following cases, and transmission is stopped. ? if the parity of the control bit is incorrect ? if control bit 3 is ? 1 ? (write operation) when the slave reception enable flag (bcr.enslvrx bit) is not set (1) note ? if the control bit indicates reading of data (3h or 7h) when the slave transmission enable flag (bcr.enslvtx bit) is not set (1) note ? if a unit other than that has set locking requests 3h, 6h, 7h, ah, bh, eh, or fh of the control bit when locking is set ? if the control bit indicates reading of lock addresses (4h, 5h) even when locking is not set ? if a timing error occurs ? if the control bit is undefined note refer to 18.3 (1) iebus control register (bcr) . cautions 1. the ack signal is always returned when the control data of the slave status request is received, even if the enslvtx bit = 0. 2. the nack signal is returned by the acknowledge bit in the control field when the control data for data/command writing is received, even if the enslvrx bit = 0. slave reception can be disabled (communication stopped) by enslvrx bit only in the case of individual communication. in the case of broadcast communication, communication is maintained and the data request interrupt request signal (intie1) or iebus end interrupt request signal (intie2) is generated. (c) last acknowledge bit of telegraph length field the last acknowledge bit of the telegraph length field serves as a nack signal in any of the following cases, and transmission is stopped. ? if the parity of the telegraph length bit is incorrect ? if a timing error occurs (d) last acknowledge bit of data field the last acknowledge bit of the data field serves as a nack signal in any of the following cases, and transmission is stopped. ? if the parity of the data bit is incorrect note ? if a timing error occurs after the preceding acknowledge bit has been transmitted ? if the receive data is stored in the dr register and no more data can be received note note in this case, when the communication executed is individual communication, if the maximum number of transmit bytes is within the value that can be transmitted in one frame, the transmission side executes transmission of that data field again. for broadcast communication, the transmission side does not execute transmission again, a communication error occurs on the reception side and reception stops.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 527 18.1.7 transfer data (1) slave status the master unit can learn why the slave unit did not return the ack signal by reading the slave status. the slave status is determined according to the result of the last communication the slave unit has executed. all the slave units can supply information on the slave status. the configuration of the slave status is shown below. figure 18-7. bit configuration of slave status msb lsb bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 note 1 meaning 0 transmit data is not written in dr register 1 transmit data is written in dr register bit 1 note 2 meaning 0 receive data is not stored in dr register 1 receive data is stored in dr register bit 2 meaning 0 unit is not locked 1 unit is locked bit 3 meaning 0 fixed to 0 bit 4 note 3 meaning 0 slave transmission is stopped 1 slave transmission is ready bit 5 meaning 0 fixed to 0 bit 7 bit 6 meaning 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 not used indicates the highest mode supported by the unit note 4 . notes 1. after reset: bit 0 is set to 1. 2. the receive buffer size is 1 byte. 3. when the v850es/sg2 serves as a slave unit, this bit corresponds to the status indicated by bcr.enslvtx bit. 4. bits 7 and 6 are fixed to ? 10 ? because the v850es/sg2 can support modes 1 and 2.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 528 (2) lock address when the lock address is read (control bit: 4h or 5h), the address (12 bits) of the master unit that has issued the lock instruction is configured in 1-byte units as shown below and read. figure 18-8. configuration of lock address msb lower 8 bits undefined higher 4 bits control bit: 4h control bit: 5h lsb (3) data if the control bit indicates reading of data (3h or 7h), the data in the data buffer of the slave unit is read by the master unit. if the control bit indicates writing of data (bh or fh), the data received by the slave unit is processed according to the operation rule of that slave unit. (4) locking and unlocking the lock function is used when a message is transferred in two or more communication frames. the unit that is locked does not receive data from units other than the one that has locked the unit (does not receive broadcast communication). a unit is locked or unlocked as follows. (a) locking if the communication frame is completed without succeeding to transmit or receive data of the number of bytes specified by the telegraph length bit after the telegraph length field has been transmitted or received (ack = 0) by the control bit that specifies locking (3h, ah, or bh), the slave unit is locked by the master unit. at this time, the bit (bit 2) in the byte indicating the slave status is set to ? 1 ? . (b) unlocking after transmitting or receiving data of the number of data bytes specified by the telegraph length bit in one communication frame by the control bit that has specified locking (3h, ah, or bh), or the control bit that has specified unlocking (6h), the slave unit is unlocked by the master unit. at this time, the bit related to locking (bit 2) in the byte indicating the slave status is reset to ? 0 ? . locking or unlocking is not performed during broadcast communication. locking and unlocking conditions are shown below.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 529 table 18-7. lock setting conditions broadcast communication individual communication control data communication end frame end communication end frame end 3h, 6h note cannot be locked lock set ah, bh cannot be locked cannot be locked cannot be locked lock set 0h, 4h, 5h, eh, fh cannot be locked cannot be locked cannot be locked cannot be locked note the frame end of control data 6h (slave status read/unlock) occurs when the parity in the data field is odd, and when the nack signal from the iebus unit is repeated up to the maximum number of transfer bytes with being output. table 18-8. unlock release conditions (while locked) broadcast communication from lock request unit individual communication from lock request unit control data communication end frame end communication end frame end 3h, 6h note unlocked remains locked ah, bh unlocked unlocked unlocked remains locked 0h, 4h, 5h, eh, fh remains locked remains locked remains locked remains locked note the frame end of control data 6h (slave status read/unlock) occurs when the parity in the data field is odd, and when the nack signal from the iebus unit is repeated up to the maximum number of transfer bytes with being output. 18.1.8 bit format the format of the bits constituting the communication frame of the iebus is shown below. figure 18-9. bit format of iebus logic ? 1 ? logic ? 0 ? preparation period synchronization period data period stop period preparation period: first low-level (logic ? 1 ? ) period synchronization period: next high-level (logic ? 0 ? ) period data period: period indicating value of bit stop period: last low-level (logic ? 1 ? ) period the synchronization period and data period are almost equal to each other in length. the iebus synchronizes each bit. the specifications on the time of the entire bit and the time related to the period allocated to that bit differ depending on the type of the transmit bit, or whether the unit is the master unit or a slave unit. the master and slave units monitor whether each period (preparation period, synchronization period, data period, and stop period) is output for specified time while they are in communication. if a period is not output for the specified time, the master and slave units report a timing error, immediately terminate communication and enter the standby status.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 530 18.2 configuration the block diagram of the iebus controller is shown below. figure 18-10. iebus controller block diagram ietx0 f xx to f xx /3 ierx0 uar, sar 12 ocks2 prescaler prescaler block 8 bcr, psr, isr esr, cdr, dlr, dr 12 8 reception block transmission block transmit shift register receive shift register field processing block bit processing block interrupt control block internal register block iebus interface block interrupt request signal iebus controller internal bus ssr, usr, fsr, scr, ccr 4 rar, rsa noise filter (1) hardware configuration and functions iebus mainly consists of the following six internal blocks. ? interrupt control block ? internal registers ? bit processing block ? field processing block ? iebus interface block ? prescaler block
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 531 (a) interrupt control block this control block transfers interrupt request signals from the iebus controller to the cpu. (b) internal registers these registers set data to the control registers and fields that control iebus (for the internal registers, refer to 18.3 control registers ). (c) bit processing block this block generates and breaks down bit timing, and mainly consists of a bit sequence rom, 8-bit preset timer, and comparator. (d) field processing block this block generates each field in the communication frame, and mainly consists of a field sequence rom, 4-bit down counter, and comparator. (e) iebus interface block this is the interface block for an external driver/receiver, and mainly consists of a noise filter, shift register, and transmission/reception block (collision detector, parity detector, parity generator, and ack/nack generator). (f) prescaler block this block selects the clock to be supplied to the iebus controller.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 532 18.3 control registers the registers that control the iebus controller are shown below. table 18-9. control registers of iebus controller bit unit for manipulation address function register name symbol r/w 1816 after reset fffff348h iebus clock select register ocks2 fffff360h iebus control register bcr ? fffff361h iebus power save register psr r/w ? 00h fffff362h iebus slave status register ssr 81h fffff363h iebus unit status register usr r fffff364h iebus interrupt status register isr ? fffff365h iebus error status register esr ? 00h fffff366h iebus unit address register uar fffff368h iebus slave address register sar r/w fffff36ah iebus partner address register par fffff36ch iebus receive slave address register rsa r 0000h fffff36eh iebus control data register cdr 00h fffff36fh iebus telegraph length register dlr 01h fffff370h iebus data register dr r/w fffff371h iebus field status register fsr 00h fffff372h iebus success count register scr 01h fffff373h iebus communication count register ccr r 20h
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 533 (1) iebus control register (bcr) the bcr register is an 8-bit register that controls the operations of the iebus controller. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h rw address: fffff360h <7> <6> <5> <4> <3> 2 1 0 bcr eniebus mstrq allrq enslvtx enslvrx 0 0 0 eniebus communication enable flag 0 iebus unit stopped 1 iebus unit active mstrq master request flag 0 iebus unit not requested as master 1 iebus unit requested as master allrq broadcast request flag 0 individual communication requested 1 broadcast communication requested enslvtx slave transmission enable flag 0 slave transmission disabled 1 slave transmission enabled enslvrx slave reception enable flag 0 slave reception disabled 1 slave reception enabled cautions 1. while iebus is operating as the master, writing to the bcr register (including bit manipulation instructions) is disabled until either the end of that communication or frame, or until communication is stopped by the occurrence of an arbitration-loss communication error. master requests cannot therefore be multiplexed. however, the case when communication has been forcibly stopped (eniebus flag = 0) is not problem. 2. if a bit manipulation instruction for the bcr register conflicts with a hardware reset of the mstrq bit, the bcr register may not operate normally. the following countermeasures are recommended in this case. ? ? ? ? because the hardware reset is instigated in the acknowledgement period of the slave address field, be sure to observe caution 1 of (b) master request flag (mstrq) below. ? ? ? ? be sure to observe the caution above regarding writing to the bcr register.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 534 (a) communication enable flag (eniebus)...bit 7 set: by software clear: by software the iebus controller participates in communication differently depending on the timing of setting the eniebus bit (1), as follows. table 18-10. timing of setting eniebus bit and participation in communication timing of setting eniebus bit how iebus controller participates in communication if communication is not performed on iebus participates in communication from the next frame or starts communication. if other bus master is communicating start bit while communication is in progress on iebus participates in communication from that frame if the start bit is detected. if the start bit is not detected, participates in communication from the next frame. if communication is in progress on iebus after start bit from other bus master is detected participates in communication from the next frame. if the eniebus bit is cleared (0), communication is immediately stopped even while it is in progress, and the internal flags and registers are reset, with some exceptions. the registers that are not reset by the eniebus bit are listed in the table below. the iebus controller does not respond even if another unit starts communication when the eniebus bit = 0. table 18-11. registers that are not reset by eniebus bit registers not reset by eniebus bit remark uar not reset sar not reset cdr data written from cpu is not reset but data received during communication is reset. dlr data written from cpu is not reset but data received during communication is reset. dr data written from cpu is not reset but data received during communication is reset. caution before setting the eniebus bit (1), the following registers must be set depending on the mode of communication to be started. table 18-12. registers that must be set before each communication mode of communication registers that must be set in advance master transmission uar, sar, cdr, dlr, dr (first 1-byte data) master reception uar, sar, cdr slave transmission note uar, dlr, dr (first 1-byte data) note slave reception uar note when starting slave transmission, information such as the value to be set to the dlr register and which data is to be returned (value to be set to the dr register) must be assigned in advance.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 535 (b) master request flag (mstrq)...bit 6 set: by software clear: cleared (0) by hardware when master communication is started and immediately before the start interrupt of the master occurs. cleared (0) by hardware before a communication error occurs. when the eniebus bit is cleared. when the mstrq bit is set (1), the iebus controller starts communication on iebus as the master. if communication is in progress on iebus (if the start bit cannot be detected while the start bit is being communicated or if communication is in progress after the start bit has been detected), however, the controller waits until the current frame ends (holds the master request pending), outputs the start bit after the frame has ended, and starts communication as the master. cautions 1. if the iebus controller has lost in arbitration, issue the master request again by software. in doing so, set (1) the mstrq bit at a timing other than that illustrated below. figure 18-11. timing at which mstrq bit cannot be set mstrq bit mstrq bit cannot be set (1) (approx. 167 ns (mode 1, at 6.29 mhz)). mstrq bit clear signal start interrupt request signal (intie2, intsta) 2. when a master request has been sent and bus mastership acquired, do not set the mstrq, enslvtx, or enslvrx bit until the end of communication (i.e. the communication end flag (isr.endtrns bit) or frame end flag (isr.endfram bit) is set (1)) as setting these flags disables interrupt request signal generation. however, these flags can be set if communication has been aborted. (c) broadcast request flag (allrq)...bit 5 set: by software clear: by software caution when requesting broadcast communication, always set (1) the allrq bit, then the mstrq bit.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 536 (d) slave transmission enable flag (enslvtx)...bit 4 set: by software clear: by software cautions 1. the enslvtx bit must be set before the parity bit in the control field is received. 2. clear the enslvtx bit (0) before setting the mstrq bit (1) when making a master request. this is to avoid transmission of the data of the dr register that tries master transmission if the controller loses in arbitration after master operation and if slave transmission is requested by the master. 3. when returning to an enabled state from a disabled state, transmission becomes valid from the next frame. 4. if control data (3h or 7h) for data/command writing is received when the enslvtx bit = 0, the nack signal is returned by the acknowledge bit in the control field. 5. the status interrupt request signals (intie2, intsta) will be generated and communication continued when the control data of a slave status request is returned, even if the enslvtx bit = 0. (e) slave reception enable flag (enslvrx)...bit 3 set: by software clear: by software cautions 1. the enslvrx bit must be set before the parity bit in the control field is received. 2. while the cpu is busy with other processing, slave reception can be prevented by clearing the enslvrx bit (0). during individual communication, the nack signal is returned in the control field and communication is completed. during broadcast communication, communication cannot be completed because the acknowledge bit is ignored. however, the iebus controller does not respond to the broadcast communication and does not generate an interrupt request signal. 3. when returning to an enabled state from a disabled state, transmission becomes valid from the next frame.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 537 (2) iebus power save register (psr) the psr register is an 8-bit register that controls the internal clock and communication mode of the iebus controller. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h rw address: fffff361h <7><6>543210 psrenclkiemode000000 enclk internal clock operation enable flag 0 stop internal clock of iebus controller 1 enable internal clock of iebus controller iemode iebus communication mode setting flag 0 set communication mode 1 1 set communication mode 2 cautions 1. do not set the psr register while communication is enabled (bcr.eniebus bit = 1). 2. be sure to clear bits 5 to 0 to 0.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 538 (3) iebus slave status register (ssr) the ssr register is an 8-bit register that indicates the communication status of the slave unit. after receiving a slave status transmission request from the master, read this register by software, and write a slave status to the dr register to transmit the slave status. at this time, the telegraph length is automatically set to ? 01h ? , so setting of the dlr register is not required (because it is preset by hardware). bits 6 and 7 indicate the highest mode supported by the unit, and are fixed to ? 10 ? (mode 2). this register is read-only, in 8-bit units. reset input sets this register to 81h. after reset: 81h r address: fffff362h 7 6 5 <4> 3 <2> <1> <0> ssr 1 0 0 statslv 0 statlock statrx stattx statslv slave transmission status flag 0 slave transmission stops 1 slave transmission enabled statlock lock status flag 0 unlock status 1 lock status statrx dr register receive status 0 receive data not stored in dr register 1 receive data stored in dr register stattx dr register transmit status 0 transmit data not stored in dr register 1 transmit data stored in dr register (a) slave transmission status flag (statslv)...bit 4 reflects the contents of the slave transmission enable flag (bcr.enslvtx bit). (b) lock status flag (statlock)...bit 2 reflects the contents of the lock flag (usr.lock bit). (c) dr register reception status (statrx)...bit 1 this flag indicates the dr register reception state. (d) dr register transmission status (stattx)...bit 0 this flag indicates the dr register transmission state.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 539 (4) iebus unit status register (usr) the usr register is an 8-bit register that indicates the iebus unit status. this register is read-only, in 8-bit units. reset input clears this register to 00h. after reset: 00h r address: fffff363h 76543210 usr 0 slvrq arbit alltrns ack lock 0 0 slvrq slave request flag 0 no request from master to slave 1 request from master to slave arbit arbitration result flag 0 arbitration win 1 arbitration loss alltrns broadcast communication flag 0 individual communication status 1 broadcast communication status ack acknowledge transmission flag 0 nack signal transmitted 1 ack signal transmitted lock lock status flag 0 unit unlocked 1 unit locked
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 540 (a) slave request flag (slvrq)...bit 6 a flag indicating whether there has been a slave request from the master. set: when the unit is requested as a slave (if the condition in table 18-13 slave request condition (slvrq bit setting condition ) is satisfied), this flag is set (1) by hardware when the acknowledge period of the slave address field starts. clear: this flag is cleared (0) by hardware when the unit is not requested as a slave (if the condition in table 18-13 slave request condition (slvrq bit setting condition ) is not satisfied). the reset timing is the same as the set timing. if the unit is requested as a slave immediately after communication has been correctly received (when the slvrq bit = 1), and if a parity error occurs in the slave address field for that communication, the flag is not cleared. table 18-13. slave request condition (slvrq bit setting condition) status of unit received master address communication mode received slave address individual uar register matching group matching not locked don ? t care broadcast fffh individual uar register matching group matching locked locked master matching broadcast fffh caution if a unit other than the locked master communicates with the unit while the unit is locked, the slvrq bit is not set but the ack signal is returned to the slave address field. this is because communication must be continued, even if a unit other than the locked master returns the signal, if the control data is a slave status request. (b) arbitration result flag (arbit)...bit 5 a flag that indicates the result of arbitration. set: this flag is set (1) when the data output by the iebus unit during the arbitration period does not match the bus line data. clear: this flag is cleared (0) by the start bit timing. cautions 1. the timing at which the arbitration result flag (arbit bit) is cleared differs depending on whether the unit outputs a start bit. ? ? ? ? if start bit is output: the flag is cleared at the output start timing. ? ? ? ? if start bit is not output: the flag is cleared at the detection timing of the start bit (approx. 160 s (mode 1, at 6.29 mhz) after output) 2. the flag is cleared (0) at the detection timing of the start bit if the other unit outputs the start bit earlier and the unit does not output the start bit after the master request.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 541 (c) broadcast communication flag (alltrns)...bit 4 flag indicating whether the unit is performing broadcast communication. the contents of the flag are updated in the broadcast field of each frame. except for initialization (reset) by system reset, the set/clear conditions vary depending on the receive data of the broadcast field bit. set: when ? broadcast ? is received by the broadcast field clear: when ? individual ? is received by the broadcast field, or upon the input of a system reset. caution the broadcast flag is updated regardless of whether iebus is the communication target or not. figure 18-12. example of broadcast communication flag operation broadcast communication flag clear set not cleared by start bit iebus sequence start m11 broad- cast m10 m11 individual m10 start (d) acknowledge transmission flag (ack)...bit 3 a flag that indicates whether the ack signal has been transmitted in the acknowledge bit period of the acknowledge bit field when iebus is the receiving unit. the contents of the flag are updated in the acknowledge bit period of each frame. however, if the internal circuit is initialized by the occurrence of a parity error, etc., the contents are not updated in the acknowledge bit period of that field. (e) lock status flag (lock)...bit 2 a flag that indicates whether the unit is locked. set: this flag is set (1) when the communication end flag (isr.endtrns bit) goes low and the frame end flag (isr.endfram bit) goes high after receipt of a lock specification (3h, 6h, ah, bh) in the control field. clear: when the communication enable flag (bcr.eniebus bit) is cleared (0). when the communication end flag (endtrns bit) is set (1) after receipt of a lock release (3h, 6h, ah, bh) in the control field. caution lock specification/release is not possible in broadcast communication. in the lock status, individual communication from a unit other than the one that requests locking is not acknowledged. however, even communication from a unit other than the one that requests locking is acknowledged as long as the communication is a slave status request.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 542 (5) iebus interrupt status register (isr) the isr register indicates the interrupt source when iebus issues an interrupt request signal. this register is read to generate an interrupt request signal, after which the specified interrupt processing is carried out. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w note 1 address: fffff364h 7<6>543210 isr 0 ieerr startf statusf endtrns endfram 0 0 ieerr communication error flag (during communication) 0 no communication error 1 communication error startf start interrupt flag 0 start interrupt request signal did not occur 1 start interrupt request signal occurred statusf status transmission flag (slave) 0 no slave status/lock address (higher 4 bits, lower 8 bits) transmission request 1 slave status/lock address (higher 4 bits, lower 8 bits) transmission request endtrns communication end flag 0 communication does not end after the number of bytes set in the telegraph length field have been transferred 1 communication ends after the number of bytes set in the telegraph length field have been transferred endfram frame end flag 0 the frame (transfer of the maximum number of bytes) does not end 1 the frame (transfer of the maximum number of bytes) ends notes 1. only the ieerr bit can be written, and only to 0 (i.e., the ieerr bit can only be cleared). the ieerr bit is not set (1) even if 1 is written to it. 2. mode 1: 32 bytes mode 2: 128 bytes
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 543 (a) communication error flag (ieerr)...bit 6 a flag that indicates a communication error has occurred. when a communication error occurs, the intie2 and interr interrupt request signals are generated. set: the flag is set (1) if a timing error, parity error (except in the data field), nack reception error (except in the data field), underrun error, overrun error (that occurs during broadcast communication reception), or write error occurs. clear: by software (b) start interrupt flag (startf)...bit 5 a flag that indicates the start interrupt. when a start interrupt occurs, the intie2 and intsta interrupt request signals are generated. set: this flag is set (1) in the slave address field, upon a master request. when iebus is a slave unit, this flag is set (1) upon a request from the master (only if it was a slave request in the locked state from the unit requesting a lock). clear: this flag is cleared (0) if the status transmission interrupt, communication end interrupt, frame end interrupt, or intie1 interrupt request signal is generated. (c) status transmission flag (statusf)...bit 4 a flag that indicates the master requested transmission of the slave status and lock address (higher 4 bits and lower 8 bits) when the controller was serving as a slave. set: this flag is set (1) when 0h, 4h, 5h, or 6h is received in the control field from the master when the iebus is a slave unit. clear: this flag is cleared (0) if the start interrupt, communication end interrupt, frame end interrupt, or intie1 interrupt request signal is generated. (d) communication end flag (endtrans)...bit 3 a flag that indicates whether communication ends after the number of bytes set in the telegraph length field have been transferred. when a communication error occurs, the intie2 and intsta interrupt request signals are generated. set: this flag is set (1) when the count value of the scr register is 00h. clear: this flag is cleared (0) if the start interrupt, status transmission interrupt, frame end interrupt (if the communication end interrupt does not occur), or intie1 interrupt request signal is generated.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 544 (e) frame end flag (endfram)...bit 2 a flag that indicates whether communication ends after the maximum number of bytes (mode 1: 32 bytes, mode 2: 128 bytes) have been transferred. set: this flag is set (1) when the count value of the ccr register is 00h. clear: this flag is cleared (0) if the start interrupt, status transmission interrupt, communication end interrupt (if the frame end interrupt does not occur), or intie1 interrupt request signal is generated cautions 1. if both the ccr and scr registers are cleared to 00h, the endtrns and endfram bits are set (1) at the same time. 2. if the last data field is the nack signal when the maximum number of transmitted bytes is reached as a result of retransmitting the data, the endfram bit and ieerr (nack reception error) bit are set at the same time.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 545 (6) iebus error status register (esr) the esr register indicates the source of the communication error interrupt request signal of iebus. each bit of this register is set (1) as soon as the communication error flag (isr.ieerr bit) is set (1). the source of a communication error, if any, can be identified by checking the contents of this register. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. after reset: 00h r/w address: fffff365h <7> <6> <5> <4> <3> <2> 1 <0> esr terr perr nerr uerr oerr werr 0 deflag terr timing error occurrence flag 0 timing error did not occur 1 timing error occurred perr parity error occurrence flag 0 parity error did not occur 1 parity error occurred nerr nack reception error occurrence flag 0 nack reception error does not occur 1 nack reception error occurred uerr underrun error occurrence flag 0 underrun error did not occur 1 underrun error occurred oerr overrun error occurrence flag 0 overrun error did not occur 1 overrun error occurred werr write error occurrence flag 0 write error did not occur 1 write error occurred deflag third party error occurrence flag 0 error occurred during communication with unit 1 error occurred during communication with station other than unit cautions 1. each bit can only be cleared (0). it cannot be set (1) even if 1 is written to it. 2. the value of the esr register is updated when an error occurs. if the esr register is read at this time, however, an undefined value is read. it is recommended to read the esr register in error interrupt servicing. 3. if a communication error occurs, the iebus controller returns to the default status and makes preparation for communication. if communication is started without the error corrected, the error flag accumulates the error. correct the error before the next communication is started.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 546 (a) timing error occurrence flag (terr)?bit 7 set: this flag is set (1) if a timing error occurs. clear: by software a timing error occurs if the high-/low-level width of the communication bit is not the defined value. the defined value of the high- and low-level width is set to the bit processing block and monitored by the internal timer. if a timing error occurs, the interr and intie2 interrupt request signals are generated. (b) parity error occurrence flag (perr)?bit 6 set: this flag is set (1) if a parity error occurs. clear: by software a parity error occurs if the parity generated in each field does not match the received parity while the controller is serving as a receiver unit. if the parity does not match in the data field during individual communication, however, the nack signal is returned and retransmission of data is requested. therefore, the parity error does not occur. table 18-14. operation if parity does not match field communication mode operation if parity does not match master address field individual/broadcast parity error occurs. slave address field individual/broadcast parity error occurs. control data field individual/broadcast parity error occurs. telegraph length field individual/broadcast parity error occurs. individual retransmission is requested by returning nack signal. data field broadcast parity error occurs. (c) nack reception error occurrence flag (nerr)?bit 5 set: this flag is set (1) if a nack reception error occurs. clear: by software a nack reception error occurs if the nack signal is received during the acknowledge bit period of the slave address field, control data field, or telegraph length field during individual communication, regardless of whether the controller is operating as the master or a slave. if the nack signal is received during the acknowledge bit period of the data field, a nack reception error does not occur because data is retransmitted. if the nack signal is received during the acknowledge period of the last data field when the maximum number of transfer bytes is reached, the nack reception error occurs. the nack reception error does not occur during broadcast communication because the ack/nack signal is not identified. the nack reception error does not occur during third-party communication because only the timing/parity error is detected as an error.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 547 (d) underrun error occurrence flag (uerr) ? bit 4 set: this flag is set (1) if an underrun error occurs. clear: by software an underrun error occurs if the next data is not transmitted to the dr register in time before the ack signal is received. if the nack signal is received during individual communication and during the acknowledge bit period, the underrun error does not occur because the data is retransmitted. figure 18-13. timing of underrun error occurrence p . . . . . . a data field data field pa request to write data to dr register underrun error occurs if data is not written to dr register during this period. intie1 remark p: parity bit a: acknowledge bit
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 548 (e) overrun error occurrence flag (oerr) ? bit 3 set: this flag is set (1) if an overrun error occurs. clear: by software if 1-byte data is stored in the dr register while the iebus controller serves as a receiver unit, the data request interrupt request signal (intie1) is generated, and the dr register is read by means of dma or by software. if this reading is delayed and the next data is received, an overrun error occurs. cautions 1. if the dr register is not read and the number of retransmitted data reaches the maximum number of transmitted bytes (32 bytes) after the overrun error has occurred, the frame end interrupt request signal (intsta or intie2) occurs. the overrun status is maintained until the dr register is read, even after the frame has ended. 2. the overrun status is cleared only when the dr register is read and when the system is reset. therefore, be sure to read the dr register in the communication error interrupt processing program. 3. the next data cannot be transmitted in the overrun status if it is 2 bytes or more. because the data request interrupt request signal (intie1) does not occur, the transmit data cannot be set and an underrun error occurs. therefore, be sure to execute transmission after clearing the overrun status. remark during individual communication reception, the nack signal is returned during the acknowledge bit period of the next data. in response, the transmitter unit retransmits data. therefore, the ccr register is decremented but the scr register is not decremented. during broadcast communication reception, the communication error interrupt request signal (intie2) is generated and reception is stopped. at this time, the dr register is not updated. the intie1 signal is not generated. the statrx bit of the ssr register is held set (to 1). the overrun status is cleared when data is received after the dr register has been read. figure 18-14. timing of overrun error occurrence p . . . . . . a data field data field pa request to write data to dr register overrun error occurs if data is not written to dr register during this period. intie1 remark p: parity bit a: acknowledge bit
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 549 (f) write error occurrence flag (werr) ? bit 2 set: this flag is set (1) if a write error occurs. clear: by software a write error occurs if the data written to the dr register is not transmitted in the data field during unit transmission. the timing of occurrence of a write error is illustrated below. figure 18-15. timing of write error occurrence . . . . . . data field acknowledge bit write error occurs if data is not written to dr register during this period. approx. 170 ns intie1 cautions 1. even when the werr bit is set (1), the intie1 interrupt request signal may be generated. 2. if the nack signal is returned, the werr bit is not set because data is retransmitted. (g) third-party error occurrence flag (deflag)?bit 0 set: this flag is set (1) if a timing error or parity error occurs during communication regardless of the unit (during communication between third parties). clear: by software caution if an error occurs before the third-party communication starts even when the slave address field does not match that of the unit (for example, if the nack signal is received when the received address does not match that of the unit in the slave address field (if the nerr bit is set (1))), the deflag bit is not set (1). remark communication between third parties may take place in the following two cases. <1> if the received address in the slave address field does not match that of the unit (during individual communication: matching with uar register, during broadcast communication: matching with group or fffh) and if communication continues after the ack signal has been received, the unit monitors that communication. <2> if the unit cannot respond to the received control data in the control field during broadcast communication and if communication continues, the unit monitors that communication. for example, this happens when the unit receives control data fh from master during broadcast communication but the slave reception enable flag of the unit is disabled (bcr.enslvrx bit = 0) (the nack signal is returned and communication ends during individual communication).
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 550 (7) iebus unit address register (uar) the uar register sets the unit address of an iebus unit. this register must always be set before starting communication. sets the unit address (12 bits) to bits 11 to 0. this register can be read or written in 16-bit units. reset input clears this register to 0000h. 15 0 14 0 13 0 12 0 uar 11 10 9 8 7 6 5 4 3 2 1 0 address fffff366h after reset 0000h r/w r/w caution do not set the uar register while communication is enabled (bcr.eniebus bit = 1). (8) iebus slave address register (sar) during a master request, the value of this register is reflected in the value of the transmit data in the slave address field. the sar register must always be set before starting communication. the sar register sets the slave address (12 bits) to bits 11 to 0. this register can be read or written in 16-bit units. reset input clears this register to 0000h. 15 0 14 0 13 0 12 0 sar 11 10 9 8 7 6 5 4 3 2 1 0 address fffff368h after reset 0000h r/w r/w caution do not set the sar register while communication is enabled (bcr.eniebus bit = 1). (9) iebus partner address register (par) the par register stores the master address value received in the master address field regardless of whether the unit is operating as the master or a slave. if a request ? 4h ? to read the lock address (lower 8 bits) is received from the master, read the value of this register by software, and write the data of the lower 8 bits to the dr register. if a request ? 5h ? to read the lock address (higher 4 bits) is received from the master, read the value of this register by software and write the data of bits 11 to 8 to the higher 4 bits of the dr register. the par register sets the partner address (12 bits) to bits 11 to 0. this register is read-only, in 16-bit units. reset input clears this register to 0000h. 15 0 14 0 13 0 12 0 par 11 10 9 8 7 6 5 4 3 2 1 0 address fffff36ah after reset 0000h r/w r caution the par register stores an address value if the parity is correct and the unit is not locked when the parity period of the master address field expires. if the par register is read at this time, an undefined value is read.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 551 (10) iebus receive slave address register (rsa) the rsa register stores the slave address value received in the slave address field regardless of whether the unit is operating as the master or a slave. this register is read-only, in 16-bit units. reset input clears this register to 0000h. 15 0 14 0 13 0 12 0 rsa 11 10 9 8 7 6 5 4 3 2 1 0 address fffff36ch after reset 0000h r/w r caution the rsa register stores an address value if the parity is correct and the unit is not locked when the parity period of the slave address field expires. if the rsa register is read at this time, an undefined value is read. (11) iebus control data register (cdr) the cdr register can be read or written in 8-bit units. reset input clears this register to 00h. remark the cdr register consists of a write register and a read register and data written to the cdr register cannot be read as is. the data read from this register is the data received by iebus communication. (a) when master unit the data of the lower 4 bits is reflected in the data transmitted in the control field. during a master request, the cdr register must be set in advance before starting communication. (b) when slave unit the data received in the control field is written to the lower 4 bits. when the status transmission flag (isr.statusf bit) is set (1), an interrupt request signal (intie2) is issued, and each processing should be performed by software, according to the value of the lower 4 bits of the cdr register.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 552 after reset: 00h r/w address: fffff36eh 76543210 cdr 0 0 0 0 mod selcl2 selcl1 selcl0 mod selcl2 selcl1 selcl0 function 0 0 0 0 read slave status 0 0 0 1 undefined 0 0 1 0 undefined 0 0 1 1 read data and lock 0 1 0 0 read lock address (lower 8 bits) 0 1 0 1 read lock address (lower 4 bits) 0 1 1 0 read slave status and unlock 0 1 1 1 read data 1 0 0 0 undefined 1 0 0 1 undefined 1 0 1 0 write command and lock 1 0 1 1 write data and lock 1 1 0 0 undefined 1 1 0 1 undefined 1 1 1 0 write command 1 1 1 1 write data cautions 1. because the slave unit must judge whether the received data is a ?command? or ?data?, read the value of the cdr register after completing communication. 2. if the master unit sets an undefined value, the slave unit returns the nack signal and communication is aborted. during broadcast communication, the master unit ignores the acknowledge bit and continues communication. therefore, do not set an undefined value.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 553 (c) slave status return operation when iebus receives a request to transfer from master to slave status or a lock address request (control data: 0h, 6h), whether the ack/nack signal in the control field is returned or not depends on the status of the iebus unit. (1) if 0h or 6h control data was received in the unlocked state ack signal returned (2) if 4h or 5h control data was received in the unlocked state nack signal returned (3) if 0h, 4h, 5h or 6h control data was received in the locked state from the unit that sent the lock request ack signal returned (4) if 0h, 4h, or 5h control data was received in the locked state from other than the unit that sent the lock request ack signal returned (5) if 6h control data was received in the locked state from other than the unit that sent the lock request nack signal returned in all of the above cases, the acknowledgement of a slave status or lock request will cause the statusf bit to be set (1) and the status interrupt signal (intie2, intsta) to be generated. the generation timing is at the end of the control field parity bit (at the start of the acknowledge bit). however, if nack is returned, a nack receive error is generated after the acknowledge bit, and communication is terminated. figure 18-16. interrupt request signal generation timing (for (1), (3), and (4)) intie2, intsta signal set by reception of 0h, 4h, 5h, 6h iebus sequence cleared by software control field telegraph length field statusf bit internal nack flag 0 control bits (4 bits) parity bit (1 bit) acknowledge bit (1 bit) telegraph length bits (8 bits)
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 554 figure 18-17. interrupt request signal generation timing (for (2) and (5)) intie2 intsta interr set by reception of 0h, 4h, 5h, 6h iebus sequence cleared by software set by detection of nack signal control field statusf bit internal nack flag control bit (4 bits) parity bit (1 bit) acknowledge bit (1 bit) terminated by communication error because in (4) and (5) the communication was from other than the unit that sent the lock request while iebus was in the locked state, the start or communication end interrupt request signals (intie2, intsta) are not generated, even if the iebus unit is the communication target. the statusf bit is set (1) and the status interrupt request signals (intie2, intsta) are generated, however, if a slave status or lock address request is acknowledged. note that even if the same control data is received while iebus is in the locked state, the interrupt generation timing for intie2 and intsta differs depending on whether the master unit (3) or another unit (4) is requesting the locked state. figure 18-18. timing of intie2 and intsta interrupt request signal generation in locked state (for (4) and (5)) intie2, intsta iebus sequence status interrupt start master address (12 + p) broad- cast slave address (12 + p + a) control (4 + p + a) telegraph length note (8 + p + a) data note (8 + p + a) note the telegraph length and data modes are not set in the case of (5) because the nack signal is returned. remark p: parity bit, a: acknowledge bit
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 555 figure 18-19. timing of intie2 and intsta interrupt request signal generation in locked state (for (3)) intie2, intsta iebus sequence status interrupt start master address (12 + p) broad- cast slave address (12 + p + a) control (4 + p + a) telegraph length (8 + p + a) communication end interrupt data (8 + p + a) start interrupt remark p: parity bit, a: acknowledge bit
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 556 (12) iebus telegraph length register (dlr) the dlr register can be read or written in 8-bit units. reset input sets this register to 01h. (a) when transmission unit ... master transmission, slave transmission the data of this register is reflected in the data transmitted in the telegraph length field and indicates the number of bytes of the transmit data. the dlr register must be set in advance before transmission. (b) when reception unit ... master reception, slave reception the receive data in the telegraph length field transmitted from the transmission unit is written to this register. remark the dlr register consists of a write register and a read register. consequently, data written to this register cannot be read as is. the data that can be read is the data received during iebus communication. after reset: 01h r/w address: fffff36fh 76543210 dlr bit 76543210 setting value remaining number of communication data bytes 0 0 0 0 0 0 0 1 01h 1 byte 0 0 0 0 0 0 1 0 02h 2 bytes :::::::: : : 0 0 1 0 0 0 0 0 20h 32 bytes :::::::: : : 1 1 1 1 1 1 1 1 ffh 255 bytes 0 0 0 0 0 0 0 0 00h 256 bytes cautions 1. when the master issues a request (0h, 4h, 5h, or 6h) for transmission of a slave status or a lock address (higher 4 bits and lower 8 bits), 01h is transmitted as the telegraph length regardless of the contents of the dlr register. it is therefore not necessary to set the dlr register by software. 2. when the iebus controller serves as a receiver unit, the dlr register stores a telegraph length if the value of the parity bit of the telegraph length field is correct. if the dlr register is read at this time, an undefined value is read.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 557 (13) iebus data register (dr) the dr register sets the communication data (8 bits) to bits 7 to 0. this register can be read or written in 8-bit units. reset input clears this register to 00h. remark the dr register consists of a write register and a read register. consequently, data written to this register cannot be read as is. the data that can be read is the data received during iebus communication. (a) when transmission unit the data (1 byte) written to the dr register is stored in the transmit shift register of the iebus interface block. it is then output from the most significant bit, and an interrupt request signal (intie1) is generated each time 1 byte has been transmitted. if the nack signal is received after 1-byte data has been transferred during individual transfer, data is not transferred from the dr register to the transmit shift register, and the same data is retransmitted. at this time, intie1 signal is not generated. intie1 signal is generated when the transmit shift register stores the dr register value. however, when the last byte and 32nd byte (the last byte of 1 communication frame) is stored in the transmit shift register, the intie1 signal is not generated. (b) when reception unit one byte of the data received by the receive shift register of the iebus interface block is stored in this register. each time 1 byte has been correctly received, an interrupt request signal (intie1) is generated. when transmit/receive data is transferred to and from the dr register, using dma can reduce the cpu processing load. after reset: 00h r/w address: fffff370h 76543210 dr cautions 1. if the next data is not in time while the transmission unit is set, an underrun occurs, and a communication error interrupt request signal (intie2, interr) occurs, stopping transmission. 2. if data is not read in time before the next data is read when the iebus controller functions as a receiver unit during individual communication reception, the nack signal is returned by the acknowledge bit of the data field, requesting the master to retransmit the data. if the dr register is not read after the data has reached the maximum number of transmit bytes, however, the frame end interrupt request signal (intie2, intsta) and nack reception error interrupt request signal (intie2, interr) are generated at the same time. 3. if data is not read in time before the next data is received when the iebus controller functions as a receiver unit during broadcast communication reception, an overrun error occurs and the communication error interrupt request signal (intie2, interr) is generated. 4. when the iebus controller serves as a receiver unit, the dr register stores receive data if the value of the parity bit of the data field is correct. if the dr register is read at this time, an undefined value is read.
chapter 18 iebus controller preliminary user?s manual u16541ej1v0um 558 (14) iebus field status register (fsr) the fsr register stores the status of the field status of the iebus controller if an interrupt request signal (intie1, intie2, intsta, or interr) is generated. this register is read-only, in 8-bit units. reset input clears this register to 00h. cautions 1. if an interrupt request signal is generated during communication between third parties, the fsr register is cleared to 00h. however, because only an interrupt request signal that is generated if an error occurs is generated during communication between third parties, the error can be identified as that during communication between third parties, by reading third-party error flag (esr.deflag bit). 2. the fsr register updates the status information when an interrupt request signal is generated. if the fsr register is read at this time, however, an undefined value is read. 3. if another interrupt request signal is generated before the fsr register is read, the status information when the preceding interrupt occurred is updated by the status information when the new interrupt occurs. 4. use the fsr register only for problem analysis; do not use it with the actual software. 0 fsr 0 0 0 00 fstate1 fstate0 after reset: 00h r address: fffff371h 6543210 7 remark for the explanation of the fstate1 and fstate0 bits, refer to table 18-15 field status . table 18-15. field status explanation field status master/slave field transmission/reception start field master address field slave address field control data field telegraph length field slave transmission status fsr = 00h slave operation data field reception telegraph length field slave transmission status fsr = 01h slave operation data field transmission telegraph length field master reception status fsr = 02h master operation data field reception start field master address field slave address field control data field telegraph length field master transmission status fsr = 03h master operation data field transmission
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 559 (15) iebus success count register (scr) the scr register indicates the number of remaining communication bytes. the count value of the counter in which the value set by the dlr register is decremented by the ack signal in the data field is read from this register. when the count value has reached ? 00h ? , the communication end flag (isr.endtrns bit) is set (1). after reset: 01h r address: fffff372h 76543210 scr bit 76543210 setting value remaining number of communication data bytes 0 0 0 0 0 0 0 1 01h 1 byte 0 0 0 0 0 0 1 0 02h 2 bytes :::::::: : : 0 0 1 0 0 0 0 0 20h 32 bytes :::::::: : : 1 1 1 1 1 1 1 1 ffh 255 bytes 00000000 00h 0 bytes (end of communication) or 256 bytes note note the actual counter consists of 9 bits. when ? 00h ? is read, it cannot be judged whether the remaining number of communication data bytes is 0 (end of communication) or 256. therefore, either the communication end flag (endtrns bit) is used, or if ? 00h ? is read when the first interrupt occurs at the beginning of communication, the remaining number of communication data bytes is judged to be 256. caution the scr register is updated when the parity period of the telegraph field expires and when the ack signal of the data field is received. if the scr register is read at this time, however, an undefined value is read.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 560 (16) iebus communication count register (ccr) the ccr register indicates the number of bytes remaining from the communication byte number specified by the communication mode. this register indicates the number of transfer bytes. the maximum number of transmitted bytes per frame defined in each mode (mode 1: 32 bytes, mode 2: 128 bytes) is preset to this register. the count value of the counter that is decremented during the acknowledge bit period of the data field regardless of the ack/nack signal is read from this register. whereas the scr register is decremented during normal communication (ack signal), the ccr register is decremented when 1 byte has been communicated, regardless of whether the signal is ack or nack. when the count value has reached ? 00h ? , the frame end flag (isr.endfram bit) is set (1). the preset value of the maximum number of transmitted bytes per frame is 20h (32 bytes) in mode 1 and 80h (128 bytes) in mode 2. this register is read-only, in 8-bit units. reset input sets this register to 20h. after reset: 20h r address: fffff373h 76543210 ccr caution the maximum number of transmit bytes is preset to the ccr register when the start bit is transmitted or received, and the register is decremented when the parity period of the data field expires. if the ccr register is read at this time, however, an undefined value is read.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 561 (17) iebus clock select register (ocks2) the ocks2 register selects the clock of iebus. the main clock frequencies that can be used are shown below. no other main clock frequencies can be used. this register can be read or written in 8-bit units. reset input clears this register to 00h. ? 6.0 mhz/6.291 mhz ? 12.0 mhz/12.582 mhz ? 18.0 mhz/18.873 mhz 0 iebus clock operation stops 5 iebus clock operation enabled ocksen2 0 1 iebus clock operation specification ocks2 0 0 ocksen2 0 ocks22 ocks21 ocks20 f xx /2 (when f xx = 12.0 mhz or f xx = 12.852 mhz) f xx /3 (when f xx = 18.0 mhz or f xx = 18.873 mhz) f xx (when f xx = 6.0 mhz or f xx = 6.291 mhz) setting prohibited ocks22 0 0 1 ocks21 0 0 0 ocks20 0 1 0 iebus clock selection other than above after reset: 00h r/w address: fffff348h 6543210 7
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 562 18.4 interrupt operations of iebus controller 18.4.1 interrupt control block interrupt request signal <1> communication error ieerr (i) timing error: terr (ii) parity error: perr (iii) nack receive error: nerr (iv) underrun error: uerr (v) overrun error: oerr (vi) write error: werr <2> start interrupt startf <3> status communication statusf <4> end of communication endtrns <5> end of frame endfram <6> transmit data write request stattx <7> receive data read request statrx a communication error <1> occurs if any of the above error sources (i) to (vi) is generated. these error sources are assigned to the error status register (esr) (refer to table 18-18 communication error source processing list ). the above interrupt signals <1> to <5> are assigned to the isr register (refer to table 18-17 interrupt source list ). the configuration of the interrupt control block is illustrated below.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 563 figure 18-20. configuration of interrupt control block intsta intie1 interr intie2 intc of v850es/sg2 interrupt control block iebus controller startf statusf endtrns endfram stattx statrx terr perr nerr uerr oerr werr cautions 1. the logical sum (or) output of the statrx and stattx signals is treated as an interrupt request signal (intie1). 2. the logical sum (or) output of the terr, perr, nerr, uerr, oerr, and werr signals is treated as a communication error (ieerr) or an interrupt request signal (interr). 3. the logical sum (or) output of the startf, statusf, endtrns, and endfram signals is treated as an interrupt request signal (intsta). 4. the logical sum (or) output of the ieerr, startf, statusf, endtrns, and endfram signals (logical sum (or) output of intsta and interr signals) is treated as an interrupt request signal (intie2). table 18-16. interrupt request signal generation source list interrupt request signal interrupt source symbol intie1 intie2 interr intsta communication error interrupt ieerr timing error terr parity error perr nack reception error nerr underrun error uerr overrun error oerr write error werr ? start interrupt startf ? status transmission statusf ? end of communication endtrns ? end of frame endfram ? transmit data write request stattx receive data write request statrx
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 564 18.4.2 example of identifying interrupt the iebus controller processes interrupts in the following two ways. ? using three interrupt request signals: intie1, interr, and intsta ? using two interrupt request signals: intie1 and intie2 caution mask the interrupt sources that are not used so that the interrupts do not occur. how an interrupt is identified in each of the above cases is explained below. (1) when intie1, interr, and intsta signals are used figure 18-21. example of identifying intie1 signal interrupt (when intie1, interr, and intsta signals are used) transmission write processing intie1 signal generated reception read processing master transmission or slave transmission yes no figure 18 - 22. example of identifying interr signal interrupt (when intie1, interr, and intsta signals are used) interr signal generated esr register teer bit peer bit neer bit ueer bit oeer bit weer bit error source identification
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 565 figure 18-23. example of identifying intsta signal interrupt (when intie1, interr, and intsta signals are used) intsta signal generated isr register ssr register startf bit start interrupt occurs cdr register statusf bit endtrns bit communication end identification endfram bit frame end identification status transmission identification status transmission processing arbitration loss detection arbit bit remaster processing 00h, 06h writing ssr register to dr register 04h writing lower 8 bits of par register to dr register 05h writing higher 4 bits of par register to dr register slvrq bit slave request identification (2) when intie1 and intie2 signals are used figure 18-24. example of identifying intie1 signal interrupt (when intie1 and intie2 signals are used) transmission write processing intie1 signal generated reception read processing master transmission or slave transmission yes no
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 566 figure 18-25. example of identifying intie2 signal interrupt (when intie1 and intie2 signals are used) intie2 signal generated isr register ssr register startf bit ieerr bit start interrupt occurs communication error identification cdr register statusf bit endtrns bit communication end identification endfram bit frame end identification status transmission identification status transmission processing arbitration loss detection arbit bit remaster processing 00h, 06h 04h 05h slvrq bit slave request identification esr register teer bit peer bit neer bit ueer bit oeer bit weer bit error source identification writing ssr register to dr register writing lower 8 bits of par register to dr register writing higher 4 bits of par register to dr register
chapter 18 iebus controller preliminary user?s manual u16541ej1v0um 567 18.4.3 interrupt source list the interrupt request signals of the internal iebus controller in the v850es/sg2 can be classified into vector interrupts and dma transfer interrupts. these interrupt request signals can be specified via software manipulation. the interrupt sources are listed below. table 18-17. interrupt source list condition of generation interrupt source unit field software processing after generation of interrupt request signal remark timing error master/slave all fields other than data (individual) parity error reception all fields (broadcast) nack reception reception (transmission) other than data (individual) underrun error transmission data overrun error reception data (broadcast) communication error write error transmission data undo communication processing communication error is logical sum (or) output of timing error, parity error, nack reception error, underrun error, overrun error, and write error. master slave/address slave request judgment arbitration judgment (if lost, remaster processing) communication preparation processing interrupt always occurs if lost in arbitration during master request start interrupt slave slave/address slave request judgment communication preparation processing generated only during slave request status transmission slave control refer to transmission processing example such as slave status. interrupt occurs regardless of slave transmission enable flag interrupt occurs if nack is returned in the control field. transmission data dma transfer end processing end of communication reception data dma transfer end processing receive data processing set if scr register is cleared to 00h transmission data retransmission preparation processing end of frame reception data re-reception preparation processing set if ccr register is cleared to 00h transmit data write transmission data reading of transmit data note set after transfer transmission data to internal shift register this does not occur when the last data is transferred. receive data read reception data reading of received data note set after normal data reception note if dma transfer or software manipulation is not executed.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 568 18.4.4 communication error source processing list the following table shows the occurrence conditions of the communication errors (timing error, nack reception error, overrun error, underrun error, parity error, and write error), error processing by the iebus controller, and examples of processing by software. table 18-18. communication error source processing list (1/2) timing error unit status reception transmission occurrence condition if bit specification timing is not correct occurrence condition location of occurrence other than data field data field other than data field data field hardware processing reception stops. intie2 signal occurs to start bit waiting status remark communication between other units does not end. transmission stops. intie2 signal occurs to start bit waiting status broadcast communication software processing error processing (such as retransmission request) error processing (such as retransmission request) hardware processing reception stops. intie2 signal occurs nack signal is returned. to start bit waiting status transmission stops. intie2 signal occurs to start bit waiting status individual communication software processing error processing (such as retransmission request) error processing (such as retransmission request) nack reception error unit status reception transmission occurrence condition unit nack signal transmission unit nack signal transmission occurrence condition location of occurrence other than data field data field other than data field data field nack signal reception of data of 32nd byte hardware processing ????? broadcast communication software processing ????? hardware processing reception stops. intie2 signal occurs. to start bit waiting status intie2 signal does not occur. data retransmitted by other unit is received. reception stops. intie2 signal occurs. to start bit waiting status intie2 signal does not occur. retrans- mission processing intie2 signal occurs. to start bit waiting status individual communication software processing error processing (such as retransmission request) ? error processing (such as retransmission request) ? error processing (such as retransmission request)
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 569 table 18-18. communication error source processing list (2/2) overrun error underrun error/write error unit status reception transmission occurrence condition dr register cannot be read in time before the next data is received. dr register cannot be written in time before the next data is transmitted. occurrence condition location of occurrence other than data field data field other than data field data field hardware processing ? reception stops. intie2 signal occurs. to start bit waiting status remarks 1. communication between other units does not end. 2. data cannot be received until the overrun status is cleared. ? transmission stops. intie2 signal occurs. to start bit waiting status broadcast communication software processing ? dr register is read and overrun status is cleared. error processing (such as retransmission request) ? error processing (such as retransmission request) hardware processing ? intie2 signal does not occur. nack signal is returned. data is retransmitted from other unit. remark data cannot be received until overrun status is cleared. ? transmission stops. intie2 signal occurs. to start bit waiting status individual communication software processing ? dr register is read and overrun status is cleared. error processing (such as retransmission request) ? error processing (such as retransmission request) parity error unit status reception transmission occurrence condition received data and received parity do not match. ? occurrence condition location of occurrence other than data field data field other than data field data field hardware processing reception stops. intie2 signal occurs. to start bit waiting status remark communication between other units does not end. ?? broadcast communication software processing error processing (such as retransmission request) ?? hardware processing reception stops. intie2 signal occurs. to start bit waiting status reception does not stop. intie2 signal does not occur. nack signal is returned. data retransmitted by other unit is received. ?? individual communication software processing error processing (such as retransmission request) ???
chapter 18 iebus controller preliminary user?s manual u16541ej1v0um 570 18.5 interrupt request signal generation timing and main cpu processing 18.5.1 master transmission initial preparation processing: sets a unit address, slave address, control data, telegraph length, and the first byte of the transmit data. communication start processing: set the bcr register (enable communication, master request, and slave reception). figure 18-26. master transmission start broad- cast m address p s address p a control p a telegraph length p a data 1 pa data 1 data 2 p a data n ? 1pa data n p a <1> <2> approx. 624 s (mode 1, at 6.29 mhz) approx. 390 s (mode 1, at 6.29 mhz) <1> interrupt request signal (intie2, intsta) occurrence judgment of occurrence of error note error processing judgment of slave request slave reception processing (see 18.5.1 (1) slave reception processing ) judgment of arbitration result remaster request processing <2> interrupt request signal (intie2, intsta) occurrence judgment of occurrence of error note error processing judgment of end of communication end of communication processing judgment of end of frame recommunication processing (see 18.5.1 (3) recommunication processing ) note this processing is necessary only when the intie2 interrupt request signal is used as the start interrupt, and is not necessary when the intsta interrupt request signal is used (in this case, the error processing is performed by using the interr interrupt request signal). remarks 1. : interrupt request signal (intie1) occurrence (see 18.5.1 (2) interrupt request signal (intie1) occurrence ) the transmit data of the second and subsequent bytes is written to the dr register by dma transfer. at this time, the data transfer direction is ram on-chip peripheral i/o 2. : an interrupt request signal (intie1) does not occur. 3. n = final number of data bytes
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 571 (1) slave reception processing if a slave reception request is confirmed during vector interrupt servicing, the data transfer direction of the macro service must change from ram on-chip peripheral i/o to on-chip peripheral i/o ram until the first data is received. the maximum pending period of this data transfer direction changing processing is about 1,040 s in communication mode 1 (at 6.29 mhz). (2) interrupt request signal (intie1) occurrence if the nack signal is received from the slave in the data field, an interrupt request signal (intie1) is not issued to the interrupt controller (intc), and the same data is retransmitted by hardware. if the transmit data is not written in time during the period of writing the next data, a communication error interrupt request signal (interr) occurs due to occurrence of underrun, and communication ends midway. (3) recommunication processing in the vector interrupt servicing in <2>, it is judged whether the data has been correctly transmitted within one frame. if the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remainder of the data must be transmitted.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 572 18.5.2 master reception before performing master reception, it is necessary to notify the unit that will be the slave of slave transmission. therefore, more than two communication frames are necessary for master reception. the slave unit prepares the transmit data, sets (1) the slave transmission enable flag (bcr.enslvtx bit), and waits. initial preparation processing: set a unit address, slave address, and control data. communication start processing: set the bcr register (enable communication and master request). figure 18-27. master reception approx. 1,014 s (mode 1, at 6.29 mhz) start broad- cast m address p s address p a control a p telegraph length a p data 1 approx. 390 s (mode 1, at 6.29 mhz) data 1 p a data 2 p a data n ? 1 p a data n p a < 2 > < 1 > <1> interrupt request signal (intie2, intsta) occurrence judgment of occurrence of error note error processing judgment of slave request slave processing judgment of arbitration result remaster request processing <2> interrupt request signal (intie2, intsta) occurrence judgment of occurrence of error note error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 18.5.2 (2) frame end processing ) note this processing is necessary only when the intie2 interrupt request signal is used as the start interrupt, and is not necessary when the intsta interrupt request signal is used (in this case, the error processing is performed by using the interr interrupt request signal). remarks 1. : interrupt request signal (intie1) occurrence (see 18.5.2 (1) interrupt request signal (intie1) occurrence ) the receive data stored in the dr register is read by dma transfer. at this time, the data transfer direction is on-chip peripheral i/o ram. 2. n = final number of data bytes
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 573 (1) interrupt request signal (intie1) occurrence if the nack signal is transmitted (hardware processing) in the data field, an interrupt request signal (intie1) is not issued to the intc, and the same data is retransmitted from the slave. if the receive data is not read by the time the next data is received, the hardware automatically transmits the nack signal. (2) frame end processing in the vector interrupt servicing in <2>, it is judged whether the data has been correctly received within one frame. if the data has not been correctly received (if the number of data to be received in one frame could not be received), a request to retransmit the data must be made to the slave in the next communication frame.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 574 18.5.3 slave transmission initial preparation processing: set a unit address, telegraph length, and the first byte of the transmit data. communication start processing: set the bcr register (enable communication, slave transmission, and slave reception). figure 18-28. slave transmission start m address p s address p a control p a data 1 pa data 1 data 2 p a data n ? 1pa data n p a <1> <2> pa approx. 390 s (mode 1, at 6.29 mhz) approx. 624 s (mode 1, at 6.29 mhz) broad- cast telegraph length <1> interrupt request signal (intie2, intsta) occurrence judgment of occurrence of error note error processing judgment of slave request <2> interrupt request signal (intie2, intsta) occurrence judgment of occurrence of error note error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 18.5.3 (2) frame end processing ) note this processing is necessary only when the intie2 interrupt request signal is used as the start interrupt, and is not necessary when the intsta interrupt request signal is used (in this case, the error processing is performed by using the interr interrupt request signal). remarks 1. : interrupt request signal (intie1) occurrence (see 18.5.3 (1) interrupt request signal (intie1) occurrence ). the transmit data of the second and subsequent bytes is written to the dr register by dma transfer. at this time, the data transfer direction is ram on-chip peripheral i/o. 2. : an interrupt request signal (intie1) does not occur. 3. : interrupt request signal (intie2) occurrence an interrupt request signal occurs only when 0h, 4h, 5h, or 6h is received in the control field in the slave status (for the slave status response operation during the locked status, refer to 18.3 (11) iebus control data register (cdr) ). 4. n = final number of data bytes
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 575 (1) interrupt request signal (intie1) occurrence if the nack signal is received from the master in the data field, an interrupt request signal (intie1) is not issued to the intc, and the same data is retransmitted by hardware. if the transmit data is not written in time during the period of writing the next data, a communication error interrupt request signal (interr) occurs due to occurrence of underrun, and communication is abnormally ended. (2) frame end processing in the vector interrupt servicing in <2>, it is judged whether the data has been correctly transmitted within one frame. if the data has not been correctly transmitted (if the number of data to be transmitted in one frame could not be transmitted), the data must be retransmitted in the next frame, or the remaining data must be transmitted.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 576 18.5.4 slave reception initial preparation processing: set a unit address. communication start processing: set the bcr register (enable communication, disables slave transmission, and enables slave reception). figure 18-29. slave reception start m address p s address p a control p a data 1 pa data 1 data 2 p a data n ? 1pa data n p a <1> pa <2> approx. 390 s (mode 1, at 6.29 mhz) approx. 1,014 s (mode 1, at 6.29 mhz) broad- cast telegraph length <1> interrupt request signal (intie2, intsta) occurrence judgment of occurrence of error note error processing judgment of slave request slave processing <2> interrupt request signal (intie2, intsta) occurrence judgment of occurrence of error note error processing judgment of end of communication end of communication processing judgment of end of frame frame end processing (see 18.5.4 (2) frame end processing ). note this processing is necessary only when the intie2 interrupt request signal is used as the start interrupt, and is not necessary when the intsta interrupt request signal is used (in this case, the error processing is performed by using the interr interrupt request signal). remarks 1. : interrupt request signal (intie1) occurrence (see 18.5.4 (1) interrupt request signal (intie1) occurrence ). the receive data stored in the dr register is read by dma transfer. at this time, the data transfer direction is on-chip peripheral i/o ram. 2. n = final number of data bytes
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 577 (1) interrupt request signal (intie1) occurrence if the nack signal is transmitted in the data field, an interrupt request signal (intie1) is not issued to the intc, and the same data is retransmitted from the master. if the receive data is not read by the time the next data is received, the nack signal is automatically transmitted. (2) frame end processing in the vector interrupt servicing in <2>, it is judged whether the data has been correctly received within one frame.
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 578 18.5.5 interval of occurrence of interrupt request signal for iebus control each control interrupt request signal must occur at each point of communication and perform the necessary processing until the next interrupt request signal occurs. therefore, the iebus control block is controlled by software, taking the shortest time of this interrupt request signal occurrence interval into consideration. the locations at which the following interrupt request signals may occur are indicated by in the field where it may occur. does not mean that the interrupt request signal occurs at each of the points indicated by . if an error interrupt request signal (timing error, parity error, or nack receive error) occurs, the iebus internal circuit is initialized. as a result, the following interrupt request signal does not occur in that communication frame. (1) master transmission figure 18-30. master transmission (interval of interrupt request signal occurrence) start bit t t1 t broad- cast master address t t2 p slave address t pa at t t3 control p a a t4 tat telegraph length p a data p a communication starts communication start interrupt pa data data a p data tt t4 end of communication end of frame u u t5 a remarks 1. t: timing error a: nack receive error u: underrun error : data set interrupt (intie1) 2. end of frame occurs at the end of 32-byte data. values in parentheses indicate min. value (iebus: mode 1, at 6.29 mhz). t1: communication starts timing error (approx. 93 s) t2: communication starts communication start interrupt (approx. 1,282 s) t3: communication start interrupt timing error (approx. 15 s t4: communication start interrupt end of communication (approx. 1,012 s) t5: transmission data request interrupt interval (approx. 375 s)
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 579 (2) master reception figure 18-31. master reception (interval of interrupt request signal occurrence) pa pa pa pa pa p a data data data p t1 t communication starts start bit broad- cast master address slave address control telegraph length data tt a end of communication end of frame communication start interrupt tt t t t at t4 t4 t5 t2 a p t a t3 remarks 1. t: timing error p: parity error a: nack receive error : data set interrupt request signal (intie1) 2. end of frame occurs at the end of 32-byte data. values in parentheses indicate min. value (iebus: mode 1, at 6.29 mhz). t1: communication starts timing error (approx. 93 s) t2: communication starts communication start interrupt (approx. 1,282 s) t3: communication start interrupt timing error (approx. 15 s) t4: communication start interrupt end of communication (approx. 1,012 s) t5: receive data read interval (approx. 375 s)
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 580 (3) slave transmission figure 18-32. slave transmission (interval of interrupt request signal occurrence) pa pa pa pa pa pa p t1 t tt u u tt t p p t t tt at t5 t4 t3 t6 t7 t7 t2 a p a communication starts end of communication end of frame communication start interrupt status request data data data start bit broad- cast master address slave address control data telegraph length remarks 1. t: timing error p: parity error a: nack receive error u: underrun error : data set interrupt request signal (intie1) 2. end of frame occurs at the end of 32-byte data. values in parentheses indicate min. value (iebus: mode 1, at 6.29 mhz). t1: communication starts timing error (approx. 96 s) t2: communication starts communication start interrupt (approx. 1,192 s) t3: communication start interrupt timing error (approx. 15 s) t4: communication start interrupt status request (approx. 225 s) t5: transmission data request interrupt interval (approx. 375 s) t6: status request timing error (approx. 15 s) t7: status request end of communication (approx. 787 s)
chapter 18 iebus controller preliminary user ? s manual u16541ej1v0um 581 (4) slave reception figure 18-33. slave reception (interval of interrupt request signal occurrence) pa pa pa pa pa p a p t1 t tt tt t p p tt at t4 t4 t5 t2 p a pt a t3 p o a p o p start bit data data data end of communication end of frame communication start interrupt communication starts broad- cast master address slave address control data telegraph length remarks 1. t: timing error p: parity error a: nack receive error o: overrun error : data set interrupt request signal (intie1) 2. end of frame occurs at the end of 32-byte data. values in parentheses indicate min. value (iebus: mode 1, at 6.29 mhz). t1: communication starts timing error (approx. 96 s) t2: communication starts communication start interrupt (approx. 1,192 s) t3: communication start interrupt timing error (approx. 15 s) t4: communication start interrupt end of communication (approx. 1,012 s) t5: receive data read interval (approx. 375 s)
preliminary user?s manual u16541ej1v0um 582 chapter 19 can controller 19.1 outline the v850es/sg2 features an on-chip 1-channel can (controller area network) controller that complies with the can protocol as standardized in iso 11898. the v850es/sg2 products with an on-chip can controller are as follows. ? pd703280, 703280y, 703281, 703281y, 703282, 703282y, 703283, 703283y, 70f3281, 70f3281y, 70f3283, 70f3283y 19.1.1 features ? compliant with iso 11898 and tested according to iso dis 16845 ? standard frame and expanded frame transmission/reception enabled ? transfer rate: 1 mbps max. ? 32 message buffers/channel ? receive/transmit history list function ? automatic block transmission function ? multi-buffer receive block function ? mask setting of four patterns is possible for each channel.
chapter 19 can controller preliminary user?s manual u16541ej1v0um 583 19.1.2 overview of functions table 19-1 presents an overview of can controller functions. table 19-1. overview of functions function description protocol can protocol iso 11898 (standard and extended frame transmission/reception) baud rate maximum 1 mbps (@can clock input 8 mhz) data storage 32 message buffers/channel each message buffer can be set to be either a transmit message buffer or a receive message buffer. message reception ? unique id can be set in each message buffer. ? mask setting of four patterns is possible for each channel. ? can receive interrupt after each message storage ? buffers for reception can be used to form a multi-buffer receive fifo (multi-buffer receive block function). ? receive history list function message transmission ? unique id can be set in each message buffer. ? can transmit completion interrupt for each message ? message buffers #0-7 appointed as the transmission message buffers for transmission in order of the buffer number including programmable delay between messages (automatic block transmission function). ? transmit history list function remote frame processing ? remote frame handling by message buffer defined for transmit time stamp functions ? a time stamp function can be set for receive messages. ? trigger for time stamp capture selectable (sof or eof detection in a can message frame) ? a time stamp function can be set for transmit messages. ? specific bytes in the data field are replaced by the captured time stamp. diagnostics ? readable error counters ? ?valid protocol operation flag? for verification of bus connections ? receive-only mode ? single-shot mode ? can protocol error type decoding ? self-test mode including self-reception power save modes ? can sleep mode (wakeup function using can bus enabled) ? can stop mode (wakeup function using can bus disabled)
chapter 19 can controller preliminary user?s manual u16541ej1v0um 584 19.1.3 configuration the can controller is composed of the following four blocks. (1) npb interface this functional block provides an npb (nec peripheral i/o bus) interface and a means of transmitting and receiving signals between the can and the host cpu. (2) mac (memory access controller) this functional block controls access to the can protocol layer and to the can ram within the can module. (3) can protocol layer this functional block is involved in the operation of the can protocol and its related settings. (4) can ram this is the can memory functional block, which is used to store message ids, message data, etc. figure 19-1. block diagram of can module cantx canrx cpu can controller can ram npb (nec peripheral i/o bus) mac (memory access controller) npb interface interrupt request intc0trx intc0rec intc0err intc0wup can protocol layer can transceiver message buffer 0 message buffer 1 message buffer 2 message buffer 3 message buffer 31 c1mask1 c1mask2 c1mask3 c1mask4 ... can_h can_l can bus
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 585 19.2 can protocol can (controller area network) is a high-speed multiplex communication protocol for real-time communication in automotive applications (class c). can is prescribed by iso 11898. for details, refer to the iso 11898 specifications. the can specification is generally divided into two layers: a physical layer and a data link layer. in turn, the data link layer includes logical link control and medium access control. the composition of these layers is illustrated below. figure 19-2. composition of layers physical layer prescription of signal level and bit description data link layer note logical link control (llc) medium access control (mac) acceptance filtering overload report recovery management data capsuled/not capsuled frame coding (stuffing/not stuffing) medium access management error detection error report acknowledgement seriated/not seriated higher lower note can controller specification 19.2.1 frame format (1) standard format frame in this format, 2048 different identifiers can be set. ? the standard format frame uses 11-bit identifiers, which means that it can handle up to 2048 messages. (2) extended format frame this format is used to set identifiers of approx. 5.3 million types. ? the extended format frame uses 29-bit (11 bits + 18 bits) identifiers which increase the number of messages that can be handled to 2048 2 18 messages. ? extended format frame is set when ? recessive level ? (cmos level equals ? 1 ? ) is set for both the srr and ide bits in the arbitration field.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 586 19.2.2 frame types the following four types of frames are used in the can protocol. table 19-2. frame types frame type description data frame frame used to transmit data remote frame frame used to request a data frame error frame frame used to report error detection overload frame frame used to delay the next data frame or remote frame (1) bus value the bus values are divided into dominant and recessive. ? dominant level is indicated by logical 0. ? recessive level is indicated by logical 1. ? when a dominant level and a recessive level are transmitted simultaneously, the bus value becomes dominant level. 19.2.3 data frame and remote frame (1) data frame a data frame is composed of seven fields. figure 19-3. data frame r d interframe space end of frame (eof) ack field crc field data field control field arbitration field start of frame (sof) data frame <1> <2> <3> <4> <5> <6> <7> <8> remark d: dominant = 0 r: recessive = 1
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 587 (2) remote frame a remote frame is composed of six fields. figure 19-4. remote frame r d interframe space end of frame (eof) ack field crc field control field arbitration field start of frame (sof) remote frame <1> <2> <3> <5> <6> <7> <8> remarks 1. the data field is not transferred even if the control field ? s data length code is not ? 0000b ? . 2. d: dominant = 0 r: recessive = 1 (3) description of fields <1> start of frame (sof) the start of frame field is located at the start of a data frame or remote frame. figure 19-5. start of frame (sof) r d 1 bit start of frame (interframe space or bus idle) (arbitration field) remark d: dominant = 0 r: recessive = 1 ? if dominant level is detected in the bus idle state, the start of frame is recognized. ? if recessive level is detected at the sample point of the start of frame, the preceding dominant level is judged as noise and the bus idle state is entered again.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 588 <2> arbitration field the arbitration field is used to evaluate the priority between data frames, remote frames, and frame formats (standard or extended identifier). figure 19-6. arbitration field (in standard format mode) r d ide (r1) r0 rtr identifier arbitration field (control field) (11 bits) id28 id18 (1 bit) (1 bit) remark d: dominant = 0 r: recessive = 1 figure 19-7. arbitration field (in extended format mode) r d r1 r0 rtr ide srr identifier identifier arbitration field (control field) (11 bits) (18 bits) id28 id18 id17 id0 (1 bit) (1 bit) (1 bit) cautions 1. id28 to id0 are identifier bits. 2. identifier bits are transferred in msb-first order. remark d: dominant = 0 r: recessive = 1 table 19-3. rtr frame settings frame type rtr bit data frame 0 (d) remote frame 1 (r) table 19-4. frame format setting (ide bit) and number of identifier (id) bits frame format srr bit ide bit no. of bits standard format mode none 0 (d) 11 bits extended format mode 1 (r) 1 (r) 29 bits
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 589 <3> control field the control field sets ? n ? as the number of data bytes in the data field (n = 0 to 8). figure 19-8. control field r d r1 (ide) r0 rtr dlc2 dlc3 dlc1 dlc0 control field (data field) (arbitration field) remark d: dominant = 0 r: recessive = 1 in a standard format frame, the control field ? s ide bit is the same as the r1 bit. table 19-5. data length code settings data length code dlc3 dlc2 dlc1 dlc0 data byte count 0000 0 bytes 0001 1 byte 0010 2 bytes 0011 3 bytes 0100 4 bytes 0101 5 bytes 0110 6 bytes 0111 7 bytes 1000 8 bytes other than above 8 bytes regardless of the value of dlc3 to dlc0 caution in the remote frame, there is no data field even if the data length code is not 0000b.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 590 <4> data field the data field contains the amount of data (byte units) set by the control field. up to 8 units of data can be set. figure 19-9. data field r d data (8 bits) data (8 bits) data field (crc field) (control field) remark d: dominant = 0 r: recessive = 1 <5> crc field the crc field is a 16-bit field that is used to check for errors in transmit data. figure 19-10. crc field r d crc sequence crc delimiter (1 bit) (15 bits) crc field (ack field) (data field or control field) remark d: dominant = 0 r: recessive = 1 ? the polynomial p(x) used to generate the 15-bit crc sequence is expressed as follows. p(x) = x 15 + x 14 + x 10 + x 8 + x 7 + x 4 + x 3 + 1 ? transmitting node: the crc sequence calculated from the data (before bit stuffing) in the start of frame, arbitration field, control field, and data field is transferred. ? receiving node: the crc sequence calculated using data bits that exclude the stuffing bits in the receive data is compared with the crc sequence in the crc field. if the two crc sequences do not match, the node issues an error frame.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 591 <6> ack field the ack field is used to confirm normal reception. figure 19-11. ack field r d ack slot (1 bit) ack delimiter (1 bit) ack field (end of frame) (crc field) remark d: dominant = 0 r: recessive = 1 ? if no crc error is detected, the receiving node sets the ack slot to the dominant level. ? the transmitting node outputs two recessive-level bits. <7> end of frame (eof) the end of frame field indicates the end of data frame/remote frame. figure 19-12. end of frame (eof) r d end of frame (7 bits) (interframe space or overload frame) (ack field) remark d: dominant = 0 r: recessive = 1
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 592 <8> interframe space the interframe space is inserted after a data frame, remote frame, error frame, or overload frame to separate one frame from the next. ? the length of this field differs depending on the error status. (a) error active node the error active node inserts a 3-bit intermission field before bus idle is encountered or another frame is transmitted. figure 19-13. interframe space (error active node) r d interframe space intermission (3 or 2 bits) bus idle (0 or more bits) (frame) (frame) remarks 1. bus idle: state in which the bus is not used by any node. 2. d: dominant = 0 r: recessive = 1 (b) error passive node the error passive node inserts a 3-bit intermission field, followed by a suspend transmission field before bus idle is encountered or another frame is transmitted. figure 19-14. interframe space (error passive node) r d interframe space intermission (3 or 2 bits) suspend transmission (8 bits) bus idle (0 or more bits) (frame) (frame) remarks 1. bus idle: state in which the bus is not used by any node. suspend transmission: sequence of 8 recessive bits transmitted from the node in the error passive status after the intermission field. 2. d: dominant = 0 r: recessive = 1
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 593 ? operation in error status table 19-6. operation in error status error status operation error active any node in this state is able to start a transmission whenever the bus is idle. error passive any node in this state has to wait for 11 consecutive recessive bits before initiating a transmission. ? operation when the third bit of the intermission field is dominant level table 19-7. operation when third bit of intermission is dominant level error status operation no pending transmissions a receive operation is performed when a start of frame output by another node is detected. pending transmission exists the identifier is transmitted when a start of frame output by the local node is detected.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 594 19.2.4 error frame ? this frame is sent from a node if an error is detected. ? the type of error frame is defined by its error flag: an active error flag or passive error flag. which kind of flag a node transmits after detecting an error condition depends on the internal count of the error counters of each node. figure 19-15. error frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame error delimiter error flag error flag error bit error frame remark d: dominant = 0 r: recessive = 1 table 19-8. definition of each field no. name bit count definition <1> error flag 6 error active node: sends 6 bits of dominant level continuously. error passive node: sends 6 bits of recessive level continuously. <2> error flag 0 to 6 nodes receiving an ? error flag ? detect bit stuff errors and issue error flags themselves. <3> error delimiter 8 sends 8 bits of recessive level continuously. in the case of monitoring the dominant level at the 8th bit, an overload frame is transmitted after the next bit. <4> erroneous bit ? an error frame is transmitted continuously after the bit where the error has occurred (in the case of a crc error, transmission continues after the ack delimiter). <5> interframe space/overload frame 3/14 20 max. interframe space or overload frame continues.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 595 19.2.5 overload frame an overload frame is transmitted under the following conditions. ? when the receiving node is not yet ready to receive. ? if a dominant level is detected at the first two bits in intermission mode. ? if a dominant level is detected at the last bit (8th bit) of the end of frame or at the last bit (8th bit) of the error delimiter/overload delimiter. figure 19-16. overload frame <1> r d <2> <3> 6 bits 0 to 6 bits 8 bits (<4>) (<5>) interframe space or overload frame overload delimiter overload flag (node n) overload flag (node m) frame overload frame remarks 1. node n/node m: each node (n m) 2. d: dominant = 0 r: recessive = 1 table 19-9. field definition of overload frame no name bit count definition <1> overload flag starting from node m 6 consecutive output of 6 dominant-level bits. output when node m is not ready to receive. <2> overload flag starting from node n 0 to 6 node n, which has received an overload flag in the interframe space, outputs an overload flag. <3> overload delimiter 8 consecutive output of 8 recessive-level bits. if a dominant level is detected at the eighth bit, an overload frame is sent starting at the next bit. <4> frame ? output following an end of frame, error delimiter, or overload delimiter. <5> interframe space or overload frame ? an interframe space or overload frame starts from here. remark node n/node m: each node (n m)
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 596 19.3 functions 19.3.1 arbitration if two or more nodes happen to start transmission at the same time, the access conflict is solved by a bit-wise arbitration mechanism during transmission of the arbitration field. (1) when a node starts transmission during bus idle, the node having the output data can transmit. (2) when more than one node starts transmission the node with the lower identifier wins the arbitration. the transmitting node compares its output arbitration field and the data level on the bus. it loses arbitration when it sends a recessive level and reads a dominant level from the bus. table 19-10. arbitration level detection status of node in arbitration conformity of level continuous transmission non-conformity of level the data output is stopped from the next bit and reception operation starts (3) priority of data frame and remote frame when a data frame and remote frame with the same message identifier are on the bus, the data frame has priority because its rtr bit carries a ? dominant level ? . the data frame wins the arbitration.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 597 19.3.2 bit stuffing when the same level continues for more than 5 bits, bit stuffing (inserting 1 bit with the inverse level) takes place. due to this, resynchronization of the bit timing can be done at least every 10 bits. nodes detecting an error condition send an error frame without implementing the bit stuffing rule, indicating this message to be erroneous for all nodes. table 19-11. bit stuffing transmission during the transmission of a data frame and a remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, 1 bit level with inverse-level data is inserted before the following bit. reception during the reception of a data frame and a remote frame, when the same level continues for 5 bits in the data between the start of frame and the ack field, the reception is continued by deleting the next bit. 19.3.3 multi masters as the bus priority is determined by the identifier, any node can be the bus master. 19.3.4 multi cast any message can be received by any node (broadcast). 19.3.5 sleep mode/stop function this is a function to put the can controller in waiting mode to achieve low power consumption. the sleep mode of the can complies with the method described in iso 11898. the can sleep mode can be woken up by bus operation, but the can stop mode is fully controlled by the cpu device.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 598 19.3.6 error control function (1) error types table 19-12. error types description of error detection state type detection method detection condition transmission/ reception field/frame bit error comparison of output level and level on the bus (except stuff bit) mismatch of levels transmission/ reception node bit that output data on the bus at the start of frame to the end of frame, error frame and overload frame. stuff error check of the reception data at the stuff bit 6 consecutive bits of the same output level transmission/ reception node start of frame to crc sequence crc error comparison of the crc generated from the reception data and the received crc sequence mismatch of crc reception node start of frame to data field form error field/frame check of the fixed format detection of the fixed format error reception node crc delimiter ack field end of frame error frame overload frame ack error check of the ack slot by the transmission node detection of recessive level in ack slot transmission node ack slot (2) output timing of error frame table 19-13. output timing of error frame type output timing bit error, stuff error, form error, ack error the error frame is started at the next bit timing following the detected error error passive the crc error frame is started at the next bit timing following the ack delimiter (3) measures when error occurs the transmission node re-transmits the data frame or the remote frame after the error frame. the can standard (iso-11898) allows programmable suppression of this re-transmission. it is called single-shot mode.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 599 (4) error state (a) types of error state ? there are three types of error state: error active, error passive and bus off. the transmission error counter (tec) and the reception error counter (rec) control the error state. the error counters are incremented on each error occurrence (see table 19-15 ). if the value of an error counter exceeds 96, the warning level for the error passive state is reached. when only one node is active at startup, it may not receive an acknowledgment of a transmitted message. this will increment tec until the error passive state is reached. the bus off state will not be reached because, for this specific condition, tec will not increment any more if a value greater than 127 is reached. a node in the bus off state will not issue any dominant level at the can transmit pin. the reception of messages is not affected by the bus off state. table 19-14. types of error type operation value of error counter output error flag type error active transmission/ reception 0 to 127 active error flag (6 bits of dominant level continue) transmission 128 to 255 error passive reception 128 or more passive error flag (6 bits of recessive level continue) transmission more than 255 communication cannot be made bus off reception ? does not exist
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 600 (b) error counter the error counter counts up when an error has occurred, and counts down upon successful transmission and reception. the error counters are updated at the first bit of an error flag. table 19-15. error counter state transmission error counter (tec) reception error counter (rec) reception node detects an error (except bit error in the active error flag or overload flag). no change +1 reception node detects a dominant level following the error flag of its own error frame. no change +8 transmission node transmits an error flag. exception: 1. ack error is detected in the error passive state and dominant level is not detected in the passive error flag sent. 2. stuff error generation in arbitration field. +8 no change bit error detection in active error flag and overload flag when transmitting node is in error active state. +8 no change bit error detection in active error flag and overload flag when receiving node is in error active state. no change +8 when the node detects fourteen continuous dominant bits counted from the beginning of the active error flag or the overload flag, and every time, eight subsequent dominant bits after that are detected. every time when the node detects eight continuous dominant bits after the passive error flag. +8 +8 when the transmitting node has completed transmission without error. ? 1 (0 when error counter = 0) no change when the reception node has completed reception without error. no change ? 1 (1 rec 127) 0 (rec = 0) 119 to 127 (rec > 127) (c) overload frame if the recessive level of the first intermission bit is driven to the dominant level, an overload frame occurs on the bus. upon detection of an overload frame, transmit requests will be postponed until the bus becomes idle.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 601 19.3.7 baud rate control function (1) nominal bit time (8 to 25 time quanta) the definition of 1 data bit time is as follows. figure 19-17. nominal bit time (8 to 25 time quanta) sync segment prop segment phase segment 1 phase segment 2 nominal bit time sjw sjw sample point remark minimum time for one time/quantum (tq) = 1/fx sync segment: in this segment the bit synchronization is performed. prop segment: this segment absorbs delays of the output buffer, the can bus and the input buffer. prop segment time = (output buffer delay) + (can bus delay) + (input buffer delay). phase segment 1/2: these segments compensate the data bit time error. the larger the size measured in tq, the larger the tolerable error. the synchronization jump width (sjw) specifies the synchronization range. the sjw is programmable. sjw can have less or the same number of tq as phase segment 2. table 19-16. segment name and segment length segment name segment length (allowable number of tq) sync segment (synchronization segment) 1 prop segment (propagation segment) programmable 1 to 8 phase segment 1 (phase buffer segment 1) programmable 1 to 8 phase segment 2 (phase buffer segment 2) maximum of phase segment 1 and the ipt note sjw programmable 1 to 4 note ipt = information processing time. it needs to be less than or equal to 2 tq.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 602 (2) adjusting synchronization of the data bit the transmission node transmits data synchronized with the transmission node bit timing. the reception node adjusts synchronization at recessive to dominant edges on the bus. depending on the protocol this synchronization can be a hard or soft synchronization. (a) hard synchronization this type of synchronization is performed when the reception node detects a start of frame in the bus idle state. when the node detects the falling edge of an sof, the current time quantum becomes the synchronization segment. the length of the following segments are defined by the values programmed into the sync0 and sync1 registers. figure 19-18. adjusting synchronization of data bit sync segment prop segment phase segment 1 phase segment 2 can bus bit timing bus idle start of frame
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 603 (b) soft synchronization when a recessive to dominant level change on the bus is detected, a soft synchronization is performed. if the phase error is larger than the programmed sjw value, the node will adjust the timing by applying this sjw value. full synchronization is achieved by subsequent adjustments on the next recessive to dominant edge(s). errors that are equal to or less than the programmed sjw are corrected instantly and full synchronization is achieved already for the next bit. the tq at which the edge occurs becomes the sync segment forcibly if the phase error is less than or equal to sjw. figure 19-19. bit synchronization sync segment prop segment phase segment ? sjw sync segment prop segment phase segment 2 +sjw
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 604 19.3.8 state transition chart figure 19-20. transmission state transition chart start of frame arbitration field data field control field crc field ack field end of frame intermission 1 error frame overload frame bus idle intermission 2 c a b initialization setting reception reception reception end rtr = 0 end end end end error active bit error rtr = 1 bit error bit error bit error ack error bit error bit error end end bit error form error error passive 8 bits of '1' start of frame reception start of frame transmission
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 605 figure 19-21. reception state transition chart start of frame arbitration field data field control field crc field ack field end of frame intermission 1 error frame overload frame bus idle a c initialization setting transmission transmission b transmission end rtr = 0 end end end end rtr = 1 stuff error stuff error crc error, stuff error ack error, bit error bit error, form error bit error end end not ready form error start of frame transmission start of frame reception stuff error not ready
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 606 figure 19-22. error state transition chart (a) transmission error active bus off error passive tec > 128 tec > 256 tec < 127 tec = 0 (b) reception error active error passive rec > 128 rec < 127
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 607 19.4 connection with target system the can module has to be connected to the can bus using an external transceiver. figure 19-23. connection to can bus can module transceiver ctxd crxd canl canh
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 608 19.5 internal registers of can controller 19.5.1 can controller configuration table 19-17. list of can controller registers item configuration can0 module control register (c0gmctrl) can0 module clock selection register (c0gmcs) can0 automatic block transmission register (c0gmabt) can0 automatic block transmission delay register (c0gmabtd) can0 module mask 1 registers (c0mask1l, c0mask1h) can0 module mask 2 registers (c0mask2l, c0mask2h) can0 module mask 3 registers (c0mask3l, c0mask3h) can0 module mask 4 registers (c0mask4l, c0mask4h) can0 module control register (c0ctrl) can0 module last error code register (c0lec) can0 module information register (c0info) can0 module error counter register (c0erc) can0 module interrupt enable register (c0ie) can0 module interrupt status register (c0ints) can0 module bit-rate prescaler register (c0brp) can0 module bit rate register (c0btr) can0 module last in-pointer register (c0lipt) can0 module receive history list register (c0rgpt) can0 module last out-pointer register (c0lopt) can0 module transmit history list register (c0tgpt) control registers can0 module time stamp register (c0ts) can0 message data byte 01 register m (c0mdata01m) can0 message data byte 0 register m (c0mdata0m) can0 message data byte 1 register m (c0mdata1m) can0 message data byte 23 register m (c0mdata23m) can0 message data byte 2 register m (c0mdata2m) can0 message data byte 3 register m (c0mdata3m) can0 message data byte 45 register m (c0mdata45m) can0 message data byte 4 register m (c0mdata4m) can0 message data byte 5 register m (c0mdata5m) can0 message data byte 67 register m (c0mdata67m) can0 message data byte 6 register m (c0mdata6m) can0 message data byte 7 register m (c0mdata7m) can0 message data length code register m (c0mdlcm) can0 message register m (c0mconfm) can0 message identifier register m (c0midlm, c0midhm) message buffer registers can0 message control register m (c0mctrlm) remark m: number of buffer (0 to 31)
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 609 19.5.2 register access type table 19-18. control register access types bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec000h can0 module control register c0gmctrl 0000h fffec002h can0 module clock selection register c0gmcs 0fh fffec006h can0 automatic block transmission register c0gmabt 0000h fffec008h can0 automatic block transmission delay register c0gmabtd 00h fffec040h c0mask1l undefined fffec042h can0 module mask 1 register c0mask1h undefined fffec044h c0mask2l undefined fffec046h can0 module mask 2 register c0mask2h undefined fffec048h c0mask3l undefined fffec04ah can0 module mask 3 register c0mask3h undefined fffec04ch c0mask4l undefined fffec04eh can0 module mask 4 register c0mask4h undefined fffec050h can0 module control register c0ctrl 0000h fffec052h can0 module last error code register c0lec r/w 00h fffec053h can0 module information register c0info 00h fffec054h can0 module error counter register c0erc r 0000h fffec056h can0 module interrupt enable register c0ie 0000h fffec058h can0 module interrupt status register c0ints 0000h fffec05ah can0 module bit-rate prescaler register c0brp ffh fffec05ch can0 module bit-rate register c0btr r/w 370fh fffec05eh can0 module last in-pointer register c0lipt r undefined fffec060h can0 module receive history list register c0rgpt r/w xxxh, xx10b fffec062h can0 module last out-pointer register c0lopt r undefined fffec064h can0 module transmit history list register c0tgpt xxxh, xx10b fffec066h can0 module time stamp register c0ts r/w 0000h
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 610 table 19-19. message buffer register access types (1/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec100h can0 message data byte 01 register 00 c0mdata0100 undefined fffec100h can0 message data byte 0 register 00 c0mdata000 undefined fffec101h can0 message data byte 1 register 00 c0mdata100 undefined fffec102h can0 message data byte 23 register 00 c0mdata2300 undefined fffec102h can0 message data byte 2 register 00 c0mdata200 undefined fffec103h can0 message data byte 3 register 00 c0mdata300 undefined fffec104h can0 message data byte 45 register 00 c0mdata4500 undefined fffec104h can0 message data byte 4 register 00 c0mdata400 undefined fffec105h can0 message data byte 5 register 00 c0mdata500 undefined fffec106h can0 message data byte 67 register 00 c0mdata6700 undefined fffec106h can0 message data byte 6 register 00 c0mdata600 undefined fffec107h can0 message data byte 7 register 00 c0mdata700 undefined fffec108h can0 message data length code register 00 c0mdlc00 0000xxxx fffec109h can0 message configuration register 00 c0mconf00 undefined fffec10ah c0midl00 undefined fffec10ch can0 message identifier register 00 c0midh00 undefined fffec10eh can0 message control register 00 c0mctrl00 00x00000 000xx000b fffec120h can0 message data byte 01 register 01 c0mdata0101 undefined fffec120h can0 message data byte 0 register 01 c0mdata001 undefined fffec121h can0 message data byte 1 register 01 c0mdata101 undefined fffec122h can0 message data byte 23 register 01 c0mdata2301 undefined fffec122h can0 message data byte 2 register 01 c0mdata201 undefined fffec123h can0 message data byte 3 register 01 c0mdata301 undefined fffec124h can0 message data byte 45 register 01 c0mdata4501 undefined fffec124h can0 message data byte 4 register 01 c0mdata401 undefined fffec125h can0 message data byte 5 register 01 c0mdata501 undefined fffec126h can0 message data byte 67 register 01 c0mdata6701 undefined fffec126h can0 message data byte 6 register 01 c0mdata601 undefined fffec127h can0 message data byte 7 register 01 c0mdata701 undefined fffec128h can0 message data length code register 01 c0mdlc01 0000xxxx fffec129h can0 message configuration register 01 c0mconf01 undefined fffec12ah c0midl01 undefined fffec12ch can0 message identifier register 01 c0midh01 undefined fffec12eh can0 message control register 01 c0mctrl01 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 611 (2/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec140h can0 message data byte 01 register 02 c0mdata0102 undefined fffec140h can0 message data byte 0 register 02 c0mdata002 undefined fffec141h can0 message data byte 1 register 02 c0mdata102 undefined fffec142h can0 message data byte 23 register 02 c0mdata2302 undefined fffec142h can0 message data byte 2 register 02 c0mdata202 undefined fffec143h can0 message data byte 3 register 02 c0mdata302 undefined fffec144h can0 message data byte 45 register 02 c0mdata4502 undefined fffec144h can0 message data byte 4 register 02 c0mdata402 undefined fffec145h can0 message data byte 5 register 02 c0mdata502 undefined fffec146h can0 message data byte 67 register 02 c0mdata6702 undefined fffec146h can0 message data byte 6 register 02 c0mdata602 undefined fffec147h can0 message data byte 7 register 02 c0mdata702 undefined fffec148h can0 message data length code register 02 c0mdlc02 0000xxxx fffec149h can0 message configuration register 02 c0mconf02 undefined fffec14ah c0midl02 undefined fffec14ch can0 message identifier register 02 c0midh02 undefined fffec14eh can0 message control register 02 c0mctrl02 00x00000 000xx000b fffec160h can0 message data byte 01 register 03 c0mdata0103 undefined fffec160h can0 message data byte 0 register 03 c0mdata003 undefined fffec161h can0 message data byte 1 register 03 c0mdata103 undefined fffec162h can0 message data byte 23 register 03 c0mdata2303 undefined fffec162h can0 message data byte 2 register 03 c0mdata203 undefined fffec163h can0 message data byte 3 register 03 c0mdata303 undefined fffec164h can0 message data byte 45 register 03 c0mdata4503 undefined fffec164h can0 message data byte 4 register 03 c0mdata403 undefined fffec165h can0 message data byte 5 register 03 c0mdata503 undefined fffec166h can0 message data byte 67 register 03 c0mdata6703 undefined fffec166h can0 message data byte 6 register 03 c0mdata603 undefined fffec167h can0 message data byte 7 register 03 c0mdata703 undefined fffec168h can0 message data length code register 03 c0mdlc03 0000xxxx fffec169h can0 message configuration register 03 c0mconf03 undefined fffec16ah c0midl03 undefined fffec16ch can0 message identifier register 03 c0midh03 undefined fffec16eh can0 message control register 03 c0mctrl03 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 612 (3/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec180h can0 message data byte 01 register 04 c0mdata0104 undefined fffec180h can0 message data byte 0 register 04 c0mdata004 undefined fffec181h can0 message data byte 1 register 04 c0mdata104 undefined fffec182h can0 message data byte 23 register 04 c0mdata2304 undefined fffec182h can0 message data byte 2 register 04 c0mdata204 undefined fffec183h can0 message data byte 3 register 04 c0mdata304 undefined fffec184h can0 message data byte 45 register 04 c0mdata4504 undefined fffec184h can0 message data byte 4 register 04 c0mdata404 undefined fffec185h can0 message data byte 5 register 04 c0mdata504 undefined fffec186h can0 message data byte 67 register 04 c0mdata6704 undefined fffec186h can0 message data byte 6 register 04 c0mdata604 undefined fffec187h can0 message data byte 7 register 04 c0mdata704 undefined fffec188h can0 message data length code register 04 c0mdlc04 0000xxxx fffec189h can0 message configuration register 04 c0mconf04 undefined fffec18ah c0midl04 undefined fffec18ch can0 message identifier register 04 c0midh04 undefined fffec18eh can0 message control register 04 c0mctrl04 00x00000 000xx000b fffec1a0h can0 message data byte 01 register 05 c0mdata0105 undefined fffec1a0h can0 message data byte 0 register 05 c0mdata005 undefined fffec1a1h can0 message data byte 1 register 05 c0mdata105 undefined fffec1a2h can0 message data byte 23 register 05 c0mdata2305 undefined fffec1a2h can0 message data byte 2 register 05 c0mdata205 undefined fffec1a3h can0 message data byte 3 register 05 c0mdata305 undefined fffec1a4h can0 message data byte 45 register 05 c0mdata4505 undefined fffec1a4h can0 message data byte 4 register 05 c0mdata405 undefined fffec1a5h can0 message data byte 5 register 05 c0mdata505 undefined fffec1a6h can0 message data byte 67 register 05 c0mdata6705 undefined fffec1a6h can0 message data byte 6 register 05 c0mdata605 undefined fffec1a7h can0 message data byte 7 register 05 c0mdata705 undefined fffec1a8h can0 message data length code register 05 c0mdlc05 0000xxxx fffec1a9h can0 message configuration register 05 c0mconf05 undefined fffec1aah c0midl05 undefined fffec1ach can0 message identifier register 05 c0midh05 undefined fffec1aeh can0 message control register 05 c0mctrl05 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 613 (4/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec1c0h can0 message data byte 01 register 06 c0mdata0106 undefined fffec1c0h can0 message data byte 0 register 06 c0mdata006 undefined fffec1c1h can0 message data byte 1 register 06 c0mdata106 undefined fffec1c2h can0 message data byte 23 register 06 c0mdata2306 undefined fffec1c2h can0 message data byte 2 register 06 c0mdata206 undefined fffec1c3h can0 message data byte 3 register 06 c0mdata306 undefined fffec1c4h can0 message data byte 45 register 06 c0mdata4506 undefined fffec1c4h can0 message data byte 4 register 06 c0mdata406 undefined fffec1c5h can0 message data byte 5 register 06 c0mdata506 undefined fffec1c6h can0 message data byte 67 register 06 c0mdata6706 undefined fffec1c6h can0 message data byte 6 register 06 c0mdata606 undefined fffec1c7h can0 message data byte 7 register 06 c0mdata706 undefined fffec1c8h can0 message data length code register 06 c0mdlc06 0000xxxx fffec1c9h can0 message configuration register 06 c0mconf06 undefined fffec1cah c0midl06 undefined fffec1cch can0 message identifier register 06 c0midh06 undefined fffec1ceh can0 message control register 06 c0mctrl06 00x00000 000xx000b fffec1e0h can0 message data byte 01 register 07 c0mdata0107 undefined fffec1e0h can0 message data byte 0 register 07 c0mdata007 undefined fffec1e1h can0 message data byte 1 register 07 c0mdata107 undefined fffec1e2h can0 message data byte 23 register 07 c0mdata2307 undefined fffec1e2h can0 message data byte 2 register 07 c0mdata207 undefined fffec1e3h can0 message data byte 3 register 07 c0mdata307 undefined fffec1e4h can0 message data byte 45 register 07 c0mdata4507 undefined fffec1e4h can0 message data byte 4 register 07 c0mdata407 undefined fffec1e5h can0 message data byte 5 register 07 c0mdata507 undefined fffec1e6h can0 message data byte 67 register 07 c0mdata6707 undefined fffec1e6h can0 message data byte 6 register 07 c0mdata607 undefined fffec1e7h can0 message data byte 7 register 07 c0mdata707 undefined fffec1e8h can0 message data length code register 07 c0mdlc07 0000xxxx fffec1e9h can0 message configuration register 07 c0mconf07 undefined fffec1eah c0midl07 undefined fffec1ech can0 message identifier register 07 c0midh07 undefined fffec1eeh can0 message control register 07 c0mctrl07 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 614 (5/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec200h can0 message data byte 01 register 08 c0mdata0108 undefined fffec200h can0 message data byte 0 register 08 c0mdata008 undefined fffec201h can0 message data byte 1 register 08 c0mdata108 undefined fffec202h can0 message data byte 23 register 08 c0mdata2308 undefined fffec202h can0 message data byte 2 register 08 c0mdata208 undefined fffec203h can0 message data byte 3 register 08 c0mdata308 undefined fffec204h can0 message data byte 45 register 08 c0mdata4508 undefined fffec204h can0 message data byte 4 register 08 c0mdata408 undefined fffec205h can0 message data byte 5 register 08 c0mdata508 undefined fffec206h can0 message data byte 67 register 08 c0mdata6708 undefined fffec206h can0 message data byte 6 register 08 c0mdata608 undefined fffec207h can0 message data byte 7 register 08 c0mdata708 undefined fffec208h can0 message data length code register 08 c0mdlc08 0000xxxx fffec209h can0 message configuration register 08 c0mconf08 undefined fffec20ah c0midl08 undefined fffec20ch can0 message identifier register 08 c0midh08 undefined fffec20eh can0 message control register 08 c0mctrl08 00x00000 000xx000b fffec220h can0 message data byte 01 register 09 c0mdata0109 undefined fffec220h can0 message data byte 0 register 09 c0mdata009 undefined fffec221h can0 message data byte 1 register 09 c0mdata109 undefined fffec222h can0 message data byte 23 register 09 c0mdata2309 undefined fffec222h can0 message data byte 2 register 09 c0mdata209 undefined fffec223h can0 message data byte 3 register 09 c0mdata309 undefined fffec224h can0 message data byte 45 register 09 c0mdata4509 undefined fffec224h can0 message data byte 4 register 09 c0mdata409 undefined fffec225h can0 message data byte 5 register 09 c0mdata509 undefined fffec226h can0 message data byte 67 register 09 c0mdata6709 undefined fffec226h can0 message data byte 6 register 09 c0mdata609 undefined fffec227h can0 message data byte 7 register 09 c0mdata709 undefined fffec228h can0 message data length code register 09 c0mdlc09 0000xxxx fffec229h can0 message configuration register 09 c0mconf09 undefined fffec22ah c0midl09 undefined fffec22ch can0 message identifier register 09 c0midh09 undefined fffec22eh can0 message control register 09 c0mctrl09 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 615 (6/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec240h can0 message data byte 01 register 10 c0mdata0110 undefined fffec240h can0 message data byte 0 register 10 c0mdata010 undefined fffec241h can0 message data byte 1 register 10 c0mdata110 undefined fffec242h can0 message data byte 23 register 10 c0mdata2310 undefined fffec242h can0 message data byte 2 register 10 c0mdata210 undefined fffec243h can0 message data byte 3 register 10 c0mdata310 undefined fffec244h can0 message data byte 45 register 10 c0mdata4510 undefined fffec244h can0 message data byte 4 register 10 c0mdata410 undefined fffec245h can0 message data byte 5 register 10 c0mdata510 undefined fffec246h can0 message data byte 67 register 10 c0mdata6710 undefined fffec246h can0 message data byte 6 register 10 c0mdata610 undefined fffec247h can0 message data byte 7 register 10 c0mdata710 undefined fffec248h can0 message data length code register 10 c0mdlc10 0000xxxx fffec249h can0 message configuration register 10 c0mconf10 undefined fffec24ah c0midl10 undefined fffec24ch can0 message identifier register 10 c0midh10 undefined fffec24eh can0 message control register 10 c0mctrl10 00x00000 000xx000b fffec260h can0 message data byte 01 register 11 c0mdata0111 undefined fffec260h can0 message data byte 0 register 11 c0mdata011 undefined fffec261h can0 message data byte 1 register 11 c0mdata111 undefined fffec262h can0 message data byte 23 register 11 c0mdata2311 undefined fffec262h can0 message data byte 2 register 11 c0mdata211 undefined fffec263h can0 message data byte 3 register 11 c0mdata311 undefined fffec264h can0 message data byte 45 register 11 c0mdata4511 undefined fffec264h can0 message data byte 4 register 11 c0mdata411 undefined fffec265h can0 message data byte 5 register 11 c0mdata511 undefined fffec266h can0 message data byte 67 register 11 c0mdata6711 undefined fffec266h can0 message data byte 6 register 11 c0mdata611 undefined fffec267h can0 message data byte 7 register 11 c0mdata711 undefined fffec268h can0 message data length code register 11 c0mdlc11 0000xxxx fffec269h can0 message configuration register 11 c0mconf11 undefined fffec26ah c0midl11 undefined fffec26ch can0 message identifier register 11 c0midh11 undefined fffec26eh can0 message control register 11 c0mctrl11 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 616 (7/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec280h can0 message data byte 01 register 12 c0mdata0112 undefined fffec280h can0 message data byte 0 register 12 c0mdata012 undefined fffec281h can0 message data byte 1 register 12 c0mdata112 undefined fffec282h can0 message data byte 23 register 12 c0mdata2312 undefined fffec282h can0 message data byte 2 register 12 c0mdata212 undefined fffec283h can0 message data byte 3 register 12 c0mdata312 undefined fffec284h can0 message data byte 45 register 12 c0mdata4512 undefined fffec284h can0 message data byte 4 register 12 c0mdata412 undefined fffec285h can0 message data byte 5 register 12 c0mdata512 undefined fffec286h can0 message data byte 67 register 12 c0mdata6712 undefined fffec286h can0 message data byte 6 register 12 c0mdata612 undefined fffec287h can0 message data byte 7 register 12 c0mdata712 undefined fffec288h can0 message data length code register 12 c0mdlc12 0000xxxx fffec289h can0 message configuration register 12 c0mconf12 undefined fffec28ah c0midl12 undefined fffec28ch can0 message identifier register 12 c0midh12 undefined fffec28eh can0 message control register 12 c0mctrl12 00x00000 000xx000b fffec2a0h can0 message data byte 01 register 13 c0mdata0113 undefined fffec2a0h can0 message data byte 0 register 13 c0mdata013 undefined fffec2a1h can0 message data byte 1 register 13 c0mdata113 undefined fffec2a2h can0 message data byte 23 register 13 c0mdata2313 undefined fffec2a2h can0 message data byte 2 register 13 c0mdata213 undefined fffec2a3h can0 message data byte 3 register 13 c0mdata313 undefined fffec2a4h can0 message data byte 45 register 13 c0mdata4513 undefined fffec2a4h can0 message data byte 4 register 13 c0mdata413 undefined fffec2a5h can0 message data byte 5 register 13 c0mdata513 undefined fffec2a6h can0 message data byte 67 register 13 c0mdata6713 undefined fffec2a6h can0 message data byte 6 register 13 c0mdata613 undefined fffec2a7h can0 message data byte 7 register 13 c0mdata713 undefined fffec2a8h can0 message data length code register 13 c0mdlc13 0000xxxx fffec2a9h can0 message configuration register 13 c0mconf13 undefined fffec2aah c0midl13 undefined fffec2ach can0 message identifier register 13 c0midh13 undefined fffec2aeh can0 message control register 13 c0mctrl13 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 617 (8/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec2c0h can0 message data byte 01 register 14 c0mdata0114 undefined fffec2c0h can0 message data byte 0 register 14 c0mdata014 undefined fffec2c1h can0 message data byte 1 register 14 c0mdata114 undefined fffec2c2h can0 message data byte 23 register 14 c0mdata2314 undefined fffec2c2h can0 message data byte 2 register 14 c0mdata214 undefined fffec2c3h can0 message data byte 3 register 14 c0mdata314 undefined fffec2c4h can0 message data byte 45 register 14 c0mdata4514 undefined fffec2c4h can0 message data byte 4 register 14 c0mdata414 undefined fffec2c5h can0 message data byte 5 register 14 c0mdata514 undefined fffec2c6h can0 message data byte 67 register 14 c0mdata6714 undefined fffec2c6h can0 message data byte 6 register 14 c0mdata614 undefined fffec2c7h can0 message data byte 7 register 14 c0mdata714 undefined fffec2c8h can0 message data length code register 14 c0mdlc14 0000xxxx fffec2c9h can0 message configuration register 14 c0mconf14 undefined fffec2cah c0midl14 undefined fffec2cch can0 message identifier register 14 c0midh14 undefined fffec2ceh can0 message control register 14 c0mctrl14 00x00000 000xx000b fffec2e0h can0 message data byte 01 register 15 c0mdata0115 undefined fffec2e0h can0 message data byte 0 register 15 c0mdata015 undefined fffec2e1h can0 message data byte 1 register 15 c0mdata115 undefined fffec2e2h can0 message data byte 23 register 15 c0mdata2315 undefined fffec2e2h can0 message data byte 2 register 15 c0mdata215 undefined fffec2e3h can0 message data byte 3 register 15 c0mdata315 undefined fffec2e4h can0 message data byte 45 register 15 c0mdata4515 undefined fffec2e4h can0 message data byte 4 register 15 c0mdata415 undefined fffec2e5h can0 message data byte 5 register 15 c0mdata515 undefined fffec2e6h can0 message data byte 67 register 15 c0mdata6715 undefined fffec2e6h can0 message data byte 6 register 15 c0mdata615 undefined fffec2e7h can0 message data byte 7 register 15 c0mdata715 undefined fffec2e8h can0 message data length code register 15 c0mdlc15 0000xxxx fffec2e9h can0 message configuration register 15 c0mconf15 undefined fffec2eah c0midl15 undefined fffec2ech can0 message identifier register 15 c0midh15 undefined fffec2eeh can0 message control register 15 c0mctrl15 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 618 (9/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec300h can0 message data byte 01 register 16 c0mdata0116 undefined fffec300h can0 message data byte 0 register 16 c0mdata016 undefined fffec301h can0 message data byte 1 register 16 c0mdata116 undefined fffec302h can0 message data byte 23 register 16 c0mdata2316 undefined fffec302h can0 message data byte 2 register 16 c0mdata216 undefined fffec303h can0 message data byte 3 register 16 c0mdata316 undefined fffec304h can0 message data byte 45 register 16 c0mdata4516 undefined fffec304h can0 message data byte 4 register 16 c0mdata416 undefined fffec305h can0 message data byte 5 register 16 c0mdata516 undefined fffec306h can0 message data byte 67 register 16 c0mdata6716 undefined fffec306h can0 message data byte 6 register 16 c0mdata616 undefined fffec307h can0 message data byte 7 register 16 c0mdata716 undefined fffec308h can0 message data length code register 16 c0mdlc16 0000xxxx fffec309h can0 message configuration register 16 c0mconf16 undefined fffec30ah c0midl16 undefined fffec30ch can0 message identifier register 16 c0midh16 undefined fffec30eh can0 message control register 16 c0mctrl16 00x00000 000xx000b fffec320h can0 message data byte 01 register 17 c0mdata0117 undefined fffec320h can0 message data byte 0 register 17 c0mdata017 undefined fffec321h can0 message data byte 1 register 17 c0mdata117 undefined fffec322h can0 message data byte 23 register 17 c0mdata2317 undefined fffec322h can0 message data byte 2 register 17 c0mdata217 undefined fffec323h can0 message data byte 3 register 17 c0mdata317 undefined fffec324h can0 message data byte 45 register 17 c0mdata4517 undefined fffec324h can0 message data byte 4 register 17 c0mdata417 undefined fffec325h can0 message data byte 5 register 17 c0mdata517 undefined fffec326h can0 message data byte 67 register 17 c0mdata6717 undefined fffec326h can0 message data byte 6 register 17 c0mdata617 undefined fffec327h can0 message data byte 7 register 17 c0mdata717 undefined fffec328h can0 message data length code register 17 c0mdlc17 0000xxxx fffec329h can0 message configuration register 17 c0mconf17 undefined fffec32ah c0midl17 undefined fffec32ch can0 message identifier register 17 c0midh17 undefined fffec32eh can0 message control register 17 c0mctrl17 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 619 (10/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec340h can0 message data byte 01 register 18 c0mdata0118 undefined fffec340h can0 message data byte 0 register 18 c0mdata018 undefined fffec341h can0 message data byte 1 register 18 c0mdata118 undefined fffec342h can0 message data byte 23 register 18 c0mdata2318 undefined fffec342h can0 message data byte 2 register 18 c0mdata218 undefined fffec343h can0 message data byte 3 register 18 c0mdata318 undefined fffec344h can0 message data byte 45 register 18 c0mdata4518 undefined fffec344h can0 message data byte 4 register 18 c0mdata418 undefined fffec345h can0 message data byte 5 register 18 c0mdata518 undefined fffec346h can0 message data byte 67 register 18 c0mdata6718 undefined fffec346h can0 message data byte 6 register 18 c0mdata618 undefined fffec347h can0 message data byte 7 register 18 c0mdata718 undefined fffec348h can0 message data length code register 18 c0mdlc18 0000xxxx fffec349h can0 message configuration register 18 c0mconf18 undefined fffec34ah c0midl18 undefined fffec34ch can0 message identifier register 18 c0midh18 undefined fffec34eh can0 message control register 18 c0mctrl18 00x00000 000xx000b fffec360h can0 message data byte 01 register 19 c0mdata0119 undefined fffec360h can0 message data byte 0 register 19 c0mdata019 undefined fffec361h can0 message data byte 1 register 19 c0mdata119 undefined fffec362h can0 message data byte 23 register 19 c0mdata2319 undefined fffec362h can0 message data byte 2 register 19 c0mdata219 undefined fffec363h can0 message data byte 3 register 19 c0mdata319 undefined fffec364h can0 message data byte 45 register 19 c0mdata4519 undefined fffec364h can0 message data byte 4 register 19 c0mdata419 undefined fffec365h can0 message data byte 5 register 19 c0mdata519 undefined fffec366h can0 message data byte 67 register 19 c0mdata6719 undefined fffec366h can0 message data byte 6 register 19 c0mdata619 undefined fffec367h can0 message data byte 7 register 19 c0mdata719 undefined fffec368h can0 message data length code register 19 c0mdlc19 0000xxxx fffec369h can0 message configuration register 19 c0mconf19 undefined fffec36ah c0midl19 undefined fffec36ch can0 message identifier register 19 c0midh19 undefined fffec36eh can0 message control register 19 c0mctrl19 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 620 (11/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec380h can0 message data byte 01 register 20 c0mdata0120 undefined fffec380h can0 message data byte 0 register 20 c0mdata020 undefined fffec381h can0 message data byte 1 register 20 c0mdata120 undefined fffec382h can0 message data byte 23 register 20 c0mdata2320 undefined fffec382h can0 message data byte 2 register 20 c0mdata220 undefined fffec383h can0 message data byte 3 register 20 c0mdata320 undefined fffec384h can0 message data byte 45 register 20 c0mdata4520 undefined fffec384h can0 message data byte 4 register 20 c0mdata420 undefined fffec385h can0 message data byte 5 register 20 c0mdata520 undefined fffec386h can0 message data byte 67 register 20 c0mdata6720 undefined fffec386h can0 message data byte 6 register 20 c0mdata620 undefined fffec387h can0 message data byte 7 register 20 c0mdata720 undefined fffec388h can0 message data length code register 20 c0mdlc20 0000xxxx fffec389h can0 message configuration register 20 c0mconf20 undefined fffec38ah c0midl20 undefined fffec38ch can0 message identifier register 20 c0midh20 undefined fffec38eh can0 message control register 20 c0mctrl20 00x00000 000xx000b fffec3a0h can0 message data byte 01 register 21 c0mdata0121 undefined fffec3a0h can0 message data byte 0 register 21 c0mdata021 undefined fffec3a1h can0 message data byte 1 register 21 c0mdata121 undefined fffec3a2h can0 message data byte 23 register 21 c0mdata2321 undefined fffec3a2h can0 message data byte 2 register 21 c0mdata221 undefined fffec3a3h can0 message data byte 3 register 21 c0mdata321 undefined fffec3a4h can0 message data byte 45 register 21 c0mdata4521 undefined fffec3a4h can0 message data byte 4 register 21 c0mdata421 undefined fffec3a5h can0 message data byte 5 register 21 c0mdata521 undefined fffec3a6h can0 message data byte 67 register 21 c0mdata6721 undefined fffec3a6h can0 message data byte 6 register 21 c0mdata621 undefined fffec3a7h can0 message data byte 7 register 21 c0mdata721 undefined fffec3a8h can0 message data length code register 21 c0mdlc21 0000xxxx fffec3a9h can0 message configuration register 21 c0mconf21 undefined fffec3aah c0midl21 undefined fffec3ach can0 message identifier register 21 c0midh21 undefined fffec3aeh can0 message control register 21 c0mctrl21 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 621 (12/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec3c0h can0 message data byte 01 register 22 c0mdata0122 undefined fffec3c0h can0 message data byte 0 register 22 c0mdata022 undefined fffec3c1h can0 message data byte 1 register 22 c0mdata122 undefined fffec3c2h can0 message data byte 23 register 22 c0mdata2322 undefined fffec3c2h can0 message data byte 2 register 22 c0mdata222 undefined fffec3c3h can0 message data byte 3 register 22 c0mdata322 undefined fffec3c4h can0 message data byte 45 register 22 c0mdata4522 undefined fffec3c4h can0 message data byte 4 register 22 c0mdata422 undefined fffec3c5h can0 message data byte 5 register 22 c0mdata522 undefined fffec3c6h can0 message data byte 67 register 22 c0mdata6722 undefined fffec3c6h can0 message data byte 6 register 22 c0mdata622 undefined fffec3c7h can0 message data byte 7 register 22 c0mdata722 undefined fffec3c8h can0 message data length code register 22 c0mdlc22 0000xxxx fffec3c9h can0 message configuration register 22 c0mconf22 undefined fffec3cah c0midl22 undefined fffec3cch can0 message identifier register 22 c0midh22 undefined fffec3ceh can0 message control register 22 c0mctrl22 00x00000 000xx000b fffec3e0h can0 message data byte 01 register 23 c0mdata0123 undefined fffec3e0h can0 message data byte 0 register 23 c0mdata023 undefined fffec3e1h can0 message data byte 1 register 23 c0mdata123 undefined fffec3e2h can0 message data byte 23 register 23 c0mdata2323 undefined fffec3e2h can0 message data byte 2 register 23 c0mdata223 undefined fffec3e3h can0 message data byte 3 register 23 c0mdata323 undefined fffec3e4h can0 message data byte 45 register 23 c0mdata4523 undefined fffec3e4h can0 message data byte 4 register 23 c0mdata423 undefined fffec3e5h can0 message data byte 5 register 23 c0mdata523 undefined fffec3e6h can0 message data byte 67 register 23 c0mdata6723 undefined fffec3e6h can0 message data byte 6 register 23 c0mdata623 undefined fffec3e7h can0 message data byte 7 register 23 c0mdata723 undefined fffec3e8h can0 message data length code register 23 c0mdlc23 0000xxxx fffec3e9h can0 message configuration register 23 c0mconf23 undefined fffec3eah c0midl23 undefined fffec3ech can0 message identifier register 23 c0midh23 undefined fffec3eeh can0 message control register 23 c0mctrl23 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 622 (13/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec400h can0 message data byte 01 register 24 c0mdata0124 undefined fffec400h can0 message data byte 0 register 24 c0mdata024 undefined fffec401h can0 message data byte 1 register 24 c0mdata124 undefined fffec402h can0 message data byte 23 register 24 c0mdata2324 undefined fffec402h can0 message data byte 2 register 24 c0mdata224 undefined fffec403h can0 message data byte 3 register 24 c0mdata324 undefined fffec404h can0 message data byte 45 register 24 c0mdata4524 undefined fffec404h can0 message data byte 4 register 24 c0mdata424 undefined fffec405h can0 message data byte 5 register 24 c0mdata524 undefined fffec406h can0 message data byte 67 register 24 c0mdata6724 undefined fffec406h can0 message data byte 6 register 24 c0mdata624 undefined fffec407h can0 message data byte 7 register 24 c0mdata724 undefined fffec408h can0 message data length code register 24 c0mdlc24 0000xxxx fffec409h can0 message configuration register 24 c0mconf24 undefined fffec40ah c0midl24 undefined fffec40ch can0 message identifier register 24 c0midh24 undefined fffec40eh can0 message control register 24 c0mctrl24 00x00000 000xx000b fffec420h can0 message data byte 01 register 25 c0mdata0125 undefined fffec420h can0 message data byte 0 register 25 c0mdata025 undefined fffec421h can0 message data byte 1 register 25 c0mdata125 undefined fffec422h can0 message data byte 23 register 25 c0mdata2325 undefined fffec422h can0 message data byte 2 register 25 c0mdata225 undefined fffec423h can0 message data byte 3 register 25 c0mdata325 undefined fffec424h can0 message data byte 45 register 25 c0mdata4525 undefined fffec424h can0 message data byte 4 register 25 c0mdata425 undefined fffec425h can0 message data byte 5 register 25 c0mdata525 undefined fffec426h can0 message data byte 67 register 25 c0mdata6725 undefined fffec426h can0 message data byte 6 register 25 c0mdata625 undefined fffec427h can0 message data byte 7 register 25 c0mdata725 undefined fffec428h can0 message data length code register 25 c0mdlc25 0000xxxx fffec429h can0 message configuration register 25 c0mconf25 undefined fffec42ah c0midl25 undefined fffec42ch can0 message identifier register 25 c0midh25 undefined fffec42eh can0 message control register 25 c0mctrl25 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 623 (14/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec440h can0 message data byte 01 register 26 c0mdata0126 undefined fffec440h can0 message data byte 0 register 26 c0mdata026 undefined fffec441h can0 message data byte 1 register 26 c0mdata126 undefined fffec442h can0 message data byte 23 register 26 c0mdata2326 undefined fffec442h can0 message data byte 2 register 26 c0mdata226 undefined fffec443h can0 message data byte 3 register 26 c0mdata326 undefined fffec444h can0 message data byte 45 register 26 c0mdata4526 undefined fffec444h can0 message data byte 4 register 26 c0mdata426 undefined fffec445h can0 message data byte 5 register 26 c0mdata526 undefined fffec446h can0 message data byte 67 register 26 c0mdata6726 undefined fffec446h can0 message data byte 6 register 26 c0mdata626 undefined fffec447h can0 message data byte 7 register 26 c0mdata726 undefined fffec448h can0 message data length code register 26 c0mdlc26 0000xxxx fffec449h can0 message configuration register 26 c0mconf26 undefined fffec44ah c0midl26 undefined fffec44ch can0 message identifier register 26 c0midh26 undefined fffec44eh can0 message control register 26 c0mctrl26 00x00000 000xx000b fffec460h can0 message data byte 01 register 27 c0mdata0127 undefined fffec460h can0 message data byte 0 register 27 c0mdata027 undefined fffec461h can0 message data byte 1 register 27 c0mdata127 undefined fffec462h can0 message data byte 23 register 27 c0mdata2327 undefined fffec462h can0 message data byte 2 register 27 c0mdata227 undefined fffec463h can0 message data byte 3 register 27 c0mdata327 undefined fffec464h can0 message data byte 45 register 27 c0mdata4527 undefined fffec464h can0 message data byte 4 register 27 c0mdata427 undefined fffec465h can0 message data byte 5 register 27 c0mdata527 undefined fffec466h can0 message data byte 67 register 27 c0mdata6727 undefined fffec466h can0 message data byte 6 register 27 c0mdata627 undefined fffec467h can0 message data byte 7 register 27 c0mdata727 undefined fffec468h can0 message data length code register 27 c0mdlc27 0000xxxx fffec469h can0 message configuration register 27 c0mconf27 undefined fffec46ah c0midl27 undefined fffec46ch can0 message identifier register 27 c0midh27 undefined fffec46eh can0 message control register 27 c0mctrl27 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 624 (15/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec480h can0 message data byte 01 register 28 c0mdata0128 undefined fffec480h can0 message data byte 0 register 28 c0mdata028 undefined fffec481h can0 message data byte 1 register 28 c0mdata128 undefined fffec482h can0 message data byte 23 register 28 c0mdata2328 undefined fffec482h can0 message data byte 2 register 28 c0mdata228 undefined fffec483h can0 message data byte 3 register 28 c0mdata328 undefined fffec484h can0 message data byte 45 register 28 c0mdata4528 undefined fffec484h can0 message data byte 4 register 28 c0mdata428 undefined fffec485h can0 message data byte 5 register 28 c0mdata528 undefined fffec486h can0 message data byte 67 register 28 c0mdata6728 undefined fffec486h can0 message data byte 6 register 28 c0mdata628 undefined fffec487h can0 message data byte 7 register 28 c0mdata728 undefined fffec488h can0 message data length code register 28 c0mdlc28 0000xxxx fffec489h can0 message configuration register 28 c0mconf28 undefined fffec48ah c0midl28 undefined fffec48ch can0 message identifier register 28 c0midh28 undefined fffec48eh can0 message control register 28 c0mctrl28 00x00000 000xx000b fffec4a0h can0 message data byte 01 register 29 c0mdata0129 undefined fffec4a0h can0 message data byte 0 register 29 c0mdata029 undefined fffec4a1h can0 message data byte 1 register 29 c0mdata129 undefined fffec4a2h can0 message data byte 23 register 29 c0mdata2329 undefined fffec4a2h can0 message data byte 2 register 29 c0mdata229 undefined fffec4a3h can0 message data byte 3 register 29 c0mdata329 undefined fffec4a4h can0 message data byte 45 register 29 c0mdata4529 undefined fffec4a4h can0 message data byte 4 register 29 c0mdata429 undefined fffec4a5h can0 message data byte 5 register 29 c0mdata529 undefined fffec4a6h can0 message data byte 67 register 29 c0mdata6729 undefined fffec4a6h can0 message data byte 6 register 29 c0mdata629 undefined fffec4a7h can0 message data byte 7 register 29 c0mdata729 undefined fffec4a8h can0 message data length code register 29 c0mdlc29 0000xxxx fffec4a9h can0 message configuration register 29 c0mconf29 undefined fffec4aah c0midl29 undefined fffec4ach can0 message identifier register 29 c0midh29 undefined fffec4aeh can0 message control register 29 c0mctrl29 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 625 (16/16) bit manipulation units address register name symbol r/w 1 bit 8 bits 16 bits after reset fffec4c0h can0 message data byte 01 register 30 c0mdata0130 undefined fffec4c0h can0 message data byte 0 register 30 c0mdata030 undefined fffec4c1h can0 message data byte 1 register 30 c0mdata130 undefined fffec4c2h can0 message data byte 23 register 30 c0mdata2330 undefined fffec4c2h can0 message data byte 2 register 30 c0mdata230 undefined fffec4c3h can0 message data byte 3 register 30 c0mdata330 undefined fffec4c4h can0 message data byte 45 register 30 c0mdata4530 undefined fffec4c4h can0 message data byte 4 register 30 c0mdata430 undefined fffec4c5h can0 message data byte 5 register 30 c0mdata530 undefined fffec4c6h can0 message data byte 67 register 30 c0mdata6730 undefined fffec4c6h can0 message data byte 6 register 30 c0mdata630 undefined fffec4c7h can0 message data byte 7 register 30 c0mdata730 undefined fffec4c8h can0 message data length code register 30 c0mdlc30 0000xxxx fffec4c9h can0 message configuration register 30 c0mconf30 undefined fffec4cah c0midl30 undefined fffec4cch can0 message identifier register 30 c0midh30 undefined fffec4ceh can0 message control register 30 c0mctrl30 00x00000 000xx000b fffec4e0h can0 message data byte 01 register 31 c0mdata0131 undefined fffec4e0h can0 message data byte 0 register 31 c0mdata031 undefined fffec4e1h can0 message data byte 1 register 31 c0mdata131 undefined fffec4e2h can0 message data byte 23 register 31 c0mdata2331 undefined fffec4e2h can0 message data byte 2 register 31 c0mdata231 undefined fffec4e3h can0 message data byte 3 register 31 c0mdata331 undefined fffec4e4h can0 message data byte 45 register 31 c0mdata4531 undefined fffec4e4h can0 message data byte 4 register 31 c0mdata431 undefined fffec4e5h can0 message data byte 5 register 31 c0mdata531 undefined fffec4e6h can0 message data byte 67 register 31 c0mdata6731 undefined fffec4e6h can0 message data byte 6 register 31 c0mdata631 undefined fffec4e7h can0 message data byte 7 register 31 c0mdata731 undefined fffec4e8h can0 message data length code register 31 c0mdlc31 0000xxxx fffec4e9h can0 message configuration register 31 c0mconf31 undefined fffec4eah c0midl31 undefined fffec4ech can0 message identifier register 31 c0midh31 undefined fffec4eeh can0 message control register 31 c0mctrl31 r/w 00x00000 000xx000b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 626 19.5.3 control bits of message buffers table 19-20. control bits of control registers (1/2) address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 fffec000h 0000000cgom fffec001h c0gmctrl(w) 000000sefsdsgom fffec000h 000000efsdgom fffec001h c0gmctrl(r) mbon0000000 fffec002hc0gmcs0000ccp3ccp2ccp1ccp0 fffec006h 0000000cabttrgg fffec007h c0gmabt(w) 000000sabtclrsabttrg fffec006h 000000abtclrabttrg fffec007h c0gmabt(r) 00000000 fffec008hc0gmabtd0000abtd3abtd2abtd1abtd0 fffec040h cm1id [7:0] fffec041h c0mask1l cm1id [15:8] fffec042h cm1id [23:16] fffec043h c0mask1h 0 0 0 cm1id [28:24] fffec044h cm2id [7:0] fffec045h c0mask2l cm2id [15:8] fffec046h cm2id [23:16] fffec047h c0mask2h 0 0 0 cm2id [28:24] fffec048h cm3id [7:0] fffec049h c0mask3l cm3id [15:8] fffec04ah cm3id [23:16] fffec04bh c0mask3h 0 0 0 cm3id [28:24] fffec04ch cm4id [7:0] fffec04dh c0mask4l cm4id [15:8] fffec04eh cm4id [23:16] fffec04fh c0mask4h 0 0 0 cm4id [28:24] fffec050h cccerc cal cvalid cps mode1 cps mode0 cop mode2 cop mode1 cop mode0 fffec051h c0ctrl(w) sccerc sal 0 sps mode1 sps mode0 sop mode2 sop mode1 sop mode0 fffec050h ccerc al valid ps mode1 ps mode0 op mode2 op mode1 op mode0 fffec051h c0ctrl(r) 00000000 fffec052hc0lec(w)00000000 fffec052hc0lec(r)00000lec2lec1lec0 fffec053h c0info 0 0 0 boff tecs1 tecs0 recs1 recs0
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 627 table 19-20. control bits of control registers (2/2) address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 fffec054h tec[7:0] fffec055h c0erc rec[7:0] fffec056h 0 0 ccie5 ccie4 ccie3 ccie2 ccie1 ccie0 fffec057h c0ie (w) 0 0 scie5 scie4 scie3 scie2 scie1 scie0 fffec056h 0 0 cie5 cie4 cie3 cie2 cie1 cie0 fffec057h c0ie (r) 00000000 fffec058h 0 0 ccints5 ccints4 ccints3 ccints2 ccints1 ccints0 fffec059h c0ints (w) 00000000 fffec058h 0 0 cints5 cints4 cints3 cints2 cints1 cints0 fffec059h c0ints (r) 00000000 fffec05ah c0brp tqprs[7:0] fffec05bh ? access prohibited (reserved for future use) fffec05ch 0 0 0 0 tseg1[3:0] fffec05dh c0btr sjw[1:0] 0 tseg2[2:0] fffec05eh c0lipt lipt[7:0] fffec05fh ? access prohibited (reserved for future use) fffec060h 0000000crovf fffec061h c0rgpt(w) 00000000 fffec060h 000000rhpmrovf fffec061h c0rgpt(r) rgpt[7:0] fffec062h c0lopt lopt[7:0] fffec063h ? access prohibited (reserved for future use) fffec064h 0000000ctovf fffec065h c0tgpt(w) 00000000 fffec064h 0 0 0 0 0 0 thpm tovf fffec065h c0tgpt(r) tgpt[7:0] fffec066h 0 0 0 0 0 ctslock ctssel ctsen fffec067h c0ts(w) 0 0 0 0 0 stslock stssel stsen fffec066h 0 0 0 0 0 tslock tssel tsen fffec067h c0ts(r) 00000000 fffec068h- ? access prohibited (reserved for future use)
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 628 table 19-21. control bits of message buffers address symbol bit 7/15 bit 6/14 bit 5/13 bit 4/12 bit 3/11 bit 2/10 bit 1/9 bit 0/8 fffecxx0h message data (byte 0) fffecxx1h c0mdata01m message data (byte 1) fffecxx0h c0mdata0m message data (byte 0) fffecxx1h c0mdata1m message data (byte 1) fffecxx2h message data (byte 2) fffecxx3h c0mdata23m message data (byte 3) fffecxx2h c0mdata2m message data (byte 2) fffecxx3h c0mdata3m message data (byte 3) fffecxx4h message data (byte 4) fffecxx5h c0mdata45m message data (byte 5) fffecxx4h c0mdata4m message data (byte 4) fffecxx5h c0mdata5m message data (byte 5) fffecxx6h message data (byte 6) fffecxx7h c0mdata67m message data (byte 7) fffecxx6h c0mdata6m message data (byte 6) fffecxx7h c0mdata7m message data (byte 7) fffecxx8h c0mdlcm 0 mdlc3 mdlc2 mdlc1 mdlc0 fffecxx9h c0mconfm ows rtr mt2 mt1 mt0 ma2 ma1 ma0 fffecxxah id7 id6 id5 id4 id3 id2 id1 id0 fffecxxbh c0midlm id15 id14 id13 id12 id11 id10 id9 id8 fffecxxch id23 id22 id21 id20 id19 id18 id17 id16 fffecxxdh c0midhm ide 0 0 id28 id27 id26 id25 id24 fffecxxeh 0 0 0 cmow cie cdn ctrq crdy fffecxxfh c0mctrlm 0 0 0 0 sie sdn strq srdy fffecxxeh 0 0 0 mow ie dn trq rdy fffecxxfh c0mctrlm 00muc00000
chapter 19 can controller preliminary user?s manual u16541ej1v0um 629 19.6 control registers (1) can0 module control register (c0gmctrl) (1/2) (a) read 15 14 13 12 11 10 9 8 address initial value c0gmctrlmbon0000000 fffec001h 00h 76543210 000000efsdgom fffec000h 00h (b) write 15 14 13 12 11 10 9 8 c0gmctrl000000set efsd set gom fffec001h 76543210 0000000clear gom fffec000h (a) read mbon access enable bit for message buffers 0 write access and read access to the message buffers is impossible because can module is in can sleep and/or can stop mode. 1 write access and read access to the message buffers is possible. caution be sure not to access the message buffer registers (c0mdata0m, c0mdata1m, c0mdata2m, c0mdata3m, c0mdata4m, c0mdata5m, c0mdata6m, c0mdata7m, c0mdlcm, c0mconfm, c0midlm, c0midhm or c0mctrlm ) while the mbon bit is cleared (0). remark mbon: message buffer access on efsd enabled forced shutdown request bit 0 forced shutdown request is disabled. 1 forced shutdown request is enabled. gom global operation mode bit 0 can module is in reset state. 1 can module is enabled.
chapter 19 can controller preliminary user?s manual u16541ej1v0um 630 (2/2) (b) write set efsd efsd bit setting 0 no change in efsd bit?s value 1efsd bit set (1) caution when the efsd bit is set (1), the subsequent cpu access to the can module has to clear the gom bit (0). if the gom bit is not cleared (0) in the subsequent access, the efsd bit is cleared (0) automatically (forced shutdown request is invalid). set gom clear gom gom bit setting 0 1 gom bit cleared (0) 1 0 gom bit set (1) other than above no change in gom bit?s value remark the gom bit is cleared (0) only in init mode.
chapter 19 can controller preliminary user?s manual u16541ej1v0um 631 (2) can0 module clock selection register (c0gmcs) 76543210addressinitial value c0gmcs mbon 0 0 0 ccp3 ccp2 ccp1 ccp0 fffec002h 0fh (read/write) ccp3 ccp2 ccp1 ccp1 can module system clock (f canmod ) 0000f can /1 0001f can /2 0010f can /3 0011f can /4 0100f can /5 0101f can /6 0110f can /7 0111f can /8 1000f can /9 1001f can /10 1010f can /11 1011f can /12 1100f can /13 1101f can /14 1110f can /15 1111f can /16 remark f can = clock supply to can
chapter 19 can controller preliminary user?s manual u16541ej1v0um 632 (3) can0 automatic block transmission register (c0gmabt) (1/2) (a) read 15 14 13 12 11 10 9 8 address initial value c0gmabt00000000 fffec007h 00h 76543210 000000abtclrabttrg fffec006h 00h (b) write 15 14 13 12 11 10 9 8 c0gmabt000000set abtclr set abttrg fffec007h 76543210 0000000clear abttrg fffec006h caution before switching from ?normal operating mode with automatic block transmission? to the init mode, be sure to clear the bits in the c0gmabt register to their initial values. (a) read abtclr automatic block transmission engine clear request bit 0 the automatic block transmission engine is in the idle state or operating. 1 clear request to the automatic block transmission engine. upon re-start of the automatic block transmission engine by setting abttrg (1), the automatic block transmission engine starts transmission from the first abt message buffer (i.e. message buffer 0). abttrg automatic block transmission start bit 0 automatic block transmission stop 1 automatic block transmission start
chapter 19 can controller preliminary user?s manual u16541ej1v0um 633 (2/2) (b) write set abtclr abtclr bit setting 0 no change in abtclr bit?s value 1 abtclr bit set (1) remarks 1. the abtclr bit must not be set (1) when the abttrg bit is set (1). 2. the abtclr bit is automatically cleared (0) by the internal abt engine, when a clear request has been accepted by setting the avtclr bit (1). set abttrg clear abttrg abttrg bit setting 0 1 abttrg bit cleared (0) 1 0 abttrg bit set (1) caution be sure not to set the abttrg bit in init mode. the correct operation after init mode cannot be guaranteed when the abttrg bit is set in init mode.
chapter 19 can controller preliminary user?s manual u16541ej1v0um 634 (4) can0 automatic block transmission delay register (c0gmabtd) 76543210addressinitial value c0gmabt 0 0 0 0 abtd3 abtd2 abtd1 abtd0 fffec008h 00h (read/write) abtd3 abtd2 abtd1 abtd0 data frame interval during automatic block transmission (unit = bit time; dbt) 00000 dbt 00012 5 dbt 00102 6 dbt 00112 7 dbt 01002 8 dbt 01012 9 dbt 01102 10 dbt 01112 11 dbt 10002 12 dbt other than above setting prohibited caution be sure not to change the contents of the c0gmabtd register while the abttrg bit is set (1).
chapter 19 can controller preliminary user?s manual u16541ej1v0um 635 (5) can0 module mask register (c0maskal, c0maskah) (a = 1, 2, 3, 4) figure 19-24. can0 module mask 1 registers (c0mask1l, c0mask1h) 15 14 13 12 11 10 9 8 address initial value c0mask1l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 fffec041h undefined (read/write) 7 6543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 fffec040h undefined 15 14 13 12 11 10 9 8 c0mask1h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 fffec043h undefined (read/write) 7 6543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 fffec042h undefined figure 19-25. can0 module mask 2 registers (c0mask2l, c0mask2h) 15 14 13 12 11 10 9 8 address initial value c0mask2l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 fffec045h undefined (read/write) 7 6543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 fffec044h undefined 15 14 13 12 11 10 9 8 c0mask2h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 fffec047h undefined (read/write) 7 6543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 fffec046h undefined figure 19-26. can0 module mask 3 registers (c0mask3l, c0mask3h) 15 14 13 12 11 10 9 8 address initial value c0mask3l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 fffec049h undefined (read/write) 7 6543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 fffec048h undefined 15 14 13 12 11 10 9 8 c0mask3h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 fffec04bh undefined (read/write) 7 6543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 fffec04ah undefined
chapter 19 can controller preliminary user?s manual u16541ej1v0um 636 figure 19-27. can0 module mask 4 registers (c0mask4l, c0mask4h) 15 14 13 12 11 10 9 8 address initial value c0mask4l cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 fffec04dh undefined (read/write) 7 6543210 cmid7 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 fffec04ch undefined 15 14 13 12 11 10 9 8 c0mask4h 0 0 0 cmid28 cmid27 cmid26 cmid25 cmid24 fffec04fh undefined (read/write) 7 6543210 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 cmid17 cmid16 fffec04eh undefined cmid28 to cmid0 mask identifier pattern 0 the id bit of a received message frame is compared with the id bit of the message buffer set by the cmid28 to cmid0 bits. 1 the id bit of a received message frame is not compared (= is masked) with the id bit of the message buffer set by the cmid28 to cmid0 bits.
chapter 19 can controller preliminary user?s manual u16541ej1v0um 637 (6) can0 module control register (c0ctrl) (1/4) (a) read 15 14 13 12 11 10 9 8 address initial value c0ctrl000000rstattstat fffec051h 00h 76543210 ccerc al valid psmode 1 psmode 0 opmode 2 opmode 1 opmode 0 fffec050h 00h (b) write 15 14 13 12 11 10 9 8 c0ctrl set ccerc set al 0set psmode 1 set psmode 0 set opmode 2 set opmode 1 set opmode 0 fffec051h 76543210 clear ccerc clear al clear valid clear psmode 1 clear psmode 0 clear opmode 2 clear opmode 1 clear opmode 0 fffec050 (a) read rstat can reception status bit 0 no reception activity on the can bus 1 reception activity on the can bus remark the rstat bit is set (1) under the following conditions. ? the sof bit of a receive frame is detected ? arbitration was lost during a transmission frame the rstat bit is cleared (0) under the following conditions. ? ?recessive? is detected at the 2nd bit of an interframe space. ? initialization mode was shifted to at the first bit of an interframe space
chapter 19 can controller preliminary user?s manual u16541ej1v0um 638 (2/4) tstat can transmission status bit 0 no transmission activity on the can bus 1 transmission activity on the can bus remark the tstat bit is set (1) under the following conditions. ? the sof bit of a transmission frame is detected ? the first bit of an error flag is detected during a transmission frame the tstat bit is cleared (0) under the following conditions. ? can shifted to the bus-off status ? arbitration was lost during a transmission frame ? ?recessive? is detected at the 2nd bit of an interframe space. ? initialization mode was shifted to at the first bit of an interframe space ccerc can clear error counter bit 0 while in init mode, the can module error counter c0erc and the can module information register c0info will not be cleared. 1 while in init mode, the can module error counter c0erc and the can module information register c0info will be cleared. al arbitration loss bit 0 in the ?single-shot mode?, no re-transmission when an error occurs. transmit message will not be queued for a re-transmission request when arbitration is lost. 1 in the ?single-shot mode?, no re-transmission when an error occurs. transmit message will be queued for a re-transmission request when arbitration is lost. remarks 1. the al bit is effective only in the ?single-shot mode?. 2. if a can module operates in the ?single-shot mode? and the al bit is set (1), the interrupt cints4 is not generated upon arbitration loss. valid valid receive message frame detection bit 0 no valid message frame reception in the can protocol transfer layer since the valid bit was cleared (0) last time. 1 valid message frame reception in the can protocol transfer layer since the valid bit was cleared (0) last time. remarks 1. a valid reception does not require acceptance of the message frame in a receive message buffer (data frame) or transmit message buffer (remote frame). 2. before switching from init mode to any operational mode, the user has to clear the valid bit (0). 3. if only two can nodes are connected to the can bus and one of the can nodes is in ?normal operating mode? and transmitting message frames while the other can node is in ?receive-only mode?, the valid bit will not be set (1) before the transmitting node becomes error passive.
chapter 19 can controller preliminary user?s manual u16541ej1v0um 639 (3/4) psmode1 psmode0 power save mode 0 0 no power save mode selected (can module is in init mode or in one of the operational modes) 0 1 can sleep mode 1 0 setting prohibited 1 1 can stop mode opmode2 opmode1 opmode0 operation mode 0 0 0 no operational mode selected (can module is in init mode) 0 0 1 normal operating mode 0 1 0 normal operating mode with automatic block transmission 0 1 1 receive-only mode 1 0 0 single-shot mode 1 0 1 self-test mode other than above setting prohibited. (b) write set ccerc clear ccerc ccerc bit setting 0 1 ccerc bit cleared (0) 1 0 ccerc bit set (1) other than above no change in ccerc bit?s value set al clear al al bit setting 0 1 al bit cleared (0) 1 0 al bit set (1) other than above no change in al bit?s value clear valid valid bit setting 0 valid bit not changed 1 valid bit cleared (0) set psmode1 clear psmode1 psmode1 bit setting 0 1 psmode1 bit cleared (0) 10psmode1 bit set (1) other than above no change in psmode1 bit?s value
chapter 19 can controller preliminary user?s manual u16541ej1v0um 640 (4/4) set psmode2 clear psmode2 psmode2 bit setting 0 1 psmode2 bit cleared (0) 10psmode2 bit set (1) other than above no change in psmode2 bit?s value set opmode0 clear opmode0 opmode0 bit setting 0 1 opmode0 bit cleared (0) 1 0 opmode0 bit set (1) other than above no change in opmode0 bit?s value set opmode1 clear opmode1 opmode1 bit setting 0 1 opmode1 bit cleared (0) 1 0 opmode1 bit set (1) other than above no change in opmode1 bit?s value set opmode2 clear opmode2 opmode2 bit setting 0 1 opmode2 bit cleared (0) 1 0 opmode2 bit set (1) other than above no change in opmode2 bit?s value
chapter 19 can controller preliminary user?s manual u16541ej1v0um 641 (7) can0 module last error code register (c0lec) 76543210addressinitial value c0lec00000lec2lec1lec0 fffec052h 00h (read/write) remarks 1. switching the can module from an operational mode to the init mode does not clear the actual content of c0lec. 2. when cpu attempts to write c0lec with data other than 00h, it is simply ignored. lec2 lec1 lec0 last error code of protocol error type 0 0 0 no error 0 0 1 stuff error 0 1 0 form error 0 1 1 ack error 100 bit error (the can module tried to send a ?recessive? ?1? bit as part of the transmitted message (with the exception of the arbitration field), but the monitored can bus value was ?dominant? ?0?) 101 bit error (the can module tried to send a ?dominant? ?0? bit as part of the transmitted message or as an ack bit, error or overload frame, but the monitored can bus value was ?recessive? ?1?) 1 1 0 crc error 1 1 1 unused
chapter 19 can controller preliminary user?s manual u16541ej1v0um 642 (8) can0 module information register (c0info) 76543210addressinitial value c0info 0 0 0 boff tecs1 tecs0 recs1 recs0 fffec053h 00h (read only) boff bus-off status bit 0 can is not in the bus-off state (transmission error counter < 255) 1 can is in the bus-off state (transmission error counter 255) tecs1 tecs0 transmit error counter status bit 0 0 transmission error counter below warning level (< 96) 0 1 transmission error counter in the warning level range (96 ? 127) 1 0 not used 1 1 transmission error counter in the error passive or bus-off range ( 128) recs1 recs0 receive error counter status bit 0 0 reception error counter below warning level (< 96) 0 1 reception error counter in the warning level range (96 ? 127) 1 0 not used 1 1 reception error counter in the error passive range ( 128) (9) can0 module error counter register (c0erc) 15 14 13 12 11 10 9 8 address initial value c0erc rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 fffec055h 00h (read only) 7 6543210 tec7 tec6 tec5 tec4 tec3 tec2 tec1 tec0 fffec054h 00h rec7 to rec0 receive error counter bit 0 to 255 number of reception error counter. this reflects the current status of the reception error counter. the count value is defined by the can protocol. tec7 to tec0 transmit error counter bit 0 to 255 number of transmission error counter. this reflects the current status of the transmission error counter. the count value is defined by the can protocol.
chapter 19 can controller preliminary user?s manual u16541ej1v0um 643 (10) can0 module interrupt enable register (c0ie) (1/2) (a) read 15 14 13 12 11 10 9 8 address initial value c0ie00000000 fffec057h 00h 76543210 0 0 cie5 cie4 cie3 cie2 cie1 cie0 fffec056h 00h (b) write 15 14 13 12 11 10 9 8 c0ie 0 0 set cie5 set cie4 set cie3 set cie2 set cie1 set cie0 fffec057h 76543210 0 0 clear cie5 clear cie4 clear cie3 clear cie2 clear cie1 clear cie0 fffec056h (a) read cie5 to cie0 can interrupt enable bus 0 the corresponding interrupt pending bit in the interrupt control register c0intx is disabled. 1 the corresponding interrupt pending bit in the interrupt control register c0intx is enabled.
chapter 19 can controller preliminary user?s manual u16541ej1v0um 644 (2/2) (b) write set cie5 clear cie5 cie5 bit setting 0 1 cie5 bit cleared (0) 1 0 cie5 bit set (1) other than above no change in cie5 bit?s value set cie4 clear cie4 cie4 bit setting 0 1 cie4 bit cleared (0) 1 0 cie4 bit set (1) other than above no change in cie4 bit?s value set cie3 clear cie3 cie3 bit setting 0 1 cie3 bit cleared (0) 1 0 cie3 bit set (1) other than above no change in cie3 bit?s value set cie2 clear cie2 cie2 bit setting 0 1 cie2 bit cleared (0) 1 0 cie2 bit set (1) other than above no change in cie2 bit?s value set cie1 clear cie1 cie1 bit setting 0 1 cie1 bit cleared (0) 1 0 cie1 bit set (1) other than above no change in cie1 bit?s value set cie0 clear cie0 cie0 bit setting 0 1 cie0 bit cleared (0) 1 0 cie0 bit set (1) other than above no change in cie0 bit?s value
chapter 19 can controller preliminary user?s manual u16541ej1v0um 645 (11) can0 module interrupt status register (c0ints) (1/2) (a) read 15 14 13 12 11 10 9 8 address initial value c0ints00000000 fffec059h 00h 76543210 0 0 cints5 cints4 cints3 cints2 cints1 cints0 fffec058h 00h (b) write 15 14 13 12 11 10 9 8 c0ints00000000 fffec059h 76543210 0 0 clear cints5 clear cints4 clear cints3 clear cints2 clear cints1 clear cints0 fffec058h (a) read cints5 to cints0 can interrupt status bit 0 the related interrupt source event is not pending. 1 the related interrupt source event is pending. interrupt status bit related interrupt source event cints5 can module wakeup from can sleep mode interrupt status note . cints4 can module arbitration loss interrupt status. cints3 can module protocol error interrupt status. cints2 can module error state interrupt status. cints1 can module interrupt status bit for interrupt event ?valid message frame reception in message buffer m?. cints0 can module interrupt status bit for interrupt event ?message frame successfully transmitted from message buffer m?. note only a wakeup from can sleep mode by can bus operation generates the cints5 signal. can sleep mode release by the cpu will not generate the cints5 signal.
chapter 19 can controller preliminary user?s manual u16541ej1v0um 646 (2/2) (b) write clear cint5 cint5 bit setting 0 cint5 bit not changed 1 cint5 bit cleared (0) clear cint4 cint4 bit setting 0 cint4 bit not changed 1 cint4 bit cleared (0) clear cint3 cint3 bit setting 0 cint3 bit not changed 1 cint3 bit cleared (0) clear cint2 cint2 bit setting 0 cint2 bit not changed 1 cint2 bit cleared (0) clear cint1 cint1 bit setting 0 cint1 bit not changed 1 cint1 bit cleared (0) clear cint0 cint0 bit setting 0 cint0 bit not changed 1 cint0 bit cleared (0)
chapter 19 can controller preliminary user?s manual u16541ej1v0um 647 (12) can0 module bit-rate prescaler register (c0brp) 76543210addressinitial value c0brp tqprs7 tqprs6 tqprs5 tqprs4 tqprs3 tqprs2 tqprs1 tqprs0 fffec05ah ffh (read/write) tqprs7 to tqprs0 can protocol layer basic system clock (f tq ) 0f canmod /1 1f canmod /2 nf canmod /(n+1) ..... ..... 255 f canmod /256 figure 19-28. can controller clocks ccp 3 ccp2 prescaler can0 module bit-rate prescaler register (c0brp) can0 module clock select register (c0gmcs) baud rate generator can0 module bit-rate register (c0btr) ccp1 ccp0 tqprs0 f can f canmod f tq 0 0 0 0 tqprs1 tqprs2 tqprs3 tqprs4 tqprs5 tqprs6 tqprs7 remark f can : clock supplied to can f canmod : can module system clock f tq : can protocol layer basic system clock
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 648 (13) can0 module bit rate register (c0btr) (1/2) 15 14 13 12 11 10 9 8 address initial value c0btr 0 0 sjw1 sjw0 0 tseg22 tseg21 tseg20 fffec05dh 37h (read/write) 76543210 0 0 0 0 tseg13 tseg12 tseg11 tseg10 fffec05ch 0fh figure 19-29. data bit time data bit time (dbt) time segment 1 (tseg1) phase segment 2 phase segment 1 sample point(spt) prop segment sync segment time segment 2 (tseg2)
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 649 (2/2) sjw1 sjw0 length of synchronization jump width 001 tq 012 tq 103 tq 114 tq tseg22 tseg21 tseg20 length of time segment 2 0001 tq 0012 tq 0103 tq 0114 tq 1005 tq 1016 tq 1107 tq 1118 tq tseg13 tseg12 tseg11 tseg10 length of time segment 1 0 0 0 0 setting prohibited. 0001 2 tq note 0010 3 tq note 00114 tq 01005 tq 01016 tq 01117 tq 10008 tq 10019 tq 101010 tq 101111 tq 110012 tq 110113 tq 111014 tq 111115 tq note setting prohibited when c0brp = 00h. remark tq = 1/f tq (f tq : can protocol layer basic system clock)
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 650 (14) can0 module last in-pointer register (c0lipt) 76543210addressinitial value c0lipt lipt7 lipt6 lipt5 lipt4 lipt3 lipt2 lipt1 lipt0 fffec05eh undefined (read-only) lipt7 to lipt0 last in-pointer of receive history list 0.....m max. note reading the c0lipt register delivers the message buffer number in which the last data frame was saved or the last remote frame was stored. note the maximum number of message buffers implemented in a can channel varies (m max. = 16, 32 or 48). remark as long as no data frame has been stored in a message buffer or no received remote frame has been stored, an undefined value is read from the c0lipt register. the user cannot read the c0lipt register after switching the can module to one of the operational modes as long as the rhpm bit is set (1).
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 651 (15) can0 module receive history list register (c0rgpt) (1/2) (a) read 15 14 13 12 11 10 9 8 address initial value c0rgpt rgpt7 rgpt6 rgpt5 rgpt4 rgpt3 rgpt2 rgpt1 rgpt0 fffec06h1h undefined 76543210 000000rhpmrovf fffec06h0h xxxxxx10b (b) write 15 14 13 12 11 10 9 8 c0rgpt00000000 fffec06h1h 76543210 0000000clear rovf fffec06h0h (a) read rgpt7 to rgpt0 receive history list pointer match 0.....m max. note 1 reading the c0rgpt register delivers the message buffer number from which the user has to read received data (receive message buffer) or to which a remote frame was received (transmit message buffer). rhpm receive history list pointer match 0 there is no unread message left in the rhl. 1 there is at least one unread message in the rhl. rovf receive history list overview bit 0 no overflow of the rhl occurred. upon data frame storage or remote frame assignment, the corresponding message buffer number is logged into the rhl. 1 the rhl is fully loaded with the unread message buffer number and all rhl elements besides the last one are preserved. the message buffer number of the subsequent data frame storage or remote frame assignment is always logged in the rhl element lipt pointer -1 is pointing to note 2 . notes 1. the maximum number of message buffers implemented in a can channel varies (m max. = 16, 32 or 48). 2. the rhl will be updated, but the lipt pointer will not be incremented. the position that the lipt pointer ? 1 is pointing to is always overwritten. (b) write clear rovf rovf bit setting 0 rovf bit not changed 1 rovf bit cleared (0)
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 652 (16) can0 module last out-pointer register (c0lopt) 76543210addressinitial value c0lopt lopt7 lopt6 lopt5 lopt4 lopt3 lopt2 lopt1 lopt0 fffec062h undefined (read-only) lopt7 to lopt0 last out-pointer of transmit history list 0.....m max. note reading the c0lopt register delivers the message buffer number from which the last message frame was sent. note the maximum number of message buffers implemented in a can channel varies (m max. = 16, 32, or 48) remark if no message frame has been sent, an undefined value is read from the c0lopt register as long as the thpm bit is set (1).
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 653 (17) can0 module transmit history list register (c0tgpt) (a) read 15 14 13 12 11 10 9 8 address initial value c0tgpt tgpt7 tgpt6 tgpt5 tgpt4 tgpt3 tgpt2 tgpt1 tgpt0 fffec065h undefined 76543210 000000thpmtovf fffec064h xxxxxx10b (b) write 15 14 13 12 11 10 9 8 c0tgpt00000000 fffec065h 76543210 0000000clear tovf fffec064h (a) read tgpt7 to tgpt0 transmit history list pointer match 0.....m max. note 1 reading the c0tgpt register delivers the message buffer number which can be loaded with new data for the next transmission. thpm transmit history pointer match 0 there is at least one unread message in the thl. 1 there is no unread message in the thl. tovf transmit history list overflow 0 upon successful message frame transmission, the corresponding message buffer number is logged into the thl. 1 the thl is fully loaded with the unread message buffer number and all thl elements besides the last one are preserved. the message buffer number of the successfully transmitted message frame is always logged in the thl element lopt pointer -1 is pointing to note 2 . notes 1. the maximum number of message buffers implemented in a can channel varies (m max. = 16, 32, or 48). 2. the thl will be updated, but the lopt pointer will not be incremented. the position that the lopt pointer -1 is pointing to is always overwritten. (b) write clear tovf rovf bit setting 0 tovf bit not changed 1 tovf bit cleared (0)
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 654 (18) can0 module time stamp register (c0ts) (1/2) (a) read 15 14 13 12 11 10 9 8 address initial value c0ts00000000 fffec067h 00h 76543210 00000tslocktsseltsen fffec066h 00h (b) write 15 14 13 12 11 10 9 8 c0ts00000set tslock set tssel set tsen fffec067h 76543210 00000clear tslock clear tssel clear tsen fffec066h remark the basic time stamp function cannot be used when the can module operates in ? normal operating mode with automatic block transmission ? (a) read tslock time stamp lock function enable bit 0 the time stamp lock function is disabled. the tsout signal is toggled upon every selected time stamp capture event. 1 the time stamp lock function is enabled. the tsout signal generation is locked after a data frame was successfully received in message buffer 0. tssel time stamp capture event selection bit 0 the time stamp capture event is the sof event (start-of-frame on the can bus) 1 the time stamp capture event is the eof event (the last bit of the end-of-frame field. the tsout signal is generated at the sample point of the last bit in the eof field.) tsen tsout operation setting bit 0 time stamp signal tsout generation is disabled. 1 time stamp signal tsout generation is enabled.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 655 (2/2) (b) write set tslock clear tslock tslock bit setting 0 1 tslock bit cleared (0) 1 0 tslock bit set (1) other than above no change in tslock bit ? s value set tssel clear tssel tssel bit setting 0 1 tssel bit cleared (0) 1 0 tssel bit set (1) other than above no change in tssel bit ? s value set tsen clear tsen tsen bit setting 0 1 tsen bit cleared (0) 1 0 tsen bit set (1) other than above no change in tsen bit ? s value
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 656 (19) can0 message data byte register (c0mdata x m) (x = 0 to 7, m = 0 to 31) 76543210addressinitial value c0mdata01m mdata01 7 mdata01 6 mdata01 5 mdata01 4 mdata01 3 mdata01 2 mdata01 1 mdata01 0 fffecxx0h fffecxx1h undefined 76543210addressinitial value c0mdata0m mdata0 7 mdata0 6 mdata0 5 mdata0 4 mdata0 3 mdata0 2 mdata0 1 mdata0 0 fffecxx0h undefined 76543210addressinitial value c0mdata1m mdata1 7 mdata1 6 mdata1 5 mdata1 4 mdata1 3 mdata1 2 mdata1 1 mdata1 0 fffecxx1h undefined 76543210addressinitial value c0mdata23m mdata23 7 mdata23 6 mdata23 5 mdata23 4 mdata23 3 mdata23 2 mdata23 1 mdata23 0 fffecxx2h fffecxx3h undefined 76543210addressinitial value c0mdata2m mdata2 7 mdata2 6 mdata2 5 mdata2 4 mdata2 3 mdata2 2 mdata2 1 mdata2 0 fffecxx2h undefined 76543210addressinitial value c0mdata3m mdata3 7 mdata3 6 mdata3 5 mdata3 4 mdata3 3 mdata3 2 mdata3 1 mdata3 0 fffecxx3h undefined 76543210addressinitial value c0mdata45m mdata45 7 mdata45 6 mdata45 5 mdata45 4 mdata45 3 mdata45 2 mdata45 1 mdata45 0 fffecxx4h fffecxx5h undefined 76543210addressinitial value c0mdata4m mdata4 7 mdata4 6 mdata4 5 mdata4 4 mdata4 3 mdata4 2 mdata4 1 mdata4 0 fffecxx4h undefined 76543210addressinitial value c0mdata5m mdata5 7 mdata5 6 mdata5 5 mdata5 4 mdata5 3 mdata5 2 mdata5 1 mdata5 0 fffecxx5h undefined 76543210addressinitial value c0mdata67m mdata67 7 mdata67 6 mdata67 5 mdata67 4 mdata67 3 mdata67 2 mdata67 1 mdata67 0 fffecxx6h fffecxx7h undefined 76543210addressinitial value c0mdata6m mdata6 7 mdata6 6 mdata6 5 mdata6 4 mdata6 3 mdata6 2 mdata6 1 mdata6 0 fffecxx6h undefined 76543210addressinitial value c0mdata7m mdata7 7 mdata7 6 mdata7 5 mdata7 4 mdata7 3 mdata7 2 mdata7 1 mdata7 0 fffecxx7h undefined
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 657 (20) can0 message data length code register m (c0mdlcm) 76543210addressinitial value c0mdlcm 0 0 0 0 mdlc3 mdlc2 mdlc1 mdlc0 fffecxx8h 0000xxxxb mdlc3 mdlc2 mdlc1 mdlc0 message data length code 0 0 0 0 0 bytes 0 0 0 1 1 byte 0 0 1 0 2 bytes 0 0 1 1 3 bytes 0 1 0 0 4 bytes 0 1 0 1 5 bytes 0 1 1 0 6 bytes 0 1 1 1 7 bytes 1 0 0 0 8 bytes 1 0 0 1 data frame contains 8 bytes in the data field. 1 0 1 0 data frame contains 8 bytes in the data field. 1 0 1 1 data frame contains 8 bytes in the data field. 1 1 0 0 data frame contains 8 bytes in the data field. 1 1 0 1 data frame contains 8 bytes in the data field. 1 1 1 0 data frame contains 8 bytes in the data field. 1 1 1 1 data frame contains 8 bytes in the data field. caution be sure to write 0000b to bits 7 to 4 of the c0mdlcm register.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 658 (21) can0 message configuration register (c0mconfm) 76543210addressinitial value c0mconfm ows rtr mt2 mt1 mt0 0 0 ma0 fffecxx9h xxxxxxxxb ows overwrite select bit 0 a newly received data frame does not overwrite the occupied message buffer note . the newly received data frame is discarded. 1 a newly received data frame overwrites an occupied message buffer note an occupied message buffer means a receive message buffer into which a data frame has already been accepted (i.e. dn is set(1)), but the cpu has not yet read that message buffer. rtr remote frame request bit note 0 data frame transmission 1 remote frame transmission note the rtr bit only determines the message frame for the transmission process from a message buffer defined as transmit message buffer (i.e. mt2 to mt0 = 00h). upon valid reception of a remote frame, rtr remains cleared (0) in the corresponding transmit message buffer. if a transmit message buffer is prepared to send a remote frame by setting the rtr bit (1) and a remote frame is received in parallel from the can bus, that received remote frame is not accepted by the message buffer. that is, no interrupt generation, no update of the dn flag, no update of the mdlc3 to mdlc0 bit string and no update of the receive history list will be issued for that buffer. mt2 mt1 mt0 message buffer type 0 0 0 message buffer is a transmit message buffer. 0 0 1 message buffer is a receive message buffer not linked to a mask in the assigned can i/f channel. 0 1 0 message buffer is a receive message buffer linked to mask 1 in the assigned can i/f channel. 0 1 1 message buffer is a receive message buffer linked to mask 2 in the assigned can i/f channel. 1 0 0 message buffer is a receive message buffer linked to mask 3 in the assigned can i/f channel. 1 0 1 message buffer is a receive message buffer linked to mask 4 in the assigned can i/f channel. other than above setting prohibited. ma0 message buffer assignment 0 a message buffer is not assigned to any can i/f channel. 1 a message buffer is assigned to can i/f channel 1. caution be sure to set bits 2 and 1 to 0.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 659 (22) can0 message identifier registers (c0midlm, c0midhm) (m = 0 to 31) 15 14 13 12 11 10 9 8 address initial value c0midlm id15 id14 id13 id12 id11 id10 id9 id8 fffecxxbh undefined (read/write) 7 6543210 id7 id6 id5 id4 id3 id2 id1 id0 fffecxxah 15 14 13 12 11 10 9 8 c0gmctrl ide 0 0 id28 id27 id26 id25 id24 fffecxxdh (read/write) 7 6543210 x00xxxxx xxxxxxxxb id23 id22 id21 id20 id19 id18 id17 id16 fffecxxch ide identifier extension bit 0 11-bit standard identifier note . 1 29-bit extended identifier note the id17 to id0 bits are not used and may contain undefined values. id28 to id0 message identifier id28 to id18 = 0...(2 11 ? 1) range for 11-bit standard identifier values id28 to id0 = 0...(2 29 ? 1) range for 29-bit extended identifier values
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 660 (23) can0 message control register m (c0mctrlm) (1/3) (a) read 15 14 13 12 11 10 9 8 address initial value c0mctrlm00muc00000 fffecxxfh 76543210 00x00000h 000xx000b 0 0 0 mow ie dn trq rdy fffecxxeh (b) write 15 14 13 12 11 10 9 8 c0mctrlm0000set ie set dn set trq set rdy fffecxxfh 76543210 0 0 0 clear mow clear ie clear dn clear trq clear rdy fffecxxeh (a) read muc message buffer under change flag 0 the assigned can module is not writing to the message buffer. 1 the assigned can module is writing to the message buffer. mow message buffer overwritten flag 0 a newly received data frame has not overwritten the message buffer. 1 a newly received data frame has overwritten the message buffer.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 661 (2/3) ie interrupt enable for message buffer interrupt event 0 interrupt generation is disabled for the following events: ? interrupt events linked to the cints0 interrupt status bit in the c0ints register (i.e. when mt2 to mt0 = 0, ? data frame successfully transmitted from message buffer m ? , ? remote frame successfully transmitted from message buffer m ? ) ? interrupt events linked to the cints1 interrupt status bit in the c0ints register (i.e. when mt2 to mt0 = 1, 2, 3, 4 or 5, ? valid data frame reception in message buffer m ? and when mt2 to mt0 = 0 ? valid remote frame reception in message buffer m ? ) 1 interrupt generation is enabled for the following events: ? interrupt events linked to the cints0 interrupt status bit in the c0ints register (i.e. when mt2 to mt0 = 0, ? data frame successfully transmitted from message buffer m ? , ? remote frame successfully transmitted from message buffer m ? ) ? interrupt events linked to the cints1 interrupt status bit in the c0ints register (when mt2 to mt0 = 1, 2, 3, 4 or 5, ? valid data frame reception in message buffer m ? and when mt2 to mt0 = 0 ? valid remote frame reception in message buffer m. ? ) dn message buffer data new bit 0 no data frame has been stored in the message buffer (message buffer is defined as receive message buffer (mt2 to me0 > 00h)). no remote frame has been stored in the message buffer (message buffer is defined as receive message buffer (mt2 to me0> 00h)). 1 a data frame has been stored in the message buffer (message buffer is defined as receive message buffer (mt2 to me0 > 00h)). a remote frame has been stored in the message buffer (message buffer is defined as receive message buffer (mt2 to me0> 00h)). caution be sure not to set the dn flag (1) by software. trq message buffer transmit request bit 0 no message frame transmission request is pending or ongoing from the message buffer. 1 a message frame transmission request is pending or a message frame transmission is ongoing from the message buffer. rdy message buffer ready bit 0 the cpu can write to the message buffer. the assigned can module does not access the message buffer. 1 the assigned can module accesses the message buffer. cpu write access to the message buffer is ignored (except write access to the rdy bit, trq bit, dn bit and mow bit).
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 662 (3/3) (b) write clear mow mow bit setting 0 mow bit not changed 1 mow bit cleared (0) set ie clear ie ie bit setting 0 1 ie bit cleared (0) 1 0 ie bit set (1) other than above no change in ie bit ? s value set dn clear dn dn bit setting 0 1 dn bit cleared (0) 1 0 dn bit set (1) other than above no change in dn bit ? s value set trq clear trq trq bit setting 0 1 trq bit cleared (0) 10trq bit set (1) other than above no change in trq bit ? s value set rdy clear rdy rdy bit setting 0 1 rdy bit cleared (0) 1 0 rdy bit set (1) other than above no change in rdy bit ? s value
chapter 19 can controller preliminary user?s manual u16541ej1v0um 663 19.7 bit set/clear function the can control registers include registers whose bits can be set or cleared via the cpu and via the can interface. an operation error occurs if the following registers are written directly. do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values. ? can0 control register (c0gmctrl) ? can0 automatic block transmission register (c0gmabt) ? can0 module control register (c0ctrl) ? can0 module interrupt enable register (c0ie) ? can0 module interrupt status register (c0ints) ? can0 module receive history list register (c0rgpt) ? can0 module interrupt history list register (c0tgpt) ? can0 module time stamp register (c0ts) ? can0 message control register (c0mctrlm) remark m = message buffer number (0 to 31) all 16 bits in the above registers can be read via the usual method. use the procedure described in figure 19-30 below to set or clear the lower 8 bits in these registers. setting or clearing of the lower 8 bits in the above registers is performed in combination with the higher 8 bits (see figure 19-31 ). figure 19-30 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register. figure 19-30. example of bit setting/clearing operations 0000000011010001 0000101111011000 set00001011 0000000000000011 clear 11011000 set set no change no change clear no change clear clear bit status register ? s current values write values register ? s value after write operations
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 664 figure 19-31. 16-bit data during write operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n clear n status of bit n after bit set/clear operation 0 0 no change 01 0 10 1 1 1 no change
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 665 19.8 can controller initialization 19.8.1 initialization of can module before the can module operation is enabled, the can module system clock needs to be set in ccp[3:0] of the c0gmcs register by software. do not change the setting of the can module system clock after can module operation is enabled. the can module is enabled by setting (1) the gom bit of the c0gmctrl register. regarding initialization processing, see 19.16 operation of can controller 19.8.2 initialization of message buffer after the can module is enabled, the message buffers contain undefined values. a minimum initialization for all message buffers, even for those not used in the application, is necessary before switching the can module from init mode to one of the operational modes. the minimum initialization has to include the proper configuration of the following bits and bit strings to avoid unexpected behavior from the can module in the operational modes. table 19-22. minimum configuration of message buffer even when unused in application register bit minimum initialization value c0mctrlm rdy 0b c0mctrlm trq 0b c0mctrlm dn 0b c0mconfm ma0 0b
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 666 19.8.3 transition from init mode to operational mode the can module in each can i/f channel can be switched to the following operational modes. ? normal operating mode ? ? normal operating mode with automatic block transmission ? ? receive-only mode ? ? single-shot mode ? ? self-test mode ? figure 19-32. transition to can module operational modes can i/f ch annel disab led gom = 1 can module init mode opmode[2:0] =00h can module " normal operating mode" opmode[2:0]=01h opmode[2:0]=01h opmode[2:0]=00h and can bus idle can module "normal operating mode with automatic block transmission" opmode[2:0]=02h opmode[2:0]=00h and can bus idle can module " single-shot mode " opmode[2:0]=04 h opmode[2:0]=04h opmode[2:0]=00h and can bus idle opmode[2:0]=00h and can bus busy opmode[2:0]=00h and can bus busy opmode[2:0]=00h and can bus busy (all can module s in init mode) and (gom = 0) not all can modules in init mode and gom = 0 efsd = 1 and gom = 0 opmode[2:0]=03h can module " recei ve-only mode " opmode[2:0]=03h opmode[2:0]=00h and can bus idle opmode[2:0]=00h and can bus busy can module " self-test mode" opmode[2:0]=05 h opmode[2:0]=05h opmode[2:0]=00h and can bus idle opmode[2:0]=00 h and can bus busy opmode[2:0]=02h reset release reset the transition from init mode to the operational modes is controlled by the bit strings opmode2 to opmode0 in the c0ctrl register. changing from one operational mode to another requires shifting to init mode in between. the can module refuses cpu attempts to change from one operational mode to another directly. transition requests from the operational modes to the init mode are not directly accepted by the can module when the can bus is not idle (i.e. frame reception or transmission is ongoing), but it is kept until the can module detects the first bit of intermission. as soon the above mentioned condition is detected, the transition from the operational mode to the init mode is executed and the opmode2 to opmode0 bit string values change to 00h. the cpu has to confirm the proper transition to init mode by reading the opmode2 to opmode0 bit strings until opmode2 to opmode0 = 000b.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 667 19.8.4 resetting of can module error counter c0erc in init mode for evaluation purposes, it is necessary to reset the can module error counter c0erc and the can module information register c0info. therefore it is possible to set the ccerc bit in the c0ctrl register (1) in init mode of the can module. as a result, the can module error counter c0erc and the can module information register c0info register are cleared to their default values when the can module shifts to any operational mode.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 668 19.9 message reception 19.9.1 message reception in all the operational modes of the can module, when a data frame is received, whether the received data frame has to be stored in one of the message buffers that satisfy the following conditions is checked. ? the message buffer has to be assigned to receive data frames (ma0 bit set (1) in c0mconfm register) ? the message buffer has to be configured as a receive message buffer (mt[2:0] bit string in c0mconfm register has to hold the values 001b, 010b, 011b, 100b or 101b) ? the message buffer has to be marked ready for can protocol processing (rdy bit set (1) in c0mctrlm register) when two or more message buffers of the can module receive a message, the message (data frame or remote frame) is always stored in the receive message buffer with the highest priority. for example, when an unmasked receive message buffer and a message buffer linked to mask 0 have the same identifier, the message is always stored in the unmasked receive message buffer even if this unmasked receive message buffer has already received a message earlier (dn flag is set already). priority conditions 1 (highest) unmasked message buffer 2 message buffer linked to mask 1 3 message buffer linked to mask 2 4 message buffer linked to mask 3 5 (lowest) message buffer linked to mask 4 19.9.2 receive history list function the receive history list (rhl) function records the number of the receive message buffer in which each data frame or remote frame was stored. the rhl consists of 23 elements and two pointers, the last in-message pointer (lipt pointer) with the corresponding c0lipt register and the receive history list get pointer (rgpt pointer) with the corresponding c0rgpt register. after the transition from init mode to one of the operational modes, the rhl elements contain undefined values. the lipt pointer is utilized as a write pointer for the message buffer numbers stored in the rhl. anytime a data frame or remote frame is stored, a message buffer number is recorded to the rhl element. the lipt pointer points to this element. the lipt pointer is incremented automatically when new elements are entered in the rhl. in this way, the number of message buffers that received new messages recently will be recorded chronologically. the rgpt pointer is utilized as a read pointer for message buffer numbers stored in the rhl. the rgpt pointer points to the first rhl element that the cpu did not read yet. a stored message buffer number is read by reading the c0rgpt register. the rgpt pointer is incremented automatically each time a message buffer number is read from the c0rgpt register. the receive history list pointer match bit (rhpm bit) in the c0rgpt register is set (1) whenever the rgpt pointer matches the lipt pointer. the rhpm bit set (1) signals to the application software that no more message frames have been received. when a new message buffer number is recorded, the lipt pointer is incremented again, and the rhpm bit is cleared (0). in other words, the message buffer numbers that are stored in rhl indicate unread message buffers. the receive history list overflow bit (rovf bit) is set (1) from the can module whenever the lipt pointer points to the rgpt pointer-1. in this state, the rhl is completely filled with message buffer numbers that have not been read yet. when further reception of messages occurs, the last record in rhl is overwritten by the buffer number of the
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 669 newly stored message. therefore, after the rovf bit is set (1), a recorded message buffer number in the rhl does not completely reflect the chronological order. figure 19-33. receive history list 23 msg # 7 msg # 2 msg # 9 msg # 6 1 2 3 4 5 6 7 8 receive history list get pointer receive history list (rhl) receive history list (rhl) last in- message pointer 23 msg # 8 msg # 4 msg # 3 msg # 7 msg # 2 msg # 9 1 2 3 4 5 6 7 8 last in- message pointer message buffer #6 get (read) 23 1 2 3 4 5 6 7 8 receive history list (rhl) receive history list (rhl) 23 msg # 9 msg # 5 msg # 8 msg # 4 msg # 3 msg # 7 msg # 2 msg # 9 msg # 7 1 2 3 4 5 6 7 8 message buffer #3 receive rhl is in the full state rovf is set (1). msg # 9 msg # 5 msg # 8 msg # 4 msg # 3 msg # 7 msg # 2 msg # 9 msg # 3 last in- message pointer (rgpt) receive history list get pointer (rgpt) receive history list get pointer (rgpt) receive history list get pointer (rgpt) (lipt) (lipt) (lipt) last in- message pointer (lipt)
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 670 figure 19-34. message reception procedure using receive history list sw read data request rhpm bit cleared (0) or cints1 bit set (1) rovf bit set (1) clear rovf bit (0) sw read access to rgpt pointer sw clears dn bit (0) of particular message buffer sw read access to message buffer dn bit cleared (0) and muc bit cleared (0) rhpm bit set (1) clear cints1 (0) end ye s no no ye s ye s ye s no no
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 671 figure 19-35. c0rgpt pointer handling with respect to rhpm bit start rhpm = 1 read access to the rgpt pointer end ye s no
chapter 19 can controller preliminary user?s manual u16541ej1v0um 672 19.9.3 mask function a mask function can be linked to each receive message buffer. this means that there is no need to distinguish between local masks and global masks. when the mask function is used, the identifier of a received message is compared with the identifier of the particular message buffer. bits in the mask configured as ?don?t care? will prevent any comparison. thus, the respective bits of the identifier of the receive message will be stored regardless of the corresponding values in the message buffer. when the mask function is linked to a receive message buffer, a bit whose value is defined as ?1? by masking is not subject to the above-mentioned comparison between the identifier of the received message and the identifier in the message buffer. however, this comparison is performed for any bit whose value is defined as ?0? by the mask. for example, let us assume that all messages that have a standard-format identifier, in which bits id27 to id25 = 0 and bits id24 and id22 = 1, are to be stored in message buffer 14. the procedure for this example is shown below. example: <1> identifier bits to be stored in message buffer 14 id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x0001x1xxxx x = don?t care messages with id in which bits id27 to id25 = 0 and bits id24 and id22 = 1 are registered (initialized) in message buffer 14. <2> identifier bits to be configured in message buffer 14 (example) (using can0 message id registers l14 and h14 (c0midl14 and c0midh14)) id28 id27 id26 id25 id24 id23 id22 id21 id20 id19 id18 x0001x1xxxx id17 id16 id15 id14 id13 id12 id11 id10 id9 id8 id7 xxxxxxxxxxx id6 id5 id4 id3 id2 id1 id0 xxxxxxx x = don?t care message buffer 14 is set as a standard-format identifier linked to mask 1.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 673 <3> mask setting for can module 1 (mask 1) (example) (using can1 address mask 1 registers l and h (c1maskl1 and c1maskh1)) cmid28 cmid27 cmid26 cmid25 cmid24 cmid23 cmid22 cmid21 cmid20 cmid19 cmid18 10000101111 cmid17 cmid16 cmid15 cmid14 cmid13 cmid12 cmid11 cmid10 cmid9 cmid8 cmid7 11111111111 cmid6 cmid5 cmid4 cmid3 cmid2 cmid1 cmid0 1111111 1: do not compare (mask) 0: compare values are written to mask 1, bits cmid27 to cmid24 and cmid22 = 0 and bits cmid28, cmid23, and cmid21 to cmid0 = 1. 19.9.4 multi buffer receive block function two or more receive message buffers can be grouped as a multi buffer receive block (mbrb) by setting the same id to two or more message buffers. the mbrb can store two or more data frames from the can bus without overwriting previously received messages. support by the cpu is not necessary for this operation. the user can determine which data block reception completion the cpu has to be informed of by setting the ie bit in the c0mctrlm register of the message buffer. if a data block consists of message k, the user could initialize the message k buffer for the reception of the data block. in message buffers 0 to (k-1) the ie bits are cleared (0) (i.e. interrupts disabled) and in message buffer k the ie bit is set (1) (interrupts enabled). this kind of configuration establishes a ring buffer that provides received messages to the cpu in a fifo manner when the cpu reads the messages before the mbrb overflows. 19.9.5 remote frame reception in the operational modes ? normal operating mode ? , ? normal operating mode with abt ? , ? receive-only mode ? , ? single-shot mode ? and ? self-test mode ? the receive message acceptance filtering machine evaluates all message buffers that satisfy the following conditions as to whether the received remote frame should be accepted. ? the message buffer has to be assigned to the can i/f channel (ma0 bit in c0mconfm register is set to 1b or larger). ? the message buffer has to be configured as a transmit message buffer (mt2 to mt0 bits in c0mconfm register are set to 000b). ? the message buffer has to be marked ready for can protocol processing (rdy bit set (1) in c0mctrlm register) ? the rtr bit in the transmit message buffer has to be cleared (0). ? the trq bit in the transmit message buffer has to be cleared (0). upon acceptance of a remote frame, the following actions are executed if the identifier of the received remote frame matches the identifier of a message buffer that satisfies the above conditions. ? the mdlc[3:0] bit string in the c0mdlcm register is overwritten by the dlc value of the received remote frame. ? the dn flag is set (1) ? the interrupt status bit cints1 in the c0ints register is set (1)
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 674 ? when it has been enabled by setting the cie1 enable bit in the c0ie register (1), the interrupt request signal intc0trec is generated. ? the reception history list is updated with the message buffer number for which the received remote frame has been accepted ? the setting of the ows bit in the c0mconfm register has no meaning for the acceptance of a remote frame. it means the remote frame is accepted regardless of whether the ows bit is cleared (0) or set (1) and the dn flag has already been set (1). if more than one transmit message buffer with the same identifier is assigned to a can i/f channel, the remote frame acceptance evaluation is just executed for the transmit message buffer with the lowest message buffer number.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 675 19.10 message transmission 19.10.1 message transmission in the operational modes ? normal operating mode ? , ? normal operating mode with abt ? and ? single-shot mode ? and ? self-test mode ? of the can module, the transmit message search machine is triggered when the trq bit is set to 1 in a message buffer that satisfies the following conditions. ? the message buffer has to be assigned to the particular can i/f channel (ma0 bit in c0mconfm register is set to 1b or larger). ? the message buffer has to be configured as a transmit message buffer (mt2 to mt0 bits in c0mconfm register are set to 000b). ? the message buffer has to be marked ready for can protocol processing (rdy bit set (1) in c0mconfm register). the can system is a multiplexed communication system. the priority of message transmission within this system is determined based on message identifiers (ids). to facilitate communication processing by application software when there are several messages awaiting transmission, the can module uses hardware to check the priority identifiers and automatically determine which message has to be sent out first. this eliminates the need for software-based priority control. figure 19-36. message processing example (when pbb bit = 0) message no. can module transmits messages in the following sequence. message waiting to be transmitted id = 120h id = 229h id = 223h id = 023h id = 123h 0 1 2 3 4 5 6 7 8 9 1. message 6 2. message 1 3. message 8 4. message 5 5. message 2 the transmit message search machine compares the message buffer that has a new transmit request with the message buffers in which the trq bit is set to 1. if the new transmit request has the highest priority, the transmit message search machine overwrites the temporary transmit buffer with the message frame, which is stored in the corresponding message buffer. overwriting is only possible as long the transmit process has not already been started for the message frame currently occupying the temporary transmit buffer. if overwriting of the temporary transmit buffer is impossible, the new transmit request is sent at a later point in time. the highest priority is determined according the following rules.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 676 priority conditions description 1 (highest) 11 msb identifier value rule [id28 to id18] the first 11 bits of the identifier (i.e. id28 to id18) are the first criteria used to judge which message frame has to be sent first. as a result, message frames with the lowest value represented by the 11 most significant bits of the identifier have to be sent first. 11-bit standard identifiers have a higher priority than message frames with 29-bit extended identifiers if the value of the 11-bit standard identifier is equal to or smaller than the 11 most significant bits (11 msb) of the 29-bit extended identifier. 2 frame type rule the priority 1 rule does not provide an unambiguous result when the 11 most significant bits of the identifier are equal. then the frame type represented by the rtr bit of 11-bit standard identifier message frames and the srr bit of the 29-bit extended identifier message frames is the next criteria to judge which message frame has to be sent first. in this case data frames with 11-bit standard identifiers (i.e. rtr bit cleared (0)) have a higher priority than remote frames with a standard identifier and message frames with an extended identifier. 3 identifier type rule if even the priority 2 rule cannot deliver an unambiguous result, the identifier type represented by the ide bit is the next criteria in the decision process. in this case a standard identifier message frame (i.e. ide bit cleared (0)) has a higher priority than a message frame with an extended identifier. 4 18 lsb identifier value rule [id17 to id0] the next criteria to find the message that has to be sent first are the 18 least significant bits of the extended identifier. the message frame with the lowest value represented by those bits is sent first. the priority 4 rule applies in cases where two transmission-pending extended identifier message frames have equal values in the 11 most significant bits of the identifier and have the same frame type (the rtr bit value is the same). 5 (lowest) message buffer number the last criteria to find the message that has to be sent first is the message buffer number. the priority 5 criteria applies when 2 or more message buffers try to send message frames with exactly the same identifier. in this case the message from the message buffer with the lowest message buffer number is sent first. remark when the can module operates in ? normal operating mode with abt ? only one message buffer from the abt message buffer group has the trq bit set to 1 at a time. this buffer competes with transmit message buffers, which do not belong to the abt message buffers. within the abt message buffers, a fixed order determines which message buffer is sent next. upon successful transmission of a message frame, the trq flag in the corresponding transmit message buffer is automatically cleared (0) and the corresponding ? transmit successful ? interrupt status bit cints0 in the c0ints register is set (1). in addition, an interrupt request signal will be released, when it has been enabled by setting the cie0 enable bit in the c0ie register (1).
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 677 19.10.2 transmit history list function the transmit history list (thl) function records the number of the message buffer for each transmitted message (data frame or remote frame). the thl consists of 7 elements and two pointers, the last out-message pointer (lopt pointer) with the corresponding c0lopt register and the transmit history list get pointer (tgpt pointer) with the corresponding c0tgpt register. after the transition from init mode to one of the operational modes, the thl elements contain undefined values. the lopt pointer is utilized as a write pointer for message buffer numbers in the thl. when a data frame or remote frame was transmitted successfully, a message buffer number is recorded to the thl element referenced by the lopt pointer. when the record to the thl is completed, the lopt pointer is incremented automatically. in this way, message buffer numbers of transmitted messages are recorded chronologically. the tgpt pointer is utilized as a read pointer for message buffer numbers in the thl. the tgpt pointer points to the first thl element that cpu has not read yet. a message buffer number is read by reading the c0tgpt register. the tgpt pointer is incremented automatically anytime a message buffer number from the c0tgpt register is read. the transmit history list pointer match bit (thpm bit) in the c0tgpt register is set (1) whenever the tgpt pointer matches the lopt pointer. the thpm bit setting (1) signals to the application software that no more message frames have been sent. when a new message is sent, the lopt pointer is incremented, the pointers do not match anymore, and the thpm bit is cleared (0). in other words, numbers of message buffers that have not been read yet are stored in the thl. the transmit history list overflow bit (tovf bit) is set (1) from the can module whenever the lopt pointer points to the tgpt pointer-1. in this state, the thl is completely filled with message buffer numbers that have not been read yet. when further transmission occurs, the last entry in the thl is overwritten, and a record of the message buffer number from where the last transmission was executed is stored. therefore, after the tovf bit is set (1), a recorded message buffer number in the thl does not completely reflect the chronological order. figure 19-37. transmit history list msg # 7 msg # 2 msg # 9 msg # 6 1 2 3 4 5 6 7 transmit history list get pointer (tgpt) transmit history list get pointer (tgpt) transmit history list get pointer (tgpt) transmit history list get pointer (tgpt) transmit history list (thl) transmit history list (thl) transmit history list (thl) transmit history list (thl) last on- message pointer msg # 4 msg # 3 msg # 7 msg # 2 msg # 9 1 2 3 4 5 6 7 message buffer #6 get (read) 1 2 3 4 5 6 7 msg # 8 msg # 4 msg # 3 msg # 7 msg # 2 msg # 9 msg # 7 1 2 3 4 5 6 7 message buffer #3 transmit thl is in the full state tovf is set (1). msg # 8 msg # 4 msg # 3 msg # 7 msg # 2 msg # 9 msg # 3 (lopt) last on- message pointer (lopt) last on- message pointer (lopt) last on- message pointer (lopt)
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 678 figure 19-38. message transmission procedure using transmit history list start new message successfully transmitted: increment lopt pointer lopt = 1 tgpt-1 ye s no tovf = 1 end
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 679 figure 19-39. c0tgpt pointer handling with respect to thpm bit start thpm = 1 read access to the tgpt pointer end ye s no
chapter 19 can controller preliminary user?s manual u16541ej1v0um 680 19.10.3 automatic block transmission (abt) the automatic block transmission (abt) function can transfer data frames successively with no cpu interaction. the maximum number of transmit message buffers assigned to the abt function is 8 (message buffer numbers 0 to 7). the abt function is selected by setting the opmode[2:0] bit string. for the abt function, the message buffers must be initialized before a transmission request by the cpu is submitted in the abt mode. for all message buffers used for abt, the can module assignment (max) has to be set and the mt[2:0] bits have to be set to 000b. if several data blocks are sent in separate messages but with the same identifier, all message buffers in the abt area have to be set with the same identifier. if two or more data frames with different identifiers are sent, the identifier needs to be set by the c0midlm/c0midhm register. the c0mdlcm register and the c0mdata0m to c0mdata7m registers have to be set before a transmission request for the abt function is submitted. after initialization of a message buffer for abt is finished, the rdy bit needs to be set (1). in the abt mode, the trq bit does not have to be manipulated by software. after all the data for the message buffer in the abt area has been prepared, the abttrg bit can be set (1). then the automatic block transmission of the message buffer with rdy = 1 is started. the abt function sets trq of the first message buffer (message buffer 0) automatically, and the transmission of a message is started. after the transmission of message buffer 0 has finished, trq of message buffer 1 is set (1) automatically, and the message is transmitted. however the abt function enables delaying the setting of the next trq automatically by a programmable period. this delay is defined by the c0gmabtd register. the unit of the lsb of that register is the dbt (data bit time). the dbt depends on the setting in the c0brp register and the c0btr register. when the abt function encounters a message buffer with rdy = 0, the abttrg bit is cleared (0) and the abt operation is finished. in this situation, the rdy bit of the buffer where the abt mode stopped can be set and the abttrg bit can be set (1) again. then the abt function will continue the abt mode from the message buffer at which it stopped previously. if it is not necessary to continue the abt mode at the buffer where the abt mode previously stopped, clear (0) the abttrg bit via the abtclr bit. the internal abt engine is reset by when the abtclr bit is set (1). if abttrg is set (1) again now, the transmission is started from message buffer 0. the transmission of data frames from all the message buffers in the abt area can be controlled by using the transmission complete interrupt. the ie bit of the c0mctrlm register of each message buffer in use except the last message buffer needs to be cleared (0). in this case, the application will get a transmission complete interrupt when all messages in the abt area have been sent. normally, the transmission of message buffers except those used by the abt function (message buffer 8 to n max ) is defined by the priority of the identifier. in this case the sequence of transmitted messages is evaluated between the identifier of the message buffer in the abt area waiting for transmission and all other identifiers not belonging to the abt area. when the abt function is activated, the transmission of data frames from message buffers in the abt area is not recorded in the transmission history list (thl). 19.10.4 transmission request abort process (1) transmission request abort in normal operation mode the user can clear the trq bit in the c0mctrlm register to abort a transmit request. the trq bit will be cleared immediately if the abort was successful. whether the message was really transmitted or not can be checked using the tstat bit in the c0ctrl register or the thl. (2) transmission request abort in normal operation mode with automatic block transmission (abt) it can become necessary to abort an already started automatic block transmission (abt). in this case, the user has to clear the abttrg bit in the cgmabt register (0). if the last transmission was successful, the abt mode is left with the internal abt pointer pointing to the next message buffer to be transmitted.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 681 in the case of an erroneous transmission, the position of the internal abt pointer depends on the status of the trq bit of the last transmitted message buffer. ? if the trq bit was cleared (0) in addition to the clear of abttrg (0), the internal abt pointer points to the next message buffer. ? if the trq bit remains set at the time when abttrg is cleared(0), the internal abt pointer points to the last transmitted message buffer. in the case of a restart of the abt mode (abttrg is set (1)), the next message to be transmitted can be determined from the following table. trq abort after successful transmission abort after erroneous transmission set (1) next message buffer in the abt area note same message buffer in the abt area cleared (0) next message buffer in the abt area note next message buffer in the abt area note note if the last message buffer in the abt area (buffer 7) is reached or if all the subsequent buffers in the abt area have their rdy bit cleared (0), the internal abt pointer points to buffer 0. (3) transmission of remote frames remote frames are only sent from message buffers defined as transmit message buffers. to distinguish a transmission request for a data frame and for a remote frame, the rtr bit in the c0mconfm register has to be programmed accordingly. setting (1) the rtr bit defines a remote frame transmission request.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 682 19.11 power saving modes 19.11.1 can sleep mode the can sleep mode can be used to set the can controller to standby mode in order to reduce power consumption. the can sleep mode can be entered from all operational modes of the can module. a release of the can sleep mode returns the can module to exactly the same operational mode from which the can sleep mode was entered. in the can sleep mode, the can module does not transmit messages, even when transmit requests are issued or pending. (1) entering can sleep mode the cpu issues a can sleep mode transition request by writing 01b to the psmode1, psmode0 bit string in the c0ctrl register. that transition request is only accepted under the following conditions. (i) the can module is already in one of the following operational modes. ? ? normal operating mode ? ? ? normal operating mode with automatic block transmission ? ? ? receive-only mode ? ? ? single-shot mode ? ? ? self-test mode ? ? ? can stop mode ? (ii) the can bus state is bus idle. if one of the conditions mentioned above is not met, the can module will operate as follows. ? if can sleep mode is requested from init mode, the can sleep mode transition request is ignored and the can module remains in init mode. ? if the can bus state is not bus idle (i.e., the can bus state is either ? transmitting ? or ? receiving ? ) when can sleep mode is requested, immediate transition to can sleep mode is not possible. the can sleep mode transition request has to be held pending until the can bus state becomes bus idle. in the time from can sleep mode transition request to successful transition, the psmode1, psmod0 bit string remains 00h. (2) releasing can sleep mode the can sleep mode is released by the following events. ? when the cpu writes 00b to the psmode1, psmode0 bit string in the c0ctrl register. ? a falling edge on the can0rx pin (i.e., the can bus level shifts from recessive to dominant) after releasing the can sleep mode, the can module returns to the operational mode from which can sleep mode was requested and psmode1, psmode0 in the c0ctrl register are reset to 00b. the interrupt status bit cints5 in the c0ints register is also set (1), if the interrupt enable bit cie5 is set (1). when init mode is requested while the can module is in can sleep mode, that request is ignored; the cpu has to release sleep mode first before entering the init mode. 19.11.2 can stop mode the can stop mode can be used to set the can controller to standby mode to reduce power consumption, but without the ability to wake up again autonomously. the can stop mode can only be entered from the can sleep mode of the can module. a release of the can stop mode puts the can module in the sleep mode. in the can stop mode, the can module does not transmit messages, even when transmit requests are issued or pending.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 683 (1) entering can stop mode the cpu issues a can stop mode transition request by writing 10b to the psmode1, psmode0 bit string in the c0ctrl register. the can stop mode transition request is only accepted when the can module is in can sleep mode. in all other modes, the can stop mode transition request is ignored. (2) releasing can stop mode the can stop mode can only be released by writing 01b to the psmode1, psmode0 bit string in the c0ctrl register. when init mode is requested while the can module is in can stop mode, that request is ignored; the cpu has to release stop mode and subsequently can sleep mode before entering the init mode.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 684 19.12 interrupt function 19.12.1 interrupts generated by can module each can module of a can i/f channel provides 6 different interrupt sources. the occurrence of these interrupt sources is stored in interrupt status registers. four separate interrupt request signals are generated from the six sources. after determination of the interrupt source, the user has to clear the corresponding interrupt status bit. table 19-23. list of can module interrupt sources interrupt status bit interrupt enable bit no. name register name register interrupt request signal interrupt source description 1cints0 c0ints cie0 note c0ie intc0trx can module interrupt status bit for interrupt event 'message frame successfully transmitted from message buffer m' 2cints1 c0ints cie1 note c0ie intc0rec can module interrupt status bit for interrupt event 'valid message frame reception in message buffer m' 3 cints2 c0ints cie2 c0ie can module error state interrupt status 4 cints3 c0ints cie3 c0ie can module protocol error interrupt status 5 cints4 c0ints cie4 c0ie intc0err can module arbitration loss interrupt status 6 cints5 c0ints cie5 c0ie intc0wup can module wakeup from can sleep mode by can bus interrupt status bit note the ie bit (message buffer interrupt enable bit) in the c0mctrl register of the corresponding message buffer has to be set to 1 for that message buffer to participate in the interrupt generation process.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 685 19.13 diagnosis functions and special operational modes the can module provides the receive-only mode, single-shot mode, and self-test mode to support can bus diagnosis or the operation of specific can communication methods. 19.13.1 receive-only mode the ? receive-only mode ? can be used for can bus analysis nodes, which have to receive all messages without causing any interference on the can bus. for example, receive-only mode is used for automatic baud-rate detection. for automatic bit-rate detection, the bit-rate in the can module is changed until a valid reception is detected. a valid reception means that a message frame has been received in the can protocol transfer layer without occurrence of an error. a valid reception does not require acceptance of the message frame in a receive message buffer (data frame) or transmit message buffer (remote frame). the event of a valid reception is indicated by setting the valid bit in the c0ctrl register (1). figure 19-40. can module terminal connection in receive-only mode can macro rx tx stuck '1' can0tx can0rx in the operational mode ? receive-only mode ? , no message frames can be sent from the can module to the can bus. transmit requests issued for message buffers defined as transmit message buffers are ignored. in ? receive-only mode ? , the can0tx output terminal of the can module is stuck at the recessive level. therefore, no active error flag can be sent from the can module when a can bus error is detected while receiving a message frame. since no transmission can be issued from the can module, the transmit error counter tec is never updated. a can module in ? receive-only mode ? never enters the can protocol error state bus-off.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 686 a can module in the ? receive-only mode ? is also not able to generate a dominant bit on the can bus in the ack slot of the ack field upon a valid reception of a message frame. furthermore, in ? receive-only mode ? , no overload frames can be generated. caution if only 2 can nodes are connected to the can bus and one of the can nodes is operating in ?receive-only mode?, there is no acknowledgment on the can bus. due to the missing acknowledgment, the transmitter will send an active error flag and repeat sending the message frame. the transmitter becomes ?error passive? after sending the message frame 16 times (assuming the error counters were zero in the beginning and no other errors have occurred). when the message frame is sent for the 17th time, the transmitter generates a passive error flag, so the transmitter in ?receive-only mode? gets the first ?valid? message frame and the valid bit is set (1) for the first time. 19.13.2 single-shot mode in the operational mode ? single-shot mode ? automatic re-transmission as defined in the can protocol is switched off. (according to the can protocol, a message frame transmission that has been aborted by either ? arbitration loss ? or ? error occurrence ? has to be repeated without any interaction by software.) the ? single-shot mode ? disables the re-transmission of an aborted message frame transmission according the setting of the al bit in c0ctrl register. when the al bit is cleared (0) re-transmission upon ? arbitration loss ? and upon ? error occurrence ? is disabled. if the al bit is set (1), re-transmission upon ? error occurrence ? is disabled, but re- transmission upon ? arbitration loss ? is enabled. as a consequence, the trq flag in a message buffer defined as a transmit message buffer may be cleared (0) by the following events. ? successful transmission of the message frame ? ? arbitration loss ? while sending the arbitration field of the message frame ? ? error occurrence ? while sending the message frame the events ? arbitration loss ? and ? error occurrence ? have to be distinguished by checking the lec2 to lec0 bits in the c0ints register. upon a successful transmission, the ? transmit successful ? interrupt status bit cints0 in the c0ints register is set (1). in addition, an interrupt request signal will be generated, when it has been enabled by setting the cie0 enable bit in the c0ie register (1). the ? single-shot mode ? can be used when emulating time-triggered communication methods (ex. ttcan level 1).
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 687 19.13.3 self-test mode in the ? self-test mode ? , message frame transmission and message frame reception can be tested without connecting the can node to the can bus or without affecting the can bus. in the operational mode ? self-test mode ? , the can module of a can i/f channel is completely disconnected from the can bus, but internal switches connect the transmit path with the receive path. the can0tx pin of the can i/f channel is stuck to a ? recessive ? can bus level. figure 19-41. can module terminal connection in self-test mode can macro rx tx stuck '1' can0tx can0rx
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 688 19.14 time stamp function can is an asynchronous, serial protocol. all nodes connected to the bus have a local, autonomous clock. as a consequence, the clocks of the nodes have no relation (i.e., the clocks are asynchronous and may even have different frequencies). but in some applications, a common time base over the network (global time base) is needed. in order to build up a global time base, a time stamp (ts) function is used. the essential mechanism of a ts function is the capture of timer values triggered by signals on the can bus. 19.14.1 basic time stamp function the can module supports the capturing of successfully received data frames upon occurrence of an event (basic time stamp function). for the basic ts, a 16-bit timer with a capture and compare register in a microcontroller system is used. in this case, the 16-bit capture timer unit captures the timer value according to a trigger signal (tsout) provided by the can module. the cpu can retrieve the point in time when the event happened by reading the captured value. in other words, the cpu can get the time stamp of a message received from the can bus. tsout is generated by two source events selected by the tssel bit in the c0ts register. ? sof event (start of frame): tssel = 0 ? eof event (last bit of end of frame): tssel = 1 the tsout signal has to be enabled by setting the tsen bit in the c0ts register. figure 19-42. timing diagram of capture output signal tsout t tsout sof sof sof sof tsout toggles its level upon occurrence of the selected source event (in the timing diagram in figure 19-42, the sof event is selected) during data frame reception. as a consequence, the function ? capture on falling or rising edge ? has to be selected in the 16-bit timer in the microcontroller system. the time stamp function is controlled by the tslock bit in the c0ts register. when tslock is cleared (0) upon the selected source event, a tsout pulse is generated. if tslock is set (1) upon the selected source event, a tsout pulse is generated, but as soon as a data frame has been successfully received in message buffer 0, the tsen signal is automatically cleared (0) to prevent further time stamp pulses. thus, the toggle of tsout is suppressed, and the time stamp value references a data frame in message buffer 0. the cpu does not need to react quickly as the value will not be overwritten until tsen is set (1) again. the basic ts function cannot be used while the can module operates in ? normal operating mode with automatic block transmission ? .
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 689 19.15 rules for setting baud rate always make sure that the settings are within the range of limit values for ensuring correct operation of the can controller as follows. (a) 5 tq spt (sampling point) 17 tq spt = tseg1 + 1 (b) 8 tq dbt (data bit time) 25 tq dbt = tseg1 + tseg2 + 1tq = tseg2 + spt (c) 1tq sjw (synchronization jump width) 4tq sjw dbt ? spt (d) 4 tseg1 16 [3 setting value of tseg1[3:0] 15] (e) 1 tseg2 8 [0 setting value of tseg2[2:0]] 7] remark tq = 1/f tq (f tq : can protocol layer basic system clock) tseg1[3:0] (bits 3 to 0 of the can0 bit rate register (c0btr)) tseg2[2:0] (bits 10 to 8 of the can0 bit rate register (c0btr)) (1) example of can baud rate setting the following is an example of how correct settings for the c0brp register and c0btr register can be calculated. conditions from can bus: <1> can module system clock (f canmod ): 8 mhz <2> can bus baud rate: 500 kbps <3> sample point: 80% or more <4> synchronization jump width: 3 tq first, calculate the ratio between the can module system clock frequency and the can bus baud rate frequency as shown below. f canmod /can bus band rate = 8 mhz/500 khz = 16 set a number between 1 and 256 to the c0brp register ? s tqprs7 to tqprs0 bits as the setting for the prescaler (can protocol layer basic system clock: f tq ), then set a value between 8 and 25 to the c0sync register ? s dtbr4 to dbtr0 bits as the data bit time. since it is assumed that the sjw (synchronization jump width) value is 3, the maximum setting for spt (sample point) is the ? data bit time setting minus 3 ? or less and 17 or less. (spt dbt ? 3 and spt 17)
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 690 given the above limit values, the following two settings are possible. prescaler dbt spt(max.) tseg1 tseg2 calculated spt 1 16 13 12 3 13/16 = 81% 2 8 5 4 3 5/8 = 62.5% 8 mhz/500 khz = 16 = 1 16 <1> = 2 8<2> = 4 4<3> = 8 2<4> = 16 1<5> the settings that can actually be made for the device are in the range from <1> to <2> above (the section enclosed in broken lines). among these options in the range from <1> to <2> above, option <1> is the ideal setting when actually setting the register. (i) prescaler (can protocol layer basic system clock: f tq ) setting f tq is calculated as shown below. ? f tq = f canmod /(a + 1) : [0 a 255] value a is set using bits 7 to 0 (tqprs[7:0]) of the c0brp register. f tq = 8 mhz/1 = 8 mhz/(0 + 1) thus a = 5 therefore, c0brp register = 0005h
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 691 (ii) tseg1 setting tseg1 is calculated as shown below. ? tseg1 = (a + 1)tq : [1 a 15] value a is set using bits 3 to 0 (tseg1[3:0]) of the c0btr register. tseg1 = 12tq = (a + 1)tq thus a = 11 therefore, the c0btr register ? s bits 3 to 0 = 1011b (iii) tseg2 setting tseg2 is calculated as shown below. ? tseg2 = (a + 1)tq : [0 a 7] value a is set using bits 10 to 8 (tseg2[2:0]) of the c0btr register. tseg2 = 3tq = (a + 1)tq thus a = 11 therefore, the c0btr register ? s bits 10 to 8 = 010b (iv) sjw (synchronization jump width) setting sjw is calculated as shown below. ? sjw = (a + 1)tq : [0 a 3] value a is set using bits13 and 12 (sjw1, sjw0) of the c0btr register. sjw= 3tq = (a + 1)tq thus a = 2 therefore, the c0btr register ? s bits 13 and 12 = 10b the c0btr register settings based on these results are shown in figure 19-43 below.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 692 figure 19-43. c0btr register settings 15 14 13 12 11 10 9 8 c0btr 0 0 0 0 tseg13 tseg12 tseg11 tseg10 setting00001011 76543210 0 0 sjw1 sjw0 0 tseg22 tseg21 tseg20 setting10100010
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 693 19.16 operation of can controller figure 19-44. initialization start set cgmcs register set gom = 1 set c0brp register c0btr register set c0ie register set c0mask register initialize message buffers set opmode end remark opmode: normal operating mode, normal operating mode with abt, receive-only mode, single-shot mode, self-test mode.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 694 figure 19-45. reinitialization start set c0brp register c0btr register set c0ie register set c0mask register set opmode end clear opmode init mode no yes set ccerc yes no c0erc and c0info clear? redefine message buffers caution before a message buffer is initialized, the rdy bit must be cleared. remark opmode: normal operating mode, normal operating mode with abt, receive-only mode, single-shot mode, self-test mode.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 695 figure 19-46. message buffer initialization start set c0mconfm set c0midhm, c0midlm set c0mdlcm clear c0mdatam set c0mctrlm end transmit message buffer? yes no
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 696 figure 19-47. message buffer redefinition start clear rdy = 1 set message buffers set rdy = 1 end rdy = 0? yes no rdy = 1? yes no
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 697 figure 19-48. transmit preparation (normal mode) start write data set trq = 1 end trq = 0? yes no clear rdy = 1 set rdy = 1 caution the trq bit should be set after the rdy bit is set. the trq bit and rdy bit should not be set at the same time.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 698 figure 19-49. transmit preparation (abt mode) start write data set abttrg = 1 end clear rdy = 1 set rdy = 1
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 699 figure 19-50. transmission via interrupt (c0lopt) start write data set trq = 1 end clear rdy = 1 set rdy = 1 transmit interrupt clear cints0 = 1 read c0lopt caution the trq bit should be set after the rdy bit is set. the trq bit and rdy bit should not be set at the same time.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 700 figure 19-51. transmission via interrupt (c0tgpt) start write data set trq = 1 end clear rdy = 1 set rdy = 1 clear cints0 = 1 read c0tgpt tovf = 1? clear tovf = 1 read c0tgpt thpm = 1? yes no yes no transmit interrupt caution the trq bit should be set after the rdy bit is set. the trq bit and rdy bit should not be set at the same time.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 701 figure 19-52. transmit software polling start write data set trq = 1 end clear rdy = 1 set rdy = 1 clear cints0 = 1 read c0tgpt cints0 = 1? tovf = 1? clear tovf = 1 read c0tgpt thpm = 1? yes no yes no yes no caution the trq bit should be set after the rdy bit is set. the trq bit and rdy bit should not be set at the same time.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 702 figure 19-53. transmission request abort process (normal mode) start end clear trq = 1 check c0tgpt yes no c0tgpt points to aborted message buffer? transmission successful transmit abort request was successful note note the user must decide when to check.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 703 figure 19-54. transmission request abort process (abt mode) start end abttrg = 0? yes no transmission abort clear abttrg = 1 start point clear? yes no set abtclr = 1
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 704 figure 19-55. reception via interrupt (c0lipt) start clear dn = 1 clear cints1 = 1 end read c0lipt read data dn = 0 and muc = 0 yes no receive interrupt note note check the muc bit and dn bit using one read access.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 705 figure 19-56. reception via interrupt (c0rgpt) start clear cints1 = 1 end read c0rgpt read data dn = 0 and muc = 0 yes no receive interrupt rovf = 1? yes no clear rovf = 1 read c0rgpt clear dn = 1 rhpm = 1? no yes note check the muc bit and dn bit using one read access. note
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 706 figure 19-57. receive software polling start clear cints1 = 1 end read c0rgpt read data dn = 0 and muc = 0 yes no rovf = 1? yes no clear rovf = 1 read c0rgpt clear dn = 1 rhpm = 1? no yes cints1 = 1? no yes note note check the muc bit and dn bit using one read access.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 707 figure 19-58. setting can sleep/stop mode start end set psmode0 = 1 yes no psmode0 = 1? sleep mode stop mode yes psmode1 = 1? no set psmode1 = 1 caution when accessing a message buffer after requesting shift to sleep mode, confirm that the mbon bit is set. if mbon is cleared, the read value is undefined.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 708 figure 19-59. clear can sleep/stop mode start end clear psmode1 = 1 stop mode sleep mode bus active psmode0 = 0 clear cints5 = 1 clear psmode0 = 1
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 709 figure 19-60. bus-off recovery start end clear opmode dn = 0 and muc = 0 yes no yes no boff = 1? no yes matched clear bus-off condition set opmode set ccerc = 1 bus off clear? no yes init mode? set opmode
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 710 figure 19-61. shutdown process (normal shutdown) start clear gom = 0 shutdown successful gom = 0, efsd = 0 end all can modules in init mode remark if the gom bit is set after shutdown, the message buffer must be reinitialized before it is shifted to any operation mode.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 711 figure 19-62. shutdown process (forcible shutdown) start set efsd = 1 clear gom = 0 shutdown successful gom = 0, efsd = 0 end can module is opmode must be a continuous write gom = 0? yes no cautions 1. do not read- or write-access any register between setting the efsd bit and clearing the gom bit. 2. if the gom bit is not cleared after clearing the gom bit in the shutdown sequence, set the efsd bit again. otherwise, interrupts will be set to disabled between when the efsd bit is set and the gom bit is cleared. remark opmode: normal operating mode, normal operating mode with abt, receive-only mode, single-shot mode, self-test mode.
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 712 figure 19-63. error handling start error interrupt cints2 = 1? cints3 = 1? check protocol error state check error state cints4 = 1? next operation clear cints2 = 1 clear cints3 = 1 clear cints4 = 1 end yes no no yes no yes
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 713 figure 19-64. setting cpu standby (from can sleep mode) start end set psmode0 = 1 dn = 0 and muc = 0 yes no yes no dn = 0 and muc = 0 yes set cpu standby mode no cints5 = 1? clear cints5 yes no sleep mode entered psmode0 = 1? mbon = 0?
chapter 19 can controller preliminary user ? s manual u16541ej1v0um 714 figure 19-65. setting cpu standby (from can stop mode) start end set psmode0 = 1 psmode0 = 1? yes no yes mbon = 0? yes set cpu standby mode clear cints5 no set psmode1 = 1 yes psmode1 = 1? no sleep mode entered yes stop mode entered
preliminary user?s manual u16541ej1v0um 715 chapter 20 dma functions (dma controller) the v850es/sg2 include a direct memory access (dma) controller (dmac) that executes and controls dma transfer. the dmac controls data transfer between memory and i/o, between memories, or between i/os based on dma requests issued by the on-chip peripheral i/o (serial interface, real-time pulse unit, and a/d converter), interrupts from external input pins, or software triggers (memory refers to internal ram or external memory). 20.1 features ? 4 independent dma channels ? transfer unit: 8/16 bits ? maximum transfer count: 65,536 (2 16 ) ? transfer type: two-cycle transfer ? transfer mode: single transfer mode ? transfer requests ? request by interrupts from on-chip peripheral i/o (serial interface, timer/counter, a/d converter) or interrupts from external input pin ? requests by software trigger ? transfer objects ? internal ram ? peripheral i/o ? peripheral i/o ? peripheral i/o ? internal ram ? external memory ? external memory ? peripheral i/o ? external memory ? external memory
chapter 20 dma functions (dma controller) preliminary user?s manual u16541ej1v0um 716 20.2 configuration cpu internal ram on-chip peripheral i/o on-chip peripheral i/o bus internal bus data control address control count control channel control dmac v850es/sg2 bus interface external bus external ram external rom external i/o dma source address register n (dsanh/dsanl) dma transfer count register n (dbcn) dma channel control register n (dchcn) dma destination address register n (ddanh/ddanl) dma addressing control register n (dadcn) dma trigger factor register n (dtfrn) remark n = 0 to 3
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 717 20.3 control registers 20.3.1 dma source address registers 0 to 3 (dsa0 to dsa3) the dsa0 to dsa3 registers set the dma source addresses (28 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, dsanh and dsanl. (1) dma source address registers 0h to 3h (dsa0h to dsa3h) the dsa0h to dsa3h registers can be read or written in 16-bit units. dsanh (n = 0 to 3) external memory, on-chip peripheral i/o internal ram ir 0 1 specification of dma source address sets the dma source addresses (a25 to a16). during dma transfer, it stores the next dma transfer source address. sa25 to sa16 after reset: undefined r/w address: dsa0h fffff082h, dsa1h fffff08ah, dsa2h fffff092h, dsa3h fffff09ah sa23 sa22 sa21 sa20 sa19 sa18 sa17 sa16 ir 0 0 0 0 0 sa25 sa24 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 (2) dma source address registers 0l to 3l (dsa0l to dsa3l) the dsa0l to dsa3l registers can be read or written in 16-bit units. dsanl (n = 0 to 3) after reset: undefined r/w address: dsa0l fffff080h, dsa1l fffff088h, dsa2l fffff090h, dsa3l fffff098h sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 sa15 sa14 sa13 sa12 sa11 sa10 sa9 sa8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 sets the dma source addresses (a15 to a0). during dma transfer, it stores the next dma transfer source address. sa15 to sa0 caution the dsanh and dsanl registers cannot be changed during transfer. set the init bit of the dchcn register to 1 to initialize these registers before changing them.
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 718 20.3.2 dma destination address registers 0 to 3 (dda0 to dda3) the dda0 to dda3 registers set the dma destination address (28 bits each) for dma channel n (n = 0 to 3). these registers are divided into two 16-bit registers, ddanh and ddanl. (1) dma destination address registers 0h to 3h (dda0h to dda3h) the dda0h to dda3h registers can be read or written in 16-bit units. ddanh (n = 0 to 3) external memory, on-chip peripheral i/o internal ram ir 0 1 dma destination address specification after reset: undefined r/w address: dda0h fffff086h, dda1h fffff08eh, dda2h fffff096h, dda3h fffff09eh da23 da22 da21 da20 da19 da18 da17 da16 ir 0 0 0 0 0 da25 da24 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 sets the dma destination addresses (a25 to a16). during dma transfer, it stores the next dma transfer destination address. da25 to da16 (2) dma destination address registers 0l to 3l (dda0l to dda3l) the dda0l to dda3l registers can be read or written in 16-bit units. ddanl (n = 0 to 3) after reset: undefined r/w address: dda0l fffff084h, dda1l fffff08ch, dda2l fffff094h, dda3l fffff09ch da7 da6 da5 da4 da3 da2 da1 da0 da15 da14 da13 da12 da11 da10 da9 da8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 sets the dma destination addresses (a15 to a0). during dma transfer, it stores the next dma transfer destination address. da15 to da0 caution the ddanh and ddanl registers cannot be changed during transfer. set the init bit of the dchcn register to 1 to initialize these registers before changing them.
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 719 20.3.3 dma byte count registers 0 to 3 (dbc0 to dbc3) the dbc0 to dbc3 registers are 16-bit registers that set the byte transfer count for dma channels n (n = 0 to 3). these registers store the remaining transfer count during dma transfer. these registers can be read or written in 16-bit units. remark if the dbcn register is read during dma transfer after a terminal count has occurred without the register being overwritten, the value set immediately before the dma transfer will be read out (0000h will not be read, even if dma transfer has ended). dbcn (n = 0 to 3) byte transfer count 1 or remaining byte transfer count byte transfer count 2 or remaining byte transfer count : byte transfer count 65,536 (2 16 ) or remaining byte transfer count bc15 to bc0 0000h 0001h : ffffh byte transfer count setting or remaining byte transfer count during dma transfer after reset: undefined r/w address: dbc0 fffff0c0h, dbc1 fffff0c2h, dbc2 fffff0c4h, dbc3 fffff0c6h bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 bc15 bc14 bc13 bc12 bc11 bc10 bc9 bc8 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 caution the dbcn register cannot be changed during transfer. set the init bit of the dchcn register to 1 to initialize this register before changing it.
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 720 20.3.4 dma addressing control registers 0 to 3 (dadc0 to dadc3) the dadc0 to dadc3 registers are 16-bit registers that control the dma transfer mode for dma channel n (n = 0 to 3). these registers cannot be accessed during dma operation. these registers can be read or written in 16-bit units. dadcn (n = 0 to 3) 8 bits 16 bits ds0 0 1 setting of transfer data size for dma transfer increment decrement fixed setting prohibited sad1 0 0 1 1 sad0 0 1 0 1 setting of count direction of the source address for dma channel n increment decrement fixed setting prohibited dad1 0 0 1 1 dad0 0 1 0 1 setting of count direction of the destination address for dma channel n after reset: 0000h r/w address: dadc0 fffff0d0h, dadc1 fffff0d2h, dadc2 fffff0d4h, dadc3 fffff0d6h sad1 sad0 dad1 dad0 0 0 0 0 0ds000 00 0 0 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 721 20.3.5 dma channel control registers 0 to 3 (dchc0 to dchc3) the dchc0 to dchc3 registers are 8-bit registers that control the dma transfer operating mode for dma channel n (n = 0 to 3). these registers can be read or written in 8-bit or 1-bit units. (however, bit 7 is read-only and bits 1 and 2 are write- only. if bit 1 or 2 is read, the read value is always 0.) reset input clears these registers to 00h. dchcn (n = 0 to 3) dma transfer had not ended. dma transfer had ended. it is set to 1 when dma transfer ends and cleared (to 0) when it is read. tcn 0 1 status flag indicates whether dma transfer through dma channel n has ended or not dma transfer disabled dma transfer enabled this bit is cleared to 0 when dma transfer ends. it is also cleared to 0 when dma transfer is forcibly terminated by means of nmi input. enn 0 1 setting of whether dma transfer through dma channel n is to be enabled or disabled if this bit is set to 1 in the dma transfer enable state (tcn bit = 0, enn bit = 1), dma transfer is started. stgn after reset: 00h r/w address: dchc0 fffff0e0h, dchc1 fffff0e2h, dchc2 fffff0e4h, dchc3 fffff0e6h tcn note 1 0 0 0 0 initn note 2 stgn enn note 2 <0> <1> <2> 3 4 5 6 <7> set the init bit to 1 when the enn bit = 0. initn to change the ddanh, ddanl, dsanh, dsanl, or dbcn register before the number of the transfers set for dbcn is complete, set this bit to 1 to initialize dma. notes 1. the tcn bit is read-only. 2. the initn and stgn bits are write-only. cautions 1. before generating a dma transfer request by software, make sure that the tcn bit is set to 1 and then clear the tcn bit to 0. 2. if the init bit setting and the dma transfer of another channel conflict, initialization may not performed.
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 722 20.3.6 dma trigger factor registers 0 to 3 (dtfr0 to dtfr3) the dtfr0 to dtfr3 registers are 8-bit registers that control the dma transfer start trigger through interrupt request signals from on-chip peripheral i/o. the interrupt request signals set with these registers serve as dma transfer start factors. these registers can be read or written in 8-bit units. however, only bit 7 (dfn) can be read or written in 1-bit units. reset input clears these registers to 00h. dtfrn (n = 0 to 3) no dma transfer request dma transfer request dfn note 0 1 setting of interrupt source that serves as the dma start factor after reset: 00h r/w address: dtfr0 fffff810h, dtfr1 fffff812h, dtfr2 fffff814h, dtfr3 fffff816h dfn 0 ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 0 1 2 3 4 5 6 <7> note the dfn bit is a write-only bit. write 0 to this bit to clear a dma transfer request if the interrupt that is specified as the cause of starting dma transfer while dma transfer is disabled. cautions 1. be sure to stop dma operation before making changes to dtfrn register settings. 2. an interrupt request input in a standby mode (idle or software stop mode) cannot be used as a dma transfer start factor. 3. for details of ifcn5 to ifcn0 bits, see table 20-1 dma start factor. remark n = 0 to 3
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 723 table 20-1. dma start factor (1/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 0 0 0 0 0 0 dma request by interrupt disabled 000001intp0 000010intp1 000011intp2 000100intp3 000101intp4 000110intp5 000111intp6 001000intp7 001001inttq0ov 0 0 1 0 1 0 inttq0cc0 0 0 1 0 1 1 inttq0cc1 0 0 1 1 0 0 inttq0cc2 0 0 1 1 0 1 inttq0cc3 001110inttp0ov 0 0 1 1 1 1 inttp0cc0 0 1 0 0 0 0 inttp0cc1 010001inttp1ov 0 1 0 0 1 0 inttp1cc0 0 1 0 0 1 1 inttp1cc1 010100inttp2ov 0 1 0 1 0 1 inttp2cc0 0 1 0 1 1 0 inttp2cc1 0 1 0 1 1 1 inttp3cc0 0 1 1 0 0 0 inttp3cc1 0 1 1 0 0 1 inttp4cc0 0 1 1 0 1 0 inttp4cc1 0 1 1 0 1 1 inttp5cc0 0 1 1 1 0 0 inttp5cc1 011101inttm0eq0 0 1 1 1 1 0 intcb0r/intiic1 note 0 1 1 1 1 1 intcb0t 1 0 0 0 0 0 intcb1r 1 0 0 0 0 1 intcb1t 1 0 0 0 1 0 intcb2r 1 0 0 0 1 1 intcb2t 1 0 0 1 0 0 intcb3r 1 0 0 1 0 1 intcb3t 100110intua0r/intcb4r 1 0 0 1 1 1 intua0t/intcb4t 1 0 1 0 0 0 intua1r/intiic2 note 101001intua1t 1 0 1 0 1 0 intua2r/intiic0 note note i 2 c bus version (y version) only remark n = 0 to 3
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 724 table 20-1. dma start factor (2/2) ifcn5 ifcn4 ifcn3 ifcn2 ifcn1 ifcn0 interrupt source 101011intua2t 101100intad 101101intkr 101110interr note 101111intsta note 110000intie1 note other than above setting prohibited note iebus controller version only remark n = 0 to 3
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 725 20.4 dma bus states 20.4.1 types of bus states the dmac bus states consist of the following 10 states. (1) ti state the ti state is an idle state, during which no access request is issued. the dma request signals are sampled at the rising edge of the clkout signal. (2) t0 state dma transfer ready state (state in which a dma transfer request has been issued and the bus mastership is acquired for the first dma transfer). (3) t1r state the bus enters the t1r state at the beginning of a read operation in the two-cycle transfer mode. address driving starts. after entering the t1r state, the bus enters the t2r state. (4) t1ri state the t1ri state is a state in which the bus waits for the acknowledge signal corresponding to an external memory read request. after entering the last t1ri state, the bus invariably enters the t2r state. (5) t2r state the t2r state corresponds to the last state of a read operation in the two-cycle transfer mode, or to a wait state. in the last t2r state, read data is sampled. after entering the last t2r state, the bus enters the t1w state. (6) t2ri state state in which the bus is ready for dma transfer to on-chip peripheral i/o or internal ram (state in which the bus mastership is acquired for dma transfer to on-chip peripheral i/o or internal ram). after entering the last t2ri state, the bus invariably enters the t1w state. (7) t1w state the bus enters the t1w state at the beginning of a write operation in the two-cycle transfer mode. address driving starts. after entering the t1w state, the bus enters the t2w state. (8) t1wi state state in which the bus waits for the acknowledge signal corresponding to an external memory write request. after entering the last t1wi state, the bus invariably enters the t2w state. (9) t2w state the t2w state corresponds to the last state of a write operation in the two-cycle transfer mode, or to a wait state. in the last t2w state, the write strobe signal is made inactive. (10) te state the te state corresponds to dma transfer completion. the dmac generates the internal dma transfer completion signal and various internal signals are initialized. after entering the te state, the bus invariably enters the ti state.
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 726 20.4.2 dmac bus cycle state transition each time the processing for a dma transfer is completed, the bus mastership is released. figure 20-1. dmac bus cycle state transition ti t0 t1r t1ri t2r t1w t2w te ti t2ri t1wi
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 727 20.5 transfer mode 20.5.1 single transfer mode in single transfer mode, the dmac releases the bus at each byte/halfword transfer. if there is a subsequent dma transfer request, transfer is performed again once. this operation continues until a terminal count occurs. when the dmac has released the bus, if another higher priority dma transfer request is issued, the higher priority dma request always takes precedence. 20.6 transfer types 20.6.1 two-cycle transfer in two-cycle transfer, data transfer is performed in two cycles, a read cycle (source to dmac) and a write cycle (dmac to destination). in the first cycle, the source address is output and reading is performed from the source to the dmac. in the second cycle, the destination address is output and writing is performed from the dmac to the destination.
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 728 20.7 transfer object 20.7.1 transfer object table 20-2 shows the relationship with transfer object ( : transfer enabled, : transfer disabled). table 20-2. relationship with transfer object destination internal rom on-chip peripheral i/o internal ram external memory on-chip peripheral i/o ?? internal ram ? external memory ?? source internal rom caution the operation is not guaranteed for combinations of transfer destination and source marked with ? ? in table 20-2. remark during two-cycle 16-bit transfer, if the data bus width of the transfer source and that of the transfer destination are different, the operation becomes as follows. in the case of transfer from a 16-bit bus to an 8-bit bus a 16-bit read cycle is generated and then an 8-bit write cycle is generated twice. in the case of transfer from an 8-bit bus to a 16-bit bus an 8-bit read cycle is generated twice and then a 16-bit write cycle is generated. 20.7.2 external bus cycles during dma transfer (two-cycle transfer) the external bus cycles during dma transfer (two-cycle transfer) are shown below. table 20-3. external bus cycles during dma transfer (two-cycle transfer) transfer object external bus cycle on-chip peripheral i/o, internal ram none note ? external i/o yes sram cycle external memory yes memory access cycle note other external cycles such as a cpu-based bus cycle can be started.
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 729 20.8 dma channel priorities the dma channel priorities are fixed as follows. dma channel 0 > dma channel 1 > dma channel 2 > dma channel 3 these priorities are valid in the ti state only. in the block transfer mode, the channel used for transfer is never switched. in the single-step transfer mode, if a higher priority dma transfer request is issued while the bus is released (in the ti state), the higher priority dma transfer request is acknowledged. 20.9 dma transfer start factors there are two types of dma transfer start factors, as shown below. (1) request from software if the stgn, enn, and tcn bits of the dchcn register are set as follows, dma transfer starts (n = 0 to 3). ? stgn bit = 1 ? enn bit = 1 ? tcn bit = 0 (2) request from on-chip peripheral i/o if, when the enn and tcn bits of the dchcn register are set as shown below, an interrupt request is issued from the on-chip peripheral i/o that is set in the dtfrn register, dma transfer starts (n = 0 to 3). ? enn bit = 1 ? tcn bit = 0 20.10 dma transfer end 20.10.1 dma transfer end interrupt when dma transfer ends and the tcn bit of the dchcn register is set to 1, a dma transfer end interrupt (intdman) is issued to the interrupt controller (intc) (n = 0 to 3). 20.10.2 terminal count output upon dma transfer end the terminal count signal becomes active for one clock during the last dma transfer cycle.
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 730 20.11 precautions (1) memory boundary the transfer operation is not guaranteed if the source or the destination address exceeds the area of dma objects (external memory, internal ram, or on-chip peripheral i/o) during dma transfer. (2) transfer of misaligned data dma transfer of 16-bit bus width misaligned data is not supported. (3) times related to dma transfer the overhead before and after dma transfer and the minimum execution clock for dma transfer are shown below. ? internal ram access: 2 clocks note that for external memory access, the time depends on the type of external memory connected. (4) bus arbitration for cpu the cpu can access external memory, on-chip peripheral i/o, and internal ram not undergoing dma transfer. while data transfer among external memories or to and from i/o is being performed, the cpu can access internal ram. (5) notes on initn bit (n = 0 to 3) of dma channel control registers 0 to 3 (dchc0 to dchc3) when a channel executing dma transfer is to be initialized, the channel may not be initialized even if the initn bit is set to 1. to accurately initialize the channel, execute either of the following two procedures. (a) to temporarily stop transfer of all dma channels [procedure] <1> disable interrupts (di status). <2> read the enn bit of the dchcn register of the dma channels other than the one to be forcibly stopped, and transfer the value of that bit to a general-purpose register. <3> clear the enn bit of the dma channels being used (including the channel to be forcibly stopped). execute the instruction that clears the enn bit twice if the channel is the last dma channel. if data is to be transferred from or to the internal ram at this time, execute the instruction three times. for example, execute the following instructions when channels 0, 1, and 2 are being used. ? clear e00 bit of dchc0 register (to 0) ? clear e11 bit of dchc1 register (to 0) ? clear e22 bit of dchc2 register (to 0) ? clear e22 bit of dchc2 register (to 0) again <4> set the initn bit of the channel to be forcibly stopped. <5> if both the tcn bit and enn bit of the channels not to be stopped forcibly are 1 (if the result of anding is 1) as a result of step <2> above, clear the enn bit that has been saved (to 0). <6> write the enn bit to the dchcn register after the operation in step <5> above. <7> enable interrupts (ei status). caution be sure to perform step <5> above to prevent the enn bit of the channels that have been completed normally in steps <2> or <3> from being illegally set again.
chapter 20 dma functions (dma controller) preliminary user ? s manual u16541ej1v0um 731 (b) repeatedly setting initn bit until dma transfer is forcibly stopped [procedure] <1> clear the enn bit of the dchcn register of the channel to be forcibly stopped to 0. <2> clear the enn bit of the above channel to 0 again. if data is transferred from or to the internal ram to or from the channel to be forcibly stopped, execute step <2> again. <3> copy the initial number of transfers of the channel to be forcibly stopped to a general-purpose register. <4> set the initn bit of the dchcn register of the channel to be forcibly stopped to 1. <5> read the value of the dma transfer count register (dbcn) of the channel to be forcibly stopped, and compare that value with the value copied in step <3> above. if the two values do not match, repeat steps <4> and <5>. cautions 1. if the dbcn register is read in step <5>, and if dma transfer is stopped due to trouble, the remaining number of transfers will be read. if dma transfer has been forcibly stopped correctly, the initial number of transfers will be read. 2. this procedure may take time in an application where dma transfer of a channel other than that to be forcibly stopped is frequently executed until the channel in question is forcibly stopped. (6) program execution of internal ram and dma transfer if the following condition is satisfied, the cpu may not operate correctly. if this happens, only the reset signal can be acknowledged. [condition] ? when dma is executed to transfer data to/from the internal ram therefore, take either of the following remedial measures. [remedy] ? to execute dma transfer to transfer data to/from the internal ram, do not execute the bit manipulation instructions (set1, clr1, not1) located on the internal ram, and do not execute data access instruction that accesses a misaligned address. ? when executing the bit manipulation instructions (set1, clr1, not1) located on the internal ram or data access instruction that accesses a misaligned address, do not execute dma transfer to transfer data to/from the internal ram. (7) notes on tcn bit (n = 0 to 3) of dma channel control registers 0 to 3 (dchc0 to dchc3) the tcn bit is not automatically cleared even if it is read at the specified timing. this can be avoided by the following two methods. (a) polling tcn bit to wait for completion of dma transfer after confirming that the tcn bit has been set, read the tcn bit three times. (b) reading tcn bit by interrupt servicing routine read the tcn bit three times. 20.11.1 interrupt factors dma transfer is interrupted if a bus hold is issued. if the factor (bus hold) interrupting dma transfer disappears, dma transfer promptly restarts.
preliminary user?s manual u16541ej1v0um 732 chapter 21 crc function 21.1 functions ? crc operation circuit for the detection of data block errors ? generation of 16-bit crc code using a crc-ccitt (x 16 + x 12 + x 5 + 1) generating function for blocks of data of any length in 8-bit units ? crc code is set to the crc data register each time 1-byte data is transferred to the crcin register, after the initial value is set to the crcd register. 21.2 configuration the crc function includes the following hardware. table 21-1. crc configuration item configuration control registers crc input register (crcin) crc data register (crcd) figure 21-1. block diagram of crc register crc data register (crcd) (16 bits) crc input register (crcin) (8 bits) internal bus internal bus crc code generator a0-b0 a1-b1 a2-b2 a3-b3 a4-b4 a5-b5 a6-b6 a7-b7 a8 a9 a10 a11 a12 a13 a14 a15 r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0
chapter 21 crc function preliminary user ? s manual u16541ej1v0um 733 21.3 control registers (1) crc input register (crcin) the crcin register is an 8-bit register for data setting. this register can be read or written in 8-bit units. reset input clears this register to 00h. crcin 654321 after reset: 00h r/w address: fffff310h 7 0 (2) crc data register (crcd) the crcd register is a 16-bit register that stores crc-ccitt operation results. this register can be read or written in 16-bit units. reset input clears this register to 0000h. cautions 1. following write to the crcd register, do not write the crc calculator output to the crcd register during the first write access to the crcin register. (do not load the operation result.) 2. through the operation of the crcin register, the crc operation results are saved to the crcd register. therefore, to write to the crcd register via the internal bus and then read the written value, read the crcd register before writing to crcin. crcd 12 10 8 6 4 2 after reset: 0000h r/w address: fffff312h 14 0 13 11 9 7 5 3 15 1
chapter 21 crc function preliminary user ? s manual u16541ej1v0um 734 21.4 operation 21.4.1 crc operation circuit operation example figure 21-2. crc operation circuit operation example (lsb first) (1) setting of crcin = (01) 16 1st machine cycle 2nd machine cycle (1189) 16 b15 b0 b0 b7 crc code is saved (2) crcd register read the code when (01) 16 is send lsb first is (1000 0000). therefore, the crc code with generating function x 16 + x 12 + x 5 + 1 becomes the remainder when (1000 0000) x 16 is divided with (1 0001 0000 0010 0001) using the modulo-2 operation formula. the modulo-2 operation is performed based on the following formula. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 ? 1 = 1 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb lsb msb msb therefore, crc sign becomes . since lsb first is used, this corresponds to (1189) 16 in hexadecimal notation. 1001 9811 0001 1000 1000
chapter 21 crc function preliminary user ? s manual u16541ej1v0um 735 21.4.2 operation circuit configuration the crc operation principle is division, but crc code can be generated by hardware using a shift register and exclusive or (ex-or). figure 21-3. operation circuit configuration (crc data register) 15 14 13 12 11 10 9 8 7 6 5 4 3210 data input shift register ex-or using the denotation of data a15 to a0 of the crcd register, data b7 to b0 of the crcin register, and crc operation results r15 to r0, the crc code generation circuit is configured as follows. r15 = a7 b7 a3 b3 r14 = a6 b6 a2 b2 r13 = a5 b5 a1 b1 r12 = a4 b4 a0 b0 r11 = a3 b3 r10 = a7 b7 a3 b3 a2 b2 r9 = a6 b6 a2 b2 a1 b1 r8 = a5 b5 a1 b1 a0 b0 r7 = a4 b4 a0 b0 a15 r6 = a3 b3 a14 r5 = a2 b2 a13 r4 = a1 b1 a12 r3 = a7 b7 a3 b3 a0 b0 a11 r2 = a6 b6 a2 b2 a10 r1 = a5 b5 a1 b1 a9 r0 = a4 b4 a0 b0 a8
chapter 21 crc function preliminary user ? s manual u16541ej1v0um 736 21.4.3 usage method the usage method of the crc operation circuit is described below. figure 21-4. crc operation flow start write of 0000h to crcd register crcd register read crcin register write yes no input data exists? end [basic usage method] <1> write 0000h to the crcd register. <2> write the required quantity of data to the crcin register. <3> read the crcd register.
chapter 21 crc function preliminary user ? s manual u16541ej1v0um 737 communication errors can easily be detected if the crc code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes. the following is an illustration using the transmission of 12345678h (0001 0010 0011 0100 0101 0110 0111 1000b) lsb first as an example. figure 21-5. crc transmission example 78 transmit/receive data (12345678h) crc code (08fh) 56 34 12 f6 08 setting procedure on transmitting side <1> write the initial value 0000h to the crcd register. <2> write the 1 byte of data to be transmitted first to the transmit buffer register. (at this time, also write the same data to the crcin register.) <3> when transmitting several bytes of data, write the same data to the crcin register each time transmit data is written to the transmit buffer register. <4> after all the data has been transmitted, write the contents of the crcd register (crc code) to the transmit buffer register and transmit them. (since this is lsb first, transmit the data starting from the lower bytes, then the higher bytes.) setting procedure on receiving side <1> write the initial value 0000h to the crcd register. <2> when the reception of the first 1 byte of data has been completed, write that receive data to the crcin register. <3> if receiving several bytes of data, write the receive data to the crcin register upon every transmission completion. (in the case of normal reception, when all the receive data has been written to the crcin register, the contents of the crcd register on the receiving side and the contents of the crcd register on the transmitting side are the same.) <4> next, the crc code is transmitted from the transmitting side, so write this data to the crcin register similarly to receive data. (when reception of all the data, including the crc code, has been completed, reception was normal if the contents of the crcd register are 0000h.) <5> if the contents of the crcd register are other than 0000h, this indicates a communication error, so transmit a resend request to the transmitting side.
preliminary user?s manual u16541ej1v0um 738 chapter 22 interrupt/exception processing function the v850es/sg2 is provided with a dedicated interrupt controller (intc) for interrupt servicing and can process a total of 54 interrupt requests. an interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. the v850es/sg2 can process interrupt request signals from the on-chip peripheral hardware and external sources. moreover, exception processing can be started by the trap instruction (software exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). 22.1 features interrupts non-maskable interrupts: 2 sources maskable interrupts: external: 8, internal: 47/51 sources (see table 1-1 ) 8 levels of programmable priorities (maskable interrupts) multiple interrupt control according to priority masks can be specified for each maskable interrupt request. noise elimination, edge detection, and valid edge specification for external interrupt request signals. exceptions software exceptions: 32 sources exception trap: 2 sources (illegal opcode exception) interrupt/exception sources are listed in table 22-1.
chapter 22 interrupt/exception processing function preliminary user?s manual u16541ej1v0um 739 table 22-1. interrupt source list (1/3) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register reset interrupt ? reset reset pin input reset input by internal source reset 0000h 00000000h undefined ? ? nmi nmi pin valid edge input pin 0010h 00000010h nextpc ? non- maskable interrupt ? intwdt2 wdt2 overflow wdt2 0020h 00000020h nextpc ? ? trap0n note trap instruction ? 004nh note 00000040h nextpc ? software exception exception ? trap1n note trap instruction ? 005nh note 00000050h nextpc ? exception trap exception ? ilgop/ dbg0 illegal opcode/ dbtrap instruction ? 0060h 00000060h nextpc ? 0 intlvi low voltage detection poclvi 0080h 00000080h nextpc lviic 1 intp0 external interrupt pin input edge detection (intp0) pin 0090h 00000090h nextpc pic0 2intp1 external interrupt pin input edge detection (intp1) pin 00a0h 000000a0h nextpc pic1 3intp2 external interrupt pin input edge detection (intp2) pin 00b0h 000000b0h nextpc pic2 4 intp3 external interrupt pin input edge detection (intp3) pin 00c0h 000000c0h nextpc pic3 5intp4 external interrupt pin input edge detection (intp4) pin 00d0h 000000d0h nextpc pic4 6 intp5 external interrupt pin input edge detection (intp5) pin 00e0h 000000e0h nextpc pic5 7intp6 external interrupt pin input edge detection (intp6) pin 00f0h 000000f0h nextpc pic6 8 intp7 external interrupt pin input edge detection (intp7) pin 0100h 00000100h nextpc pic7 9 inttq0ov tmq0 overflow tmq0 0110h 00000110h nextpc tq0ovic 10 inttq0cc0 tmq0 capture 0/compare 0 match tmq0 0120h 00000120h nextpc tq0ccic0 11 inttq0cc1 tmq0 capture 1/compare 1 match tmq0 0130h 00000130h nextpc tq0ccic1 12 inttq0cc2 tmq0 capture 2/compare 2 match tmq0 0140h 00000140h nextpc tq0ccic2 13 inttq0cc3 tmq0 capture 3/compare 3 match tmq0 0150h 00000150h nextpc tq0ccic3 14 inttp0ov tmp0 overflow tmp0 0160h 00000160h nextpc tp0ovic 15 inttp0cc0 tmp0 capture 0/compare 0 match tmp0 0170h 00000170h nextpc tp0ccic0 16 inttp0cc1 tmp0 capture 1/compare 1 match tmp0 0180h 00000180h nextpc tp0ccic1 maskable interrupt 17 inttp1ov tmp1 overflow tmp1 0190h 00000190h nextpc tp1ovic note n = 0 to fh
chapter 22 interrupt/exception processing function preliminary user?s manual u16541ej1v0um 740 table 22-1. interrupt source list (2/3) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 18 inttp1cc0 tmp1 capture 0/compare 0 match tmp1 01a0h 000001ah nextpc tp1ccic0 19 inttp1cc1 tmp1 capture 1/compare 1 match tmp1 01b0h 000001b0h nextpc tp1ccic1 20 inttp2ov tmp2 overflow tmp2 01c0h 000001c0h nextpc tp2ovic 21 inttp2cc0 tmp2 capture 0/compare 0 match tmp2 01d0h 000001d0h nextpc tp2ccic0 22 inttp2cc1 tmp2 capture 1/compare 1 match tmp2 01e0h 000001e0h nextpc tp2ccic1 23 inttp3ov tmp3 overflow tmp3 01f0h 000001f0h nextpc tp3ovic 24 inttp3cc0 tmp3 capture 0/compare 0 match tmp3 0200h 00000200h nextpc tp3ccic0 25 inttp3cc1 tmp3 capture 1/compare 1 match tmp3 0210h 00000210h nextpc tp3ccic1 26 inttp4ov tmp4 overflow tmp4 0220h 00000220h nextpc tp4ovic 27 inttp4cc0 tmp4 capture 0/compare 0 match tmp4 0230h 00000230h nextpc tp4ccic0 28 inttp4cc1 tmp4 capture 1/compare 1 match tmp4 0240h 00000240h nextpc tp4ccic1 29 inttp5ov tmp5 overflow tmp5 0250h 00000250h nextpc tp5ovic 30 inttp5cc0 tmp5 capture 0/compare 0 match tmp5 0260h 00000260h nextpc tp5ccic0 31 inttp5cc1 tmp5 capture 1/compare 1 match tmp5 0270h 00000270h nextpc tp5ccic1 32 inttm0eq0 tmm0 compare match tmm0 0280h 00000280h nextpc tm0eqic0 33 intcb0r/ intiic1 csib0 reception completion/iic1 transfer completion csib0/ iic1 0290h 00000290h nextpc cb0ric/ iicic1 34 intcb0t csib0 consecutive transmission write enable csib0 02a0h 000002a0h nextpc cb0tic 35 intcb1r csib1 reception completion csib1 02b0h 000002b0h nextpc cb1ric 36 intcb1t csib1 consecutive transmission write enable csib1 02c0h 000002c0h nextpc cb1tic 37 intcb2r csib2 reception completion csib2 02d0h 000002d0h nextpc cb2ric 38 intcb2t csib2 consecutive transmission write enable csib2 02e0h 000002e0h nextpc cb2tic 39 intcb3r csib3 reception completion csib3 02f0h 000002f0h nextpc cb3ric 40 intcb3t csib3 consecutive transmission write enable csib3 0300h 00000300h nextpc cb3tic 41 intua0r/ intcb4r uarta0 reception completion/csib4 reception completion uarta0/ csib4 0310h 00000310h nextpc ua0ric/ cb4ric maskable interrupt 42 intua0t/ intcb4t uarta0 transmission enable/csib4 consecutive transmission write enable uarta0/ csib4 0320h 00000320h nextpc ua0tic/ cb4tic note i 2 c bus version (y version) only
chapter 22 interrupt/exception processing function preliminary user?s manual u16541ej1v0um 741 table 22-1. interrupt source list (3/3) type classification default priority name trigger generating unit exception code handler address restored pc interrupt control register 43 intua1r/ intiic2 note 1 uarta1 reception completion/ uarta1 reception error/ iic2 transfer completion uarta1/ iic2 0330h 00000330h nextpc ua1ric/ iicic2 44 intua1t uarta1 transmission enable uarta1 0340h 00000340h nextpc ua1tic 45 intua2r/ intiic0 note 1 uarta2 reception completion/ iic0 transfer completion uarta/ iic0 0350h 00000350h nextpc ua2ric/ iicic0 46 intua2t uarta2 transmission enable uarta2 0360h 00000360h nextpc ua2tic 47 intad a/d conversion completion a/d 0370h 00000370h nextpc adic 48 intdma0 dma0 transfer completion dma 0380h 00000380h nextpc dmaic0 49 intdma1 dma1 transfer completion dma 0390h 00000390h nextpc dmaic1 50 intdma2 dma2 transfer completion dma 03a0h 000003a0h nextpc dmaic2 51 intdma3 dma3 transfer completion dma 03b0h 000003b0h nextpc dmaic3 52 intkr key return interrupt kr 03c0h 000003c0h nextpc kric 53 intwti watch timer interval wt 03d0h 000003d0h nextpc wtiic 54 intwt watch timer reference time wt 03e0h 000003e0h nextpc wtic 55 intc0err note 2 / interr note 3 afcan0 error/iebus error afcan0/ iebus 03f0h 000003f0h nextpc erric0/ erric 56 intc0wup note 2 / intsta note 3 afcan0 wakeup/ iebus status afcan0/ iebus 0400h 00000400h nextpc wupic0/ stsaic 57 intc0rec note 2 / intie1 note 3 afcan0 reception/ iebus data interrupt afcan0/ iebus 0410h 00000410h nextpc recic0/ ieic1 maskable interrupt 58 intc0trx note 2 / intie2 note 3 afcan0 transmission/ iebus error/iebus status afcan0/ iebus 0420h 00000420h nextpc trxic0/ ieic2 notes 1. i 2 c bus version (y version) only 2. can controller version only 3. iebus controller version only remarks 1. default priority: the priority order when two or more maskable interrupt requests occur at the same time. the highest priority is 0. restored pc: the value of the program counter (pc) saved to eipc or fepc when interrupt servicing is started. note, however, that the restored pc when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextpc (if an interrupt is acknowledged during interrupt execution, execution stops, and then resumes after the interrupt servicing has finished). ? load instructions (sld.b, sld.bu, sld.h, sld.hu, sld.w) ? division instructions (div, divh, divu, divhu) ? prepare, dispose instructions (only if an interrupt is generated before the stack pointer is updated) nextpc: the pc value that starts the processing following interrupt/exception processing. 2. the execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (restored pc ? 4).
chapter 22 interrupt/exception processing function preliminary user?s manual u16541ej1v0um 742 22.2 non-maskable interrupts a non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (di) status. an nmi is not subject to priority control and takes precedence over all the other interrupt request signals. this product has the following two non-maskable interrupt request signals. ? nmi pin input (nmi) ? non-maskable interrupt request signal generated by overflow of watchdog timer (intwdt2) the valid edge of the nmi pin can be selected from four types: ?rising edge?, ?falling edge?, ?both edges?, and ?no edge detection?. the non-maskable interrupt request signal generated by overflow of the watchdog timer 2 (intwdt2) functions when the wdm21 and wdm20 bits of the wdtm2 register are set to ?01?. if two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority is serviced, as follows (the interrupt request signal with the lower priority is ignored). intwdt2 > nmi if a new nmi or intwdt2 request signal is issued while a nmi is being serviced, it is serviced as follows. (1) if new nmi request signal is issued while nmi is being serviced the new nmi request signal is held pending, regardless of the value of the np bit of psw in the cpu. the pending nmi request signal is acknowledged after the nmi currently under execution has been serviced (after the reti instruction has been executed). (2) if intwdt2 request signal is issued while nmi is being serviced the intwdt2 request signal is held pending if the np bit of the psw remains set (1) while the nmi is being serviced. the pending intwdt2 request signal is acknowledged after the nmi currently under execution has been serviced (after the reti instruction has been executed). if the np bit of psw is cleared (0) while the nmi is being serviced, the newly generated intwdt2 request signal is executed (the nmi servicing is stopped). caution if a non-maskable interrupt request signal is generated, the values of the pc and psw are saved to the nmi status save registers (fepc and fepsw). at this time, execution can be returned by the reti instruction only from an nmi signal. execution cannot be returned while intwdt2 signal is being serviced. therefore, reset the system after the interrupt has been serviced. figure 22-1. non-maskable interrupt request signal acknowledgment operation (1/2) (a) nmi and intwdt2 request signals generated at the same time main routine system reset nmi and intwd t2 requests (generated simultaneously) intwd t2 servicing
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 743 figure 22-1. non-maskable interrupt request signal acknowledgment operation (2/2) (b) non-maskable interrupt request signal generated during non-maskable interrupt servicing non-maskable interrupt being serviced non-maskable interrupt request signal generated during non-maskable interrupt servicing nmi intwdt2 nmi ? nmi request generated during nmi servicing ? intwdt2 request generated during nmi servicing (np = 1 retained before intwdt2 request) main routine nmi request nmi servicing (held pending) servicing of pending nmi nmi request main routine system reset nmi request nmi servicing (held pending) intwdt2 servicing intwdt2 request ? intwdt2 request generated during nmi servicing (np = 0 set before intwdt2 request) main routine system reset nmi request nmi servicing intwdt2 servicing intwdt2 request np = 0 ? intwdt2 request generated during nmi servicing (np = 0 set after intwdt2 request) main routine system reset nmi request nmi servicing intwdt2 servicing np = 0 ? intwdt2 request generated during intwdt2 servicing main routine system reset intwdt2 request intwdt2 servicing (invalid) ? nmi request generated during intwdt2 servicing intwdt2 main routine system reset intwdt2 request intwdt2 servicing (invalid) nmi request (held pending) intwdt2 request intwdt2 request
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 744 22.2.1 operation if a non-maskable interrupt request signal is generated, the cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to fepc. <2> saves the current psw to fepsw. <3> writes exception code (0010h, 0020h) to the higher halfword (fecc) of ecr. <4> sets the np and id bits of the psw and clears the ep bit. <5> sets the handler address (00000010h, 00000020h) corresponding to the non-maskable interrupt to the pc, and transfers control. the servicing configuration of a non-maskable interrupt is shown in figure 22-2. figure 22-2. servicing configuration of non-maskable interrupt psw.np fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restored pc psw 0010h 1 0 1 00000010h, 00000020h 1 0 nmi input non-maskable interrupt request interrupt servicing interrupt request held pending intc acknowledged cpu processing
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 745 22.2.2 restore (1) from nmi input execution is restored from the nmi servicing by the reti instruction. when the reti instruction is executed, the cpu performs the following processing, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from fepc and fepsw, respectively, because the ep bit of the psw is 0 and the np bit of the psw is 1. <2> transfers control back to the address of the restored pc and psw. figure 22-3 illustrates how the reti instruction is processed. figure 22-3. reti instruction processing psw.ep reti instruction psw.np original processing restored 1 1 0 0 pc psw eipc eipsw pc psw fepc fepsw caution when the psw.ep bit and psw.np bit are changed by the ldsr instruction during non- maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow. (2) from intwdt2 signal execution cannot be returned from intwdt2 by the reti instruction. execute a system reset after the interrupt has been serviced.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 746 22.2.3 np flag the np flag is a status flag that indicates that non-maskable interrupt servicing is under execution. this flag is set when a non-maskable interrupt request signal has been acknowledged, and masks non-maskable interrupt requests to prohibit multiple interrupts from being acknowledged. 0 np ep id sat cy ov s z psw no non-maskable interrupt servicing non-maskable interrupt currently being serviced np 0 1 non-maskable interrupt servicing status after reset: 00000020h 22.2.4 eliminating noise on nmi pin the nmi pin has a noise eliminator that eliminates noise using analog delay. unless the level input to the nmi pin is held for a specific time, therefore, it cannot be detected as an edge i.e., the edge is detected after specific time. the nmi pin is used to release the software stop mode. because the internal system clock is stopped in the software stop mode, noise is not eliminated by using the system clock. 22.2.5 function to detect edge of nmi pin the valid edge of the nmi pin can be selected from four types: ? rising edge ? , ? falling edge ? , ? both edges ? , and ? no edge detection ? . specify the valid edge of the nmi pin by using the intr0 and intf0 registers. after reset, it is specified that ? no edge is detected ? on the nmi pin. unless the valid edge is specified by the intf0 and intr0 registers, therefore, an interrupt request signal is not acknowledged (the nmi pin serves as a port pin). to use the p00/nmi pin as an i/o port pin, specify that the valid edge of the nmi pin is ? no edge detection ? .
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 747 (1) external interrupt falling edge specification register 0 (intf0) the intf0 register is an 8-bit register that specifies detection of the falling edge of an nmi via bit 2. this register can be read or written in 8-bit or 1-bit units. reset input cleats this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf0n and intr0n bits to 0, and then set the port mode. 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 after reset: 00h r/w address: fffffc00h remark for how to specify a valid edge, see table 22-2 . (2) external interrupt rising edge specification register 0 (intr0) the intr0 register is an 8-bit register that specifies detection of the rising edge of the nmi pin via bit 2. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf0n and intr0n bits to 0, and then set the port mode. 0 intr0 intr06 intr05 intr04 intr03 intr02 0 0 after reset: 00h r/w address: fffffc20h remark for how to specify a valid edge, see table 22-2 . table 22-2. nmi valid edge specification intf02 intr02 nmi valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 748 22.3 maskable interrupts maskable interrupt request signals can be masked by interrupt control registers. the v850es/sg2 has 54 maskable interrupt sources. if two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority. in addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). when an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt request signals is disabled and the interrupt disabled (di) status is set. when the ei instruction is executed in an interrupt service routine, the interrupt enabled (ei) status is set, which enables servicing of interrupts having a higher priority than the interrupt request signal in progress (specified by the interrupt control register). note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. to enable multiple interrupts, however, save eipc and eipsw to memory or registers before executing the ei instruction, and execute the di instruction before the reti instruction to restore the original values of eipc and eipsw. 22.3.1 operation if a maskable interrupt occurs, the cpu performs the following processing, and transfers control to a handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower halfword of ecr (eicc). <4> sets the id bit of the psw and clears the ep bit. <5> sets the handler address corresponding to each interrupt to the pc, and transfers control. the maskable interrupt request signal masked by intc and the maskable interrupt request signal generated while another interrupt is being serviced (while psw.np = 1 or psw.id = 1) are held pending inside intc. in this case, servicing a new maskable interrupt is started in accordance with the priority of the pending maskable interrupt request signal if either the maskable interrupt is unmasked or psw.np and psw.id are cleared to 0 by using the reti or ldsr instruction. how maskable interrupts are serviced is illustrated below.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 749 figure 22-4. maskable interrupt servicing int input xxif = 1 no xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request held pending psw.np psw.id 1 1 interrupt request held pending 0 0 interrupt servicing cpu processing intc accepted yes yes yes priority higher than that of interrupt currently being serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id corresponding bit of ispr note pc restored pc psw exception code 0 1 1 handler address interrupt requested? note for the ispr register, see 22.3.6 in-service priority register (ispr) .
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 750 22.3.2 restore recovery from maskable interrupt servicing is carried out by the reti instruction. when the reti instruction is executed, the cpu performs the following steps, and transfers control to the address of the restored pc. <1> loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 0 and the np bit of the psw is 0. <2> transfers control to the address of the restored pc and psw. figure 22-5 illustrates the processing of the reti instruction. figure 22-5. reti instruction processing psw.ep reti instruction psw.np restores original processing 1 1 0 0 pc psw corresponding bit of ispr note eipc eipsw 0 pc psw fepc fepsw note for the ispr register, see 22.3.6 in-service priority register (ispr) . caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during maskable interrupt servicing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 0 and psw.np back to 0 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 751 22.3.3 priorities of maskable interrupts the intc performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. multiple interrupts can be controlled by priority levels. there are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxprn) of the interrupt control register (xxicn). when two or more interrupts having the same priority level specified by the xxprn bit are generated at the same time, interrupt request signals are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. for more information, see table 22-1 interrupt/exception source list . the programmable priority control customizes interrupt request signals into eight levels by setting the priority level specification flag. note that when an interrupt request signal is acknowledged, the id flag of psw is automatically set to 1. therefore, when multiple interrupts are to be used, clear the id flag to 0 beforehand (for example, by placing the ei instruction in the interrupt service program) to set the interrupt enable mode. remark xx: identification name of each peripheral unit (see table 22-3 interrupt control register (xxicn) ) n: peripheral unit number (see table 22-3 interrupt control register (xxicn) ).
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 752 figure 22-6. example of processing in which another interrupt request signal is issued while an interrupt is being serviced (1/2) main routine ei ei interrupt request a (level 3) servicing of a servicing of b servicing of c interrupt request c (level 3) servicing of d servicing of e ei interrupt request e (level 2) servicing of f ei servicing of g interrupt request g (level 1) interrupt request h (level 1) servicing of h interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. interrupt request b (level 2) interrupt request d (level 2) interrupt request f (level 3) caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt request signals.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 753 figure 22-6. example of processing in which another interrupt request signal is issued while an interrupt is being serviced (2/2) main routine ei interrupt request i (level 2) servicing of i servicing of k interrupt request j (level 3) servicing of j interrupt request l (level 2) ei ei ei interrupt request o (level 3) interrupt request s (level 1) interrupt request k (level 1) servicing of l servicing of n servicing of m servicing of s servicing of u servicing of t interrupt request m (level 3) interrupt request n (level 1) servicing of o interrupt request p (level 2) interrupt request q (level 1) interrupt request r (level 0) interrupt request u (level 2) note 2 interrupt request t (level 2) note 1 servicing of p servicing of q servicing of r ei if levels 3 to 0 are acknowledged interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. pending interrupt requests are acknowledged after servicing of interrupt request l. at this time, interrupt request n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. pending interrupt requests t and u are acknowledged after servicing of s. because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. notes 1. lower default priority 2. higher default priority
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 754 figure 22-7. example of servicing interrupt request signals simultaneously generated default priority a > b > c main routine ei interrupt request a (level 2) interrupt request b (level 1) interrupt request c (level 1) servicing of interrupt request b . . servicing of interrupt request c servicing of interrupt request a interrupt request b and c are acknowledged first according to their priorities. because the priorities of b and c are the same, b is acknowledged first according to the default priority. caution to perform multiple interrupt servicing, the values of the eipc and eipsw registers must be saved before executing the ei instruction. when returning from multiple interrupt servicing, restore the values of eipc and eipsw after executing the di instruction. remarks 1. a to c in the figure are the temporary names of interrupt request signals shown for the sake of explanation. 2. the default priority in the figure indicates the relative priority between two interrupt request signals.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 755 22.3.4 interrupt control register (xxicn) the xxicn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 47h. caution disable interrupts (di) to read the xxifn bit of the xxicn register. if the xxifn bit is read while interrupts are enabled (ei), the correct value may not be read when acknowledging an interrupt and reading the bit conflict. xxifn interrupt request not issued interrupt request issued xxifn 0 1 interrupt request flag note xxicn xxmkn 0 0 0 xxprn2 xxprn1 xxprn0 interrupt servicing enabled interrupt servicing disabled (pending) xxmkn 0 1 interrupt mask flag specifies level 0 (highest). specifies level 1. specifies level 2. specifies level 3. specifies level 4. specifies level 5. specifies level 6. specifies level 7 (lowest). xxprn2 0 0 0 0 1 1 1 1 interrupt priority specification bit xxprn1 0 0 1 1 0 0 1 1 xxprn0 0 1 0 1 0 1 0 1 after reset: 47h r/w address: fffff112h to fffff17ch <6> <7> note the flag xxlfn is reset automatically by the hardware if an interrupt request signal is acknowledged. remark xx: identification name of each peripheral unit (see table 22-3 interrupt control register (xxicn) ) n: peripheral unit number (see table 22-3 interrupt control register (xxicn) ). the addresses and bits of the interrupt control registers are as follows.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 756 table 22-3. interrupt control register (xxicn) (1/2) bit address register <7><6>543210 fffff110h lviic lviif lvimk 0 0 0 lvipr2 lvipr1 lvipr0 fffff112h pic0 pif0 pmk0 0 0 0 ppr02 ppr01 ppr00 fffff114h pic1 pif1 pmk1 0 0 0 ppr12 ppr11 ppr10 fffff116h pic2 pif2 pmk2 0 0 0 ppr22 ppr21 ppr20 fffff118h pic3 pif3 pmk3 0 0 0 ppr32 ppr31 ppr30 fffff11ah pic4 pif4 pmk4 0 0 0 ppr42 ppr41 ppr40 fffff11ch pic5 pif5 pmk5 0 0 0 ppr52 ppr51 ppr50 fffff11eh pic6 pif6 pmk6 0 0 0 ppr62 ppr61 ppr60 fffff120h pic7 pif7 pmk7 0 0 0 ppr72 ppr71 ppr70 fffff122h tq0ovic tq0ovif tq0ovmk 0 0 0 tq0ovpr2 tq0ovpr1 tq0ovpr0 fffff124h tq0ccic0 tq0ccif0 tq0ccmk0 0 0 0 tq0ccpr02 tq0ccpr01 tq0ccpr00 fffff126h tq0ccic1 tq0ccif1 tq0ccmk1 0 0 0 tq0ccpr12 tq0ccpr11 tq0ccpr10 fffff128h tq0ccic2 tq0ccif2 tq0ccmk2 0 0 0 tq0ccpr22 tq0ccpr21 tq0ccpr20 fffff12ah tq0ccic3 tq0ccif3 tq0ccmk3 0 0 0 tq0ccpr32 tq0ccpr31 tq0ccpr30 fffff12ch tp0ovic tp0ovif tp0ovmk 0 0 0 tp0ovpr2 tp0ovpr1 tp0ovpr0 fffff12eh tp0ccic0 tp0ccif0 tp0ccmk0 0 0 0 tp0ccpr02 tp0ccpr01 tp0ccpr00 fffff130h tp0ccic1 tp0ccif1 tp0ccmk1 0 0 0 tp0ccpr12 tp0ccpr11 tp0ccpr10 fffff132h tp1ovic tp1ovif tp1ovmk 0 0 0 tp1ovpr2 tp1ovpr1 tp1ovpr0 fffff134h tp1ccic0 tp1ccif0 tp1ccmk0 0 0 0 tp1ccpr02 tp1ccpr01 tp1ccpr00 fffff136h tp1ccic1 tp1ccif1 tp1ccmk1 0 0 0 tp1ccpr12 tp1ccpr11 tp1ccpr10 fffff138h tp2ovic tp2ovif tp2ovmk 0 0 0 tp2ovpr2 tp2ovpr1 tp2ovpr0 fffff13ah tp2ccic0 tp2ccif0 tp2ccmk0 0 0 0 tp2ccpr02 tp2ccpr01 tp2ccpr00 fffff13ch tp2ccic1 tp2ccif1 tp2ccmk1 0 0 0 tp2ccpr12 tp2ccpr11 tp2ccpr10 fffff13eh tp3ovic tp3ovif tp3ovmk 0 0 0 tp3ovpr2 tp3ovpr1 tp3ovpr0 fffff140h tp3ccic0 tp3ccif0 tp3ccmk0 0 0 0 tp3ccpr02 tp3ccpr01 tp3ccpr00 fffff142h tp3ccic1 tp3ccif1 tp3ccmk1 0 0 0 tp3ccpr12 tp3ccpr11 tp3ccpr10 fffff144h tp4ovic tp4ovif tp4ovmk 0 0 0 tp4ovpr2 tp4ovpr1 tp4ovpr0 fffff146h tp4ccic0 tp4ccif0 tp4ccmk0 0 0 0 tp4ccpr02 tp4ccpr01 tp4ccpr00 fffff148h tp4ccic1 tp4ccif1 tp4ccmk1 0 0 0 tp4ccpr12 tp4ccpr11 tp4ccpr10 fffff14ah tp5ovic tp5ovif tp5ovmk 0 0 0 tp5ovpr2 tp5ovpr1 tp5ovpr0 fffff14ch tp5ccic0 tp5ccif0 tp5ccmk0 0 0 0 tp5ccpr02 tp5ccpr01 tp5ccpr00 fffff14eh tp5ccic1 tp5ccif1 tp5ccmk1 0 0 0 tp5ccpr12 tp5ccpr11 tp5ccpr10 fffff150h tm0eqic0 tm0eqif0 tm0eqmk0 0 0 0 tm0eqpr02 tm0eqpr01 tm0eqpr00 fffff152h cb0ric/ iicic1 note cb0rif/ iicif1 cb0rmk/ iicmk1 000 cb0rpr2/ iicpr12 cb0rpr1/ iicpr11 cb0rpr0/ iicpr10 fffff154h cb0tic cb0tif cb0tmk 0 0 0 cb0tpr2 cb0tpr1 cb0tpr0 fffff156h cb1ric cb1rif cb1rmk 0 0 0 cb1rpr2 cb1rpr1 cb1rpr0 fffff158h cb1tic cb1tif cb1tmk 0 0 0 cb1tpr2 cb1tpr1 cb1tpr0 fffff15ah cb2ric cb2rif cb2rmk 0 0 0 cb2rpr2 cb2rpr1 cb2rpr0 fffff15ch cb2tic cb2tif cb2tmk 0 0 0 cb2tpr2 cb2tpr1 cb2tpr0 fffff15eh cb3ric cb3rif cb3rmk 0 0 0 cb3rpr2 cb3rpr1 cb3rpr0 fffff160h cb3tic cb3tif cb3tmk 0 0 0 cb3tpr2 cb3tpr1 cb3tpr0 note i 2 c bus version (y version) only
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 757 table 22-3. interrupt control register (xxicn) (2/2) bit address register <7><6>543210 fffff162h ua0ric/ cb4ric ua0rif/ cb4rif ua0rmk/ cb4rmk 000 ua0rpr2/ cb4rpr2 ua0rpr1/ cb4rpr1 ua0rpr0/ cb4rpr0 fffff164h ua0tic/ cb4tic ua0tif/ cb4tif ua0tmk/ cb4tmk 0 0 0 ua0tpr2/ cb4tpr2 ua0tpr1/ cb4tpr1 ua0tpr0/ cb4tpr0 fffff166h ua1ric/ iicic2 note 1 ua1rif/ iicif2 ua1rmk/ iicmk2 000 ua1rpr2/ iicpr22 ua1rpr1/ iicpr21 ua1rpr0/ iicpr20 fffff168h ua1tic ua1tif ua1tmk 0 0 0 ua1tpr2 ua1tpr1 ua1tpr0 fffff16ah ua2ric/ iicic0 note 1 ua2rif/ iicif0 ua2rmk/ iicmk0 0 0 0 ua2rpr2/ iicpr02 ua2rpr1/ iicpr01 ua2rpr0/ iicpr00 fffff16ch ua2tic ua2tif ua2tmk 0 0 0 ua2tpr2 ua2tpr1 ua2tpr0 fffff16eh adic adif admk 0 0 0 adpr2 adpr1 adpr0 fffff170h dmaic0 dmaif0 dmamk0 0 0 0 dmapr02 dmapr01 dmapr00 fffff172h dmaic1 dmaif1 dmamk1 0 0 0 dmapr12 dmapr11 dmapr10 fffff174h dmaic2 dmaif2 dmamk2 0 0 0 dmapr22 dmapr21 dmapr20 fffff176h dmaic3 dmaif3 dmamk3 0 0 0 dmapr32 dmapr31 dmapr30 fffff178h kric krif krmk 0 0 0 krpr2 krpr1 krpr0 fffff17ah wtiic wtiif wtimk 0 0 0 wtipr2 wtipr1 wtipr0 fffff17ch wtic wtif wtmk 0 0 0 wtpr2 wtpr1 wtpr0 fffff17eh erric0 note 2 / erric note 3 errif0/ errif errmk0/ errmk 0 0 0 errpr02/ errpr2 errpr01/ errpr1 errpr00/ errpr0 fffff180h wupic0 note 2 / staic note 3 wupif0/ staif wupmk0/ stami 000 wuppr02/ stapr2 wuppr01/ stapr1 wuppr00/ stapr0 fffff182h recic0 note 2 / ieic1 note 3 recif0/ ieif1 recmk0/ iemk1 0 0 0 recpr02/ iepr12 recpr01/ iepr11 recpr00/ iepr10 fffff184h trxic0 note 2 / ieic2 note 3 trxif0/ ieif2 trxmk0/ iemk2 000 trxpr02/ iepr22 trxpr01/ iepr21 trxpr00/ iepr20 notes 1. i 2 c bus version (y version) only 2. can controller version only 3. iebus controller version only
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 758 22.3.5 interrupt mask registers 0 to 3 (imr0 to imr3) the imr0 to imr3 registers set the interrupt mask state for the maskable interrupts. the xxmkn bit of the imr0 to imr3 registers is equivalent to the xxmkn bit of the xxicn register. the imrm register can be read or written in 16-bit units (m = 0 to 3). if the higher 8 bits of the imrm register are used as an imrmh register and the lower 8 bits as an imrml register, these registers can be read or written in 8-bit or 1-bit units (m = 0 to 3). bits 11 to 15 of the imr3 register are fixed to 1. if these bits are not 1, the operation cannot be guaranteed. reset input sets these registers to ffffh. caution the device file defines the xxmkn bit of the xxicn register as a reserved word. if a bit is manipulated using the name of xxmkn, the contents of the xxicn register, instead of the imrm register, are rewritten (as a result, the contents of the imrm register are also rewritten). tp0ccmk0 pmk6 imr0 tp0ovmk pmk5 tq0ccmk3 pmk4 tq0ccmk2 pmk3 tq0ccmk1 pmk2 tq0ccmk0 pmk1 tq0ovmk pmk0 pmk7 lvimk after reset: ffffh r/w address: fffff100h after reset: ffffh r/w address: fffff102h after reset: ffffh r/w address: fffff104h tp5ccmk1 tp3ovmk imr1 tp5ccmk0 tp2ccmk1 tp5ovmk tp2ccmk0 tp4ccmk1 tp2ovmk tp4ccmk0 tp1ccmk1 tp4ovmk tp1ccmk0 tp3ccmk1 tp1ovmk tp3ccmk0 tp0ccmk1 admk cb3rmk cb3tmk tm0eqmk0 xxmkn 0 1 interrupt servicing enabled interrupt servicing disabled imr2 ua2tmk cb2tmk cb2rmk ua1tmk cb1tmk cb1rmk cb0tmk ua0tmk/ cb4tmk ua2rmk/ iicmk0 ua0rmk/ cb4rmk cb0rmk/ iicmk1 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 1 imr3 1 wtmk 1 wtimk 1 krmk 1 dmamk3 dmamk2 dmamk1 dmamk0 after reset: ffffh r/w address: fffff106h 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 8 9 10 11 12 13 setting of interrupt mask flag 14 15 1 2 3 4 5 6 7 0 ua1rmk/ iic2mk trxmk0/ iemk2 recmk0/ iemk1 wupmk0/ stamk errmk0/ errmk remark xx: identification name of each peripheral unit (see table 22-3 interrupt control register (xxicn) ). n: peripheral unit number (see table 22-3 interrupt control register (xxicn) )
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 759 22.3.6 in-service priority register (ispr) the ispr register holds the priority level of the maskable interrupt currently acknowledged. when an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced. when the reti instruction is executed, the bit corresponding to the interrupt request signal having the highest priority is automatically reset to 0 by hardware. however, it is not reset to 0 when execution is returned from non- maskable interrupt servicing or exception processing. this register is read-only, in 8-bit or 1-bit units. reset input clears this register to 00h. caution if an interrupt is acknowledged while the ispr register is being read in the interrupt enabled (ei) status, the value of the ispr register after the bits of the register have been set by acknowledging the interrupt may be read. to accurately read the value of the ispr register before an interrupt is acknowledged, read the register while interrupts are disabled (di). ispr7 interrupt request signal with priority n not acknowledged interrupt request signal with priority n acknowledged isprn 0 1 priority of interrupt currently acknowledged ispr ispr6 ispr5 ispr4 ispr3 ispr2 ispr1 ispr0 after reset: 00h r address: fffff1fah <7> <6> <5> <4> <3> <2> <1> <0> remark n = 0 to 7 (priority level)
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 760 22.3.7 id flag this flag controls the maskable interrupt ? s operating state, and stores control information regarding enabling or disabling of interrupt request signals. an interrupt disable flag (id) is incorporated, which is assigned to the psw. 0 np ep id sat cy ov s z psw maskable interrupt request signal acknowledgment enabled maskable interrupt request signal acknowledgment disabled (pending) id 0 1 specification of maskable interrupt servicing note after reset: 00000020h note interrupt disable flag (id) function this bit is set to 1 by the di instruction and reset to 0 by the ei instruction. its value is also modified by the reti instruction or ldsr instruction when referencing the psw. non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. when a maskable interrupt request signal is acknowledged, the id flag is automatically set to 1 by hardware. the interrupt request signal generated during the acknowledgment disabled period (id = 1) is acknowledged when the xxifn bit of xxicn is set to 1, and the id flag is reset to 0.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 761 22.3.8 watchdog timer mode register 2 (wdtm2) the wdtm2 register is a special register and write-only in a specific sequence. this register can be read or written in 8-bit or 1-bit units (for details, see chapter 12 functions of watchdog timer 2 ). reset input clears this register to 00h. 0 wdtm2 wdm21 wdm20 0 0 0 0 0 after reset: 00h r/w address: fffff6d0h stops operation non-maskable interrupt request mode reset mode (initial-value) wdm21 0 0 1 wdm20 0 1 selection of watchdog timer operation mode 22.3.9 eliminating noise on intp0 to intp7 pins the intp0 to intp7 pins have a noise eliminator that eliminates noise using analog delay. unless the level input to each pin is held for a specific time, therefore, it cannot be detected as a signal edge i.e., the edge is detected after specific time. 22.3.10 function to detect edge of intp0 to intp7 pins the valid edge of the intp0 to intp7 pins can be selected from the following four. ? rising edge ? falling edge ? both edges ? no edge detection
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 762 (1) external interrupt falling edge specification register 0 (intf0) the intf0 register is an 8-bit register that specifies detection of the falling edge of the external interrupt pins (intp0 to intp3) by bits 3 to 6. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf0n and intr0n bits to 0, and then set the port mode. 0 intf0 intf06 intf05 intf04 intf03 intf02 0 0 after reset: 00h r/w address: fffffc00h remark for how to specify a valid edge, see table 22-4 . (2) external interrupt rising edge specification register 0 (intr0) the intr0 register is an 8-bit register that specifies detection of the rising edge of the external interrupt pins (intp0 to intp3) via bits 3 to 6. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf0n and intr0n bits to 0, and then set the port mode. 0 intr0 intr06 intr05 intr04 intr03 intr02 0 0 after reset: 00h r/w address: fffffc20h remark for how to specify a valid edge, see table 22-4 . table 22-4. valid edge specification intf0n intr0n valid edge specification (n = 2 to 6) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges remark n = 3 to 6: control of intp0 to intp3 pins
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 763 (3) external interrupt falling edge specification register 3l (intf3l) the intf3l register is an 8-bit register that specifies detection of the falling edge of the external interrupt pin (intp7). this register can be read or written in 8-bit or 1-bit units. reset input cleats this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf31 and intr31 bits to 0, and then set the port mode. intf3l after reset: 00h r/w address: fffffc06h 0 0 0 0 0 0 intf31 0 remark for how to specify a valid edge, see table 22-5 . (4) external interrupt rising edge specification register 3l (intr3l) the intr3l register is an 8-bit register that specifies detection of the rising edge of the external interrupt pin (intp7). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf31 and intr31 bits to 0, and then set the port mode. intr3 after reset: 00h r/w address: fffffc26h 0 0 0 0 0 0 intr31 0 remark for how to specify a valid edge, see table 22-5 . table 22-5. valid edge specification intf31 intr31 valid edge specification 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf31 and intr31 bits to 00 when these registers are not used as intp7.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 764 (5) external interrupt falling edge specification register 9h (intf9h) the intf9h register is an 8-bit register that specifies detection of the falling edge of the external interrupt pins (intp4 to intp6). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf9n and intr9n bits to 0, and then set the port mode. intf9h after reset: 00h r/w address: fffffc13h inth915 intf914 intf913 0 0 0 0 0 8 9 10 11 12 13 14 15 remark for how to specify a valid edge, see table 22-6 . (6) external interrupt rising edge specification register 9h (intr9h) the intr9h register is an 8-bit register that specifies detection of the rising edge of the external interrupt pins (intp4 to intp6). this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. caution when the function is changed from the external interrupt function (alternate function) to the port function, an edge may be detected. therefore, clear the intf9n and intr9n bits to 0, and then set the port mode. intr9h after reset: 00h r/w address: fffffc33h intr915 intr914 intr913 0 0 0 0 0 8 9 10 11 12 13 14 15 remark for how to specify a valid edge, see table 22-6 . table 22-6. valid edge specification intf9n intr9n valid edge specification (n = 13 to 15) 0 0 no edge detected 0 1 rising edge 1 0 falling edge 1 1 both rising and falling edges caution be sure to clear the intf9n and intr9n bits to 00 when these registers are not used as intp4 to intp6. remark n = 13 to 15: control of intp4 to intp6 pins
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 765 (7) noise elimination control register digital noise elimination can be selected for the intp3 pin. the noise elimination settings are performed with the nfc register. when digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f xx /64, f xx /128, f xx /256, f xx /512, f xx /1,024, and f xt . sampling is performed 3 times. even when digital noise elimination is selected, using f xt as the sampling clock makes it possible to use the intp3 interrupt request signal to release the idle and stop modes. this register can be read or written in 8-bit units. reset input clears this register to 00h. caution after the sampling clock has been changed, it takes 3 sampling clocks to initialize the digital noise eliminator. therefore, if an intp3 valid edge is input within these 3 sampling clocks after the sampling clock has been changed, an interrupt request signal may occur. therefore, be careful about the following points when using the dma function. ? ? ? ? when using the interrupt function, after the 3 sampling clocks have elapsed, allow the interrupt after the interrupt request flag (bit 7 of pic3) has been cleared. ? ? ? ? when using the dma function (started with intp3), enable dma after 3 sampling clocks have elapsed. nfen nfc 0 0 0 0 nfc2 nfc1 nfc0 f xx /64 f xx /128 f xx /256 f xx /512 f xx /1,024 f xt (subclock) nfc2 0 0 0 0 1 1 digital sampling clock setting prohibited nfc1 0 0 1 1 0 0 nfc0 0 1 0 1 0 1 after reset: 00h r/w address: fffff318h analog noise elimination (60 ns (typ.)) digital noise elimination nfen 0 1 settings of intp3 pin noise elimination other than above remarks 1. since sampling is performed 3 times, the reliably eliminated noise width is 2 sampling clocks. 2. in the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is generated if noise synchronized with the sampling clock is input.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 766 22.4 software exception a software exception is generated when the cpu executes the trap instruction, and can always be acknowledged. 22.4.1 operation if a software exception occurs, the cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to eipc. <2> saves the current psw to eipsw. <3> writes an exception code to the lower 16 bits (eicc) of ecr (interrupt source). <4> sets the ep and id bits of the psw. <5> sets the handler address (00000040h or 00000050h) corresponding to the software exception to the pc, and transfers control. figure 22-8 illustrates the processing of a software exception. figure 22-8. software exception processing trap instruction eipc eipsw ecr.eicc psw.ep psw.id pc restored pc psw exception code 1 1 handler address cpu processing exception processing note note trap instruction format: trap vector (the vector is a value from 0 to 1fh.) the handler address is determined by the trap instruction ? s operand (vector). if the vector is 0 to 0fh, it becomes 00000040h, and if the vector is 10h to 1fh, it becomes 00000050h.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 767 22.4.2 restore recovery from software exception processing is carried out by the reti instruction. by executing the reti instruction, the cpu carries out the following processing and shifts control to the restored pc ? s address. <1> loads the restored pc and psw from eipc and eipsw because the ep bit of the psw is 1. <2> transfers control to the address of the restored pc and psw. figure 22-9 illustrates the processing of the reti instruction. figure 22-9. reti instruction processing psw.ep reti instruction pc psw eipc eipsw psw.np original processing restored pc psw fepc fepsw 1 1 0 0 caution when the psw.ep bit and the psw.np bit are changed by the ldsr instruction during the software exception processing, in order to restore the pc and psw correctly during recovery by the reti instruction, it is necessary to set psw.ep back to 1 using the ldsr instruction immediately before the reti instruction. remark the solid line shows the cpu processing flow.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 768 22.4.3 ep flag the ep flag is bit 6 of the psw, and is a status flag used to indicate that exception processing is in progress. it is set when an exception occurs. 0 np ep id sat cy ov s z psw exception processing not in progress. exception processing in progress. ep 0 1 exception processing status after reset: 00000020h
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 769 22.5 exception trap an exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. in the v850es/sg2, an illegal opcode exception (ilgop: illegal opcode trap) is considered as an exception trap. 22.5.1 illegal opcode definition the illegal instruction has an opcode (bits 10 to 5) of 111111b, a sub-opcode (bits 26 to 23) of 0111b to 1111b, and a sub-opcode (bit 16) of 0b. an exception trap is generated when an instruction applicable to this illegal instruction is executed. 15 16 23 22 0 1 1 1 1 1 1 27 26 31 0 4 5 10 11 1 1 1 1 1 1 0 1 to : arbitrary caution since it is possible to assign this instruction to an illegal opcode in the future, it is recommended that it not be used. (1) operation if an exception trap occurs, the cpu performs the following processing, and transfers control to the handler routine. <1> saves the restored pc to dbpc. <2> saves the current psw to dbpsw. <3> sets the np, ep, and id bits of the psw. <4> sets the handler address (00000060h) corresponding to the exception trap to the pc, and transfers control. figure 22-10 illustrates the processing of the exception trap.
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 770 figure 22-10. exception trap processing exception trap (ilgop) occurs dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing (2) restore recovery from an exception trap is carried out by the dbret instruction. by executing the dbret instruction, the cpu carries out the following processing and controls the address of the restored pc. <1> loads the restored pc and psw from dbpc and dbpsw. <2> transfers control to the address indicated by the restored pc and psw. figure 22-11 illustrates the restore processing from an exception trap. figure 22-11. restore processing from exception trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 771 22.5.2 debug trap a debug trap is an exception that is generated when the dbtrap instruction is executed and is always acknowledged. upon occurrence of a debug trap, the cpu performs the following processing. (1) operation <1> saves restored pc to dbpc. <2> saves current psw to dbpsw. <3> sets the np, ep, and id bits of psw. <4> sets handler address (00000060h) for d ebug trap to pc and transfers control. figure 22-12 shows the debug trap processing format. figure 22-12. debug trap processing format dbtrap instruction dbpc dbpsw psw.np psw.ep psw.id pc restored pc psw 1 1 1 00000060h exception processing cpu processing
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 772 (2) restoration restoration from a debug trap is executed with the dbret instruction. with the dbret instruction, the cpu performs the following steps and transfers control to the address of the restored pc. <1> the restored pc and psw are read from dbpc and dbpsw. <2> control is transferred to the fetched address of the restored pc and psw. table 22-13 shows the processing format for restoration from a debug trap. figure 22-13. processing format of restoration from debug trap dbret instruction pc psw dbpc dbpsw jump to address of restored pc
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 773 22.6 interrupt acknowledge time of cpu except the following cases, the interrupt acknowledge time of the cpu is 5 clocks minimum. to input interrupt request signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt. ? in software/hardware stop mode ? when the external bus is accessed ? when interrupt request non-sampling instructions are successively executed (see 22.7 periods in which interrupts are not acknowledged by cpu .) ? when the interrupt control register is accessed figure 22-14. pipeline operation at interrupt request signal acknowledgment (outline) internal clock instruction 1 instruction 2 interrupt acknowledgment operation instruction (start instruction of interrupt service routine) interrupt request if id ex df wb ifx idx 4 system clocks if if id ex int1 int2 int3 int4 remark int1 to int4: interrupt acknowledgment processing ifx: invalid instruction fetch idx: invalid instruction decode interrupt acknowledge time (internal system clock) internal interrupt external interrupt condition minimum 4 4 + analog delay time maximum 6 6 + analog delay time the following cases are exceptions. ? in idle/software stop mode ? external bus access ? two or more interrupt request non-sample instructions are executed in succession ? access to peripheral i/o register
chapter 22 interrupt/exception processing function preliminary user ? s manual u16541ej1v0um 774 22.7 periods in which interrupts are not acknowledged by cpu an interrupt is acknowledged by the cpu while an instruction is being executed. however, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). the interrupt request non-sample instructions are as follows. ? ei instruction ? di instruction ? ldsr reg2, 0x5 instruction (for psw) ? the store instruction for the command register (prcmd) ? the load, store, or bit manipulation instructions for the following interrupt-related registers. interrupt control register (xxicn), interrupt mask registers 0 to 3 (imr0 to imr3), in-service priority register (ispr) remark xx: identification name of each peripheral unit (see table 22-3 interrupt control register (xxicn) ) n: peripheral unit number (see table 22-3 interrupt control register (xxicn) ).
preliminary user?s manual u16541ej1v0um 775 chapter 23 key interrupt function 23.1 function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the eight key input pins (kr0 to kr7) by setting the key return mode register (krm). table 23-1. assignment of key return detection pins flag pin description krm0 controls kr0 signal in 1-bit units krm1 controls kr1 signal in 1-bit units krm2 controls kr2 signal in 1-bit units krm3 controls kr3 signal in 1-bit units krm4 controls kr4 signal in 1-bit units krm5 controls kr5 signal in 1-bit units krm6 controls kr6 signal in 1-bit units krm7 controls kr7 signal in 1-bit units figure 23-1. key return block diagram intkr key return mode register (krm) krm7 krm6 krm5 krm4 krm3 krm2 krm1 krm0 kr7 kr6 kr5 kr4 kr3 kr2 kr1 kr0
chapter 23 key interrupt function preliminary user ? s manual u16541ej1v0um 776 23.2 control register (1) key return mode register (krm) the krm register controls the krm0 to krm7 bits using the kr0 to kr7 signals. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. krm7 does not detect key return signal detects key return signal krmn 0 1 control of key return mode krm krm6 krm5 krm4 krm3 krm2 krm1 krm0 < > < > < > < > < > < > < > < > after reset: 00h r/w address: fffff300h caution if the krm register is changed, an interrupt request flag may be set. to prevent this, change the krm register after disabling interrupts, and then enable interrupts after clearing the interrupt request flag.
preliminary user?s manual u16541ej1v0um 777 chapter 24 standby function 24.1 overview the power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. the available standby modes are listed in table 24-1. table 24-1. standby modes mode functional outline halt mode mode to stop only the operating clock of the cpu idle1 mode mode to stop all the internal operations of the chip except the oscillator, pll operation note , and flash memory programming mode idle2 mode mode to stop all the internal operations of the chip except the oscillator software stop mode mode to stop all the internal operations of the chip except the subclock oscillator subclock operation mode mode to use the subclock as the internal system clock sub-idle mode mode to stop all the internal operations of the chip except the oscillator, pll operation note , and flash memory programming mode, in the subclock operation mode note the pll holds the previous operation status (in clock-through mode or pll mode).
chapter 24 standby function preliminary user?s manual u16541ej1v0um 778 figure 24-1. status transition normal operation mode (operation with main clock) wait for stabilization of oscillation wait for stabilization of oscillation wait for stabilization of oscillation end of oscillation stabilization time count end of oscillation stabilization time count end of oscillation stabilization time count setting of halt mode interrupt note 2 setting of stop mode idle1/idle2 mode halt mode software stop mode reset note 6 interrupt note 3 setting of idle mode interrupt note 5 reset note 4 reset note 4 setup wait note 1 notes 1. idle2 mode only 2. non-maskable interrupt request signal (nmi, intwdt2), unmasked external interrupt request signal, or unmasked internal maskable interrupt request signal operable in idle1/idle2 mode. 3. non-maskable interrupt request signal, unmasked external interrupt request signal, or unmasked internal maskable interrupt request signal. 4. reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm). 5. non-maskable interrupt request signal (nmi, intwdt2), unmasked external interrupt request signal, or unmasked internal maskable interrupt request signal operable in software stop mode. 6. reset by reset pin input, wdt2res signal, or low-voltage detector (lvi).
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 779 figure 24-2. status transition (during subclock operation) normal operation mode (operation with main clock) wait for stabilization of oscillation sub-idle mode subclock operation mode end of oscillation stabilization time count reset note 1 setting of normal operation setting of subclock operation setting of idle mode interrupt note 2 reset note 1 notes 1. reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm). 2. non-maskable interrupt request signal (nmi, intwdt2), unmasked external interrupt request signal, or unmasked internal maskable interrupt request signal operable in sub-idle mode.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 780 24.2 halt mode 24.2.1 setting and operation status the halt mode is set when a dedicated instruction (halt) is executed in the normal operation mode. in the halt mode, the clock oscillator continues operating. only clock supply to the cpu is stopped; clock supply to the other on-chip peripheral functions continues. as a result, program execution is stopped, and the internal ram retains the contents before the halt mode was set. the on-chip peripheral functions that are independent of instruction processing by the cpu continue operating. table 24-3 shows the operation status in the halt mode. the average power consumption of the system can be reduced by using the halt mode in combination with the normal operation mode for intermittent operation. cautions 1. insert five or more nop instructions after the halt instruction. 2. when the halt instruction is executed while an interrupt request signal is being held pending, the status shifts to halt mode, but the halt mode is then released immediately by the pending interrupt request. 24.2.2 releasing halt mode the halt mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from a peripheral function operable in the halt mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). after the halt mode has been released, the normal operation mode is restored. (1) releasing halt mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal the halt mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the halt mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the halt mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the halt mode is released and that interrupt request signal is acknowledged. table 24-2. operation after releasing halt mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address or the next instruction is executed. the next instruction is executed.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 781 (2) releasing halt mode by reset input the same operation as the normal reset operation is performed. table 24-3. operation status in halt mode setting of halt mode operation status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled ring-osc generator oscillation enabled pll operable cpu stops operation dma operable interrupt controller operable rom correction stops operation timer p (tmp0 to tmp5) stops operation timer q (tmp0) stops operation timer m (tmm0) operable when a clock other than f xt is selected as the count clock operable watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable when a clock other than f xt is selected as the count clock operable csib0 to csib4 operable i 2 c00 to i 2 c02 operable serial interface uarta0 to uarta2 operable can controller operable iebus controller operable a/d converter operable d/a converter operable real-time output function (rto) operable key interrupt function (kr) operable crc arithmetic circuit operable (in the status in which data is not input to crcin to stop the cpu) external bus interface see chapter 5 bus control function . port function retains status before halt mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the halt mode was set.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 782 24.3 idle1 mode 24.3.1 setting and operation status the idle1 mode is set by clearing the psm1 and psm0 bits of the psmr register to 00 and setting the stp bit of the psc register to 1 in the normal operation mode. in the idle1 mode, the clock oscillator, pll operation, and flash memory continue operating but clock supply to the cpu and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle1 mode was set are retained. the cpu and other on-chip peripheral functions stop operating. however, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. table 24-5 shows the operation status in the idle1 mode. the idle1 mode can reduce the current consumption more than the halt mode because it stops the operation of the on-chip peripheral functions. the main clock oscillator does not stop, so the normal operation mode can be restored without waiting for the oscillation stabilization time after the idle1 mode has been released, in the same manner as when the halt mode is released. caution insert five or more nop instructions after the instruction that stores data in the psc register to set the idle1 mode. 24.3.2 releasing idle1 mode the idle1 mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from a peripheral function operable in the idle1 mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). after the idle1 mode has been released, the normal operation mode is restored. (1) releasing idle1 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal the idle1 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle1 mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is processed as follows. caution an interrupt request signal that is disabled by setting the nmi1m, nmi0m, and intm bits of the psc register to 1 becomes invalid and idle1 mode is not released. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the idle1 mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the idle1 mode is released and that interrupt request signal is acknowledged.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 783 table 24-4. operation after releasing idle1 mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after securing the prescribed setup time. maskable interrupt request signal execution branches to the handler address or the next instruction is executed after securing the prescribed setup time. the next instruction is executed after securing the prescribed setup time. (2) releasing idle1 mode by reset input the same operation as the normal reset operation is performed. table 24-5. operation status in idle1 mode setting of idle1 mode operation status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled ring-osc generator oscillation enabled pll operable cpu stops operation dma stops operation interrupt controller stops operation (but standby mode release enabled) rom correction stops operation timer p (tmp0 to tmp5) stops operation timer q (tmq0) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable when f r is selected as the count clock operable when f r or f xt is selected as the count clock csib0 to csib4 operable when sckbn input clock is selected as operation clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation serial interface uarta0 to uarta2 stops operation (but uarta0 is operable when the ascka0 input clock is selected) can controller stops operation iebus controller stops operation a/d converter stops operation d/a converter stops operation real-time output function (rto) stops operation key interrupt function (kr) operable crc arithmetic circuit stops operation external bus interface see chapter 5 bus control function . port function retains status before idle1 mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle1 mode was set.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 784 24.4 idle2 mode 24.4.1 setting and operation status the idle2 mode is set by setting the psm1 and psm0 bits of the psmr register to 10 and setting the stp bit of the psc register to 1 in the normal operation mode. in the idle2 mode, the clock oscillator continues operation but clock supply to the cpu, pll operation, flash memory, and other on-chip peripheral functions stops. as a result, program execution stops and the contents of the internal ram before the idle2 mode was set are retained. the cpu and other on-chip peripheral functions stop operating. however, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. table 24-7 shows the operation status in the idle2 mode. the idle2 mode can reduce the current consumption more than the idle1 mode because it stops the operations of the on-chip peripheral functions and flash memory. however, because the pll operation and flash memory are stopped, a setup time for the pll operation and flash memory is required when idle2 mode is released. caution insert five or more nop instructions after the instruction that stores data in the psc register to set the idle2 mode. 24.4.2 releasing idle2 mode the idle2 mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the idle2 mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). the pll returns to the operation status before the idle2 mode was set. after the idle2 mode has been released, the normal operation mode is restored. (1) releasing idle2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal the idle2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the idle2 mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is processed as follows. caution the interrupt request signal that is disabled by setting the nmi1m, nmi0m, and intm bits of the psc register to 1 becomes invalid and idle2 mode is not released. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the idle2 mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the idle2 mode is released and that interrupt request signal is acknowledged.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 785 table 24-6. operation after releasing idle2 mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after securing the prescribed setup time. maskable interrupt request signal execution branches to the handler address or the next instruction is executed after securing the prescribed setup time. the next instruction is executed after securing the prescribed setup time. (2) releasing idle2 mode by reset input the same operation as the normal reset operation is performed. table 24-7. operation status in idle2 mode setting of idle2 mode operation status item when subclock is not used when subclock is used main clock oscillator oscillation enabled subclock oscillator ? oscillation enabled ring-osc generator oscillation enabled pll stops operation (recommended to stopping pll operation because of reducing consumption current) cpu stops operation dma stops operation interrupt controller stops operation rom correction stops operation timer p (tmp0 to tmp5) stops operation timer q (tmp0) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer operable when f x (divided brg) is selected as the count clock operable watchdog timer 2 operable when f r is selected as the count clock operable when f r or f xt is selected as the count clock csib0 to csib4 operable when sckbn input clock is selected as operation clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation serial interface uarta0 to uarta2 stops operation (but uarta0 is operable when the ascka0 input clock is selected) can controller stops operation iebus controller stops operation a/d converter operable when f brg is selected as operation clock d/a converter stops operation real-time output function (rto) stops operation key interrupt function (kr) operable crc arithmetic circuit stops operation external bus interface see chapter 5 bus control function . port function retains status before idle2 mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the idle2 mode was set.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 786 24.4.3 securing setup time when releasing idle2 mode secure the setup time for the rom (flash memory) after releasing the idle2 mode because the operation of the blocks other than the main clock oscillator stops after idle2 mode is set. (1) releasing idle2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal secure the specified setup time by setting the osts register. when the releasing source is generated, the dedicated internal timer starts counting according to the osts register setting. when it overflows, the normal operation mode is restored. oscillated waveform rom circuit stopped setup time count main clock idle mode status interrupt request (2) release by reset input (reset pin input, wdt2res generation) this operation is the same as that of a normal reset. the oscillation stabilization time is the initial value of the osts register, 2 16 /f x .
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 787 24.5 software stop mode 24.5.1 setting and operation status the software stop mode is set by setting the psm1 and psm0 bits of the psmr register to 01 and setting the stp bit of the psc register to 1 in the normal operation mode. in the software stop mode, the subclock oscillator continues operation but the main clock oscillator stops. clock supply to the cpu and the on-chip peripheral functions is stopped. as a result, program execution stops, and the contents of the internal ram before the software stop mode was set are retained. the on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an external clock continue operating. table 24-9 shows the operation status in the software stop mode. because the software stop stops operation of the main clock oscillator, it reduces the current consumption to a level lower than the idle2 mode. if the subclock oscillator, ring-osc, and external clock are not used, the power consumption can be minimized with only leakage current flowing. caution insert five or more nop instructions after the instruction that stores data in the psc register to set the software stop mode. 24.5.2 releasing software stop mode the software stop mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the software stop mode, or reset signal (reset by reset pin input, wdt2res signal, or low-voltage detector (lvi)). after the software stop mode has been released, the normal operation mode is restored after the oscillation stabilization time has been secured. caution the interrupt request that is disabled by setting the nmi1m, nmi0m, and intm bits of the psc register to 1 becomes invalid and software stop mode is not released. (1) releasing software stop mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal the software stop mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the software stop mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the software stop mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the software stop mode is released and that interrupt request signal is acknowledged.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 788 table 24-8. operation after releasing software stop mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address after securing the oscillation stabilization time. maskable interrupt request signal execution branches to the handler address or the next instruction is executed after securing the oscillation stabilization time. the next instruction is executed after securing the oscillation stabilization time. (2) releasing software stop mode by reset input the same operation as the normal reset operation is performed. table 24-9. operation status in software stop mode setting of software stop mode operation status item when subclock is not used when subclock is used main clock oscillator stops oscillation subclock oscillator ? oscillation enabled ring-osc generator oscillation enabled pll stops operation cpu stops operation dma stops operation interrupt controller stops operation rom correction stops operation timer p (tmp0 to tmp5) stops operation timer q (tmp0) stops operation timer m (tmm0) operable when f r /8 is selected as the count clock operable when f r /8 or f xt is selected as the count clock watch timer stops operation operable when f xt is selected as the count clock watchdog timer 2 operable when f r is selected as the count clock operable when f r or f xt is selected as the count clock csib0 to csib4 operable when sckbn input clock is selected as operation clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation serial interface uarta0 to uarta2 stops operation (but uart0 is operable when the ascka0 input clock is selected) can controller stops operation iebus controller stops operation a/d converter stops operation d/a converter stops operation real-time output function (rto) stops operation key interrupt function (kr) operable crc arithmetic circuit stops operation external bus interface see chapter 5 bus control function . port function retains status before software stop mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the software stop mode was set.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 789 24.5.3 securing oscillation stabilization time when releasing software stop mode secure the oscillation stabilization time for main clock oscillator after releasing the software stop mode because the operation of the blocks other than the main clock oscillator stops after software stop mode is set. (1) releasing software stop mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal secure the oscillation stabilization time by setting the osts register. when the releasing source is generated, the dedicated internal timer starts counting according to the osts register setting. when it overflows, the normal operation mode is restored. oscillated waveform rom circuit stopped setup time count main clock stop status interrupt request (2) release by reset this operation is the same as that of a normal reset. the oscillation stabilization time is the initial value of the osts register, 2 16 /f x .
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 790 24.7 subclock operation mode 24.7.1 setting and operation status the subclock operation mode is set by setting the ck3 bit of the pcc register to 1 in the normal operation mode. when the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. check whether the clock has been switched by using the cls bit of the pcc register. when the mck bit of the pcc register is set to 1, the operation of the main clock oscillator is stopped. as a result, the system operates only with the subclock. however, watchdog timer 2 stops counting when subclock operation is started (cls bit of pcc register = 1). (watchdog timer 2 retains the value before the subclock operation mode was set.) in the subclock operation mode, the current consumption can be reduced to a level lower than in the normal operation mode because the subclock is used as the internal system clock. in addition, the current consumption can be further reduced to the level of the software stop mode by stopping the operation of the main system clock oscillator. table 24-10 shows the operation status in subclock operation mode. caution when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits of the pcc register (using a bit manipulation instruction to manipulate the bit is recommended). for details of the pcc register, see 6.3 (1) processor clock control register (pcc). 24.7.2 releasing subclock operation mode the subclock operation mode is released by reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)) when the ck3 bit is cleared to 0. if the main clock is stopped (mck bit = 1), set the mck bit to 1, secure the oscillation stabilization time of the main clock by software, and clear the ck3 bit to 0. the normal operation mode is restored when the subclock operation mode is released. caution when manipulating the ck3 bit, do not change the set values of the ck2 to ck0 bits (using a bit manipulation instruction to manipulate the bit is recommended). for details of the pcc register, see 6.3 (1) processor clock control register (pcc).
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 791 table 24-10. operation status in subclock operation mode operation status setting of subclock operation mode item when main clock is oscillating when main clock is stopped subclock oscillator oscillation enabled ring-osc generator oscillation enabled pll operable stops operation note cpu operable dma operable interrupt controller operable rom correction operable timer p (tmp0 to tmp5) operable stops operation timer q (tmp0) operable stops operation timer m (tmm0) operable operable when f r /8 or f xt is selected as the count clock watch timer operable operable when f xt is selected as the count clock watchdog timer 2 operable operable when f r or f xt is selected as the count clock csib0 to csib4 operable operable when sckbn input clock is selected as operation clock (n = 0 to 4) i 2 c00 to i 2 c02 operable stops operation serial interface uarta0 to uarta2 operable stops operation (but uarta0 is operable when the ascka0 input clock is selected) can controller operable stops operation iebus controller operable stops operation a/d converter operable stops operation d/a converter operable stops operation real-time output function (rto) operable stops operation key interrupt function (kr) operable crc arithmetic circuit operable external bus interface see chapter 5 bus control function . port function settable internal data settable note be sure to stop the pll (pllon bit of pllctl register = 0) before stopping the main clock.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 792 24.8 sub-idle mode 24.8.1 setting and operation status the sub-idle mode is set by setting the psm1 and psm0 bits of the psmr register to 10 and setting the stp bit of the psc register to 1 in the subclock operation mode. in this mode, the clock oscillator continues operation but clock supply to the cpu, flash memory, and the other on- chip peripheral functions is stopped. as a result, program execution stops and the contents of the internal ram before the sub-idle mode was set are retained. the cpu and the other on-chip peripheral functions are stopped. however, the on-chip peripheral functions that can operate with the subclock or an external clock continue operating. because the sub-idle mode stops operation of the cpu, flash memory, and other on-chip peripheral functions, it can reduce the current consumption more than the subclock operation mode. if the sub-idle mode is set after the main clock has been stopped, the current consumption can be reduced to a level as low as that in the software stop mode. table 24-12 shows the operation status in the sub-idle mode. 24.8.2 releasing sub-idle mode the sub-idle mode is released by a non-maskable interrupt request signal (nmi pin input, intwdt2 signal), unmasked external interrupt request signal (intp0 to intp7 pin input), unmasked internal interrupt request signal from the peripheral functions operable in the sub-idle mode, or reset signal (reset by reset pin input, wdt2res signal, low-voltage detector (lvi), or clock monitor (clm)). the pll returns to the operation status before the sub- idle mode was set. when the sub-idle mode is released by an interrupt request signal, the subclock operation mode is set. if it is released by reset signal, the normal operation mode is restored. (1) releasing sub-idle mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal the sub-idle mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt request signal, regardless of the priority of the interrupt request signal. if the sub-idle mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued later is serviced as follows. caution the interrupt request signal that is disabled by setting the nmi1m, nmi0m, and intm bits of the psc register to 1 becomes invalid and sub-idle mode is not released. (a) if an interrupt request signal with a priority lower than that of the interrupt request currently being serviced is issued, only the sub-idle mode is released, and that interrupt request signal is not acknowledged. the interrupt request signal itself is retained. (b) if an interrupt request signal with a priority higher than that of the interrupt request currently being serviced is issued (including a non-maskable interrupt request signal), the sub-idle mode is released and that interrupt request signal is acknowledged.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 793 table 24-11. operation after releasing sub-idle mode by interrupt request signal release source interrupt enabled (ei) status interrupt disabled (di) status non-maskable interrupt request signal execution branches to the handler address. maskable interrupt request signal execution branches to the handler address or the next instruction is executed. the next instruction is executed. (2) releasing sub-idle mode by reset input the same operation as the normal reset operation is performed. table 24-12. operation status in sub-idle mode setting of sub-idle mode operation status item when main clock is oscillating when main clock is stopped subclock oscillator oscillation enabled ring-osc generator oscillation enabled pll operable stops operation note cpu stops operation dma stops operation interrupt controller stops operation rom correction stops operation timer p (tmp0 to tmp5) stops operation timer q (tmp0) stops operation timer m (tmm0) operable when f r /8 or f xt is selected as the count clock watch timer stops operation operable when f xt is selected as the count clock watchdog timer 2 operable when f r or f xt is selected as the count clock csib0 to csib4 operable when sckbn input clock is selected as operation clock (n = 0 to 4) i 2 c00 to i 2 c02 stops operation serial interface uarta0 to uarta2 stops operation (but uarta0 is operable when the ascka0 input clock is selected) can controller stops operation iebus controller stops operation a/d converter stops operation d/a converter stops operation real-time output function (rto) stops operation key interrupt function (kr) operable crc arithmetic circuit stops operation external bus interface see chapter 5 bus control function (same operation status as idle1, idle2 mode). port function retains status before sub-idle mode was set. internal data the cpu registers, statuses, data, and all other internal data such as the contents of the internal ram are retained as they were before the sub-idle mode was set. note be sure to stop the pll (pllon bit of pllctl register = 0) before stopping the main clock.
chapter 24 standby function preliminary user ? s manual u16541ej1v0um 794 24.9 control registers (1) power save control register (psc) the psc register is an 8-bit register that controls the standby function. the stp bit of this register is used to specify the software stop mode. this register is a special register (see 3.4.9 special registers ). data can be written to this register only in a specific sequence so that its contents are not rewritten by mistake due to a program hang-up. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 psc nmi1m nmi0m intm 0 0 stp 0 7 <6> <5> <4> 3 2 <1> 0 after reset: 00h r/w address: fffff1feh standby mode release by intwdt2 signal enabled standby mode release by intwdt2 signal disabled nmi1m 0 1 standby mode release control upon occurrence of intwdt2 signal standby mode release by nmi pin input enabled standby mode release by nmi pin input disabled nmi0m 0 1 standby mode release control by nmi pin input standby mode release by maskable interrupt request signal enabled standby mode release by maskable interrupt request signal disabled intm 0 1 standby mode release control via maskable interrupt request signal normal mode standby mode stp 0 1 standby mode note setting note standby mode by stp bit: idle1 mode, idle2 mode, software stop mode, sub-idle mode caution before setting idle1, idle2, software stop, or sub idle mode, set the psm1 and psm0 bits of the psmr register.
preliminary user?s manual u16541ej1v0um 795 chapter 25 reset functions 25.1 overview the following reset functions are available. ? reset by reset pin input ? reset by watchdog timer 2 overflow (wdt2res) ? system reset by low-voltage detector (lvi) ? system reset by clock monitor (clm) 25.2 registers to check reset source (1) reset source flag register (resf) the resf register indicates from which source a reset signal is generated. this register is read-only, in 8-bit units. reset input clears this register to 00h. the default value differs if the source of reset is other than reset. 0 wdt2rf 0 1 not generated generated resf 0 0 wdt2rf 0 0 clmrf lvirf after reset: 00h r/w address: fffff888h reset signal from wdt2 lvirf 0 1 not generated generated reset signal from lvi clmrf 0 1 not generated generated reset signal from clm note the value of this register is cleared to 00h when a reset is executed via the reset pin. when a reset is executed by the wdt2res signal, low-voltage detector (lvi), or clock monitor (clm), the reset flags of this register (wdt2rf bit, clmrf bit, and lvirf bit) are set (with the other sources retained). caution only ?0? can be written to each bit of this register. if writing ?0? conflicts with setting the flag (occurrence of reset), setting the flag takes precedence.
chapter 25 reset functions preliminary user?s manual u16541ej1v0um 796 25.3 operation 25.3.1 reset operation via reset pin when a low level is input to the reset pin, the system is reset, and each hardware unit is initialized. when the level of the reset pin is changed from low to high, the reset status is released. if the reset status is released by reset pin input, the oscillation stabilization time elapses (reset value of osts register: 2 16 /f x ) and then the cpu starts program execution. table 25-1. hardware status on reset pin input item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues ring-osc generator oscillation stops oscillation starts peripheral clock (f x to f x /1,024) operation stops operation starts after securing of oscillation stabilization time internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts after securing of oscillation stabilization time (initialized to f xx /8) cpu initialized program execution starts after securing of oscillation stabilization time watchdog timer 2 operation stops operation starts internal ram undefined if power-on reset or writing data to ram (by cpu) and reset input conflict (data is damaged). otherwise value immediately after reset input is retained note . i/o lines (ports/alternate-function pins) high impedance on-chip peripheral i/o registers initialized to specified status, ocdm register is set (01h). other on-chip peripheral functions operation stops operation can be started after securing oscillation stabilization time note the firmware of the v850es/sg2 uses part of the internal ram after the internal system reset operation has been released because it supports a boot swapping function. therefore, the contents of some ram areas are not retained on power-on reset. caution the v850es/sg2 may enter on-chip debug mode (flash memory version only) after the reset status has been released, depending on the pin status. for details, see chapter 4 port functions.
chapter 25 reset functions preliminary user ? s manual u16541ej1v0um 797 figure 25-1. timing of reset operation by reset pin input counting of oscillation stabilization time initialized to f xx /8 operation oscillation stabilization timer overflows internal system reset signal analog delay (eliminated as noise) analog delay analog delay (eliminated as noise) reset f x f clk analog delay figure 25-2. timing of power-on reset operation oscillation stabilization time count must be 2 s or longer. initialized to f xx /8 operation overflow of timer for oscillation stabilization internal system reset signal reset f x v dd f clk analog delay
chapter 25 reset functions preliminary user ? s manual u16541ej1v0um 798 25.3.2 reset operation by wdt2res signal when watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (wdt2res signal generation), a system reset is executed and the hardware is initialized to the initial status. following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay), and the reset status is then automatically released. following reset release, the cpu starts program execution after securing the oscillation stabilization time (initial value of osts register: 2 16 /f x ) of the main clock oscillator. the main clock oscillator is stopped during the reset period. table 25-2. hardware statuses during wst2res signal generation item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues ring-osc generator oscillation stops oscillation starts peripheral clock (f xx to f xx /1,024) operation stops operation starts after securing oscillation stabilization time internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu initialized program execution after securing oscillation stabilization time watchdog timer 2 operation stops operation starts after securing oscillation stabilization time internal ram undefined if power-on reset or writing data to ram (by cpu) and reset input conflict (data is damaged). otherwise value immediately after reset input is retained note . i/o lines (ports/alternate-function pins) high impedance on-chip peripheral i/o register initialized to specified status, ocdm register retains its value. on-chip peripheral functions other than above operation stops operation can be started after securing oscillation stabilization time. note the firmware of the v850es/sg2 uses part of the internal ram after the internal system reset operation has been released because it supports a boot swapping function. therefore, the contents of some ram areas are not retained on power-on reset.
chapter 25 reset functions preliminary user ? s manual u16541ej1v0um 799 figure 25-3. timing of reset operation by wdt2res signal generation counting of oscillation stabilization time initialized to f xx /8 operation oscillation stabilization timer overflow internal system reset signal wdt2res f x f clk analog delay analog delay
chapter 25 reset functions preliminary user ? s manual u16541ej1v0um 800 25.3.3 reset operation by low-voltage detector if the supply voltage falls below the voltage detected by the low-voltage detector when lvi operation is enabled, a system reset is executed (when the lvimd bit of the lvim register is set to 1), and the hardware is initialized to the initial status. the reset status lasts from when a supply voltage drop has been detected until the supply voltage rises above the lvi detection voltage detector. following reset release, the cpu starts program execution after securing the oscillation stabilization time (initial value of osts register: 2 16 /f x ) of the main clock oscillator. the main clock oscillator is stopped during the reset period. table 25-3. hardware statuses during reset operation by low-voltage detector item during reset after reset main clock oscillator (f x ) oscillation stops oscillation starts subclock oscillator (f xt ) oscillation continues ring-osc generator oscillation stops oscillation starts peripheral clock (f x to f x /1,024) operation stops operation starts after securing oscillation stabilization time internal system clock (f xx ), cpu clock (f cpu ) operation stops operation starts after securing oscillation stabilization time (initialized to f xx /8) cpu initialized program execution starts after securing oscillation stabilization time watchdog timer 2 operation stops operation starts internal ram undefined if power-on reset or writing data to ram (by cpu) and reset input conflict (data is damaged). otherwise value immediately after reset input is retained note . i/o lines (ports/alternate-function pins) high impedance on-chip peripheral i/o register initialized to specified status, ocdm register retains its value. lvi operation stops on-chip peripheral functions other than above operation stops operation can be started after securing oscillation stabilization time. note the firmware of the v850es/sg2 uses part of the internal ram after the internal system reset operation has been released because it supports a boot swapping function. therefore, the contents of some ram areas are not retained on power-on reset.
chapter 25 reset functions preliminary user ? s manual u16541ej1v0um 801 figure 25-4. timing of reset operation by low-voltage detector time supply voltage ( v dd ) lvi detection voltage internal reset signal lvi reset signal lvion
chapter 25 reset functions preliminary user ? s manual u16541ej1v0um 802 (1) low-voltage detection register (lvim) the lvim register is used to enable or disable low-voltage detection and select the operation mode. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. lvion lvion 0 1 operation disable . operation enable . lvim 0 rren 0 0 0 lvimd lvif after reset: 00h r/w address: fffff890h low-voltage detection operation enable/disable lvif 0 1 when supply voltage > detection voltage or when operation is disabled supply voltage < detection voltage low-voltage detection flag lvimd 0 1 generate interrupt request signal intlvi when supply voltage < detection voltage. generate internal reset signal lvires when supply voltage < detection voltage. selection of operation mode of low-voltage detection <7> 6 5 4 3 2 <1> <0> cautions 1. after setting the lvion bit to 1, wait for 0.1 ms (typ.) (target value) before checking the voltage using the lvif bit. 2. the value of the lvif flag is output as the signal intlvi when the lvion bit = 1 and lvimd bit = 0.
chapter 25 reset functions preliminary user ? s manual u16541ej1v0um 803 (2) low-voltage detection level select register (lvis) the lvis register is used to select the low voltage level to be detected. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 lvis0 0 1 3.0 v 0.15 v 2.85 v 0.15 v lvis 0 0 0 0 0 0 lvis0 after reset: 00h r/w address: fffff891h detection level (3) internal ram data status register (rams) the rams register is used to make the data of the internal ram valid or invalid. this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 01h. 0 valid invalid ramf 0 1 internal ram data valid/invalid rams 0 0 0 0 0 0 ramf after reset: 01h r/w address: fffff892h < >
chapter 25 reset functions preliminary user ? s manual u16541ej1v0um 804 25.3.4 clock monitor (1) function of clock monitor the clock monitor samples the main clock using the internal ring-osc and generates a reset request signal when oscillation of the main clock is stopped. once the operation of the clock monitor has been enabled by the operation enable flag, it can be stopped only by reset. the clock monitor is automatically stopped under the following conditions. ? when the oscillation stabilization time is counted after the software stop mode has been released ? when the main clock is stopped (mck bit of pcc register = 1 when subclock operates and cls bit of pcc register = 0 when main clock operates) ? when the sampling clock is stopped (ring-osc) ? when the cpu operates on ring-osc table 25-4. operation status of clock monitor (clm.clme bit = 1, with ring-osc operating) cpu operation clock operation mode main clock status ring-osc clock status clock monitor status halt mode oscillates oscillates note 1 operates note 2 idle mode oscillates oscillates note 1 operates note 2 main clock stop mode stops oscillates note 1 stops halt mode oscillates oscillates note 1 operates note 2 idle mode oscillates oscillates note 1 operates note 2 subclock (mck bit of pcc register = 0) stop mode stops oscillates note 1 stops halt mode stops oscillates note 1 stops idle mode stops oscillates note 1 stops subclock (mck bit of pcc register = 1) stop mode stops oscillates note 1 stops ring-osc clock ? stops stops note 1 stops during reset ? stops stops stops notes 1. ring-osc can be stopped by setting the rstop bit of the rcm register to 1. 2. the clock monitor is stopped when ring-osc is stopped.
chapter 25 reset functions preliminary user ? s manual u16541ej1v0um 805 (2) clock monitor mode register (clm) the clm register is used to select the operation mode of the clock monitor. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 operation of clock monitor disabled. operation of clock monitor enabled. clme 0 1 clock monitor operation enable disable clm 0 0 0 0 0 0 clme after reset: 00h r/w address: fffff870h 76 54 32 1<0> caution once the clme bit has been set to 1, it can be cleared to 0 only by reset. (3) operation of clock monitor (a) operation when main clock oscillation is stopped (clme bit = 1) if oscillation of the main clock is stopped when the clme bit = 1, an internal reset signal is generated at the timing shown in figure 25-5. figure 25-5. when oscillation of main clock is stopped 4 clocks of ring-osc clock main clock ring-osc clock internal reset signal
chapter 25 reset functions preliminary user ? s manual u16541ej1v0um 806 (b) operation in software stop mode and after software stop mode is released if the software stop mode is set when the clme bit = 1, the monitor operation is stopped in the software stop mode and while the oscillation stabilization time is being counted. the monitor operation is automatically started after the oscillation stabilization time has elapsed. figure 25-6. operation in software stop mode and after software stop mode is released clock monitor status during monitoring monitor stops during monitoring clme ring-osc clock main clock cpu operation normal operation software stop oscillation stabilization time normal operation oscillation stops oscillation stabilization time (set by osts register) (c) operation when main clock is stopped if the main clock is stopped by setting the mck bit of the pcc register to 1 while the subclock is operating (cls bit of pcc register = 1), the monitor operation is stopped until the main clock operates (cls bit of pcc register = 0). the monitor operation is automatically started when the main clock starts operating. figure 25-7. operation when main clock is stopped clock monitor status during monitoring monitor stops monitor stops during monitoring clme ring-osc clock main clock cpu operation oscillation stops subclock operation main clock operation oscillation stabilization time (set by osts register) oscillation stabilization time counted by software pccmck bit = 1 (d) operation when cpu operates on ring-osc clock (cclsf bit of ccls register = 1) the monitor operation is not started even if the clme bit is set to 1 when the cclsf bit is 1.
preliminary user?s manual u16541ej1v0um 807 chapter 26 regulator 26.1 outline the v850es/sg2 include a regulator to reduce the power consumption and noise. this regulator supplies a stepped-down v dd power supply voltage to the oscillator block and internal logic circuits (except the a/d converter, d/a converter, and output buffer). the regulator output voltage is set to 2.5 v ( 0.2 v). figure 26-1. regulator ev dd i/o buffer (normal port) 3.0 to 3.6 v bidirectional level shifter bv dd i/o buffer (external access port) 3.0 to 3.6 v regulator a/d converter 3.0 to 3.6 v d/a converter 3.0 to 3.6 v bv dd av ref0 av ref1 flmd0 v dd ev dd regc flash memory main/sub oscillator internal digital circuits 2.5 v
chapter 26 regulator preliminary user ? s manual u16541ej1v0um 808 26.2 operation the regulator of this product always operates in any mode (normal operation mode, halt mode, idle1 mode, idle2 mode, software stop mode, or during reset). be sure to connect a capacitor (4.7 f (recommended value)) to the regc pin to stabilize the regulator output. a diagram of the regulator pin connection method is shown below. figure 26-2. regc pin connection (regc = capacity) reg input voltage = 3.0 to 3.6 v voltage supply to oscillator/internal logic = 2.5 v v dd regc 4.7 f (recommended)
preliminary user?s manual u16541ej1v0um 809 chapter 27 rom correction function 27.1 overview the rom correction function is used to replace part of the program in the mask rom with the program of an external ram or the internal ram. by using this function, instruction bugs found in the mask rom can be corrected at up to four places. figure 27-1. block diagram of rom correction instruction address bus block replaced by dbtrap instruction instruction data bus rom dbtrap instruction generation block correction address register n (coradn) correction control register (corenn bit) comparator remark n = 0 to 3
chapter 27 rom correction function preliminary user ? s manual u16541ej1v0um 810 27.2 control registers (1) correction address registers 0 to 3 (corad0 to corad3) the corad0 to corad3 registers set the first address (correction address) of the instruction to be corrected in the rom. the program can be corrected at up to four places because four coradn registers are provided (n = 0 to 3). the coradn register can be read or written in 32-bit units. if the higher 16 bits of the coradn register are used as the coradnh register, and the lower 16 bits as the coradnl register, these registers can be read or written in 16-bit units. reset input clears these registers to 00000000h. because the rom capacity differs from one product to another, set the correction addresses in the following ranges. ? pd703260, 703260y, 703270, 703270y, 703280, 703280y (256 kb): 0000000h to 003ffffh ? pd703261, 703261y, 703271, 703271y, 703281, 703281y (384 kb): 0000000h to 005ffffh ? pd703262, 703262y, 703272, 703272y, 703282, 703282y (512 kb): 0000000h to 007ffffh ? pd703263, 703263y, 703273, 703273y, 703283, 703283y (640 kb): 0000000h to 009ffffh correction address fixed to 0 0 coradn (n = 0 to 3) after reset: 00000000h r/w address: corad0 fffff840h corad2 fffff848h corad1 fffff844h corad3 fffff84ch 31 17 18 1 0 correction address fixed to 0 0 coradn (n = 0 to 3) 31 18 19 1 0 correction address fixed to 0 0 coradn (n = 0 to 3) 31 19 20 1 0 (a) 256 kb (b) 384 kb, 512 kb (c) 640 kb
chapter 27 rom correction function preliminary user ? s manual u16541ej1v0um 811 (2) correction control register (corcn) the corcn register disables or enables the correction operation of each coradn register (n = 0 to 3). each channel can be enabled or disabled by this register. this register can be read or written in 8-bit or 1-bit units. reset input clears this register to 00h. 0 disabled enabled corenn 0 1 enables/disables correction operation corcn 0 0 0 coren3 coren2 coren1 coren0 after reset: 00h r/w address: fffff880h 0 1 2 3 4 5 6 7 remark n = 0 to 3 table 27-1. correspondence between corcn register bits and coradn registers corcn register bit corresponding coradn register coren3 corad3 coren2 corad2 coren1 corad1 coren0 corad0
chapter 27 rom correction function preliminary user ? s manual u16541ej1v0um 812 27.3 rom correction operation and program flow <1> if the address to be corrected and the fetch address of the internal rom match, the fetch code is replaced by the dbtrap instruction. <2> when the dbtrap instruction is executed, execution branches to address 00000060h. <3> software processing after branching causes the result of rom correction to be judged (the fetch address and rom correction operation are confirmed) and execution to branch to the correction software. <4> after the correction software has been executed, the return address is set, and return processing is started by the dbret instruction. cautions 1. the software that performs <3> and <4> must be executed in the internal rom/ram. 2. develop the program so that the rom correction function is not used until data has been completely written to the corcn register that controls rom correction. 3. when setting an address to be corrected to the coradn register, clear the higher bits to 0 in accordance with the capacity of the internal rom. 4. the rom correction function cannot be used to correct the data of the internal rom. it can only be used to correct instruction codes. if rom correction is used to correct data, that data is replaced with the dbtrap instruction code.
chapter 27 rom correction function preliminary user ? s manual u16541ej1v0um 813 figure 27-2. rom correction operation and program flow reset & start fetch address = coradn? coradn = dbpc-2? corenn bit = 1? initialize microcontroller set coradn register change fetch code to dbtrap instruction branch to rom correction judgment address branch to correction code address of corresponding channel n execute fetch code read data for setting rom correction from external memory execute dbtrap instruction jump to address 00000060h execute correction code execute dbret instruction write return address to dbpc. write value of psw to dbpsw as necessary. set corcn register yes yes yes no no remarks 1. : processing by user program (software) 2. n = 0 to 3 : processing by rom correction (hardware) load program for judgment of rom correction and correction codes execute fetch code ilgop processing no
preliminary user?s manual u16541ej1v0um 814 chapter 28 flash memory the following products are the flash memory versions of the v850es/sg2. caution there are differences in the amount of noise tolerance and noise radiation between flash memory versions and mask rom versions. when considering changing from a flash memory version to a mask rom version during the process from experimental manufacturing to mass production, make sure to sufficiently evaluate commercial samples (cs) (not engineering samples (es)) of the mask rom versions. ? pd70f3261, 70f3261y, 70f3271, 70f3271y, 70f3281, 70f3281y: 384 kb flash memory versions ? pd70f3263, 70f3263y, 70f3273, 70f3273y, 70f3283, 70f3283y: 640 kb flash memory versions in the instruction fetch to this flash memory, 4 bytes can be accessed by a single clock, the same as in the mask rom version. writing to flash memory can be performed with the memory mounted on the target system (on board). a dedicated flash programmer is connected to the target system to perform writing. the following can be considered as the development environment and the applications using a flash memory. software can be altered after the v850es/sg2 is solder-mounted on the target system. small scale production of various models is made easier by differentiating software. data adjustment in starting mass production is made easier.
chapter 28 flash memory preliminary user?s manual u16541ej1v0um 815 28.1 features 4-byte/1-clock access (in instruction fetch access) chip erase/block unit erase communication via serial interface with the dedicated flash programmer erase/write voltage: can be erased/written with a single power supply (flmd0 = v dd , flmd1 = v ss ). on-board programming flash memory programming by self-writing 28.1.1 erasure unit the erasure units for 384/640 kb flash memory versions are shown below. (1) chip erase the area of xx000000h to xx05ffffh and xx000000 to xx09ffffh can be erased at the same time. (2) block erase erasure can be performed in block units (28 kb 4, 4 kb 4, 64 kb 8 note ). block 0: 28 kb block 1: 28 kb block 2: 28 kb block 3: 28 kb block 4: 8 kb block 5: 8 kb block 6: 8 kb block 7: 8 kb block 8: 64 kb block 9: 64 kb block 10: 64 kb block 11: 64 kb block 12: 64 kb block 13: 64 kb block 14: 64 kb block 15: 64 kb note 384 kb ( pd70f3261, 70f3261y, 70f3271, 70f3271y, 70f3281, and 70f3281y) are divided into four blocks, 8 to 11.
chapter 28 flash memory preliminary user?s manual u16541ej1v0um 816 28.2 writing with flash programmer writing can be performed either on-board or off-board with the dedicated flash programmer. (1) on-board programming the contents of the flash memory are rewritten after the v850es/sg2 is mounted on the target system. mount connectors, etc., on the target system to connect the dedicated flash programmer. (2) off-board programming writing to flash memory is performed by a dedicated program adapter (fa series), etc., before mounting the v850es/sg2 on the target system. remark fa series is a product of naito densei machida mfg. co., ltd. 28.3 programming environment the following shows the environment required for writing programs to the flash memory of v850es/sg2. figure 28-1. environment required for writing programs to flash memory host machine rs-232c dedicated flash programmer v850es/sg2 flmd0 v dd v ss reset uarta/csib pg-fp4 (f la s h p ro 4 ) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve a host machine is required for controlling the dedicated flash programmer. uarta0 or csib0 is used for the interface between the dedicated flash programmer and the v850es/sg2 to perform writing, erasing, etc. a dedicated program adapter (fa series) required for off-board writing.
chapter 28 flash memory preliminary user ? s manual u16541ej1v0um 817 28.4 communication mode the communication between the dedicated flash programmer and the v850es/sg2 is performed by serial communication using uarta0 or csib0 of the v850es/sg2. (1) uarta0 transfer rate: 4,800 to 76,800 bps figure 28-2. communication with dedicated flash programmer (uarta0) dedicated flash programmer v850es/sg2 v dd v ss reset txda0 rxda0 flmd0, flmd1 flmd0 v dd gnd reset rxd txd pg-fp4 (f la s h p ro 4 ) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve (2) csib0 serial clock: up to 1 mhz (msb first) figure 28-3. communication with dedicated flash programmer (csib0) dedicated flash programmer v850es/sg2 flmd0 v dd v ss reset sob0 sib0 sckb0 flmd0, flmd1 v dd gnd reset si so sck pg-fp4 (f las h p ro 4 ) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve
chapter 28 flash memory preliminary user ? s manual u16541ej1v0um 818 (3) csib0 + + + + hs serial clock: up to 1 mhz (msb first) figure 28-4. communication with dedicated flash programmer (csib0 + + + + hs) dedicated flash programmer v850es/sg2 v dd v ss reset sob0 sib0 sckb0 pcm0 v dd flmd0 flmd0 gnd reset si so sck hs pg-fp4 (f la sh p ro 4 ) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve the dedicated flash programmer outputs the transfer clock, and the v850es/sg2 operate as slaves. when the pg-fp4 is used as the dedicated flash programmer, it generates the following signals to the v850es/sg2. for details, refer to the pg-fp4 manual. table 28-1. signal generation of dedicated flash programmer (pg-fp4) pg-fp4 v850es/sg2 connection handling signal name i/o pin function pin name csib0 uarta0 csib0 + hs flmd0 output writing enable/disable flmd0 v dd i/o v dd voltage generation/ voltage monitoring v dd gnd ? ground v ss clk output clock output to v850es/sg2 x1 reset output reset signal reset si/rxd input receive signal sob0/txda0 so/txd output transmit signal sib0/rxda0 sck output transfer clock sckb0 hs input handshake signal of csib0 + hs pcm0 remark : always connected : does not need to be connected
chapter 28 flash memory preliminary user ? s manual u16541ej1v0um 819 28.5 pin connection when performing on-board writing, mount a connector on the target system to connect to the dedicated flash programmer. also, incorporate a function on-board to switch from the normal operation mode to the flash memory programming mode. when switched to the flash memory programming mode, all the pins not used for flash memory programming become the same status as that immediately after reset. therefore, all the ports enter the output high-impedance status, so that pin handling is required when the external device does not acknowledge the output high-impedance status. 28.5.1 flmd0 pin in the normal operation mode, 0 v is input to the flmd0 pin. in the flash memory programming mode, the v dd write voltage is supplied to the flmd0 pin. the following shows an example of the connection of the flmd0 pin. figure 28-5. flmd0 pin connection example v850es/sg2 flmd0 dedicated flash programmer connection pin pull-down resistor (r flmd0 )
chapter 28 flash memory preliminary user ? s manual u16541ej1v0um 820 28.5.2 flmd1 pin when 0 v is input to the flmd0 pin, the flmd1 pin does not function. when v dd is supplied to the flmd0 pin, the flash memory programming mode is entered, so 0 v must be input to the flmd1 pin. an flmd1 pin connection example is shown below. figure 28-6. flmd1 pin connection example flmd1 pull-down resistor (r flmd1 ) other device v850es/sg2 caution if the v dd signal is input to the flmd1 pin from another device during on-board writing and immediately after reset, isolate this signal. table 28-2. relationship of operation mode of flmd0 and flmd1 pins flmd0 flmd1 operation mode 0 normal operation mode v dd 0 flash memory programming mode v dd v dd setting prohibited
chapter 28 flash memory preliminary user ? s manual u16541ej1v0um 821 28.5.3 serial interface pin the following shows the pins used by each serial interface. table 28-3. pins used by serial interfaces serial interface pins used csib0 sob0, sib0, sckb0 csib0 + hs sob0, sib0, sckb0, pcm0 uarta0 txda0, rxda0 when connecting a dedicated flash programmer to a serial interface pin that is connected to another device on- board, care should be taken to avoid conflict of signals and malfunction of the other device. (1) conflict of signals when the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. figure 28-7. conflict of signals (serial interface input pin) v850es/sg2 input pin conflict of signals dedicated flash programmer connection pins other device output pin in the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals another device outputs. therefore, isolate the signals on the other device side.
chapter 28 flash memory preliminary user ? s manual u16541ej1v0um 822 (2) malfunction of other device when the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), the signal is output to the other device, causing the device to malfunction. to avoid this, isolate the connection to the other device or make the setting so that the input signal to the other device is ignored. figure 28-8. malfunction of other device v850es/sg2 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the v850es/sg2 outputs affects the other device, isolate the signal on the other device side. v850es/sg2 pin dedicated flash programmer connection pin other device input pin in the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side.
chapter 28 flash memory preliminary user ? s manual u16541ej1v0um 823 28.5.4 reset pin when the reset signals of the dedicated flash programmer are connected to the reset pin that is connected to the reset signal generator on-board, a conflict of signals occurs. to avoid the conflict of signals, isolate the connection to the reset signal generator. when a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. therefore, do not input signals other than the reset signals from the dedicated flash programmer. figure 28-9. conflict of signals (reset pin) v850es/sg2 reset dedicated flash programmer connection pin reset signal generator conflict of signals output pin in the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. therefore, isolate the signals on the reset signal generator side. 28.5.5 port pins (including nmi) when the flash memory programming mode is set, all the port pins except the pins that communicate with the dedicated flash programmer enter the output high-impedance status. if problems such as disabling output high- impedance status should occur in the external devices connected to the port, connect the port pins to v dd or v ss via resistors. 28.5.6 other signal pins connect x1, x2, xt1, and xt2 to the same status as that in the normal operation mode. 28.5.7 power supply supply the same power (v dd , v ss , ev dd , ev ss , av ss , bv dd , bv ss , av ref0 , av ref1 ) as in normal operation mode.
chapter 28 flash memory preliminary user ? s manual u16541ej1v0um 824 28.6 programming method 28.6.1 flash memory control the following shows the procedure for manipulating the flash memory. figure 28-10. procedure for manipulating flash memory start select communication system manipulate flash memory end? yes supplies reset pulse no end switch to flash memory programming mode
chapter 28 flash memory preliminary user ? s manual u16541ej1v0um 825 28.6.2 flash memory programming mode when rewriting the contents of flash memory using the dedicated flash programmer, set the v850es/sg2 to the flash memory programming mode. when switching modes, set the flmd0 and flmd1 pins before releasing reset. when performing on-board writing, change modes using a jumper, etc. figure 28-11. flash memory programming mode v dd v dd reset (input) flmd1 (input) flmd0 (input) rxda0 (input) txda0 (output) 0 v v dd 0 v v dd 0 v v dd 0 v v dd 0 v v dd 0 v (note) power on oscillation stabilized communication mode selected flash control command communication (erasure, write, etc.) reset cleared note the number of clocks to be inserted differs depending on the communication mode. for details, see table 28-4 .
chapter 28 flash memory preliminary user ? s manual u16541ej1v0um 826 28.6.3 selection of communication mode in the v850es/sg2, the communication mode is selected by inputting pulses (12 pulses max.) to the flmd0 pin after switching to the flash memory programming mode. the flmd0 pulse is generated by the dedicated flash programmer. the following shows the relationship between the number of pulses and the communication mode. table 28-4. list of communication modes flmd0 pulse communication mode remarks 8 csib0 v850es/sg2 perform slave operation, msb first 11 csib0 + hs v850es/sg2 perform slave operation, msb first 9 csib3 v850es/sg2 perform slave operation, msb first 12 csib3 + hs v850es/sg2 perform slave operation, msb first 0 uarta0 communication rate: 9,600 bps (at reset), lsb first others rfu setting prohibited caution when uarta is selected, the receive clock is calculated based on the reset command sent from the dedicated flash programmer after receiving the flmd0 pulse.
chapter 28 flash memory preliminary user ? s manual u16541ej1v0um 827 28.6.4 communication command the v850es/sg2 communicate with the dedicated flash programmer by means of commands. the command sent from the dedicated flash programmer to the v850es/sg2 is called a ? command ? . the response signal sent from the v850es/sg2 to the dedicated flash programmer is called a ? response command ? . figure 28-12. communication command dedicated flash programmer v850es/sg2 command response command pg-fp4 (flash pro4) cxxxxxx bxxxxx axxxx x x x y y y x x x x x x x x x x x x x x x x x x x y y y y statve the following shows the commands for flash memory control of the v850es/sg2. all of these commands are issued from the dedicated flash programmer, and the v850es/sg2 perform the various processing corresponding to the commands. table 28-5. flash memory control command support category command name csib csib + hs uarta function blank check block blank check command ?? checks the erase state of the entire memory. chip erase command ?? erases the contents of the entire memory. erase block erase command ?? erases the contents of the specified block memory. write write command ?? writes data according to the specification of the write address and the number of bytes to be written, and executes a verify check. verify verify command ?? compares the contents of the entire memory and the input data. reset command ?? escapes from each state. oscillating frequency setting command ?? sets the oscillation frequency. baud rate setting command ?? sets the baud rate when using uart. silicon signature command ?? reads the silicon signature information. version acquisition command ?? reads the version information of the device. status command ?? acquires the operation status. system setting and control security setting command ?? erases chip and blocks, and sets security of write. the v850es/sg2 return response commands to the commands issued from the dedicated flash programmer. the following shows the response commands returned by the v850es/sg2. table 28-6. response commands response command name function ack acknowledges command/data, etc. nak acknowledges illegal command/data, etc.

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