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? 2005 microchip technology inc. ds21930a-page 1 24aa00/24lc00/24c00 24aa01/24lc01b 24aa014/24lc014 24c01c 24aa02/24lc02b 24c02c 24aa024/24lc024 24aa025/24lc025 24aa04/24lc04b 24aa08/24lc08b 24aa16/24lc16b 24aa32a/24lc32a 24aa64/24lc64 24aa128/24lc128/24fc128 24aa256/24lc256/24fc256 24aa512/24lc512/24fc512 features: ? 128-bit through 512 kbit devices ? single-supply with operation down to 1.8v for 24aaxx devices ? low-power cmos technology: - 1 ma active current typical -1 a standby current typical (i-temp) ? 2-wire serial interface bus, i 2 c? compatible ? schmitt trigger inputs for noise suppression ? output slope control to eliminate ground bounce ? 100 khz (1.8v) and 400 khz ( 2.5v) compatibility ? 1 mhz for 24fcxx products ? self-timed write cycl e (including auto-erase) ? page write buffer ? hardware write-protect av ailable on most devices ? factory programming (qtp) available ? esd protection > 4,000v ? 1 million erase/write cycles ? data retention > 200 years ? 8-lead pdip, soic, ts sop and msop packages ? 5-lead sot-23 package (most 1-16 kbit devices) ? 8-lead 2x3mm and 5x6mm dfn packages available ? available for extend ed temperature ranges: - industrial (i): -40c to +85c - automotive (e): -40c to +125c description: the microchip technology inc. 24cxx, 24lcxx, 24aaxx and 24fcxx (24xx*) devices are a family of 128-bit through 512 kbit electrically erased proms. the devices are organized in blocks of x8-bit memory with 2-wire serial inte rfaces. low voltage design permits operation down to 1.8v (for 24aaxx devices), with standby and active currents of only 1 a and 1 ma, respectively. devices 1 kbit and larger have page write capability. parts havin g functional address lines allow connection of up to 8 devices on the same bus. the 24xx family is available in the standard 8-pin pdip, surface mount soic, tssop and msop pack- ages. most 128-bit throug h 16 kbit devices are also available in the 5-lead sot-23 package. dfn packages (2x3mm or 5x6mm) are also available. all packages are available in a pb-free (matte tin) finish. package types (1) a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp (3) scl sda pdip/soic a0 a1 a2 v ss 1 2 3 4 8 7 6 5 v cc wp (3) scl sda tssop/msop (2) nc a0 a1 nc a2 v ss nc nc v cc wp nc scl sda nc 1 2 3 4 14 13 12 11 5 10 6 9 7 8 tssop 15 4 3 scl v ss sda v cc nc 2 sot-23-5 (24xx00) sot-23-5 15 4 3 scl v ss sda wp v cc 2 (all except 24xx00) a0 a1 a2 v ss wp (3) scl sda 5 6 7 8 4 3 2 1 v cc dfn note 1: pins a0, a1, a2 and wp are not used by some devices (no internal connections). see table 1-1, device selection table, for details. 2: pins a0 and a1 are no-connects for the 24xx128 and 24xx256 msop devices. 3: pin 7 is ?not used? for 24xx00, 24xx025 and 24c01c. i 2 c ? serial eeprom family data sheet *24xx is used in this document as a generic part number fo r 24 series devices in this data sheet. 24xx64, for example, represents all voltages of the 64 kbit device.
24aaxx/24lcxx/24fcxx ds21930a-page 2 ? 2005 microchip technology inc. table 1-1: device selection table part number v cc range max clock frequency page size write- protect scheme functional address pins temp range packages (5) 128-bit devices 24aa00 1.8-5.5v 400 khz (1) ? none none c, i p, sn, st, ot, mc 24lc00 2.5-5.5v 400 khz (1) c, i 24c00 4.5-5.5v 400 khz c, i, e 1 kb devices 24aa01 1.8-5.5v 400 khz (2) 8 bytes entire array none i p, sn, st, ms, ot, mc 24lc01b 2.5-5.5v 400 khz i, e 24aa014 1.8-5.5v 400 khz (2) 16 bytes entire array a0, a1, a2 i p, sn, st, ms, mc 24lc014 2.5-5.5v 400 khz i 24c01c 4.5v-5.5v 400 khz 16 bytes none a0, a1, a2 c, i, e p, sn, st, mc 2 kb devices 24aa02 1.8-5.5v 400 khz (2) 8 bytes entire array none i p, sn, st, ms, ot, mc 24lc02b 2.5-5.5v 400 khz i, e 24aa024 1.8-5.5v 400 khz (2) 16 bytes entire array a0, a1, a2 i p, sn, st, ms, mc 24lc024 2.5-5.5v 400 khz i 24aa025 1.8-5.5v 400 khz (2) 16 bytes none a0, a1, a2 i p, sn, st,ms, mc 24lc025 2.5-5.5v 400 khz i 24c02c 4.5-5.5v 400 khz 16 bytes upper half of array a0, a1, a2 c, i, e p, sn, st, mc 4 kb devices 24aa04 1.8-5.5v 400 khz (2) 16 bytes entire array none i p, sn, st, ms, ot, mc 24lc04b 2.5-5.5v 400 khz i, e 8 kb devices 24aa08 1.8-5.5v 400 khz (2) 16 bytes entire array none i p, sn, st, ms, ot, mc 24lc08b 2.5-5.5v 400 khz i, e 16 kb devices 24aa16 1.8-5.5v 400 khz (2) 16 bytes entire array none i p, sn, st, ms, ot, mc 24lc16b 2.5-5.5v 400 khz i, e 32 kb devices 24aa32a 1.8-5.5v 400 khz (2) 32 bytes entire array a0, a1, a2 i p, sn, sm, st, ms, mc 24lc32a 2.5-5.5v 400 khz i, e 64 kb devices 24aa64 1.8-5.5v 400 khz (2) 32 bytes entire array a0, a1, a2 i p, sn, sm, st, ms, mc 24lc64 2.5-5.5v 400 khz i, e note 1: 100 khz for v cc <4.5v. 2: 100 khz for v cc <2.5v. 3: 400 khz for v cc <2.5v 4: pins a0 and a1 are no-connects for the 24xx128 and 24xx256 in the msop package. 5: p = 8-pdip, sn = 8-soic (150 mil jedec), st = 8- tssop, ot = 5 or 6-sot23, mc = 2x3mm dfn, ms = 8-msop, sm = 8-soic (200 mil eiaj) , mf = 5x6mm dfn, st14 = 14-tssop.
? 2005 microchip technology inc. ds21930a-page 3 24aaxx/24lcxx/24fcxx 128 kb devices 24aa128 1.8-5.5v 400 khz (2) 64 bytes entire array a0, a1, a2 (4) i p, sn, sm, st, ms, mf, st14 24lc128 2.5-5.5v 400 khz i, e 24fc128 1.8-5.5v 1 mhz (3) i 256 kb devices 24aa256 1.8-5.5v 400 khz (2) 64 bytes entire array a0, a1, a2 (4) i p, sn, sm, st, ms, mf, st14 24lc256 2.5-5.5v 400 khz i, e 24fc256 1.8-5.5v 1 mhz (3) i 512 kb devices 24aa512 1.8-5.5v 400 khz (2) 128 bytes entire array a0, a1, a2 i p, sm, mf, st14 24lc512 2.5-5.5v 400 khz i, e 24fc512 1.8-5.5v (3) 1 mhz i table 1-1: device selection table (continued) part number v cc range max clock frequency page size write- protect scheme functional address pins temp range packages (5) note 1: 100 khz for v cc <4.5v. 2: 100 khz for v cc <2.5v. 3: 400 khz for v cc <2.5v 4: pins a0 and a1 are no-connects for the 24xx128 and 24xx256 in the msop package. 5: p = 8-pdip, sn = 8-soic (150 mil jedec), st = 8-tssop, ot = 5 or 6-sot23, mc = 2x3mm dfn, ms = 8-msop, sm = 8-soic (200 mil eiaj ), mf = 5x6mm dfn, st14 = 14-tssop.
24aaxx/24lcxx/24fcxx ds21930a-page 4 ? 2005 microchip technology inc. 2.0 electrical characteristics absolute maximum ratings (?) v cc ......................................... .............................................. ........................................ ..............................................6.5v all inputs and outputs w.r.t. v ss ..................................... .................................. .................................. -0.6v to v cc +1.0v storage temperature .......................... ............................................. ..................................... ...................-65c to +150c ambient temperature with power appli ed .............................................. ........................................... .......-40c to +125c esd protection on all pins .......................... ............................ ........................... ........................ ...................... ....................... 4kv table 2-1: dc characteristics ? notice: stresses above those l isted under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating on ly and functional operation of the device at those or any other conditions above those indicated in the operationa l listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics electrical characteristics: commercial (c): v cc = +1.8v to 5.5v t a = 0c to +70c industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions d1 ? a0, a1, a2, scl, sda and wp pins: ???? d2 v ih high-level input voltage 0.7 v cc ?v? d3 v il low-level input voltage ? 0.3 v cc 0.2 v cc v v v cc 2.5v v cc < 2.5v d4 v hys hysteresis of schmitt trigger inputs (sda, scl pins) 0.05 v cc ?v (note 1) d5 v ol low-level output voltage ? 0.40 v i ol = 3.0 ma @ v cc = 2.5v d6 i li input leakage current ? 1 av in = v ss or v cc d7 i lo output leakage current ? 1 av out = v ss or v cc d8 c in , c out pin capacitance (all inputs/outputs) ?10pfv cc = 5.0v (note 1) t a = 25c, f clk = 1 mhz d9 i cc read operating current ? 400 1 a ma 24xx128, 256, 512: v cc = 5.5v, scl = 400 khz all except 24xx128, 256, 512: v cc = 5.5v, scl = 400 khz i cc write ? 3 5 ma ma v cc = 5.5v, all except 24xx512 v cc = 5.5v, 24xx512 d10 i ccs standby current ? 1 at a = -40c to +85c scl = sda = v cc = 5.5v a0, a1, a2, wp = v ss or v cc ?5 at a = -40c to 125c scl = sda = v cc = 5.5v a0, a1, a2, wp = v ss or v cc ?50 a 24c01c and 24c02c only scl = sda = v cc = 5.5v a0, a1, a2, wp = v ss or v cc note 1: this parameter is periodically sampled and not 100% tested.
? 2005 microchip technology inc. ds21930a-page 5 24aaxx/24lcxx/24fcxx table 2-2: ac characteristics ? all except 24xx00, 24c01c and 24c02c ac characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions 1f clk clock frequency ? ? ? ? 100 400 400 1000 khz 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fcxxx 2.5v v cc 5.5v 24fcxxx 2t high clock high time 4000 600 600 500 ? ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fcxxx 2.5v v cc 5.5v 24fcxxx 3t low clock low time 4700 1300 1300 500 ? ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fcxxx 2.5v v cc 5.5v 24fcxxx 4t r sda and scl rise time (note 1) ? ? ? 1000 300 300 ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc 5.5v 24fcxxx 5t f sda and scl fall time (note 1) ? ? 300 100 ns all except 24fcxxx 1.8v v cc 5.5v 24fcxxx 6t hd : sta start condition hold time 4000 600 600 250 ? ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fcxxx 2.5v v cc 5.5v 24fcxxx 7t su : sta start condition setup time 4700 600 600 250 ? ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fcxxx 2.5v v cc 5.5v 24fcxxx 8t hd : dat data input hold time 0 ? ns (note 2) 9t su : dat data input setup time 250 100 100 ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc 5.5v 24fcxxx 10 t su : sto stop condition setup time 4000 600 600 250 ? ? ? ? ns 1.8 v v cc < 2.5v 2.5 v v cc 5.5v 1.8v v cc < 2.5v 24fcxxx 2.5 v v cc 5.5v 24fcxxx 11 t su : wp wp setup time 4000 600 600 ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc 5.5v 24fcxxx 12 t hd : wp wp hold time 4700 1300 1300 ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc 5.5v 24fcxxx note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the fa lling edge of scl to avoid unintended generation of start or stop conditions. 3: this parameter is not tested but ensured by charac terization. for e ndurance estimates in a specific application, please consult the to tal endurance? model, which can be obtained from microchip?s web site: www.microchip.com. 4: 24fcxxx denotes the 24fc128, 24fc256 and 24fc512 devices.
24aaxx/24lcxx/24fcxx ds21930a-page 6 ? 2005 microchip technology inc. 13 t aa output valid from clock (note 2) ? ? ? ? 3500 900 900 400 ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fcxxx 2.5v v cc 5.5v 24fcxxx 14 t buf bus free time: time the bus must be free before a new transmission can start 4700 1300 1300 500 ? ? ? ? ns 1.8v v cc < 2.5v 2.5v v cc 5.5v 1.8v v cc < 2.5v 24fcxxx 2.5v v cc 5.5v 24fcxxx 15 t of output fall time from v ih minimum to v il maximum c b 100 pf 10 + 0.1c b 250 250 ns all except 24fcxxx (note 1) 24fcxxx (note 1) 16 t sp input filter spike suppression (sda and scl pins) ? 50 ns all except 24fcxxx (note 1) 17 t wc write cycle time (byte or page) ?5ms 18 ? endurance 1,000,000 ? cycles 25c (note 3) table 2-2: ac characteristics ? all except 24xx00, 24c01c and 24c02c (continued) ac characteristics electrical characteristics: industrial (i): v cc = +1.8v to 5.5v t a = -40c to +85c automotive (e): v cc = +2.5v to 5.5v t a = -40c to 125c param. no. sym. characteristic min. max. units conditions note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to br idge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generat ion of start or stop conditions. 3: this parameter is not tested but ensured by charac terization. for endurance estimates in a specific application, please consult the tota l endurance? model, which can be ob tained from microchip?s web site: www.microchip.com. 4: 24fcxxx denotes the 24fc128, 24fc256 and 24fc512 devices.
? 2005 microchip technology inc. ds21930a-page 7 24aaxx/24lcxx/24fcxx table 2-3: ac characteristics ? 24xx00, 24c01c and 24c02c all parameters apply across all recommended operating ranges unless otherwise noted commercial (c): t a = 0c to +70c, v cc = 1.8v to 5.5v industrial (i): t a = -40c to +85c, v cc = 1.8v to 5.5v automotive (e): t a = -40c to +125c, v cc = 4.5v to 5.5v parameter symbol min max units conditions clock frequency f clk ? ? ? 100 100 400 khz 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 5.5v clock high time t high 4000 4000 600 ? ? ? ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 5.5v clock low time t low 4700 4700 1300 ? ? ? ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 5.5v sda and scl rise time (note 1) t r ? ? ? 1000 1000 300 ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 5.5v sda and scl fall time t f ?300ns (note 1) start condition hold time t hd : sta 4000 4000 600 ? ? ? ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 5.5v start condition setup time t su : sta 4700 4700 600 ? ? ? ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 5.5v data input hold time t hd : dat 0?ns (note 2) data input setup time t su : dat 250 250 100 ? ? ? ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 5.5v stop condition setup time t su : sto 4000 4000 600 ? ? ? ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 5.5v output valid from clock (note 2) t aa ? ? ? 3500 3500 900 ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 5.5v bus free time: time the bus must be free before a new transmis- sion can start t buf 4700 4700 1300 ? ? ? ns 4.5v vcc 5.5v (e temp range) 1.8v vcc 4.5v 4.5v vcc 5.5v output fall time from v ih minimum to v il maximum t of 20+0.1 cb 250 ns (note 1) , cb 100 pf input filter spike suppression (sda and scl pins) t sp ?50ns (note 1) write cycle time t wc ?4 1.5 ms 24xx00 24c01c, 24c02c endurance 1,000,000 ? cycles (note 3) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to br idge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended gener ation of start or stop conditions. 3: this parameter is not tested but ensured by charac terization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained at www.microchip.com.
24aaxx/24lcxx/24fcxx ds21930a-page 8 ? 2005 microchip technology inc. figure 2-1: bus timing data (unprotected) (protected) scl sda in sda out wp 5 7 6 16 3 2 89 13 d4 4 10 11 12 14
? 2005 microchip technology inc. ds21930a-page 9 24aaxx/24lcxx/24fcxx 3.0 pin descriptions the descriptions of the pins are listed in table 3-1. table 3-1: pin function table 3.1 a0, a1, a2 chip address inputs the a0, a1 and a2 pins are not used by the 24xx01 through 24xx16 devices. the a0, a1 and a2 inputs are used by the 24c01c, 24c02c, 24xx014, 24xx024, 24xx025 and the 24xx32 through 24xx512 fo r multiple device opera- tions. the levels on these in puts are compared with the corresponding bits in the slave address. the chip is selected if the compare is true. for the 24xx128 and 24xx2 56 in the msop package only, pins a0 and a1 are not connected. up to eight devices (two for the 24xx128 and 24xx256 msop package) ma y be connected to the same bus by using diff erent chip select bit combinations. in most applications, the ch ip address inputs a0, a1 and a2 are hard-wired to logic ? 0 ? or logic ? 1 ?. for applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ? 0 ? or logic ? 1 ? before normal device operation can proceed. 3.2 serial data (sda) this is a bidirectional pin us ed to transfer addresses and data into and out of t he device. it is an open drain terminal. therefore, the sda bus requires a pull-up resistor to v cc (typical 10 k for 100khz, 2k for 400 khz and 1 mhz). for normal data transfer, sda is allowed to change only during scl low. changes during scl high are reserved for indicating t he start and stop conditions. 3.3 serial clock (scl) this input is used to synchronize the data transfer to and from the device. 3.4 write-protect (wp) this pin must be connected to either v ss or v cc . if tied to v ss , write operations are enabled. if tied to v cc , write operations are inhibited but read operations are not affected. see table 1-1 for the write-protect scheme of each device. 3.5 power supply (v cc ) a v cc threshold detect circuit is employed which disables the internal erase/write logic if v cc is below 1.5v at nominal conditions. for the 24c00, 24c01c and 24c02c devices, the erase/write logic is disabled below 3.8v at nominal conditions. pin name 8-pin pdip and soic 8-pin tssop and msop 5-pin sot-23 24xx00 5-pin sot-23 all except 24xx00 14-pin tssop 8-pin 5x6 dfn and 2x3 dfn function a0 1 1 (1) ? ? 1 1 user configurable chip select (3) a1 2 2 (1) ??22 user configurable chip select (3) a2 3 3 ? ? 6 3 user configurable chip select (3) v ss 4 4 2 2 7 4 ground sda 5 5 3 3 8 5 serial data scl 6 6 1 1 9 6 serial clock (nc) ? ? 4 ? 3, 4, 5, 10, 11, 12 ? not connected wp 7 (2) 7 (2) ? 5 13 7 write-protect input v cc 8 8 5 4 14 8 power supply note 1: pins 1 and 2 are not connected for the 24xx128 and 24xx256 msop packages. 2: pin 7 is not used for 24xx00, 24xx025 and 24c01c. 3: pins a0, a1 and a2 are not used by some devices (no internal connections). see table 1-1 for details.
24aaxx/24lcxx/24fcxx ds21930a-page 10 ? 2005 microchip technology inc. 4.0 functional description each 24xx device supports a bidirectional, 2-wire bus and data transmission prot ocol. a device that sends data onto the bus is defined as a transmitter, while a device receiving data is defin ed as a receiver. the bus has to be controlled by a master device which gener- ates the serial clock (scl ), controls the bus access and generates the start and stop conditions, while the 24xx works as slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. block diagram hv generator eeprom array page latches* ydec xdec sense amp. r/w control m emory c ontrol l ogic i/o c ontrol l ogic i/o a0*a1*a2* sda scl v cc v ss wp* * a0, a1, a2, wp and page latches are not used by some devices. see table 1-1, device selection table, for details.
? 2005 microchip technology inc. ds21930a-page 11 24aaxx/24lcxx/24fcxx 5.0 bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clo ck line is high will be interpreted as a start or stop condition. accordingly, the following bus conditions have been defined (figure 5-1). 5.1 bus not busy (a) both data and clock lines remain high. 5.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 5.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 5.4 data valid (d) the state of the data line represents valid data when, after a start condition, th e data line is stable for the duration of the high pe riod of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop cond ition. the number of data bytes transferred between st art and stop conditions is determined by the master device.
24aaxx/24lcxx/24fcxx ds21930a-page 12 ? 2005 microchip technology inc. 5.5 acknowledge each receiving device, when a ddressed, is obliged to generate an acknowledge a fter the reception of each byte. the master device mu st generate an extra clock pulse which is associated wi th this acknowledge bit. the device that acknowledg es has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. during reads, a master must signal an end-of- data to the slave by not g enerating an acknowledge bit on the last byte that has be en clocked out of the slave. in this case, the slave (24xx) will leave the data line high to enable the master to generate the stop condition (figure 5-2). figure 5-1: data transfer sequence on the serial bus figure 5-2: acknowledge timing note: during a write cycle, the 24xx will not acknowledge commands. scl sda (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition scl 9 8 7 6 5 4 3 2 1123 transmitter must release th e sda line at this point, allowing the receiver to pull the sda line low to acknowledge the previous eight bits of data. receiver must release the sda line at this point so the transmitter can continue sending data. data from transmitter sda acknowledge bit data from transmitter
? 2005 microchip technology inc. ds21930a-page 13 24aaxx/24lcxx/24fcxx 5.6 device addressing for devices without functional address pins a control byte is the first byte received following the start condition from the master device (figure 5-3). the control byte begins with a four-bit control code. for the 24xx, this is set as ? 1010 ? binary for read and write operations. the next three bits of the control byte are the block-select bits (b2, b1 , b0). they are used by the master device to select whic h of the 256-word blocks of memory are to be accessed. t hese bits are in effect the three most significant bits of the word address. note that b2, b1 and b0 are ?don? t care? for the 24xx00, the 24xx01 and 24xx02. b2 and b1 are ?don?t care? for the 24xx04. b2 is ?don? t care? for the 24xx08. the last bit of the control byte defines the operation to be performed. when set to ? 1 ?, a read operation is selected. when set to ? 0 ? a write operation is selected. following the start condition, the 24xx monitors the sda bus. upon receiving a ? 1010 ? code, the block select bits and the r/w bit, the slave device outputs an acknowledge signal on the sda line. the address byte follows the acknowledge. figure 5-3: control and address byte assignments for devices without address pins s 1010xxx r/w ack s 1010xxx r/w ack s 1010xxx r/w ack s 1010xx b0 r/w ack s 1010x b1 b0 r/w ack s 1010 b2 b1 b0 r/w ack 24xx01 24xx02 24xx04 24xx08 24xx016 x = ?don?t care? bit acknowledge control code start bit control byte block select bits address byte 24xx00 read/write bit (read = 1 , write = 0 ) xxxx a3 . . a0 x a6 . . . . . a0 a7 . . . . . . a0 a7 . . . . . . a0 a7 . . . . . . a0 a7 . . . . . . a0 bit
24aaxx/24lcxx/24fcxx ds21930a-page 14 ? 2005 microchip technology inc. 5.7 device addressing for devices with functional address pins a control byte is the first byte received following the start condition from the master device (figure 5-4). the control byte begins with a 4-bit control code. for the 24xx, this is set as ? 1010 ? binary for read and write operations. the next three bits of the control byte are the chip select bits (a2, a1 , a0). the chip select bits allow the use of up to eight 24xx devices on the same bus and are used to select which device is accessed. the chip select bits in the control byte must corre- spond to the logic levels on the corresponding a2, a1 and a0 pins for the device to respond. these bits are, in effect, the three most significant bits of the word address. for 24xx128 and 24xx256 in the msop package, the a0 and a1 pins are not connected. during device addressing, the a0 and a1 chip select bits (figure 5-4) should be set to ? 0 ?. only two 24xx128 or 24xx256 msop packages can be con nected to the same bus. the last bit of the control byte defines the operation to be performed. when set to a ? 1 ?, a read operation is selected. when set to a ? 0 ?, a write operation is selected. for higher density de vices (24xx32 through 24xx512), the next two bytes received define the address of the first data by te. depending on the prod- uct density, not all bits in the address high byte are used. a15, a14, a13 and a12 are ?don?t care? for 24xx32. a15, a14 and a1 3 are ?don?t care? for 24xx64. a15 and a14 are ?d on?t care? for 24xx128. a15 is ?don?t care? for 24xx256. all address bits are used for the 24xx512. the upper address bits are transferred first, followed by the less significant bits. following the start conditi on, the 24xx monitors the sda bus. upon receiving a ? 1010 ? code, appropriate device select bits and the r/w bit, the slave device out- puts an acknowledge signal on the sda line. the address byte(s) follow the acknowledge. figure 5-4: control and address byte assignments for devices with address pins s 1010 a2 a1 a0 r/w ack s 1010 a2 a1 a0 r/w ack s 1010 a2 a1 a0 r/w ack s 1010 a2 a1 a0 r/w ack s 1010 a2 a1 a0 r/w ack 24xx64 24xx128 24xx256 24xx512 x = ?don?t care? bit acknowledge control code start bit control byte chip select bits* address high byte 24xx32 read/write bit xxxx a11 a10 a9 a8 xxx a12 a11 a10 a9 a8 xx a13 a12 a11 a10 a9 a8 x a14 a13 a12 a11 a10 a9 a8 a15 a14 a13 a12 a11 a10 a9 a8 bit s 1010 a2 a1 a0 r/w ack s 1010 a2 a1 a0 r/w ack s 1010 a2 a1 a0 r/w ack x a6 . . . . . a0 a7 . . . . . . a0 a7 . . . . . . a0 24xx024/025 24c02c 24c01c address byte a7 . . . . . . a0 a7 . . . . . . a0 a7 . . . . . . a0 a7 . . . . . . a0 a7 . . . . . . a0 address low byte * chip select bits a1 and a0 must be set to ? 0 ? for 24xx128/256 devices in the msop package. control byte (read = 1 , write = 0 )
? 2005 microchip technology inc. ds21930a-page 15 24aaxx/24lcxx/24fcxx 5.7.1 contiguous addressing across multiple devices chip select bits a2, a1 and a0 can be used to expand the contiguous address space by adding up to eight 24xxs on the same bus. software can use the three address bits of the contro l byte as the three most significant bits of the address byte. for example, in the 24xx32 devices, software can use a0 of the control byte as address bit a12; a1 as address bit a13; and a2 as address bit a14 (table 5-1). it is not possible to sequentially read across device boundaries. table 5-1: control byte address bits maximum devices maximum contiguous address space chip select bit a2 chip select bit a1 chip select bit a0 1k (24c01c) 8 8 kb a10 a9 a8 1k (24xx014) 8 8 kb a10 a9 a8 2k (24c02c) 8 16 kb a10 a9 a8 2k (24xx024/025 8 16 kb a10 a9 a8 32k (24xx32) 8 256 kb a14 a13 a12 64k (24xx64) 8 512 kb a15 a14 a13 128k (24xx128) 8* 1 mb a16* a15* a14 256k (24xx256) 8* 2 mb a17* a16* a15 512k (24xx512) 8 4 mb a18 a17 a16 * up to two 24xx128 or 24xx256 devices in the msop package can be added for up to 256 kb or 512 kb of address space, respectively. bits a0 and a1 must be set to ? 0 ?.
24aaxx/24lcxx/24fcxx ds21930a-page 16 ? 2005 microchip technology inc. 6.0 write operations 6.1 byte write a byte write operation begi ns with a start condition from the master followed by the four-bit control code (see figure 6-1 and figure 6 -2). the next 3 bits are either the block address bits (for devices without address pins) or the chip select bits (for devices with address pins). then the mast er transmitter clocks the r/w bit (which is a logic lo w) onto the bus. the slave then generates an acknowled ge bit during the ninth clock cycle. the next byte transmitted by the master is the address byte (for 128-bit to 16 kbit devices) or the high-order address byte (for 32-512 kbit devices). for 32 through 512 kbit devices, the high-order address byte is followed by the low-order addr ess byte. in either case, each address byte is ackn owledged by the 24xx and the address bits are latched into the internal address counter of the 24xx. for the 24xx00 devices, onl y the lower four address bits are used by the device . the upper four bits are ?don?t cares.? after receiving the ack from the 24xx acknowledging the final address byte, the ma ster device transmits the data word to be written in to the addressed memory location. the 24xx ack nowledges again and the master generates a stop condi tion, which initiates the internal write cycle. if an attempt is made to write to an array with the wp pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written, and the device wi ll immediately accept a new command. after a byte wr ite command, the internal address counter will increment to the next address location. during a writ e cycle, the 24xx will not acknowledge commands. figure 6-1: byte write: 128-bit to 16 kbit devices figure 6-2: byte write: 32 to 512 kbit devices s p bus activity master sda line bus activity s t a r t s t o p control byte address byte data a c k a c k a c k byte bus activity master sda line bus activity s t a r t control byte high order address byte low order address byte data s t o p a c k a c k a c k a c k s p byte
? 2005 microchip technology inc. ds21930a-page 17 24aaxx/24lcxx/24fcxx 6.2 page write the write control byte, word address byte(s), and the first data byte are transmitte d to the 24xx in much the same way as in a byte write (see figure 6-3 and figure 6-4 ). the exception is that instead of generating a stop condition, the master transmits up to one page of bytes (1) , which is temporarily stored in the on-chip page buffer. this data is then written into memory once the master has transmitted a stop condition. upon receipt of each word, the internal address counter is incremented by one. if the master should transmit more than one page of data prio r to generating the stop con- dition, the address counter w ill roll over and the previ- ously received data will be ov erwritten. as with the byte write operation, once the st op condition is received, an internal write cycle begins. during the write cycle, the 24xx will not acknowledge commands. page writes can be any numb er of bytes within a page (up to the page size), starting at any address. only the data bytes being addressed wi ll be changed within the page. if an attempt is made to wr ite to the array with the wp pin held high, the devi ce will acknowledge the command, but no write cycle wi ll occur, no data will be written and the device will immediately accept a new command. 6.3 write-protection the wp pin allows the user to write-protect the array when the pin is tied to v cc . see device selection table 1-1 for the write-prot ect scheme of each device. if tied to v ss , the write protection is disabled. the wp pin is sampled prior to the stop bit for every write command (figure 2-1). toggling the wp pin after the stop bit will have no effect on the execution of the write cycle. figure 6-3: page write: 1 kb to 16 kbit devices figure 6-4: page write: 32 to 512 kbit devices * see table 1-1 for maximum number of data bytes in a page. note 1: see device selection table 1-1 for the page size of each device. note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries st art at addresses that are integer multiples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size ? 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (over- writing data previously stored there), instead of being written to the next page, as might be expected. it is there- fore necessary for the application soft- ware to prevent page write operations that would attempt to cross a page boundary. s p bus activity master sda line bus activity s t a r t control byte address byte initial final s t o p a c k a c k a c k a c k a c k second data byte data byte data byte* bus activity master sda line bus activity s t a r t control byte high order address byte low order address byte initial s t o p a c k a c k a c k a c k final a c k s p data byte data byte*
24aaxx/24lcxx/24fcxx ds21930a-page 18 ? 2005 microchip technology inc. 7.0 acknowledge polling since the device will not acknowledge commands during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the intern ally timed write cycle. ack polling can be initiated imm ediately. this involves the master sending a start condit ion, followed by the con- trol byte for a write command (r/w = 0 ). if the device is still busy with the writ e cycle, then no ack will be returned. if no ack is return ed, the start bit and control byte must be re-sent. if t he cycle is complete, then the device will return the ack and the master can then pro- ceed with the next read or write command. see figure 7-1 for flow diagram. figure 7-1: acknowledge polling flow send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 did device acknowledge (ack = 0 )? next operation no yes
? 2005 microchip technology inc. ds21930a-page 19 24aaxx/24lcxx/24fcxx 8.0 read operation read operations are initiated in much the same way as write operations with th e exception that the r/w bit of the control byte is set to ? 1 ?. there are three basic types of read operations: current address read, random read and sequential read. 8.1 current address read the 24xx contains an addr ess counter that maintains the address of the last byte accessed, internally incre- mented by ? 1 ?. therefore, if the previous read or write operation was to address ? n ? ( n is any legal address), the next current address r ead operation would access data from address n + 1 . upon receipt of the control byte with r/w bit set to ? 1 ?, the 24xx issues an acknow ledge and transmits the 8-bit data byte. the master will not acknowledge the transfer, but does generate a stop condition and the 24xx discontinues tran smission (figure 8-1). figure 8-1: current address read 8.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, the byte address must first be set. this is done by sendin g the byte address to the 24xx as part of a write operation (r/w bit set to ? 0 ? ). once the byte address is sent, the master generates a start condition following the acknowledge. this termi- nates the write operation, but not before the internal address counter is set. the master then issues the control byte again, but with the r/w bit set to a ? 1 ?. the 24xx will then issue an ac knowledge and transmit the 8-bit data byte. the master will not acknowledge the transfer but does generate a stop condition, which causes the 24xx to discontinue transmission (figure 8-2 and figure 8- 3). after a random read command, the internal address counter will increment to the next address location. figure 8-2: random read: 128-bit to 16 kbit devices figure 8-3: random read: 32 to 512 kbit devices bus activity master sda line bus activity p s s t o p control byte s t a r t data a c k n o a c k byte s p s bus activity master sda line bus activity s t a r t s t o p control byte a c k address byte (n) control byte s t a r t data a c k a c k n o a c k byte bus activity master sda line bus activity a c k n o a c k a c k a c k a c k s t o p s t a r t control byte high order address byte low order address byte control byte data byte s t a r t s s p
24aaxx/24lcxx/24fcxx ds21930a-page 20 ? 2005 microchip technology inc. 8.3 sequential read sequential reads are initiated in the same way as a random read except that af ter the 24xx transmits the first data byte, the master issues an acknowledge as opposed to the stop condit ion used in a random read. this acknowledge directs t he 24xx to transmit the next sequentially addressed data byte (figure 8-4). follow- ing the final byte transmitt ed to the master, the master will not generate an acknowle dge but will generate a stop condition. to provide s equential reads, the 24xx contains an internal address pointer which is incre- mented by one at the comp letion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. if the last address byte in the array is acknowledged, the address pointer will roll over to address 0x00. figure 8-4: sequential read bus activity master sda line bus activity control byte data byte data byte data byte data byte n o a c k a c k a c k a c k a c k s t o p p initial second third final
? 2005 microchip technology inc. ds21930a-page 21 24aaxx/24lcxx/24fcxx appendix a: revision history revision a original release of doc ument. combined serial eeprom 24xxx device data sheets.
24aaxx/24lcxx/24fcxx ds21930a-page 22 ? 2005 microchip technology inc. 9.0 packaging information 9.1 package marking information 8-lead pdip packag e marking (pb-free) device line 1 marking device line 1 marking device line 1 marking device line 1 marking 24aa00 24aa00 24lc00 24lc00 24c00 24c00 24aa01 24aa01 24lc01b 24lc01b 24aa014 24aa014 24lc014 24lc014 24c01c 24c01c 24aa02 24aa02 24lc02b 24lc02b 24aa024 24aa024 24lc024 24lc024 24aa025 24aa025 24lc025 24lc025 24c02c 24c02c 24aa04 24aa04 24lc04b 24lc04b 24aa08 24aa08 24lc08b 24lc08b 24aa16 24aa16 24lc16b 24lc16b 24aa32a 24aa32a 24lc32a 24lc32a 24aa64 24aa64 24lc64 24lc64 24aa128 24aa128 24lc128 24lc128 24fc128 24fc128 24aa256 24aa256 24lc256 24lc256 24fc256 24fc256 24aa512 24aa512 24lc512 24lc512 24fc512 24fc512 note: please visit www.microchip.c om/pbfree for the latest information on pb-free conversion. legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no ro om for the pb-fre e jedec designator , the marking wi ll only appear on the oute r carton or reel label. note : in the event the full microchip part numb er cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e xxxxxnnn xxxxxxxx yyww 8-lead pdip i/p 1l7 24lc01b 0528 example: sn/pb i/p 1l7 24lc01b 0528 example: pb-free 3 e
? 2005 microchip technology inc. ds21930a-page 23 24aaxx/24lcxx/24fcxx note: t = temperature range: i = industrial, e = extended, (blank) = commercial xxxxxnnn xxxxxxxx yyww 8-lead soic i/sn 0528 24lc01b 1l7 example: sn/pb sn 0528 24lc01bi 1l7 example: pb-free 3 e 8-lead soic package marking (pb-free) device line 1 marking device line 1 marking device line 1 marking device line 1 marking 24aa00 24aa00t 24lc00 24lc00t 24c00 24c00t 24aa01 24aa01t 24lc01b 24lc01bt 24aa014 24aa014t 24lc014 24lc014t 24c01c 24c01ct 24aa02 24aa02t 24lc02b 24lc02bt 24aa024 24aa024t 24lc024 24lc024t 24aa025 24aa025t 24lc025 24lc025t 24c02c 24c02ct 24aa04 24aa04t 24lc04b 24lc04bt 24aa08 24aa08t 24lc08b 24lc08bt 24aa16 24aa16t 24lc16b 24lc16bt 24aa32a 24aa32at 24lc32a 24lc32at 24aa64 24aa64t 24lc64 24lc64t 24aa128 24aa128t 24lc128 24lc128t 24fc128 24fc128t 24aa256 24aa256t 24lc256 24lc256t 24fc256 24fc256t 24aa512 24aa512t 24lc512 24lc512t 24fc512 24fc512t note: please visit www.microchip.com/pbfree for t he latest information on pb-free conversion. legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec desi gnator for matte tin (sn) plated devices note : for very small packages with no room for the pb-free jedec designator , the marking will only appea r on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for customer-specific information. 3 e 3 e
24aaxx/24lcxx/24fcxx ds21930a-page 24 ? 2005 microchip technology inc. 8-lead 2x3 dfn example: 244 506 l7 xxx yww nn 8-lead 2x3mm dfn package marking (pb-free) device industrial line 1 marking device industrial line 1 marking e-temp line 1 marking device industrial line 1 marking e-temp line 1 marking 24aa00 201 24lc00 204 205 24c00 207 208 24aa01 211 24lc01b 214 215 24aa014 2n1 24lc014 2n4 2n5 24c01c 2n7 2n8 24aa02 221 24lc02b 224 225 24aa024 2p1 24lc024 2p4 2p5 24aa025 2r1 24lc025 2r4 2r5 24c02c 2p7 2p8 24aa04 231 24lc04b 234 235 24aa08 241 24lc08b 244 245 24aa16 251 24lc16b 254 255 24aa32a 261 24lc32a 264 265 24aa64 271 24lc64 274 275 legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of ja nuary 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no ro om for the pb-free jedec designator , the marking wi ll only appear on the oute r carton or reel label. note : in the event the full microchip part numb er cannot be marked on one line, it will be carried over to the next line, th us limiting the number of available characters for customer-specific information. 3 e 3 e
? 2005 microchip technology inc. ds21930a-page 25 24aaxx/24lcxx/24fcxx note: temperature range (t) listed on sec ond line. i = indust rial, e = extended 8-lead dfn example : pb-free xxxxxxx t/xxxxx yyww 24aa128 i/mf 0528 1l7 nnn example : sn/pb 24aa128 i/mf 0528 1l7 3 e 8-lead 5x6mm dfn package marking (pb-free) device line 1 marking device line 1 marking device line 1 marking 24aa128 24aa128 24lc128 2 4lc128 24fc128 24fc128 24aa256 24aa256 24lc256 2 4lc256 24fc256 24fc256 24aa512 24aa512 24lc512 2 4lc512 24fc512 24fc512 legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no ro om for the pb-free jedec designator , the marking will only appear on the oute r carton or reel label. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
24aaxx/24lcxx/24fcxx ds21930a-page 26 ? 2005 microchip technology inc. example: 5-lead sot-23 xxnn 5el7 5-lead sot-23 package marking (pb-free) device comm. marking indust. marking device comm. marking indust. marking e-temp marking device comm. marking indust. marking e-temp marking 24aa00 a0nn b0nn 24lc00 l0nn m0nn n0nn 24c00 c0nn d0nn e0nn 24aa01 a1nn b1nn 24lc01b l1nn m1nn n1nn 24aa02 a2nn b2nn 24lc02b l2nn m2nn n2nn 24aa04 a3nn b3nn 24lc04b l3nn m3nn n3nn 24aa08 a4nn b4nn 24lc08b l4nn m4nn n4nn 24aa16 a5nn b5nn 24lc16b l5nn m5nn n5nn legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no ro om for the pb-fre e jedec designator , the marking wi ll only appear on the oute r carton or reel label. note : in the event the full microchip part numb er cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 2005 microchip technology inc. ds21930a-page 27 24aaxx/24lcxx/24fcxx note: t = temperature range: i = industrial, e = extended, (blank) = commercial 8-lead msop (150 mil) example: xxxxxxt ywwnnn 4l8bi 2281l7 8-lead msop package marking (pb-free) device line 1 marking device line 1 marking device line 1 marking device line 1 marking 24aa01 4a01t 24lc01b 4l1bt 24aa014 4a14t 24lc014 4l14t 24c01c 4c1ct 24aa02 4a02t 24lc02b 4l2bt 24aa024 4a24t 24lc024 4l24t 24aa025 4a25t 24lc025 4l25t 24c02c 4c2ct 24aa04 4a04t 24lc04b 4l4bt 24aa08 4a08t 24lc08b 4l8bt 24aa16 4a16t 24lc16b 4l16t 24aa32a 4a32at 24lc32a 4l32at 24aa64 4a64t 24lc64 4l64t 24aa128 4a128t 24lc128 4l128t 24fc128 4f128t 24aa256 4a256t 24lc256 4l256t 24fc256 4f256t legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no room for the pb-free jedec designator , the marking will only appea r on the outer carton or reel label. note : in the event the full microchip part numb er cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for customer-specific information. 3 e 3 e
24aaxx/24lcxx/24fcxx ds21930a-page 28 ? 2005 microchip technology inc. note: t = temperature range: i = industrial , e = extended, (blank) = commercial nnn xxxx tyww 8-lead tssop 1l7 4l08 i228 example: 8-lead tssop package marking (pb-free) device line 1 marking device line 1 marking device line 1 marking device line 1 marking 24aa00 4a00 24lc00 4l00 24c00 4c00 24aa01 4a01 24lc01b 4l1b 24aa014 4a14 24lc014 4l14 24c01c 4c1c 24aa02 4a02 24lc02b 4l02 24aa024 4a24 24lc024 4l24 24aa025 4a25 24lc025 4l25 24c02c 4c2c 24aa04 4a04 24lc04b 4l04 24aa08 4a08 24lc08b 4l08 24aa16 4a16 24lc16b 4l16 24aa32a 4aa 24lc32a 4la 24aa64 4ab 24lc64 4lb 24aa128 4ac 24lc128 4lc 24fc128 4fc 24aa256 4ad 24lc256 4ld 24fc256 4fd legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of ja nuary 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, th us limiting the number of available characters for customer-specific information. 3 e 3 e
? 2005 microchip technology inc. ds21930a-page 29 note: t = temperature range: i = industrial, e = extended 14-lead tssop example : xxxxxxxt yyww nnn 4a256i 0528 1l7 14-lead tssop package marking (pb-free) device line 1 marking device line 1 marking device line 1 marking 24aa128 4a128t 24lc128 4l128t 24fc128 4f128t 24aa256 4a256t 24lc256 4l256t 24fc256 4f256t 24aa512 4a512t 24lc512 4l512t 24fc512 4f512t legend: xx...x part number or part number code y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) plated devices note : for very small packages with no room for the pb-free jedec designator , the marking will only appea r on the outer carton or reel label. note : in the event the full microchip part numb er cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for customer-specific information. 3 e 3 e
24aaxx/24lcxx/24fcxx ds21930a-page 30 ? 2005 microchip technology inc. 8-lead plastic dual in-line (p) ? 300 mil (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches* millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .11 5 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flas h or protrusions shall not exceed jedec equivalent: ms-001 drawing no. c04-018 .010? (0.254mm) per side. significant characteristic
? 2005 microchip technology inc. ds21930a-page 31 24aaxx/24lcxx/24fcxx 8-lead plastic small outlin e (sn) ? narrow, 150 mil (soic) foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.33 .020 .017 .013 b lead width 0.25 0.23 0.20 .010 .009 .008 c lead thickness 0.76 0.62 0.48 .030 .025 .019 l foot length 0.51 0.38 0.25 .020 .015 .010 h chamfer distance 5.00 4.90 4.80 .197 .193 .189 d overall length 3.99 3.91 3.71 .157 .154 .146 e1 molded package width 6.20 6.02 5.79 .244 .237 .228 e overall width 0.25 0.18 0.10 .010 .007 .004 a1 standoff 1.55 1.42 1.32 .061 .056 .052 a2 molded package thickness 1.75 1.55 1.35 .069 .061 .053 a overall height 1.27 .050 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters inches* units 2 1 d n p b e e1 h l c 45 a2 a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flas h or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-012 drawing no. c04-057 significant characteristic
24aaxx/24lcxx/24fcxx ds21930a-page 32 ? 2005 microchip technology inc. 8-lead plastic dual flat no lead packag e (mc) 2x3x0.9 mm body (dfn) ? saw singulated exposed pad width exposed pad length contact length *controlling parameter contact width drawing no. c04-123 notes: exposed pad dimensions vary with paddle size. overall width e2 d2 l b e .016 .012 .008 .047 .055 .010 .118 bsc number of pins standoff contact thickness overall length overall height pitch p n units a a1 d a3 dimension limits 8 .000 .001 .008 ref. .079 bsc .031 .020 bsc min inches nom 0.40 0.25 3.00 bsc 0.30 .020 .071 .012 .064 0.20 1.20 1.39 0.50 0.30 1.80 1.62 0.02 0.80 2.00 bsc 0.20 ref. 0.50 bsc millimeters* .002 .039 0.00 min max nom 8 0.05 1.00 max 3. package may have one or more exposed tie bars at ends. 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. 0.90 .035 (not e 3) (not e 3) 4. jedec equivalent: mo-229 l e2 a3 a1 a top view d e exposed pad metal d2 bottom view 21 b p n (note 1) exposed tie bar pin 1 (note 2) id index area revised 05/24/04 -- -- -- --
? 2005 microchip technology inc. ds21930a-page 33 24aaxx/24lcxx/24fcxx 8-lead plastic dual flat no lead pa ckage (mf) 6x5 mm body (dfn-s) ? saw singulated
24aaxx/24lcxx/24fcxx ds21930a-page 34 ? 2005 microchip technology inc. 5-lead plastic small outline transistor (ot) (sot-23) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 .075 p1 outside lead pitch (basic) 0.95 .038 p pitch 5 5 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 p d b n e e1 l c a2 a a1 p1 exceed .005" (0.127mm) per side. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not notes: eiaj equivalent: sc-74a drawing no. c04-091 *controlling parameter
? 2005 microchip technology inc. ds21930a-page 35 24aaxx/24lcxx/24fcxx 8-lead plastic micro small outline package (ms) (msop) d a a1 l c (f) a2 e1 e p b n 1 2 dim e nsions d and e1 do not includ e mold flash or protrusions. mold flash or protrusions shall not .0 3 7 ref f footprint (r e f e r e nc e ) e xc ee d .010" (0.254mm) p e r sid e . not e s: drawing no. c04-111 *controlling param e t e r mold draft angl e top mold draft angl e bottom foot angl e l e ad width l e ad thickn e ss c b .00 3 .009 .006 .012 dim e nsion limits ov e rall h e ight mold e d packag e thickn e ss mold e d packag e width ov e rall l e ngth foot l e ngth standoff ov e rall width numb e r of pins pitch a l e1 d a1 e a2 .016 .024 .118 bsc .118 bsc .000 .0 3 0 .19 3 typ. .0 33 min p n units .026 bsc nom 8 inches 0.95 ref - - .009 .016 0.08 0.22 0 0.2 3 0.40 8 millimeters* 0.65 bsc 0.85 3 .00 bsc 3 .00 bsc 0.60 4.90 bsc .04 3 .0 3 1 .0 3 7 .006 0.40 0.00 0.75 min max nom 1.10 0.80 0.15 0.95 max 8 -- - 15 5 - 15 5 - jedec equival e nt: mo-187 0 - 8 5 5 - - 15 15 - - - -
24aaxx/24lcxx/24fcxx ds21930a-page 36 ? 2005 microchip technology inc. 8-lead plastic thin shrink sma ll outline (st) ? 4.4 mm (tssop) 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 3.10 3.00 2.90 .122 .118 .114 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 8 8 n number of pins max nom min max nom min dimension limits millimeters* inches units a2 a a1 l c 1 2 d n p b e e1 foot angle 048048 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or prot rusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-086 significant characteristic
? 2005 microchip technology inc. ds21930a-page 37 24aaxx/24lcxx/24fcxx 14-lead plastic thin shrink small outline (st) ? 4.4 mm body (tssop) 8 4 0 8 4 0 foot angle 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.30 0.25 0.19 .012 .010 .007 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 0.70 0.60 0.50 .028 .024 .020 l foot length 5.10 5.00 4.90 .201 .197 .193 d molded package length 4.50 4.40 4.30 .177 .173 .169 e1 molded package width 6.50 6.38 6.25 .256 .251 .246 e overall width 0.15 0.10 0.05 .006 .004 .002 a1 standoff 0.95 0.90 0.85 .037 .035 .033 a2 molded package thickness 1.10 .043 a overall height 0.65 .026 p pitch 14 14 n number of pins max nom min max nom min dimension limits millimeters* inches units l c 2 1 d n b p e1 e a2 a1 a * controlling parameter notes: dimensions d and e1 do not include mol d flash or protrusions . mold flash or protrusions shall not exceed .005? (0.127mm) per side. jedec equivalent: mo-153 drawing no. c04-087 significant characteristic
24aaxx/24lcxx/24fcxx ds21930a-page 38 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21930a-page 39 24aaxx/24lcxx/24fcxx the microchip web site microchip provides online su pport via our www site at www.microchip.com. this web si te is used as a means to make files and inform ation easily available to customers. accessible by us ing your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guid es and hardware support documents, latest softwar e releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notif ication service helps keep customers current on microc hip products. subscribers will receive e-mail notifica tion whenever there are changes, updates, revisions or errata related to a specified product family or de velopment tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow t he registration instructions. customer support users of microchip produc ts can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field appl ication engineer (fae) for support. local sales offices are also available to help customers. a listing of sa les offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com in addition, there is a development systems information line which list s the latest versions of microchip?s development systems software products. this line also provides information on how customers can receive currently available upgrade kits. the development systems information line numbers are: 1-800-755-2345 ? united stat es and most of canada 1-480-792-7302 ? other in ternational locations
24aaxx/24lcxx/24fcxx ds21930a-page 40 ? 2005 microchip technology inc. reader response it is our intention to provide yo u with the best documentation possible to en sure successful use of your microchip prod- uct. if you wish to provide your comm ents on organization, clarity, subject matt er, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us wi th your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _ ________ - _________ ds21930a 24aaxx/24lcxx/24fcxx 1. what are the best features of this document? 2. how does this document meet your ha rdware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you th ink would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or mislead ing information (what and where)? 7. how would you improve this document?
? 2005 microchip technology inc. ds21930a-page41 24aaxx/24lcxx/24fcxx product identification system to order or obtain information, e.g., on pricing or deliver y, refer to the factory or the listed sales office. note 1: most products manufactured after january 2005 have a matte tin (pb-free) finish. most products manufactured before january 2005 have a fi nish of approximately 63% sn and 37% pb (sn/pb). please visit www.microchip.com/pbfree for the latest information on pb-free conversion, including conversion date codes. sales and support data sheets products supported by a preliminary data sheet may have an erra ta sheet describing minor operational differences and recom- mended workarounds. to determine if an errata sheet exists for a particular devic e, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literatu re center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon a nd data sheet (include literature #) you are using. customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products. part no. x /xx package temperature range device part examples: a) 24c00/p: 128-bit, commercial temper- ature, 5v, pdip package b) 24aa014-i/sn: 1 kbit, industrial temperature, 1.8v, soic package c) 24aa02t-i/ot: 2 kbit, industrial temperature, 1.8v, sot-23 package, tape and reel d) 24lc16b-i/p: 16 kbit, industrial tempera- ture, 2.5v, pdip package e) 24lc32a-e/ms: 32 kbit, extended temperature, 2.5v, msop package f) 24lc64t-i/mc: 64 kbit, industrial temperature, 2.5v 2x3 mm dfn package, tape and reel g) 24lc256-e/stg: 256 kbit, extended temperature, 2.5v, tssop package, pb-free h) 24fc512t-i/sm: 512 kbit, industrial temperature, 1 mhz, soic package, tape and reel lead finish x device: see table 1-1 temperature range: i = -40c to +85c e = -40c to +125c c = 0c to +70c packaging medium: t = tape and reel blank = tube package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead sm = plastic soic (208 mil body), 8-lead st = plastic tssop (4.4 mm), 8-lead st14 = plastic tssop (4.4 mm), 14-lead ms = plastic micro small outline (msop), 8-lead ot = sot-23, 5-lead (tape and reel only) mc = 2x3 mm dfn, 8-lead mf = 5x6 mm dfn, 8-lead lead finish: blank = pb-free ? matte tin (see note 1) g = pb-free ? matte tin only number (table 1-1) x packaging medium
24aaxx/24lcxx/24fcxx ds21930a-page 42 ? 2005 microchip technology inc. notes:
? 2005 microchip technology inc. ds21930a-page 43 information contained in this publication regarding device applications and the like is pr ovided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition , quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip?s products as critical components in life support systems is not autho rized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictai l, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance and wiperlock are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2005, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of produc ts is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications contained in microchip?s data sheets. most likely, the per son doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about th e integrity of their code. ? neither microchip nor an y other semiconductor manufacturer can guarantee the se curity of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for reli ef under that act. microchip received iso/ts-16949:2002 quali ty system certification for its worldwide headquarters, design and wa fer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microp eripherals, nonvolatile memory and analog products. in addition, microc hip?s quality system for the design and manufacture of de velopment systems is iso 9001:2000 certified.
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