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scbs666b ? july 1996 ? revised june 2004 1 post office box 655303 ? dallas, texas 75265 members of the texas instruments widebus ? family output ports have equivalent 25- ? series resistors so no external resistors are required typical v olp (output ground bounce) <1 v at v cc = 5 v, t a = 25 c high-impedance state during power up and power down i off and power-up 3-state support hot insertion distributed v cc and gnd pins minimize high-speed switching noise flow-through architecture optimizes pcb layout description/ordering information these 18-bit bus-interface flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. they are particularly suitable for implementing wider buffer registers, i/o ports, bidirectional bus drivers with parity, and working registers. the ?abt162823a devices can be used as two 9-bit flip-flops or one 18-bit flip-flop. with the clock-enable (clken ) input low, the d-type flip-flops enter data on the low-to-high transitions of the clock. taking clken high disables the clock buffer, thus latching the outputs. taking the clear (clr ) input low causes the q outputs to go low independently of the clock. ordering information t a package ? orderable part number top-side marking ssop ? dl tube sn74abt162823adl abt162823a ?40 c to 85 c ssop ? dl tape and reel sn74abt162823adlr abt162823a ?40 c to 85 c tssop ? dgg tape and reel sn74abt162823adggr abt162823a ?55 c to 125 c cfp ? wd tube snj54abt162823awd snj54abt162823awd ? package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. copyright ? 2004, texas instruments incorporated please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. widebus is a trademark of texas instruments. sn54abt162823a . . . wd package sn74abt162823a . . . dgg or dl package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1clr 1oe 1q1 gnd 1q2 1q3 v cc 1q4 1q5 1q6 gnd 1q7 1q8 1q9 2q1 2q2 2q3 gnd 2q4 2q5 2q6 v cc 2q7 2q8 gnd 2q9 2oe 2clr 1clk 1clken 1d1 gnd 1d2 1d3 v cc 1d4 1d5 1d6 gnd 1d7 1d8 1d9 2d1 2d2 2d3 gnd 2d4 2d5 2d6 v cc 2d7 2d8 gnd 2d9 2clken 2clk
scbs666b ? july 1996 ? revised june 2004 2 post office box 655303 ? dallas, texas 75265 description/ordering information (continued) a buffered output-enable (oe ) input places the nine outputs in either a normal logic state (high or low level) or a high-impedance state. in the high-impedance state, the outputs neither load nor drive the bus lines significantly. the high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. oe does not affect the internal operation of the flip-flops. old data can be retained or new data can be entered while the outputs are in the high-impedance state. the outputs, which are designed to source or sink up to 12 ma, include equivalent 25- ? series resistors to reduce overshoot and undershoot. these devices are fully specified for hot-insertion applications using i off and power-up 3-state. the i off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. the power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. to ensure the high-impedance state during power up or power down, oe shall be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. function table (each 9-bit flip-flop) inputs output oe clr clken clk d output q l l x x x l l hl hh l hl ll l hl lx q 0 l hhxx q 0 h x x x x z
scbs666b ? july 1996 ? revised june 2004 3 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) to eight other channels 1d1 1q1 1clken 1oe 1clr 2 1 55 54 r 1d c1 3 ce 56 1clk to eight other channels 2d1 2q1 2clken 2oe 2clr 27 28 30 42 r 1d c1 15 ce 29 2clk absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage range, v cc ?0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 1) ?0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high or power-off state, v o ?0.5 v to 5.5 v . . . . . . . . . . . . . . . . . . . current into any output in the low state, i o 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) ?18 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0) ?50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, ja (see note 2): dgg package 64 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dl package 56 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observe d. 2. the package thermal impedance is calculated in accordance with jesd 51-7.
scbs666b ? july 1996 ? revised june 2004 4 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 3) sn54abt162823a sn74abt162823a unit min max min max unit v cc supply voltage 4.5 5.5 4.5 5.5 v v ih high-level input voltage 2 2 v v il low-level input voltage 0.8 0.8 v v i input voltage 0 v cc 0 v cc v i oh high-level output current ?3 ?12 ma i ol low-level output current 8 12 ma ? t/ ? v input transition rise or fall rate outputs enabled 10 10 ns/v ? t/ ? v cc input transition rise or fall rate 200 200 s/v t a operating free-air temperature ?55 125 ?40 85 c note 3: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions t a = 25 c sn54abt162823a sn74abt162823a unit parameter test conditions min typ ? max min max min max unit v ik v cc = 4.5 v, i i = ?18 ma ?1.2 ?1.2 ?1.2 v v cc = 4.5 v, i oh = ?1 ma 2.5 2.5 2.5 v oh v cc = 5 v, i oh = ?1 ma 3 3 3 v v oh v cc = 4.5 v i oh = ?3 ma 2.4 2.4 2.4 v v cc = 4.5 v i oh = ?12 ma 2* 2 v ol v cc = 4.5 v i ol = 8 ma 0.4 0.8 0.65 v v ol v cc = 4.5 v i ol = 12 ma 0.8* 0.8 v i i v cc = 5.5 v, v i = v cc or gnd 1 1 1 a i ozpu v cc = 0 to 2.1 v, v o = 0.5 v to 2.7 v, oe = x 50 50 50 a i ozpd v cc = 2.1 v to 0, v o = 0.5 v to 2.7 v, oe = x 50 50 50 a i ozh ? v cc = 5.5 v, v o = 2.7 v 10 10 10 a i ozl ? v cc = 5.5 v, v o = 0.5 v ?10 ?10 ?10 a i off v cc = 0, v i or v o 4.5 v 100 100 a i cex v cc = 5.5 v, v o = 5.5 v outputs high 50 50 50 a i o v cc = 5.5 v, v o = 2.5 v ?25 ?55 ?100 ?25 ?100 ?25 ?100 ma v cc = 5.5 v, outputs high 0.5 0.5 0.5 i cc v cc = 5.5 v, i o = 0, v = v or gnd outputs low 80 80 80 ma i cc i o = 0, v i = v cc or gnd outputs disabled 0.5 0.5 0.5 ? i cc ? v cc = 5.5 v, one input at 3.4 v, other inputs at v cc or gnd 1.5 1.5 1.5 ma c i v i = 2.5 v or 0.5 v 3.5 pf c o v o = 2.5 v or 0.5 v 9 pf * on products compliant to mil-prf-38535, this parameter does not apply. ? all typical values are at v cc = 5 v. ? the parameters i ozh and i ozl include the input leakage current. not more than one output should be tested at a time, and the duration of the test should not exceed one second. ? this is the increase in supply current for each input that is at the specified ttl-voltage level, rather than v cc or gnd.
scbs666b ? july 1996 ? revised june 2004 5 post office box 655303 ? dallas, texas 75265 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see figure 1) v cc = 5 v, t a = 25 c sn54abt162823a sn74abt162823a unit min max min max min max unit f clock clock frequency 150 150 150 mhz t w pulse duration clr low 3.3 3.3 3.3 ns t w pulse duration clk high or low 3.3 3.3 3.3 ns clr inactive 1.6 2 1.6 t su setup time before clk data 2 2 2 ns t su setup time before clk clken low 0.6 0.6 0.6 ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, c l = 50 pf (unless otherwise noted) (see figure 1) parameter from (input) to (output) v cc = 5 v, t a = 25 c sn54abt162823a sn74abt162823a unit parameter (input) (output) min typ max min max min max unit f max 150 150 150 mhz t plh clk q 2.3 4.6 6.2 2.3 8.4 2.3 7.5 ns t phl clk q 2.8 4.6 6.1 2.8 7.1 2.8 6.7 ns t phl clr q 2.8 5 6.3 2.8 7.2 2.8 7 ns t pzh oe q 1.7 3.8 5 1.7 5.8 1.7 5.9 ns t pzl oe q 3 5 6.1 3 7.2 3 7 ns t phz oe q 2.6 4.8 6.1 2.6 7.3 2.6 6.6 ns t plz oe q 1.9 4.6 6.7 1.9 10.2 1.9 9 ns
scbs666b ? july 1996 ? revised june 2004 6 post office box 655303 ? dallas, texas 75265 parameter measurement information 1.5 v t h t su from output under test c l = 50 pf (see note a) load circuit s1 7 v open gnd 500 ? 500 ? data input timing input 1.5 v 3 v 0 v 1.5 v 1.5 v 3 v 0 v 3 v 0 v 1.5 v t w input voltage waveforms setup and hold times voltage waveforms propagation delay times inverting and noninverting outputs voltage waveforms pulse duration t plh t phl t phl t plh v oh v oh v ol v ol 1.5 v 1.5 v 3 v 0 v 1.5 v 1.5 v input 1.5 v output control output waveform 1 s1 at 7 v (see note b) output waveform 2 s1 at open (see note b) v ol v oh t pzl t pzh t plz t phz 1.5 v 1.5 v 3.5 v 0 v 1.5 v v ol + 0.3 v 1.5 v v oh ? 0.3 v 0 v 3 v voltage waveforms enable and disable times low- and high-level enabling output output t plh /t phl t plz /t pzl t phz /t pzh open 7 v open test s1 notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 ? , t r 2.5 ns, t f 2.5 ns . d. the outputs are measured one at a time, with one transition per measurement. e. all parameters and waveforms are not applicable to all devices. 1.5 v figure 1. load circuit and voltage waveforms
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 74abt162823adggre4 active tssop dgg 56 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74abt162823adggrg4 active tssop dgg 56 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 74abt162823adlrg4 active ssop dl 56 1000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74abt162823adggr active tssop dgg 56 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74abt162823adl active ssop dl 56 20 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74abt162823adlg4 active ssop dl 56 20 green (rohs & no sb/br) cu nipdau level-1-260c-unlim sn74abt162823adlr active ssop dl 56 1000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 18-sep-2008 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn74abt162823adggr tssop dgg 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 q1 sn74abt162823adlr ssop dl 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.0 q1 package materials information www.ti.com 11-mar-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn74abt162823adggr tssop dgg 56 2000 346.0 346.0 41.0 sn74abt162823adlr ssop dl 56 1000 346.0 346.0 49.0 package materials information www.ti.com 11-mar-2008 pack materials-page 2
mechanical data msso001c ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 dl (r-pdso-g**) plastic small-outline package 4040048 / e 12/01 48 pins shown 56 0.730 (18,54) 0.720 (18,29) 48 28 0.370 (9,40) (9,65) 0.380 gage plane dim 0.420 (10,67) 0.395 (10,03) a min a max 0.010 (0,25) pins ** 0.630 (16,00) (15,75) 0.620 0.010 (0,25) seating plane 0.020 (0,51) 0.040 (1,02) 25 24 0.008 (0,203) 0.0135 (0,343) 48 1 0.008 (0,20) min a 0.110 (2,79) max 0.299 (7,59) 0.291 (7,39) 0.004 (0,10) m 0.005 (0,13) 0.025 (0,635) 0 ? 8 0.005 (0,13) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). d. falls within jedec mo-118
mechanical data mtss003d january 1995 revised january 1998 post office box 655303 ? dallas, texas 75265 dgg (r-pdso-g**) plastic small-outline package 4040078 / f 12/97 48 pins shown 0,25 0,15 nom gage plane 6,00 6,20 8,30 7,90 0,75 0,50 seating plane 25 0,27 0,17 24 a 48 1 1,20 max m 0,08 0,10 0,50 0 8 56 14,10 13,90 48 dim a max a min pins ** 12,40 12,60 64 17,10 16,90 0,15 0,05 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without 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with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband clocks and timers www.ti.com/clocks digital control www.ti.com/digitalcontrol interface interface.ti.com medical www.ti.com/medical logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security rfid www.ti-rfid.com telephony www.ti.com/telephony rf/if and zigbee? solutions www.ti.com/lprf video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2008, texas instruments incorporated

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