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december 2005 document control #ml0022 rev 1.3 1 stk14ca8 128k x 8 autostore tm nvsram quantumtrap tm cmos nonvolatile static ram features ? 25ns, 35ns and 45ns access times ? ?hands-off? automatic store on power down with only a small capacitor ? store to quantumtrap? nonvolatile elements is initiated by software , device pin or autostore ? on power down ? recall to sram initiated by software or power up ? unlimited read, write and recall cycles ? 10ma typical i cc at 200ns cycle time ? high-reliability o endurance to 500k store cycles o data retention to 20 years ? single 3v +20%, -10% operation ? commercial and industrial temperatures ? soic, and ssop packages (rohs compliance) description the simtek stk14ca8 is a fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorporate simtek?s quantumtrap tm technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable quantumtrap tm cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. block diagram row decoder input buffers column dec g e w column i/o power control hsb store/ recall control software detect a 15 ? a 0 a 5 a 6 a 7 a 8 a 9 a 12 a 13 a 14 a 15 a 16 quantum trap 1024 x 1024 static ram array 1024 x 1024 store recall dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 a 0 a 1 a 2 a 3 a 4 a 10 a 11 v cc v cap figure 1. block diagram
stk14ca8 december 2005 document control #ml0022 rev 1.3 2 v cap dq 0 dq 1 dq 2 g a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 v cc a 15 a 13 a 8 a 11 v ss dq 6 a 10 dq 7 dq 5 dq 4 dq 3 a 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 w hsb e 32 pin soic 48 pin ssop v cap v ss a 16 a 14 a 12 a 7 a 6 a 5 a 4 v cc a 15 a 13 a 8 dq 0 v ss dq 6 a 9 1 2 3 4 5 6 7 8 9 1 0 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 w hsb dq 1 dq 2 g a 3 a 2 a 1 a 0 dq 5 a 10 dq 7 dq 4 dq 3 v cc 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 e a 11 packages pin descriptions pin name i/o description a 16 ? a 0 input address: the 17 address inputs select one of 131,072 bytes in the nvsram array. dq 7 ?dq 0 i/o data: bi-directional 8-bit data bus for accessing the nvsram. e input chip enable: the active low e input selects the device. w input write enable: the active low w enables data on the dq pins to be written to the address location latched by the falling edge of e . g input output enable: the active low g input enables the data output buffers during read cycles. de-asserting g high causes the dq pins to tri-state. v cc power supply power 3.0v +20%, -10% hsb i/o hardware store busy: when low this output indicates a hardware store is in progress. when pulled low external to the chip it will initiate a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected. (connection optional) v cap power supply autostore capacitor: supplies power to nvsram during power loss to store data from sram to nonvolatile elements. v ss power supply ground (blank) no connect unlabeled pins have no internal connection. ssop relative pcb area usage. see website for detailed package size specifications.
stk14ca8 december 2005 document control #ml0022 rev 1.3 3 package thermal characteristics see website: http://www.simtek.com/ dc characteristics commercial industrial symbol parameter min max min max units notes t avav = 25ns t avav = 35ns i cc1 average v cc current 65 55 50 70 60 55 ma ma ma t avav = 45ns dependent on output loading and cycle rate. values obtained without output loads. i cc2 average v cc current during store 3 3 ma all inputs don?t care, v cc = max average current for duration of store cycle (t store ). average v cc current at t avav = 200ns w (v cc ? 0.2v) i cc3 3v, 25c, typical 10 10 ma all others inputs cycling, at cmos levels. dependent on output loading and cycle rate. values obtained without output loads. i cc4 average v cap current during autostore ? cycle 3 3 ma all inputs don?t care average current for duration of store cycle (t store ). v cc standby current e (v cc ? 0.2v) i sb (standby, stable cmos input levels) 3 3 ma all others v in 0.2v or (v cc ? 0.2v) standby current level after nonvolatile cycle is complete. v cc = max i ilk input leakage current 1 1 a v in = v ss to v cc v cc = max i olk off-state output leakage current 1 1 a v in = v ss to v cc , e or g v ih v ih input logic ?1? voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 v all inputs v il input logic ?0? voltage v ss ? 0.5 0.8 v ss ? 0.5 0.8 v all inputs v oh output logic ?1? voltage 2.4 2.4 v i out = ?2ma v ol output logic ?0? voltage 0.4 0.4 v i out = 4ma t a operating temperature 0 70 ?40 85 o c v cc operating voltage 2.7 3.6 2.7 3.6 v 3.0v +20%, -10% v cap storage capacitor 17 57 17 57 f between vcap pin and vss, 5v rated. nv c nonvolatile store operations 500 500 500 k data r data retention 20 20 years @ maximum operating temperature absolute maximum ratings a power supply voltage voltage on input relative to v ss voltage on outputs temperature under bias junction temperature storage temperature power dissipation dc output current (1 output at a time, 1s duration) notes a: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at con- ditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect reliability. -0.5v to +4.1v -0.5v to (v cc + 0.5v) -0.5v to (v cc + 0.5v) ?55 c to 125 c ?55 c to 140 c ?65 c to 150 c 1w 15ma
stk14ca8 december 2005 document control #ml0022 rev 1.3 4 ac test conditions capacitance b (t a = 25 c, f = 1.0mhz) symbol parameter max units conditions c in input capacitance 7 pf ? v = 0 to 3v c out output capacitance 7 pf ? v = 0 to 3v notes b: these parameters are guaranteed but not tested 3.0v 30 pf including scope and fixture 577 ohms 789 ohms output 3.0v 30 pf including scope and fixture 577 ohms 789 ohms output figure 3. ac output loading, for tristate specs ( t hz , t lz , t wlqz , t whqz , t glqx , t ghqz ) figure 2. ac output loading input pulse levels input rise and fall times input and output timing reference levels output load 0v to 3v 5ns 1.5v see figure 2 and figure 3 5 pf
stk14ca8 december 2005 document control #ml0022 rev 1.3 5 sram read cycles #1 & #2 symbols stk14ca8-25 stk14ca8-35 stk14ca8-45 no. #1 #2 alt. parameter min max min max min max units 1 t elqv t acs chip enable access time 25 35 45 ns 2 t avav c t avav c t rc read cycle time 25 35 45 ns 3 t avqv d t aa address access time 25 35 45 ns 4 t glqv t oe output enable to data valid 12 15 20 ns 5 t axqx d t oh output hold after address change 3 3 3 ns 6 t elqx t lz chip enable to output active 3 3 3 ns 7 t ehqz e t hz chip disable to output inactive 10 13 15 ns 8 t glqx t olz output enable to output active 0 0 0 ns 9 t ghqz e t ohz output disable to output inactive 10 13 15 ns 10 t elicc b t pa chip enable to power active 0 0 0 ns 11 t ehicc b t ps chip disable to power standby 25 35 45 ns notes c: w must be high during sram read cycles d: device is continuously selected with e and g both low e: measured 200mv from steady state output voltage f: hsb must remain high during read and write cycles. sram read cycle #1: address controlled c,d,f sram read cycle #2: e controlled c,f dq (data out) a ddress 3 t avqv 5 t axqx data valid 2 t avav 2 t avav data valid address dq ( data out ) i cc standby active 1 t elqv 6 t elq x 4 t glqv 8 t glq x 10 t elicch 11 t ehiccl 7 t ehqz 9 t ghqz e g
stk14ca8 december 2005 document control #ml0022 rev 1.3 6 sram write cycles #1 & #2 notes g: if w is low when e goes low, the outputs remain in the high-impedance state. h: e or w must be v ih during address transitions. sram write cycle #1: w controlled h,f sram write cycle #2: e controlled h,f symbols stk14ca8-25 stk14ca8-35 stk14ca8-45 units no. #1 #2 alt. parameter min max min max min max 12 t avav t avav t wc write cycle time 25 35 45 ns 13 t wlwh t wleh t wp write pulse width 20 25 30 ns 14 t elwh t eleh t cw chip enable to end of write 20 25 30 ns 15 t dvwh t dveh t dw data set-up to end of write 10 12 15 ns 16 t whdx t ehdx t dh data hold after end of write 0 0 0 ns 17 t avwh t aveh t aw address set-up to end of write 20 25 30 ns 18 t avwl t avel t as address set-up to start of write 0 0 0 ns 19 t whax t ehax t wr address hold after end of write 0 0 0 ns 20 t wlqz e,g t wz write enable to output disable 10 13 15 ns 21 t whqx t ow output active after end of write 3 3 3 ns address data out data in w e address high impedance data valid previous data 14 t elwh 19 t whax 17 t avwh 18 t avwl 13 t wlwh 15 t dvwh 16 t whd x 20 t wlqz 21 t whqx 12 t a va v 12 t avav data out data in w e high impedance data valid 14 t eleh 18 t avel 19 t ehax 17 t aveh 13 t wleh 15 t dveh 16 t ehdx
stk14ca8 december 2005 document control #ml0022 rev 1.3 7 autostore ? /power-up recall symbols parameter stk14ca8 no. standard alternate min max units notes 22 t hrecall power-up recall duration 20 ms i 23 t store t hlhz store cycle duration 12.5 ms j , k 24 v switch low voltage trigger level 2.55 2.65 v 25 t vccrise v cc rise time 150 s notes i: t hrecall starts from the time v cc rises above v switch j: if an sram write has not taken place since the last nonvolatile cycle, no store will take place k: industrial grade devices require 15ms max. autostore ?/power-up recall note: read and write cycles will be ignored during store, recall and while v cc is below v switch power-up recall v cc 23 t store 22 t hrecall 24 v switch autostore tm power down autostore tm brown out autostore tm power-up recall read & write inhibited 25 t vccrise 23 t store 22 t hrecall power-up recall store occurs only if a sram write has happened. no store occurs without at least one sram write.
stk14ca8 december 2005 document control #ml0022 rev 1.3 8 software-controlled store / recall cycle l,m symbols stk14ca8-25 stk14ca8-35 stk14ca8-45 no. e cont g cont alt. parameter min max min max min max units notes 26 t avav t avav t rc store/recall initiation cycle time 25 35 45 ns m 27 t avel t avgl t as address set-up time 0 0 0 ns 28 t eleh t glgh t cw clock pulse width 20 25 30 ns 29 t elax t glax address hold time 20 20 20 ns 30 t recall t recall recall duration 50 50 50 s notes l: the software sequence is clocked with e controlled reads or g controlled reads. m: the six consecutive addresses must be read in the order listed in the mode selection table. w must be high during all six consecutive cycles. software store / recall cycle: e controlled m software store / recall cycle: g controlled m dq (data) g e 26 t a va v data valid address address #1 high impedence 27 t avel 29 t elax 28 t eleh 30 t recall 26 t a va v address #6 23 t store data valid / address e g dq (data) 26 t avav data valid address #1 high impedence 29 t glax 30 t recall 26 t avav address #6 23 t store 27 t a vgl 28 t glgh data valid /
stk14ca8 december 2005 document control #ml0022 rev 1.3 9 hardware store cycle symbols stk14ca8 no. standard alternate parameter min max units notes 31 t delay t hlqz time allowed to complete sram cycle 1 s n 32 t hlhx hardware store pulse width 15 ns 33 t hlbl hardware store low to store busy 300 ns notes n: read and write cycles in progress before hsb is asserted are given this amount of time to complete. hardware store cycle soft sequence commands symbols stk14ca8 no. standard parameter min max units notes 34 t ss soft sequence processing time 70 s o , p notes o: this is the amount of time that it takes to take action on a soft sequence command. vcc power must remain high to effective ly register command. p: commands like store and recall lock out i/o until operation is complete which further increases this time. see specific com mand. hsb (out) hsb (in) dq (data out) high impedence 31 t dela y data valid 32 t hlhx 33 t hlbl high impedence data valid 23 t s t o re vcc 34 t ss address address #1 soft sequence command address #6 address #1 soft sequence command address #6 34 t ss
stk14ca8 december 2005 document control #ml0022 rev 1.3 10 mode selection e w g a 15 - a 0 mode i/o power notes h x x x not selected output high z standby l h l x read sram output data active l l x x write sram input data active l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8b45 read sram read sram read sram read sram read sram autostore disable output data output data output data output data output data output data active q , r , s l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4b46 read sram read sram read sram read sram read sram autostore enable output data output data output data output data output data output data active q , r , s l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x8fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active icc2 q , r , s l h l 0x4e38 0xb1c7 0x83e0 0x7c1f 0x703f 0x4c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active q , r , s notes q: the six consecutive addresses must be in the order listed. w must be high during all six consecutive cycles to enable a nonvolatile cycle. r: while there are 17 addresses on the stk14ca8, only the lower 16 are used to control software modes s: i/o state depends on the state of g . the i/o table shown assumes g low.
stk14ca8 december 2005 document control #ml0022 rev 1.3 11 nvsram the stk14ca8 nvsram is made up of two functional components paired in the same physical cell. these are a sram memory cell and a nonvolatile quantumtrap ? cell . the sram memory cell operates as a standard fast static ram. data in the sram can be transferred to the nonvolatile cell (the store operation), or from the nonvolatile cell to sram (the recall operation). this unique architecture allows all cells to be stored and recalled in parallel. during the store and recall operations sram read and write operations are inhibited. the stk14ca8 supports unlimited reads and writes just like a typical sram. in addition, it provides unlimited recall operations from the nonvolatile cells and up to 500k store operations. sram read the stk14ca8 performs a read cycle whenever e and g are low while w and hsb are high. the address specified on pins a 16-0 determines which of the 131,072 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t avqv (read cycle #1). if the read is initiated by e or g , the outputs will be valid at t elqv or at t glqv , whichever is later (read cycle #2). the data outputs will repeatedly respond to address changes within the t avqv access time without the need for transitions on any control input pins, and will remain valid until another address change or until e or g is brought high, or w or hsb is brought low. v cc v cap 10k ohm 0.1f v cc v cap w sram write a write cycle is performed whenever e and w are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on the common i/o pins dq 0-7 will be written into the memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write. it is recommended that g be kept high during the entire write cycle to avoid data bus contention on common i/o lines. if g is left low, internal circuitry will turn off the output buffers t wlqz after w goes low. autostore ? operation the stk14ca8 stores data to nvsram using one of three storage operations. these three operations are hardware store, activated by hsb , software store, actived by an address sequence, and autostore ?, on device power down. autostore ? operation is a unique feature of simtek quantumtrap ? technology and is enabled by default on the stk14ca8. during normal operation, the device will draw current from vcc to charge a capacitor connected to the vcap pin. this stored charge will be used by the chip to perform a single store operation. if the voltage on the vcc pin drops below vswitch, the part will automatically disconnect the vcap pin from vcc. a store operation will be initiated with power provided by the vcap capacitor. figure 4 shows the proper connection of the storage capacitor (vcap) for automatic store operation. refer to the dc characteristics table for the size of vcap. the voltage on the vcap pin is driven to 5v by a charge pump internal to the chip. a pull up should be placed on w to hold it inactive during power up. to reduce unneeded nonvolatile stores, autostore ? and hardware store operations will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation has taken place. the hsb signal can be monitored by the system to detect an autostore ? cycle is in progress. device operation figure 4 : autostore tm mode
stk14ca8 december 2005 document control #ml0022 rev 1.3 12 hardware store (hsb ) operation the stk14ca8 provides the hsb pin for controlling and acknowledging the store operations. the hsb pin can be used to request a hardware store cycle. when the hsb pin is driven low, the stk14ca8 will conditionally initiate a store operation after t delay . an actual store cycle will only begin if a write to the sram took place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the store (initiated by any means) is in progress. sram read and write operations that are in progress when hsb is driven low by any means are given time to complete before the store operation is initiated. after hsb goes low, the stk14ca8 will continue sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it will be allowed a time, t delay , to complete. however, any sram write cycles requested after hsb goes low will be inhibited until hsb returns high. during any store operation, regardless of how it was initiated, the stk14ca8 will continue to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation the stk14ca8 will remain disabled until the hsb pin returns high. if hsb is not used, it should be left unconnected. hardware recall (power-up) during power up, or after any low-power condition (v cc < v switch ), an internal recall request will be latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle will automatically be initiated and will take t hrecall to complete. software store data can be transferred from the sram to the nonvolatile memory by a software address sequence. the stk14ca8 software store cycle is initiated by executing sequential e controlled read cycles from six specific address locations in exact order. during the store cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. once a store cycle is initiated, further input and output are disabled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence will be aborted and no store or recall will take place. to initiate the software store cycle, the following read sequence must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8fc0 initiate store cycle the software sequence may be clocked with e controlled reads or g controlled reads. once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be disabled. it is important that read cycles and not write cycles be used in the sequence, although it is not necessary that g be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. software recall data can be transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of e controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4c63 initiate recall cycle
stk14ca8 december 2005 document control #ml0022 rev 1.3 13 internally, recall is a two-step procedure. first, the sram data is cleared, and second, the nonvolatile information is transferred into the sram cells. after the t recall cycle time the sram will once again be ready for read and write operations. the recall operation in no way alters the data in the nonvolatile elements. data protection the stk14ca8 protects data from corruption during low-voltage conditions by inhibiting all externally initiated store and write operations. the low-voltage condition is detected when v cc < v switch . if the stk14ca8 is in a write mode (both e and w low ) at power-up, after a recall , or after a store, the write will be inhibited until a negative transition on e or w is detected. this protects against inadvertent writes during power up or brown out conditions. noise considerations the stk14ca8 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss , using leads and traces that are as short as possible. as with all high-speed cmos ics, careful routing of power, ground and signals will reduce circuit noise. low average active power cmos technology provides the stk14ca8 this the benefit of drawing significantly less current when it is cycled at times longer than 50ns. figure 5 shows the relationship between i cc and read/write cycle time. worst-case current consumption is shown for commercial temperature range, v cc = 3.6v, and chip enable at maximum frequency. only standby current is drawn when the chip is disabled. the overall average current drawn by the stk14ca8 depends on the following items: 1. the duty cycle of chip enable. 2. the overall cycle rate for accesses. 3. the ratio of reads to writes. 4. the operating temperature. 5. the v cc level. 6. i/o loading. average active current (ma) 100 150 200 300 0 10 20 30 40 50 writes reads cycle time (ns) 50 figure 5 current vs. cycle time
stk14ca8 december 2005 document control #ml0022 rev 1.3 14 preventing autostore tm the autostore ? function can be disabled by initiating an autostore disable sequence. a sequence of read operations is performed in a manner similar to the software store initiation. to initiate the autostore disable sequence, the following sequence of e controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x8b45 autostore disable the autostore ? can be re-enabled by initiating an autostore enable sequence. a sequence of read operations is performed in a manner similar to the software recall initiation. to initiate the autostore enable sequence, the following sequence of e controlled read operations must be performed: 1. read address 0x4e38 valid read 2. read address 0xb1c7 valid read 3. read address 0x83e0 valid read 4. read address 0x7c1f valid read 5. read address 0x703f valid read 6. read address 0x4b46 autostore enable if the autostore ? function is disabled or re-enabled a manual store operation (hardware or software) needs to be issued to save the autostore state through subsequent power down cycles. the part comes from the factory with autostore ? enabled.
stk14ca8 december 2005 document control #ml0022 rev 1.3 15 extended tempurature range the stk14ca8 is offered in an extended temperature range part num ber. this part number is tested from -55oc to +85oc. this range is extended from the standard industrial range device on the maximum cold temperature specification. all of the industrial specifications in this datasheet apply to the extended temperature range device except for the maximum number of store (endurance) cycles . the maximum number of store cycles for the extended temperature range device is 100k cycles.
stk14ca8 december 2005 document control #ml0022 rev 1.3 16 ordering information stk14ca8 ? r f 45 i temperature range blank = commercial (0 to 70oc) i = industrial (-40 to 85oc) g = extended (-55 to 85oc) access time 25 = 25ns 35 = 35ns 45 = 45ns lead finish blank = 85% sn / 15% pb f = 100% sn (matte tin) rohs compliant package n = plastic 32-pin 300 mil soic (50 mil pitch) r = plastic 48-pin 300 mil ssop (25 mil pitch)
stk14ca8 december 2005 document control #ml0022 rev 1.3 17 document revision history revision date summary 0.0 january 2003 publish new datasheet 0.1 may 2003 add 48 pin ssop, modify autostore drawing (figure 2), update mode selection table and absolute maximum ratings, added g control software store. 0.2 september 2003 added lead-free lead finish 1.0 december 2004 parameter old value new value notes vcap min 10f 17 f t vccrise na 150 s new spec i cc1 max com. 35 ma 50 ma @ 45ns access i cc1 max com. 40 ma 55 ma @ 35ns access i cc1 max com. 50 ma 65 ma @ 25ns access i cc1 max ind. 35 ma 55 ma @ 45ns access i cc1 max ind. 45 ma 60 ma @ 35ns access i cc1 max ind. 55 ma 70 ma @ 25ns access i cc2 max 1.5 ma 3.0 ma com. & ind. i cc4 max 0.5 ma 3 ma com & ind. t hrecall 5 ms 20 ms t store 10 ms 12.5 ms t recall 20s 40s t glqv 10ns 12ns 25 ns device 1.1 august 2005 removed plastic dip 32 pin package offering. package type ?w?. parameter old value new value notes i cc3 max com. 5 ma 10 ma i cc3 max ind. 5 ma 10 ma i sb max com. 2 ma 3 ma i sb max ind. 2 ma 3 ma t recall 40 s 50 s soft recall t store 12.5 ms 15 ms industrial grade only max. store cycles 1x10 6 5x10 5 contact simtek for details. 1.2 september 2005 added an extended temperature range device tested from -55oc to +85oc. 1.3 december 2005 parameter old value new value notes t recall 60 s 50 s typographical error in datasheet t ss undefined 70 s data r 100 years at unspecified temperature 20 years @ max temperature data retention new specification simtek stk14ca8 data sheet, december 2005 copyright 2005, simtek corporation. all rights reserved. this datasheet may only be printed for the express use of simtek customers. no part of this datasheet may be reproduced in any other form or means without express written permission from simtek corporation. the information contained in this publication is believed to be accurate, but changes may be made without notice. simtek does not assume responsibility for, or grant or imply any warranty, including merch antability or fitness for a particular purpose regarding this information, the product or its use. nothing herein constitutes a license, grant or transfer of any rights to any simtek patent, copyright, trademark or other proprietary right.

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