NJU8761 -1- ver.2006-06-19 analog signal input monaural class-d power amplifier for piezo speaker general description the NJU8761 is an analog signal input monaural class-d amplifier for piezo speaker. the NJU8761 incorporates btl amplifiers, which eliminate ac coupling capacitor. the input block operates on 2.6v(min.) as power supply and the output block operates up to 12v, therefore it can output close to 17.5v p-p amplified signal and drive piezo speaker with louder sound and high efficiency. class-d operation achieves lower power operation for piezo speaker, thus the NJU8761 is suited for battery-powered applications such as cellular phone and pda. features piezo speaker driving output voltage 6.2 vrms (typ.) @v ddo =10 v, thd+n=10% analog input, monaural btl output standby(hi-z), mute control built-in low voltage detector for v dd & v ddo operating voltage input block: 2.6~3.6v(v dd ) output block: 8.0~12.0v(v ddo ) cmos technology package outline qfn20-m1 pin configuration NJU8761km1 package outline preliminary v ss boost nfin in v ss com v dd r osc c osc muteb nc test test test stbyb v ddo out n v ss out p v ddo 1 5 6 10 11 15 16 20
NJU8761 - 2 - ver.2006-06-19 block diagram v dd v ss muteb control logic test r osc c osc stbyb pulse width modulator 2.8 v ddo v ss v ss v ddo out n out p + - + - com in nfin low voltage detector osc boost
nju3555 nju3555 NJU8761 -3- ver.2006-04-04 pin description no. symbol i/o function 1 boost i/o input capacitor charge terminal 2 nfin i/o input amplifier gain setting terminal 3 in i signal input terminal 4,9,18 v ss - power gnd: v ss =0v 5 com - analog common 6 v dd - power supply 7 r osc i resistor connection terminal for oscillator 8 c osc i capacitor connection terminal for oscillator 10 muteb i mute control h: normal operation, l: mute on 11 stbyb i standby control h: normal operation, l: standby on 12,13,14 test i maker test terminal l: normal operation 15 nc - non connection 16,20 v ddo - output power supply: v ddo =max.12v 17 out p o positive signal output terminal 19 out n o negative signal output terminal note 1) pin no. 4,9,18(v ss ) should be connected at the nearest point of the ic on the pcb. note 2) pin no.16, 20(v ddo ) should be connected at the nearest point of the ic on the pcb.
NJU8761 - 4 - ver.2006-06-19 function description (1) power supply v dd : power supply for input amplifier in power amplifier block and pwm(pulse width modulator)circuit block. v ddo : power supply for output drivers in power amplifier block. (2) standby control by setting the stbyb pin to ?l? level, it switches the NJU8761 into standby condition. during the standby condition, output pins (out p , out n ) become high impedance. keep the stbyb pin to ?l? level at least 41ms once switched into the standby condition. for normal operation, the stbyb pin requires ?h? level. note 3) the stbyb pin must be required into ?l? level at power-on. (3) boost function the boost function provides the pop-noise reduction on startup by charging the input capacitor(c c ) to the same voltage of the com pin. the charging needs 41ms since the stbyb pin has been changed to ?h? level from ?l? level. (4) mute control by setting the muteb pin to ?l? level, it switches the NJU8761 into mute condition. during the mute condition, output pins (out p , out n ) output the pwm waves (duty 50%). note 4) the NJU8761 has a built-in circuit for the pop-noise reduction at power-on. however the control with the following sequence can realize more effective the pop-noise reduction. (5) power supply voltage detection circuit to prevent an irregular oscillation in the internal circuit, the NJU8761 ceases operating when power supply voltage reaches the detection voltage as shown below. detection circuits in v dd and v ddo blocks work individually and each operation is as shown below. note 5) output blocks become high-impedance during halts. when v dd > > > > approx 1.8v and v ddo < < < < approx 5.0v , only output block is halted. when v dd > > > > approx 1.6v , the whole circuits are halted.(if v dd is recovered, the NJU8761 restarts after 41ms as same as the standby-off. v dd v ddo operating start-voltage around 1.8v around 5.5v operating halt-voltage around 1.6v around 5.0v 41ms or further power-on stbyb mute data mute data required before standby-on muteb mute data
nju3555 nju3555 NJU8761 -5- ver.2006-04-04 (6) power amplifier (6-1) input signal the amount of current passing through a capacitive load increases proportionately with frequency of audio signal. input filters should be put in the input line to reduce load current at high frequency-band. the input filters are composed of 1st-order rc lpf(low pass filter) and 1st-order rc hpf(high pass filter). f ch1 (cut-off frequency of hpf) and f cl1 (cut-off frequency of lpf) are determined by input resistance(r in ), resistor for lpf(r lpf ), capacitor for lpf(c lpf ) and ac coupling capacitor(c c ). when r in =10k ? , r lpf =3k ? and c lpf =0.01f, c c =2.2f, f ch1 and f cl1 are roughly calculated as following expressions. (6-2) output signal the output signals are pwm signals, which will be converted to analog signal via external 2nd-order or higher lc filter. to reduce the current consumption with signal-input close to cutoff-frequency of lpf(f c ). damping resistor should be connected between out p pin and coil, and between out n pin and coil. note 6) q(the gain of lpf at f c ) should be within 1 with settings of l, c and r damp . when l=22f, cl=1.1f, r damp =4.3 ? and equivalent series resistance(r dcr )=0.21 ? , cut-off frequency of lpf(fc) and q are roughly calculated as following expressions. (6-3) voltage gain the voltage gain is estimated by multiplying the voltage gain of input amplifier by the gain of pwm circuit and the gain of btl output stages. the gain of pwm circuit is 2.8 times and the gain of btl output stage is twofold. the voltage gain of input amplifier is determined by the ratio of negative feedback resistor (rfb connected with nfin pin) versus external input resistor (r in connected with in pin). note 7) the negative feedback resistor (r fb ) must be set 10k ? or further. in addition, due to the limitation of phase-margin, the gain of input amplifier must be one time or further. when input resistor is 10k ? and negative feedback resistor is 39k ? , total voltage gain is roughly calculated as following. voltage gain = 39k ? / 10k ? x 2.8 x 2 = 21.8 times ? 26db note 8) the maximum output amplitude is approx ?v dd x0.7 [v pp ]?. when the gain of input amplifier is one time, maximum input amplitude is ?v dd x0.7 / 1 [v pp ]?. if input signal exceeds maximum input amplitude, output waveform must be distorted. (6-4) oscillation frequency the oscillation frequency is determined by r osc (connected with r osc pin), c osc (connected with c osc pin) and power supply (v dd ). note 9) 250khz 20khz is recommended for oscillation frequency. the following conditions would be suitable at this frequency. (v dd is 2.85v, r osc is 180k ? and c osc is 390pf) [hz] 6 . 5 10 2 . 2 ) 10 3 10 10 ( 3.14 2 1 ) ( 2 1 6 - 3 3 ch1 ? + = + = c l p f in c r r f [khz] 9 . 6 10 01 . 0 ) 10 3 // 10 10 ( 3.14 2 1 ) // ( 2 1 6 - 3 3 cl1 ? = = l p f l p f in c r r f [khz] 23 10 1 . 1 10 22 2 3.14 2 1 2lc 2 1 c 6 - 6 - l ? = = f ( ) ( ) .70 0 10 1 . 1 2 10 22 21 . 0 3 . 4 1 2 1 q 6 - -6 ? + = + = l d cr d am p c l r r ] [ 255 10 180 10 390 5 . 8 85 . 2 3 . 3 5 . 8 3 . 3 3 12 - khz r c v f osc osc d d osc ? + = + =
NJU8761 - 6 - ver.2006-06-19 absolute maximum ratings (ta=25 c) parameter symbol rating unit v dd -0.3 ~ +4.0 v supply voltage v ddol v ddor -0.3 ~ +18.0 v input voltage vin -0.3 ~ v dd +0.3 v operating temperature topr -40 ~ +85 c storage temperature tstg -40 ~ +125 c power dissipation p d 620 mw * :.mounted on two-layer board based on jedec note10) all voltage are relative to ?v ss =0v? reference. the lsi must be used within the ?absolute maximum ratings?. otherwise, a stress may cause permanent damage to the lsi. note11) de-coupling capacitors for v dd -v ss and v ddo -v ss should be connected for stable operation. note12) mounted on pcb (50mm x 50mm x 1.6mm) electrical characteristics (ta=25 c, v dd =2.85v, v ddo =10.0v, v ss =0v,test=0v stbyb=muteb=2.85v,input signal=1khz, input signal level=250mvrms, frequency band=20hz~20khz, load impedance=1.1 f, 2nd-order 23khz lc filter(q=0.70)) r osc =180k ? , c osc =390pf, r in =10k ? , r fb =39k ? parameter symbol conditions min typ max unit v dd supply voltage v dd 2.6 2.85 3.6 v v ddo supply voltage v ddo 8.0 10.0 12.0 v voltage gain a v - 26 - db thd+n thd input signal level =250mvrms - 0.3 0.8 % output voltage vo output thd=10% - 6.2 - vrms operating current(stanby) i st stbyb=0v - - 1 a i dd - 1.5 3 operating current (no signal input) i ddo no-load operating no signal input - 1 2 ma v ih muteb, stbyb pins 1.5 - v dd v input voltage v il muteb, stbyb pins 0 - 0.3 v input leakage current i lk en, mode pins - - 1.0 a note13) test system of the output thd+n the output thd+n is tested in the system shown in figure 1, where a 2nd-order lc lpf and another filter incorporated in an audio analyzer are used. 2nd-order lpf : refer to ?typical application circuit?. filters : 22hz hpf + 20khz lpf(aes17) input signal thd measuring apparatus filte r 20khz (aes17) 2nd-order lc lpf NJU8761 test board audio analyzer figure 1. thd+n test system NJU8761
nju3555 nju3555 NJU8761 -7- ver.2006-04-04 typical application circuit note 13) vdd power-on must be applied before v ddo power-on. note 14) (1) to (20) indicates pin numbers. note 15) de-coupling capacitors must be connected between each power-supply pin and gnd. the capacitance should be adjusted on the application circuit and the operation temperature. it may malfunction if capacitance is small. note 16) the transition time for stbyb and muteb signals must be less than 100 s. otherwise, a multifunction may be caused. note 17) external coils, diodes, capacitors and resistors should be connected at the nearest point to the ic. note 18) the above circuit shows only application example and does not guarantee any electrical characteristic. cut-off frequency of the lc filter influences the quality of sound. therefore, please test the circuit carefully to fit your application. NJU8761 out p (17) out n (19) v dd (6) v ss (4) v dd nfin(2) com(5) in test(12) stbyb(11) v ss (9) muteb(10) c osc (8) r osc (7) in(3) 1.1f 22h 22h 4.3 ? 4.3 ? c osc 390pf 1f c lpf 0.01f c c 2.2f 0.1f 0.1f 10f 10k ? 3k ? r osc 180k ? piezo speaker 39k ? r damp r damp l(r dcr =0.21 ? ) r in r fb v ddo ( 16,20 ) v ss (18) 0.1f 10f v ddo l(r dcr =0.21 ? ) r lpf boost(1) test(13) test(14) [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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