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? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram mt58l2my18d_16_b.fm - rev. b, pub. 1/03 1 ?2003, micron technology inc. 36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance ? 36mb syncburst ? sram mt58l2my18d, mt58v2mv18d, mt58l1my32d, mt58v1mv32d, mt58l1my36d, mt58v1mv36d 3.3v v dd , 3.3v or 2.5v i/o; 2.5v v dd , 2.5v i/o features ? fast clock and oe# access times single 3.3v 5 percent or 2.5v 5 percent power supply separate 3.3v 5 percent or 2.5v 5 percent isolated output buffer supply (v dd q) snooze mode for reduced-power standby common data inputs and data outputs individual byte write control and global write three chip enables for simple depth expansion and address pipelining clock-controlled and registered addresses, data i/os, and control signals internally self-timed write cycle automatic power-down burst control (interleaved or linear burst) low capacitive bus loadin g part number example: mt58l1my36dt-10 general description the micron ? syncburst ? sram family employs high-speed, low-power cmos designs that are fabri- cated using an advanced cmos process. micron?s 36mb syncburst srams integrate a 2 meg x 18, 1 meg x 32, or 1 meg x 36 sram core with advanced synchronous peripheral circuitry and a 2-bit burst counter. all synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (clk). the synchronous inputs include all addresses, all data inputs, active low chip enable options tqfp marking timing (access/cycle/mhz) 3.1ns/5ns/200 mhz 3.5ns/6ns/166 mhz 4.2ns/7.5ns/133 mhz 5ns/10ns/100 mhz -5 -6 -7.5 -10 configurations 3.3v v dd , 3.3v or 2.5v i/o 2 meg x 18 1 meg x 32 1 meg x 36 mt58l2my18d mt58l1my32d mt58l1my36d 2.5v v dd , 2.5v i/o 2 meg x 18 1 meg x 32 1 meg x 36 mt58v2mv18d mt58v1mv32d mt58v1mv36d packages 100-pin, 16mm x 22.1mm tqfp t 165-ball, 13mm x 15mm fbga f 1 note: 1. a part marking guide for the fbga devices can be found on micron?s web site? http://www.micron.com/numberguide. operating temperature range commercial (0oc t a +70oc industrial (-40oc t a +85oc) none it 2 2. contact factory for availability of industrial temperature devices. figure 1: 100-pin tqfp jedec-standard ms-026 bha (lqfp) figure 2: 165-ball fbga jedec-standard mo-216 (var. cab-1)
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 2 ?2003, micron technology inc. (ce#), two additional chip enables for easy depth expansion (ce2, ce2#), burst control inputs (adsc#, adsp#, adv#), byte write enables (bwx#), and global write (gw#). asynchronous inputs include the output enable (oe#), clock (clk) and snooze enable (zz). there is also a burst mode input (mode) that selects between interleaved and linear burst modes. the data-out (q), enabled by oe#, is also asynchronous. write cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. burst operation can be initiated with either address status processor (adsp#) or address status controller (adsc#) inputs. subsequent burst addresses can be internally generated as controlled by the burst advance input (adv#). address and write control are registered on-chip to simplify write cycles. this allows self-timed write cycles. individual byte enables allow individual bytes to be written. during write cycles on the x18 device, bwa# controls dqa pins/balls and dqpa; bwb# con- trols dqb pins/balls and dqpb. during write cycles on the x32 and x36 devices, bwa# controls dqa pins/ balls and dqpa; bwb# controls dqb pins/balls and dqpb; bwc# controls dqc pins/balls and dqpc; bwd# controls dqd pins/balls and dqpd. gw# low causes all bytes to be written. parity bits are only available on the x18 and x36 versions. this device incorporates an additional pipelined enable register which delays turning off the output buffer an additional cycle when a deselect is executed. this feature allows depth expansion without penaliz- ing system performance. micron?s 36mb syncburst srams operate from a 3.3v or 2.5v v dd power supply, and all inputs and outputs are lvttl-compatible. users can use either a 3.3v or 2.5v i/o, depending on the v dd voltage. the device is ideally suited for pentium ? and powerpc pipelined systems and systems that benefit from a very wide, high-speed data bus. the device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applications. please refer to micron?s web site ( www.micron.com/ sramds ) for the latest data sheet. dual voltage i/o the 3.3v v dd device is tested for 3.3v and 2.5v i/o function. the 2.5v v dd device is tested for only 2.5v i/o function.
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 3 ?2003, micron technology inc. figure 3: functional block diagram 2 meg x 18 figure 4: functional block diagram 1 meg x 32/36 note: functional block diagrams illustrate simplified device operation. see truth tables, pin/ball descriptions, and tim- ing diagrams for detailed information. sa0, sa1, sas address register adv# clk binary counter and logic clr q1 q0 adsc# 21 21 19 21 bwb# bwa# ce# byte ?b? write register byte ?a? write register enable register sa0' sa1' oe# sense amps 2 meg x 9 x 2 memory array adsp# 2 sa0-sa1 mode ce2 ce2# gw# bwe# pipelined enable dqs dqpa dqpb 2 output registers input registers e byte ?b? write driver byte ?a? write driver output buffers 9 9 9 9 18 18 18 18 18 address register adv# clk binary counter clr q1 q0 adsp# adsc# mode 20 20 18 20 bwd# bwc# bwb# bwa# bwe# gw# ce# ce2 ce2# oe# byte ?d? write register byte ?c? write register byte ?b? write register byte ?a? write register enable register pipelined enable dqs dqpa dqpb dqpc dqpd 4 output registers sense amps 1 meg x 8 x 4 (x32) 1 meg x 9 x 4 (x36) memory array output buffers e byte ?a? write driver byte ?b? write driver byte ?c? write driver byte ?d? write driver input registers sa0, sa1, sas sa0' 9 9 9 9 9 9 36 36 36 36 36 9 9 sa1' sa0-sa1
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 4 ?2003, micron technology inc. figure 5: pin layout (top view) 100-pin tqfp note: 1. no function (nf) is used on the x32 versio n. parity (dqpx) is used on the x36 version. 2. pin 38 is reserved for 72mb address expansion. sa sa adv# adsp# adsc# oe# (g#) bwe# gw# clk v ss v dd ce2# bwa# bwb# nc nc ce2 ce# sa sa 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 sa nc nc v dd q v ss nc dqpa dqa dqa v ss v dd q dqa dqa v ss nc v dd zz dqa dqa v dd q v ss dqa dqa nc nc v ss v dd q nc nc nc sa sa sa sa sa sa sa sa sa v dd v ss sa dnu 2 sa0 sa1 sa sa sa sa mode (lbo#) nc nc nc v dd q v ss nc nc dqb dqb v ss v dd q dqb dqb nc v dd nc v ss dqb dqb v dd q v ss dqb dqb dqpb nc v ss v dd q nc nc nc x18 sa sa adv# adsp# adsc# oe# (g#) bwe# gw# clk v ss v dd ce2# bwa# bwb# bwc# bwd# ce2 ce# sa sa 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 nf/ dqpb 1 dqb dqb v dd q v ss dqb dqb dqb dqb v ss v dd q dqb dqb v ss nc v dd zz dqa dqa v dd q v ss dqa dqa dqa dqa v ss v dd q dqa dqa nf/ dqpa 1 sa sa sa sa sa sa sa sa sa v dd v ss sa dnu 2 sa0 sa1 sa sa sa sa mode (lbo#) nf/ dqpc 1 dqc dqc v dd q v ss dqc dqc dqc dqc v ss v dd q dqc dqc nc v dd nc v ss dqd dqd v dd q v ss dqd dqd dqd dqd v ss v dd q dqd dqd nf/ dqpd 1 x32/x36
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 5 ?2003, micron technology inc. table 1: tqfp pin descriptions symbol type description adv# input synchronous address advance: this active low input is used to advance the internal burst counter, controlling burst access a fter the external address is loaded. a high on this pin effectively causes wait states to be generated (no address advance). to ensure use of correct address during a write cycle, adv# must be high at the rising edge of the first clock after an adsp# cycle is initiated. adsp# input synchronous address status processor: this active low input interrupts any ongoing burst, causing a new external address to be registered. a read is performed using the new address, independent of the byte write enables and adsc#, but dependent upon ce#, ce2, and ce2#. adsp# is ignored if ce# is high. power-down st ate is entered if ce2 is low or ce2# is high. adsc# input synchronous address status controller: this ac tive low input interrupts any ongoing burst, causing a new external address to be registe red. a read or write is performed using the new address if ce# is low. adsc# is also used to place the chip into power-down state when ce# is high. bwa# bwb# bwc# bwd# input synchronous byte write enables: these active low inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of clk. a byte write enable is low for a write cycle and high for a read cycle. for the x18 version, bwa# controls dqa pins and dqpa; bwb# controls dqb pins and dqpb. for the x32 and x36 versions, bwa# controls dqa pins and dqpa; bwb# controls dqb pins and dqpb; bwc# controls dqc pins and dqpc; bwd# controls dqd pins and dqpd. parity is only available on the x18 and x36 versions. bwe# input byte write enable: this active low input permits byte write operations and must meet the setup and hold times around the rising edge of clk. ce# input synchronous chip enable: this active low input is used to enable the device and conditions the internal use of adsp#. ce# is sampled on ly when a new external address is loaded. ce2# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded. ce2 input synchronous chip enable: this active high input is used to enable the device and is sampled only when a new external address is loaded. clk input clock: this signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. all synchronous inputs must meet setup and hold times around the clock?s rising edge. gw# input global write: this active low input allows a full 18-, 32-, or 36-bit write to occur independent of the bwe# and bwx# lines and must meet the setup and hold times around the rising edge of clk. mode (lbo#) input mode: this input selects the burst sequence. a low on this pin selects ?linear burst.? nc or high on this pin selects ?interleaved burst.? do not alter input state while device is operating. lbo# is the jedec-standard term for mode. oe# (g#) input output enable: this active low, asynchronous inpu t enables the data i/o output drivers. g# is the jedec-standard term for oe#. sa0 sa1 sa input synchronous address inputs: these inputs are re gistered and must meet the setup and hold times around the rising edge of clk. zz input snooze enable: this active high, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. when zz is active, all other inputs are ignored. this pin has an internal pull-down and can be left unconnected. dqa dqb dqc dqd input/ output sram data i/os: for the x18 version, byte ?a? is associated with dqa pins; byte ?b? is associated with dqb pins. for the x32 and x36 ve rsions, byte ?a? is associated with dqa pins; byte ?b? is associated with dqb pins; byte ?c? is associated with dqc pins; byte ?d? is associated with dqd pins. input data must meet setup and hold times around the rising edge of clk.
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 6 ?2003, micron technology inc. nf/ dqpa nf/ dqpb nf/ dqpc nf/ dqpd nf i/o no function/parity data i/os: on the x32 version, these pins are no function (nf). on the x18 version, byte ?a? parity is dqpa; byte ?b? parity is dqpb. on the x36 version, byte ?a? parity is dqpa; byte ?b? parity is dqpb; byte ?c? pa rity is dqpc; byte ?d? parity is dqpd. no function pins are internally connected to the die and have the capacitance of an input pin. it is allowable to leave these pins unconnected or driven by signals. v dd supply power supply: see dc electrical characteristics and operating conditions for range. v dd q supply isolated output buffer supply: see dc electri cal characteristics and operating conditions for range. v ss supply ground: gnd. dnu ? do not use: these signals may either be un connected or wired to gnd to improve package heat dissipation. nc ? no connect: these signals are not internally connected and may be connected to ground to improve package heat dissipation. table 1: tqfp pin descriptions (continued) symbol type description
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 7 ?2003, micron technology inc. figure 6: ball layout (top view) 165-ball fbga x18 x32/x36 note: 1. no function (nf) is used on the x32 versio n. parity (dqpx) is used on the x36 version. 2. ball 2p is reserved for 72mb address expansion. a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 2 ce# ce2 v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqb dqb dqb dqb v ss nc nc nc nc nc nc 2 sa nc nc nc nc nc nc nc v dd dqb dqb dqb dqb dqpb nc mode (lbo#) bwb# nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa nc bwa# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc td1 tms ce2# clk v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss sa sa1 sa0 bwe# gw# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss td0 tck adsc# oe# (g#) v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa adv# adsp# v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc nc nc nc nc nc dqa dqa dqa dqa nc sa sa sa nc dqpa dqa dqa dqa dqa zz nc nc nc nc nc sa sa top view 3456789 10 11 1 a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 2 ce# ce2 v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqc dqc dqc dqc v ss dqd dqd dqd dqd nc nc 2 sa nc nc nf/ dqpc 1 dqc dqc dqc dqc v dd dqd dqd dqd dqd nf/ dqpd 1 nc mode (lbo#) bwc# bwd# v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa bwb# bwa# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss nc td1 tms ce2# clk v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss sa sa1 sa0 bwe# gw# v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss td0 tck adsc# oe# (g#) v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss sa sa adv# adsp# v dd q v dd q v dd q v dd q v dd q nc v dd q v dd q v dd q v dd q v dd q sa sa sa sa nc dqb dqb dqb dqb nc dqa dqa dqa dqa nc sa sa nc nc nf/ dqpb 1 dqb dqb dqb dqb zz dqa dqa dqa dqa nf/ dqpa 1 sa sa top view 3456789 10 11 1
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 8 ?2003, micron technology inc. table 2: fbga ball descriptions symbol type description adv# input synchronous address advance: this active low input is used to advance the internal burst counter, controlling burst access after the ex ternal address is loaded. a high on adv# effectively causes wait states to be generated (no address advance). to ensure use of correct address during a write cycle, adv# must be high at the rising edge of the first clock after an adsp# cycle is initiated. adsp# input synchronous address status processor: this ac tive low input interrupts any ongoing burst, causing a new external address to be registered. a read is performed using the new address, independent of the byte write enables and adsc#, but dependent upon ce#, ce2, and ce2#. adsp# is ignored if ce# is high. power-down state is entered if ce2 is low or ce2# is high. adsc# input synchronous address status controller: this active low input inte rrupts any ongoing burst, causing a new external address to be regist ered. a read or write is performed using the new address if ce# is low. adsc# is also used to place the chip into power-down state when ce# is high. bwa# bwb# bwc# bwd# input synchronous byte write enables: these active low inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of clk. a byte write enable is low for a write cycle and high for a read cycle. for the x18 version, bwa# controls dqa balls and dqpa; bwb# controls dqb balls and dqpb. for the x32 and x36 versions, bwa# controls dqa balls and dqpa; bwb# controls dqb balls and dqpb; bwc# controls dqc balls and dqpc; bwd# controls dqd balls and dqpd. parity is only available on the x18 and x36 versions. bwe# input byte write enable: this active low input perm its byte write operations and must meet the setup and hold times around the rising edge of clk. ce# input synchronous chip enable: this active low input is used to enable the device and conditions the internal use of adsp#. ce# is sampled only when a new external address is loaded. ce2# input synchronous chip enable: this active low input is used to enable the device and is sampled only when a new external address is loaded. clk input clock: this signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. all sync hronous inputs must meet setup and hold times around the clock?s rising edge. clk input clock: this signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. all sync hronous inputs must meet setup and hold times around the clock?s rising edge. gw# input global write: this active low input allows a full 18-, 32- or 36-bit write to occur independent of the bwe# and bwx# lines and must meet the setup and hold times around the rising edge of clk. mode (lb0#) input mode: this input selects the burst sequence. a low on this ball selects ?linear burst.? nc or high on this input selects ?interleaved burst.? do not alter input state while device is operating. lbo# is the jedec-standard term for mode. oe# (g#) input output enable: this active low, asynchronous i nput enables the data i/o output drivers. g# is the jedec-standard term for oe#. sa0 sa1 sa input synchronous address inputs: these inputs are registered and must meet the setup and hold times around the rising edge of clk. tms tdi tck input ieee 1149.1 test inputs: jedec-standard 2.5v i/o levels. these balls may be left as no connects if the jtag function is not used in the circuit. zz input snooze enable: this active high, asynchronous i nput causes the device to enter a low-power standby mode in which all data in the memory a rray is retained. when zz is active, all other inputs are ignored. this ball has an internal pull-down and can be left unconnected.
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 9 ?2003, micron technology inc. dqa dqb dqc dqd input/ output sram data i/os: for the x18 version, byte ?a? is associated dqa balls; byte ?b? is associated with dqb balls. for the x32 and x36 versions, byte ?a? is associated with dqa balls; byte ?b? is associated with dqbs; byte ?c? is associated with dqc balls; byte ?d? is associated with dqd balls. input data must meet setup and hold times around the rising edge of clk. nf/ dqpa nf/ dqpb nf/ dqpc nf/ dqpd nf i/o no function/parity data i/os: on the x32 ve rsion, these are no function (nf). on the x18 version, byte ?a? parity is dqpa; byte ?b? parity is dqpb. on the x36 version, byte ?a? parity is dqpa; byte ?b? parity is dqpb; byte ?c? pa rity is dqpc; byte ?d? parity is dqpd. no function balls are internally connected to the die and have the capacitance of an input ball. it is allowable to leave these balls unconnected or driven by signals. tdo output ieee 1149.1 test output: jedec-standard 2.5v i/o level. v dd supply power supply: see dc electrical characteristics and operating conditions for range. v dd q supply isolated output buffer supply: see dc electrical characteristics and operating conditions for range. v ss supply ground: gnd. nc ? no connect: these signals are not internally connected and may be connected to ground to improve package heat dissipation. table 2: fbga ball descriptions (continued) symbol type description
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 10 ?2003, micron technology inc. note: using bwe# and bwa# through bwd#, any one or more bytes may be written. note: using bwe# and bwa# through bwd#, any one or more bytes may be written. table 3: interleaved burst address table (mode = nc or high) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x00 x...x11 x...x10 x...x10 x...x11 x...x00 x...x01 x...x11 x...x10 x...x01 x...x00 table 4: linear burst address table (mode = low) first address (external) second address (internal) third address (internal) fourth address (internal) x...x00 x...x01 x...x10 x...x11 x...x01 x...x10 x...x11 x...x00 x...x10 x...x11 x...x00 x...x01 x...x11 x...x00 x...x01 x...x10 table 5: partial truth table for write commands (x18) function gw# bwe# bwa# bwb# read hhxx read hlhh write byte ?a? hl lh write byte ?b? hlhl write all bytes hlll write all bytes lxxx table 6: partial truth table for write commands (x32/x36) function gw# bwe# bwa# bwb# bwc# bwd# read hhxxxx read h l hhhh write byte ?a? h l l hhh write all bytes hlllll write all bytes lxxxxx
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 11 ?2003, micron technology inc. note: 1. x means ?don?t care.? # means active low. h means logic high. l means logic low. 2. for write#, l means any one or more byte write enable signals (bwa#, bwb#, bwc#, or bwd#), and bwe# are low or gw# is low. write# = h for all bwx#, bwe#, gw# high. 3. bwa# enables writes to dqa pins/balls and dqpa. bwb# enables writes to dqb pins/balls and dqpb. bwc# enables writes to dqc pins/balls and dqpc. bwd# enables writes to dqd pins/balls and dqpd. dqpa and dqpb are only avail- able on the x18 and x36 versions. dqpc and dqpd are only available on the x36 version. 4. all inputs except oe# and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, oe# mu st be high before the input data setup time and held high throughout the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high-z during power-up. 8. adsp# low always initiates an internal read at the l-h edge of clk. a write is performed by setting one or more byte write enable signals and bwe# low or gw# low for the subsequent l-h edge of clk. refer to write timing diagram for clarification. table 7: truth table notes 1?8 operation address used ce# ce2# ce2 zz adsp# adsc# adv# write# oe# clk dq deselect cycle, power-down none h x x l x l x x x l-h high-z deselect cycle, power-down none l x l l l x x x x l-h high-z deselect cycle, power-down none l h x l l x x x x l-h high-z deselect cycle, power-down none l x l l h l x x x l-h high-z deselect cycle, power-down none l h x l h l x x x l-h high-z snooze mode, power-down none x x x h x x x x x x high-z read cycle, begin burst external l l h l l x x x l l-h q read cycle, begin burst external l l h l l x x x h l-h high-z write cycle, begin burst external l l h l h l x l x l-h d read cycle, begin burst external l l h l h l x h l l-h q read cycle, begin burst external l l h l h l x h h l-h high-z read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h high-z read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h high-z write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h high-z read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h high-z write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 12 ?2003, micron technology inc. absolute maximum ratings 3.3v v dd voltage on v dd supply relative to v ss ....................................... -0.5v to +4.6v voltage on v dd q supply relative to v ss ....................................... -0.5v to +4.6v v in (dqx) ....................................... -0.5v to v dd q + 0.5v v in (inputs) ....................................... -0.5v to v dd + 0.5v storage temperature (tqfp).................-55oc to +150oc storage temperature (fbga).................-55oc to +125oc junction temperature .......................................... +150oc short circuit output current ...............................100ma 2.5v v dd voltage on v dd supply relative to v ss ....................................... -0.3v to +3.6v voltage on v dd q supply relative to v ss ....................................... -0.3v to +3.6v v in (dqx) ....................................... -0.3v to v dd q + 0.3v v in (inputs) ....................................... -0.3v to v dd + 0.3v storage temperature (tqfp).................-55oc to +150oc storage temperature (fbga).................-55oc to +125oc junction temperature .......................................... +150oc short circuit output current ...............................100ma stresses greater than those listed may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum junction temperature depends upon package type, cycle time, loading, ambient tempera- ture, and airflow. see micron technical note tn-05-14 for more information. table 8: 3.3v v dd , 3.3v i/o dc electrical characteristics and operating conditions notes appear following parameter tables on page 17; 0oc t a +70oc; v dd and v dd q = 3.3v 0.165v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih 2.0 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.8 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 a 4 output leakage current output(s) disabled, 0v v in v dd il o -1.0 1.0 a output high voltage i oh = -4.0ma v oh 2.4 ? v 1, 5 output low voltage i ol = 8.0ma v ol ? 0.4 v 1, 5 supply voltage v dd 3.135 3.465 v 1 isolated output buffer supply v dd q3.135 v dd v1, 6
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 13 ?2003, micron technology inc. table 9: 3.3v v dd , 2.5v i/o dc electrical characteristics and operating conditions notes appear following parameter tables on page 17; 0oc t a +70oc; v dd = 3.3v 0.165v and v dd q = 2.5v 0.125v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage data bus (dqx) v ih q 1.7 v dd q + 0.3 v 1, 2 inputs v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -1.0 1.0 a 4 output leakage current output(s) disabled, 0v v in v dd q (dqx) il o -1.0 1.0 a output high voltage i oh = -2.0ma v oh 1.7 ? v 1, 5 i oh = -1.0ma v oh 2.0 ? v 1, 5 output low voltage i ol = 2.0ma v ol ? 0.7 v 1, 5 i ol = 1.0ma v ol ? 0.4 v 1, 5 supply voltage v dd 3.135 3.465 v 1 isolated output buffer supply v dd q 2.375 2.625 v 1, 6 table 10: 2.5v v dd , 2.5v i/o dc electrical characteristics and operating conditions notes appear following parameter tables on page 17; 0oc t a +70oc; v dd and v dd q = 2.5v 0.125v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage data bus (dqx) v ih q1.7v dd q + 0.3 v 1, 3 inputs v ih 1.7 v dd + 0.3 v 1, 3 input low (logic 0) voltage v il -0.3 0.7 v 1, 3 input leakage current 0v v in v dd il i -1.0 1.0 a 4 output leakage current output(s) disabled, 0v v in v dd q (dqx) il o -1.0 1.0 a output high voltage i oh = -2.0ma v oh 1.7 ? v 1, 5 i oh = -1.0ma v oh 2.0 ? v 1, 5 output low voltage i ol = 2.0ma v ol ? 0.7 v 1, 5 i ol = 1.0ma v ol ? 0.4 v 1, 5 supply voltage v dd 2.375 2.625 v 1 isolated output buffer supply v dd q 2.375 2.625 v 1, 6
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 14 ?2003, micron technology inc. table 11: tqfp capacitance note 7; notes appear following parameter tables on page 17 table 12: fbga capacitance note 7; notes appear following parameter tables on page 17 table 13: tqfp thermal resistance note 7; notes appear following parameter tables on page 17 table 14: fbga thermal resistance note 7; notes appear following parameter tables on page 17 description conditions symbol typ max units control input capacitance t a = 25oc; f = 1 mhz; v dd = 3.3v c i 4.2 5 pf input/output capacitance (dq) c o 3.5 4 pf address capacitance c a 45 pf clock capacitance c ck 4.2 5 pf description conditions symbol typ max units address/control input capacitance t a = 25oc; f = 1 mhz c i 45pf output capacitance (q) c o 44.5pf clock capacitance c17 5 5.5 pf description conditions symbol typ units thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. ja tbd oc/w thermal resistance (junction to top of case) jc tbd oc/w description conditions symbol typ units junction to ambient (airflow of 1m/s) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. ja tbd oc/w junction to case (top) jc tbd oc/w junction to balls (bottom) jb tbd oc/w
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 15 ?2003, micron technology inc. table 15: 3.3v v dd , i dd operating conditions and maximum limits (2 meg x 18 and 1 meg x 32/36) notes appear following parameter tables on page 17; 0oc t a +70oc; v dd 3.3v 0.165v and v dd q = 3.3v 0.165v or 2.5v 0.125v unless otherwise noted table 16: 2.5 v dd i dd operating conditions and maximum limits (2 meg x 18 and 1 meg x 32/36) notes appear following parameter tables on page 17; 0oc t a +70oc; v dd 3.3v 0.165v and v dd q = 3.3v 0.165v or 2.5v 0.125v unless otherwise noted max description conditions symbol typ -5 -6 -7.5 -10 units notes power supply current: operating device selected; all inputs v il or v ih ; cycle time t kc (min); v dd = max; outputs open i dd tbd 460 410 340 280 ma 8, 9, 10 power supply current: idle device selected; v dd = max; adsc#, adsp#, adv#, gw#, bwx# v ih ; all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min); outputs open i dd 1 tbd 255 220 195 175 ma 8, 9, 10 cmos standby device deselected; v dd = max; all inputs v ss + 0.2 or v dd - 0.2; all inputs static; clk frequency = 0 i sb 2 tbd30303030ma9, 10 clock running device deselected; v dd = max; adsc#, adsp#, adv#, gw#, bwx# v ih ; all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min) i sb 4 tbd 255 220 195 175 ma 9, 10 snooze mode zz v ih i sb 2z tbd30303030ma 10 max description conditions symbol typ -5 -6 -7.5 -10 units notes power supply current: operating device selected; all inputs v il or v ih ; cycle time t kc (min); v dd = max; outputs open i dd tbd 435 375 315 255 ma 8, 9, 11 power supply current: idle device selected; v dd = max; adsc#, adsp#, adv#, gw#, bwx# v ih ; all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min); outputs open i dd 1 tbd 230 200 170 145 ma 8, 9, 11 cmos standby device deselected; v dd = max; all inputs v ss + 0.2 or v dd - 0.2; all inputs static; clk frequency = 0 i sb 2 tbd30303030ma9, 11 clock running device deselected; v dd = max; adsc#, adsp#, adv#, gw#, bwx# v ih ; all inputs v ss + 0.2 or v dd - 0.2; cycle time t kc (min) i sb 4 tbd 230 200 170 145 ma 9, 11 snooze mode zz v ih i sb 2z tbd30303030ma 11
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 16 ?2003, micron technology inc. table 17: ac electrical characteristics and recommended operating conditions note 12; notes appear following parameter tables on page 17; 0oc t a +70oc; v dd = 3.3v 0.165v unless otherwise noted description sym -5 -6 -7.5 -10 units notes min max min max min max min max clock clock cycle time t kc 5.0 6.0 7.5 10 ns clock frequency f kf 200 166 133 100 mhz clock high time t kh 2.0 2.3 2.5 3.0 ns 13 clock low time t kl 2.0 2.3 2.5 3.0 ns 13 output times clock to output valid t kq 3.1 3.5 4.0 5.0 ns clock to output invalid t kqx 1.0 1.5 1.5 1.5 ns 14 clock to output in low-z t kqlz 0000ns7, 14, 15, clock to output in high-z t kqhz 3.1 3.5 4.2 5.0 ns 7, 14, 15 oe# to output valid t oeq 3.1 3.5 4.0 5.0 ns 16 oe# to output in low-z t oelz 0000ns7, 14, 15 oe# to output in high-z t oehz 3.0 3.0 3.5 4.5 ns 7, 14, 15 setup times address t as 1.4 1.5 1.5 2.0 ns 17, 18 address status (adsc#, adsp#) t adss 1.4 1.5 1.5 2.0 ns 17, 18 address advance (adv#) t aas 1.4 1.5 1.5 2.0 ns 17, 18 write signals (bwa#-bwd#, gw#, bwe#) t ws 1.4 1.5 1.5 2.0 ns 17, 18 data-in t ds 1.4 1.5 1.5 2.0 ns 17, 18 chip enable (ce#) t ces 1.4 1.5 1.5 2.0 ns 17, 18 hold times address t ah 0.4 0.5 0.5 0.5 ns 17, 18 address status (adsc#, adsp#) t adsh 0.4 0.5 0.5 0.5 ns 17, 18 address advance (adv#) t aah 0.4 0.5 0.5 0.5 ns 17, 18 write signals (bwa#-bwd#, gw#, bwe#) t wh 0.4 0.5 0.5 0.5 ns 17, 18 data-in t dh 0.4 0.5 0.5 0.5 ns 17, 18 chip enable (ce#) t ceh 0.4 0.5 0.5 0.5 ns 17, 18
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 17 ?2003, micron technology inc. notes 1. all voltages referenced to v ss (gnd). 2. for 3.3v v dd : overshoot: v ih +4.6v for t t kc/2 for i 20ma undershoot: v il -0.7v for t t kc/2 for i 20ma power-up: v ih +3.6v and v dd 3.135v for t 200ms 3. for 2.5v v dd : overshoot: v ih +3.6v for t t kc/2 for i 20ma undershoot: v il -0.5v for t t kc/2 for i 20ma power-up: v ih +2.65v and v dd 2.375v for t 200ms 4. the mode pin/ball has an internal pull-up, and input leakage = 10a. 5. the load used for v oh , v ol testing is shown in fig- ures 11 and 12 for 3.3v i/o, and figures 13 and 14 for 2.5v i/o. ac load current is higher than the stated dc values. ac i/o curves are available upon request. 6. v dd q should never exceed v dd . v dd and v dd q can be connected together. 7. this parameter is sampled. 8. i dd is specified with no output current and increases with faster cycle times. i dd q increases with faster cycle times and greater output loading. 9. ?device deselected? means device is in power- down mode as defined in the truth table. ?device selected? means device is active (not in power- down mode). 10. typical values are measured at 3.3v, 25 o c, and 10ns cycle time. 11. typical values are measured at 2.5v, 25 o c, and 10ns cycle time. 12. test conditions as specified with the output load- ing shown in figures 11 and 12 for 3.3v i/o, and figures 13 and 14 for 2.5v i/o unless otherwise noted. 13. measured as high above v ih and low below v il . 14. this parameter is measured with the output load- ing shown in figure 12 for 3.3v i/o and figure 14 for 2.5v i/o. 15. refer to technical note tn-58-09, ?synchronous sram bus contention design considerations,? for a more thorough discussion of these parame- ters. 16. oe# can be considered a ?don?t care? during writes; however, controlling oe# can help fine- tune a system for turnaround timing. 17. a write cycle is defined by r/w# low, having been registered into the device at adv/ld# low. a read cycle is defined by r/w# high with adv/ ld# low. both cases must meet setup and hold times. 18. this is a synchronous device. all addresses must meet the specified setup and hold times with sta- ble logic levels for all rising edges of clk when the chip is enabled. to remain enabled, chip enable must be valid at each rising edge of clk when adv/ld# is low.
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 18 ?2003, micron technology inc. figure 7: read timing note: 1. q(a2) refers to output from address a2. q(a2 + 1) refers to output from the next internal burst address following a2. 2. ce2# and ce2 have timing identical to ce#. on this diagram, when ce# is low, ce2# is low and ce2 is high. when ce# is high, ce2# is high and ce2 is low. 3. timing is shown assuming that the device was not enabled before entering into this sequence. oe# does not cause q to be driven until after the following clock rising edge. (this note applies to whole diagram.) 4. outputs are disabled two clock cycles after deselect. t kc t kl clk adsp# t adsh t adss address t kh oe# adsc# ce# (note 2) t ah t as a1 t ceh t ces gw#, bwe#, bwa#-bwd# q high-z t kqlz t kqx t kq adv# t oehz t kq single read burst read t oeq t oelz t kqhz burst wraps around to its initial state t aah t aas t wh t ws t adsh t adss q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a3) q(a2 + 3) a2 a3 (note 1) deselect cycle (note 3) burst continued with new base address (note 4) adv# suspends burst don?t care undefined
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 19 ?2003, micron technology inc. figure 8: write timing note: 1. d(a2) refers to output from address a2. d(a2 + 1) refers to output from the next internal burst address following a2. 2. ce2# and ce2 have timing identical to ce#. on this diagram, when ce# is low, ce2# is low and ce2 is high. when ce# is high, ce2# is high and ce2 is low. 3. oe# must be high before the input data setup and held high throughout the data hold time. this prevents input/ output data contention for the time period prior to the byte write enable inputs being sampled. 4. adv# must be high to permit a write to the loaded address. 5. full-width write can be initiated by gw# low; or gw # high and bwe#, bwa# and bwb# low for x18 device; or gw# high and bwe#, bwa#-bwd# low for x32 and x36 devices. t kc t kl clk adsp# t adsh t adss address t kh oe# adsc# ce# (note 2) t ah t as a1 t ceh t ces bwe#, bwa#-bwd# q high-z adv# burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 d extended burst write d(a2 + 2) single write t adsh t adss t adsh t adss t oehz t aah t aas t wh t ws t dh t ds (note 3) (note 1) (note 4) gw# t wh t ws (note 5) byte write signals are ignored for first cycle when adsp# initiates burst adsc# extends burst. adv# suspends burst don?t care undefined d(a1)
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 20 ?2003, micron technology inc. figure 9: read/write timing note: 1. q(a4) refers to output from address a4. q(a4 + 1) refers to output from the next internal burst address following a4. 2. ce2# and ce2 have timing identical to ce#. on this diagram, when ce# is low, ce2# is low and ce2 is high. when ce# is high, ce2# is high and ce2 is low. 3. the data bus (q) remains in high-z following a write cy cle unless an adsp#, adsc#, or adv# cycle is performed. (this note applies to whole diagram.) 4. gw# is high. 5. back-to-back reads may be controlled by either adsp# or adsc#. 6. this undefined read will follow any write cycle which is transitioned to a read, deselect, or snooze. t kc t kl clk adsp# t adsh t adss address t kh oe# adsc# ce# (note 2) t ah t as a2 t ceh t ces q high-z adv# single write d(a3) a4 a5 a6 d(a5) d(a6) d burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t wh t ws q(a4+3) t oehz t dh t ds t oelz (note 5) (note 1) t kqlz t kq back-to-back writes a1 bwe#, bwa#-bwd# (note 4) a3 don?t care undefined (note 6) (note 3)
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 21 ?2003, micron technology inc. snooze mode snooze mode is a low-current, power-down mode in which the device is deselected and current is reduced to i sb2z . the duration of snooze mode is dictated by the length of time zz is in a high state. after the device enters snooze mode, all inputs except zz become gated inputs and are ignored. zz is an asynchronous, active high input that causes the device to enter snooze mode. when zz becomes a logic high, i sb2z is guaranteed after the setup time t zz is met. any read or write operation pending when the device enters snooze mode is not guaranteed to complete successfully. therefore, snooze mode must not be initiated until valid pend- ing operations are completed. note: 1. this parameter is sampled. figure 10: snooze mode waveform table 18: snooze mode electrical characteristics description conditions symbol min max units notes current during snooze mode zz v ih i sb 2 z 30 ma zz active to input ignored t zz 2 ( t kc) ns 1 zz inactive to input sampled t rzz 2 ( t kc) ns 1 zz active to snooze current t zzi 2 ( t kc) ns 1 zz inactive to exit snooze current t rzzi 0ns1 t zz i supply clk zz t rzz all inputs (except zz) don?t care i isb2z t zzi t rzzi outputs (q) high-z deselect or read only
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 22 ?2003, micron technology inc. 3.3v v dd , 3.3v i/o ac test conditions input pulse levels ....................v ih = (v dd /2.2) + 1.5v ................................................... v il = (v dd /2.2) - 1.5v input rise and fall times......................................... 1ns input timing reference levels ........................ v dd /2.2 output reference levels................................v dd q/2.2 output load .............................. see figures 11 and 12 3.3v v dd , 2.5v i/o ac test conditions input pulse levels ................v ih = (v dd /2.64) + 1.25v ............................................... v il = (v dd /2.64) - 1.25v input rise and fall times......................................... 1ns input timing reference levels ...................... v dd /2.64 output reference levels...................................v dd q/2 output load .............................. see figures 13 and 14 2.5v v dd , 2.5v i/o ac test conditions input pulse levels .....................v ih = (v dd /2) + 1.25v .................................................... v il = (v dd /2) - 1.25v input rise and fall times......................................... 1ns input timing reference levels ........................... v dd /2 output reference levels..................................... v dd /2 output load .............................. see figures 13 and 14 load derating curves micron 2 meg x 18, 1 meg x 32, and 1 meg x 36 syncburst sram timing is dependent upon the capacitive loading on the outputs. consult the factory for copies of i/o current versus voltage curves. 3.3v i/o output load equivalents figure 11: figure 12: 2.5v i/o output load equivalents figure 13: figure 14: q 50 v = v dd q/2.2 z = 50 o t q 351 317 5pf +3.3v q 50 ? v = v dd q/2 z = 50 ? o t q 225 ? 225 ? 5pf +2.5v
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 23 ?2003, micron technology inc. ieee 1149.1 serial boundary scan (jtag) the sram incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 2.5v i/o logic levels. the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature these balls can be left floating (unconnected), if the jtag function is not to be implemented. upon power- up, the device will come up in a reset state which will not interfere with the operation of the device. figure 15: tap controller state diagram note: the 0/1 next to each state represents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see figure 15. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signifi- cant bit (msb) of any register. (see figure 16.) test data-out (tdo) the tdo output ball is used to serially clock data- out from the registers. the output is active depending upon the current state of the tap state machine. (see figure 15.) the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see figure 16.) figure 16: tap controller block diagram note: x = 75 for all configurations. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register* 0 1 2 . . x . . . selection circuitry selection circuitry tck tms tap controller tdi tdo
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 24 ?2003, micron technology inc. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is seri- ally loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in figure 16. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board- level serial test data path. bypass register to save time when serially shifting data through reg- isters, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with mini- mal delay. the bypass register is set low (vss) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the sram has a 76-bit-long register. the boundary scan register is loaded with the con- tents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins/balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is con- nected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32- bit code during the capture-dr state when the idcode command is loaded in the instruction regis- ter. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift- dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully imple- mented. the tap controller cannot be used to load address, data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller dur- ing the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction regis- ter through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruc- tion. when an extest instruction is loaded into the instruction register, the sram responds as if a sam- ple/preload instruction has been loaded. there is
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 25 ?2003, micron technology inc. one difference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruc- tion. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1-compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap con- troller?s capture setup plus hold time ( t cs plus t ch). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruc- tion will have the same effect as the pause-dr com- mand. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instruc- tion is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 26 ?2003, micron technology inc. figure 17: tap timing note: 1. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 2. test conditions are specified using the load in figure 18. t tlth test clock (tck) 123456 test mode select (tms) t thtl test data-out (tdo) t thth test data-in (tdi) t thmx t mvth t thdx t dvth t tlox t tlov don?t care undefined table 19: tap ac electrical characteristics notes 1, 2; 0oc t a +70oc; v dd 3.3v 0.165v or 2.5v 0.125v description symbol min max units clock clock cycle time t thth 100 ns clock frequency f tf 10 mhz clock high time t thtl 40 ns clock low time t tlth 40 ns output times tck low to tdo unknown t tlox 0ns tck low to tdo valid t tlov 20 ns tdi valid to tck high t dvth 10 ns tck high to tdi invalid t thdx 10 ns setup times tms setup t mvth 10 ns capture setup t cs 10 ns hold times tms hold t thmx 10 ns capture hold t ch 10 ns
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 27 ?2003, micron technology inc. tap ac test conditions input pulse levels ........................................... v ss to 2.5v input rise and fall times ..............................................1ns input timing reference levels.................................. 1.25v output reference levels ........................................... 1.25v test load termination supply voltage .................... 1.25v figure 18: tap ac output load equivalent note: 1. all voltages referenced to v ss (gnd). 2. overshoot: v ih (ac) v dd + 1.5v for t t khkh/2 undershoot: v il (ac) -0.5v for t t khkh/2 power-up: v ih +2.6v and v dd 2.4v and v dd q 1.4v for t 200ms during normal operation, v dd q must not exceed v dd . control input signals (ld#, r/w#, etc.) may not have pulse widths less than t khkl (min) or operate at frequencies exceeding f kf (max). tdo 1.25v 20pf z = 50 ? o 50 ? table 20: 3.3v v dd , tap dc electrical characteristics and operating conditions 0oc t a +70oc; v dd = 3.3v 0.165v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih 2.0 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.8 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current output(s) disabled, 0v v in v dd q (dqx) il o -5.0 5.0 a output low voltage i olc = 100a v ol1 0.7 v 1 i olt = 2ma v ol2 0.8 v 1 output high voltage i ohc = -100a v oh1 2.9 v 1 i oht = -2ma v oh2 2.0 v 1 table 21: 2.5v v dd , tap dc electrical characteristics and operating conditions 0oc t a +70oc; v dd = 2.5v 0.125v unless otherwise noted description conditions symbol min max units notes input high (logic 1) voltage v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current output(s) disabled, 0v v in v dd q (dqx) il o -5.0 5.0 a output low voltage i olc = 100a v ol1 0.2 v 1 i olt = 2ma v ol2 0.7 v 1 output high voltage i ohc = -100a v oh1 2.1 v 1 i oht = -2ma v oh2 1.7 v 1
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 28 ?2003, micron technology inc. table 22: identification register definitions instruction field bit configuration description revision number (31:28) 0000 reserved for version number. device depth (27:23) 01000 00111 defines depth of 2mb. defines depth of 1mb. device width (22:18) 00011 00100 defines width of x18 bits. defines width of x32 or x36 bits. micron device id (17:12) xxxxxx reserved for future use. micron jedec id code (11:1) 00000101100 allows unique identification of sram vendor. id register presence indicator (0) 1 indicates the presence of an id register. table 23: scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan: x18, x32, x36 76 table 24: instruction codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. this instruction does not implement 1149.1 preload function and is therefor e not 1149.1-compliant. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 29 ?2003, micron technology inc. table 25: 165-ball fbga boundary scan order (x18) bit# signal name ball id bit# signal name ball id 1 sa 11p 39 clk 6b 2 sa 2r 40 ce2# 6a 3 sa 8r 41 bw1# 5b 4 sa 8p 42 nc 5a 5 sa 9r 43 bw2# 4a 6 sa 9p 44 nc 4b 7 sa 10r 45 ce2 3b 8 sa 10p 46 ce# 3a 9 sa 11r 47 sa 2a 10 zz 11h 48 sa 2b 11 nc 11n 49 nc 1b 12 nc 11m 50 nc 1a 13 nc 11l 51 nc 1c 14 nc 11k 52 nc 1d 15 nc 11j 53 nc 1e 16 dqa 10m 54 nc 1f 17 dqa 10l 55 nc 1g 18 dqa 10k 56 dqb 2d 19 dqa 10j 57 dqb 2e 20 dqa 11g 58 dqb 2f 21 dqa 11f 59 dqb 2g 22 dqa 11e 60 dqb 1j 23 dqa 11d 61 dqb 1k 24 dqpa 11c 62 dqb 1l 25 nc 10g 63 dqb 1m 26 nc 10f 64 dqpb 1n 27 nc 10e 65 nc 2j 28 nc 10d 66 nc 2k 29 sa 11a 67 nc 2l 30 nc 11b 68 nc 2m 31 sa 10b 69 sa 6n 32 sa 10a 70 mode (lbo#) 1r 33 adv# 9a 71 sa 3p 34 adsp# 9b 72 sa 3r 35 adsc# 8a 73 sa 4p 36 oe# (g#) 8b 74 sa 4r 37 bwe# 7a 75 sa1 6p 38 gw# 7b 76 sa0 6r
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 30 ?2003, micron technology inc. table 26: 165-ball fbga boundary scan order (x32) bit# signal name ball id bit# signal name ball id 1 sa 11p 39 clk 6b 2 sa 2r 40 ce2# 6a 3 sa 8r 41 bw1# 5b 4 sa 8p 42 bw2# 5a 5 sa 9r 43 bw3# 4a 6 sa 9p 44 bw4# 4b 7 sa 10r 45 ce2 3b 8 sa 10p 46 ce# 3a 9 sa 11r 47 sa 2a 10 zz 11h 48 sa 2b 11 nf 11n 49 nc 1b 12 dqa 11m 50 nc 1a 13 dqa 11l 51 nf 1c 14 dqa 11k 52 dqc 1d 15 dqa 11j 53 dqc 1e 16 dqa 10m 54 dqc 1f 17 dqa 10l 55 dqc 1g 18 dqa 10k 56 dqc 2d 19 dqa 10j 57 dqc 2e 20 dqb 11g 58 dqc 2f 21 dqb 11f 59 dqc 2g 22 dqb 11e 60 dqd 1j 23 dqb 11d 61 dqd 1k 24 dqb 10g 62 dqd 1l 25 dqb 10f 63 dqd 1m 26 dqb 10e 64 dqd 2j 27 dqb 10d 65 dqd 2k 28 nf 11c 66 dqd 2l 29 nc 11a 67 dqd 2m 30 nc 11b 68 nf 1n 31 sa 10b 69 sa 6n 32 sa 10a 70 mode (lbo#) 1r 33 adv# 9a 71 sa 3p 34 adsp# 9b 72 sa 3r 35 adsc# 8a 73 sa 4p 36 oe# (g#) 8b 74 sa 4r 37 bwe# 7a 75 sa1 6p 38 gw# 7b 76 sa0 6r
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 31 ?2003, micron technology inc. table 27: 165-ball fbga boundary scan order (x36) bit# signal name ball id bit# signal name ball id 1 sa 11p 39 clk 6b 2 sa 2r 40 ce2# 6a 3 sa 8r 41 bw1# 5b 4 sa 8p 42 bw2# 5a 5 sa 9r 43 bw3# 4a 6 sa 9p 44 bw4# 4b 7 sa 10r 45 ce2 3b 8 sa 10p 46 ce# 3a 9 sa 11r 47 sa 2a 10 zz 11h 48 sa 2b 11 dqpa 11n 49 nc 1b 12 dqa 11m 50 nc 1a 13 dqa 11l 51 dqpc 1c 14 dqa 11k 52 dqc 1d 15 dqa 11j 53 dqc 1e 16 dqa 10m 54 dqc 1f 17 dqa 10l 55 dqc 1g 18 dqa 10k 56 dqc 2d 19 dqa 10j 57 dqc 2e 20 dqb 11g 58 dqc 2f 21 dqb 11f 59 dqc 2g 22 dqb 11e 60 dqd 1j 23 dqb 11d 61 dqd 1k 24 dqb 10g 62 dqd 1l 25 dqb 10f 63 dqd 1m 26 dqb 10e 64 dqd 2j 27 dqb 10d 65 dqd 2k 28 dqpb 11c 66 dqd 2l 29 nc 11a 67 dqd 2m 30 nc 11b 68 dqpd 1n 31 sa 10b 69 sa 6n 32 sa 10a 70 mode (lbo#) 1r 33 adv# 9a 71 sa 3p 34 adsp# 9b 72 sa 3r 35 adsc# 8a 73 sa 4p 36 oe# (g#) 8b 74 sa 4r 37 bwe# 7a 75 sa1 6p 38 gw# 7b 76 sa0 6r
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 32 ?2003, micron technology inc. figure 19: 100-pin plastic tqfp (jedec lqfp) note: 1. all dimensions in millimeters or typical where noted. 2. package width and length do not include mold protrusi on; allowable mold protrusion is 0.25mm per side. 14.00 0.10 1.40 0.05 16.00 0.20 0.10 +0.10 -0.05 0.15 +0.03 -0.02 22.10 +0.10 -0.20 0.32 +0.06 -0.10 20.10 0.10 0.65 typ 0.625 1.60 max detail a see detail a 0.60 0.15 1.00 typ gage plane 0.25 0.10 pin #1 id max min ------------- -
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron, the m logo, the micron logo, and syncburst are trademarks and/or service marks of micron technology, inc. pentium is a registered trademark of intel corporation. 36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram ?2003, micron technology inc. mt58l2my18d_16_b.fm - rev. b; pub 1/03 33 figure 20: 165-ball fbga note: 1. all dimensions in millimeters or typical where noted. data sheet designation advance: this data sheet contains initial descriptions of products still under development. 10.00 14.00 15.00 0.10 1.00 typ 1.00 typ 5.00 0.05 13.00 0.10 pin a1 id pin a1 id ball a1 mold compound: epoxy novolac substrate: plastic laminate 6.50 0.05 7.00 0.05 7.50 0.05 1.20 max solder ball material: eutectic 62% sn, 36% pb, 2% ag solder ball pad: ? .33mm solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.40 seating plane 0.85 0.075 0.12 c c 165x ? 0.45 ball a11 max min ------------- -
36mb: 2 meg x 18, 1 meg x 32/36 pipelined, dcd syncburst sram 0.13m process advance 36mb: 2 meg x 18, 1 meg x 32/36, pipelined, dcd syncburst sram micron technology, inc., reserves the right to change products or specifications without notice. mt58l2my18d_16_b.fm - rev. b, pub 1/03 34 ?2003, micron technology inc. revision history revised fbga dimensions for 165-ball fbga ..................................................................................... .....................1/03 new advance data sheet for 0.13m process; rev. a, pub. 11 /02 ................................................................. ....11/02

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