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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. _______________________________________________________________ maxim integrated products 1 ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b general description the max5969a/max5969b provide a complete interface for a powered device (pd) to comply with the ieee ? 802.3af/at standard in a power-over-ethernet (poe) sys - tem. the max5969a/max5969b provide the pd with a detection signature, classification signature, and an inte - grated isolation power switch with inrush current control. during the inrush period, the max5969a/max5969b limit the current to less than 180ma before switching to the higher current limit (720ma to 880ma) when the isolation power mosfet is fully enhanced. the devices feature an input uvlo with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition during power-on/-off conditions. the max5969a/max5969b can withstand up to 100v at the input. the max5969a/max5969b support a 2-event classifica - tion method as specified in the ieee 802.3at standard and provide a signal to indicate when probed by type 2 power-sourcing equipment (pse). the devices detect the presence of a wall adapter power-source connec - tion and allow a smooth switchover from the poe power source to the wall power adapter. the max5969a/max5969b also provide a power-good (pg) signal, two-step current limit and foldback, over - temperature protection, and di/dt limit. the max5969a/max5969b are available in a space-sav - ing, 10-pin, 3mm x 3mm, tdfn power package. these devices are rated over the -40 n c to +85n c extended temperature range. applications ieee 802.3af/at powered devices ip phones, wireless access nodes, ip security cameras wimaxk base station features s ieee 802.3af/at compliant s 2-event classification s simplified wall adapter interface s poe classification 0 to 5 s 100v input absolute maximum rating s inrush current limit of 180ma maximum s current limit during normal operation between 720ma and 880ma s current limit and foldback s legacy uvlo at 36v (max5969a) s ieee 802.3af/at-compliant, 40v uvlo (max5969b) s overtemperature protection s thermally enhanced, 3mm x 3mm, 10-pin tdfn 19-5008; rev 0; 12/09 + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. ordering information pin configuration ieee is a registered service mark of the institute of electrical and electronics engineers, inc. wimax is a trademark of wimax forum. evaluation kit available part temp range pin- package uvlo threshold (v) max5969aetb+ -40nc to +85nc 10 tdfn-ep* 35.4 MAX5969BETB+ -40nc to +85nc 10 tdfn-ep* 38.6 1 3 4 10 8 7 cls pg wad v dd n.c. i.c. ep* *ep = exposed pad. connect to v ss . max5969a max5969b 2 9 2ec det 5 6 rtn v ss tdfn (3mm 3mm) top view +
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b 2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to v ss .......................................................... -0.3v to +100v det, rtn, wad, pg, 2ec to v ss ....................... -0.3v to +100v cls to v ss .............................................................. -0.3v to +6v maximum current on cls (100ms maximum) ................. 100ma continuous power dissipation (t a = +70 n c) (note 1) 10-pin tdfn (derate 24.4mw/ n c above +70nc) multilayer board ........................................................ 1951mw package thermal resistance (note 2) b ja ................................................................................. 4nc/w b jc ................................................................................ 9nc/w operating temperature range .......................... -40n c to +85nc maximum junction temperature ..................................... +150nc storage temperature range ............................ -65n c to +150nc soldering temperature (reflow) .................................... +260 nc electrical characteristics (v in = (v dd - v ss ) = 48v, r det = 24.9k, r cls = 619. rtn, wad, pg, and 2ec unconnected, all voltages are referenced to v ss, unless otherwise noted. t a = t j = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) absolute maximum ratings note 1: maximum power dissipation is obtained using jedec jesd51-5 and jesd51-7 specifications. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . parameter symbol conditions min typ max units detection mode input offset current i offset v in = 1.4v to 10.1v (note 4) 10 fa effective differential input resistance dr v in = 1.4v up to 10.1v with 1v step, v dd = rtn = wad = pg = 2ec (note 5) 23.95 25.00 25.5 ki classification mode classification disable threshold v th,cls v in rising (note 6) 22.0 22.8 23.6 v classification stability time 0.2 ms classification current i class v in = 12.5v to 20.5v, v dd = rtn = wad = pg = 2ec class 0, r cls = 619i 0 3.96 ma class 1, r cls = 117i 9.12 11.88 class 2, r cls = 66.5i 17.2 19.8 class 3, r cls = 43.7i 26.3 29.7 class 4, r cls = 30.9i 36.4 43.6 class 5, r cls = 21.3i 52.7 63.3 type 2 (802.3at) classification mode mark event threshold v thm v in falling 10.1 10.7 11.6 v hysteresis on mark event threshold 0.84 v mark event current i mark v in falling to enter mark event, 5.2v p v in p 10.1v 0.25 0.85 ma reset event threshold v thr v in falling 2.8 4 5.2 v power mode v in supply voltage range 60 v v in supply current i q measured at v dd 0.27 0.55 ma
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = (v dd - v ss ) = 48v, r det = 24.9k, r cls = 619. rtn, wad, pg, and 2ec unconnected, all voltages are referenced to v ss, unless otherwise noted. t a = t j = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) parameter symbol conditions min typ max units v in turn-on voltage v on v in rising max5969a 34.3 35.4 36.6 v max5969b 37.2 38.6 40 v in turn-off voltage v off v in falling 30 v v in turn-on/-off hysteresis (note 7) v hyst_uvlo max5969a 4.2 v max5969b 7.3 v in deglitch time t off_dly v in falling from 40v to 20v (note 8) 30 120 fs inrush to operating mode delay t delay t delay = minimum pg current pulse width after entering into power mode 80 96 112 ms isolation power mosfet on-resistance r on_iso i rtn = 600ma t j = +25nc 0.5 0.7 i t j = +85nc 0.65 1 t j = +125nc 0.8 rtn leakage current i rtn_lkg v rtn = 12.5v to 30v 10 fa current limit inrush current limit i inrush during initial turn-on period, v rtn = 1.5v 90 135 180 ma current limit during normal operation i lim after inrush completed, v rtn = 1v 720 800 880 ma foldback threshold v rtn (note 9) 13 16.5 v logic wad detection threshold v wad-ref v wad rising, v in = 14v to 48v (referenced to rtn) 8 9 10 v wad detection threshold hysteresis v wad falling, v rtn = 0v, v ss unconnected 0.725 wad input current i wad-lkg v wad = 10v (referenced to rtn) 3.5 fa 2ec sink current v 2ec = 3.5v (referenced to rtn), v ss unconnected 1 1.5 2.25 ma 2ec off-leakage current v 2ec = 48v 1 fa pg sink current v rtn = 1.5v, v pg = 0.8v, during inrush period 125 230 375 fa pg off-leakage current v pg = 48v 1 fa thermal shutdown thermal-shutdown threshold t sd t j rising +140 nc thermal-shutdown hysteresis t j falling 28 nc
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b 4 ______________________________________________________________________________________ electrical characteristics (continued) (v in = (v dd - v ss ) = 48v, r det = 24.9k, r cls = 619. rtn, wad, pg, and 2ec unconnected, all voltages are referenced to v ss, unless otherwise noted. t a = t j = -40 n c to +85 n c, unless otherwise noted. typical values are at t a = +25 n c.) (note 3) note 3: all devices are 100% production tested at t a = +25 n c. limits over temperature are guaranteed by design. note 4: the input offset current is illustrated in figure 1. note 5: effective differential input resistance is defined as the differential resistance between v dd and v ss . see figure 1. note 6: classification current is turned off whenever the device is in power mode. note 7: uvlo hysteresis is guaranteed by design, not production tested. note 8: a 20v glitch on input voltage that takes v dd below v on shorter than or equal to t off_dly does not cause the max5969a/ max5969b to exit power-on mode. note 9: in power mode, current-limit foldback is used to reduce the power dissipation in the isolation mosfet during an overload condition across v dd and rtn. figure 1. effective differential input resistance/offset current i in i ini + 1 i ini i offset dr i 1v v ini v ini + 1 i offset = i ini - v ini dr i dr i = (v ini + 1 - v ini ) = 1v (i ini + 1 - i ini ) (i ini + 1 - i ini ) v in
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b _______________________________________________________________________________________ 5 typical operating characteristics (v in = (v dd - v ss ) = 54v, r det = 24.9k, r cls = 615. rtn, wad, pg, and 2ec unconnected; all voltages are referenced to v ss. ) input current (detection) vs. input voltage max5969a toc01 v in (v) i in (ma) 8 6 4 2 0.1 0.2 0.3 0.4 0.5 0 0 10 i in = i vdd + i det r det = 24.9k i rtn = 2ec = pg = wad = v dd -40c p t a p +85 n c signature resistance vs. input voltage r signature (ki) 8 6 4 2 24.5 25.0 25.5 26.0 24.0 0 10 max5969a toc02 v in (v) i in = i vdd + i det r det = 24.9ki rtn = 2ec = pg = wad = v dd t a = -40nc t a = +85nc t a = +25nc input offset current vs. input voltage input offset current (a) 8 6 4 2 -2 0 2 4 -4 0 10 max5969a toc03 v in (v) t a = +85nc t a = -40nc t a = +25nc input current (classification) vs. input voltage max5969a toc04 v in (v) i in (ma) 25 20 15 10 5 10 20 30 40 50 60 70 0 0 30 class 5 class 4 class 3 class 2 class 1 class 0 classification settling time max5969a toc05 v in 10v/div i in 200ma/div 0v 0a v cls 1v/div 100s/div r cls = 30.9 i 2ec sink current vs. 2ec voltage v 2ec (v) i 2ec (ma) 50 40 30 20 10 0.4 0.8 1.2 1.6 2.0 0 0 60 max5969a toc06 v ss unconnected v 2ec referenced to rtn v wad = 14v t a = -40 n c t a = +85 n c t a = +25 n c pg sink current vs. pg voltage v pg (v) i pg (a) 50 40 30 20 10 100 150 200 250 300 50 0 60 max5969a toc07 t a = -40 n c t a = +85 n c t a = +25 n c inrush current limit vs. rtn voltage max5969a toc08 v rtn (v) inrush current limit (ma) 50 40 30 20 10 70 90 110 130 150 50 0 60 normal operation current limit vs. rtn voltage max5969a toc09 v rtn (v) current limit (ma) 50 40 10 20 30 200 300 400 500 600 700 800 900 100 0 60
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b 6 ______________________________________________________________________________________ typical operating characteristics (continued) (v in = (v dd - v ss ) = 54v, r det = 24.9k, r cls = 615. rtn, wad, pg, and 2ec unconnected; all voltages are referenced to v ss. ) inrush control waveform with type 2 classification max5969a toc10 0v 0v 0a 0v v rtn 50v/div i rtn 100ma/div v dd 50v/div v 2ec 50v/div 200 s/div using typical application circuit 2ec pulled up to v dd with 10ki entering power mode with type 2 classification max5969a toc11 v pg 10v/div 0v 0v 0v 0a 0v v rtn 50v/div i rtn 200ma/div v dd 50v/div 20ms/div v 2ec 40v/div using typical application circuit 2ec pulled up to v dd with 10ki
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b _______________________________________________________________________________________ 7 pin description pin name function 1 v dd positive supply input. connect a 68nf (min) bypass capacitor between v dd and v ss . 2 det detection resistor input. connect a signature resistor (r det = 24.9k i ) from det to v dd . 3 n.c. no connection. not internally connected. 4 i.c. internally connected. leave unconnected. 5 v ss negative supply input. v ss connects to the source of the integrated isolation n-channel power mosfet. 6 rtn drain of isolation mosfet. rtn connects to the drain of the integrated isolation n-channel power mosfet. connect rtn to the downstream dc-dc converter ground as shown in the typical application circuit . 7 wad wall power adapter detector input. wall adapter detection is enabled the moment v dd - v ss crosses the mark event threshold. detection occurs when the voltage from wad to rtn is greater than 9v. when a wall power adapter is present, the isolation n-channel power mosfet turns off, 2ec current sink turns on. connect wad directly to rtn when the wall power adapter or other auxiliary power source is not used. 8 pg open-drain power-good indicator output. pg sinks 230 f a to disable the downstream dc-dc converter while turning on the hot-swap mosfet switch until the hot-swap switch is fully on. pg current sink is disabled during detection, classification, and in the steady-state power mode. 9 2ec active-low 2-event classification detect or wall adapter detect output. a 1.5ma current sink is enabled at 2ec when a type 2 pse or a wall adapter is detected. when powered by a type 2 pse, the 2ec current sink is enabled and latched low after the isolation mosfet is fully on until v in drops below the uvlo threshold. 2ec also asserts when a wall adapter supply, typically greater than 9v, is applied between wad and rtn. 2ec is not latched if asserted by wad. 10 cls classification resistor input. connect a resistor (r cls ) from cls to v ss to set the desired classification current. see the classification current specifications in the electrical characteristics table to find the resis - tor value for a particular pd classification. CC ep exposed pad. do not use ep as an electrical connection to v ss . ep is internally connected to v ss through a resistive path and must be connected to v ss externally. to optimize power dissipation, solder the exposed pad to a large copper power plane.
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b 8 ______________________________________________________________________________________ simplified block diagram 1.5ma 46a v dd en cls 1.23v pse 2 2ec v dd 5v 11.6v/10.8v 11.6v/4v d q q set clr det v ss 5v regulator 5v 1.23v 22.8v/22v thermal shutdown q r s v dd v dd v dd wad wapd rtn v on /v off v dd d q q set clr 9v 230a pg classification i switch k x i switch isolation switch s mux i0 135ma v on /v off = 38.6v/31v for max5969b v on /v off = 35.4v/31v for max5969a 760ma i1 1/k max5969a max5969b 95ms hson 4v 15v i ref
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b _______________________________________________________________________________________ 9 typical operating circuit 2-event classification detection -54v max5969a max5969b v dd rtn wad pg 2ec 24v/48v battery 68nf rj-4 5 and bridge rectifier gnd smaj58a r det 24.9ki r cls v ss det cls enable dc-dc converter in+ in- gnd
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b 10 _____________________________________________________________________________________ detailed description operating modes depending on the input voltage (v in = v dd - v ss ), the max5969a/max5969b operate in four different modes: pd detection, pd classification, mark event, and pd power. the devices enter pd detection mode when the input voltage is between 1.4v and 10.1v. the device enters pd classification mode when the input voltage is between 12.6v and 20v. the device enters pd power mode once the input voltage exceeds v on . detection mode (1.4v v in 10.1v) in detection mode, the pse applies two voltages on v in in the range of 1.4v to 10.1v (1v step minimum) and then records the current measurements at the two points. the pse then computes d v/ d i to ensure the presence of the 24.9k signature resistor. connect the signature resistor (r det ) from v dd to det for proper signature detection. the max5969a/max5969b pull det low in detection mode. det goes high impedance when the input voltage exceeds 12.5v. in detection mode, most of the max5969a/max5969b internal circuitry is off and the offset current is less than 10a. if the voltage applied to the pd is reversed, install pro - tection diodes at the input terminal to prevent internal damage to the max5969a/max5969b (see the typical application circuit ). since the pse uses a slope tech - nique ( dv/d i) to calculate the signature resistance, the dc offset due to the protection diodes is subtracted and does not affect the detection process. classification mode (12.6v v in 20v) in the classification mode, the pse classifies the pd based on the power consumption required by the pd. this allows the pse to efficiently manage power distribution. class 0 to 5 is defined as shown in table 1. (the ieee 802.3af/at standard defines only class 0 to 4 and class 5 for any special requirement.) an external resistor (r cls ) connected from cls to v ss sets the classification current. the pse determines the class of a pd by applying a volt - age at the pd input and measuring the current sourced out of the pse. when the pse applies a voltage between 12.6v and 20v, the max5969a/max5969b exhibit a cur - rent characteristic with a value shown in table 1. the pse uses the classification current information to classify the power requirement of the pd. the classification cur - rent includes the current drawn by r cls and the supply current of the max5969a/max5969b so the total current drawn by the pd is within the ieee 802.3af/at standard figures. the classification current is turned off whenever the device is in power mode. 2-event classification and detection during 2-event classification, a type 2 pse probes pd for classification twice. in the first classification event, the pse presents an input voltage between 12.6v and 20v and the max5969a/max5969b present the pro - grammed load i class . the pse then drops the probing voltage below the mark event threshold of 10.1v and the max5969a/max5969b present the mark current (i mark ). this sequence is repeated one more time. table 1. setting classification current *v in is measured across the max5969a/max5969b input v dd to v ss . class maximum power used by pd (w) r cls (i) v in * (v) class current seen at v in (ma) ieee 802.3af/at pse classification current specification (ma) min max min max 0 0.44 to 12.95 619 12.6 to 20 0 4 0 5 1 0.44 to 3.94 117 12.6 to 20 9 12 8 13 2 3.84 to 6.49 66.5 12.6 to 20 17 20 16 21 3 6.49 to 12.95 43.7 12.6 to 20 26 30 25 31 4 12.95 to 25.5 30.9 12.6 to 20 36 44 35 45 5 > 25.5 21.3 12.6 to 20 52 64
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b ______________________________________________________________________________________ 11 when the max5969a/max5969b are powered by a type 2 pse, the 2-event identification output 2ec asserts low after the internal isolation n-channel mosfet is fully turned on. 2ec current sink is turned off when v dd goes below the uvlo threshold (v off ) and turns on when v dd goes above the uvlo threshold (v on ), unless v dd goes below v thr to reset the latched output of the type 2 pse detection flag. alternatively, the 2ec output also serves as a wall adapt- er detection output when the max5969a/max5969b are powered by an external wall power adapter. see the wall power adapter detection and operation section for more information. power mode (wake mode) the max5969a/max5969b enter power mode when v in rises above the undervoltage lockout threshold (v on ). when v in rises above v on , the max5969a/max5969b turn on the internal n-channel isolation mosfet to con - nect v ss to rtn with inrush current limit internally set to 135ma (typ). the isolation mosfet is fully turned on when the voltage at rtn is near v ss and the inrush cur - rent is reduced below the inrush limit. once the isolation mosfet is fully turned on, the max5969a/max5969b change the current limit to 800ma. the open-drain power-good output (pg) remains low for a minimum of t delay until the power mosfet fully turns on to keep the downstream dc-dc converter disabled during inrush. undervoltage lockout the max5969a/max5969b operate up to a 60v sup - ply voltage with a turn-on uvlo threshold (v on ) at 35.4v/38.6v and a turn-off uvlo threshold (v off ) at 31v. when the input voltage is above v on , the max5969a/ max5969b enter power mode and the internal mosfet is turned on. when the input voltage goes below v off for more than t off_dly , the mosfet turns off. power-good output an open-drain output (pg) is used to allow disabling downstream dc-dc converter until the n-channel isola - tion mosfet is fully turned on. pg is pulled low to v ss for a period of t delay and until the internal isolation mosfet is fully turned on. the pg is also pulled low when coming out of thermal shutdown. thermal-shutdown protection the max5969a/max5969b include thermal protection from excessive heating. if the junction temperature exceeds the thermal-shutdown threshold of +140 nc, the max5969a/max5969b turn off the internal power mosfet and 2ec current sink. when the junction tem- perature falls below +112 n c, the devices enter inrush mode and then return to power mode. inrush mode ensures the downstream dc-dc converter is turned off as the internal power mosfet is turned on. wall power adapter detection and operation for applications where an auxiliary power source such as a wall power adapter is used to power the pd, the max5969a/max5969b feature wall power adapter detection. once the input voltage (v dd - v ss ) exceeds the mark event threshold, the max5969a/max5969b enable wall adapter detection. the wall power adapt - er is connected from wad to rtn. the max5969a/ max5969b detect the wall power adapter when the voltage from wad to rtn is greater than 9v. when a wall power adapter is detected, the internal n-channel isolation mosfet turns off, 2ec current sink turns on, and classification current is disabled if v in is in the clas - sification range.
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b 12 _____________________________________________________________________________________ applications information operation with 12v adapter layout procedure careful pcb layout is critical to achieve high efficiency and low emi. follow these layout guidelines for optimum performance: 1) place the input capacitor, classification resistor, and transient voltage suppressor as close as possible to the max5969a/max5969b. 2) use large smt component pads for power dissipat - ing devices such as the max5969a/max5969b and the external diodes. 3) use short and wide traces for high-power paths. 4) use the max5969 evaluation kit layout as a refer - ence. figure 2. typical configuration when using a 12v wall power adapter 68nf 2-event classi fication (asserted on ) enable dc-dc converter in+ in- rj-4 5 and bridge rectifier gnd gnd -54v smaj58a max5969a max5969b r det 24.9ki r cls v dd v ss rtn wad pg det cls 2ec 12v battery this circuit achieves pr op er 2e c logi c wh en battery is < 12.5v
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b ______________________________________________________________________________________ 13 typical application circuit 68nf isolated 2-event classification output gnd v ac v ac gnd -54v smaj58a max5969a max5969b 24.9ki 43.7i v dd v ss rtn wad pg pg det cls 2ec 24/48v battery rtn max15000 uvlo/en in v cc uflg fb comp cs pg cs v cc v cc cs rtn isolated +5.3v/2a isolated rtn isolated rtn gnd rtn gnd 33ki 10ki 249i 22.1i 0.75i 1ki 619i 8.2nf 330pf 649i 4.99ki 1ki 100pf 33nf 8.06ki 2.49ki 1ki 18.1ki rtn 4.99ki ndrv gnd rt 51.5ki 1.37mi 0.1f 0.1f 0.1f 0.1f 22f 4.7f 2.2nf 8.06ki
ieee 802.3af/at-compliant, powered device interface controllers with integrated power mosfet max5969a/max5969b maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. package information for the latest package outline information and land pat - terns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suf - fix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos package type package code document no. 10 tdfn-ep t1033+1 21-0137

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