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| rev.4.00 jun 15, 2005 page 1 of 39 ha16107p/fp, ha16108p/fp pwm switching regulator for high-performance voltage mode control rej03f0141-0400 (previous: ade-204-012c) rev.4.00 jun 15, 2005 description the ic products in this series are primary control switching regulator control ic?s approp riate for obtaining stabilized dc voltages from commercial ac power. these ic?s can directly drive power mos fet?s, they ha ve a timer function built in to the secondary overcurrent protection, and they can perform intermittent operation or delayed latched shutdown as protection operations in unusual conditions. they can be used to implement switching power supplies with a high level of safety due to the wide range of built-in functionality. functions ? 6.45 v reference voltage ? triangle wave generator ? error amplifier ? under voltage lockout protector ? pwm comparator ? pulse-by-pulse current limitting ? timer-latch current limitting (ha16107) ? on/off timer function (ha16108) ? soft start and quick shutdown ? output circuit for power mos fet driving features ? operating frequencies up to a high 600 khz ? built-in pre-driver circuit for driving power mos fet ? built-in timer latch over-current protection function (ha16107) ? the ocl enables intermittent operation by an on/off timer for prevention of secondary overcurrent. (ha16108) ? the uvl function (under voltage lockout) is applied to both vin and vref. ? on/off reset: an auto-reset function which is based on the time constant of an external capacitor and observation of drops in vin. ? since the over-voltage protection function ovp (the tl pin) only observes voltage drops in vin, it is possible to use the ovp and on/off pin for independent purposes. ? built-in 34 v zener diode between vin and ground.
ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 2 of 39 ordering information typical threshold voltage product uvl1 ovp notes package code (previous code) ha16107p dp-16 ha16107fp hi: 16.2 v lo: 9.5 v 7.0 v timer latch protection prsp0016dh-a (fp-16da) ha16108p dp-16 ha16108fp hi: 16.2 v lo: 9.5 v hi: 7.0 v lo: 1.3 v on-off timer protection prsp0016dh-a (fp-16da) pin arrangement v in out cl(+) v e cl( ? ) r t1 c t r t2 tl, on/off e/o in( ? ) nc gnd in(+) st vref (top view) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 note 1 note 2 notes: 1. 2. in the sop package models (ha16107fp and ha16108fp) pins 4, 5, and 13 are connected inside the ic. however, all must be connected to the system ground. pin 16 is tl (ha16107), on/off (ha16108). ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 3 of 39 pin functions ? ha16107p, ha16108p pin no. symbol pin functions 1 v in input voltage 2 out pulse output 3 cl (+) current limiter 4 v e output ground 5 cl (?) current limiter 6 r t1 timing resistor (rising time) 7 c t timing capacitor 8 r t2 timing resistor (falling time) 9 vref reference voltage output 10 st soft start 11 in (+) error amp (+) input 12 gnd ground 13 nc nc 14 in (?) error amp (?) input 15 e/o error output 16 tl, on/off timer latch (ha16107), on/off (ha16108) ? ha16107fp, ha16108fp pin no. symbol pin functions 1 v in input voltage 2 out pulse output 3 cl (+) current limiter 4 gnd ground 5 gnd ground 6 r t1 timing resistor (rising time) 7 c t timing capacitor 8 r t2 timing resistor (falling time) 9 vref reference voltage output 10 st soft start 11 in (+) error amp (+) input 12 gnd ground 13 gnd ground 14 in (?) error amp (?) input 15 e/o error output 16 tl, on/off timer latch (ha16107), on/off (ha16108) ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 4 of 39 block diagram 6.45 v zener type ref. voltage gen. uvl1 h l v l v h r s q tl 16 e/o 15 in ( ? ) 14 nc 13 gnd 12 in (+) 11 st 10 vref 9 1 v in 2 out 3 cl (+) 4 v e 5 cl ( ? ) 6 r t1 7 c t 8 r t2 16 a 4 a on/off latch (v th = 7 v) o v p uvl2 h l 4 v 5 v uvl1 st triangle waveform uvl1 and uvl2 pulse-by-pulse latch q q r s out v e v c qclm ++ ? pwm comparator current limiter triangle waveform osc triangle waveform latch reset pulse on duty pulse 3.4 v 10 a 34 v v in uvl2 vref vref error amp. ea + ? 140 a 6.45 v zener type ref. voltage gen. uvl1 h l v l v h r s q on/off 16 e/o 15 in ( ? ) 14 nc 13 gnd 12 in (+) 11 st 10 vref 9 1 v in 2 out 3 cl (+) 4 v e 5 cl ( ? ) 6 r t1 7 c t 8 r t2 16 a 4 a on/off latch (v th = 7 v) o v p uvl2 h l 4 v 5 v uvl1 st triangle waveform uvl1 and uvl2 pulse-by-pulse latch q q r s out v e v c qclm ++ ? pwm comparator current limiter triangle waveform osc triangle waveform latch reset pulse on duty pulse 3.4 v 10 a 34 v v in uvl2 note: dotted lines apply to the sop package model (pins 4, 5, and 13: ground) vref vref error amp. ea + ? 140 a ? ha16107p/fp ? ha16108p/fp ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 5 of 39 function and timing chart triangle waveform and pwm output v th 4.2 v typ triangle waveform is output to c t pin e/o c t v rt2 out 0 v 0 v v tl 2.2 v typ dead band t db t on i 1 = vref ? 2v be r t1 c t r t1 2v vref ? 2v be 0.4 c t r t1 (s) i 2 = 9 8 7 6 2 2 2 i 1 i 1 2i 2 i 2 r t1 c t vref (connected internally) ? + ? + comparator for triangle waveform oscillation 0.6 v the 2s are transistors whose emitter area is doubled. t db = r t2 2r t1 du max = r t2 2r t1 ? r t2 t on t db 1 ? du max t db f osc (s) (hz) note: when f osc is high, the actual value will differ from that given by the formula due to the delay time. determine the correct constants after constructing a test circuit. r t2 v rt2 2 ? timing chart (during normal operation) ? oscillator equivalent circuit v in 2v be vref ? 2v be r t2 ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 6 of 39 1. timing in normal operation timing in these ics is based on a triangular voltage waveform. the rising edge (leading edge) defines the deadband time t db . the falling edge (trailing edge) defines the on-duty control band t on . pwm output is on in the area within t on that is bounded above by the triangle wave v ct and error output v e/o . the following pin outputs are related to pwm control: ? c t (pin 7): triangle-wave voltage output ? e/o (pin 15): error output voltage ? r t2 (pin 8): on-duty pulse output voltage ? out (pin 2): pwm pulse output (for driving the gate of a power mos fet) 2. triangle oscillator, waveform and frequency the triangle oscillator in these ics generates a triangular waveform by charging and discharging timing capacitor c t with a constant current, as shown in the equivalent circuit. the c t charge current is: i(c tchg ) = i 1 = v ref ? 2v be r t1 the discharge current is: i(c tdischg ) = 2i 2 ? i 1 , where i 2 = v ref ? 2v be r t2 in these equations vref (reference voltage) is typically 6.45 v, and v be (base-emitter voltage of internal transistors) is about 0.7 v. the deadband time is: + 0.25 s c t r t1 2v v ref ? 2v be t db = 0.4 c t r t1 + 0.25 s the on-duty time is: r t2 2r t1 ? r t2 t on = t db the 0.25 s in these equations is a correction term for internal circuit delays. the maximum on-duty is r t2 2r t1 du max = the oscillating frequency is: f osc = 1 0.4 c t r t1 + 0.25 1 ? r t2 2r t1 + 0.25 = 1 0.8 c t r t1 2 + 0.25 2r t1 2r t1 ? r t2 + 0.25 (hz) when r t1 = r t2 , the maximum on-duty is 50%, and: 1 0.8 c t r t1 + 0.25 2 + 0.25 f osc 1 0.8 c t r t1 + 0.75 (hz) = this approximation is fairly close, but it should be checked in-circuit. ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 7 of 39 3. programming of maximum on-duty (du max) the preceding equations should be used to program the d eadband or maximum on-duty. the following table gives a summary. condition r t1 > r t2 r t1 = r t2 r t1 < r t2 triangle waveform du max less than 50% 50% greater than 50%* note: in a primary-control switching regulator, du max > 50% is dangerous because the transformer will saturate. soft start and quick shutdown one purpose of the soft-start function is to protect the switching controller and power mos fet from surges at power- up. another purpose is to let the secondary-side dc voltage rise smoothly. when power goes off, the quick-shutdown function rapidly discharges the capacitor in the soft-start circuit (and at the same time switches the pwm output off) to prepare for the next power-on. the soft-start function in these ics lets the pwm output develop smoothly from zero to the designated pulse width at power-up. the soft-start voltage is the 3.8 v voltage value of an internal zener diode, so the pwm output is able to start widening gradually as soon as the soft-start function starts operating. the soft-start function will start promptly even if c st is large. the soft-start and quick-shutdown modes are selected au tomatically in the ic, under control of the uvl signal. ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 8 of 39 level determined by transformer ? timing waveforms 16.2 v 9.5 v 6.45 v 5 v 4 v 0 v v in (time t) normal operation soft start v in v st v ct c st discharge st quick shutdown v e/o 4.2 v 3.8 v 2.2 v 0 v 0 v v ct , v st , v e/o v out (pwm pulse) + + ? vref from vref from uvl2 (effective for quick shutdown) pwm comparator v ct e/o 15 7 10 9 10 a zener diode 3.8 v vref c st st note: the soft-start time constant is determined by c st and the constant-current value (typically 10 a). vref vref v in ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 9 of 39 vref protection functions: overvoltage and undervoltage vref overvoltage and undervoltage conditions are detected by the overvoltage detection circuit and uvl2 circuit. pwm output shuts down when vref 8 v. uvl2 detects undervoltage with hysteresis between approximately 4 v and 5 v. pwm output also shuts down below these voltages. it follows that pwm output will shut off whenever the vref pin is shorted to the power supply (v in ) or ground (gnd). pwm output also shuts off when v in is turned on or off. the following diagram shows how these protection functions operate when power comes on and goes off (vref < 6.45 v), and when a high external voltage is applied to the vref pin (vref > 6.45 v). pwm output shut- down region pwm output operating region power-off, or shorted to ground pwm out pwm output shut-down region power-up shorted to power supply 0 4 v 5 v 6.45 v 8 v 10 v uvl2 vref ovp vref 1. current-limiter circuit the current limiter pin (cl) is connected to the emitter of an npn transistor, as shown in the block diagram. the threshold voltage is 240 mv typ. the switching speed of this circuit is approximately 100 ns from detection of overcurrent to shut-down of pwm output. switching speed increases with the strength of the signal input to the cl pin. instead of simple pulse-by-pulse current limiting, in these ics the current limiting circuit is linked to the timer-and- latch or on/off timer circuit, and also detects the degree of overcurrent. the overcurrent value is determined from the point at which current limiting is triggered in the on-duty cycle. with a large overcurrent (causing current limiting to operate even at a small on-duty), the ic automatically shortens the timer time. ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 10 of 39 undervoltage lockout and pwm output the undervoltage lockout function turns off the pwm pulse output when the controller?s supply voltage goes below a designated value. these ics have two undervoltage lockout circuits. the uvl1 circuit senses the supply voltage v in . the uvl2 circuit senses the vref voltage. a feature of these ics is that pwm output is turned on only when both voltages are above designated values. otherwise, the ic operates in standby mode. the two built-in undervoltage lockout circuits make it possible to configure an extremely safe power supply system. pwm output will shut down under a variety of abnormal conditions, such as if vref is shorted to ground while v in is applied. 0 10 v 20 v 30 v 34 v i in 9.5 v 16.2 v * 1 0 10 v 20 v 30 v * 2 6.45 v notes: 1. 2. breakdown voltage of the internal zener diode (v z = 34 v typ). hysteresis characteristic. 0 10 v 20 v 30 v vref 6.45 v 0 10 v 20 v 30 v out 5 v 4 v pwm output shut-down region operating region v in v in v in v in v in (uvl1) vref (uvl2) pwm out standby mode note: double circles indicate standby mode. l l l h l l h h out ? l h l ? uvl1 (v in and vref) ? uvl2 (vref and pwm output) ? uvl1 and uvl2 vref ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 11 of 39 timer latch and on/off timer the ha16107 has a built-in timer-latch function. the ha16108 has a built-in on/off timer function. the timer-latch function is an overvoltage protection function that combines latched shutdown of pwm output with a timer function to vary the time until latched shutdown occurs according to the overcurrent value. a dedicated voltage detection pin is provided in addition to vref overvoltage protection. the on/off timer function is equivalent to the above timer-latch function without the latch. if overcurrent is detected continuously, pwm output shuts down temporarily, then normal operation resumes. this process repeats, temporary shutdown alternating with normal operation. both the timer-latch function in the ha16107 and the on/off function in the ha16108 wait for an interval after overcurrent detection before shutting down pwm output. the interval is determined by capacitor c tm and the value of the charge/discharge current supplied internally from th e ic. normal operation therefore continues if a single overcurrent spike is detected, while if continuous overcurrent is detected, the current and voltage droop curves for the secondary-side output have sharp characteristics. 1. use of timer-latch pin (ha16107) ? timer-latch usage see external circuit 1 in the following diagram. under continuous overcurrent, the cml switch turns on, charging c tm with 12 a. pwm output shuts down when the voltage at pin 15 exceeds 7 v. ? overvoltage protection usage see external circuit 2 in the diagram. this configuration is suitable when overvoltage is detected by an ovp signal received through an optocoupler from the dc ou tput on the secondary side of an ac/dc converter. pwm output shuts down when the ovp signal allows the voltage at the tl pin to exceed 7 v. the shutdown is latched. v in must go below approximately 6.5 v (v inr2 ) to release the latched state. c tm 15 16 a 4 a from cml ovp with latch timer ha16107 v in ovp signal (from secondary) ? external circuit 1 t l v th latch (pwm output shuts down) 7.0 v 0 v v tl a b t ocl detected continuously (activating pulse-by-pulse current limiter) notes: 1. 2. 3. the latch function is cleared when v in goes below approximately 7.0 v. path a is followed if the ocl input stops before v th is reached. path b is followed if ocl is detected continuously until the latch point is reached. ? external circuit 2 ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 12 of 39 2. use of on/off timer pin (ha16108) ? external circuit 16 16 a 4 a from cml ovp with latch timer ha16108 ion ioff + ? on/off timer operation v thh 7.0 v 0 v t 1.2 v v thl t off t on ocl detected (pwm output on) pwm output shut down ocl detected (pwm output on) pulse-by-pulse current limiting notes: 1. 2. 3. 4. t on c 5.8 v (0.9 ? du) 16 a ? 4 a t off c 5.8 v 4 a c is the capacitance of an external timing capacitor connected between this pin and ground. du is the on-duty of the pwm output when overcurrent limiting is triggered. the values of t on and t off for tl can be determined by the same equations as given for the on/off timer, except that 5.8 v (v thh ? v thl ) becomes v thh = 7 v. if the timer goes off during soft start or in the undervoltage lockout region, after recovery, output will come on after the soft-start time or after the rise time to the undervoltage lockout release point, which is determined by the time constant. ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 13 of 39 absolute maximum ratings (ta = 25 c) item symbol rating value units notes supply voltage v in 30 v output current (dc) i o 0.2 a output current (peak) iopeak 2 a current limiter voltage v cl +4, ?1 v error amp input voltage v iea vref v e/o output voltage v ie/o vref v r t1 pin current i rt1 500 a r t2 pin current i rt2 5 ma power dissipation p t 680 mw 1, 2 operating temperature range topr ?20 to +85 c storage temperature range tstg ?55 to +125 c notes: 1. for the ?fp? products (sop package), this value is when mounted on a 40 by 40 by 1.6 mm glass epoxy substrate. however, this value must be derated by 8.3 mw/ c from ta = 45 c. when the wiring density is 10%, and 11.1 mw/c from ta = 64 c when the wiring density is 30%. 2. for the ?p? products (dip package), this value is valid up to 45 c, and must be derated by 8.3 mw/c above 45 c. 3. in the case of sop, use center 4 pins, (4), (5), (12), (13) for solder-mounting and connect the wide ground pattern, because these pins are available for heat sink of this ic. 700 600 500 400 300 200 100 ? 20 0 20 40 60 80 100 120 140 45 c64 c 30% wiring density 10% wiring density ambient temperature ta ( c) power dissipation p t (mw) ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 14 of 39 electrical characteristics (ta = 25 c, v in = 18 v, f osc = 100 khz) section item symbol min typ max unit test conditions note output voltage vref 6.10 6.45 6.80 v line regulation line ? 30 60 mv 12 v v in 30 v load regulation load ? 30 60 mv 0 ma i o 10 ma temperature stability ? vref/ ? ta ? 40 ? ppm/ c short circuit current i os 30 50 ? ma vref = 0 v reference voltage over voltage protec- tion (vref ovp voltage) vrovp 7.4 8.0 9.0 v maximum frequency fmax 600 ? ? khz minimum frequency fmin ? ? 1 khz voltage stability ? f/fo 1 ? 1 3 % 12 v v in 30 v fo 1 = (fmax + fmin)/2 temperature stability ? f/fo 2 ? 1 ? % ?20 c ta +85 c fo 2 = (fmax + fmin)/2 triangle wave generator frequency accuracy f osc 270 300 330 khz r t1 = r t2 = 27 k ? c t = 120 pf minimum deadband pulse width t db ? ? 1.0 s low level threshold voltage v tl 1.9 2.2 2.5 v high level threshold v th 3.8 4.2 4.6 v differential threshold ? v th 1.7 2.0 2.3 v deadband width initial accuracy ? db1 ? 1 3 % r t1 = r t2 = 27 k ? c t = 470 pf deadband width voltage stability ? db2 ? 0.2 2.0 % 12 v v in 30 v (dmax ? dmin)/2 pwm comparator deadband width temperature stability ? db3 ? 1 ? % ?20 c ta +85 c (dmax ? dmin)/2 input offset voltage v io ? 2 10 mv input bias current i ib ? 0.8 2.0 a input sink current iosink 80 140 ? a v o = 2 v output source current iosource 80 140 ? a v o = 5 v high level output voltage v oh vref ? 1.5 ? ? v i o = 10 a low level output voltage v ol ? ? 0.5 v i o = 10 a voltage gain g v ? 55 ? db f = 10 khz band width bw ? 15 ? mhz (?) common mode voltage v cm ? 1.2 ? ? v error amp (+) common mode voltage v cm + ? ? vref ? 1.5 v (+) threshold voltage v th + 0.216 0.240 0.264 v (+) bias current i b + ? 180 250 a v cl + = 0 v (?) threshold voltage v th ? ?0.264 ?0.240 ?0.216 v 1, 2 (?) bias current i b ? ? 950 1350 a v cl = ?0.3 v 1, 2 over- current detector response time t off ? 100 ? ns cl; open v cl = +0.35 v notes: 1. only applies to the ha16107p, ha16108p 2. the terminal should not be applied under ?1.0 v. ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 15 of 39 electrical characteristics (cont.) (ta = 25 c, v in = 18 v, f osc = 100 khz) section item symbol min typ max unit test conditions note high level voltage v sth 3.2 3.8 4.4 v isink = 1 ma soft start sink current isink 7 10 13 a v st = 2.0 v v in high level thre- shold voltage v inth 14.7 16.2 17.7 v v in low level thre- shold voltage v intl 8.5 9.5 10.5 v under voltage lockout 1 threshold differential voltage ? v th 5.2 6.2 7.2 v (v inth ? v intl ) vref high level thre- shold voltage v rth 4.5 5.0 5.5 v under voltage lockout 2 vref low level thre- shold voltage v rtl 3.5 4.0 4.5 v latch threshold voltage v thh 6.5 7.0 7.5 v latch threshold voltage v in reset voltage v inr2 6.0 6.5 7.0 v reset voltage v thl2 1.0 1.3 1.6 v 1 differential threshold to uvl low voltage ? v 2.0 3.0 ? v (v intl ? v inr2 ) source current (ocl mode) isource 8 12 16 a over current detection mode timer latch, on/off timer * 2 sink current (latch mode) isink 2.5 4 5.5 a tl(on/off) terminal = 4 v low voltage v ol1 ? 1.7 2.2 v iosink = 0.2 a high voltage v oh v in ? 2.2 ? ? v iosource = 0.2 a low voltage (standby mode) v ol2 ? ? 0.5 v iosink = 1 ma rising time t r ? 40 ? ns c l = 1000 pf output falling time t f ? 60 ? ns c l = 1000 pf standby current ist ? 160 250 a v in = 14 v operation current i in1 ? 16 20 ma v in = 30 v, c l = 1000 pf, f = 100 khz operation current i in2 ? 12 16 ma v in = 30 v, f = 100 khz, output open on/off latch current i in3 ? 350 460 a v in = 14 v total v in ? gnd zener voltage v z 30 34 ? v notes: 1. only applies to the ha16108p/fp. 2. timer latch: ha16107p/fp. on/off timer: ha16108p/fp. ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 16 of 39 note on standby current in the test circuit shown in figure 1, the operating current at the start of pwm pulse output is the standby current. if the resistance connected externally to the vref pin (including r t2 ) is smaller than that of the test circuit, the apparent standby current will increase. v in c in i in vref rref ha16107 series ist + figure 1 standby current test circuit ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 17 of 39 application note ? case: when dc power is applied directly as the power supply of the ha16107/ha16108, without using the transformer backup coil. ? phenomenon: the ic may not be activated in the case of a circuit in which v in rises quickly (10 v/100 s or faster), such as that shown in figure 2. ? reason: because of the ic circuit configuration, the timer latch block operates first. ? remedy (counter measure): take remedial action such as configuring a time cons tant circuit as shown in figure 3, to keep the v in rise speed below 10 v/100 s. if the ic power supply consists of an activation resistance and backup coil, as in an ac/dc converter, the v in rise speed is usually around 1 v/100 s, and there is no risk of this phenomenon occurring. input v in v in ha16107 series gnd feedback output figure 2 example of circuit with fast v in rise time input v in v in 18 v 1 f c ha16107 series gnd feedback output r 51 ? time constant circuit figure 3 sample remedial circuit ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 18 of 39 characteristic curves 0 10203040 10 20 30 40 ta = 25 c r t1 = r t2 = 27 k ? c t = 470 pf f osc = 100 khz operating current (ma) operating current vs. power supply voltage latch current vs. power supply voltage 010203040 0.5 1.0 1.5 2.0 ta = 25 c r t1 = r t2 = 27 k ? c t =470 pf f osc = 100 khz latch current (ma) power supply voltage (v) power supply voltage (v) ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 19 of 39 048 1620 100 200 300 400 12 024 810 5 10 15 20 6 ta = 25 c v in = 20 v c t = 470 pf standby current ( a) power supply voltage (v) output v oh (v) reference voltage (v) output v oh vs. reference voltage vref uvl 2 voltage vref ovp voltage ta = 25 c r t1 = r t2 = 27 k ? c t =470 pf f osc = 100 khz standby current vs. power supply voltage ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 20 of 39 v cl (v) output off time vs. v cl 0102030 2 4 6 8 reference voltage (v) power supply voltage (v) ta = 25 c r t1 = r t2 = 27 k ? c t =470 pf f osc = 100 khz 0 0.2 0.3 0.4 100 200 300 400 v cl output off time (ns) c l = 100 pf c l = unloaded ta = 25 c r t1 = r t2 = 27 k ? c t =470 pf f osc = 100 khz reference voltage vs. power supply voltage ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 21 of 39 01 3 5 20 40 60 10 30 50 2 4 output on duty (%) error input voltage (v) output on duty vs. error input voltage ta = 25 c r t1 = r t2 = 27 k ? c t =470 pf f osc = 100 khz ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 22 of 39 0 0.1 0.2 0.3 0.4 3.0 vref 0 0.1 0.2 0.3 0.4 3.0 pwm out 0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 1.0 vref pwm out 0 ? 0.1 ? 0.2 ? 0.3 ? 0.4 ? 1.0 reference voltage and pwm out vs. c l (+) reference voltage and pwm out vs. c l ( ? ) c l (+) c l ( ? ) ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 23 of 39 30 40 50 60 70 5 10 15 20 80 ta = 25 c 0 r t1 r t2 ? 1000 0 1000 2000 ? 2000 ? 20 0 25 50 75 85 timing resistance r t1, r t2 ( k ? ) deadband duty (%) timing resistance vs. deadband duty temperature fluctuation vs. ambient temperature temperature fluctuation (ppm) ambient temperature ( c) v in = 18v r t1 = r t2 = 27 k ? c t = 470 pf f osc = 100 khz v in = 18v c t = 470 pf f osc 100 khz ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 24 of 39 02550 85 ? 5 0 5 10 75 ? 20 ? 10 02550 85 ? 5 0 5 10 75 ? 20 ? 10 frequency variance (%) ambient temperature ( c) frequency variance vs. ambient temperature frequency variance vs. ambient temperature frequency variance (%) ambient temperature ( c) v in = 18v r t1 = r t2 = 27 k ? c t = 120 pf f osc = 3 00 khz v in = 18v r t1 = r t2 = 27 k ? c t = 470 pf f osc = 100 khz ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 25 of 39 02550 85 ? 5 0 5 10 75 ? 20 ? 10 02550 85 ? 5 0 5 10 v in = 18v 75 ? 20 ? 10 f = 100 khz f = 300 khz f = 600 khz frequency variance (%) output on duty variance (%) v in = 18v r t1 = r t2 = 13 k ? c t = 120 pf f osc = 600 khz output on duty variance vs. ambient temperature ambient temperature ( c) ambient temperature ( c) frequency variance vs. ambient temperature ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 26 of 39 600 500 300 100 90 70 50 30 10 9 7 5 7 10 30 50 70 100 3300 pf 820 pf 470 pf 270 pf c t = 120 pf oscillator frequency (khz) timing resistance r t1 (= r t2 ) (k ?) oscillator frequency vs. timing resistance v in = 18 v ta = 25 c ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 27 of 39 ? 500 0 500 0 10 20 30 i o (ma) 200 ns/div ? 500 0 500 0 10 20 30 i o (ma) vout (v) vout (v) vout output rising waveform vout output falling waveform 40 40 200 ns/div v in out cl (+) r t1 c t s t r t2 vref tl 1 f + + c st 1 f 27 k ? 470 pf 27 k ? 1000 pf c l i o current probe * current probe: tektronix am503 test circuit ta = 25 c r t1 = r t2 = 27 k ? c t = 470 pf f osc = 100 khz ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 28 of 39 0 1 2 3 4 5 6 v tl (v) 0.5 sec/div 7 t on t off sw on sw off when overcurrent is input at the point where the duty cycle is 0%. 0 1 2 3 4 5 6 v tl (v) 7 when overcurrent is input at the point where the duty cycle is 30%. operating waveform at the tl pin output pulse shutdown region t on t off sw on sw off output pulse shutdown region a b a b 0.5 sec/div v in out cl(+) r t1 c t s t r t2 vref tl 1 f + + c st 1 f 27 k ? 470 pf 1000 pf c l sw t2 t1 du = 100 (%) t1 t2 t v tl a b c t v tl test circuit triangle wave cl(+) when input at a duty of 0% cl(+) when input at a duty of 30% enlargement of section ctl discharged at 4 a ctl discharged at 12 a ctl discharged at 4 a : pwm pulse output is high : the point where overcurrent is detected : pwm pulse output is low. a to b b b to c b enlargement of section a clock 27 k ? v in = 18v ha16107 r t1 = r t2 = 27 k ? c t = 470 pf f osc = 100 khz ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 29 of 39 out output pulse shutdown region triangle wave cl(+) when input at a duty of 0% cl(+) when input at a duty of 30% du = 100 (%) enlargement of section ctl discharged at 4 a ctl discharged at 12 a t 1 t 2 0.5 sec/div 0.5 sec/div sw off sw on on/off clock cl(+) r t1 t off t on t off t on t off t 1 t 2 t on + + c t v t tl c st c l v = 18v in r = r = 27 k? t1 t2 c = 470 pf t f = 100khz osc s 1 f 1 f t r 27 k? 27 k? 470 pf 1000 pf t2 operating waveform at the on/off pin 7 6 5 4 3 2 1 0 v on/off (v) b a output pulse shutdown region sw off sw on t off t on t off t on 7 6 5 4 3 2 1 0 v on/off (v) b a a a b a b b c c b enlargement of section ctl discharged at 4 a to : pwm pulse output is high. : the point where overcurrent is detected. to : pwm pulse output is low. v t tl b v in test circuit ha16108 when overcurrent is input at the point where the duty cycle is 0%. when overcurrent is input at the point where the duty cycle is 30%. ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 30 of 39 error amplifier characteristic 10 k 0 20 40 180 90 0 a vo 45 135 60 30 k 100 k 300 k 1 m input signal frequency f in (hz) open loop gain a vo (db) phase change (deg) 3 m 10 m 30 m 100 m examples of drooping characteristics of power supplies using these ics normal operation 0 2.5 5.0 1 v out (dc) (v) 2 i out (dc) (a) i out (dc) (a) ha16107 (latch shut-down) 34 0 1234 pulse by pulse current limiter operation a heavy load b light load on on off off a a b b 2.5 5.0 v out (dc) (v) pulse by pulse current limiter operation a heavy load b light load latch state here ha16108 (intermittent operation by means of on/off timer) ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 31 of 39 operating circuit example ac input + ? + + + ? + + ? + + ? ? ? bridge diode ? 82 k ? 1 w 51 ? 40t 23t 1.5 ? 3 w 50 v hzp 16 tl e/o in( ? ) in(+) nc gnd st 1 f 1 f vref 110 ? 51 ? 27 k ? ha16107p/fp 27 k ? cl( ? ) cl(+) v e r t1 r t2 c t v out in 470 pf 4700 pf 22 f 16 v 330 k ? 33k ? 33k ? 68 k ? 510 k ? 16 v 16 v 3.225 v 6.45 v 6.45 v zener type reference voltage generation circuit 34 v error amp. 3.4 v 10 a 1 f 6t 2sk1567 140 v el-30 trans former 470 f 5 v output hrp 24 hrp 32 18.9 v schottky barrier diode hzp 16 start-up resistor current sense current sense l.p.f. ovp detector timerlatch capacitor phase comp. frequency, max, duty setting fosc = 100 khz, dumax = 50% flyback transforrmer application example (ic vref used as system as reference voltage) rfi filter 11 12 10 9 13 14 15 16 6 5 7 8 4 3 2 1 soft start cap. out v qclm c v vref vref uvl2 4 a 16 a 140 a current limiter e q r r s q o v p uvl1 uvl1 uvl1&uvl2 pwm comparator triangle wave p{ulse by pulse latch on/off latch (v = 7v) st h l l th h v in v v uvl2 h l 4v 5v s q ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 32 of 39 ac input bridge diode power thermister 200 v 100 f dfg1c8 hrw26f 47 h 0.5 8 t * 0.5 8 t * 0.3 50 t 0.3 50 t 50 v 22 f + ? 16 v 1000 f 3.3 f 1.8 k ? 4.7 k ? b secondary error amplifier tlp521 * bifiler transfomer core size ei-30 equivalent product dc out (5 v) 330 ? 3.3 k ? + ? + ? + ? + ? hzp16 13 k ? + + + 0.47 f 1 w 82 k ? 10 k ? 1 f 1 f (start-up resistor) (soft start capacitor) ? ? ? 13 k ? 12345678 9 10 11 12 13 14 15 16 tl r b v out r t1 c t c t2 e/o in ( ? ) cl (+) ha16107p/108p in (+) nc st vref 51 ? 51 ? 4700 pf 470 pf 110 ? 2sk1567 3 w 1.5 ? (current sense) (current sense filter) timer latch capacitor ? forward transformer application example ha17431p ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 33 of 39 v in r b ovp detector 1 f + tl v in out cl(+) ? when ovp signal is inserted at cl(+) pin when the ovp detection zener diode turns on, latch shutdown of the output is performed after the elapse of the time determined by the capacitance connected the tl pin. ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 34 of 39 application 1. use of error amplifier for flyback transformer primary-side control in this example, the fact that the transformers winding ratio and voltage ratio in figure 4 are mutually proportional is made use of in a flyback transformer type ac-dc converter. as fluctuation of output voltage v 2 also appears in ic power supply voltage v 3 , this is divided by a resistance and amplified by an error amplifier. an advantage of this method is that a photocoupler need not be used, making it possible to configure a power supply with a small number of parts (this example cannot be applied to a forward transformer). 14 11 15 commercial ac input v 3 (ic power supply voltage) error amp. 2.5v r 2 r 1 r 4 r 3 ? + e/o flyback transformer n 1 n 3 n 2 start-up resistance to switch element c 1 ? v 1 (input voltage) v 2 (output voltage) output r 1 + r 2 r 2 n 3 n 2 v 3 = 2 1 vref v 3 = v 2 , where figure 4 error amplifier peripheral circuitry diagram ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 35 of 39 in figure 5, the parameters are given by the following equations. gain g 1 = v 3 /v 2 r 3 /r 1 g 2 = v 3 /v 2 r 4 /r 1 corner frequencies f 1 = 1/(2 c 1 r 3 ) f 2 = 1/(2 c 1 r 4 ) where r3>>r4 (10:1 or above) g 1 is made around 30 to 50 db, taking both regulati on and stability into consideration. f 1 is made a lower value than commercial frequency ripple f ac , thus preventing hunting (a system instability phenomenon). next, g 2 is set to 0 db or less as a guideline, so that there is no gain in ic operating frequency f osc (several tens to several hundreds of khz). f 2 should be set to a value that is substantially smaller than f osc , and that is appropriate for the power supply response speed (several khz). in the case of a bridge type rectification circuit, the commercial frequency ripple is twice the input frequenc y (with a 50 hz commercial frequency, f ac = 100 hz). 2. external constant design for current detection section (ha16107, ha16108, ha16666) in the above ic models, which incorporat e a current detection function, a low-pass filter such as shown in figure 6 must be inserted between switch elemen t current detection resistance r cs and the current detection pin of the ic. output switch element power mos fet floating capacitance input voltage from pwm output pin of ic to current detection pin of ic current detection resistance several hundred m ? to several ? filter (lpf) c a r b r cs r a i d c x v b 140v v 11 v 12 figure 6 current detection circuit ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 36 of 39 the reason for this is that, when the sw itch element is on in each cycle, there is an impulse current associated with charging of transformer floating capacitance c x , and ic current detection malfunctions (see figure 7). v 11 v th v 12 figure 7 current detection waveform ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 37 of 39 3. ic heat emission problem and count ermeasures (ha16107 series, ha16114 series) while the above ics can directly drive a power mos fet gate, if the method of use is not thoroughly investigated, there will be a tendency for the gate drive power to increase and a problem of heat emission by the ic may occur. this section should therefore be noted and appropriate measures taken to prevent this kind of problem. 1. power mos fet drive characteristics when power mos fet drive is performed, in order to lower the on-resistance sufficiently, overdrive is normally performed with a voltage considerably higher than 5 v, for example, such as the 15 v power supply voltage of the ic. at this time, the power that should be supplied from the ic to the power mos fet is determined by gate load qg in figure 9. 2. ic heat-emission power calculation (figure 9) the power that contributes to ic heat emission is calculated by means of the following equation. pd = v in i q + 2qg v in f where v in : power supply voltage of ic i q : operating current of ic (unloaded) qg : above-mentioned gate load f : operating frequency of ic the coefficient, 2, indicates that gate discharging also contributes to heat emission. 4. power mos fet gate resistance design (ha16107 series, ha16114 series) there are the following three purposes in c onnecting a gate resistance, and the circuit is generally of the kind shown in figure 8. (1) to suppress peak current due to gate charging (2) to protect ic output pins (3) to provide drive appropriate to power mos fet input characteristics r g1 d g out c s r cs ic output pin to transforme r power mos fet r g2 figure 8 gate drive circuit ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 38 of 39 this gate resistance r g is given by the following equation. r g = (v g /i g ) ? (v g t on )/qg, r g = r g1 + r g2 i g : gate input peak current v g : gate drive voltage wave high value (equal to power supply voltage of ic) t on : power mos fet turn-on time t off : power mos fet turn-off time qg : gate charge according to figure 9 v ds v ds (v) v gs v gs (v) qg (nc) figure 9 power mos fet dynamic input characteristics refer to the power mos fet catalog for information on t on and qg. by dividing r g into r g1 and r g2 , it is possible for speed to be slowed when the power mos fet is on, and increased when off. power mos fet on and off times when mounted, t on ? and t off ?, are as follows. t on ? = t on + qg(r g1 + r g2 )/v g t off ? = t off + qg ? r g2 /v g ha16107p/fp, ha16108p/fp rev.4.00 jun 15, 2005 page 39 of 39 package dimensions package code jedec jeita mass (reference value) dp-16 conforms conforms 1.07 g 6.30 19.20 16 9 8 1 1.3 20.00 max 7.40 max 7.62 0.25 + 0.13 ? 0.05 2.54 0.25 0.48 0.10 0.51 min 2.54 min 5.06 max 0 ? 15 1.11 max as of january, 2003 unit: mm f e 1 y xm p * 3 * 2 * 1 8 9 16 index mark b z a h e d terminal cross section p 1 1 c b b c detail f 1 1 l l a 0.80 0.15 1.27 7.50 8.00 0.42 0.34 p a 1 10.5 fp-16da renesas code jeita package code previous code max nom min dimension in millimeters symbol reference 2.20 0.90 0.70 0.50 0.20 5.5 0.20 0.10 0.00 0.50 0.40 0.27 0.22 0.17 7.80 8 0 0.12 1.15 10.06 0.24g mass[typ.] 1 e 1 1 2 l z h y x c b a e d b c e l a p-sop16-5.5x10.06-1.27 prsp0016dh-a note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is al ways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating i n the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents in formation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or e rrors. please also pay attention to information published by renesas technology corp. by various means, including the renesas technolo gy corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, an d algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under cir cumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materia ls. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lice nse from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. unit2607 ruijing building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices ? 200 5. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon 2.0 |
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