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[ak7780] 24bit 5ch adc & src + audio dsp ak7780 the ak7780 is a highly integrated audio processor, including a 28-bit float ing point dsp, two 24-bit stereo adc?s and one mono adc. the stereo adc?s feature high performance, achieving 96db dynamic range, they include 8:1 input selectors. the adc supports sampling frequencies from 7.35 khz to 96 khz. the ak7780 also includes a stereo sample rate converter (src), so it can be used as a master device when it receives digital audio inputs. the dsp includes 168kbits of sram for audio delay data that is suitable for creating simulated surround fields. the programmabl e dsp block is realized with 2560step/fs dsp. it supports sampling frequencies from 7.35khz to 96 kh z. the ak7780 is used to implement complete sound field control, such as echo, 3d, parametric equalization, and other sound enhancements. it is packaged in a 100-lead lqfp package. general description features [dsp] main ? word length: 28-bit (data ram f24.4 limited range floating point) ? instruction cycle time: 8.1 ns (2560step/fs fs=48khz; 1280step/fs fs=96khz) ? multiplier: 24 x 16 40-bit (double precision available) ? divider: 24 / 24 24-bit ? alu: 44-bit arithmetic operation (overflow margin: 4-bits) f24.4 arithmetic and logic operation ? shift+register: flexible setting ? program ram: 2048 x 36-bit ? coefficient ram: 2048 x 16-bit ? data ram: 2048 x 28-bit (f24.4[sign bit + 23-bit mantissa + 4-bit exponent]) ? offset ram: 64 x 13-bit ? internal delay ram: 168kbits ( 6144 x 28 bit / 2048 x 28 bit + 8192 x 14 bit / 3072 x 28 bit + 6144 x 14 bit / 4096 x 28 bit + 4096 x 14 bit) 4 pattern setting 28bit = f24.4 [24 bit sign & mantissa: 4 bit exponent] 14bit = f10.4 [10 bit sign & mantissa: 4 bit exponent] ? sampling frequency: 7.35khz ~ 96khz ? serial interface port for microcontroller or i 2 c bus control ? master clock: 2560fs (generated by pll from 32fs ,64fs, 256fs and 384fs) ? master/slave operation ? serial signal input port (10ch): msb justifie d 24-bit / lsb justified 16/20/24-bit and i 2 s ? serial signal output port(12ch): msb justifie d 24-bit / lsb justified 24,16-bit and i 2 s (sdout1,sdout2 and sdout3) [adc] 4 channels (2 stereo pairs) ? 24-bit 64x over-sampling delta-sigma (fs = 7.35khz ~ 96khz) ? dr, s/n: 96dba (fs = 48khz, fully-differential input) ? s/(n+d): 92db (fs = 48khz) ? digital hpf (fc = 1hz) ms0581-e-00-pb 2007/09 - 1 -
[ak7780] [adc] mono single channel ? 24-bit 64x over-sampling delta sigma (fs = 7.35khz ~ 96khz) ? dr, s/n: 95dba ( fs = 48khz) ? includes digital attenuator [src] stereo pair ? input frequency 7.35khz ~ 96khz output frequency 44.1khz ~ 96khz [other] ? power supply: +3.3v 0.3v, +1.7v~+2.0v(typ +1.8v) ? operating temperature range: -40 c~85 c ? package: 100pin lqfp(0.5mm pitch) ms0581-e-00-pb 2007/09 - 2 -
[ak7780] block diagram src_bick src_lrck pull down hi-z ctrl reg sw 4 vref 3 ainl-,ainr- a inl2,ainr2 a inl3,ainr3 a inl5,ainr5 a inl4,ainr4 2 a inl6,ainr6 a inl7,ainr7 a inl8,ainr8 a inm a dc2 a dc1 asel1[2:0] asel2[2:0] sdouta1 avss vrefl vcom vrefh avdd ainl+,ainr+ a dcm mux vol p_dsprst p_srcrst src_lflt testo p_ckrst init_reset srcset[1] srcset[0] sdout6 outa1e_ n sdout1 sclk/scl so sdout4 sdout3 sdout2 si/cad0 rq_n/cad1 sdin3 sdin5 sdin2 sdin1 sdout4 sdout3 sdout2 sdout1 sdin4 sdin3 sdin2 sdin1 dsp lrclk_i smode lflt controller xti xto clko1 sdin5 sdin4 sdout5 clko2 sdout5 out5e_ n out4e_ n out3e_ n out2e_ n out1e_ n wdt sto rdy gpo0 gpo1 swg1 swg0 clko2e_n clko1e_n lrclk_o bitclk_o bitclk_i sda irpt swirp t (master="h",slave="l") jx0 crc_e testi2 ckm[2:0] 3 i2csel src seli5 seli4 p_srcsmute r_srcsmute r_srcrst_n crc jx1 wdte_n lock_e jx1 jx0 7 3 8 3 dvdd18 dvss bvss 2 srcout unlock r_ckrst_n r_dsprst_n testi1 p_adrst r_adrst_n ckrst_n s_reset_n dsprst_n a drst_n micif sel_sdo1 jx2 0 2 1 3 0 2 1 3 seloa1[1:0] seloa2[1:0] jx2 3 sdin6 seli3 srci seli1 sdout6 sel_sdo6 dvdd 6 i/o out6e_ n sel_sdo2 2 2 2 2 2 2 figure 1. whole block diagram * figure 1 shows a simplified diagram of the ak7780, which isn?t the perfect same as the actual circuit diagram. each \ describes the relationship of rese t control and target reset blocks. ms0581-e-00-pb 2007/09 - 3 -
[ak7780] cp0,cp1 cram 2048w16bit dp0 dram 1024w 28bit mpx16 mpx24 ofram 64w13bit x y multiply 16bit24bit 40bit micon i/f control pram 2048w 36bit dec pc stack : 5level(max) mul dbus shift a b alu 44bit overflow margin: 4bit dr0~3 over flow data generator division 24 24 24 peak detector serial i/f cbus(16bit) dbus(28bit) 40bit 28bit 44bit 44bit 44bit sdout4 dlram 6kw28bit (default) ptmp(lifo) 62 t 8bi dlp0,dlp1 dp1 1024w 28bit tmp 28bi 224bit 8 t 224/20/16bit 224/20/16bit sdin3 224/20/16bit 224/20/16bit sdin1 sdin2 sdin4 sdout2 224/20/16bit sdin5 224/16bit 224/16bit 224/16bit 224bit 224bit sdout5 44bit sdout3 sdout1 sdin6 224bit sdout6 figure 2. dsp block diagram ms0581-e-00-pb 2007/09 - 4 -
[ak7780] ordering guide AK7780VQ -40 +85 c 100pin lqfp(0.5mm pitch) akd7780 evaluation board for ak7780 pin layout (top view) 100 p in lqf p testo so 76 77 78 79 80 81 82 83 84 8 5 87 88 86 89 91 92 90 93 94 9 5 97 98 96 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 4 5 44 43 42 41 39 38 40 37 3 5 34 36 33 32 31 29 28 30 27 26 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 sto sdouta1 sdout6 clko2 dvdd dvss dvdd18 jx2 jx1 jx0 sdin1 src_bick src_lrck dvdd18 rdy dvss dvdd bvss p_srcsmut testi2 avdd avss src_lflt ainm ainr4 dvdd dvss ainl4 ainl2 avdd vrefh vcom vrefl ainr5 ainr+ ainl- ainl6 ainr7 ainr8 ainl8 avdd testi1 i2csel dvdd18 si / cad0 sclk/scl p_ckrst rq / cad1 p_dsprst dvss dvdd18 sdin5 bitclk_i dvdd18 sdout5 srcset[0] bvss dvdd dvss xti ainr3 ainl3 bitclk_o sdout1 sdin4 ainr2 lflt sdout4 sdout3 p_adrst ainr6 ainl5 avss ainr- sdin2 ainl7 srcset[1] sdout2 sdin3 input output i/o power input output i/o power pin clko1 avss ainl+ dvss dvdd18 xto dvss dvdd lrclk_o lrclk_i dvdd init_reset ckm[1] ckm[0] ckm[2] dvdd18 dvss p_srcrst sda ms0581-e-00-pb 2007/09 - 5 -
[ak7780] pin function no pin name i/o function classification 1 lflt o filter connection pin for ak7780 core pll when using the pll function, connect with r (1.5k ) and c (47nf) in series and connected to analog ground (avss) see. 9. system design (1) analog output 2 avss - analog ground 0v 3 avdd - power supply pin for analog section 3.3v (typ) analog power supply 4 testi1 i test pin (internal pull-down) * connect to dvss test 5 i2csel i i 2 cbus select pin * i2csel= ?l?: normal serial interface * i2csel= ?h?: i 2 cbus selected mode. scl and sda are active. i2csel must be set to ?l (dvss)? or ?h (dvdd)?. i 2 c select 6 srcset [1] i src select pin 1 7 srcset [0] i src select pin 0 src 8 bvss - silicon substrate potential 0v connect to avss. analog power supply 9 dvdd - power supply pin for digital section 3.3v (typ) 10 dvss - ground pin for digital section 0v digital power supply 11 xti i master clock input pin connect a crystal between this pin and the xto pin, or input an external cmos clock signal to the xti pin. 12 xto o crystal oscillator output pin when using a crystal, connect it between xti and xto. when using an external clock, keep this pin open. system clock 13 dvss - ground pin for digital section 0v 14 dvdd18 - power supply pin for digital section 1.8v (typ) digital power supply 15 ckm [1] i clock mode select pin 1 16 ckm [0] i clock mode select pin 0 17 ckm [2] i clock mode select pin 2 mode select 18 dvdd18 - power supply pin for digital section 1.8v (typ) 19 dvss - ground pin for digital section 0v digital power supply 20 dvdd - power supply pin for digital section 3.3v (typ) ms0581-e-00-pb 2007/09 - 6 -
[ak7780] no pin name i/o function classification 21 lrclk_o o lr channel select clock output pin master mode: outputs fs clock. slave mode: outputs lrclk_i clock. 22 bitclk_o o serial bit clock output pin master mode: outputs 64fs clock. slave mode: outputs bitclk_i clock system clock 23 sdout1 o dsp serial data output pin * compatible with msb justified 24 bits / i 2 s. 24 sdout2 o dsp serial data output pin * compatible with msb justified 24 bits / i 2 s. 25 sdout3 o dsp serial data output pin * compatible with msb justified 24 bits / lsb justified 24 and 16 bits/ i 2 s. digital section 26 sdout4 o dsp serial data output pin * compatible with msb justified 24 bits / lsb justified 24 and 16 bits/ i 2 s. 27 sdout5 o dsp serial data output pin * compatible with msb justified 24 bits / lsb justified 24 and 16 bits/ i 2 s. serial output data 28 clko1 o clock output pin 1 select the output frequency through a control register. clock output 29 dvdd - power supply pin for digital section 3.3v(typ) 30 dvss - ground pin for digital section 0.0v 31 dvdd18 - power supply pin for digital section 1.8v(typ) digital power supply 32 sdin2 i dsp serial data input pin compatible with msb justified 24 bits / lsb justified 24, 20 and 16 bits / i 2 s. * if not used, connect to dvss 33 sdin3 i dsp serial data input pin compatible with msb justified 24 bits / lsb justified 24, 20 and 16 bits / i 2 s. * if not used, connect to dvss 34 sdin4 i dsp serial data input pin compatible with msb justified 24 bits / lsb justified 24, 20 and 16 bits / i 2 s. * if not used, connect to dvss digital section serial input data 35 sdin5 i dsp serial data input pin compatible with msb justified 24 bits / lsb justified 24, 20 and 16 bits / i 2 s. * if not used, connect to dvss ms0581-e-00-pb 2007/09 - 7 -
[ak7780] no pin name i/o function classification 36 bitclk_i i serial bit clock input pin 37 lrclk_i i lr channel select clock input pin. system clock 38 dvdd18 - power supply pin for digital section 1.8v(typ) 39 dvss - ground pin for digital section 0.0v digital power supply 40 init_reset i reset pin ( for initialization) use for initialization. when changing ckm[2:0], xti or bitclk_i input frequency, this reset pin must be used. 41 p_ckrst i clock reset pin when changing ckm[2:0] and xti or bitclk_i input frequency without using init_reset, p in control is necessary. the control register r_ckrst_n can also rest the clock. i adc reset pin the control register r_adrst _n can also reset the adc. 42 p_adrst p_adrst = ?l? and p_dsprst = ?l? state causes a system reset (s_reset). i dsp reset pin the control register r_dsprst _n can also rest the dsp. 43 p_dsprst p_adrst = ?l? and p_dsprst = ?l? state causes a system reset (s_reset). reset 44 rq i i2csel= ?l? microcomputer interface write request pin. after initial reset, if the microcomputer interface is not used, leave rq = ?h? microcomputer interface. cad1 i i2csel=?h? i 2 c bus address setting pin 1 i 2 c 45 si i microcomputer interface serial data input and serial data output contro l pin. when si is not used, leave si = ?l?. microcomputer interface. cad0 i i2csel= ?h? i 2 c bus address pin 0 i 2 c 46 sclk i i2csel= ?l? microcomputer interface serial data clock pin. when sclk is not used, leave sclk= ?h? microcomputer interface. scl i i2csel= ?h? i 2 c bus data clock pin i 2 c 47 dvdd18 - power supply pin for digital section 1.8v(typ) 48 dvss - ground pin for digital section 0.0v 49 dvdd - power supply pin for digital section 3.3v(typ) digital power supply 50 so o serial data output pin for microcomputer interfaces. when rq = ?h?, so = hi-z microcomputer interface. ms0581-e-00-pb 2007/09 - 8 -
[ak7780] no pin name i/o function classification 51 rdy o data write ready output pin for microcomputer interface. microcomputer interface. 52 sto o status output pin normal state output ?h?. when wdt, crc error or src unlock occurs, then output ?l?. see 3.(1) whole block diagram. status 53 sdouta1 o dsp or adc serial data output pin * compatible with msb justified 24 bits / i 2 s. 54 sdout6 o dsp or adc serial data output pin digital section * compatible with msb justified 24 bits / i 2 s. serial output data 55 clko2 o clock output pin 2 select the output frequency through a control register. clock output 56 dvdd - power supply pin for digital section 3.3v(typ) 57 dvss - ground pin for digital section 0.0v 58 dvdd18 - power supply pin for digital section 1.8v(typ) digital power supply 59 jx2 i external condition jump pin * when not used, connect to dvss 60 jx1 i external condition jump pin * when not used, connect to dvss conditional input 61 jx0 i external condition jump pin * when not used, connect to dvss 62 sdin1 i dsp/src serial input pin input pin for src. when not used, connect to dvss. digital section serial input data 63 src_bick i src serial bit clock input pin. 64 src_lrck i src lr channel select clock input pin. src i i2csel= ?l? sda outputs ?l? level. 65 sda i/o i2csel= ?h? i 2 c bus interface data pin i 2 c 66 p_srcrst i src reset pin the control register r_srcrst_n can also rest the src. reset 67 dvdd18 - power supply pin for digital section 1.8v(typ) 68 dvss - ground pin for digital section 0.0v 69 dvdd - power supply pin for digital section 3.3v(typ) digital power supply 70 bvss - silicon substrate potential 0v connect to avss. analog power supply 71 p_src smute i src soft mute pin the control register r_srcsmute can also execute a soft mute on the src. src 72 testi2 i test pin ( internal pull-down ) * connect to dvss. test 73 avdd - power supply pin for analog section 3.3v (typ) 74 avss - analog ground 0v analog power supply 75 src_lflt o rc filter connection pin for src. analog output see p.86 10-2-5-2: src pll loop filter setting. ms0581-e-00-pb 2007/09 - 9 -
[ak7780] no pin name i/o function classification 76 testo o test out pin hi-z output pin. leave it open. test 77 ainm i adcm single ended analog input 78 ainr4 i adc1 or adc2 rch single ended analog input 4 79 ainl4 i adc1 or adc2 lch single ended analog input 4 80 ainr3 i adc1 or adc2 rch single ended analog input 3 81 ainl3 i adc1 or adc2 lch single ended analog input 3 82 ainr2 i adc1 or adc2 rch single ended analog input 2 83 ainl2 i adc1 or adc2 lch single ended analog input 2 analog input 84 avdd - power supply pin for analog section 3.3v (typ) analog power supply 85 vrefh i analog reference voltage input pin . connect to avdd, and connect 0.1 f and 10 f bypass capacitors between this pin and avss. analog input 86 vcom o common voltage connect to 0.1 f and 10 f capacitors between this pin and avss. do not connect to external circuitry. analog output 87 vrefl i analog reference voltage input pin for low-level. connect to avss. analog input 88 avss - analog ground 0v analog power supply 89 ainr? i adc1 or adc2 rch inverted input pin 90 ainr+ i adc1 or adc2 rch non- inverted input pin 91 ainl? i adc1 or adc2 lch inverted input pin 92 ainl+ i adc1 or adc2 lch non- inverted input pin 93 ainr5 i adc1 or adc2 rch single ended analog input 5 94 ainl5 i adc1 or adc2 lch single ended analog input 5 95 ainr6 i adc1 or adc2 rch single ended analog input 6 analog input 96 ainl6 i adc1 or adc2 lch single ended analog input 6 97 ainr7 i adc1 or adc2 rch single ended analog input 7 98 ainl7 i adc1 or adc2 lch single ended analog input 7 99 ainr8 i adc1 or adc2 rch single ended analog input 8 100 ainl8 i adc1 or adc2 lch single ended analog input 8 note 1. digital input pins must not be allowed to float note 2. if analog input pins (ainr?, ainr+, ainl?, ainl+, ainl2-8, ainr2-8, ainm) are not used, leave them open. note 3. i2csel should be set to ?l? (dvss) or ?h? (dvdd). relationship with i2csel and sda. i2csel init_reset sda normal microcontroller l l l interface l h l i 2 c bus compatible h l ?hi-z? pull-up h h function ms0581-e-00-pb 2007/09 - 10 -
[ak7780] (avss = bvss = dvss = 0v: all indicated voltages are with respect to ground.) item symbol absolute maximum ratings min max unit power supply voltage analog(avdd) digital(dvdd) digital(dvdd18) |avss(bvss) ? dvss| ( note 4 ) va vd vd18 gnd -0.3 -0.3 -0.3 4.3 4.3 2.5 0.3 v v v v input current (except for power supply pin ) iin - 10 ma analog input voltage ainl+, ainl?, ainr+, ainr?, ainl2-8, ainr2-8, ainm vrefh,vrefl vina -0.3 va+0.3 v digital input voltage vind -0.3 vd+0.3 v operating ambient temperature ta -40 85 c storage temperature tstg -65 150 c note 4. avss (bvss) should be at the same level as dvss. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these critical conditions. (avss = bvss = dvss = 0v: all indicated voltages are with respect to ground.) items symbol min recommended operating conditions typ max unit power supply voltage avdd dvdd dvdd18 va vd vd18 3.0 3.0 1.7 3.3 3.3 1.8 3.6 3.6 2.0 v v v reference voltage (vref) vrefh ( note 5 ) vrefl ( note 6 ) vrh vrl va 0.0 v v note 5. vrefh normally connects to avdd. note 6. vrefl normally connects to avss note : the analog input voltage and output voltage are proportional to the vrefh-vrefl voltages. * akemd assumes no responsibility for the usag e beyond the conditions in this datasheet. ms0581-e-00-pb 2007/09 - 11 -
[ak7780] electric characteristics (1) analog characteristics 1) adc characteristics (unless otherwise specified, ta = 25 c; avdd = dvdd = 3.3v, dvdd18=1.8v; vrefh = avdd, vrefl = avss; bitclk = 64 fs; signal frequency = 1khz; measurement bandwidth = 20hz to 20khz @ 48khz, 20hz ~ 40khz @ 96khz; adc specified with differential inputs (adc1, adc2); ckm mode 1(ckm[2:0]= ?000?), src reset) parameter min typ max unit resolution 24 bits dynamic characteristics s/(n+d) fs = 48khz (-1dbfs) ( note 7 ) fs = 96khz (-1dbfs) 82 92 90 db db dynamic range fs = 48khz (a filter) ( note 7 , note 8 ) fs = 96khz 88 96 93 db db stereo adc adc1 adc2 s/n fs = 48khz (a filter) ( note 7 ) 88 96 db fs = 96khz 93 db inter-channel isolation (f=1khz) ( note 9 ) 90 115 db dc accuracy channel gain mismatch 0.1 0.3 db analog input input voltage ( differential input ) ( note 10 ) 1.85 2.00 2.15 vp-p input voltage ( single-ended input ) ( note 11 ) 1.85 2.00 2.15 vp-p input impedance ( note 12 ) 22 33 k resolution 24 bits dynamic characteristics monaural s/(n+d fs = 48khz (-1dbfs) fs = 96khz ( -1dbfs) 78 88 87 db db adc part adcm dynamic range fs = 48khz (a filter) ( note 8 ) 87 95 db fs = 96khz 92 db s/n fs = 48khz (a filter) 87 95 db fs = 96khz 92 db analog input input voltage ( note 13 ) 1.85 2.00 2.15 vp-p note 14 ) input impedance ( 22 33 k note 7. this value is not guaranteed for single-ended inputs. note 8. indicates s/(n+d) when -60 dbfs signal is applied. note 9. indicates isolation between l and r when -1dbfs signal is applied. note 10. target input pins are ainl+, ainl-, ainr+ and ainr-. differential full scale is ( fs=(vrefh-vrefl)x(2.0/3.3)) note 11. target input pins are ainl2~l8, ainr2~r8., single-ended full scale is (fs=(vrefh-vrefl) x (2.0/3.3)) note 12. target input pins are ainl+, ainl?, ainr+, ainr?, ainl2-l8, ainr2-r8. note 13. target input pin is ainm, the full scale of this pin is (fs=(vrefh-vrefl) x (2.0/3.3)) note 14. target input pin is ainm. ms0581-e-00-pb 2007/09 - 12 -
[ak7780] 2) src characteristics (ta=25 c; avdd = 3.3v; dvdd=3.3v; dvdd18=1.8v; data = 24-bits; measurement bandwidth = 20hz fso/2; unless otherwise specified.) parameter symbol min typ max units resolution 24 bits input sample rate fsi 7.35 96 khz output sample rate fso 44.1 96 khz thd+n (input= 1khz, 0dbfs) fso/fsi=44.1khz/48khz -113 db fso/fsi=44.1khz/96khz -112 db fso/fsi=48khz/44.1khz -113 db fso/fsi=48khz/96khz -113 db fso/fsi=48khz/8khz -112 -103 db dynamic range (input= 1khz, -60dbfs) fso/fsi=44.1khz/48khz 114 db fso/fsi=44.1khz/96khz 114 db fso/fsi=48khz/44.1khz 114 db fso/fsi=48khz/96khz 114 db fso/fsi=48khz/8khz 110 114 db dynamic range (input= 1khz, -60dbfs, a-weighted fso/fsi=44.1khz/48khz 116 db ratio between input and output sample rate fso/fsi 0.45 6 - ms0581-e-00-pb 2007/09 - 13 -
[ak7780] (2) dc characteristics (ta = -40 c ~ 85 c; avdd = dvdd = 3.0~3.6v; dvdd18 = 1.7~2.0v) parameter symbol min typ max unit high level input voltage ( note 15 ) vih 80%dvdd v low level input voltage ( note 15 ) vil 20%dvdd v scl,sda high level input voltage vih 70%dvdd v scl,sda low level input voltage vil 30%dvdd v voh dvdd-0.5 v high level output voltage iout=-100 a vol 0.5 v low level output voltage iout=100 a ( note 16 ) sda low level output voltage iout=3ma vol 0.4 v input leak current ( note 17 ) iin 10 a input leak current (pull-down) ( note 18 ) iid 22 a input leak current (xti pin ) iix 26 a note 15. scl (i2csel=1) and sda pins are not included. (sclk pin is included when i2csel=0) note 16. sda pin is not included. note 17. the pull-down pins and xti pin are not included. note 18. the pull-down pins (typ150k ) are: testi1, testi2 (3) current consumption (ta=25 c; avdd=dvdd=3.0~3.6v(typ=3.3v,max=3.6v); dvdd18=1.7~2.0v(typ=1.8v, max=2.0v)) power supply parameter min typ max unit power supply current ( note 19 ) 1) a) avdd 52 70 ma b) dvdd 8 15 ma c) dvdd18 110 165 ma 1 ma 2) init_reset = ?l? (reference) ( note 20 ) note 19. varies slightly according to the syst em frequency and contents of the dsp program. note 20. this is a reference value when using a crystal oscillator. since most of the supply current at the initial reset state is in the oscillator section, the value may vary slightly according to the crystal type a nd the external circuit. this is a ?reference value? only. ms0581-e-00-pb 2007/09 - 14 -
[ak7780] (4) digital filter characteristics 1) adc section: adc1, adc2 (ta=-40 c~85 c; avdd = dvdd =3.0v~3.6v; dvdd18=1.7v~2.0v; fs=48khz; note 21 ) parameter symbol min typ max unit pb 0 21.5 khz pass band ( 0.005db) ( note 22 ) 21.768 khz (-0.02db) 24.00 khz (-6.0db) stop band sb 26.5 khz pass band ripple ( note 22 ) pr 0.005 db stop band attenuation ( note 23 , note 24 ) sa 80 db group delay distortion 0 gd s group delay (ts=1/fs) gd 29 ts digital filter + sfc amplitude characteristics (20hz~20.0khz) 0.01 db note 21. each parameter is related to the samp ling frequency (fs). hpf response is not included. note 22. the pass band is from dc to 21.5khz at fs = 48khz. note 23. the stop band is from 26.5khz to 3.0455mhz at fs = 48khz. note 24. when fs = 48khz, the analog modulator samples the analog input at 3.072mhz. the input signal is not attenuated by the digital filter in multiple bands (n x 3.072mhz 21.99khz; n=0, 1, 2, 3...) of the sampling frequency. 2) adc section adcm (ta=-40 c~85 c; avdd = dvdd =3.0v~3.6v; dvdd18=1.7v~2.0v; fs = 48 khz; note 25 ) parameter symbol min typ max unit pb 0 21.5 khz pass band ( 0.005db) ( note 26 ) 21.768 khz (-0.02db) 24.00 khz (-6.0db) stop band sb 26.5 khz pass band ripple ( note 26 ) pr 0.005 db stop band attenuation ( note 27 , note 28 ) sa 80 db group delay distortion 0 gd s group delay (ts=1/fs) ( note 29 ) gd 29 ts digital filter + sfc amplitude characteristics (20hz~20.0khz) 0.1 db note 25. each parameter is related to the samp ling frequency (fs). hpf response is not included. note 26. the pass band is from dc to 21.5khz at fs = 48khz. note 27. the stop band is from 26.5khz to 3.0455mhz at fs = 48khz. note 28. when fs = 48khz, the analog modulator samples the analog input at 3.072mhz. the input signal is not attenuated by the digital filter in th e multiple bands (n x 3.072mhz 21.99khz; n=0, 1, 2, 3...) of the sampling frequency. note 29. vol+ mux path adds one additional ts. ms0581-e-00-pb 2007/09 - 15 -
[ak7780] 3) src (ta=-40 c~85 c; avdd=dvdd=3.0~3.6v; dvdd18 = 1.7~2.0v) parameter range symbol min typ max unit pass band -0.01db pb 0 0.4583fsi khz 0.980 fso/fsi 6.000 pb 0 0.4167fsi khz 0.900 fso/fsi < 0.990 pb 0 0.2182fsi khz 0.533 fso/fsi < 0.909 pb 0 0.2177fsi khz 0.490 fso/fsi < 0.539 pb 0 0.1948fsi khz 0.450 fso/fsi < 0.495 stop band sb 0.5417fsi khz 0.980 fso/fsi 6.000 sb 0.5021fsi khz 0.900 fso/fsi < 0.990 sb 0.2974fsi khz 0.533 fso/fsi < 0.909 sb 0.2812fsi khz 0.490 fso/fsi < 0.539 sb 0.2604fsi khz 0.450 fso/fsi < 0.495 pass band ripple pr db 0.01 stop band attenuation sa 95.2 db group delay (ts=1/fs) gd 56 ts note 30 ) ( note 30. measured from the rising edge of src_lrck on the input to the rising edge of lrclk_o on the output, with there is no phase difference between input and output. ms0581-e-00-pb 2007/09 - 16 -
[ak7780] (5) switching characteristics [ #h means hexadecimal code. (#=0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f)] 1) system clock (ta = -40~85 c; avdd=dvdd=3.0v~3.6v; dvdd18 = 1.7v~2.0v) parameter symbol min typ max unit xti ckm[2:0] 0h,1h,2h,3h a) with a crystal oscillator: ckm[2:0]=0h,2h fxti - 11.2896 - mhz 12.288 ckm[2:0]=1h,3h fxti - 16.9344 - mhz 18.432 b) with an external clock duty cycle 40 50 60 % ckm[2:0]=0h,2h fxti 11.0 12.4 mhz ckm[2:0]=1h,3h fxti 16.5 18.6 mhz clock rise time tcr 6 ns clock fall time tcf 6 ns lrclk_i frequency ( fs 7.35 48 96 khz note 31 ) clock rise time tlr 6 ns clock fall time tlf 6 ns bitclk_i frequency high level width tbclkh 64 ns low level width tbclkl 64 ns clock rise time tbr 6 ns clock fall time tbf 6 ns a) ckm[2:0]=2h,3h fbclk - 64 - fs duty cycle 40 50 60 % ckm[2:0]=2h,3h 0.23 6.2 mhz b) ckm[2:0]=4h,5h ( - 64 - fs note 32 ) fbclk duty cycle 40 50 60 % ckm[2:0]=4h fbclk 2.75 3.1 mhz ckm[2:0]=5h fbclk 5.5 6.2 mhz note 31. lrclk and sampling rate (fs) should match. note 32. when bitclk_i uses as a resource of master cl ock, it should be 64 clocks correctly divided within 1fs. ms0581-e-00-pb 2007/09 - 17 -
[ak7780] (ta = -40 c ~85 c; avdd=dvdd=3.0~3.6v, dvdd18 = 1.7~2.0v) parameter symbol min typ max unit src_lrck frequency ( fs 7.35 48 96 khz note 33 ) clock rise time tlr 6 ns clock fall time tlf 6 ns src_bick frequency high level width tbclkh 60 ns low level width tbclkl 60 ns clock rise time tbr 6 ns clock fall time tbf 6 ns ( note 34 ) fbclk 32 128 fs duty factor 40 50 60 % 0.23 6.2 mhz note 33. src_lrck and sampling rate (fs) should match. note 34. 128fs is up to fs = 48khz. 2) reset (ta=-40 c ~85 c; avdd=dvdd=3.0~3.6v; dvdd18 = 1.7~2.0v) parameter symbol min typ max unit trst 600 ns init_reset ( note 35 ) trst 600 ns p_ckrst trst 600 ns p_adrst trst 600 ns p_dsprst trst 600 ns p_srcrst note 35. ?l? is acceptable when power is turned on, but a stable master clock mu st present before transitioning to ?h?. ms0581-e-00-pb 2007/09 - 18 -
[ak7780] 3) audio interface 3-1) sdin1~sdin5,sdout1~sdout 6,sdouta1 (up to fs = 96khz) akm normal and i 2 s compatible format (ta = -40 c~85 c; avdd=dvdd=3.0~3.6v, dvdd18 = 1.7~2.0v, cl=20pf) parameter symbol min typ max unit slave mode ckm[2:0]=2h, 3h, 4h, 5h tblrd 20 ns delay time from bitclk_i ? ? to lrclk_i ( note 36 ) tlrbd 20 ns delay time from lrclk_ i to bitclk_i ? ? ( note 36 ) delay time from lrclk_i, lrclk_o to serial data output tlrd 40 ns delay time from bitclk_i, bitclk_o to serial data output tbsod 40 ns serial data input latch setup time tbsids 40 ns serial data input latch hold time tbsidh 40 ns master mode ckm[2:0]=0h, 1h bitclk_o frequency fbclk 64 fs bitclk_o duty cycle 50 % tblrd -20 40 ns delay time from bitclk_o ? ? to lrclk_o delay time from lrclk_o to serial data output tlrd 40 ns delay time from bitclk_o to serial data output tbsod 40 ns serial data input latch setup time tbsids 40 ns serial data input latch hold time tbsidh 40 ns note 36. lrclk_i edge and bitclk_i " ?edge cannot be synchronous. 3-2) sdin1(srci input) (up to fs = 96khz) (ta=-40 c~85 c; avdd=dvdd=3.0~3.6v, dvdd18 = 1.7~2.0v) parameter symbol min typ max unit slave mode tblrd 20 ns delay time from src_bick ? ? to src_lrck ( note 37 ) tlrbd 20 ns delay time from src_lrck to src_bick ? ? ( note 37 ) serial data input latch setup time tbsids 40 ns serial data input latch hold time tbsid h 40 ns note 37. src_bick edge and src_ lrck edge cannot be synchronous. ms0581-e-00-pb 2007/09 - 19 -
[ak7780] 3) microcontroller interface (ta = -40~85 c; avdd=dvdd=3.0v~3.6v, dvdd18 = 1.7~2.0v, cl = 20pf) parameter symbol min typ max unit microcomputer interface signal rq fall time twrf 30 ns rq rise time twrr 30 ns sclk fall time tsf 30 ns sclk rise time tsr 30 ns sclk frequency fsclk 2.1 mhz sclk low level width tsclkl 200 ns sclk high level width tsclkh 200 ns microcomputer to ak7780 ak7780 to microcomputer time from rq ? ? to so hi-z (iout= 360 a) release trqhr 600 ns rq ? ? to so hi-z set (iout= 360 a) trqhs 600 ns note 38. except last 1bit of the command code. time from p_dsprst , p_adrst ? ? to rq ? ? trew 500 ns time from rq ? ? to p_dsprst , p_adrst ? ? twre 500 ns rq high level width twrqh 500 ns time from rq ? ? to sclk? ? twsc 500 ns time from sclk? ? to rq ? ? tscw 800 ns si latch setup time tsis 200 ns si latch hold time tsih 200 ns tsos 300 ns delay time from sclk? ? to so output tsoh 200 ns hold time from sclk? ? to so output ( note 38 ) ms0581-e-00-pb 2007/09 - 20 -
[ak7780] 4) i2c bus interface (ta = -40 c~85 c; avdd=dvdd=3.0~3.6v, dvdd18 = 1.7~2.0v) parameter symbol min typ max unit i 2 c timing scl clock frequency fscl 400 khz bus free time between transmissions tbuf 1.3 s start condition hold time (prior to first clock pulse) thd:sta 0.6 s clock low time tlow 1.3 s clock high time thigh 0.6 s setup time for repeated start condition tsu:sta 0.6 s sda hold time from scl falling thd:dat 0 0.9 s sda setup time from scl rising tsu:dat 0.1 s rise time of both sda and scl lines tr 0.3 s fall time of both sda and scl lines tf 0.3 s setup time for stop condition tsu:sto 0.6 s pulse width of spike noise suppressed by input filter tsp 0 50 ns capacitive load on bus cb 400 pf note 39. i 2 c is a registered trademark of philips semiconductors. ms0581-e-00-pb 2007/09 - 21 -
[ak7780] (6) timing diagram 1) system clock 1/fxti tcf tcr 2) reset 1/fxti vih vil xti txti=1/fxti tlf tlr 1/fs vih vil lrclk_i src_lrck ts=1/fs tbf tbr tbclkl tbclkh 1/fbclk 1/fbclk tbclk=1/fbclk vih vil bitclk_i src_bick trst nit_reset p_adrst vil p_ckrst p _ dsprst p_srcrst ms0581-e-00-pb 2007/09 - 22 -
[ak7780] 3) audio interface c normal and i 2 s compatible format d src tbsidh tbsids tbsod tlrd tblrd tlrbd 50%dvdd 50%dvdd 50%dvdd 50%dvdd lrclk i bitclk_i sdout * sdin * sdin * =sdin1, sdin2, sdin3, sdin4, sdin5 lrclk _ o bitclk_o tmb tmbl tbsidh tbsids sdout * =sdout1, sdout2, sdout3, sdout4, sdout5, sdout6, sdouta1 tblrd tlrbd 50%dvdd 50%dvdd 50%dvdd src_lrck src_bick srci=sdin1 ms0581-e-00-pb 2007/09 - 23 -
[ak7780] 4) microcontroller interface ? microcontroller interface vih vil rq twrf twrr tsf tsr ? microcontrollerr ? ak7780 twre p_adrst rq vil twr q h trew tsis tsih si vih vil vih twsc sclk tscw tscw twsc tscw vil vih vil p_dsprst sclk tsclkh tsclkl vih vil 1/fsclk 1/fsclk ms0581-e-00-pb 2007/09 - 24 -
[ak7780] ? ak7780 ? microcontroller sclk vil vih tsos tsoh so vih vil note: timing during the run state is identical, except that p_dsprst and p_adrst are ?h?. 5) i 2 c bus interface vih vil tr q hr tr q hs rq so hi-z thigh scl sda vih tlow tbuf thd:sta tr tf thd:dat tsu:dat tsu:sta stop start start stop tsu:sto vil vih vil tsp ms0581-e-00-pb 2007/09 - 25 -
[ak7780] package ? 100 pin lqfp (unit: mm ) 16.0 0.3 ? 14.0 50 51 75 76 100 1 25 26 0.22 0.05 0.10 m 0.5 16.0 0.3 1.0 0.10 0.5 0.2 0 ~10 1.70 max. 0.20max 0.17 0.05 material & lead finish package: epoxy lead-frame: cu lead-finish: solder (pb free) plate ms0581-e-00-pb 2007/09 - 26 -
[ak7780] marking ak7780vt x xxxxxx akm 1) pin #1 indication 2) date code: xxxxxxx(7digits) 3) marking code: ak7780vt 4) asahi kasei logo important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification. ms0581-e-00-pb 2007/09 - 27 -
[ak7780] thank you for your access to akemd product informations. more detail product informations are available, please contact our sales office or authorized distributors. ms0581-e-00-pb 2007/09 - 28 -

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