 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| integrated circuit systems, inc. ics94201 94201 rev - 10/03/00 pin configuration recommended application: ? 2 - cpus @ 2.5v 13 - sdram @ 3.3v 3 - 3v66 @ 3.3v 8 - pci @3.3v 1 - 24/48mhz@ 3.3v 1 - 48mhz @ 3.3v fixed 1 - ref @3.3v, 14.318mhz features: programmable ouput frequency. programmable ouput rise/fall time for pci and sdram clocks. programmable 3v66 to pci skew. spread spectrum for emi control with programmable spread percentage. watchdog timer technology to reset system if over-clocking causes malfunction. support power management through pd#. uses external 14.318mhz crystal. fs pins for frequency select key specifications: cpu output jitter: <250ps ioapic output jitter: <500ps 48mhz, 3v66, pci output jitter: <500ps ref output jitter. <1000ps cpu output skew: <175ps pci output skew: <500ps 3v66 output skew <175ps for group skew timing, please refer to the group timing relationship table. programmable system frequency generator for p ii / iii ? 56-pin 300 mil ssop ! "# $# %&& # pll2 pll1 spread spectrum 48mhz 24_48mhz cpuclk [1:0] 2 12 8 3 sdram [11:0] ioapic pciclk [7:0] sdram_f 3v66 [2:0] x1 x2 xtal osc cpu divder sdram divder ioapic divder pci divder 3v66 divder fs[4:0] pd# sel24_48# s data sclk control logic config. reg. / 2 ref0 block diagram vddref x1 x2 gndref gnd3v66 3v66-1 3v66-2 vdd3v66 vddpci *(fs0)pciclk0 *(fs1)pciclk1 *(sel24_48#)pciclk2 gndpci pciclk3 pciclk4 pciclk5 vddpci pciclk6 pciclk7 gndpci pd# sclk s data vddsdr sdram11 sdram10 gndsdr 3v66-0 1 1 1 ref0(fs4)* vddlapic ioapic vddlcpu cpuclk0 cpuclk1 gndlcpu gndsdr sdram0 sdram1 sdram2 vddsdr sdram3 sdram4 sdram5 gndsdr sdram6 sdram7 sdram_f vddsdr gnd48 24_48mhz(fs2)* 48mhz(fs3)* vdd48 vddsdr sdram8 sdram9 gndsdr 1 1 ics94201 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice. preliminary product preview ics94201 preliminary product preview general description pin configuration ' # ( ' # ) ' ( #" * )+ ( ""* " ' )" "" ) + ( ( ##(# , ##( -#, ( # ## , ( # ## ## ', #" " #, # * # ' )+ ./ " . ( -# ( ("* "#* ( " ' #" #"0)*1 2 2" (0)-# ( # * ! " ! # $ % & ! # ' # ( ) ' # ( ' * + " ' ( , - . ! # ' # ( / 0 / 1 # ( + # ' ' ' * $ % & 2 3 " # ( ! # 3 2 4 5 6 2 2 , - .7 - / " ' ' 0 / 1 2 2 ! 8 ( % 9 : * * , - .; 9 : * - * # ) # ; ) ' ( ' ' * ; % # ' ! ) ' ' # ' ( ' # < " ' # ( ( = : 9 : * * , - .; 9 : * - * # ) # ; ) ' ( ' ' * ; % # ' ! ) ' ' # ' ( ' # < " ' # ( ( = : # 8 4 _ 4 2 _ l e sn i. t u p t u o t c e l e s o t t u p n i c i g o l 9 : * * , - .; 9 : * - * # ) # ; ) ' ( ' ' * 2 4 5 6 9 : * * , - .; 9 : * - * # ) # ; ) ' ( ' ' * > ' # ( ( ? ! ) ' # ! ' ! # ( ' # ( ? ( ' # ) # @ ) ' ! # . * ) ' ! # ! ( ! # ' # ( ) , ' ' ' = ' # ( # ! ) ' " # ' ) , ! ' ' + # ) ' 9 : * ; " ' # ( * ' # ( * @ , @ ;, - . " ' # ( ' ' # ( ( * ; % # ' ! ) ' ' # ' ( ' # < " ' # ( ( = : 0 / 1 , - .7 ; - " ' ' 0 / 1 ! 8 ( % ; % # ' ! ) ' ' # ' ( ' # < " ' # ( ( = : 0 / 1 a , - . 0 / 1 ( ' " ! # ( ) = ) ' ' ' ' 0 / 1 a % a 1 @ ;, - . ) = ) ' " " ! # ' # ' ' 1 @ ; * 2 4 5 6 1 @ ;, - . ) = ) ' " " ! # ' # ' ' 1 @ ; @ ' ' * : 3 * @ b - * " " ! # 3 4 5 6 9 : * - *, - . # ( ; % + " ! ? ( ! # < " ' ' . ' ' ' / : * @ . - * " * @ . , - . 0 / 1 2 2 ' = # ( # # ' ' 2 ; % # ' ! ) ' ' # ' ( ' # < " ' # ( ( = : % c , - . ' ' # " 0 / 1 ics94201 preliminary product preview general i 2 c serial interface information for the ics94201 how to write: how to read: controller (host) ics (slave/receiver) start bit address d2 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack byte 26 ack byte 27 ack byte 28 ack stop bit how to write: controller (host) ics (slave/receiver) start bit address d3 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack if 7 h has been written to b6 byte 7 ack if 1a h has been written to b6 byte26 ack if 1b h has been written to b6 byte 27 ack if 1c h has been written to b6 byte 28 ack stop bit how to read: ics94201 preliminary product preview )+ ' ,) + " ) *' ( ( 3 *' # 024 ! "# $ !%&'"%( )%' # )(( 5" , *6 *# , *6 7 ( # * ' !* " 6 # 77% *( "** 8 " ( ' ) + (, # 2 '$/ ( " *"# * -# ( " ** ( " ** ( + "" 2 # * "#*,*# ( * # -## 1 9 $ , (# , register name byte description pwd default functionality & frequency select register 0 output frequency, hardware / i 2 c frequency select, spread spectrum & output enable control register. see individual byte description output control registers 1-5 active / inactive output control registers. see individual byte description byte count read back register 6 w ritin g to this re g ister will confi g ure b y te count and how man y b y te will be read back. do not write 00 h to this byte. 06 h latched inputs read back register 7 the inverse of the latched inputs level could be read back from this register. see individual byte description w atchdog control registers 8 bit[6:0] w atchdog enable, watchdog status and programmable ?safe? frequency? can be configured in this register. 000,0000 vco control selection bit 8 bit[7] this bit select whether the output frequency is control by hardware/byte 0 configurations or byte 14&15 programming. 0 w atchdog timer count register 9 w riting to this register will configure the number of seconds for the watchdog timer to reset. ff h ics reserved register 10 this is an unused register. w riting to this register will not affect device functionality. 00 h device id, vendor id & revision id registers 11-12 byte 11 bit[3:0] is ics vendor id - 0001. other bits in these 2 registers designate device revision id of this part. see individual byte description ics reserved register 13 don?t write into this register, writing 1?s will cause malfunction. 00 h vco frequency control registers 14-15 these registers control the dividers ratio into the phase detector and thus control the vco output frequency. depended on hardware/byte 0 configuration spread spectrum control registers 16-17 these registers control the spread percentage amount. depended on hardware/byte 0 configuration output dividers control registers 18-20 changing bits in these registers result in frequency divider ratio changes. incorrect configuration of group output divider ratio can cause system malfunction. depended on hardware/byte 0 configuration group skews control registers 21-23 increment or decrement the group skew amount as compared to the initial skew. see individual byte description output rise/fall time select registers 24 these register will control the group rise and fall time. see individual byte description brief i 2 c registers description for ics94201 programmable system frequency generator ics94201 preliminary product preview * + , + ! -.+/0 1 t i b n o i t p i r c s e d d w p t i b ) 4 : 7 , 2 ( 2 t i b7 t i b6 t i b5 t i b4 t i b f e r / o c v r e d i v i d o c v z h m / o c v u p c k l c u p c z h m m a r d s z h m 6 6 v 3 z h m k l c i c p z h m c i p a o i z h m 1 e t o n 4 s f3 s f2 s f1 s f0 s f 00000 8 1 / 1 0 52 5 . 8 9 363 4 . 6 65 6 . 9 93 4 . 6 61 2 . 3 31 6 . 6 1 00001 4 1 / 2 5 30 0 . 0 6 360 0 . 0 60 0 . 0 90 0 . 0 60 0 . 0 30 0 . 5 1 00010 8 1 / 4 0 51 9 . 0 0 460 8 . 6 60 2 . 0 0 10 8 . 6 60 4 . 3 30 7 . 6 1 00011 1 1 / 5 1 32 0 . 0 1 463 3 . 8 60 5 . 2 0 13 3 . 8 67 1 . 4 38 0 . 7 1 00100 5 1 / 0 4 40 0 . 0 2 460 0 . 0 70 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1 00101 4 1 / 0 4 40 0 . 0 5 460 0 . 5 70 5 . 2 1 10 0 . 5 70 5 . 7 35 7 . 8 1 00110 5 1 / 3 0 54 1 . 0 8 460 0 . 0 80 0 . 0 2 10 0 . 0 80 0 . 0 40 0 . 0 2 00111 9 / 3 1 35 9 . 7 9 460 0 . 3 80 5 . 4 2 10 0 . 3 80 5 . 1 45 7 . 0 2 01000 7 3 / 5 1 59 2 . 9 9 125 6 . 9 95 6 . 9 93 4 . 6 61 2 . 3 31 6 . 6 1 01001 5 3 / 0 4 49 2 . 0 8 120 0 . 0 90 0 . 0 90 0 . 0 60 0 . 0 30 0 . 5 1 01010 7 3 / 8 1 55 4 . 0 0 22 3 2 . 0 0 13 2 . 0 0 14 8 . 6 61 4 . 3 30 7 . 6 1 01011 1 3 / 6 4 40 0 . 6 0 22 0 0 . 3 0 10 0 . 3 0 17 6 . 8 63 3 . 4 37 1 . 7 1 01100 3 3 / 4 8 40 0 . 0 1 22 0 0 . 5 0 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1 01101 3 3 / 7 0 58 9 . 9 1 22 0 0 . 0 1 10 0 . 0 1 13 3 . 3 77 6 . 6 33 3 . 8 1 01110 2 3 / 4 1 59 9 . 9 2 22 0 0 . 5 1 10 0 . 5 1 17 6 . 6 73 3 . 8 37 1 . 9 1 01111 6 1 / 7 4 41 0 . 0 0 42 0 0 . 0 0 20 0 . 0 0 23 3 . 3 3 16 6 . 6 63 3 . 3 3 10000 8 1 / 1 0 52 5 . 8 9 33 6 8 . 2 3 16 8 . 2 3 13 4 . 6 61 2 . 3 31 6 . 6 1 1000 1 3 1 / 4 5 43 0 . 0 0 53 7 6 . 6 6 17 6 . 6 6 14 3 . 3 87 6 . 1 43 8 . 0 2 100 10 8 1 / 4 0 51 9 . 0 0 43 4 6 . 3 3 14 6 . 3 3 12 8 . 6 61 4 . 3 30 7 . 6 1 100 11 7 1 / 8 8 42 0 . 1 1 43 0 0 . 7 3 10 0 . 7 3 10 5 . 8 65 2 . 4 33 1 . 7 1 10 100 5 1 / 0 4 40 0 . 0 2 43 0 0 . 0 4 10 0 . 0 4 10 0 . 0 70 0 . 5 30 5 . 7 1 10 10 1 3 1 / 5 9 35 0 . 5 3 43 0 0 . 5 4 10 0 . 5 4 10 5 . 2 75 2 . 6 33 1 . 8 1 10 110 4 1 / 0 4 40 0 . 0 5 43 0 0 . 0 5 10 0 . 0 5 10 0 . 5 70 5 . 7 35 7 . 8 1 10 111 5 1 / 3 0 54 1 . 0 8 43 0 0 . 0 6 10 0 . 0 6 10 0 . 0 80 0 . 0 40 0 . 0 2 11000 8 1 / 1 0 52 5 . 8 9 33 6 8 . 2 3 15 6 . 9 93 9 . 6 61 2 . 3 31 6 . 6 1 11001 3 1 / 4 5 43 0 . 0 0 53 7 6 . 6 6 10 0 . 5 2 14 3 . 3 87 6 . 1 43 8 . 0 2 11010 8 1 / 4 0 51 9 . 0 0 43 4 6 . 3 3 13 2 . 0 0 12 8 . 6 61 4 . 3 37 . 6 1 11011 7 1 / 8 8 42 0 . 1 1 43 0 0 . 7 3 15 7 . 2 0 10 5 . 8 65 2 . 4 33 1 . 7 1 11100 5 1 / 0 4 40 0 . 0 2 43 0 0 . 0 4 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 1 11101 3 1 / 5 9 35 0 . 5 3 43 0 0 . 5 4 15 7 . 8 0 10 5 . 2 75 2 . 6 33 1 . 8 1 11110 4 1 / 0 4 40 0 . 0 5 43 0 0 . 0 5 10 5 . 2 1 10 0 . 5 70 5 . 7 35 7 . 8 1 11111 5 1 / 3 0 54 1 . 0 8 43 0 0 . 0 6 10 0 . 0 2 10 0 . 0 80 0 . 0 40 0 . 0 2 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d a e r p s r e t n e c % 5 3 . 0 e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0 ics94201 preliminary product preview * +2! -/+'/ +0 1 )" ## :;/ * ( " ## * ( # $ 5 * ( # # " " ( -/+'/ +0 * +2! -/+'/ +0 * +2! -/+'/ +0 *& +2! -/+'/ +0 *" * 2 * 2! t i b# n i pd w pn o i t p i r c s e d 7 t i b9 31 7 m a r d s 6 t i b0 41 6 m a r d s 5 t i b2 41 5 m a r d s 4 t i b3 41 4 m a r d s 3 t i b4 41 3 m a r d s 2 t i b6 41 2 m a r d s 1 t i b7 41 1 m a r d s 0 t i b8 41 0 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b81 2 _ 6 6 v 3 6 t i b61 0 _ 6 6 v 3 5 t i b71 1 _ 6 6 v 3 4 t i b-x# 4 s f 3 t i b4 51 c i p a o i 2 t i b-x# 1 s f 1 t i b1 51 1 k l c u p c 0 t i b2 51 0 k l c u p c t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) e t o n ( d e v r e s e r 6 t i b-0 ) e t o n ( d e v r e s e r 5 t i b-0 ) e t o n ( d e v r e s e r 4 t i b-0 ) e t o n ( d e v r e s e r 3 t i b-0 ) e t o n ( d e v r e s e r 2 t i b-1 ) e t o n ( d e v r e s e r 1 t i b-1 ) e t o n ( d e v r e s e r 0 t i b-0 ) e t o n ( d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 ) d e v r e s e r ( 6 t i b-1 ) d e v r e s e r ( 5 t i b-1 ) d e v r e s e r ( 4 t i b-1 ) d e v r e s e r ( 3 t i b6 21 1 1 m a r d s 2 t i b7 21 0 1 m a r d s 1 t i b0 31 9 m a r d s 0 t i b1 31 8 m a r d s t i b# n i pd w pn o i t p i r c s e d 7 t i b0 21 7 k l c i c p 6 t i b9 11 6 k l c i c p 5 t i b7 11 5 k l c i c p 4 t i b6 11 4 k l c i c p 3 t i b5 11 3 k l c i c p 2 t i b3 11 2 k l c i c p 1 t i b2 11 1 k l c i c p 0 t i b1 11 0 k l c i c p t i b# n i pd w pn o i t p i r c s e d 7 t i b-x# 3 s f 6 t i b-x# 0 s f 5 t i b-x# 2 s f 4 t i b5 31 z h m 4 2 3 t i b-1 ) d e v r e s e r ( 2 t i b4 31 z h m 8 4 1 t i b-1 ) d e v r e s e r ( 0 t i b8 31 f _ m a r d s ics94201 preliminary product preview *( 4 2 2! * $ ! 2! *) 5 ++ * 6 $ ! +2! * 2 7 2! * 5 .6.7 .2! * 27 .2! !" # $ % & ' # () * (% + + & 1 , (% ics94201 preliminary product preview *3 2 7 2! *& 5 , +2! > ? " (@* 2* a1?bc26*a1bd-# %+; # e 5" (%+; # (78 ,# "78$= ," ,, ** c*6*1 %-.' .+. * 5 , +2! ' # / 0$+! "123 & ,4 ! ! "# $ % # # & #' %( # )*+,-.+ /00+) !$ #' 1 !!!&$ &!!& &2 0 # # 3 !(4 , &0(4 % 4 ,(5 ' 3 1 6&6 7 8 &4 &3 /9 #' 0 1 &4 : &3 /9 : ,;< % % 8 1 &0 4 % # = % > 7 = % /9 # & # /9 #' $ &4 &3 " # # vco frequency ...................... 150mhz to 500mhz vco divider range ................ 8 to 519 ref divider range ................. 2 to 129 phase detector stability .......... 0.3536 to 1.4142 $# % /9 <' ? &4 &7&7 > /9@,;< % % ) ? &4! 7 > /9 % % t i bd w pn o i t p i r c s e d 7 t i bx 8 t i b r e d i v i d o c v 6 t i bx 7 t i b r e d i v i d o c v 5 t i bx 6 t i b r e d i v i d o c v 4 t i bx 5 t i b r e d i v i d o c v 3 t i bx 4 t i b r e d i v i d o c v 2 t i bx 3 t i b r e d i v i d o c v 1 t i bx 2 t i b r e d i v i d o c v 0 t i bx 1 t i b r e d i v i d o c v t i bd w pn o i t p i r c s e d 7 t i b0 ) d e v r e s e r ( 6 t i b0 ) d e v r e s e r ( 5 t i b0 ) d e v r e s e r ( 4 t i b0 t c e l e s e s a b r e m i t 0 w s m 0 8 5 = 0 s m 2 = 1 3 t i b0 ) d e v r e s e r ( 2 t i b0 ) d e v r e s e r ( 1 t i b0 ) d e v r e s e r ( 0 t i b0 ) d e v r e s e r ( t i bd w pn o i t p i r c s e d 7 t i bx 0 t i b r e d i v i d o c v 6 t i bx 6 t i b r e d i v i d f e r 5 t i bx 5 t i b r e d i v i d f e r 4 t i bx 4 t i b r e d i v i d f e r 3 t i bx 3 t i b r e d i v i d f e r 2 t i bx 2 t i b r e d i v i d f e r 1 t i bx 1 t i b r e d i v i d f e r 0 t i bx 0 t i b r e d i v i d f e r & ics94201 preliminary product preview *" +2! *( +2! 5 6 # () 7## 4 # # ( ## 5 6 # () 7## 4 # # ( ## *) . 7 +2! * . 7 +2! 1 a?6b ))+ 2*a?1b 2# *' $ # ( %+;( -# ( ( t i bd w pn o i t p i r c s e d 7 t i bx 7 t i b l o r t n o c x u m r e d i v i d t u p t u o 6 t i bx 6 t i b l o r t n o c x u m r e d i v i d t u p t u o 5 t i bx 5 t i b l o r t n o c x u m r e d i v i d t u p t u o 4 t i bx 4 t i b l o r t n o c x u m r e d i v i d t u p t u o 3 t i bx 3 t i b l o r t n o c x u m r e d i v i d t u p t u o 2 t i bx 2 t i b l o r t n o c x u m r e d i v i d t u p t u o 1 t i bx 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 0 t i bx 0 t i b l o r t n o c x u m r e d i v i d t u p t u o t i bd w pn o i t p i r c s e d 7 t i bx 5 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 6 t i bx 4 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 5 t i bx 3 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 4 t i bx 2 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 3 t i bx 1 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 2 t i bx 0 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 1 t i bx 9 t i b l o r t n o c x u m r e d i v i d t u p t u o 0 t i bx 8 t i b l o r t n o c x u m r e d i v i d t u p t u o t i bd w pn o i t p i r c s e d 7 t i bx 7 t i b m u r t c e p s d a e r p s 6 t i bx 6 t i b m u r t c e p s d a e r p s 5 t i bx 5 t i b m u r t c e p s d a e r p s 4 t i bx 4 t i b m u r t c e p s d a e r p s 3 t i bx 3 t i b m u r t c e p s d a e r p s 2 t i bx 2 t i b m u r t c e p s d a e r p s 1 t i bx 1 t i b m u r t c e p s d a e r p s 0 t i bx 0 t i b m u r t c e p s d a e r p s t i bd w pn o i t p i r c s e d 7 t i bx 6 2 t i b l o r t n o c r e d i v i d 6 t i b0 5 2 t i b l o r t n o c r e d i v i d 5 t i bx 4 2 t i b l o r t n o c r e d i v i d 4 t i bx 2 1 t i b m u r t c e p s d a e r p s 3 t i bx 1 1 t i b m u r t c e p s d a e r p s 2 t i bx 0 1 t i b m u r t c e p s d a e r p s 1 t i bx 9 t i b m u r t c e p s d a e r p s 0 t i bx 8 t i b m u r t c e p s d a e r p s ' ( & * : 8 @ % &0(! : 8 # /9$ ,;< % % # $ % # # < > /9 #' % )aa # /9 #' # * &4 &7&7.b5 > /9@,;< % % /9 #' .b5 4 * 5 # % /9 #' # - ; 3 /9 #' $ #' - # # )* ics94201 preliminary product preview * 2 7 2! *3 8 +2! * 8 +2! %8*5)( 39 /!":+ + 4 !/ + # 5)( 1 9++ + 2! ' # * . 7 +2! 1 a?6b ) + 2*a?1b 2# *' $ # ( %+;( -# ( ( 7 )( 2 * 1 ff " "" ,2 $ 6 (# # # %8*(-75() 39 8 ": +++ 4 !/ + # (-75() t i bd w pn o i t p i r c s e d 7 t i bx 3 2 t i b l o r t n o c x u m r e d i v i d t u p t u o 6 t i bx 2 2 t i b l o r t n o c x u m r e d i v i d t u p t u o 5 t i bx 1 2 t i b l o r t n o c x u m r e d i v i d t u p t u o 4 t i bx 0 2 t i b l o r t n o c x u m r e d i v i d t u p t u o 3 t i bx 9 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 2 t i bx 8 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 1 t i bx 7 1 t i b l o r t n o c x u m r e d i v i d t u p t u o 0 t i bx 6 1 t i b l o r t n o c x u m r e d i v i d t u p t u o t i bd w pn o i t p i r c s e d 7 t i b $ ! ? & 6 t i b $ ! ? & 5 t i b $ ! ? & 4 t i b $ ! ? & 3 t i b $ ! ? & 2 t i b $ ! ? & 1 t i b $ ! ? & 0 t i b $ ! ? & t i bd w pn o i t p i r c s e d 7 t i b1 3 t i b w e k s i c p o t 6 6 v 3 6 t i b0 2 t i b w e k s i c p o t 6 6 v 3 5 t i b0 1 t i b w e k s i c p o t 6 6 v 3 4 t i b1 0 t i b w e k s i c p o t 6 6 v 3 3 t i b0 ) d e v r e s e r ( 2 t i b0 ) d e v r e s e r ( 1 t i b0 ) d e v r e s e r ( 0 t i b0 ) d e v r e s e r ( t i bd w pn o i t p i r c s e d 7 t i b0 ) d e v r e s e r ( 6 t i b0 k a e w = 1 , l a m r o n = 0 f e r 5 t i b0 k a e w = 1 , l a m r o n = 0 z h m 8 4 , 4 2 4 t i b0 ) d e v r e s e r ( 3 t i b0 k a e w = 1 , l a m r o n = 0 i c p 2 t i b0 k a e w = 1 , l a m r o n = 0 6 6 v 3 1 t i b0 k a e w = 1 , l a m r o n = 0 m a r d s 0 t i b0 ) d e v r e s e r ( t i bd w pn o i t p i r c s e d 7 t i b 0) d e v r e s e r ( 6 t i b 0) d e v r e s e r ( 5 t i b 0) d e v r e s e r ( 4 t i b 0) d e v r e s e r ( 3 t i b 03 t i b w e k s c i p a o i o t 6 6 v 3 2 t i b 12 t i b w e k s c i p a o i o t 6 6 v 3 1 t i b 11 t i b w e k s c i p a o i o t 6 6 v 3 0 t i b 10 t i b w e k s c i p a o i o t 6 6 v 3 )) ics94201 preliminary product preview absolute maximum ratings * # "# " " ( (# ( * ( ( " 5 # * # "5"#" ( 5 " (( # * electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v + 5%, vddl=2.5 v+ 5%(unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 a operating i dd3 .3 op c l = 0 pf; select @ 66m 100 ma supply current power down i dd3 .3 pd c l = 0 pf; with input address to vdd or gnd 600 a supply current input frequency f i v dd = 3.3 v; 14.318 mhz pin inductance l p in 7nh input capacitance 1 c in logic inputs 5 pf c out out put pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms delay t pzh ,t pzh output enable delay (all outputs) 1 10 ns t plz ,t pzh output disable delay (all outputs) 1 10 ns 1 guarenteed by design, not 100% tested in production. + # % 68% ); # % 78% : )# g>&h% % d% 9"*; " # i+ d 1i+ " # h8i+ di+ +" # i+ p u o r gz h m 6 6 u p c z h m 0 0 1 m a r d s z h m 0 0 1 u p c z h m 0 0 1 m a r d s z h m 3 3 1 u p c z h m 0 0 1 m a r d s z h m 3 3 1 u p c z h m 3 3 1 m a r d s t e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o tt e s f f oe c n a r e l o t m a r d s o t u p cs n 5 . 2s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5s n 5 7 . 3s p 0 0 5 6 6 v 3 o t u p cs n 5 . 7s p 0 0 5s n 0 . 5s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5 6 6 v 3 o t m a r d ss n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 0 . 0s p 0 0 5s n 5 7 . 3s p 0 0 5 i c p o t 6 6 v 3s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5s n 5 . 3 - 5 . 1s p 0 0 5 i c p o t i c ps n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1s n 0 . 0s n 0 . 1 t o d & b s uh c n y s aa / nh c n y s aa / nh c n y s aa / nh c n y s aa / n ) ics94201 preliminary product preview electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.6 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.6 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 175 ps jitter t jcyc-cyc v t = 1.5 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - cpu t a = 0 - 70c, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp2b 1 v o = v dd *(0.5) 13.5 45 ? output impedance r dsn2 b 1 v o = v dd *(0.5) 13.5 45 ? output high voltage v oh2 b i oh = -1 ma 2 v output low voltage v ol2 b i ol = 1 ma 0.4 v output high current i oh2 b v oh @min = 1.0v , v oh@ max = 2.375v -27 -27 ma output low current i ol2 b v ol @min = 1.2v , v ol@ max = 0.3v 27 30 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f2b 1 v oh = 0.4 v, v ol = 2.0 v 0.4 1.6 ns duty cycle d t2b 1 v t = 1.25 v 455055ns skew t sk2b 1 v t = 1.25 v 175 ps t jcyc-cyc 1 v t = 1.25 v 250 ps jitter 1 guarenteed by design, not 100% tested in production. ) ics94201 preliminary product preview electrical characteristics - ioapic t a = 0 - 70c;v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o = v dd *(0.5) 9 30 ? output impedance r dsn4 b 1 v o = v dd *(0.5) 9 30 ? output high voltage v oh4 \ b i oh = -5.5 ma 2 v output low voltage v ol4 b i ol = 9.0 ma 0.4 v output high current i oh4 b v oh@ mi n = 1.4 v, v oh@ max = 2.5 v -36 -21 ma output low current i ol4 b v ol@ min = 1.0 v, v ol@ max= 0.2 36 31 ma rise time t r4b 1 v ol = 0.4 v, v oh = 2.0 v 0.4 1.6 ns fall time t f4b 1 v oh = 2.0 v, v ol = 0.4 v 0.4 1.6 ns duty cycle d t4b 1 v t = 1.25 v 45 55 % jitter t jcyc-cyc v t = 1.25 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - sdram t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 - 30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp3 1 v o = v dd *(0.5) 10 24 ? output impedance r dsn3 1 v o = v dd *(0.5) 10 24 ? output high voltage v oh3 i oh = -1 ma 2.4 v output low voltage v ol3 i ol = 1 ma 0.4 v output high current i oh3 v oh @min = 2.0 v, v oh@ max =3.135 v -54 -46 ma output low current i ol3 v ol@ min = 1.0 v, v ol@ max =0.4 v 54 53 ma rise time t r3 1 v ol = 0.4 v, v oh = 2.4 v 0.4 1.6 ns fall time t f3 1 v oh = 2.4 v, v ol = 0.4 v 0.4 1.6 ns duty cycle d t3 1 v t = 1.5 v 45 55 % skew t sk3 1 v t = 1.5 v 250 ps jitter t j cyc-cyc v t = 1.5 v 250 ps 1 guarenteed by design, not 100% tested in production. ) ics94201 preliminary product preview electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp1 1 v o = v dd *(0.5) 12 55 ? output impedance r dsn1 1 v o = v dd *(0.5) 12 55 ? output high voltage v oh1 i oh = -1 ma 2.4 v output low voltage v ol1 i ol = 1 ma 0.55 v output high current i oh1 voh@ min = 1.0 v, voh@ max = 3.135 v -33 -33 ma output low current i ol1 vol@ min = 1.95 v, vol@ max= 0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 2 ns duty cycle d t1 1 v t = 1.5 v 45 55 % skew t sk1 1 v t = 1.5 v 500 ps jitter t jcyc-cyc v t = 1.5 v 500 ps 1 guarenteed by design, not 100% tested in production. electrical characteristics - 48m, ref t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 -20 pf (unless otherwise stated) parameter symbol conditions min typ max units output impedance r dsp5 1 v o = v dd *(0.5) 20 60 ? output impedance r dsn5 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh5 i oh = 1 ma 2.4 v output low voltage v ol5 i ol = -1 ma 0.4 v output high current i oh5 v oh @min =1 v, v oh@max = 3.135 v -29 -23 ma output low current i ol5 v ol@min =1.95 v, v ol@min =0.4 v 29 27 ma rise time t r5 1 v ol = 0.4 v, v oh = 2.4 v 1.8 4 ns fall time t f5 1 v oh = 2.4 v, v ol = 0.4 v 1.7 4 ns duty cycle d t5 1 v t = 1.5 v 45 55 % jitter t jcyc-cyc 1 v t = 1.5 v; fixed clocks 500 ps t jcyc-cyc 1 v t = 1.5 v; ref clocks 1000 ps 1 guarenteed by design, not 100% tested in production. ) ics94201 preliminary product preview fig. 1 shared pin operation - input/output pins = @9 @ 24!& % # % ( $ = % % 3( - # )(9 $ - # % $ % # # # # ## > = # # $ / & c ! % - &! d &!d % .9 % ( % # ' via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k < & # # 1 e 1 e # $ = 5 % ) ics94201 preliminary product preview power down waveform # 9( <&j" : ( (+<4+:!, ## ' : 5k : < $# l7" 3# /( " ( 0km ) ics94201 preliminary product preview group offset waveforms cycle repeats 0ns cpu 66mhz cpu 100mhz cpu 133mhz sdram 133mhz sdram 100mhz 3.5v 66mhz pci 33mhz apic 33mhz ref 14.318mhz usb 48mhz 10ns 20ns 30ns 40ns ) ics94201 preliminary product preview product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and other specifications are subject to change without notice. ordering information ics94201 y f-t ! " #$% & ' : -5 27 . ! ' !( & ) () 7*: % 5" ? ics xxxx y f - ppp - t min max min max a 2.413 2.794 .095 .110 a1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c 0.127 0.254 .005 .010 d e 10.033 10.668 .395 .420 e1 7.391 7.595 .291 .299 e 0.635 basic 0.025 basic h 0.381 0.635 .015 .025 l 0.508 1.016 .020 .040 n 0 8 0 8 variations min max min max 56 18.288 18.542 .720 .730 jedec mo-118 doc# 10-0034 6/1/00 rev b n d mm. d (inch) see variations symbol see variations see variations in millimeters common dimensions in inches common dimensions see variations |
Price & Availability of ICS94201YFLF
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |