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gs73024ab 128k x 24 3mb asynchronous sram 8, 10, 12 ns 3.3 v v dd center v dd and v ss bga commercial temp industrial temp rev: 1.04b 3/2007 1/13 ? 2003, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? fast access time: 8, 10, 12 ns ? cmos low power operation: 250/200/170 ma at minimum cycle time ? single 3.3 v 0.3v power supply ? all inputs and outputs are ttl-compatible ? fully static operation ? industrial temperatur e option: ?40 to 85c ? package b: 14 mm x 22 mm, 119-bump, 1.27mm pitch bga gb: rohs-compliant 119-bump bga* description the gs73024a is a high speed cmos static ram organized as 131,072 words by 24 bits. stat ic design eliminates the need for external clocks or timing strobes. operating on a single 3.3 v power supply, and all inputs and outputs are ttl-compatible. the gs73024a is available in a 119-bump bga package. 119-bump ball grid array package pin descriptions symbol description symbol description a 0 to a 16 address input dq 1 to dq 24 data input/output we write enable input oe output enable input ce chip enable input v ss ground v dd +3.3 v power supply *all gsi technology packages are at least 5/6 rohs compliant. packages listed with the additional ?g ? designator are 6/6 rohs compliant.
we oe memory array row decoder column decoder address input control i/o buffer a 0 dq 1 dq 24 a 16 ce block diagram gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 2/13 ? 2003, gsi technology
1234567 anca 3 a 2 a 16 a 1 a 0 nc bnca 7 a 6 ce a 5 a 4 nc cdq 13 nc nc nc nc nc dq 12 ddq 14 v dd v ss v ss v ss v dd dq 11 edq 15 nc v dd v ss v dd nc dq 10 fdq 16 v dd v ss v ss v ss v dd dq 9 gdq 17 nc v dd v ss v dd nc dq 8 hdq 18 v dd v ss v ss v ss v dd dq 7 j v dd v ss v dd v ss v dd v ss v dd kdq 19 v dd v ss v ss v ss v dd dq 6 ldq 20 nc v dd v ss v dd nc dq 5 mdq 21 v dd v ss v ss v ss v dd dq 4 ndq 22 nc v dd v ss v dd nc dq 3 pdq 23 v dd v ss v ss v ss v dd dq 2 rdq 24 nc nc nc nc nc dq 1 tnca 11 a 10 we a 9 a 8 nc unca 15 a 14 oe a 13 a 12 nc gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 3/13 ? 2003, gsi technology 119-bump, 1.27 mm pitch bga pad out?top view (package b)
truth table ce oe we mode dq0 to dq23 v dd current h x x not selected high z isb1, isb2 l l h read data out i dd l x l write data in l h h output disable high z gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 4/13 ? 2003, gsi technology x: ?h? or ?l? absolute maximum ratings parameter symbol rating unit supply voltage v dd ?0.5 to +4.6 v input voltage v in ?0.5 to v dd +0.5 ( 4.6 v max.) v output voltage v out ?0.5 to v dd +0.5 ( 4.6 v max.) v allowable bga power dissipation pd 1.5 w storage temperature t stg ?55 to 150 o c note: permanent device damage may occur if absolute maximum ratings ar e exceeded. functional operation shall be restricted to recomme nded operating conditions. exposure to higher than recommended voltages for extended peri ods of time could affect device reliability .
recommended oper ating conditions parameter symbol min typ max unit supply voltage for -10/12 v dd 3.0 3.3 3.6 v supply voltage for -8 v dd 3.135 3.3 3.6 v input high voltage v ih 2.0 ? v dd +0.3 v input low voltage v il ?0.3 ? 0.8 v ambient temperature, commercial range t ac 0 ? 70 o c ambient temperature, industrial range t ai ?40 ? 85 o c gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 5/13 ? 2003, gsi technology notes: 1. input overshoot voltage should be less than v dd +2 v and not exceed 20 ns. 2. input undershoot voltage should be greater than ?2 v and not exceed 20 ns. capacitance parameter symbol test condition max unit input capacitance c in v in = 0 v 5 pf i/o capacitance c out v out = 0 v 7 pf notes: 1. tested at t a = 25c, f = 1 mhz 2. these parameters are sampled and are not 100% tested. dc i/o pin characteristics parameter symbol test conditions min max input leakage current i il v in = 0 to v dd ?1 ua 1 ua output leakage current i ol output high z, v out = 0 to v dd ?1 ua 1 ua output high voltage v oh i oh = ?4 ma 2.4 ? output low voltage v ol i ol = +4 ma ? 0.4 v
dq vt = 1.4 v 50 ? 30pf 1 dq 3.3 v output load 1 output load 2 589 ? 434 ? 5pf 1 notes: 1. includes scope and jig capacitance 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted 3. output load 2 for t lz , t hz , t olz and t ohz parameter conditions input high level v ih = 2.4 v input low level v il = 0.4 v input rise time t = 1 v/ns input fall time tf = 1 v/ns input reference level 1.4 v output reference level 1.4 v output load fig. 1& 2 gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 6/13 ? 2003, gsi technology ac test conditions power supply currents parameter symbol test conditions 0 to 70c ?40 to 85c 8 ns 10 ns 12 ns 8 ns 10 ns 12 ns operating supply current i dd ce v il all other inputs v ih or v il min. cycle time i out = 0 ma 250 ma 200 ma 170 ma 260 ma 210 ma 180 ma standby current i sb1 ce v ih all other inputs v ih or v il min. cycle time 40 ma 40 ma 30 ma 50 ma 50 ma 40 ma standby current i sb2 ce v dd - 0.2v all other inputs v dd - 0.2v or 0.2v 10 ma 20 ma
read cycle parameter symbol -8 -10 -12 unit min max min max min max read cycle time t rc 8 ? 10 ? 12 ? ns address access time t aa ? 8 ? 10 ? 12 ns chip enable access time ( ce ) t ac ? 8 ? 10 ? 12 ns mux control to output valid (v/ s ) t av ? 8 ? 10 ? 12 ns output enable to output valid ( oe ) t oe ? 4 ? 5 ? 6 ns output hold from address change t oh 3 ? 3 ? 3 ? ns output hold from mux controls change t oh1 3 ? 3 ? 3 ? ns chip enable to output in low z ( ce ) t lz * 3 ? 3 ? 3 ? ns output enable to output in low z ( oe ) t olz * 0 ? 0 ? 0 ? ns chip disable to output in high z ( ce ) t hz * ? 4 ? 5 ? 6 ns output disable to output in high z ( oe ) t ohz * ? 4 ? 5 ? 6 ns gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 7/13 ? 2003, gsi technology ac characteristics * these parameters are sampled and are not 100% tested t aa t oh t rc address data out previous data data valid read cycle 1: ce = oe = v il , we = v ih
t aa t rc address t ac t lz t oe t olz ce oe data out t hz t ohz data valid high impedance gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 8/13 ? 2003, gsi technology read cycle 2: we = v ih write cycle parameter symbol -8 -10 -12 unit min max min max min max write cycle time t wc 8 ? 10 ? 12 ? ns address valid to end of write t aw 5.5 ? 7 ? 8 ? ns chip enable to end of write ( ce ) t cw 5.5 ? 7 ? 8 ? ns data set up time t dw 4 ? 5 ? 6 ? ns data hold time t dh 0 ? 0 ? 0 ? ns write pulse width t wp 5.5 ? 7 ? 8 ? ns address set up time t as 0 ? 0 ? 0 ? ns write recovery time ( we ) t wr 0 ? 0 ? 0 ? ns write recovery time ( ce ) t wr1 0 ? 0 ? 0 ? ns output low z from end of write t wlz * 2 ? 3 ? 3 ? ns write to output in high z t whz * ? 4 ? 5 ? 6 ns * these parameters are sampled and are not 100% tested
t wc address ce we data in oe data out t aw t cw t as t wp t wr t dw t dh t wlz t whz data valid high impedance gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 9/13 ? 2003, gsi technology write cycle 1: we control t wc address ce we data in oe data out t aw t wp t as t cw t wr1 t dw t dh data valid high impedance write cycle 2: ce control
gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 10/13 ? 2003, gsi technology package dimensions?119-bump fp bga (package b, variation 1 ) (date code: yyww.31) 7 6 5 4 3 2 1 a1 bottom view 1.27 7.62 1.27 20.32 140.20 220.20 b a 0.20(4x) ?0.10 ?0.30 c c a b s s ?0.60~0.90 (119x) c seating plane 0.15 c 0.50~0.70 2.06.0.13 0.900.10 0.15 c a b c d e f g h j k l m n p r t u 0.560.05 s s a b c d e f g h j k l m n p r t u 0.70 ref 12.00 1 2 3 4 5 6 7 220.20 19.50 pin #1 corner ?1.00(3x) ref 30 typ.
gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 11/13 ? 2003, gsi technology package dimensions?119-bump fp bga (package b, variation 2 ) (date code: yyww.3h) a b c d e f g h j k l m n p r t u 1 2 3 4 5 6 7 7 6 5 4 3 2 1 a1 top view a1 bottom view 1.27 7.62 1.27 20.32 140.10 220.10 b a 0.20(4x) ?0.10 ?0.30 c c a b s s ?0.60~0.90 (119x) c seating plane 0.15 c 0.50~0.70 1.86.0.13 a b c d e f g h j k l m n p r t u s s
ordering information part number 1 package 2 access time temp. range status gs73024ab-8 119-bump bga 3 8 ns commercial mp gs73024ab-10 119-bump bga 3 10 ns commercial mp gs73024ab-12 119-bump bga 3 12 ns commercial mp gs73024ab-8i 119-bump bga 3 8 ns industrial mp gs73024ab-10i 119-bump bga 3 10 ns industrial mp gs73024ab-12i 119-bump bga 3 12 ns industrial mp gs73024agb-8 rohs-compliant 119-bump bga 3 8 ns commercial pq gs73024agb-10 rohs-compliant 119-bump bga 3 10 ns commercial pq gs73024agb-12 rohs-compliant 119-bump bga 3 12 ns commercial pq gs73024agb-8i rohs-compliant 119-bump bga 3 8 ns industrial pq gs73024agb-10i rohs-compliant 119-bump bga 3 10 ns industrial pq gs73024agb-12i rohs-compliant 119-bump bga 3 12 ns industrial pq notes: 1. customers requiring tape and reel should add the character ?t? to the end of the part number. for example: gs73024ab-12t. 2. all gsi technology packages are at least 5/6 rohs compliant. packages listed with the additional ?g? designator are 6/6 rohs compliant. 3. please see pages 9 and 10 for date code information fo r variation 1 and variation 2 of the 119-bump bga. gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 12/13 ? 2003, gsi technology
revision history rev. code: old; new types of changes format or content page/revisions/reason gs73024a_r1 ? creation of new datasheet gs73024a_r1; gs73024a_r1_01 content ? corrected pinout (balls c3, c5 , r2, r3, r5, r6 changed to nc) ? corrected pin description tabl e to reflect pinout corrections ? corrected truth table to reflect pinout corrections gs73024a_r1_01; gs73024a_r1_02 content/format ? updated format ? added variation informti on to package mechanical gs73024a_r1_02; gs73024a_r1_03 content ? added variation 2 119 bga to datasheet ? added date codes to mechanicals gs73024a_r1_03; gs73024a_r1_04 content ? added rohs-compliant package information ? added rohs-compliant disclaimers gs73024ab specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.04b 3/2007 13/13 ? 2003, gsi technology

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